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update
This commit is contained in:
pvvx
parent
34d3652711
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39f77eb92b
1844 changed files with 899433 additions and 7 deletions
23
project/inc/driver/adc_drv.h
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23
project/inc/driver/adc_drv.h
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@ -0,0 +1,23 @@
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/*
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* Simple ADC DRV (adc_drv.h)
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*
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* Created on: 19 июн. 2017 г.
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* Author: pvvx
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*/
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#ifndef _DRIVER_ADC_DRV_H_
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#define _DRIVER_ADC_DRV_H_
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#include "rtl8195a.h"
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#include "rtl8195a_adc.h"
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void ADCIrqInit(IRQ_FUN IrqFunc, u32 IrqData, u32 intr_enable); // intr_enable = bits: REG_ADC_INTR_EN - BIT_ADC_FIFO_RD_ERROR_EN | BIT_ADC_FIFO_RD_REQ_EN | BIT_ADC_FIFO_FULL_EN ...
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void ADCIrqDeInit(void);
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void ADCInit(ADC_MODULE_SEL adc_idx); // RTL8711AM: adc_idx = ADC2_SEL = 2
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void ADCDeInit(void);
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void ADCEnable(void); // ADC Start
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void ADCDisable(void); // ADC Stop
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#endif /* _DRIVER_ADC_DRV_H_ */
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@ -11,7 +11,8 @@
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#define WEB_DEBUG_FUNCTIONS 1 // =1 - включить в WEB отладочные функции, =0 отключить (остается только конфигурация WiFi)
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// #define WEB_INA219_DRV 1 (set in project.mk)
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// #define WEB_INA219_DRV 1 (set in project.mk !)
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// #define WEB_ADC_DRV 1 (set in project.mk !)
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#endif // _user_config_h_
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211
project/src/adc_ws/adc_ws.c
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211
project/src/adc_ws/adc_ws.c
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@ -0,0 +1,211 @@
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/*
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* ADC + Websocket
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*
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* Created on: 18 июн. 2017 г.
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* Author: pvvx
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*/
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#include <platform_opts.h>
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#include "rtl8195a.h"
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#include "device.h"
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#include "PinNames.h"
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#include "basic_types.h"
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#include "diag.h"
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#include "osdep_api.h"
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#include "FreeRTOS.h"
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#include "diag.h"
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//------------------------------------------------------------------------------
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#include "objects.h"
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#include "PinNames.h"
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#include "hal_adc.h"
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#include "analogin_api.h"
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#include "timer_api.h"
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//#include "strproc.h"
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#include "web_srv.h"
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#include "websock.h"
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#include "driver/adc_drv.h"
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#include "rtl8195a/rtl_libc.h"
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//------------------------------------------------------------------------------
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#define ADC_USE_TIMER TIMER3 // если назначено, то для чтения ADC используется таймер
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// иначе ADC int
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//------------------------------------------------------------------------------
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#ifndef CONFIG_MBED_ENABLED
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#define malloc pvPortMalloc
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#define zalloc pvPortZalloc
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#define free vPortFree
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#endif
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//------------------------------------------------------------------------------
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typedef union _adc_data {
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unsigned short us;
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} ADC_DATA, *PADC_DATA;
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typedef struct _adc_drv {
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signed char init; // флаг
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unsigned char tmp;
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unsigned short count; // счетчик считанных значений
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unsigned short overrun; // счет переполнений буфера
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unsigned short buf_idx; // объем буфера pbuf[buf_idx+1], максимальный индекс-номер замера
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unsigned short buf_rx; // индекс-номер ещё не считанного замера
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unsigned short buf_tx; // индекс-номер для записи следующего замера
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PADC_DATA pbuf;
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#ifdef ADC_USE_TIMER
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gtimer_t timer;
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#endif
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} ADC_DRV, *PADC_DRV;
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#define mMIN(a, b) ((a<b)?a:b)
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#define mMAX(a, b) ((a>b)?a:b)
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ADC_DRV adc_drv = {
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.buf_idx = (1460*2 - 80)/(sizeof(ADC_DATA)/2) // циклический буфер на ~1420 замеров (см. sizeof(ADC_DATA))
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// Если шаг заполнения 1 ms -> буфер на 1.4 сек
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// Оптимизация под TCP: (TCP_MSS*2 - 80)/2 = (1460*2 - 80)/2 = 1420
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};
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void adc_int_handler(void *par) {
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PADC_DRV p = par; // &adc_drv
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if(p->pbuf) {
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#ifndef ADC_USE_TIMER
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int i = 4;
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while(i--)
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#endif
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{
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PADC_DATA pd = p->pbuf + p->buf_tx;
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pd->us = HAL_ADC_READ32(REG_ADC_FIFO_READ); // 2 -> sample -> 24.4 kHz (if ADC irq!)
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// (void)HAL_ADC_READ32(REG_ADC_FIFO_READ); // 4 sample -> 12.2 kHz (if ADC irq!)
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// (void)HAL_ADC_READ32(REG_ADC_FIFO_READ); // 6 sample -> 8.133 kHz (if ADC irq!)
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// (void)HAL_ADC_READ32(REG_ADC_FIFO_READ); // 8 sample -> 6.1 kHz (if ADC irq!)
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if(p->buf_tx >= p->buf_idx) p->buf_tx = 0;
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else p->buf_tx++;
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if(p->buf_rx == p->buf_tx) {
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p->overrun++; // todo: if(p->overrun++ > 100000) deinit() ?
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if(p->buf_rx >= p->buf_idx) p->buf_rx = 0;
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else p->buf_rx++;
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};
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}
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/* Clear ADC Status */
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(void)HAL_ADC_READ32(REG_ADC_INTR_STS);
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};
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}
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size_t adc_getdata(void *pd, uint16 cnt)
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{
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PADC_DRV p = &adc_drv;
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if(p->init <= 0) return 0;
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unsigned short *pus = (unsigned short *) pd;
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taskDISABLE_INTERRUPTS();
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uint16 buf_rx = p->buf_rx;
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*pus++ = cnt; // кол-во замеров
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*pus++ = p->count + p->overrun; // индекс замера для анализа пропусков на стороне приемника
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// если не пропущено, то равен прошлому + кол-во считанных замеров в прошлом блоке
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p->count += cnt; // p->overrun = 0;
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unsigned char *puc = (unsigned char *) pus;
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if(cnt) {
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uint16 lend = buf_rx + cnt;
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if(lend > p->buf_idx) {
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lend -= p->buf_idx + 1;
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p->buf_rx = lend;
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} else {
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p->buf_rx = lend;
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lend = 0;
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};
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size_t len = (cnt - lend) *sizeof(ADC_DATA);
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if(len) memcpy(puc, (void *)(p->pbuf + buf_rx), len);
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if(lend) memcpy(puc + len, (void *)p->pbuf, lend *sizeof(ADC_DATA));
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}
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taskENABLE_INTERRUPTS();
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return cnt * sizeof(ADC_DATA) + 4;
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}
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uint16 adc_chkdata(uint16 cnt)
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{
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PADC_DRV p = &adc_drv;
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if(p->init <= 0) return 0;
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int len = p->buf_tx - p->buf_rx;
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if(len < 0) len += p->buf_idx + 1;
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if(cnt > (uint16)len) cnt = (uint16)len;
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return cnt;
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}
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int adc_ws(TCP_SERV_CONN *ts_conn, char cmd)
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{
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PADC_DRV p = &adc_drv;
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switch(cmd) {
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case 'd': // deinit
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if(p->init > 0) {
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#ifdef ADC_USE_TIMER
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gtimer_stop(&p->timer);
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gtimer_deinit(&p->timer);
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ADCDisable();
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#else
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ADCDisable();
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ADCIrqDeInit();
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#endif
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ADCDeInit();
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if(p->pbuf) {
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free(p->pbuf);
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p->pbuf = NULL;
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}
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p->init = -1;
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return 0;
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}
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return 1;
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case 'c': // get count
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return adc_chkdata(p->buf_idx + 1);
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case 'i': // init
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return p->init;
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default: // get_data
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if(p->init <= 0) {
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p->count = 0;
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p->overrun = 0;
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// p->errs = 0;
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if(!p->pbuf) {
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p->pbuf = zalloc((p->buf_idx + 1) * sizeof(ADC_DATA));
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if(!p->pbuf) {
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error_printf("Error create buffer!\n");
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return -1;
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};
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p->buf_tx = 0;
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p->buf_rx = 0;
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};
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ADCInit(ADC2_SEL);
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#ifdef ADC_USE_TIMER
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// Initial a periodical timer
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gtimer_init(&p->timer, ADC_USE_TIMER);
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gtimer_start_periodical(&p->timer, 1000, (void*)adc_int_handler, (uint32_t)p);
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rtl_printf("ADC Timer Period = %u us\n", &p->timer.hal_gtimer_adp.TimerLoadValueUs);
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#else
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ADCIrqInit(adc_int_handler,(uint32)p, BIT_ADC_FIFO_FULL_EN); // BIT_ADC_FIFO_RD_REQ_EN ?
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#endif
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ADCEnable();
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p->init = 1;
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// return 0;
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}
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case 'g': // get
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{
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uint32 i = adc_chkdata(p->buf_idx + 1);
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if(i) {
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WEB_SRV_CONN *web_conn = (WEB_SRV_CONN *)ts_conn->linkd;
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i = mMIN((web_conn->msgbufsize / sizeof(ADC_DATA)), i);
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if(websock_tx_frame(ts_conn, WS_OPCODE_BINARY | WS_FRAGMENT_FIN, web_conn->msgbuf, adc_getdata(web_conn->msgbuf, i)) != ERR_OK)
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return -1;
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}
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return i;
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}
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}
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return -1;
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}
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198
project/src/driver/adc_drv.c
Normal file
198
project/src/driver/adc_drv.c
Normal file
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@ -0,0 +1,198 @@
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/*
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* Simple ADC DRV (adc_drv.c)
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* Created on: 18 июн. 2017 г.
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* Author: pvvx
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*/
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#include <platform_opts.h>
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#include "platform_autoconf.h"
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#include "diag.h"
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#include "rtl8195a_adc.h"
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#include "hal_adc.h"
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#include "driver/adc_drv.h"
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//------------------------------------------------------------------------------
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void ADCIrqInit(IRQ_FUN IrqFunc, u32 IrqData, u32 intr_enable) {
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IRQ_HANDLE IrqHandle = {
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.IrqNum = ADC_IRQ,
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.Priority = 5
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};
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IrqHandle.Data = IrqData;
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IrqHandle.IrqFun = IrqFunc;
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InterruptRegister(&IrqHandle);
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InterruptEn(&IrqHandle);
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HAL_ADC_WRITE32(REG_ADC_INTR_EN, intr_enable);
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}
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void ADCIrqDeInit(void) {
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IRQ_HANDLE IrqHandle = {
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.IrqNum = ADC_IRQ,
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.Priority = 5,
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.Data = (u32)NULL,
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.IrqFun = (IRQ_FUN) NULL
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};
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HAL_ADC_WRITE32(REG_ADC_INTR_EN, 0);
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InterruptUnRegister(&IrqHandle);
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}
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void ADCEnable(void) {
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/* Clear ADC Status */
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(void)HAL_ADC_READ32(REG_ADC_INTR_STS);
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u32 AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
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AdcTempDat &= (~BIT_ADC_PWR_AUTO);
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AdcTempDat |= 0x02;
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HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
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AdcTempDat |= 0x04;
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HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
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AdcTempDat &= (~0x08);
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HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
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/* */
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0,
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HAL_ADC_READ32(REG_ADC_ANAPAR_AD0) | BIT_ADC_EN_MANUAL);
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1,
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HAL_ADC_READ32(REG_ADC_ANAPAR_AD1) | BIT_ADC_EN_MANUAL);
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}
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void ADCDisable(void) {
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#if ADC_USE_IRQ
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HAL_ADC_WRITE32(REG_ADC_INTR_EN, 0);
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#endif
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0,
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HAL_ADC_READ32(REG_ADC_ANAPAR_AD0) & (~BIT_ADC_EN_MANUAL));
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1,
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HAL_ADC_READ32(REG_ADC_ANAPAR_AD1) & (~BIT_ADC_EN_MANUAL));
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HAL_ADC_WRITE32(REG_ADC_POWER,
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HAL_ADC_READ32(REG_ADC_POWER)
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& (~(BIT_ADC_PWR_AUTO)));
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}
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#ifdef CONFIG_SOC_PS_MODULE
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static void ADCEnablePS(void)
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{
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REG_POWER_STATE adcPwrState;
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// To register a new peripheral device power state
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adcPwrState.FuncIdx = ADC0;
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adcPwrState.PwrState = ACT;
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RegPowerState(adcPwrState);
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}
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#endif
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void ADCInit(ADC_MODULE_SEL adc_idx) {
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/* ADC Function and Clock Enable */
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/* To release DAC delta sigma clock gating */
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HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2,
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HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2) | BIT25);
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/* Turn on DAC active clock */
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ACTCK_ADC_CCTRL(ON);
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/* Enable DAC0 module */
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ADC0_FCTRL(ON);
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/* Enable ADC power cut ? */
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// ADCEnablePW();
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/* ADC Control register set-up*/
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HAL_ADC_WRITE32(REG_ADC_CONTROL,
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BIT_CTRL_ADC_COMP_ONLY(ADC_FEATURE_DISABLED) // compare mode only enable (without FIFO enable)
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| BIT_CTRL_ADC_ONESHOT(ADC_FEATURE_DISABLED) // one-shot mode enable
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| BIT_CTRL_ADC_OVERWRITE(ADC_FEATURE_DISABLED) // overwrite mode enable
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| BIT_CTRL_ADC_ENDIAN(ADC_DATA_ENDIAN_LITTLE) // endian selection
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| BIT_CTRL_ADC_BURST_SIZE(8) // DMA operation threshold
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| BIT_CTRL_ADC_THRESHOLD(8) // one shot mode threshold
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| BIT_CTRL_ADC_DBG_SEL(ADC_DBG_SEL_DISABLE));
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#if 0
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/* ADC compare value and compare method setting*/
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switch (adc_idx) {
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case ADC0_SEL:
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HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L,
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(HAL_ADC_READ32(REG_ADC_COMP_VALUE_L)
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& (~(BIT_ADC_COMP_TH_0(0xFFFF))))
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| BIT_CTRL_ADC_COMP_TH_0(0) // ADC compare mode threshold
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);
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break;
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case ADC1_SEL:
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HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L,
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(HAL_ADC_READ32(REG_ADC_COMP_VALUE_L)
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& (~(BIT_ADC_COMP_TH_1(0xFFFF))))
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| BIT_CTRL_ADC_COMP_TH_1(0) // ADC compare mode threshold
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);
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break;
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case ADC2_SEL:
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HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H,
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(HAL_ADC_READ32(REG_ADC_COMP_VALUE_H)
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& (~(BIT_ADC_COMP_TH_2(0xFFFF))))
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| BIT_CTRL_ADC_COMP_TH_2(0) // ADC compare mode threshold
|
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);
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break;
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case ADC3_SEL:
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HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H,
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(HAL_ADC_READ32(REG_ADC_COMP_VALUE_H)
|
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& (~(BIT_ADC_COMP_TH_3(0xFFFF))))
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| BIT_CTRL_ADC_COMP_TH_3(0) // ADC compare mode threshold
|
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);
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break;
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}
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/* ADC compare mode setting */
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HAL_ADC_WRITE32(REG_ADC_COMP_SET,
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HAL_ADC_READ32(REG_ADC_COMP_SET)
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& (~(1 << adc_idx))); // compare mode control : less than the compare threshold
|
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#endif
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/* ADC audio mode set-up */
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/* ADC enable manually setting */
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0,
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HAL_ADC_READ32(REG_ADC_ANAPAR_AD0)
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// & (~(BIT_ADC_AUDIO_EN)))
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// & (~(BIT_ADC_EN_MANUAL))
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| BIT_ADC_AUDIO_EN // ADC audio mode enable
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| BIT_ADC_EN_MANUAL // ADC enable manually
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);
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/* ADC analog parameter 0 */
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0,
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(HAL_ADC_READ32(REG_ADC_ANAPAR_AD0)
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// & (~BIT14) //ADC Input is internal?
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| (BIT14))
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& (~(BIT3|BIT2)));
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/* ADC analog parameter 1 */
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1,
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(HAL_ADC_READ32(REG_ADC_ANAPAR_AD1) & (~BIT1)) | (BIT2|BIT0));
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/* ADC analog parameter 2 */
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD2, 0x67884400);
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/* ADC analog parameter 3 */
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD3, 0x77780039);
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/* ADC analog parameter 4 */
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD4, 0x0004d501);
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/* ADC analog parameter 5 */
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HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD5, 0x1E010800);
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#ifdef CONFIG_SOC_PS_MODULE
|
||||
ADCEnablePS();
|
||||
#endif
|
||||
}
|
||||
|
||||
void ADCDeInit(void) {
|
||||
#ifdef CONFIG_SOC_PS_MODULE
|
||||
REG_POWER_STATE adcPwrState;
|
||||
u8 HwState;
|
||||
adcPwrState.FuncIdx = ADC0;
|
||||
QueryRegPwrState(adcPwrState.FuncIdx, &(adcPwrState.PwrState), &HwState);
|
||||
// if the power state isn't ACT, then switch the power state back to ACT first
|
||||
if ((adcPwrState.PwrState != ACT) && (adcPwrState.PwrState != INACT)) {
|
||||
ADCEnablePS();
|
||||
QueryRegPwrState(adcPwrState.FuncIdx, &(adcPwrState.PwrState), &HwState);
|
||||
}
|
||||
if (adcPwrState.PwrState == ACT) {
|
||||
adcPwrState.PwrState = INACT;
|
||||
RegPowerState(adcPwrState);
|
||||
}
|
||||
#endif
|
||||
/* Turn on DAC active clock */
|
||||
ACTCK_ADC_CCTRL(OFF);
|
||||
/* Enable DAC1 module */
|
||||
ADC0_FCTRL(OFF);
|
||||
/* To release DAC delta sigma clock gating */
|
||||
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2,
|
||||
HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2) & (~(BIT25)));
|
||||
}
|
||||
|
||||
|
|
@ -450,6 +450,16 @@ extern int ina219_ws(TCP_SERV_CONN *ts_conn, char cmd);
|
|||
else tcp_puts("%d", x);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#ifdef WEB_ADC_DRV
|
||||
else ifcmp("adc") {
|
||||
if(CheckSCB(SCB_WEBSOC)) {
|
||||
extern int adc_ws(TCP_SERV_CONN *ts_conn, char cmd);
|
||||
int x = adc_ws(ts_conn, cstr[6]);
|
||||
if(x < 0) SetSCB(SCB_FCLOSE|SCB_DISCONNECT);
|
||||
else tcp_puts("%d", x);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
else ifcmp("cfg_") {
|
||||
cstr += 4;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue