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pvvx 2017-06-21 03:00:20 +03:00
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146
USDK/component/soc/realtek/8195a/fwlib/bitband_io.h Normal file
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#ifndef _BITBAND_IO_H_
#define _BITBAND_IO_H_
#include "hal_platform.h"
#include "hal_api.h"
#include "hal_gpio.h"
#include "rtl8195a_gpio.h"
#define BITBAND_SRAM_REF 0x10000000
#define BITBAND_SRAM_BASE 0x12000000
#define BITBAND_SRAM(a,b) (BITBAND_SRAM_BASE + (a-BITBAND_SRAM_REF)*32 + (b*4)) // Convert SRAM address
/*
* in hal_platform.h
#define BITBAND_REG_BASE 0x40001000
*/
/*
* in rtl8195a_gpio.h
*
#define BITBAND_PORTA_DR 0x00 // data register
#define BITBAND_PORTA_DDR 0x04 // data direction
#define BITBAND_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
#define BITBAND_PORTB_DR 0x0c // data register
#define BITBAND_PORTB_DDR 0x10 // data direction
#define BITBAND_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
#define BITBAND_PORTC_DR 0x18 // data register
#define BITBAND_PORTC_DDR 0x1c // data direction
#define BITBAND_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
#define BITBAND_EXT_PORTA 0x50 // GPIO IN read or OUT read back
#define BITBAND_EXT_PORTB 0x54 // GPIO IN read or OUT read back
#define BITBAND_EXT_PORTC 0x58 // GPIO IN read or OUT read back
*/
#define BITBAND_PERI_REF 0x40000000
#define BITBAND_PERI_BASE 0x42000000
#define BITBAND_PERI(a,b) (BITBAND_PERI_BASE + (a-BITBAND_PERI_REF)*32 + (b*4)) // Convert PERI address
#define ucBITBAND_PERI(a,b) *((volatile unsigned char *)BITBAND_PERI(a,b))
#define uiBITBAND_PERI(a,b) *((volatile unsigned int *)BITBAND_PERI(a,b))
#define BITBAND_A0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,0) //Port = 0, bit = 0, A0
#define BITBAND_A1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,1) //Port = 0, bit = 1, A1
#define BITBAND_A2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,0) //Port = 1, bit = 0, A2
#define BITBAND_A3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,1) //Port = 1, bit = 1, A3
#define BITBAND_A4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,2) //Port = 1, bit = 2, A4
#define BITBAND_A5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,3) //Port = 1, bit = 3, A5
#define BITBAND_A6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,4) //Port = 1, bit = 4, A6
#define BITBAND_A7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,5) //Port = 1, bit = 5, A7
#define BITBAND_B0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,6) //Port = 1, bit = 6, B0
#define BITBAND_B1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,7) //Port = 1, bit = 7, B1
#define BITBAND_B2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,8) //Port = 1, bit = 8, B2
#define BITBAND_B3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,2) //Port = 0, bit = 2, B3
#define BITBAND_B4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,3) //Port = 0, bit = 3, B4
#define BITBAND_B5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,9) //Port = 1, bit = 9, B5
#define BITBAND_B6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 0, bit = 4, B6
#define BITBAND_B7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,5) //Port = 0, bit = 5, B7
#define BITBAND_C0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,10) //Port = 1, bit = 10, C0
#define BITBAND_C1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,6) //Port = 0, bit = 6, C1
#define BITBAND_C2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,11) //Port = 1, bit = 11, C2
#define BITBAND_C3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,7) //Port = 0, bit = 7, C3
#define BITBAND_C4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,8) //Port = 0, bit = 8, C4
#define BITBAND_C5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,9) //Port = 0, bit = 9, C5
#define BITBAND_C6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,10) //Port = 0, bit = 10, C6
#define BITBAND_C7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,11) //Port = 0, bit = 11, C7
#define BITBAND_C8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,12) //Port = 0, bit = 12, C8
#define BITBAND_C9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,13) //Port = 0, bit = 13, C9
#define BITBAND_D0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,12) //Port = 1, bit = 12, D0
#define BITBAND_D1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,14) //Port = 0, bit = 14, D1
#define BITBAND_D2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,13) //Port = 1, bit = 13, D2
#define BITBAND_D3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,15) //Port = 0, bit = 15, D3
#define BITBAND_D4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,16) //Port = 0, bit = 16, D4
#define BITBAND_D5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,17) //Port = 0, bit = 17, D5
#define BITBAND_D6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,18) //Port = 0, bit = 18, D6
#define BITBAND_D7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,19) //Port = 0, bit = 19, D7
#define BITBAND_D8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,14) //Port = 1, bit = 14, D8
#define BITBAND_D9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,20) //Port = 0, bit = 20, D9
#define BITBAND_E0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, E0
#define BITBAND_E1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,21) //Port = 0, bit = 21, E1
#define BITBAND_E2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,22) //Port = 0, bit = 22, E2
#define BITBAND_E3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,23) //Port = 0, bit = 23, E3
#define BITBAND_E4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,16) //Port = 1, bit = 16, E4
#define BITBAND_E5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,24) //Port = 0, bit = 24, E5
#define BITBAND_E6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,25) //Port = 0, bit = 25, E6
#define BITBAND_E7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,26) //Port = 0, bit = 26, E7
#define BITBAND_E8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,27) //Port = 0, bit = 27, E8
#define BITBAND_E9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,17) //Port = 1, bit = 17, E9
#define BITBAND_E10 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,18) //Port = 1, bit = 17, E10
#define BITBAND_F0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,19) //Port = 1, bit = 19, F0
#define BITBAND_F1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,20) //Port = 1, bit = 20, F1
#define BITBAND_F2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,21) //Port = 1, bit = 21, F2
#define BITBAND_F3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,22) //Port = 1, bit = 22, F3
#define BITBAND_F4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,23) //Port = 1, bit = 23, F4
#define BITBAND_F5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,24) //Port = 1, bit = 24, F5
#define BITBAND_G0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,25) //Port = 1, bit = 25, G0
#define BITBAND_G1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,26) //Port = 1, bit = 26, G1
#define BITBAND_G2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,27) //Port = 1, bit = 27, G2
#define BITBAND_G3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,28) //Port = 0, bit = 28, G3
#define BITBAND_G4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,28) //Port = 1, bit = 28, G4
#define BITBAND_G5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,29) //Port = 1, bit = 29, G5
#define BITBAND_G6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,30) //Port = 1, bit = 30, G6
#define BITBAND_G7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,31) //Port = 1, bit = 31, G7
#define BITBAND_H0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,0) //Port = 2, bit = 0, H0
#define BITBAND_H1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,29) //Port = 0, bit = 29, H1
#define BITBAND_H2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,1) //Port = 2, bit = 1, H2
#define BITBAND_H3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,30) //Port = 0, bit = 30, H3
#define BITBAND_H4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,2) //Port = 2, bit = 2, H4
#define BITBAND_H5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,31) //Port = 0, bit = 31, H5
#define BITBAND_H6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,3) //Port = 2, bit = 3, H6
#define BITBAND_H7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 2, bit = 4, H7
#define BITBAND_I0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,5) //Port = 2, bit = 5, I0
#define BITBAND_I1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,6) //Port = 2, bit = 6, I1
#define BITBAND_I2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,7) //Port = 2, bit = 7, I2
#define BITBAND_I3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,8) //Port = 2, bit = 8, I3
#define BITBAND_I4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,9) //Port = 2, bit = 9, I4
#define BITBAND_I5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,10) //Port = 2, bit = 10, I5
#define BITBAND_I6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,11) //Port = 2, bit = 11, I6
#define BITBAND_I7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,12) //Port = 2, bit = 12, I7
#define BITBAND_J0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,13) //Port = 2, bit = 13, J0
#define BITBAND_J1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,14) //Port = 2, bit = 14, J1
#define BITBAND_J2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, J2
#define BITBAND_J3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,16) //Port = 2, bit = 16, J3
#define BITBAND_J4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,17) //Port = 2, bit = 17, J4
#define BITBAND_J5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,18) //Port = 2, bit = 18, J5
#define BITBAND_J6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,19) //Port = 2, bit = 19, J6
#define BITBAND_K0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,20) //Port = 2, bit = 20, K0
#define BITBAND_K1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,21) //Port = 2, bit = 21, K1
#define BITBAND_K2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,22) //Port = 2, bit = 22, K2
#define BITBAND_K3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,23) //Port = 2, bit = 23, K3
#define BITBAND_K4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,24) //Port = 2, bit = 24, K4
#define BITBAND_K5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,25) //Port = 2, bit = 25, K5
#define BITBAND_K6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,26) //Port = 2, bit = 26, K6
#endif // _BITBAND_IO_H_

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USDK/component/soc/realtek/8195a/fwlib/hal_adc.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_ADC_H_
#define _HAL_ADC_H_
#include "rtl8195a.h"
#include "rtl8195a_adc.h"
#include "hal_gdma.h"
//================ ADC Configuration =========================
#define ADC_INTR_OP_TYPE 1
#define ADC_DMA_OP_TYPE 1
// ADC SAL management macros
#define SAL_ADC_USER_CB_NUM (sizeof(SAL_ADC_USER_CB) / sizeof(PSAL_ADC_USERCB_ADPT))
// ADC used module.
// Please set the ADC module flag to 1 to enable the related
#define ADC0_USED 1
#define ADC1_USED 1
#define ADC2_USED 1
#define ADC3_USED 1
//================ Debug MSG Definition =======================
#define ADC_PREFIX "RTL8195A[adc]: "
#define ADC_PREFIX_LVL " [ADC_DBG]: "
typedef enum _ADC_DBG_LVL_ {
HAL_ADC_LVL = 0x01,
SAL_ADC_LVL = 0x02,
VERI_ADC_LVL = 0x04,
}ADC_DBG_LVL,*PADC_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG_ADC_HAL
#define DBG_8195A_ADC(...) do{ \
_DbgDump(ADC_PREFIX __VA_ARGS__);\
}while(0)
#define ADCDBGLVL 0xFF
#define DBG_8195A_ADC_LVL(LVL,...) do{\
if (LVL&ADCDBGLVL){\
_DbgDump(ADC_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_ADC_LOG_PERD 100
#define DBG_8195A_ADC(...)
#define DBG_8195A_ADC_LVL(...)
#endif
//================ ADC HAL Related Enumeration ==================
// ADC Module Selection
typedef enum _ADC_MODULE_SEL_ {
ADC0_SEL = 0x0,
ADC1_SEL = 0x1,
ADC2_SEL = 0x2,
ADC3_SEL = 0x3,
}ADC_MODULE_SEL,*PADC_MODULE_SEL;
// ADC module status
typedef enum _ADC_MODULE_STATUS_ {
ADC_DISABLE = 0x0,
ADC_ENABLE = 0x1,
}ADC_MODULE_STATUS, *PADC_MODULE_STATUS;
// ADC Data Endian
typedef enum _ADC_DATA_ENDIAN_ {
ADC_DATA_ENDIAN_LITTLE = 0x0,
ADC_DATA_ENDIAN_BIG = 0x1,
}ADC_DATA_ENDIAN,*PADC_DATA_ENDIAN;
// ADC Debug Select
typedef enum _ADC_DEBUG_SEL_ {
ADC_DBG_SEL_DISABLE = 0x0,
ADC_DBG_SEL_ENABLE = 0x1,
}ADC_DEBUG_SEL,*PADC_DEBUG_SEL;
typedef enum _ADC_COMPARE_SET_ {
ADC_COMP_SMALLER_THAN = 0x0,
ADC_COMP_GREATER_THAN = 0x1,
}ADC_COMPARE_SET, *PADC_COMPARE_SET;
// ADC feature status
typedef enum _ADC_FEATURE_STATUS_{
ADC_FEATURE_DISABLED = 0,
ADC_FEATURE_ENABLED = 1,
}ADC_FEATURE_STATUS,*PADC_FEATURE_STATUS;
// ADC operation type
typedef enum _ADC_OP_TYPE_ {
ADC_RDREG_TYPE = 0x0,
ADC_DMA_TYPE = 0x1,
ADC_INTR_TYPE = 0x2,
}ADC_OP_TYPE, *PADC_OP_TYPE;
// ADC device status
typedef enum _ADC_DEVICE_STATUS_ {
ADC_STS_UNINITIAL = 0x00,
ADC_STS_INITIALIZED = 0x01,
ADC_STS_IDLE = 0x02,
ADC_STS_TX_READY = 0x03,
ADC_STS_TX_ING = 0x04,
ADC_STS_RX_READY = 0x05,
ADC_STS_RX_ING = 0x06,
ADC_STS_ERROR = 0x07,
ADC_STS_FULL = 0x08,
}ADC_DEVICE_STATUS, *PADC_DEVICE_STATUS;
// ADC error type
typedef enum _ADC_ERR_TYPE_ {
ADC_ERR_FIFO_RD_ERROR = 0x40, //ADC FIFO read error
}ADC_ERR_TYPE, *PADC_ERR_TYPE;
// ADC initial status
typedef enum _ADC_INITAIL_STATUS_ {
ADC0_INITED = 0x1,
ADC1_INITED = 0x2,
ADC2_INITED = 0x4,
ADC3_INITED = 0x8,
}ADC_INITAIL_STATUS, *PADC_INITAIL_STATUS;
//================ ADC HAL Data Structure ======================
// ADC HAL initial data structure
typedef struct _HAL_ADC_INIT_DAT_ {
u8 ADCIdx; //ADC index used
u8 ADCEn; //ADC module enable
u8 ADCEndian; //ADC endian selection,
//but actually it's for 32-bit ADC data swap control
//1'b0: no swap,
//1'b1: swap the upper 16-bit and the lower 16-bit
u8 ADCBurstSz; //ADC DMA operation threshold
u8 ADCCompOnly; //ADC compare mode only enable (without FIFO enable)
u8 ADCOneShotEn; //ADC one-shot mode enable
u8 ADCOverWREn; //ADC overwrite mode enable
u8 ADCOneShotTD; //ADC one shot mode threshold
u16 ADCCompCtrl; //ADC compare mode control,
//1'b0:less than the compare threshold
//1'b1:greater than the compare threshod
u16 ADCCompTD; //ADC compare mode threshold
u8 ADCDataRate; //ADC down sample data rate,
u8 ADCAudioEn; //ADC audio mode enable
u8 ADCEnManul; //ADC enable manually
u8 ADCDbgSel;
u32 RSVD0;
u32 *ADCData; //ADC data pointer
u32 ADCPWCtrl; //ADC0 power control
u32 ADCIntrMSK; //ADC Interrupt Mask
u32 ADCAnaParAd3; //ADC analog parameter 3
u32 ADCInInput; //ADC Input is internal?
}HAL_ADC_INIT_DAT,*PHAL_ADC_INIT_DAT;
// ADC HAL Operations
typedef struct _HAL_ADC_OP_ {
RTK_STATUS (*HalADCInit) (VOID *Data); //HAL ADC initialization
RTK_STATUS (*HalADCDeInit) (VOID *Data); //HAL ADC de-initialization
RTK_STATUS (*HalADCEnable) (VOID *Data); //HAL ADC de-initialization
u32 (*HalADCReceive) (VOID *Data); //HAL ADC receive
RTK_STATUS (*HalADCIntrCtrl) (VOID *Data); //HAL ADC interrupt control
u32 (*HalADCReadReg) (VOID *Data, u8 ADCReg);//HAL ADC read register
}HAL_ADC_OP, *PHAL_ADC_OP;
// ADC user callback adapter
typedef struct _SAL_ADC_USERCB_ADPT_ {
VOID (*USERCB) (VOID *Data);
u32 USERData;
}SAL_ADC_USERCB_ADPT, *PSAL_ADC_USERCB_ADPT;
// ADC user callback structure
typedef struct _SAL_ADC_USER_CB_ {
PSAL_ADC_USERCB_ADPT pTXCB; //ADC Transmit Callback
PSAL_ADC_USERCB_ADPT pTXCCB; //ADC Transmit Complete Callback
PSAL_ADC_USERCB_ADPT pRXCB; //ADC Receive Callback
PSAL_ADC_USERCB_ADPT pRXCCB; //ADC Receive Complete Callback
PSAL_ADC_USERCB_ADPT pRDREQCB; //ADC Read Request Callback
PSAL_ADC_USERCB_ADPT pERRCB; //ADC Error Callback
PSAL_ADC_USERCB_ADPT pDMATXCB; //ADC DMA Transmit Callback
PSAL_ADC_USERCB_ADPT pDMATXCCB; //ADC DMA Transmit Complete Callback
PSAL_ADC_USERCB_ADPT pDMARXCB; //ADC DMA Receive Callback
PSAL_ADC_USERCB_ADPT pDMARXCCB; //ADC DMA Receive Complete Callback
}SAL_ADC_USER_CB, *PSAL_ADC_USER_CB;
// ADC Transmit Buffer
typedef struct _SAL_ADC_TRANSFER_BUF_ {
u32 DataLen; //ADC Transmfer Length
u32 *pDataBuf; //ADC Transfer Buffer Pointer
u32 RSVD; //
}SAL_ADC_TRANSFER_BUF,*PSAL_ADC_TRANSFER_BUF;
typedef struct _SAL_ADC_DMA_USER_DEF_ {
u8 TxDatSrcWdth;
u8 TxDatDstWdth;
u8 TxDatSrcBstSz;
u8 TxDatDstBstSz;
u8 TxChNo;
u8 LlpCtrl;
u16 RSVD0;
u32 MaxMultiBlk;
u32 pLlix;
u32 pBlockSizeList;
}SAL_ADC_DMA_USER_DEF, *PSAL_ADC_DMA_USER_DEF;
// Software API Level ADC Handler
typedef struct _SAL_ADC_HND_ {
u8 DevNum; //ADC device number
u8 PinMux; //ADC pin mux seletion
u8 OpType; //ADC operation type selection
volatile u8 DevSts; //ADC device status
u32 ADCExd; //ADC extended options:
//bit 0: example
//bit 31~bit 1: Reserved
u32 ErrType; //
u32 TimeOut; //ADC IO Timeout count
PHAL_ADC_INIT_DAT pInitDat; //Pointer to ADC initial data struct
PSAL_ADC_TRANSFER_BUF pRXBuf; //Pointer to ADC TX buffer
PSAL_ADC_USER_CB pUserCB; //Pointer to ADC User Callback
}SAL_ADC_HND, *PSAL_ADC_HND;
// ADC SAL handle private
typedef struct _SAL_ADC_HND_PRIV_ {
VOID **ppSalADCHnd; //Pointer to SAL_ADC_HND pointer
SAL_ADC_HND SalADCHndPriv; //Private SAL_ADC_HND
}SAL_ADC_HND_PRIV, *PSAL_ADC_HND_PRIV;
//ADC SAL management adapter
typedef struct _SAL_ADC_MNGT_ADPT_ {
PSAL_ADC_HND_PRIV pSalHndPriv; //Pointer to SAL_ADC_HND
PHAL_ADC_INIT_DAT pHalInitDat; //Pointer to HAL ADC initial data( HAL_ADC_INIT_DAT )
PHAL_ADC_OP pHalOp; //Pointer to HAL ADC operation( HAL_ADC_OP )
VOID (*pHalOpInit)(VOID*);//Pointer to HAL ADC initialize function
PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
VOID (*pSalIrqFunc)(VOID*); //Used for SAL ADC interrupt function
PSAL_ADC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config
PHAL_GDMA_ADAPTER pHalGdmaAdp;
PHAL_GDMA_OP pHalGdmaOp;
PIRQ_HANDLE pIrqGdmaHnd;
VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function
PSAL_ADC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_ADC_USER_CB )
VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function
}SAL_ADC_MNGT_ADPT, *PSAL_ADC_MNGT_ADPT;
//================ ADC HAL Function Prototype ===================
// ADC HAL inline function
// For checking I2C input index valid or not
static inline RTK_STATUS
RtkADCIdxChk(
IN u8 ADCIdx
)
{
#if !ADC0_USED
if (ADCIdx == ADC0_SEL)
return _EXIT_FAILURE;
#endif
#if !ADC1_USED
if (ADCIdx == ADC1_SEL)
return _EXIT_FAILURE;
#endif
#if !ADC2_USED
if (ADCIdx == ADC2_SEL)
return _EXIT_FAILURE;
#endif
#if !ADC3_USED
if (ADCIdx == ADC3_SEL)
return _EXIT_FAILURE;
#endif
ADCIdx++; //for compile warning.
return _EXIT_SUCCESS;
}
VOID HalADCOpInit(IN VOID *Data);
PSAL_ADC_HND RtkADCGetSalHnd(IN u8 DACIdx);
RTK_STATUS RtkADCFreeSalHnd(IN PSAL_ADC_HND pSalADCHND);
RTK_STATUS RtkADCLoadDefault(IN VOID *Data);
RTK_STATUS RtkADCInit(IN VOID *Data);
RTK_STATUS RtkADCDeInit(IN VOID *Data);
//RTK_STATUS RtkADCReceive(IN VOID *Data);
u32 RtkADCReceive(IN VOID *Data);
u32 RtkADCReceiveBuf(IN VOID *Data,IN u32 *pBuf);
u32 RtkADCRxManualRotate(IN VOID *Data,IN u32 *pBuf);
PSAL_ADC_MNGT_ADPT RtkADCGetMngtAdpt(IN u8 ADCIdx);
RTK_STATUS RtkADCFreeMngtAdpt(IN PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt);
VOID ADCISRHandle(IN VOID *Data);
VOID ADCGDMAISRHandle(IN VOID *Data);
HAL_Status RtkADCDisablePS(IN VOID *Data);
HAL_Status RtkADCEnablePS(IN VOID *Data);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_API_H_
#define _HAL_API_H_
#include "basic_types.h"
#include "hal_irqn.h"
#define HAL_READ32(base, addr) \
rtk_le32_to_cpu(*((volatile u32*)(base + addr)))
#define HAL_WRITE32(base, addr, value32) \
((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32))
#define HAL_READ16(base, addr) \
rtk_le16_to_cpu(*((volatile u16*)(base + addr)))
#define HAL_WRITE16(base, addr, value) \
((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value))
#define HAL_READ8(base, addr) \
(*((volatile u8*)(base + addr)))
#define HAL_WRITE8(base, addr, value) \
((*((volatile u8*)(base + addr))) = value)
#if 0
// These "extern _LONG_CALL_" function declaration are for RAM code building only
// For ROM code building, thses code should be marked off
extern _LONG_CALL_ u8
HalPinCtrlRtl8195A(
IN u32 Function,
IN u32 PinLocation,
IN BOOL Operation
);
extern _LONG_CALL_ VOID
HalSerialPutcRtl8195a(
IN u8 c
);
extern _LONG_CALL_ u8
HalSerialGetcRtl8195a(
IN BOOL PullMode
);
extern _LONG_CALL_ u32
HalSerialGetIsrEnRegRtl8195a(VOID);
extern _LONG_CALL_ VOID
HalSerialSetIrqEnRegRtl8195a (
IN u32 SetValue
);
extern _LONG_CALL_ VOID
VectorTableInitForOSRtl8195A(
IN VOID *PortSVC,
IN VOID *PortPendSVH,
IN VOID *PortSysTick
);
extern _LONG_CALL_ BOOL
VectorIrqRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ BOOL
VectorIrqUnRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ VOID
VectorIrqEnRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ VOID
VectorIrqDisRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
#endif
extern BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
extern VOID InitWDGIRQ(VOID);
#define PinCtrl HalPinCtrlRtl8195A
#define DiagPutChar HalSerialPutcRtl8195a
#define DiagGetChar HalSerialGetcRtl8195a
#define DiagGetIsrEnReg HalSerialGetIsrEnRegRtl8195a
#define DiagSetIsrEnReg HalSerialSetIrqEnRegRtl8195a
#define InterruptForOSInit VectorTableInitForOSRtl8195A
#define InterruptRegister VectorIrqRegisterRtl8195A
#define InterruptUnRegister VectorIrqUnRegisterRtl8195A
#define InterruptEn VectorIrqEnRtl8195A
#define InterruptDis VectorIrqDisRtl8195A
#define SpicFlashInit SpicFlashInitRtl8195A
#define Calibration32k En32KCalibration
#define WDGInit InitWDGIRQ
typedef enum _HAL_Status
{
HAL_OK = 0x00,
HAL_BUSY = 0x01,
HAL_TIMEOUT = 0x02,
HAL_ERR_PARA = 0x03, // error with invaild parameters
HAL_ERR_MEM = 0x04, // error with memory allocation failed
HAL_ERR_HW = 0x05, // error with hardware error
HAL_ERR_UNKNOWN = 0xee // unknown error
} HAL_Status;
#endif //_HAL_API_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_COMMON_H_
#define _HAL_COMMON_H_
//================= Function Prototype START ===================
HAL_Status HalCommonInit(void);
//================= Function Prototype END ===================
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef __HAL_CRYPTO_H__
#define __HAL_CRYPTO_H__
#include "hal_api.h"
#include "basic_types.h"
#define CRYPTO_MAX_MSG_LENGTH 16000
#define CRYPTO_MD5_DIGEST_LENGTH 16
#define CRYPTO_SHA1_DIGEST_LENGTH 20
#define CRYPTO_SHA2_DIGEST_LENGTH 32
typedef enum _SHA2_TYPE_ {
SHA2_NONE = 0,
SHA2_224 = 224/8,
SHA2_256 = 256/8,
SHA2_384 = 384/8,
SHA2_512 = 512/8
} SHA2_TYPE;
#define _ERRNO_CRYPTO_DESC_NUM_SET_OutRange -2
#define _ERRNO_CRYPTO_BURST_NUM_SET_OutRange -3
#define _ERRNO_CRYPTO_NULL_POINTER -4
#define _ERRNO_CRYPTO_ENGINE_NOT_INIT -5
#define _ERRNO_CRYPTO_ADDR_NOT_4Byte_Aligned -6
#define _ERRNO_CRYPTO_KEY_OutRange -7
#define _ERRNO_CRYPTO_MSG_OutRange -8
#define _ERRNO_CRYPTO_IV_OutRange -9
#define _ERRNO_CRYPTO_AUTH_TYPE_NOT_MATCH -10
#define _ERRNO_CRYPTO_CIPHER_TYPE_NOT_MATCH -11
#define _ERRNO_CRYPTO_KEY_IV_LEN_DIFF -12
#define _ERRNO_CRYPTO_AES_MSGLEN_NOT_16Byte_Aligned -13
//
// External API Functions
//
// Crypto Engine
extern int rtl_cryptoEngine_init(void);
extern void rtl_cryptoEngine_info(void);
//
// Authentication
//
// md5
extern int rtl_crypto_md5(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
extern int rtl_crypto_md5_init(void);
extern int rtl_crypto_md5_process(IN const u8* message, const IN u32 msglen, OUT u8* pDigest);
// sha1
extern int rtl_crypto_sha1(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
extern int rtl_crypto_sha1_init(void);
extern int rtl_crypto_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// sha2
extern int rtl_crypto_sha2(IN const SHA2_TYPE sha2type,
IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
extern int rtl_crypto_sha2_init(IN const SHA2_TYPE sha2type);
extern int rtl_crypto_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// HMAC-md5
extern int rtl_crypto_hmac_md5(IN const u8* message, IN const u32 msglen,
IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
extern int rtl_crypto_hmac_md5_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_hmac_md5_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// HMAC-sha1
extern int rtl_crypto_hmac_sha1(IN const u8* message, IN const u32 msglen,
IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
extern int rtl_crypto_hmac_sha1_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_hmac_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// HMAC-sha2
extern int rtl_crypto_hmac_sha2(IN const SHA2_TYPE sha2type, IN const u8* message, IN const u32 msglen,
IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
extern int rtl_crypto_hmac_sha2_init(IN const SHA2_TYPE sha2type, IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_hmac_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
//
// Cipher Functions
//
// AES - CBC
extern int rtl_crypto_aes_cbc_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_aes_cbc_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_aes_cbc_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// AES - ECB
extern int rtl_crypto_aes_ecb_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_aes_ecb_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_aes_ecb_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// AES - CTR
extern int rtl_crypto_aes_ctr_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_aes_ctr_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_aes_ctr_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// 3DES - CBC
extern int rtl_crypto_3des_cbc_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_3des_cbc_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_3des_cbc_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// 3DES - ECB
extern int rtl_crypto_3des_ecb_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_3des_ecb_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_3des_ecb_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// DES - CBC
extern int rtl_crypto_des_cbc_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_des_cbc_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_des_cbc_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// DES - ECB
extern int rtl_crypto_des_ecb_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_des_ecb_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_des_ecb_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
//
// C functions in ROM
//
extern int rtl_memcmpb(const u8 *dst, const u8 *src, int bytes);
extern int rtl_memcpyb(u8 *dst, const u8 *src, int bytes);
#endif /* __HAL_CRYPTO_H__ */

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//======================================================
// Routines to access hardware
//
// Copyright (c) 2013 Realtek Semiconductor Corp.
//
// This module is a confidential and proprietary property of RealTek and
// possession or use of this module requires written permission of RealTek.
//======================================================
#ifndef _HAL_DAC_H_
#define _HAL_DAC_H_
#include "rtl8195a.h"
#include "rtl8195a_dac.h"
#include "hal_api.h"
#include "hal_gdma.h"
//================ DAC Configuration =========================
#define DAC_INTR_OP_TYPE 1
#define DAC_DMA_OP_TYPE 1
// DAC SAL management macros
#define SAL_DAC_USER_CB_NUM (sizeof(SAL_DAC_USER_CB) / sizeof(PSAL_DAC_USERCB_ADPT))
// DAC SAL used module.
// Please set the DAC module flag to 1 to enable the related DAC module functions.
#define DAC0_USED 1
#define DAC1_USED 1
//================ Debug MSG Definition =======================
#define DAC_PREFIX "RTL8195A[dac]: "
#define DAC_PREFIX_LVL " [DAC_DBG]: "
typedef enum _DAC_DBG_LVL_ {
HAL_DAC_LVL = 0x00,
SAL_DAC_LVL = 0x02,
VERI_DAC_LVL = 0x04,
}DAC_DBG_LVL,*PDAC_DBG_LVL;
#if CONFIG_DEBUG_LOG > 0
#ifdef CONFIG_DEBUG_LOG_DAC_HAL
#define DBG_8195A_DAC(...) do{ \
_DbgDump(DAC_PREFIX __VA_ARGS__);\
}while(0)
#define DACDBGLVL 0xFF
#define DBG_8195A_DAC_LVL(LVL,...) do{\
if (LVL&DACDBGLVL){\
_DbgDump(DAC_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_DAC_LOG_PERD 100
#define DBG_8195A_DAC(...)
#define DBG_8195A_DAC_LVL(...)
#endif
#endif
//================ DAC HAL Related Enumeration ==================
// DAC Module Selection
typedef enum _DAC_MODULE_SEL_ {
DAC0_SEL = 0x0,
DAC1_SEL = 0x1,
}DAC_MODULE_SEL,*PDAC_MODULE_SEL;
// DAC module status
typedef enum _DAC_MODULE_STATUS_ {
DAC_DISABLE = 0x0,
DAC_ENABLE = 0x1,
}DAC_MODULE_STATUS, *PDAC_MODULE_STATUS;
// DAC Data Rate
typedef enum _DAC_DATA_RATE_ {
DAC_DATA_RATE_10K = 0x0,
DAC_DATA_RATE_250K = 0x1,
}DAC_DATA_RATE,*PDAC_DATA_RATE;
// DAC Data Endian
typedef enum _DAC_DATA_ENDIAN_ {
DAC_DATA_ENDIAN_LITTLE = 0x0,
DAC_DATA_ENDIAN_BIG = 0x1,
}DAC_DATA_ENDIAN,*PDAC_DATA_ENDIAN;
// DAC Debug Select
typedef enum _DAC_DEBUG_SEL_ {
DAC_DBG_SEL_DISABLE = 0x0,
DAC_DBG_SEL_ENABLE = 0x1,
}DAC_DEBUG_SEL,*PDAC_DEBUG_SEL;
// DAC Dsc Debug Select
typedef enum _DAC_DSC_DEBUG_SEL_ {
DAC_DSC_DBG_SEL_DISABLE = 0x0,
DAC_DSC_DBG_SEL_ENABLE = 0x1,
}DAC_DSC_DEBUG_SEL,*PDAC_DSC_DEBUG_SEL;
// DAC Bypass Dsc Debug Select
typedef enum _DAC_BYPASS_DSC_SEL_ {
DAC_BYPASS_DSC_SEL_DISABLE = 0x0,
DAC_BYPASS_DSC_SEL_ENABLE = 0x1,
}DAC_BYPASS_DSC_SEL,*PDAC_BYPASS_DSC_SEL;
// DAC feature status
typedef enum _DAC_FEATURE_STATUS_{
DAC_FEATURE_DISABLED = 0,
DAC_FEATURE_ENABLED = 1,
}DAC_FEATURE_STATUS,*PDAC_FEATURE_STATUS;
// DAC operation type
typedef enum _DAC_OP_TYPE_ {
DAC_POLL_TYPE = 0x0,
DAC_DMA_TYPE = 0x1,
DAC_INTR_TYPE = 0x2,
}DAC_OP_TYPE, *PDAC_OP_TYPE;
// DAC device status
typedef enum _DAC_Device_STATUS_ {
DAC_STS_UNINITIAL = 0x00,
DAC_STS_INITIALIZED = 0x01,
DAC_STS_IDLE = 0x02,
DAC_STS_TX_READY = 0x03,
DAC_STS_TX_ING = 0x04,
DAC_STS_RX_READY = 0x05,
DAC_STS_RX_ING = 0x06,
DAC_STS_ERROR = 0x07,
}DAC_Device_STATUS, *PDAC_Device_STATUS;
//DAC device error type
typedef enum _DAC_ERR_TYPE_ {
DAC_ERR_FIFO_OVER = 0x04, //DAC FIFO overflow.
DAC_ERR_FIFO_STOP = 0x08, //DAC FIFO is completely empty, and it will be stopped automatically.
DAC_ERR_FIFO_WRFAIL = 0x10, //When DAC is NOT enabled, a write operation attempts to access DAC register.
DAC_ERR_FIFO_DSC_OVER0 = 0x20,
DAC_ERR_FIFO_DSC_OVER1 = 0x40,
}DAC_ERR_TYPE, *PDAC_ERR_TYPE;
// DAC data input method
typedef enum _DAC_INPUT_TYPE_{
DAC_INPUT_SINGLE_WR = 0x1, //DAC input by using single register write
DAC_INPUT_DMA_ONEBLK = 0x2, //DAC input by using single DMA block
DAC_INPUT_DMA_LLP = 0x3, //DAC input by using DMA linked list mode
}DAC_INPUT_TYPE,*PDAC_INPUT_TYPE;
//======================================================
// DAC HAL initial data structure
typedef struct _HAL_DAC_INIT_DAT_ {
u8 DACIdx; //DAC index used
u8 DACEn; //DAC module enable
u8 DACDataRate; //DAC data rate, 1'b0:10KHz, 1'b1:250KHz
u8 DACEndian; //DAC endian selection,
//but actually it's for 32-bit DAC data swap control
//1'b0: no swap,
//1'b1: swap the upper 16-bit and the lower 16-bit
u8 DACFilterSet; //DAC filter settle
u8 DACBurstSz; //DAC burst size
u8 DACDbgSel; //DAC debug sel
u8 DACDscDbgSel; //DAC debug dsc sel
u8 DACBPDsc; //DAC bypass delta sigma for loopback
u8 DACDeltaSig; //DAC bypass value of delta sigma
u16 RSVD1;
u32 *DACData; //DAC data pointer
u32 DACPWCtrl; //DAC0 and DAC1 power control
u32 DACAnaCtrl0; //DAC anapar_da control 0
u32 DACAnaCtrl1; //DAC anapar_da control 1
u32 DACIntrMSK; //DAC Interrupt Mask
}HAL_DAC_INIT_DAT,*PHAL_DAC_INIT_DAT;
// DAC HAL Operations
typedef struct _HAL_DAC_OP_ {
RTK_STATUS (*HalDACInit) (VOID *Data); //HAL DAC initialization
RTK_STATUS (*HalDACDeInit) (VOID *Data); //HAL DAC de-initialization
RTK_STATUS (*HalDACEnable) (VOID *Data); //HAL DAC de-initialization
u8 (*HalDACSend) (VOID *Data); //HAL DAC receive
RTK_STATUS (*HalDACIntrCtrl) (VOID *Data); //HAL DAC interrupt control
u32 (*HalDACReadReg) (VOID *Data, u8 DACReg);//HAL DAC read register
}HAL_DAC_OP, *PHAL_DAC_OP;
// DAC user callback adapter
typedef struct _SAL_DAC_USERCB_ADPT_ {
VOID (*USERCB) (VOID *Data);
u32 USERData;
}SAL_DAC_USERCB_ADPT, *PSAL_DAC_USERCB_ADPT;
// DAC user callback structure
typedef struct _SAL_DAC_USER_CB_ {
PSAL_DAC_USERCB_ADPT pTXCB; //DAC Transmit Callback
PSAL_DAC_USERCB_ADPT pTXCCB; //DAC Transmit Complete Callback
PSAL_DAC_USERCB_ADPT pRXCB; //DAC Receive Callback
PSAL_DAC_USERCB_ADPT pRXCCB; //DAC Receive Complete Callback
PSAL_DAC_USERCB_ADPT pRDREQCB; //DAC Read Request Callback
PSAL_DAC_USERCB_ADPT pERRCB; //DAC Error Callback
PSAL_DAC_USERCB_ADPT pDMATXCB; //DAC DMA Transmit Callback
PSAL_DAC_USERCB_ADPT pDMATXCCB; //DAC DMA Transmit Complete Callback
PSAL_DAC_USERCB_ADPT pDMARXCB; //DAC DMA Receive Callback
PSAL_DAC_USERCB_ADPT pDMARXCCB; //DAC DMA Receive Complete Callback
}SAL_DAC_USER_CB, *PSAL_DAC_USER_CB;
// DAC Transmit Buffer
typedef struct _SAL_DAC_TRANSFER_BUF_ {
u32 DataLen; //DAC Transmfer Length
u32 *pDataBuf; //DAC Transfer Buffer Pointer
u32 RSVD; //
}SAL_DAC_TRANSFER_BUF,*PSAL_DAC_TRANSFER_BUF;
typedef struct _SAL_DAC_DMA_USER_DEF_ {
u8 TxDatSrcWdth;
u8 TxDatDstWdth;
u8 TxDatSrcBstSz;
u8 TxDatDstBstSz;
u8 TxChNo;
u8 LlpCtrl;
u16 RSVD0;
u32 MaxMultiBlk;
u32 pLlix;
u32 pBlockSizeList;
}SAL_DAC_DMA_USER_DEF, *PSAL_DAC_DMA_USER_DEF;
// Software API Level DAC Handler
typedef struct _SAL_DAC_HND_ {
u8 DevNum; //DAC device number
u8 PinMux; //DAC pin mux seletion
u8 OpType; //DAC operation type selection
volatile u8 DevSts; //DAC device status
u8 DACInType; //DAC input type
u8 RSVD0;
u16 RSVD1;
u32 DACExd; //DAC extended options:
//bit 0: example
//bit 31~bit 1: Reserved
u32 ErrType; //
u32 TimeOut; //DAC IO Timeout count
PHAL_DAC_INIT_DAT pInitDat; //Pointer to DAC initial data struct
PSAL_DAC_TRANSFER_BUF pTXBuf; //Pointer to DAC TX buffer
PSAL_DAC_USER_CB pUserCB; //Pointer to DAC User Callback
PSAL_DAC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA Config
}SAL_DAC_HND, *PSAL_DAC_HND;
// DAC SAL handle private
typedef struct _SAL_DAC_HND_PRIV_ {
VOID **ppSalDACHnd; //Pointer to SAL_DAC_HND pointer
SAL_DAC_HND SalDACHndPriv; //Private SAL_DAC_HND
}SAL_DAC_HND_PRIV, *PSAL_DAC_HND_PRIV;
//DAC SAL management adapter
typedef struct _SAL_DAC_MNGT_ADPT_ {
PSAL_DAC_HND_PRIV pSalHndPriv; //Pointer to SAL_DAC_HND
PHAL_DAC_INIT_DAT pHalInitDat; //Pointer to HAL DAC initial data( HAL_I2C_INIT_DAT )
PHAL_DAC_OP pHalOp; //Pointer to HAL DAC operation( HAL_DAC_OP )
VOID (*pHalOpInit)(VOID*); //Pointer to HAL DAC initialize function
PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
PSAL_DAC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_DAC_USER_CB )
VOID (*pSalIrqFunc)(VOID*); //Used for SAL DAC interrupt function
PSAL_DAC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config
PHAL_GDMA_ADAPTER pHalGdmaAdp;
PHAL_GDMA_OP pHalGdmaOp;
VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function
PIRQ_HANDLE pIrqGdmaHnd;
VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function
}SAL_DAC_MNGT_ADPT, *PSAL_DAC_MNGT_ADPT;
//================ DAC HAL Function Prototype ===================
// DAC HAL inline function
// For checking DAC input index valid or not
static inline RTK_STATUS
RtkDACIdxChk(
IN u8 DACIdx
)
{
#if !DAC0_USED
if (DACIdx == DAC0_SEL)
return _EXIT_FAILURE;
#endif
#if !DAC1_USED
if (DACIdx == DAC1_SEL)
return _EXIT_FAILURE;
#endif
return _EXIT_SUCCESS;
}
VOID HalDACOpInit(IN VOID *Data);
RTK_STATUS RtkDACLoadDefault(IN VOID *Data);
RTK_STATUS RtkDACInit(IN VOID *Data);
RTK_STATUS RtkDACDeInit(IN VOID *Data);
RTK_STATUS RtkDACSend(IN VOID *Data);
PSAL_DAC_HND RtkDACGetSalHnd(IN u8 DACIdx);
RTK_STATUS RtkDACFreeSalHnd(IN PSAL_DAC_HND pSalDACHND);
PSAL_DAC_MNGT_ADPT RtkDACGetMngtAdpt(IN u8 DACIdx);
RTK_STATUS RtkDACFreeMngtAdpt(IN PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_DIAG_H_
#define _HAL_DIAG_H_
//Register offset
#define UART_REV_BUF_OFF 0x00
#define UART_TRAN_HOLD_OFF 0x00
#define UART_DLH_OFF 0x04
#define UART_DLL_OFF 0x00
#define UART_INTERRUPT_EN_REG_OFF 0x04
#define UART_INTERRUPT_IDEN_REG_OFF 0x08
#define UART_FIFO_CTL_REG_OFF 0x08
#define UART_LINE_CTL_REG_OFF 0x0c
#define UART_MODEM_CTL_REG_OFF 0x10
#define UART_LINE_STATUS_REG_OFF 0x14
#define UART_MODEM_STATUS_REG_OFF 0x18
#define UART_FIFO_ACCESS_REG_OFF 0x70
#define UART_STATUS_REG_OFF 0x7c
#define UART_TFL_OFF 0x80
#define UART_RFL_OFF 0x84
//Buad rate
#define UART_BAUD_RATE_2400 2400
#define UART_BAUD_RATE_4800 4800
#define UART_BAUD_RATE_9600 9600
#define UART_BAUD_RATE_19200 19200
#define UART_BAUD_RATE_38400 38400
#define UART_BAUD_RATE_57600 57600
#define UART_BAUD_RATE_115200 115200
#define UART_BAUD_RATE_921600 921600
#define UART_BAUD_RATE_1152000 1152000
#define UART_PARITY_ENABLE 0x08
#define UART_PARITY_DISABLE 0
#define UART_DATA_LEN_5BIT 0x0
#define UART_DATA_LEN_6BIT 0x1
#define UART_DATA_LEN_7BIT 0x2
#define UART_DATA_LEN_8BIT 0x3
#define UART_STOP_1BIT 0x0
#define UART_STOP_2BIT 0x4
#ifndef DEFAULT_BAUDRATE
#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
#endif
#define HAL_UART_READ32(addr) HAL_READ32(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE32(addr, value) HAL_WRITE32(LOG_UART_REG_BASE, addr, value)
#define HAL_UART_READ16(addr) HAL_READ16(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE16(addr, value) HAL_WRITE16(LOG_UART_REG_BASE, addr, value)
#define HAL_UART_READ8(addr) HAL_READ8(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE8(addr, value) HAL_WRITE8(LOG_UART_REG_BASE, addr, value)
typedef struct _LOG_UART_ADAPTER_ {
u32 BaudRate;
u32 FIFOControl;
u32 IntEnReg;
u8 Parity;
u8 Stop;
u8 DataLength;
}LOG_UART_ADAPTER, *PLOG_UART_ADAPTER;
typedef struct _COMMAND_TABLE_ {
const u8* cmd;
u16 ArgvCnt;
u32 (*func)(u16 argc, u8* argv[]);
const u8* msg;
}COMMAND_TABLE, *PCOMMAND_TABLE;
//VOID
//HalLogUartHandle(void);
extern _LONG_CALL_ROM_ u32
HalLogUartInit(
IN LOG_UART_ADAPTER UartAdapter
);
extern _LONG_CALL_ROM_ VOID
HalSerialPutcRtl8195a(
IN u8 c
);
extern _LONG_CALL_ROM_ u8
HalSerialGetcRtl8195a(
IN BOOL PullMode
);
extern _LONG_CALL_ROM_ u32
HalSerialGetIsrEnRegRtl8195a(VOID);
extern _LONG_CALL_ROM_ VOID
HalSerialSetIrqEnRegRtl8195a (
IN u32 SetValue
);
#endif//_HAL_DIAG_H_

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/*
* Routines to access hardware
* hal_efuse.h
*/
#ifndef _HAL_EFUSE_H_
#define _HAL_EFUSE_H_
_LONG_CALL_ROM_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage);
_LONG_CALL_ROM_ extern u32 HALEFUSEOneByteReadROM(IN u32 CtrlSetting, IN u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage);
_LONG_CALL_ROM_ extern u32 HALEFUSEOneByteWriteROM(IN u32 CtrlSetting, IN u16 Addr, IN u8 Data, IN u8 L25OutVoltage);
int HALOTPOneByteReadRAM(IN unsigned int CtrlSetting, IN unsigned short Addr, OUT unsigned char *Data, IN unsigned char L25OutVoltage);
int HALOTPOneByteWriteRAM(IN unsigned int CtrlSetting, IN unsigned short Addr, IN unsigned char Data, IN unsigned char L25OutVoltage);
int HALEFUSEOneByteReadRAM(IN unsigned int CtrlSetting, IN unsigned short Addr, IN unsigned char *Data, IN unsigned char L25OutVoltage);
int HALEFUSEOneByteWriteRAM(IN unsigned int CtrlSetting, IN unsigned short Addr, IN unsigned char Data, IN unsigned char L25OutVoltage);
void ReadEfuseContant(IN unsigned char UserCode, OUT unsigned char *pContant);
void ReadEfuseContant1(OUT unsigned char *pContant);
void ReadEfuseContant2(OUT unsigned char *pContant);
void ReadEfuseContant3(OUT unsigned char *pContant);
int GetRemainingEfuseLength(void);
int WriteEfuseContant(IN unsigned char UserCode, IN unsigned char CodeWordNum, IN unsigned char WordEnable, unsigned char *pContant);
int WriteEfuseContant1(IN unsigned char CodeWordNum, IN unsigned char WordEnable, IN unsigned char *pContant);
int WriteEfuseContant2(IN unsigned char CodeWordNum, IN unsigned char WordEnable, IN unsigned char *pContant);
int WriteEfuseContant3(IN unsigned char CodeWordNum, IN unsigned char WordEnable, IN unsigned char *pContant);
void ReadEOTPContant(IN unsigned char *pContant);
void WriteEOTPContant(OUT unsigned char *pContant);
void HALJtagOff(void);
#define EFUSERead8 HALEFUSEOneByteReadRAM
#define EFUSEWrite8 HALEFUSEOneByteWriteRAM
#define L25EOUTVOLTAGE 7
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_GDMA_H_
#define _HAL_GDMA_H_
#include "rtl8195a_gdma.h"
typedef struct _GDMA_CH_LLI_ELE_ {
u32 Sarx;
u32 Darx;
u32 Llpx;
u32 CtlxLow;
u32 CtlxUp;
u32 Temp;
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
#if 1
#if 0
typedef struct _GDMA_CH_LLI_ {
PGDMA_CH_LLI_ELE pLliEle;
PGDMA_CH_LLI pNextLli;
}GDMA_CH_LLI, *PGDMA_CH_LLI;
typedef struct _BLOCK_SIZE_LIST_ {
u32 BlockSize;
PBLOCK_SIZE_LIST pNextBlockSiz;
}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
#else
struct GDMA_CH_LLI {
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pNextLli;
};
struct BLOCK_SIZE_LIST {
u32 BlockSize;
struct BLOCK_SIZE_LIST *pNextBlockSiz;
};
#endif
#endif
typedef struct _HAL_GDMA_ADAPTER_ {
u32 ChSar;
u32 ChDar;
GDMA_CHANNEL_NUM ChEn;
GDMA_CTL_REG GdmaCtl;
GDMA_CFG_REG GdmaCfg;
u32 PacketLen;
u32 BlockLen;
u32 MuliBlockCunt;
u32 MaxMuliBlock;
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
typedef struct _HAL_GDMA_CHNL_ {
u8 GdmaIndx;
u8 GdmaChnl;
u8 IrqNum;
u8 Reserved;
}HAL_GDMA_CHNL, *PHAL_GDMA_CHNL;
typedef struct _HAL_GDMA_BLOCK_ {
u32 SrcAddr;
u32 DstAddr;
u32 BlockLength;
u32 SrcOffset;
u32 DstOffset;
}HAL_GDMA_BLOCK, *PHAL_GDMA_BLOCK;
typedef struct _HAL_GDMA_OP_ {
VOID (*HalGdmaOnOff)(VOID *Data);
BOOL (*HalGdamChInit)(VOID *Data);
BOOL (*HalGdmaChSeting)(VOID *Data);
BOOL (*HalGdmaChBlockSeting)(VOID *Data);
VOID (*HalGdmaChDis)(VOID *Data);
VOID (*HalGdmaChEn)(VOID *Data);
VOID (*HalGdmaChIsrEnAndDis) (VOID *Data);
u8 (*HalGdmaChIsrClean)(VOID *Data);
VOID (*HalGdmaChCleanAutoSrc)(VOID *Data);
VOID (*HalGdmaChCleanAutoDst)(VOID *Data);
}HAL_GDMA_OP, *PHAL_GDMA_OP;
typedef struct _HAL_GDMA_OBJ_ {
HAL_GDMA_ADAPTER HalGdmaAdapter;
IRQ_HANDLE GdmaIrqHandle;
volatile GDMA_CH_LLI_ELE GdmaChLli[16];
struct GDMA_CH_LLI Lli[16];
struct BLOCK_SIZE_LIST BlockSizeList[16];
u8 Busy; // is transfering
u8 BlockNum;
} HAL_GDMA_OBJ, *PHAL_GDMA_OBJ;
VOID HalGdmaOpInit(IN VOID *Data);
VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
extern HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum);
extern VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum);
extern PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption);
extern VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl);
extern BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len);
extern VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock);
extern BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern const HAL_GDMA_OP _HalGdmaOp;
extern const HAL_GDMA_CHNL GDMA_Chnl_Option[];
extern const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[];
extern const u16 HalGdmaChnlEn[6];
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_GPIO_H_
#define _HAL_GPIO_H_
#define HAL_GPIO_PIN_INT_MODE 0x80
typedef enum {
_PORT_A = 0,
_PORT_B = 1,
_PORT_C = 2,
_PORT_D = 3,
_PORT_E = 4,
_PORT_F = 5,
_PORT_G = 6,
_PORT_H = 7,
_PORT_I = 8,
_PORT_J = 9,
_PORT_K = 10,
_PORT_MAX
} HAL_GPIO_PORT_NAME;
typedef enum {
_PA_0 = (_PORT_A<<4|0),
_PA_1 = (_PORT_A<<4|1),
_PA_2 = (_PORT_A<<4|2),
_PA_3 = (_PORT_A<<4|3),
_PA_4 = (_PORT_A<<4|4),
_PA_5 = (_PORT_A<<4|5),
_PA_6 = (_PORT_A<<4|6),
_PA_7 = (_PORT_A<<4|7),
_PB_0 = (_PORT_B<<4|0),
_PB_1 = (_PORT_B<<4|1),
_PB_2 = (_PORT_B<<4|2),
_PB_3 = (_PORT_B<<4|3),
_PB_4 = (_PORT_B<<4|4),
_PB_5 = (_PORT_B<<4|5),
_PB_6 = (_PORT_B<<4|6),
_PB_7 = (_PORT_B<<4|7),
_PC_0 = (_PORT_C<<4|0),
_PC_1 = (_PORT_C<<4|1),
_PC_2 = (_PORT_C<<4|2),
_PC_3 = (_PORT_C<<4|3),
_PC_4 = (_PORT_C<<4|4),
_PC_5 = (_PORT_C<<4|5),
_PC_6 = (_PORT_C<<4|6),
_PC_7 = (_PORT_C<<4|7),
_PC_8 = (_PORT_C<<4|8),
_PC_9 = (_PORT_C<<4|9),
_PD_0 = (_PORT_D<<4|0),
_PD_1 = (_PORT_D<<4|1),
_PD_2 = (_PORT_D<<4|2),
_PD_3 = (_PORT_D<<4|3),
_PD_4 = (_PORT_D<<4|4),
_PD_5 = (_PORT_D<<4|5),
_PD_6 = (_PORT_D<<4|6),
_PD_7 = (_PORT_D<<4|7),
_PD_8 = (_PORT_D<<4|8),
_PD_9 = (_PORT_D<<4|9),
_PE_0 = (_PORT_E<<4|0),
_PE_1 = (_PORT_E<<4|1),
_PE_2 = (_PORT_E<<4|2),
_PE_3 = (_PORT_E<<4|3),
_PE_4 = (_PORT_E<<4|4),
_PE_5 = (_PORT_E<<4|5),
_PE_6 = (_PORT_E<<4|6),
_PE_7 = (_PORT_E<<4|7),
_PE_8 = (_PORT_E<<4|8),
_PE_9 = (_PORT_E<<4|9),
_PE_A = (_PORT_E<<4|10),
_PF_0 = (_PORT_F<<4|0),
_PF_1 = (_PORT_F<<4|1),
_PF_2 = (_PORT_F<<4|2),
_PF_3 = (_PORT_F<<4|3),
_PF_4 = (_PORT_F<<4|4),
_PF_5 = (_PORT_F<<4|5),
// _PF_6 = (_PORT_F<<4|6),
// _PF_7 = (_PORT_F<<4|7),
_PG_0 = (_PORT_G<<4|0),
_PG_1 = (_PORT_G<<4|1),
_PG_2 = (_PORT_G<<4|2),
_PG_3 = (_PORT_G<<4|3),
_PG_4 = (_PORT_G<<4|4),
_PG_5 = (_PORT_G<<4|5),
_PG_6 = (_PORT_G<<4|6),
_PG_7 = (_PORT_G<<4|7),
_PH_0 = (_PORT_H<<4|0),
_PH_1 = (_PORT_H<<4|1),
_PH_2 = (_PORT_H<<4|2),
_PH_3 = (_PORT_H<<4|3),
_PH_4 = (_PORT_H<<4|4),
_PH_5 = (_PORT_H<<4|5),
_PH_6 = (_PORT_H<<4|6),
_PH_7 = (_PORT_H<<4|7),
_PI_0 = (_PORT_I<<4|0),
_PI_1 = (_PORT_I<<4|1),
_PI_2 = (_PORT_I<<4|2),
_PI_3 = (_PORT_I<<4|3),
_PI_4 = (_PORT_I<<4|4),
_PI_5 = (_PORT_I<<4|5),
_PI_6 = (_PORT_I<<4|6),
_PI_7 = (_PORT_I<<4|7),
_PJ_0 = (_PORT_J<<4|0),
_PJ_1 = (_PORT_J<<4|1),
_PJ_2 = (_PORT_J<<4|2),
_PJ_3 = (_PORT_J<<4|3),
_PJ_4 = (_PORT_J<<4|4),
_PJ_5 = (_PORT_J<<4|5),
_PJ_6 = (_PORT_J<<4|6),
// _PJ_7 = (_PORT_J<<4|7),
_PK_0 = (_PORT_K<<4|0),
_PK_1 = (_PORT_K<<4|1),
_PK_2 = (_PORT_K<<4|2),
_PK_3 = (_PORT_K<<4|3),
_PK_4 = (_PORT_K<<4|4),
_PK_5 = (_PORT_K<<4|5),
_PK_6 = (_PORT_K<<4|6),
// _PK_7 = (_PORT_K<<4|7),
// Not connected
_PIN_NC = (int)0xFFFFFFFF
} HAL_PIN_NAME;
typedef enum
{
GPIO_PIN_LOW = 0,
GPIO_PIN_HIGH = 1,
GPIO_PIN_ERR = 2 // read Pin error
} HAL_GPIO_PIN_STATE;
typedef enum {
DIN_PULL_NONE = 0, //floating or high impedance ?
DIN_PULL_LOW = 1,
DIN_PULL_HIGH = 2,
DOUT_PUSH_PULL = 3,
DOUT_OPEN_DRAIN = 4,
INT_LOW = (5|HAL_GPIO_PIN_INT_MODE), // Interrupt Low level trigger
INT_HIGH = (6|HAL_GPIO_PIN_INT_MODE), // Interrupt High level trigger
INT_FALLING = (7|HAL_GPIO_PIN_INT_MODE), // Interrupt Falling edge trigger
INT_RISING = (8|HAL_GPIO_PIN_INT_MODE) // Interrupt Rising edge trigger
} HAL_GPIO_PIN_MODE;
enum {
GPIO_PORT_A = 0,
GPIO_PORT_B = 1,
GPIO_PORT_C = 2,
GPIO_PORT_D = 3
};
typedef enum {
hal_PullNone = 0,
hal_PullUp = 1,
hal_PullDown = 2,
hal_OpenDrain = 3,
hal_PullDefault = hal_PullNone
} HAL_PinMode;
typedef struct _HAL_GPIO_PORT_ {
u32 out_data; // to write the GPIO port
u32 in_data; // to read the GPIO port
u32 dir; // config each pin direction
}HAL_GPIO_PORT, *PHAL_GPIO_PORT;
#define HAL_GPIO_PIN_NAME(port,pin) (((port)<<5)|(pin))
#define HAL_GPIO_GET_PORT_BY_NAME(x) ((x>>5) & 0x03)
#define HAL_GPIO_GET_PIN_BY_NAME(x) (x & 0x1f)
typedef struct _HAL_GPIO_PIN_ {
HAL_GPIO_PIN_MODE pin_mode;
u32 pin_name; // Pin: [7:5]: port number, [4:0]: pin number
}HAL_GPIO_PIN, *PHAL_GPIO_PIN;
typedef struct _HAL_GPIO_OP_ {
#if defined(__ICCARM__)
void* dummy;
#endif
}HAL_GPIO_OP, *PHAL_GPIO_OP;
typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id);
typedef void (*GPIO_USER_IRQ_FUN)(u32 Id);
typedef struct _HAL_GPIO_ADAPTER_ {
IRQ_HANDLE IrqHandle; // GPIO HAL IRQ Handle
GPIO_USER_IRQ_FUN UserIrqHandler; // GPIO IRQ Handler
GPIO_IRQ_FUN PortA_IrqHandler[32]; // The interrupt handler triggered by Port A[x]
VOID *PortA_IrqData[32];
VOID (*EnterCritical)(void);
VOID (*ExitCritical)(void);
u32 Local_Gpio_Dir[3]; // to record direction setting: 0- IN, 1- Out
u8 Gpio_Func_En; // Is GPIO HW function enabled ?
u8 Locked;
}HAL_GPIO_ADAPTER, *PHAL_GPIO_ADAPTER;
u32
HAL_GPIO_GetPinName(
u32 chip_pin
);
VOID
HAL_GPIO_PullCtrl(
u32 pin,
u32 mode
);
VOID
HAL_GPIO_Init(
HAL_GPIO_PIN *GPIO_Pin
);
VOID
HAL_GPIO_DeInit(
HAL_GPIO_PIN *GPIO_Pin
);
VOID
HAL_GPIO_Irq_Init(
HAL_GPIO_PIN *GPIO_Pin
);
VOID
HAL_GPIO_IP_DeInit(
VOID
);
extern u16 GPIOState[_PORT_MAX]; // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию.
#endif // end of "#define _HAL_GPIO_H_"

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_I2C_H_ //#ifndef _HAL_I2C_H_
#define _HAL_I2C_H_
#include "rtl8195a_i2c.h"
#include "hal_gdma.h"
//================= I2C CONFIGURATION START ==================
// I2C SAL User Configuration Flags
// I2C SAL operation types
#define I2C_POLL_OP_TYPE 1 //1
#define I2C_INTR_OP_TYPE 1 //1
#define I2C_DMA_OP_TYPE 1 //1
// I2C supports user register address
#define I2C_USER_REG_ADDR 1 //I2C User specific register address by using
//the first I2C data as the register
//address
// I2C SAL used module. Please set the I2C module flag to 1 to enable the related
// I2C module functions.
#define I2C0_USED 1
#define I2C1_USED 1
#define I2C2_USED 1
#define I2C3_USED 1
//================= I2C CONFIGURATION END ===================
//================= I2C HAL START ==========================
// I2C debug output
#define I2C_PREFIX "RTL8195A[i2c]: "
#define I2C_PREFIX_LVL " [i2c_DBG]: "
typedef enum _I2C_DBG_LVL_ {
HAL_I2C_LVL = 0x01,
SAL_I2C_LVL = 0x02,
VERI_I2C_LVL = 0x03,
}I2C_DBG_LVL,*PI2C_DBG_LVL;
#if CONFIG_DEBUG_LOG > 0
#ifdef CONFIG_DEBUG_LOG_I2C_HAL
#define DBG_I2C_LOG_PERD 100
#define I2CDBGLVL 0xFF
#define DBG_8195A_I2C(...) do{ \
_DbgDump(I2C_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_I2C_LVL(LVL,...) do{\
if (LVL&I2CDBGLVL){\
_DbgDump(I2C_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_I2C_LOG_PERD 100
#define DBG_8195A_I2C(...)
#define DBG_8195A_I2C_LVL(...)
#endif
#else
#define DBG_I2C_LOG_PERD 100
#define DBG_8195A_I2C(...)
#define DBG_8195A_I2C_LVL(...)
#endif
#define I2C_MTR_RTY_CNT 1024
//======================================================
// I2C HAL related enumeration
// I2C Module Selection
typedef enum _I2C_MODULE_SEL_ {
I2C0_SEL = 0x0,
I2C1_SEL = 0x1,
I2C2_SEL = 0x2,
I2C3_SEL = 0x3,
}I2C_MODULE_SEL,*PI2C_MODULE_SEL;
// I2C HAL initial data structure
typedef struct _HAL_I2C_INIT_DAT_ {
u8 I2CIdx; //I2C index used
u8 I2CEn; //I2C module enable
u8 I2CMaster; //Master or Slave mode
u8 I2CAddrMod; //I2C addressing mode(7-bit, 10-bit)
u8 I2CSpdMod; //I2C speed mode(Standard, Fast, High)
u8 I2CSetup; //I2C SDA setup time
u8 I2CRXTL; //I2C RX FIFO Threshold
u8 I2CTXTL; //I2C TX FIFO Threshold
u8 I2CBusLd; //I2C bus load (pf) for high speed mode
u8 I2CReSTR; //I2C restart support
u8 I2CGC; //I2C general support
u8 I2CStartB; //I2C start byte support
u8 I2CSlvNoAck; //I2C slave no ack support
u8 I2CDMACtrl; //I2C DMA feature support
u8 I2CCmd; //I2C Command
u8 I2CDataLen; //I2C Data Length
u8 I2CSlvAckGC; //I2C slave acks to General Call
u8 I2CStop; //I2C issues STOP bit or not
u16 RSVD0; //Bit0: used to control HalI2CMassSendRtl8195a_Patch sending
// RESTART or not by upper layer SW.
u8 *I2CRWData; //I2C Read/Write data pointer
u16 I2CIntrMSK; //I2C Interrupt Mask
u16 I2CIntrClr; //I2C Interrupt register to clear
u16 I2CAckAddr; //I2C target address in I2C Master mode,
//ack address in I2C Slave mode
u16 I2CSdaHd; //I2C SDA hold time
u32 I2CClk; //I2C bus clock (in kHz)
u8 I2CTxDMARqLv; //I2C TX DMA Empty Level
u8 I2CRxDMARqLv; //I2C RX DMA Full Level
u16 RSVD1; //Reserved
}HAL_I2C_INIT_DAT,*PHAL_I2C_INIT_DAT;
// I2C HAL Operations
typedef struct _HAL_I2C_OP_ {
HAL_Status (*HalI2CInit) (VOID *Data); //HAL I2C initialization
HAL_Status (*HalI2CDeInit) (VOID *Data); //HAL I2C de-initialization
HAL_Status (*HalI2CSend) (VOID *Data); //HAL I2C send
u8 (*HalI2CReceive) (VOID *Data); //HAL I2C receive
HAL_Status (*HalI2CEnable) (VOID *Data); //HAL I2C enable module
HAL_Status (*HalI2CIntrCtrl) (VOID *Data); //HAL I2C interrupt control
u32 (*HalI2CReadReg) (VOID *Data, u8 I2CReg);//HAL I2C read register
HAL_Status (*HalI2CWriteReg) (VOID *Data, u8 I2CReg, u32 RegVal);//HAL I2C write register
HAL_Status (*HalI2CSetCLK) (VOID *Data); //HAL I2C set bus clock
HAL_Status (*HalI2CMassSend) (VOID *Data); //HAL I2C mass send
HAL_Status (*HalI2CClrIntr) (VOID *Data); //HAL I2C clear interrupts
HAL_Status (*HalI2CClrAllIntr) (VOID *Data); //HAL I2C clear all interrupts
HAL_Status (*HalI2CDMACtrl) (VOID *Data); //HAL I2C DMA control
}HAL_I2C_OP, *PHAL_I2C_OP;
//================= I2C HAL END ===========================
//================= I2C SAL START ==========================
//I2C SAL Macros
//======================================================
// I2C SAL related enumerations
// I2C Extend Features
typedef enum _I2C_EXD_SUPPORT_{
I2C_EXD_RESTART = 0x1, //BIT_0, RESTART bit
I2C_EXD_GENCALL = 0x2, //BIT_1, Master generates General Call. All "send" operations generate General Call addresss
I2C_EXD_STARTB = 0x4, //BIT_2, Using START BYTE, instead of START Bit
I2C_EXD_SLVNOACK = 0x8, //BIT_3, Slave no ack to master
I2C_EXD_BUS400PF = 0x10, //BIT_4, I2C bus loading is 400pf
I2C_EXD_SLVACKGC = 0x20, //BIT_5, Slave acks to a General Call
I2C_EXD_USER_REG = 0x40, //BIT_6, Using User Register Address
I2C_EXD_USER_TWOB = 0x80, //BIT_7, User Register Address is 2-byte
I2C_EXD_MTR_ADDR_RTY= 0x100, //BIT_8, Master retries to send start condition and Slave address when the slave doesn't ack
// the address.
I2C_EXD_MTR_ADDR_UPD= 0x200, //BIT_9, Master dynamically updates slave address
I2C_EXD_MTR_HOLD_BUS= 0x400, //BIT_10, Master doesn't generate STOP when the FIFO is empty. This would make Master hold
// the bus.
}I2C_EXD_SUPPORT,*PI2C_EXD_SUPPORT;
// I2C operation type
typedef enum _I2C_OP_TYPE_ {
I2C_POLL_TYPE = 0x0,
I2C_DMA_TYPE = 0x1,
I2C_INTR_TYPE = 0x2,
}I2C_OP_TYPE, *PI2C_OP_TYPE;
// I2C pinmux selection
typedef enum _I2C_PINMUX_ {
I2C_PIN_S0 = 0x0,
I2C_PIN_S1 = 0x1,
I2C_PIN_S2 = 0x2,
I2C_PIN_S3 = 0x3, //Only valid for I2C0 and I2C3
}I2C_PINMUX, *PI2C_PINMUX;
// I2C module status
typedef enum _I2C_MODULE_STATUS_ {
I2C_DISABLE = 0x0,
I2C_ENABLE = 0x1,
}I2C_MODULE_STATUS, *PI2C_MODULE_STATUS;
// I2C device status
typedef enum _I2C_Device_STATUS_ {
I2C_STS_UNINITIAL = 0x00,
I2C_STS_INITIALIZED = 0x01,
I2C_STS_IDLE = 0x02,
I2C_STS_TX_READY = 0x03,
I2C_STS_TX_ING = 0x04,
I2C_STS_RX_READY = 0x05,
I2C_STS_RX_ING = 0x06,
I2C_STS_ERROR = 0x10,
I2C_STS_TIMEOUT = 0x11,
}I2C_Device_STATUS, *PI2C_Device_STATUS;
// I2C feature status
typedef enum _I2C_FEATURE_STATUS_{
I2C_FEATURE_DISABLED = 0,
I2C_FEATURE_ENABLED = 1,
}I2C_FEATURE_STATUS,*PI2C_FEATURE_STATUS;
// I2C device mode
typedef enum _I2C_DEV_MODE_ {
I2C_SLAVE_MODE = 0x0,
I2C_MASTER_MODE = 0x1,
}I2C_DEV_MODE, *PI2C_DEV_MODE;
// I2C Bus Transmit/Receive
typedef enum _I2C_DIRECTION_ {
I2C_ONLY_TX = 0x1,
I2C_ONLY_RX = 0x2,
I2C_TXRX = 0x3,
}I2C_DIRECTION, *PI2C_DIRECTION;
//I2C DMA module number
typedef enum _I2C_DMA_MODULE_SEL_ {
I2C_DMA_MODULE_0 = 0x0,
I2C_DMA_MODULE_1 = 0x1
}I2C_DMA_MODULE_SEL, *PI2C_DMA_MODULE_SEL;
// I2C0 DMA peripheral number
typedef enum _I2C0_DMA_PERI_NUM_ {
I2C0_DMA_TX_NUM = 0x8,
I2C0_DMA_RX_NUM = 0x9,
}I2C0_DMA_PERI_NUM,*PI2C0_DMA_PERI_NUM;
// I2C1 DMA peripheral number
typedef enum _I2C1_DMA_PERI_NUM_ {
I2C1_DMA_TX_NUM = 0xA,
I2C1_DMA_RX_NUM = 0xB,
}I2C1_DMA_PERI_NUM,*PI2C1_DMA_PERI_NUM;
// I2C0 DMA module used
typedef enum _I2C0_DMA_MODULE_ {
I2C0_DMA0 = 0x0,
I2C0_DMA1 = 0x1,
}I2C0_DMA_MODULE,*PI2C0_DMA_MODULE;
// I2C0 DMA module used
typedef enum _I2C1_DMA_MODULE_ {
I2C1_DMA0 = 0x0,
I2C1_DMA1 = 0x1,
}I2C1_DMA_MODULE,*PI2C1_DMA_MODULE;
// I2C command type
typedef enum _I2C_COMMAND_TYPE_ {
I2C_WRITE_CMD = 0x0,
I2C_READ_CMD = 0x1,
}I2C_COMMAND_TYPE,*PI2C_COMMAND_TYPE;
// I2C STOP BIT
typedef enum _I2C_STOP_TYPE_ {
I2C_STOP_DIS = 0x0,
I2C_STOP_EN = 0x1,
}I2C_STOP_TYPE, *PI2C_STOP_TYPE;
// I2C error type
typedef enum _I2C_ERR_TYPE_ {
I2C_ERR_RX_UNDER = 0x01, //I2C RX FIFO Underflow
I2C_ERR_RX_OVER = 0x02, //I2C RX FIFO Overflow
I2C_ERR_TX_OVER = 0x04, //I2C TX FIFO Overflow
I2C_ERR_TX_ABRT = 0x08, //I2C TX terminated
I2C_ERR_SLV_TX_NACK = 0x10, //I2C slave transmission terminated by master NACK,
//but there are data in slave TX FIFO
I2C_ERR_MST_A_NACK = 0x12,
I2C_ERR_MST_D_NACK = 0x13,
I2C_ERR_USER_REG_TO = 0x20,
I2C_ERR_RX_CMD_TO = 0x21,
I2C_ERR_RX_FF_TO = 0x22,
I2C_ERR_TX_CMD_TO = 0x23,
I2C_ERR_TX_FF_TO = 0x24,
I2C_ERR_TX_ADD_TO = 0x25,
I2C_ERR_RX_ADD_TO = 0x26,
}I2C_ERR_TYPE, *PI2C_ERR_TYPE;
// I2C Time Out type
typedef enum _I2C_TIMEOUT_TYPE_ {
I2C_TIMEOOUT_DISABLE = 0x00,
I2C_TIMEOOUT_ENDLESS = 0xFFFFFFFF,
}I2C_TIMEOUT_TYPE, *PI2C_TIMEOUT_TYPE;
//======================================================
// SAL I2C related data structures
// I2C user callback adapter
typedef struct _SAL_I2C_USERCB_ADPT_ {
VOID (*USERCB) (VOID *Data);
u32 USERData;
}SAL_I2C_USERCB_ADPT, *PSAL_I2C_USERCB_ADPT;
// I2C user callback structure
typedef struct _SAL_I2C_USER_CB_ {
PSAL_I2C_USERCB_ADPT pTXCB; //I2C Transmit Callback
PSAL_I2C_USERCB_ADPT pTXCCB; //I2C Transmit Complete Callback
PSAL_I2C_USERCB_ADPT pRXCB; //I2C Receive Callback
PSAL_I2C_USERCB_ADPT pRXCCB; //I2C Receive Complete Callback
PSAL_I2C_USERCB_ADPT pRDREQCB; //I2C Read Request Callback
PSAL_I2C_USERCB_ADPT pERRCB; //I2C Error Callback
PSAL_I2C_USERCB_ADPT pDMATXCB; //I2C DMA Transmit Callback
PSAL_I2C_USERCB_ADPT pDMATXCCB; //I2C DMA Transmit Complete Callback
PSAL_I2C_USERCB_ADPT pDMARXCB; //I2C DMA Receive Callback
PSAL_I2C_USERCB_ADPT pDMARXCCB; //I2C DMA Receive Complete Callback
PSAL_I2C_USERCB_ADPT pGENCALLCB; //I2C General Call Callback
}SAL_I2C_USER_CB, *PSAL_I2C_USER_CB;
// I2C Transmit Buffer
typedef struct _SAL_I2C_TRANSFER_BUF_ {
u16 DataLen; //I2C Transmfer Length
u16 TargetAddr; //I2C Target Address. It's only valid in Master Mode.
u32 RegAddr; //I2C Register Address. It's only valid in Master Mode.
u32 RSVD; //
u8 *pDataBuf; //I2C Transfer Buffer Pointer
}SAL_I2C_TRANSFER_BUF,*PSAL_I2C_TRANSFER_BUF;
typedef struct _SAL_I2C_DMA_USER_DEF_ {
u8 TxDatSrcWdth;
u8 TxDatDstWdth;
u8 TxDatSrcBstSz;
u8 TxDatDstBstSz;
u8 TxChNo;
u8 RSVD0;
u16 RSVD1;
u8 RxDatSrcWdth;
u8 RxDatDstWdth;
u8 RxDatSrcBstSz;
u8 RxDatDstBstSz;
u8 RxChNo;
u8 RSVD2;
u16 RSVD3;
}SAL_I2C_DMA_USER_DEF, *PSAL_I2C_DMA_USER_DEF;
// RTK I2C OP
typedef struct _RTK_I2C_OP_ {
HAL_Status (*Init) (VOID *Data);
HAL_Status (*DeInit) (VOID *Data);
HAL_Status (*Send) (VOID *Data);
HAL_Status (*Receive) (VOID *Data);
HAL_Status (*IoCtrl) (VOID *Data);
HAL_Status (*PowerCtrl) (VOID *Data);
}RTK_I2C_OP, *PRTK_I2C_OP;
// Software API Level I2C Handler
typedef struct _SAL_I2C_HND_ {
u8 DevNum; //I2C device number
u8 PinMux; //I2C pin mux seletion
u8 OpType; //I2C operation type selection
volatile u8 DevSts; //I2C device status
u8 I2CMaster; //I2C Master or Slave mode
u8 I2CAddrMod; //I2C 7-bit or 10-bit mode
u8 I2CSpdMod; //I2C SS/ FS/ HS speed mode
u8 I2CAckAddr; //I2C target address in Master
//mode or ack address in Slave
//mode
u16 I2CClk; //I2C bus clock
u8 MasterRead; //I2C Master Read Supported,
//An Address will be sent before
//read data back.
u8 I2CDmaSel; //I2C DMA module select
// 0 for DMA0,
// 1 for DMA1
u8 I2CTxDMARqLv; //I2C TX DMA Empty Level
u8 I2CRxDMARqLv; //I2C RX DMA Full Level
u16 RSVD0; //Reserved
u32 AddRtyTimeOut; //I2C TimeOut Value for master send address retry
//(Originally Reserved.)
u32 I2CExd; //I2C extended options:
//bit 0: I2C RESTART supported,
// 0 for NOT supported,
// 1 for supported
//bit 1: I2C General Call supported
// 0 for NOT supported,
// 1 for supported
//bit 2: I2C START Byte supported
// 0 for NOT supported,
// 1 for supported
//bit 3: I2C Slave-No-Ack
// supported
// 0 for NOT supported,
// 1 for supported
//bit 4: I2C bus loading,
// 0 for 100pf,
// 1 for 400pf
//bit 5: I2C slave ack to General
// Call
//bit 6: I2C User register address
//bit 7: I2C 2-Byte User register
// address
//bit 8: I2C slave address no ack retry,
// It's only for Master mode,
// when slave doesn't ack the
// address
//bit 31~bit 8: Reserved
u32 ErrType; //
u32 TimeOut; //I2C IO Timeout count, in ms
PHAL_I2C_INIT_DAT pInitDat; //Pointer to I2C initial data struct
PSAL_I2C_TRANSFER_BUF pTXBuf; //Pointer to I2C TX buffer
PSAL_I2C_TRANSFER_BUF pRXBuf; //Pointer to I2C RX buffer
PSAL_I2C_USER_CB pUserCB; //Pointer to I2C User Callback
PSAL_I2C_DMA_USER_DEF pDMAConf; //Pointer to I2C User Define DMA config
}SAL_I2C_HND, *PSAL_I2C_HND;
//======================================================
// I2C SAL Function Prototypes
// For checking I2C input index valid or not
static inline HAL_Status
RtkI2CIdxChk(
IN u8 I2CIdx
)
{
if (I2CIdx > I2C3_SEL)
return HAL_ERR_UNKNOWN;
return HAL_OK;
}
#if 0
//For checking I2C operation type valid or not
static inline HAL_Status
RtkI2COpTypeChk(
IN VOID *Data
)
{
PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data;
if (pSalI2CHND->OpType == I2C_POLL_TYPE)
return HAL_ERR_UNKNOWN;
if (pSalI2CHND->OpType == I2C_DMA_TYPE)
return HAL_ERR_UNKNOWN;
if (pSalI2CHND->OpType == I2C_INTR_TYPE)
return HAL_ERR_UNKNOWN;
pSalI2CHND = pSalI2CHND;
return HAL_OK;
}
#endif
//For checking I2C DMA available or not
static inline HAL_Status
RtkI2CDMAChk(
IN VOID *Data
)
{
PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data;
if (pSalI2CHND->OpType == I2C_DMA_TYPE) {
if (pSalI2CHND->DevNum >= I2C2_SEL)
return HAL_ERR_UNKNOWN;
}
else {
return HAL_ERR_UNKNOWN;
}
return HAL_OK;
}
//For checking I2C DMA available or not
static inline HAL_Status
RtkI2CDMAInitChk(
IN VOID *Data
)
{
PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data;
if (pSalI2CHND->OpType != I2C_DMA_TYPE) {
return HAL_ERR_UNKNOWN;
}
else {
return HAL_OK;
}
}
//======================================================
//SAL I2C management function prototype
_LONG_CALL_ROM_ HAL_Status RtkI2CLoadDefault(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CInit(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CDeInit(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CSend(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CReceive(IN VOID *Data);
_LONG_CALL_ROM_ VOID RtkSalI2COpInit(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CSendUserAddr(IN VOID *Data,IN u8 MtrWr);
_LONG_CALL_ROM_ HAL_Status RtkI2CIoCtrl(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CPowerCtrl(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CInitForPS(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CDeInitForPS(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CDisablePS(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CEnablePS(IN VOID *Data);
//================= I2C SAL END ===========================
//================= I2C SAL MANAGEMENT START =================
// I2C SAL management macros
#define SAL_USER_CB_NUM (sizeof(SAL_I2C_USER_CB) / sizeof(PSAL_I2C_USERCB_ADPT))
//======================================================
// I2C SAL management data structures
// I2C SAL handle private
typedef struct _SAL_I2C_HND_PRIV_ {
VOID **ppSalI2CHnd; //Pointer to SAL_I2C_HND pointer
SAL_I2C_HND SalI2CHndPriv; //Private SAL_I2C_HND
}SAL_I2C_HND_PRIV, *PSAL_I2C_HND_PRIV;
//I2C SAL management adapter
typedef struct _SAL_I2C_MNGT_ADPT_ {
PSAL_I2C_HND_PRIV pSalHndPriv; //Pointer to SAL_I2C_HND
PHAL_I2C_INIT_DAT pHalInitDat; //Pointer to HAL I2C initial data( HAL_I2C_INIT_DAT )
PHAL_I2C_OP pHalOp; //Pointer to HAL I2C operation( HAL_I2C_OP )
VOID (*pHalOpInit)(VOID*); //Pointer to HAL I2C initialize function
PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
PSAL_I2C_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_I2C_USER_CB )
volatile u32 MstRDCmdCnt; //Used for Master Read command count
volatile u32 InnerTimeOut; //Used for SAL internal timeout count
VOID (*pSalIrqFunc)(VOID*); //Used for SAL I2C interrupt function
PSAL_I2C_DMA_USER_DEF pDMAConf; //Pointer to I2C User Define DMA config
PHAL_GDMA_ADAPTER pHalTxGdmaAdp; //Pointer to HAL_GDMA_ADAPTER
PHAL_GDMA_ADAPTER pHalRxGdmaAdp; //Pointer to HAL_GDMA_ADAPTER
PHAL_GDMA_OP pHalGdmaOp; //Pointer to HAL_GDMA_OP
VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL I2C initialize function
PIRQ_HANDLE pIrqTxGdmaHnd; //Pointer to IRQ handler for Tx GDMA
PIRQ_HANDLE pIrqRxGdmaHnd; //Pointer to IRQ handler for Rx GDMA
VOID (*pSalDMATxIrqFunc)(VOID*); //Used for SAL I2C interrupt function
VOID (*pSalDMARxIrqFunc)(VOID*); //Used for SAL I2C interrupt function
u32 RSVD; //Reserved
}SAL_I2C_MNGT_ADPT, *PSAL_I2C_MNGT_ADPT;
//======================================================
//SAL I2C management function prototype
PSAL_I2C_MNGT_ADPT RtkI2CGetMngtAdpt(IN u8 I2CIdx);
HAL_Status RtkI2CFreeMngtAdpt(IN PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt);
PSAL_I2C_HND RtkI2CGetSalHnd(IN u8 I2CIdx);
HAL_Status RtkI2CFreeSalHnd(IN PSAL_I2C_HND pSalI2CHND);
u32 RtkSalI2CSts(IN VOID *Data);
extern _LONG_CALL_ VOID I2CISRHandle(IN VOID *Data);
extern _LONG_CALL_ VOID I2CTXGDMAISRHandle(IN VOID *Data);
extern _LONG_CALL_ VOID I2CRXGDMAISRHandle(IN VOID *Data);
extern HAL_Status I2CIsTimeout (IN u32 StartCount, IN u32 TimeoutCnt);
extern HAL_TIMER_OP HalTimerOp;
//======================================================
// Function Prototypes
_LONG_CALL_ VOID HalI2COpInit(IN VOID *Data);
//================= I2C SAL MANAGEMENT END ==================
//================= Rtl8195a I2C V02 function prototype ============
_LONG_CALL_ VOID HalI2COpInitV02(IN VOID *Data);
_LONG_CALL_ VOID I2CISRHandleV02(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CSendV02(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CReceiveV02(IN VOID *Data);
_LONG_CALL_ VOID RtkSalI2COpInitV02(IN VOID *Data);
//================= Rtl8195a I2C V02 function prototype END==========
//================= Rtl8195a I2C V04 function prototype ============
_LONG_CALL_ VOID HalI2COpInit_V04(IN VOID *Data);
_LONG_CALL_ VOID I2CISRHandle_V04(IN VOID *Data);
//================= Rtl8195a I2C V04 function prototype END==========
//======================================================
//SAL I2C patch function prototype
HAL_Status RtkI2CSend_Patch(IN VOID *Data);
HAL_Status RtkI2CReceive_Patch(IN VOID *Data);
VOID HalI2COpInit_Patch(IN VOID *Data);
VOID I2CISRHandle_Patch(IN VOID *Data);
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#define RtkI2CSend RtkI2CSend_Patch
#define RtkI2CReceive RtkI2CReceive_Patch
#endif
HAL_Status RtkI2CSend_Patch(IN VOID *Data);
HAL_Status RtkI2CReceive_Patch(IN VOID *Data);
//================= I2C SAL END ===========================
#endif //#ifndef _HAL_I2C_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_I2S_H_
#define _HAL_I2S_H_
#include "rtl8195a_i2s.h"
/* User Define Flags */
#define I2S_MAX_ID 1 // valid I2S index 0 ~ I2S_MAX_ID
/**********************************************************************/
/* I2S HAL initial data structure */
typedef struct _HAL_I2S_INIT_DAT_ {
u8 I2SIdx; /*I2S index used*/
u8 I2SEn; /*I2S module enable tx/rx/tx+rx*/
u8 I2SMaster; /*I2S Master or Slave mode*/
u8 I2SWordLen; /*I2S Word length 16 or 24bits*/
u8 I2SChNum; /*I2S Channel number mono or stereo*/
u8 I2SPageNum; /*I2S Page Number 2~4*/
u16 I2SPageSize; /*I2S page Size 1~4096 word*/
u8 *I2STxData; /*I2S Tx data pointer*/
u8 *I2SRxData; /*I2S Rx data pointer*/
u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/
u32 I2STxIntrClr; /*I2S Tx Interrupt register to clear */
u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/
u32 I2SRxIntrClr; /*I2S Rx Interrupt register to clear*/
u16 I2STxIdx; /*I2S TX page index */
u16 I2SRxIdx; /*I2S RX page index */
u16 I2SHWTxIdx; /*I2S HW TX page index */
u16 I2SHWRxIdx; /*I2S HW RX page index */
u16 I2SRate; /*I2S sample rate*/
u8 I2STRxAct; /*I2S tx rx act*/
}HAL_I2S_INIT_DAT, *PHAL_I2S_INIT_DAT;
/**********************************************************************/
/* I2S Data Structures */
/* I2S Module Selection */
typedef enum _I2S_MODULE_SEL_ {
I2S0_SEL = 0x0,
I2S1_SEL = 0x1,
}I2S_MODULE_SEL,*PI2S_MODULE_SEL;
/*
typedef struct _HAL_I2S_ADAPTER_ {
u32 Enable:1;
I2S_CTL_REG I2sCtl;
I2S_SETTING_REG I2sSetting;
u32 abc;
u8 I2sIndex;
}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
*/
/* I2S HAL Operations */
typedef struct _HAL_I2S_OP_ {
RTK_STATUS (*HalI2SInit) (VOID *Data);
RTK_STATUS (*HalI2SDeInit) (VOID *Data);
RTK_STATUS (*HalI2STx) (VOID *Data, u8 *pBuff);
RTK_STATUS (*HalI2SRx) (VOID *Data, u8 *pBuff);
RTK_STATUS (*HalI2SEnable) (VOID *Data);
RTK_STATUS (*HalI2SIntrCtrl) (VOID *Data);
u32 (*HalI2SReadReg) (VOID *Data, u8 I2SReg);
RTK_STATUS (*HalI2SSetRate) (VOID *Data);
RTK_STATUS (*HalI2SSetWordLen) (VOID *Data);
RTK_STATUS (*HalI2SSetChNum) (VOID *Data);
RTK_STATUS (*HalI2SSetPageNum) (VOID *Data);
RTK_STATUS (*HalI2SSetPageSize) (VOID *Data);
RTK_STATUS (*HalI2SClrIntr) (VOID *Data);
RTK_STATUS (*HalI2SClrAllIntr) (VOID *Data);
RTK_STATUS (*HalI2SDMACtrl) (VOID *Data);
/*
VOID (*HalI2sOnOff)(VOID *Data);
BOOL (*HalI2sInit)(VOID *Data);
BOOL (*HalI2sSetting)(VOID *Data);
BOOL (*HalI2sEn)(VOID *Data);
BOOL (*HalI2sIsrEnAndDis) (VOID *Data);
BOOL (*HalI2sDumpReg)(VOID *Data);
BOOL (*HalI2s)(VOID *Data);
*/
}HAL_I2S_OP, *PHAL_I2S_OP;
/**********************************************************************/
/* I2S Pinmux Selection */
#if 0
typedef enum _I2S0_PINMUX_ {
I2S0_TO_S0 = 0x0,
I2S0_TO_S1 = 0x1,
I2S0_TO_S2 = 0x2,
}I2S0_PINMUX, *PI2S0_PINMUX;
typedef enum _I2S1_PINMUX_ {
I2S1_TO_S0 = 0x0,
I2S1_TO_S1 = 0x1,
}I2S1_PINMUX, *PI2S1_PINMUX;
#endif
typedef enum _I2S_PINMUX_ {
I2S_S0 = 0,
I2S_S1 = 1,
I2S_S2 = 2,
I2S_S3 = 3
}I2S_PINMUX, *PI2S_PINMUX;
/* I2S Module Status */
typedef enum _I2S_MODULE_STATUS_ {
I2S_DISABLE = 0x0,
I2S_ENABLE = 0x1,
}I2S_MODULE_STATUS, *PI2S_MODULE_STATUS;
/* I2S Device Status */
typedef enum _I2S_Device_STATUS_ {
I2S_STS_UNINITIAL = 0x00,
I2S_STS_INITIALIZED = 0x01,
I2S_STS_IDLE = 0x02,
I2S_STS_TX_READY = 0x03,
I2S_STS_TX_ING = 0x04,
I2S_STS_RX_READY = 0x05,
I2S_STS_RX_ING = 0x06,
I2S_STS_TRX_READY = 0x07,
I2S_STS_TRX_ING = 0x08,
I2S_STS_ERROR = 0x09,
}I2S_Device_STATUS, *PI2S_Device_STATUS;
/* I2S Feature Status */
typedef enum _I2S_FEATURE_STATUS_{
I2S_FEATURE_DISABLED = 0,
I2S_FEATURE_ENABLED = 1,
}I2S_FEATURE_STATUS,*PI2S_FEATURE_STATUS;
/* I2S Device Mode */
typedef enum _I2S_DEV_MODE_ {
I2S_MASTER_MODE = 0x0,
I2S_SLAVE_MODE = 0x1
}I2S_DEV_MODE, *PI2S_DEV_MODE;
/* I2S Word Length */
typedef enum _I2S_WORD_LEN_ {
I2S_WL_16 = 0x0,
I2S_WL_24 = 0x1,
}I2S_WORD_LEN, *PI2S_WORD_LEN;
/* I2S Bus Transmit/Receive */
typedef enum _I2S_DIRECTION_ {
I2S_ONLY_RX = 0x0,
I2S_ONLY_TX = 0x1,
I2S_TXRX = 0x2
}I2S_DIRECTION, *PI2S_DIRECTION;
/* I2S Channel number */
typedef enum _I2S_CH_NUM_ {
I2S_CH_STEREO = 0x0,
I2S_CH_RSVD = 0x1,
I2S_CH_MONO = 0x2
}I2S_CH_NUM, *PI2S_CH_NUM;
/* I2S Page number */
typedef enum _I2S_PAGE_NUM_ {
I2S_1PAGE = 0x0,
I2S_2PAGE = 0x1,
I2S_3PAGE = 0x2,
I2S_4PAGE = 0x3
}I2S_PAGE_NUM, *PI2S_PAGE_NUM;
/* I2S Sample rate*/
typedef enum _I2S_SAMPLE_RATE_ {
I2S_SR_8KHZ = 0x00, // /12
I2S_SR_16KHZ = 0x01, // /6
I2S_SR_24KHZ = 0x02, // /4
I2S_SR_32KHZ = 0x03, // /3
I2S_SR_48KHZ = 0x05, // /2
I2S_SR_96KHZ = 0x06, // x1, base 96kHz
I2S_SR_7p35KHZ = 0x10,
I2S_SR_11p02KHZ = 0x11,
I2S_SR_22p05KHZ = 0x12,
I2S_SR_29p4KHZ = 0x13,
I2S_SR_44p1KHZ = 0x15,
I2S_SR_88p2KHZ = 0x16 // x1, base 88200Hz
}I2S_SAMPLE_RATE, *PI2S_SAMPLE_RATE;
/* I2S TX interrupt mask/status */
typedef enum _I2S_TX_IMR_ {
I2S_TX_INT_PAGE0_OK = (1<<0),
I2S_TX_INT_PAGE1_OK = (1<<1),
I2S_TX_INT_PAGE2_OK = (1<<2),
I2S_TX_INT_PAGE3_OK = (1<<3),
I2S_TX_INT_FULL = (1<<4),
I2S_TX_INT_EMPTY = (1<<5)
} I2S_TX_IMR, *PI2S_TX_IMR;
/* I2S RX interrupt mask/status */
typedef enum _I2S_RX_IMR_ {
I2S_RX_INT_PAGE0_OK = (1<<0),
I2S_RX_INT_PAGE1_OK = (1<<1),
I2S_RX_INT_PAGE2_OK = (1<<2),
I2S_RX_INT_PAGE3_OK = (1<<3),
I2S_RX_INT_EMPTY = (1<<4),
I2S_RX_INT_FULL = (1<<5)
} I2S_RX_IMR, *PI2S_RX_IMR;
/* I2S User Callbacks */
typedef struct _SAL_I2S_USER_CB_{
VOID (*TXCB) (VOID *Data);
VOID (*TXCCB) (VOID *Data);
VOID (*RXCB) (VOID *Data);
VOID (*RXCCB) (VOID *Data);
VOID (*RDREQCB) (VOID *Data);
VOID (*ERRCB) (VOID *Data);
VOID (*GENCALLCB) (VOID *Data);
}SAL_I2S_USER_CB,*PSAL_I2S_USER_CB;
typedef struct _I2S_USER_CB_{
VOID (*TxCCB)(uint32_t id, char *pbuf);
u32 TxCBId;
VOID (*RxCCB)(uint32_t id, char *pbuf);
u32 RxCBId;
}I2S_USER_CB,*PI2S_USER_CB;
/* Software API Level I2S Handler */
typedef struct _HAL_I2S_ADAPTER_{
u8 DevNum; //I2S device number
u8 PinMux; //I2S pin mux seletion
u8 RSVD0; //Reserved
volatile u8 DevSts; //I2S device status
u32 RSVD2; //Reserved
u32 I2SExd; //I2S extended options:
//bit 0: I2C RESTART supported,
// 0 for NOT supported,
// 1 for supported
//bit 1: I2C General Call supported
// 0 for NOT supported,
// 1 for supported
//bit 2: I2C START Byte supported
// 0 for NOT supported,
// 1 for supported
//bit 3: I2C Slave-No-Ack
// supported
// 0 for NOT supported,
// 1 for supported
//bit 4: I2C bus loading,
// 0 for 100pf,
// 1 for 400pf
//bit 5: I2C slave ack to General
// Call
//bit 6: I2C User register address
//bit 7: I2C 2-Byte User register
// address
//bit 31~bit 8: Reserved
u32 ErrType; //
u32 TimeOut; //I2S IO Timeout count
PHAL_I2S_INIT_DAT pInitDat; //Pointer to I2S initial data struct
I2S_USER_CB UserCB; //Pointer to I2S User Callback
IRQ_HANDLE IrqHandle; // Irq Handler
u32* TxPageList[4]; // The Tx DAM buffer: pointer of each page
u32* RxPageList[4]; // The Tx DAM buffer: pointer of each page
}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
typedef struct _HAL_I2S_DEF_SETTING_{
u8 I2SMaster; // Master or Slave mode
u8 DevSts; //I2S device status
u8 I2SChNum; //I2S Channel number mono or stereo
u8 I2SPageNum; //I2S Page number 2~4
u8 I2STRxAct; //I2S tx rx act, tx only or rx only or tx+rx
u8 I2SWordLen; //I2S Word length 16bit or 24bit
u16 I2SPageSize; //I2S Page size 1~4096 word
u16 I2SRate; //I2S sample rate 8k ~ 96khz
u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/
u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/
}HAL_I2S_DEF_SETTING, *PHAL_I2S_DEF_SETTING;
/**********************************************************************/
HAL_Status
RtkI2SLoadDefault(IN VOID *Adapter, IN VOID *Setting);
HAL_Status
RtkI2SInit(IN VOID *Data);
HAL_Status
RtkI2SDeInit(IN VOID *Data);
HAL_Status
RtkI2SEnable(IN VOID *Data);
HAL_Status
RtkI2SDisable(IN VOID *Data);
extern HAL_Status
HalI2SInit( IN VOID *Data);
extern VOID
HalI2SDeInit( IN VOID *Data);
extern HAL_Status
HalI2SDisable( IN VOID *Data);
extern HAL_Status
HalI2SEnable( IN VOID *Data);
/**********************************************************************/
VOID I2S0ISRHandle(VOID *Data);
VOID I2S1ISRHandle(VOID *Data);
/**********************************************************************/
VOID HalI2SOpInit(
IN VOID *Data
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_IRQN_H_
#define _HAL_IRQN_H_
#define PERIPHERAL_IRQ_BASE_NUM 64
typedef enum _IRQn_Type_ {
#if 0
/****** Cortex-M3 Processor Exceptions Numbers ********/
NON_MASKABLE_INT_IRQ = -14,
HARD_FAULT_IRQ = -13,
MEM_MANAGE_FAULT_IRQ = -12,
BUS_FAULT_IRQ = -11,
USAGE_FAULT_IRQ = -10,
SVCALL_IRQ = -5,
DEBUG_MONITOR_IRQ = -4,
PENDSVC_IRQ = -2,
SYSTICK_IRQ = -1,
#else
/****** Cortex-M3 Processor Exceptions Numbers ********/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
#endif
/****** RTL8195A Specific Interrupt Numbers ************/
SYSTEM_ON_IRQ = 0,
WDG_IRQ = 1,
TIMER0_IRQ = 2,
TIMER1_IRQ = 3,
I2C3_IRQ = 4,
TIMER2_7_IRQ = 5,
SPI0_IRQ = 6,
GPIO_IRQ = 7,
UART0_IRQ = 8,
SPI_FLASH_IRQ = 9,
USB_OTG_IRQ = 10,
SDIO_HOST_IRQ = 11,
SDIO_DEVICE_IRQ = 12,
I2S0_PCM0_IRQ = 13,
I2S1_PCM1_IRQ = 14,
WL_DMA_IRQ = 15,
WL_PROTOCOL_IRQ = 16,
CRYPTO_IRQ = 17,
GMAC_IRQ = 18,
PERIPHERAL_IRQ = 19,
GDMA0_CHANNEL0_IRQ = 20,
GDMA0_CHANNEL1_IRQ = 21,
GDMA0_CHANNEL2_IRQ = 22,
GDMA0_CHANNEL3_IRQ = 23,
GDMA0_CHANNEL4_IRQ = 24,
GDMA0_CHANNEL5_IRQ = 25,
GDMA1_CHANNEL0_IRQ = 26,
GDMA1_CHANNEL1_IRQ = 27,
GDMA1_CHANNEL2_IRQ = 28,
GDMA1_CHANNEL3_IRQ = 29,
GDMA1_CHANNEL4_IRQ = 30,
GDMA1_CHANNEL5_IRQ = 31,
/****** RTL8195A Peripheral Interrupt Numbers ************/
I2C0_IRQ = 64,// 0 + 64,
I2C1_IRQ = 65,// 1 + 64,
I2C2_IRQ = 66,// 2 + 64,
SPI1_IRQ = 72,// 8 + 64,
SPI2_IRQ = 73,// 9 + 64,
UART1_IRQ = 80,// 16 + 64,
UART2_IRQ = 81,// 17 + 64,
UART_LOG_IRQ = 88,// 24 + 64,
ADC_IRQ = 89,// 25 + 64,
DAC0_IRQ = 91,// 27 + 64,
DAC1_IRQ = 92,// 28 + 64,
//RXI300_IRQ = 93// 29 + 64
LP_EXTENSION_IRQ = 93,// 29+64
PTA_TRX_IRQ = 95,// 31+64
RXI300_IRQ = 96,// 0+32 + 64
NFC_IRQ = 97 // 1+32+64
} IRQn_Type, *PIRQn_Type;
typedef VOID (*HAL_VECTOR_FUN) (VOID);
typedef enum _VECTOR_TABLE_TYPE_{
DEDECATED_VECTRO_TABLE,
PERIPHERAL_VECTOR_TABLE
}VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE;
typedef void (*IRQ_FUN)(VOID *Data);
typedef struct _IRQ_HANDLE_ {
IRQ_FUN IrqFun;
IRQn_Type IrqNum;
u32 Data;
u32 Priority;
}IRQ_HANDLE, *PIRQ_HANDLE;
#endif //_HAL_IRQN_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_LOG_UART_H_
#define _HAL_LOG_UART_H_
#include "hal_diag.h"
#define LOG_UART_WAIT_FOREVER 0xffffffff
// Define Line Control Register Bits
typedef enum {
LCR_DLS_5B = 0, // Data Length: 5 bits
LCR_DLS_6B = BIT(0), // Data Length: 6 bits
LCR_DLS_7B = BIT(1), // Data Length: 7 bits
LCR_DLS_8B = (BIT(1)|BIT(0)), // Data Length: 7 bits
LCR_STOP_1B = 0, // Number of stop bits: 1
LCR_STOP_2B = BIT(2), // Number of stop bits: 1.5(data len=5) or 2
LCR_PARITY_NONE = 0, // Parity Enable: 0
LCR_PARITY_ODD = BIT(3), // Parity Enable: 1, Even Parity: 0
LCR_PARITY_EVEN = (BIT(4)|BIT(3)), // Parity Enable: 1, Even Parity: 1
LCR_BC = BIT(6), // Break Control Bit
LCR_DLAB = BIT(7) // Divisor Latch Access Bit
} LOG_UART_LINE_CTRL;
// define Log UART Interrupt Indication ID
/*
IIR[3:0]:
0000 = modem status
0001 = no interrupt pending
0010 = THR empty
0100 = received data available
0110 = receiver line status
0111 = busy detect
1100 = character timeout
*/
typedef enum {
IIR_MODEM_STATUS = 0, // Clear to send or data set ready or ring indicator or data carrier detect.
IIR_NO_PENDING = 1,
IIR_THR_EMPTY = 2, // TX FIFO level lower than threshold or FIFO empty
IIR_RX_RDY = 4, // RX data ready
IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt
IIR_BUSY = 7,
IIR_CHAR_TIMEOUT = 12 // timeout: Rx dara ready but no read
} LOG_UART_INT_ID;
// Define Interrupt Enable Bit
typedef enum {
IER_ERBFI = BIT(0), // Enable Received Data Available Interrupt
IER_ETBEI = BIT(1), // Enable Transmit Holding Register Empty Interrupt
IER_ELSI = BIT(2), // Enable Receiver Line Status Interrupt
IER_EDSSI = BIT(3), // Enable Modem Status Interrupt
IER_PTIME = BIT(7) // Programmable THRE Interrupt Mode Enable
} LOG_UART_INT_EN;
// Define Line Status Bit
typedef enum {
LSR_DR = BIT(0), // Data Ready bit
LSR_OE = BIT(1), // Overrun error bit
LSR_PE = BIT(2), // Parity Error bit
LSR_FE = BIT(3), // Framing Error bit
LSR_BI = BIT(4), // Break Interrupt bit
LSR_THRE = BIT(5), // Transmit Holding Register Empty bit(IER_PTIME=0)
LSR_FIFOF = BIT(5), // Transmit FIFO Full bit(IER_PTIME=1)
LSR_TEMT = BIT(6), // Transmitter Empty bit
LSR_RFE = BIT(7) // Receiver FIFO Error bit
} LOG_UART_LINE_STATUS;
enum {
LOG_UART_RST_TX_FIFO = 0x01,
LOG_UART_RST_RX_FIFO = 0x02
};
#define LOG_UART_TX_FIFO_DEPTH 16
#define LOG_UART_RX_FIFO_DEPTH 16
// Define FIFO Control Register Bits
typedef enum {
FCR_FIFO_EN = BIT(0), // FIFO Enable.
FCR_RST_RX = BIT(1), // RCVR FIFO Reset, self clear
FCR_RST_TX = BIT(2), // XMIT FIFO Reset, self clear
FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty
FCR_TX_TRIG_2CH = BIT(4), // TX Empty Trigger: 2 characters in the FIFO
FCR_TX_TRIG_QF = BIT(5), // TX Empty Trigger: FIFO 1/4 full
FCR_TX_TRIG_HF = (BIT(5)|BIT(4)), // TX Empty Trigger: FIFO 1/2 full
FCR_TX_TRIG_MASK = (BIT(5)|BIT(4)), // TX Empty Trigger Bit Mask
FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO
FCR_RX_TRIG_QF = BIT(6), // RCVR Trigger: FIFO 1/4 full
FCR_RX_TRIG_HF = BIT(7), // RCVR Trigger: FIFO 1/2 full
FCR_RX_TRIG_AF = (BIT(7)|BIT(6)), // RCVR Trigger: FIFO 2 less than full
FCR_RX_TRIG_MASK = (BIT(7)|BIT(6)) // RCVR Trigger bits Mask
} LOG_UART_FIFO_CTRL;
typedef struct _HAL_LOG_UART_ADAPTER_ {
u32 BaudRate; //00
u32 FIFOControl; //+04
u32 IntEnReg; //+08
u8 Parity; //+0c
u8 Stop; //+0d
u8 DataLength; //+0e
u8 LineStatus; //+0f
volatile u32 TxCount; //+10 how many byte to TX
volatile u32 RxCount; //+14 how many bytes to RX
volatile u8 *pTxBuf; //+18
volatile u8 *pRxBuf; //+1c
u8 *pTxStartAddr; //+20
u8 *pRxStartAddr; //+24
IRQ_HANDLE IrqHandle; //+28
VOID (*LineStatusCallback)(VOID *para, u8 status); //+38 User Line Status interrupt callback
VOID (*TxCompCallback)(VOID *para); //+3c User Tx complete callback
VOID (*RxCompCallback)(VOID *para); //+40 User Rx complete callback
VOID *LineStatusCbPara; //+44 the argument for LineStatusCallback
VOID *TxCompCbPara; //+48 the argument for TxCompCallback
VOID *RxCompCbPara; //+4c the argument for RxCompCallback
void (*api_irq_handler)(u32 id, LOG_UART_INT_ID event); //+0x50
u32 api_irq_id; //+0x54
}HAL_LOG_UART_ADAPTER, *PHAL_LOG_UART_ADAPTER;
VOID HalLogUartIrqHandle(VOID * Data);
VOID HalLogUartSetBaudRate(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartSetLineCtrl(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartSetIntEn(HAL_LOG_UART_ADAPTER *pUartAdapter);
u32 HalLogUartInitSetting(HAL_LOG_UART_ADAPTER *pUartAdapter);
u32 HalLogUartRecv(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pRxData, u32 Length, u32 TimeoutMS);
u32 HalLogUartSend(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pTxData, u32 Length, u32 TimeoutMS);
HAL_Status HalLogUartIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pTxData, u32 Length);
HAL_Status HalLogUartIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter,
u8 *pRxData, u32 Length);
VOID HalLogUartAbortIntSend(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartAbortIntRecv(HAL_LOG_UART_ADAPTER *pUartAdapter);
HAL_Status HalLogUartRstFIFO(HAL_LOG_UART_ADAPTER *pUartAdapter, u8 RstCtrl);
VOID HalLogUartEnable(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartDisable(HAL_LOG_UART_ADAPTER *pUartAdapter);
VOID HalLogUartWaitTxFifoEmpty(VOID);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_MII_H_
#define _HAL_MII_H_
#include "rtl8195a_mii.h"
/**
* LOG Configurations
*/
#define NOLOG
#define LOG_TAG "NoTag"
#define LOG_INFO_HEADER "I"
#define LOG_DEBUG_HEADER "D"
#define LOG_ERROR_HEADER "E"
#define LOG_TEST_HEADER "T"
#define IDENT_TWO_SPACE " "
#define IDENT_FOUR_SPACE " "
#define LOG_INFO(...) do {\
DiagPrintf("\r"LOG_INFO_HEADER"/"LOG_TAG": " __VA_ARGS__);\
}while(0)
#define LOG_DEBUG(...) do {\
DiagPrintf("\r"LOG_DEBUG_HEADER"/"LOG_TAG": " __VA_ARGS__);\
}while(0)
#define LOG_ERROR(...) do {\
DiagPrintf("\r"LOG_ERROR_HEADER"/"LOG_TAG": " __VA_ARGS__);\
}while(0)
#ifdef NOLOG
#define LOGI
#define LOGD
#define LOGE
#define LOGI2
#define LOGD2
#define LOGE2
#define LOGI4
#define LOGD4
#define LOGE4
#else
#define LOGI LOG_INFO
#define LOGD LOG_DEBUG
#define LOGE LOG_ERROR
#define LOGI2(...) LOG_INFO(IDENT_TWO_SPACE __VA_ARGS__)
#define LOGD2(...) LOG_DEBUG(IDENT_TWO_SPACE __VA_ARGS__)
#define LOGE2(...) LOG_ERROR(IDENT_TWO_SPACE __VA_ARGS__)
#define LOGI4(...) LOG_INFO(IDENT_FOUR_SPACE __VA_ARGS__)
#define LOGD4(...) LOG_DEBUG(IDENT_FOUR_SPACE __VA_ARGS__)
#define LOGE4(...) LOG_ERROR(IDENT_FOUR_SPACE __VA_ARGS__)
#endif
#define ANSI_COLOR_GREEN "\x1b[32m"
#define ANSI_COLOR_CYAN "\x1b[36m"
#define ANSI_COLOR_YELLOW "\x1b[33m"
#define ANSI_COLOR_MAGENTA "\x1b[35m"
#define ANSI_COLOR_RED "\x1b[31m"
#define ANSI_COLOR_BLUE "\x1b[34m"
#define ANSI_COLOR_RESET "\x1b[0m"
#define DBG_ENTRANCE LOGI(ANSI_COLOR_GREEN "=> %s() <%s>\n" ANSI_COLOR_RESET, \
__func__, __FILE__)
// GMAC MII Configurations
#ifdef LOG_TAG
#undef LOG_TAG
#define LOG_TAG "MII"
#endif
typedef enum {
ETH_TXDONE,
ETH_RXDONE,
ETH_LINKUP,
ETH_LINKDOWN
}EthernetEventType;
typedef struct _HAL_ETHER_ADAPTER_{
IRQ_HANDLE IrqHandle;
u32 InterruptMask;
u8 tx_desc_num;
u8 rx_desc_num;
volatile u8 *TxDescAddr;
volatile u8 *RxDescAddr;
volatile u8 *pTxPktBuf;
volatile u8 *pRxPktBuf;
VOID (*CallBack)(u32 Event, u32 Data);
}HAL_ETHER_ADAPTER, *PHAL_ETHER_ADAPTER;
extern s32
HalMiiInit(
IN VOID
);
extern VOID
HalMiiDeInit(
IN VOID
);
extern s32
HalMiiWriteData(
IN const char *Data,
IN u32 Size
);
extern u32
HalMiiSendPacket(
IN VOID
);
extern u32
HalMiiReceivePacket(
IN VOID
);
extern u32
HalMiiReadData(
IN u8 *Data,
IN u32 Size
);
extern VOID
HalMiiGetMacAddress(
IN u8 *Addr
);
extern u32
HalMiiGetLinkStatus(
IN VOID
);
extern VOID
HalMiiForceLink(
IN s32 Speed,
IN s32 Duplex
);
#ifdef CONFIG_MII_VERIFY
typedef struct _HAL_MII_ADAPTER_ {
u32 InterruptMask;
PPHY_MODE_INFO pPhyModeInfo;
}HAL_MII_ADAPTER, *PHAL_MII_ADAPTER;
typedef struct _HAL_MII_OP_ {
BOOL (*HalMiiGmacInit)(VOID *Data);
BOOL (*HalMiiGmacReset)(VOID *Data);
BOOL (*HalMiiGmacEnablePhyMode)(VOID *Data);
u32 (*HalMiiGmacXmit)(VOID *Data);
VOID (*HalMiiGmacCleanTxRing)(VOID *Data);
VOID (*HalMiiGmacFillTxInfo)(VOID *Data);
VOID (*HalMiiGmacFillRxInfo)(VOID *Data);
VOID (*HalMiiGmacTx)(VOID *Data);
VOID (*HalMiiGmacRx)(VOID *Data);
VOID (*HalMiiGmacSetDefaultEthIoCmd)(VOID *Data);
VOID (*HalMiiGmacInitIrq)(VOID *Data);
u32 (*HalMiiGmacGetInterruptStatus)(VOID);
VOID (*HalMiiGmacClearInterruptStatus)(u32 IsrStatus);
}HAL_MII_OP, *PHAL_MII_OP;
VOID HalMiiOpInit(IN VOID *Data);
typedef struct _MII_ADAPTER_ {
PHAL_MII_OP pHalMiiOp;
PHAL_MII_ADAPTER pHalMiiAdapter;
PTX_INFO pTx_Info;
PRX_INFO pRx_Info;
VOID* TxBuffer;
VOID* RxBuffer;
}MII_ADAPTER, *PMII_ADAPTER;
#endif // #ifdef CONFIG_MII_VERIFY
#endif // #ifndef _HAL_MII_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _MISC_H_
#define _MISC_H_
#include <basic_types.h>
#define CHIP_ID_8711AM 0xFF
#define CHIP_ID_8195AM 0xFE
#define CHIP_ID_8711AF 0xFD
#define CHIP_ID_8710AF 0xFC
#define CHIP_ID_8711AN 0xFB
#define CHIP_ID_8710AM 0xFA
enum _HAL_RESET_REASON{
REASON_DEFAULT_RST = 0, /**< normal startup by power on */
REASON_WDT_RST, /**< hardware watch dog reset */
REASON_EXCEPTION_RST, /**< exception reset, GPIO status won't change */
REASON_SOFT_WDT_RST, /**< software watch dog reset, GPIO status won't change */
REASON_SOFT_RESTART, /**< software restart ,system_restart , GPIO status won't change */
REASON_DEEP_SLEEP_AWAKE, /**< wake up from deep-sleep */
REASON_EXT_SYS_RST /**< external system reset */
};
typedef u32 HAL_RESET_REASON;
#ifdef CONFIG_TIMER_MODULE
extern _LONG_CALL_ unsigned int HalDelayUs(unsigned int us);
#endif
extern _LONG_CALL_ unsigned int HalGetCpuClk(VOID);
extern _LONG_CALL_ unsigned char HalGetRomInfo(VOID);
extern u8 HalGetChipId(void);
extern _LONG_CALL_ROM_ void *_memset( void *s, int c, SIZE_T n );
extern _LONG_CALL_ROM_ void *_memcpy( void *s1, const void *s2, SIZE_T n );
#if defined(CONFIG_RELEASE_BUILD_LIBRARIES) && (!defined(E_CUT_ROM_DOMAIN))
// we built A/B/C cut ROM Lib with this wrong declaration, we need to keep the same for compatible
extern _LONG_CALL_ROM_ int *_memcmp( const void *av, const void *bv, SIZE_T len );
#else
extern _LONG_CALL_ROM_ int _memcmp( const void *av, const void *bv, SIZE_T len );
#endif
extern _LONG_CALL_ROM_ SIZE_T _strlen(const char *s);
extern _LONG_CALL_ROM_ int _strcmp(const char *cs, const char *ct);
VOID HalSetResetCause(IN HAL_RESET_REASON reason);
HAL_RESET_REASON HalGetResetCause(VOID);
#endif //_MISC_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_NFC_H_
#define _HAL_NFC_H_
#include "rtl8195a_nfc.h"
VOID HalNFCOpInit(
IN VOID *Data
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PCM_H_
#define _HAL_PCM_H_
#include "rtl8195a_pcm.h"
/*
typedef struct _GDMA_CH_LLI_ELE_ {
u32 Sarx;
u32 Darx;
u32 Llpx;
u32 CtlxLow;
u32 CtlxUp;
u32 Temp;
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
#if 1
#if 0
typedef struct _GDMA_CH_LLI_ {
PGDMA_CH_LLI_ELE pLliEle;
PGDMA_CH_LLI pNextLli;
}GDMA_CH_LLI, *PGDMA_CH_LLI;
typedef struct _BLOCK_SIZE_LIST_ {
u32 BlockSize;
PBLOCK_SIZE_LIST pNextBlockSiz;
}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
#else
struct GDMA_CH_LLI {
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pNextLli;
};
struct BLOCK_SIZE_LIST {
u32 BlockSize;
struct BLOCK_SIZE_LIST *pNextBlockSiz;
};
#endif
#endif
typedef struct _HAL_GDMA_ADAPTER_ {
u32 ChSar;
u32 ChDar;
GDMA_CHANNEL_NUM ChEn;
GDMA_CTL_REG GdmaCtl;
GDMA_CFG_REG GdmaCfg;
u32 PacketLen;
u32 BlockLen;
u32 MuliBlockCunt;
u32 MaxMuliBlock;
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
*/
typedef struct _HAL_PCM_ADAPTER_ {
u32 Enable:1;
PCM_CTL_REG PcmCtl;
PCM_CHCNR03_REG PcmChCNR03;
PCM_TSR03_REG PcmTSR03;
PCM_BSIZE03_REG PcmBSize03;
u32 abc;
u8 PcmIndex;
u8 PcmCh;
}HAL_PCM_ADAPTER, *PHAL_PCM_ADAPTER;
typedef struct _HAL_PCM_OP_ {
VOID (*HalPcmOnOff)(VOID *Data);
BOOL (*HalPcmInit)(VOID *Data);
BOOL (*HalPcmSetting)(VOID *Data);
BOOL (*HalPcmEn)(VOID *Data);
BOOL (*HalPcmIsrEnAndDis) (VOID *Data);
BOOL (*HalPcmDumpReg)(VOID *Data);
BOOL (*HalPcm)(VOID *Data);
}HAL_PCM_OP, *PHAL_PCM_OP;
VOID HalPcmOpInit(
IN VOID *Data
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PERI_ON_H_
#define _HAL_PERI_ON_H_
#define MASK_ALLON 0xFFFFFFFF
#define HAL_PERI_ON_READ32(addr) HAL_READ32(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE32(addr, value) HAL_WRITE32(PERI_ON_BASE, addr, value)
#define HAL_PERI_ON_READ16(addr) HAL_READ16(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE16(addr, value) HAL_WRITE16(PERI_ON_BASE, addr, value)
#define HAL_PERI_ON_READ8(addr) HAL_READ8(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE8(addr, value) HAL_WRITE8(PERI_ON_BASE, addr, value)
#define HAL_PERL_ON_FUNC_CTRL(addr,value,ctrl) \
HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~value))|((MASK_ALLON - ctrl + 1) & value)))
#define HAL_PERL_ON_PIN_SEL(addr,mask,value) \
HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~mask)) | value))
//40 REG_SYS_REGU_CTRL0
#define LDO25M_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_REGU_CTRL0, BIT_SYS_REGU_LDO25M_EN, ctrl)
//A0 SYS_DEBUG_CTRL
#define DEBUG_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_DEBUG_CTRL, BIT_SYS_DBG_PIN_EN, ctrl)
//A4 SYS_PINMUX_CTRL
#define SIC_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_SIC_PIN_EN, ctrl)
#define EEPROM_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_EEPROM_PIN_EN, ctrl)
//210 SOV_FUNC_EN
#define LXBUS_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LXBUS_EN, ctrl)
#define FLASH_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI_FLASH_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_FLASH_EN, ctrl);}
#define MEM_CTRL_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDR_SDRAM_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_MEM_CTRL_EN, ctrl);}
#define LOC_UART_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(LOG_UART_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LOG_UART_EN, ctrl);}
#define GDMA0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GDMA0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA0_EN, ctrl);}
#define GDMA1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GDMA1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA1_EN, ctrl);}
#define GTIMER_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(TIMER_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GTIMER_EN, ctrl);}
#define SECURITY_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(CRYPTO_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_SECURITY_ENGINE_EN, ctrl);}
//214 SOC_HCI_COM_FUNC_EN
#define SDIOD_ON_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN, ctrl);}
#define SDIOD_OFF_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN, ctrl);}
#define SDIOH_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_HOST_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN, ctrl);}
#define SDIO_ON_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_RST_MUX, ctrl)
#define OTG_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(USB_OTG_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_EN, ctrl);}
#define OTG_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_RST_MUX, ctrl)
#define MII_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(MII_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_MII_EN, ctrl);}
#define MII_MUX_SEL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SM_SEL, ctrl)
#define WL_MACON_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(WIFI_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_WL_MACON_EN, ctrl);}
//218 SOC_PERI_FUNC0_EN
#define UART0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART0_EN, ctrl);}
#define UART1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART1_EN, ctrl);}
#define UART2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART2_EN, ctrl);}
#define SPI0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI0_EN, ctrl);}
#define SPI1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI1_EN, ctrl);}
#define SPI2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI2_EN, ctrl);}
#define I2C0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C0_EN, ctrl);}
#define I2C1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C1_EN, ctrl);}
#define I2C2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C2_EN, ctrl);}
#define I2C3_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C3_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C3_EN, ctrl);}
#define I2S0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2S0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S0_EN, ctrl);}
#define I2S1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2S1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S1_EN, ctrl);}
#define PCM0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(PCM0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM0_EN, ctrl);}
#define PCM1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(PCM1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM1_EN, ctrl);}
//21C SOC_PERI_FUNC1_EN
#define ADC0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(ADC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_ADC0_EN, ctrl);}
#define DAC0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(DAC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC0_EN, ctrl);}
#define DAC1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(DAC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC1_EN, ctrl);}
#define GPIO_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GPIO_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_GPIO_EN, ctrl);}
//220 SOC_PERI_BD_FUNC0_EN
#define UART0_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART0_BD_EN, ctrl);}
#define UART1_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART1_BD_EN, ctrl);}
#define UART2_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART2_BD_EN, ctrl);}
//230 PESOC_CLK_CTRL
#define ACTCK_CPU_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_CKE_PLFM, ctrl)
#define ACTCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TRACE_EN, ctrl)
#define SLPCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TRACE_EN, ctrl)
#define ACTCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_VENDOR_REG_EN, ctrl)
#define SLPCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_VENDOR_REG_EN, ctrl)
#define ACTCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_FLASH_EN, ctrl)
#define SLPCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_FLASH_EN, ctrl)
#define ACTCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_SDR_EN, ctrl)
#define SLPCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_SDR_EN, ctrl)
#define ACTCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_LOG_UART_EN, ctrl)
#define SLPCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_LOG_UART_EN, ctrl)
#define ACTCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TIMER_EN, ctrl)
#define SLPCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TIMER_EN, ctrl)
#define ACTCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA0_EN, ctrl)
#define SLPCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA0_EN, ctrl)
#define ACTCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA1_EN, ctrl)
#define SLPCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA1_EN, ctrl)
#define ACTCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GPIO_EN, ctrl)
#define SLPCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GPIO_EN, ctrl)
#define ACTCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_BTCMD_EN, ctrl)
#define SLPCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_BTCMD_EN, ctrl)
//234 PESOC_PERI_CLK_CTRL0
#define ACTCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART0_EN, ctrl)
#define SLPCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART0_EN, ctrl)
#define ACTCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART1_EN, ctrl)
#define SLPCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART1_EN, ctrl)
#define ACTCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART2_EN, ctrl)
#define SLPCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART2_EN, ctrl)
#define ACTCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI0_EN, ctrl)
#define SLPCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI0_EN, ctrl)
#define ACTCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI1_EN, ctrl)
#define SLPCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI1_EN, ctrl)
#define ACTCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI2_EN, ctrl)
#define SLPCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI2_EN, ctrl)
//238 PESOC_PERI_CLK_CTRL1
#define ACTCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C0_EN, ctrl)
#define SLPCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C0_EN, ctrl)
#define ACTCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C1_EN, ctrl)
#define SLPCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C1_EN, ctrl)
#define ACTCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C2_EN, ctrl)
#define SLPCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C2_EN, ctrl)
#define ACTCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C3_EN, ctrl)
#define SLPCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C3_EN, ctrl)
#define ACTCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2S_EN, ctrl)
#define SLPCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2S_EN, ctrl)
#define ACTCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_PCM_EN, ctrl)
#define SLPCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_PCM_EN, ctrl)
#define ACTCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_ADC_EN, ctrl)
#define SLPCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_ADC_EN, ctrl)
#define ACTCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_DAC_EN, ctrl)
#define SLPCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_DAC_EN, ctrl)
//240 PESOC_HCI_CLK_CTRL0
#define ACTCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_DEV_EN, ctrl)
#define SLPCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_DEV_EN, ctrl)
#define ACTCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_HST_EN, ctrl)
#define SLPCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_HST_EN, ctrl)
#define ACTCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_OTG_EN, ctrl)
#define SLPCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_OTG_EN, ctrl)
#define ACTCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_MII_MPHY_EN, ctrl)
#define SLPCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_MII_MPHY_EN, ctrl)
//244 PESOC_COM_CLK_CTRL1
#define ACTCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_WL_EN, ctrl)
#define SLPCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_WL_EN, ctrl)
#define ACTCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_SECURITY_ENG_EN, ctrl)
#define SLPCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_SECURITY_ENG_EN, ctrl)
#define ACTCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_NFC_EN, ctrl)
#define SLPCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_NFC_EN, ctrl)
#define NFC_CAL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_NFC_CAL_EN, ctrl)
//250 REG_PERI_CLK_SEL
#define TRACE_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_TRACE_CK_SEL << BIT_SHIFT_PESOC_TRACE_CK_SEL), BIT_PESOC_TRACE_CK_SEL(num))
#define FLASH_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_FLASH_CK_SEL << BIT_SHIFT_PESOC_FLASH_CK_SEL), BIT_PESOC_FLASH_CK_SEL(num))
#define SDR_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_SDR_CK_SEL << BIT_SHIFT_PESOC_SDR_CK_SEL), BIT_PESOC_SDR_CK_SEL(num))
#define I2C_SCLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_PERI_SCLK_SEL << BIT_SHIFT_PESOC_PERI_SCLK_SEL), BIT_PESOC_PERI_SCLK_SEL(num))
//270 REG_OSC32K_CTRL
#define OSC32K_CKGEN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_OSC32K_CTRL, BIT_32K_POW_CKGEN_EN, ctrl)
//280 REG_UART_MUX_CTRL
#define UART0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART0_PIN_EN, ctrl)
#define UART0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART0_PIN_SEL << BIT_SHIFT_UART0_PIN_SEL), BIT_UART0_PIN_SEL(num))
#define UART1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART1_PIN_EN, ctrl)
#define UART1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART1_PIN_SEL << BIT_SHIFT_UART1_PIN_SEL), BIT_UART1_PIN_SEL(num))
#define UART2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART2_PIN_EN, ctrl)
#define UART2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART2_PIN_SEL << BIT_SHIFT_UART2_PIN_SEL), BIT_UART2_PIN_SEL(num))
//284 REG_SPI_MUX_CTRL
#define SPI0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_PIN_EN, ctrl)
#define SPI0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI0_PIN_SEL << BIT_SHIFT_SPI0_PIN_SEL), BIT_SPI0_PIN_SEL(num))
#define SPI1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI1_PIN_EN, ctrl)
#define SPI1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI1_PIN_SEL << BIT_SHIFT_SPI1_PIN_SEL), BIT_SPI1_PIN_SEL(num))
#define SPI2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI2_PIN_EN, ctrl)
#define SPI2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI2_PIN_SEL << BIT_SHIFT_SPI2_PIN_SEL), BIT_SPI2_PIN_SEL(num))
#define SPI0_MULTI_CS_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_MULTI_CS_EN, ctrl)
//288 REG_I2C_MUX_CTRL
#define I2C0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C0_PIN_EN, ctrl)
#define I2C0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C0_PIN_SEL << BIT_SHIFT_I2C0_PIN_SEL), BIT_I2C0_PIN_SEL(num))
#define I2C1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C1_PIN_EN, ctrl)
#define I2C1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C1_PIN_SEL << BIT_SHIFT_I2C1_PIN_SEL), BIT_I2C1_PIN_SEL(num))
#define I2C2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C2_PIN_EN, ctrl)
#define I2C2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C2_PIN_SEL << BIT_SHIFT_I2C2_PIN_SEL), BIT_I2C2_PIN_SEL(num))
#define I2C3_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C3_PIN_EN, ctrl)
#define I2C3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C3_PIN_SEL << BIT_SHIFT_I2C3_PIN_SEL), BIT_I2C3_PIN_SEL(num))
//28C REG_I2S_MUX_CTRL
#define I2S0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_PIN_EN, ctrl)
#define I2S0_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_MCK_EN, ctrl)
#define I2S0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S0_PIN_SEL << BIT_SHIFT_I2S0_PIN_SEL), BIT_I2S0_PIN_SEL(num))
#define I2S1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_PIN_EN, ctrl)
#define I2S1_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_MCK_EN, ctrl)
#define I2S1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S1_PIN_SEL << BIT_SHIFT_I2S1_PIN_SEL), BIT_I2S1_PIN_SEL(num))
#define PCM0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM0_PIN_EN, ctrl)
#define PCM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM0_PIN_SEL << BIT_SHIFT_PCM0_PIN_SEL), BIT_PCM0_PIN_SEL(num))
#define PCM1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM1_PIN_EN, ctrl)
#define PCM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM1_PIN_SEL << BIT_SHIFT_PCM1_PIN_SEL), BIT_PCM1_PIN_SEL(num))
//2A0 HCI_PINMUX_CTRL
#define SDIOD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN, ctrl)
#define SDIOH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN, ctrl)
#define MII_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN, ctrl)
//2A4 WL_PINMUX_CTRL
#define LED_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_LED_PIN_EN, ctrl)
#define LED_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_WL_PINMUX_CTRL, (BIT_MASK_WL_LED_PIN_SEL << BIT_SHIFT_WL_LED_PIN_SEL), BIT_WL_LED_PIN_SEL(num))
#define ANT0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT0_PIN_EN, ctrl)
#define ANT1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT1_PIN_EN, ctrl)
#define BTCOEX_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCOEX_PIN_EN, ctrl)
#define BTCMD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCMD_PIN_EN, ctrl)
#define NFC_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_NFC_PIN_EN, ctrl)
//2AC PWM_PINMUX_CTRL
#define PWM0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM0_PIN_EN, ctrl)
#define PWM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM0_PIN_SEL << BIT_SHIFT_PWM0_PIN_SEL), BIT_PWM0_PIN_SEL(num))
#define PWM1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM1_PIN_EN, ctrl)
#define PWM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM1_PIN_SEL << BIT_SHIFT_PWM1_PIN_SEL), BIT_PWM1_PIN_SEL(num))
#define PWM2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM2_PIN_EN, ctrl)
#define PWM2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM2_PIN_SEL << BIT_SHIFT_PWM2_PIN_SEL), BIT_PWM2_PIN_SEL(num))
#define PWM3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM3_PIN_EN, ctrl)
#define PWM3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM3_PIN_SEL << BIT_SHIFT_PWM3_PIN_SEL), BIT_PWM3_PIN_SEL(num))
#define ETE0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE0_PIN_EN, ctrl)
#define ETE0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE0_PIN_SEL << BIT_SHIFT_ETE0_PIN_SEL), BIT_ETE0_PIN_SEL(num))
#define ETE1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE1_PIN_EN, ctrl)
#define ETE1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE1_PIN_SEL << BIT_SHIFT_ETE1_PIN_SEL), BIT_ETE1_PIN_SEL(num))
#define ETE2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE2_PIN_EN, ctrl)
#define ETE2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE2_PIN_SEL << BIT_SHIFT_ETE2_PIN_SEL), BIT_ETE2_PIN_SEL(num))
#define ETE3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE3_PIN_EN, ctrl)
#define ETE3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE3_PIN_SEL << BIT_SHIFT_ETE3_PIN_SEL), BIT_ETE3_PIN_SEL(num))
//2C0 CPU_PERIPHERAL_CTRL
#define SPI_FLASH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SPI_FLSH_PIN_EN, ctrl)
#define SPI_FLASH_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_CPU_PERIPHERAL_CTRL, (BIT_MASK_SPI_FLSH_PIN_SEL << BIT_SHIFT_SPI_FLSH_PIN_SEL), BIT_SPI_FLSH_PIN_SEL(num))
#define SDR_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SDR_PIN_EN, ctrl)
#define TRACE_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_TRACE_PIN_EN, ctrl)
#define LOG_UART_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_PIN_EN, ctrl)
#define LOG_UART_IR_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_IR_EN, ctrl)
//300 REG_PESOC_MEM_CTRL
#define SDR_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_SDR_DDL_CTRL << BIT_SHIFT_PESOC_SDR_DDL_CTRL), BIT_PESOC_SDR_DDL_CTRL(ctrl))
#define FLASH_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_FLASH_DDL_CTRL << BIT_SHIFT_PESOC_FLASH_DDL_CTRL), BIT_PESOC_FLASH_DDL_CTRL(ctrl))
//304 REG_PESOC_SOC_CTRL
#define SRAM_MUX_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_SRAM_MUX_CFG << BIT_SHIFT_PESOC_SRAM_MUX_CFG), BIT_PESOC_SRAM_MUX_CFG(num))
#define LX_WL_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_WL_SWAP_SEL, ctrl)
#define LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_MST_SWAP_SEL, ctrl)
#define LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_SLV_SWAP_SEL, ctrl)
#define MII_LX_WRAPPER_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_WRAPPER_EN, ctrl)
#define MII_LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_MST_SWAP_SEL, ctrl)
#define MII_LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_SLV_SWAP_SEL, ctrl)
#define GDMA_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_GDMA_CFG << BIT_SHIFT_PESOC_GDMA_CFG), BIT_PESOC_GDMA_CFG(num))
//308 PESOC_PERI_CTRL
#define SPI_RN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CTRL, BIT_SOC_FUNC_SPI_RN, ctrl)
//320 GPIO_SHTDN_CTRL
#define GPIO_GPA_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPA_SHTDN_N, ctrl)
#define GPIO_GPB_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPB_SHTDN_N, ctrl)
#define GPIO_GPC_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPC_SHTDN_N, ctrl)
#define GPIO_GPD_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPD_SHTDN_N, ctrl)
#define GPIO_GPE_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPE_SHTDN_N, ctrl)
#define GPIO_GPF_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPF_SHTDN_N, ctrl)
#define GPIO_GPG_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPG_SHTDN_N, ctrl)
#define GPIO_GPH_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPH_SHTDN_N, ctrl)
#define GPIO_GPI_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPI_SHTDN_N, ctrl)
#define GPIO_GPJ_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPJ_SHTDN_N, ctrl)
#define GPIO_GPK_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPK_SHTDN_N, ctrl)
//374
#define EGTIM_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PERI_EGTIM_CTRL, BIT_PERI_EGTIM_EN, ctrl)
#define EGTIM_RSIG_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_REF_SIG_SEL << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL), BIT_PERI_EGTIM_REF_SIG_SEL(num))
#define EGTIME_PIN_G0_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(num))
#define EGTIME_PIN_G1_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(num))
#define EGTIME_PIN_G2_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(num))
#endif //_HAL_PERI_ON_H_

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#ifndef _HAL_PINMUX_
#define _HAL_PINMUX_
//Function Index
#define UART0 0
#define UART1 1
#define UART2 2
#define SPI0 8
#define SPI1 9
#define SPI2 10
#define SPI0_MCS 15
#define I2C0 16
#define I2C1 17
#define I2C2 18
#define I2C3 19
#define I2S0 24
#define I2S1 25
#define PCM0 28
#define PCM1 29
#define ADC0 32
#define DAC0 36
#define DAC1 37
#define SDIOD 64
#define SDIOH 65
#define USBOTG 66
#define MII 88
#define WL_LED 96
#define WL_ANT0 104
#define WL_ANT1 105
#define WL_BTCOEX 108
#define WL_BTCMD 109
#define NFC 112
#define PWM0 160
#define PWM1 161
#define PWM2 162
#define PWM3 163
#define ETE0 164
#define ETE1 165
#define ETE2 166
#define ETE3 167
#define EGTIM 168
#define SPI_FLASH 196
#define SDR 200
#define JTAG 216
#define TRACE 217
#define LOG_UART 220
#define LOG_UART_IR 221
#define SIC 224
#define EEPROM 225
#define DEBUG 226
//Location Index(Pin Mux Selection)
#define S0 0
#define S1 1
#define S2 2
#define S3 3
_LONG_CALL_ u8
HalPinCtrlRtl8195A(
IN u32 Function,
IN u32 PinLocation,
IN BOOL Operation);
u8 GpioFunctionChk(
IN u32 chip_pin,
IN u8 Operation);
u8
FunctionChk(
IN u32 Function,
IN u32 PinLocation
);
#endif //_HAL_PINMUX_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PLATFORM_
#define _HAL_PLATFORM_
#define ROMVERSION 0x03
#define ROMINFORMATION (ROMVERSION)
#define SYSTEM_CLK PLATFORM_CLOCK
#define PERIPHERAL_IRQ_STATUS 0x04
#define PERIPHERAL_IRQ_MODE 0x08
#define PERIPHERAL_IRQ_EN 0x0C
#define LP_PERI_EXT_IRQ_STATUS 0x24
#define LP_PERI_EXT_IRQ_MODE 0x28
#define LP_PERI_EXT_IRQ_EN 0x2C
#define PERIPHERAL_IRQ_ALL_LEVEL 0
#define TIMER_CLK 32*1000
#define SDR_SDRAM_BASE 0x30000000
#define SYSTEM_CTRL_BASE 0x40000000
#define PERI_ON_BASE 0x40000000
#define SPI_FLASH_BASE 0x98000000
//3 Peripheral IP Base Address
#define GPIO_REG_BASE 0x40001000
#define TIMER_REG_BASE 0x40002000
#define VENDOR_REG_BASE 0x40002800
#define NFC_INTERFACE_BASE 0x40002400
#define LOG_UART_REG_BASE 0x40003000
#define I2C2_REG_BASE 0x40003400
#define I2C3_REG_BASE 0x40003800
#define SDR_CTRL_BASE 0x40005000
#define SPI_FLASH_CTRL_BASE 0x40006000
#define ADC_REG_BASE 0x40010000
#define DAC_REG_BASE 0x40011000
#define UART0_REG_BASE 0x40040000
#define UART1_REG_BASE 0x40040400
#define UART2_REG_BASE 0x40040800
#define SPI0_REG_BASE 0x40042000
#define SPI1_REG_BASE 0x40042400
#define SPI2_REG_BASE 0x40042800
#define I2C0_REG_BASE 0x40044000
#define I2C1_REG_BASE 0x40044400
#define SDIO_DEVICE_REG_BASE 0x40050000
#define MII_REG_BASE 0x40050000
#define SDIO_HOST_REG_BASE 0x40058000
#define GDMA0_REG_BASE 0x40060000
#define GDMA1_REG_BASE 0x40061000
#define I2S0_REG_BASE 0x40062000
#define I2S1_REG_BASE 0x40063000
#define PCM0_REG_BASE 0x40064000
#define PCM1_REG_BASE 0x40065000
#define CRYPTO_REG_BASE 0x40070000
#define WIFI_REG_BASE 0x40080000
#define USB_OTG_REG_BASE 0x400C0000
#define GDMA1_REG_OFF 0x1000
#define I2S1_REG_OFF 0x1000
#define PCM1_REG_OFF 0x1000
#define SSI_REG_OFF 0x400
#define RUART_REG_OFF 0x400
#define CPU_CLK_TYPE_NO 6
enum _BOOT_TYPE_ {
BOOT_FROM_FLASH = 0,
BOOT_FROM_SDIO = 1,
BOOT_FROM_USB = 2,
BOOT_FROM_RSVD = 3,
};
enum _EFUSE_CPU_CLK_ {
#if 1
CLK_200M = 0,
CLK_100M = 1,
CLK_50M = 2,
CLK_25M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#else
CLK_25M = 0,
CLK_200M = 1,
CLK_100M = 2,
CLK_50M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#endif
};
#endif //_HAL_PLATFORM_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PWM_H_
#define _HAL_PWM_H_
#include "basic_types.h"
#define MAX_PWM_CTRL_PIN 4
// the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T)
//#define GTIMER_TICK_US 31 // micro-second, 1000000/32768 ~= 30.5
#define MIN_GTIMER_TIMEOUT 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
#define PWM_GTIMER_TICK_TIME 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
typedef struct _HAL_PWM_ADAPTER_ {
u8 pwm_id; // the PWM ID, 0~3
u8 sel; // PWM Pin selection, 0~3
u8 gtimer_id; // using G-Timer ID, there are 7 G-timer, but we prefer to use timer 3~6
u8 enable; // is enabled
// u32 timer_value; // the G-Timer auto-reload value, source clock is 32768Hz, reload will takes extra 1 tick. To set the time of a tick of PWM
u32 tick_time; // the tick time for the G-timer
u32 period; // the period of a PWM control cycle, in PWM tick
u32 pulsewidth; // the pulse width in a period of a PWM control cycle, in PWM tick. To control the ratio
// float duty_ratio; // the dyty ratio = pulswidth/period
}HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER;
extern HAL_Status
HAL_Pwm_Init(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 pwm_id,
u32 sel
);
extern void
HAL_Pwm_Enable(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_SetDuty(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SDIO_H_
#define _HAL_SDIO_H_
#include "rtl8195a_sdio.h"
#if SDIO_API_DEFINED
#include "spdio_api.h"
#endif
#if !SDIO_BOOT_DRIVER
#include "mailbox.h"
#endif
#define PURE_SDIO_INIC 0 // is a pure SDIO iNIC device or a SDIO iNIC + peripheral device
#if SDIO_BOOT_DRIVER
typedef struct _HAL_SDIO_ADAPTER_ {
u8 *pTXBDAddr; /* The TX_BD start address */
PSDIO_TX_BD pTXBDAddrAligned; /* The TX_BD start address, it must be 4-bytes aligned */
PSDIO_TX_BD_HANDLE pTXBDHdl; /* point to the allocated memory for TX_BD Handle array */
u16 TXBDWPtr; /* The SDIO TX(Host->Device) BD local write index, different with HW maintained write Index. */
u16 TXBDRPtr; /* The SDIO TX(Host->Device) BD read index */
u16 TXBDRPtrReg; /* The SDIO TX(Host->Device) BD read index has been write to HW register */
u16 reserve1;
u8 *pRXBDAddr; /* The RX_BD start address */
PSDIO_RX_BD pRXBDAddrAligned; /* The RX_BD start address, it must be 8-bytes aligned */
PSDIO_RX_BD_HANDLE pRXBDHdl; /* point to the allocated memory for RX_BD Handle array */
u16 RXBDWPtr; /* The SDIO RX(Device->Host) BD write index */
u16 RXBDRPtr; /* The SDIO RX(Device->Host) BD local read index, different with HW maintained Read Index. */
u16 IntMask; /* The Interrupt Mask */
u16 IntStatus; /* The Interrupt Status */
u32 Events; /* The Event to the SDIO Task */
u32 EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */
u8 CCPWM; /* the value write to register CCPWM, which will sync to Host HCPWM */
u8 reserve2;
u16 CCPWM2; /* the value write to register CCPWM2, which will sync to Host HCPWM2 */
s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); /* to hook the WLan driver TX callback function to handle a Packet TX */
VOID *pTxCb_Adapter; /* a pointer will be used to call the TX Callback function,
which is from the TX CallBack function register */
s8 (*pTxCallback_Backup)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); // Use to back up the registered TX Callback function, for MP/Normal mode switch
VOID *pTxCb_Adapter_Backup; // Backup the pTxCb_Adapter, for MP/Normal mode switch
_LIST FreeTxPktList; /* The list to queue free Tx packets handler */
_LIST RxPktList; /* The list to queue RX packets */
_LIST FreeRxPktList; /* The list to queue free Rx packets handler */
SDIO_TX_PACKET *pTxPktHandler; /* to store allocated TX Packet handler memory address */
SDIO_RX_PACKET *pRxPktHandler; /* to store allocated RX Packet handler memory address */
u32 RxInQCnt; /* The packet count for Rx In Queue */
u32 MemAllocCnt; // Memory allocated count, for debug only
u32 MAllocFailedCnt; // MemAlloc Failed count, for debugging
// VOID *pHalOp; /* point to HAL operation function table */
} HAL_SDIO_ADAPTER, *PHAL_SDIO_ADAPTER;
extern BOOL SDIO_Device_Init_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Device_DeInit_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Send_C2H_IOMsg_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 *C2HMsg
);
extern u8 SDIO_Send_C2H_PktMsg_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u8 *C2HMsg,
IN u16 MsgLen
);
extern VOID SDIO_Register_Tx_Callback_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize),
IN VOID *pAdapter
);
extern s8 SDIO_Rx_Callback_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN VOID *pData,
IN u16 Offset,
IN u16 Length,
IN u8 CmdType
);
#else // else of "#if SDIO_BOOT_DRIVER"
typedef struct _HAL_SDIO_ADAPTER_ {
// u8 *pTxBuff; /* point to the SDIO TX Buffer */
// u8 *pTxBuffAligned; /* point to the SDIO TX Buffer with 4-bytes aligned */
// u32 TXFifoRPtr; /* The SDIO TX(Host->Device) FIFO buffer read pointer */
#if SDIO_API_DEFINED
VOID *spdio_priv; /*Data from User*/
#endif
u8 *pTXBDAddr; /* The TX_BD start address */
PSDIO_TX_BD pTXBDAddrAligned; /* The TX_BD start address, it must be 4-bytes aligned */
PSDIO_TX_BD_HANDLE pTXBDHdl; /* point to the allocated memory for TX_BD Handle array */
u16 TXBDWPtr; /* The SDIO TX(Host->Device) BD local write index, different with HW maintained write Index. */
u16 TXBDRPtr; /* The SDIO TX(Host->Device) BD read index */
u16 TXBDRPtrReg; /* The SDIO TX(Host->Device) BD read index has been write to HW register */
u8 *pRXBDAddr; /* The RX_BD start address */
PSDIO_RX_BD pRXBDAddrAligned; /* The RX_BD start address, it must be 8-bytes aligned */
PSDIO_RX_BD_HANDLE pRXBDHdl; /* point to the allocated memory for RX_BD Handle array */
u16 RXBDWPtr; /* The SDIO RX(Device->Host) BD write index */
u16 RXBDRPtr; /* The SDIO RX(Device->Host) BD local read index, different with HW maintained Read Index. */
u16 IntMask; /* The Interrupt Mask */
u16 IntStatus; /* The Interrupt Status */
u32 Events; /* The Event to the SDIO Task */
u8 CCPWM; /* the value write to register CCPWM, which will sync to Host HCPWM */
u8 reserve1;
u16 CCPWM2; /* the value write to register CCPWM2, which will sync to Host HCPWM2 */
u8 CRPWM; /* sync from Host HRPWM */
u8 reserve2;
u16 CRPWM2; /* sync from Host HRPWM2 */
#if !TASK_SCHEDULER_DISABLED
_Sema TxSema; /* Semaphore for SDIO TX, use to wakeup the SDIO TX task */
_Sema RxSema; /* Semaphore for SDIO RX, use to wakeup the SDIO RX task */
#else
u32 EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */
#endif
s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize, u8 type); /* to hook the WLan driver TX callback function to handle a Packet TX */
VOID *pTxCb_Adapter; /* a pointer will be used to call the TX Callback function,
which is from the TX CallBack function register */
#if SDIO_API_DEFINED
s8 (*Rx_Done_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize, u8 type); /* to hook RX done callback function to release packet */
VOID *pRxDoneCb_Adapter; /* a pointer will be used to call the RX Done Callback function,
which is from the TX CallBack function register */
#endif
s8 (*pTxCallback_Backup)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize, u8 type); // Use to back up the registered TX Callback function, for MP/Normal mode switch
VOID *pTxCb_Adapter_Backup; // Backup the pTxCb_Adapter, for MP/Normal mode switch
#if SDIO_DEBUG
_LIST FreeTxPktList; /* The list to queue free Tx packets handler */
SDIO_TX_PACKET *pTxPktHandler; /* to store allocated TX Packet handler memory address */
#endif
_LIST RxPktList; /* The list to queue RX packets */
_LIST FreeRxPktList; /* The list to queue free Rx packets handler */
// _LIST RecyclePktList; /* The list to queue packets handler to be recycled */
SDIO_RX_PACKET *pRxPktHandler; /* to store allocated RX Packet handler memory address */
_Mutex RxMutex; /* The Mutex to protect RxPktList */
u32 RxInQCnt; /* The packet count for Rx In Queue */
#if SDIO_DEBUG
_Mutex StatisticMutex; /* The Mutex to protect Statistic data */
u32 MemAllocCnt; // Memory allocated count, for debug only
u32 MAllocFailedCnt; // MemAlloc Failed count, for debugging
#endif
VOID *pHalOp; /* point to HAL operation function table */
RTL_MAILBOX *pMBox; /* the Mail box for other driver module can send message to SDIO driver */
#ifdef PLATFORM_FREERTOS
xTaskHandle xSDIOTxTaskHandle; /* The handle of the SDIO Task for TX, can be used to delte the task */
xTaskHandle xSDIORxTaskHandle; /* The handle of the SDIO Task speical for RX, can be used to delte the task */
#endif
u8 RxFifoBusy; /* is the RX BD fetch hardware busy */
#if SDIO_MP_MODE
#if !TASK_SCHEDULER_DISABLED
u32 MP_Events; /* The Event to the SDIO Task */
_Sema MP_EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */
RTL_MAILBOX *pMP_MBox; /* the Mail box for communication with other driver module */
#ifdef PLATFORM_FREERTOS
xTaskHandle MP_TaskHandle; /* The handle of the MP loopback Task, can be used to delte the task */
#endif // end of "#ifdef PLATFORM_FREERTOS"
#endif // end of "#if !TASK_SCHEDULER_DISABLED"
// for MP mode
RTL_TIMER *pPeriodTimer; /* a timer to calculate throughput periodically */
u8 MP_ModeEn; /* is in MP mode */
u8 MP_LoopBackEn; /* is loop-back enabled */
u8 MP_ContinueTx; /* is continue TX test enabled */
u8 MP_ContinueRx; /* is continue RX test enabled */
u8 MP_ContinueRxMode; /* continue RX test mode: static RX Buf, Dyna-Allocate RX Buf, Pre-Allocate RX Buf */
u8 MP_CRxInfinite; /* is non-stop SDIO RX, no packet count limit */
u16 MP_CRxSize; /* SDIO RX test packet size */
u8 *pMP_CRxBuf; // the buffer for continye RX test
u32 MP_CRxPktCnt; /* SDIO RX test packet count */
u32 MP_CRxPktPendingCnt; /* SDIO RX test packet pening count */
u32 MP_TxPktCnt; /* SDIO TX packet count */
u32 MP_RxPktCnt; /* SDIO RX packet count */
u32 MP_TxByteCnt; /* SDIO TX Byte count */
u32 MP_RxByteCnt; /* SDIO RX Byte count */
u32 MP_TxDropCnt; /* SDIO TX Drop packet count */
u32 MP_RxDropCnt; /* SDIO RX Drop packet count */
u32 MP_TxPktCntInPeriod; /* SDIO TX packet count in a period */
u32 MP_RxPktCntInPeriod; /* SDIO RX packet count in a period */
u32 MP_TxByteCntInPeriod; /* SDIO TX Byte count in a period */
u32 MP_RxByteCntInPeriod; /* SDIO RX Byte count in a period */
u32 MP_TxAvgTPWin[SDIO_AVG_TP_WIN_SIZE]; /* a window of SDIO TX byte count history, for average throughput calculation */
u32 MP_RxAvgTPWin[SDIO_AVG_TP_WIN_SIZE]; /* a window of SDIO RX byte count history, for average throughput calculation */
u32 MP_TxAvgTPWinSum; /* The sum of all byte-count in the window */
u32 MP_RxAvgTPWinSum; /* The sum of all byte-count in the window */
u8 OldestTxAvgWinIdx; /* the index of the oldest TX byte count log */
u8 TxAvgWinCnt; /* the number of log in the Window */
u8 OldestRxAvgWinIdx; /* the index of the oldest RX byte count log */
u8 RxAvgWinCnt; /* the number of log in the Window */
_LIST MP_RxPktList; /* The list to queue RX packets, for MP loopback test */
#endif // end of '#if SDIO_MP_MODE'
} HAL_SDIO_ADAPTER, *PHAL_SDIO_ADAPTER;
#endif // end of "#else of "#if SDIO_BOOT_DRIVER""
typedef struct _HAL_SDIO_OP_ {
BOOL (*HalSdioDevInit)(PHAL_SDIO_ADAPTER pSDIODev);
VOID (*HalSdioDevDeInit)(PHAL_SDIO_ADAPTER pSDIODev);
VOID (*HalSdioSendC2HIOMsg)(PHAL_SDIO_ADAPTER pSDIODev, u32 *C2HMsg);
u8 (*HalSdioSendC2HPktMsg)(PHAL_SDIO_ADAPTER pSDIODev, u8 *C2HMsg, u16 MsgLen);
VOID (*HalSdioRegTxCallback)(PHAL_SDIO_ADAPTER pSDIODev,s8 (*CallbackFun)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize, u8 Type), VOID *pAdapter);
s8 (*HalSdioRxCallback)(PHAL_SDIO_ADAPTER pSDIODev, VOID *pData, u16 Offset, u16 PktSize, u8 CmdType);
#if SDIO_API_DEFINED
VOID (*HalSdioRegRxDoneCallback)(PHAL_SDIO_ADAPTER pSDIODev,s8 (*CallbackFun)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize, u8 Type), VOID *pAdapter);
#endif
#if SDIO_MP_MODE
VOID (*HalSdioDevMPApp)(PHAL_SDIO_ADAPTER pSDIODev, u16 argc, u8 *argv[]);
#endif
}HAL_SDIO_OP, *PHAL_SDIO_OP;
extern BOOL SDIO_Device_Init(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Device_DeInit(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Send_C2H_IOMsg(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 *C2HMsg
);
extern u8 SDIO_Send_C2H_PktMsg(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u8 *C2HMsg,
IN u16 MsgLen
);
extern VOID SDIO_Register_Tx_Callback(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize, u8 Type),
IN VOID *pAdapter
);
#if SDIO_API_DEFINED
extern VOID SDIO_Register_Rx_Done_Callback(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN s8 (*Rx_Done_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize, u8 Type),
IN VOID *pAdapter
);
#endif
extern s8 SDIO_Rx_Callback(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN VOID *pData,
IN u16 Offset,
IN u16 Length,
IN u8 CmdType
);
#if SDIO_MP_MODE
extern VOID SDIO_DeviceMPApp(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u16 argc,
IN u8 *argv[]
);
#endif
extern PHAL_SDIO_ADAPTER pgSDIODev;
extern VOID HalSdioInit(VOID);
extern VOID HalSdioDeInit(VOID);
#endif // #ifndef _HAL_SDIO_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SDIO_HOST_H_
#define _HAL_SDIO_HOST_H_
#include "rtl8195a_sdio_host.h"
#define SDIO_HOST_WAIT_FOREVER 0xFFFFFFFF
typedef struct _HAL_SDIO_HOST_OP_ {
HAL_Status (*HalSdioHostInitHost) (VOID *Data);
HAL_Status (*HalSdioHostInitCard) (VOID *Data);
HAL_Status (*HalSdioHostDeInit) (VOID *Data);
HAL_Status (*HalSdioHostRegIrq) (VOID *Data);
HAL_Status (*HalSdioHostReadBlocksDma) (VOID *Data, u64 ReadAddr, u32 BlockCnt);
HAL_Status (*HalSdioHostWriteBlocksDma) (VOID *Data, u64 WriteAddr, u32 BlockCnt);
HAL_Status (*HalSdioHostStopTransfer) (VOID *Data);
HAL_Status (*HalSdioHostGetCardStatus) (VOID *Data);
HAL_Status (*HalSdioHostGetSdStatus) (VOID *Data);
HAL_Status (*HalSdioHostChangeSdClock) (VOID *Data, u8 Frequency);
HAL_Status (*HalSdioHostErase) (VOID *Data, u64 StartAddr, u64 EndAddr);
HAL_Status (*HalSdioHostGetWriteProtect) (VOID *Data);
HAL_Status (*HalSdioHostSetWriteProtect) (VOID *Data, u8 Setting);
}HAL_SDIO_HOST_OP, *PHAL_SDIO_HOST_OP;
// SDIO error type
typedef enum _SDIO_ERR_TYPE_ {
SDIO_ERR_DAT_CRC = 0x01,
SDIO_ERR_CMD_TIMEOUT = 0x02,
}SDIO_ERR_TYPE;
typedef enum _SDIO_XFER_TYPE_{
SDIO_XFER_NOR = 0x00, // normal
SDIO_XFER_R = 0x01, // read and write block
SDIO_XFER_W = 0x02, // read and write block
}SDIO_XFER_TYPE;
typedef struct _HAL_SDIO_HOST_ADAPTER_{
IRQ_HANDLE IrqHandle; //+0..6(u32) Irq Handler
ADMA2_DESC_FMT *AdmaDescTbl; //+7(u32)
u32 Response[4]; //+8..11(u32)
u32 CardOCR; //+12
u32 CardStatus; //+13
u32 IsWriteProtect; //+14
u8 SdStatus[SD_STATUS_LEN]; //+15..
u8 Csd[CSD_REG_LEN]; //+31
volatile u8 CmdCompleteFlg;
volatile u8 XferCompleteFlg;
volatile u8 ErrIntFlg;
volatile u8 CardCurState;
u8 IsSdhc;
u8 CurrSdClk; //+133?
u16 RCA;
u16 SdSpecVer;
SDIO_ERR_TYPE errType;
SDIO_XFER_TYPE XferType;
VOID (*XferCompCallback)(VOID *pAdapter);
VOID *XferCompCbPara;
VOID (*ErrorCallback)(VOID *pAdapter);
VOID *ErrorCbPara;
VOID (*CardInsertCallBack)(VOID *pAdapter);
VOID *CardInsertCbPara;
VOID (*CardRemoveCallBack)(VOID *pAdapter);
VOID *CardRemoveCbPara;
}HAL_SDIO_HOST_ADAPTER, *PHAL_SDIO_HOST_ADAPTER;
extern HAL_SDIO_HOST_ADAPTER SdioHostAdapter;
extern HAL_Status
HalSdioHostInit(
IN VOID *Data
);
extern HAL_Status
HalSdioHostDeInit(
IN VOID *Data
);
extern HAL_Status
HalSdioHostEnable(
IN VOID *Data
);
extern HAL_Status
HalSdioHostDisable(
IN VOID *Data
);
extern VOID
HalSdioHostOpInit(
IN VOID *Data
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SDR_CONTROLLER_H_
#define _HAL_SDR_CONTROLLER_H_
#if 1 //def CONFIG_SDR_EN
typedef enum _DRAM_TYPE_ {
DRAM_DDR_1 = 1,
DRAM_DDR_2 = 2,
DRAM_DDR_3 = 3,
DRAM_DDR_4 = 4,
DRAM_SDR = 8
}DRAM_TYPE;
typedef enum _DRAM_COLADDR_WTH_ {
DRAM_COLADDR_8B = 0,
DRAM_COLADDR_9B = 1,
DRAM_COLADDR_10B = 2,
DRAM_COLADDR_11B = 3,
DRAM_COLADDR_12B = 4,
DRAM_COLADDR_13B = 5,
DRAM_COLADDR_14B = 6,
DRAM_COLADDR_15B = 7,
DRAM_COLADDR_16B = 8
}DRAM_COLADDR_WTH;
typedef enum _DRAM_BANK_SIZE_ {
DRAM_BANK_2 = 0,
DRAM_BANK_4 = 1,
DRAM_BANK_8 = 2
}DRAM_BANK_SIZE;
typedef enum _DRAM_DQ_WIDTH_ {
DRAM_DQ_16 = 0,
DRAM_DQ_32 = 1,
DRAM_HALF_DQ32 = 2
}DRAM_DQ_WIDTH;
typedef enum _MODE0_BST_LEN_ {
BST_LEN_4 = 0,
BST_LEN_FLY = 1,
BST_LEN_8 = 2
}MODE0_BST_LEN;
typedef enum _MODE0_BST_TYPE_ {
SENQUENTIAL = 0,
INTERLEAVE = 1
}MODE0_BST_TYPE;
typedef enum _DFI_RATIO_TYPE_ {
DFI_RATIO_1 = 0, // DFI= 1:1, or SDR
DFI_RATIO_2 = 1,
DFI_RATIO_4 = 2
}DFI_RATIO_TYPE;
typedef struct _DRAM_INFO_ {
DRAM_TYPE DeviceType;
DRAM_COLADDR_WTH ColAddrWth;
DRAM_BANK_SIZE Bank;
DRAM_DQ_WIDTH DqWidth;
}DRAM_INFO;
typedef struct _DRAM_MODE_REG_INFO_ {
MODE0_BST_LEN BstLen;
MODE0_BST_TYPE BstType;
//enum mode0_cas rd_cas;
u32 Mode0Cas;
u32 Mode0Wr;
u32 Mode1DllEnN;
u32 Mode1AllLat;
u32 Mode2Cwl;
}DRAM_MODE_REG_INFO;
typedef struct _DRAM_TIMING_INFO_ {
u32 TrfcPs;
u32 TrefiPs;
u32 WrMaxTck;
u32 TrcdPs;
u32 TrpPs;
u32 TrasPs;
u32 TrrdTck;
u32 TwrPs;
u32 TwtrTck;
//u32 TrtpPs;
u32 TmrdTck;
u32 TrtpTck;
u32 TccdTck;
u32 TrcPs;
}DRAM_TIMING_INFO;
typedef struct _DRAM_DEVICE_INFO_ {
DRAM_INFO *Dev;
DRAM_MODE_REG_INFO *ModeReg;
DRAM_TIMING_INFO *Timing;
u32 DdrPeriodPs;
DFI_RATIO_TYPE *DfiRate;
} DRAM_DEVICE_INFO, *PDRAM_DEVICE_INFO;
//======================================================
//DRAM Info
#ifdef CONFIG_FPGA
#define DRAM_INFO_TYPE DRAM_SDR
#define DRAM_INFO_COL_ADDR_WTH DRAM_COLADDR_9B
#define DRAM_INFO_BANK_SZ DRAM_BANK_4
#define DRAM_INFO_DQ_WTH DRAM_DQ_16
#else
#define DRAM_INFO_TYPE DRAM_SDR
#define DRAM_INFO_COL_ADDR_WTH DRAM_COLADDR_8B
#define DRAM_INFO_BANK_SZ DRAM_BANK_2
#define DRAM_INFO_DQ_WTH DRAM_DQ_16
#endif
//======================================================
//DRAM Timing
#ifdef CONFIG_SDR_100MHZ
#define DRAM_TIMING_TCK 10000 //ps
#endif
#ifdef CONFIG_SDR_50MHZ
#define DRAM_TIMING_TCK 20000 //ps
#endif
#ifdef CONFIG_SDR_25MHZ
#define DRAM_TIMING_TCK 40000 //ps
#endif
#ifdef CONFIG_SDR_12_5MHZ
#define DRAM_TIMING_TCK 80000 //ps
#endif
#if 1
#define DRAM_TIMING_TREF 64000 //us
#define DRAM_ROW_NUM 8192 //depends on row bit number
#define DRAM_TIMING_TRFC 60000 //ps
#define DRAM_TIMING_TREFI ((u32)((DRAM_TIMING_TREF*1000)/DRAM_ROW_NUM)*1000) //ps
#define DRAM_TIMING_TWRMAXTCK 2 //tck
#define DRAM_TIMING_TRCD 15000 //ps
#define DRAM_TIMING_TRP 15000 //ps
#define DRAM_TIMING_TRAS 42000 //ps
#define DRAM_TIMING_TRRD 2 //tck
#define DRAM_TIMING_TWR ((u32)(DRAM_TIMING_TCK*2))
#define DRAM_TIMING_TWTR 0 //tck
#define DRAM_TIMING_TMRD 2 //tck
#define DRAM_TIMING_TRTP 0 //tck
#define DRAM_TIMING_TCCD 1 //tck
#define DRAM_TIMING_TRC 60000 //ps
#else
#define DRAM_TIMING_TREF 66000 //us
#define DRAM_ROW_NUM 8192 //depends on row bit number
#define DRAM_TIMING_TRFC 66000 //ps
#define DRAM_TIMING_TREFI 63999800
#define DRAM_TIMING_TWRMAXTCK 2 //tck
#define DRAM_TIMING_TRCD 15000 //ps
#define DRAM_TIMING_TRP 15000 //ps
#define DRAM_TIMING_TRAS 37000 //ps
#define DRAM_TIMING_TRRD 2 //tck
#define DRAM_TIMING_TWR 7000
#define DRAM_TIMING_TWTR 0 //tck
#define DRAM_TIMING_TMRD 2 //tck
#define DRAM_TIMING_TRTP 0 //tck
#define DRAM_TIMING_TCCD 1 //tck
#define DRAM_TIMING_TRC 60000 //ps
#endif
#define HAL_SDR_WRITE32(addr, value32) HAL_WRITE32(SDR_CTRL_BASE, addr, value32)
#define HAL_SDR_WRITE16(addr, value16) HAL_WRITE16(SDR_CTRL_BASE, addr, value16)
#define HAL_SDR_WRITE8(addr, value8) HAL_WRITE8(SDR_CTRL_BASE, addr, value8)
#define HAL_SDR_READ32(addr) HAL_READ32(SDR_CTRL_BASE, addr)
#define HAL_SDR_READ16(addr) HAL_READ16(SDR_CTRL_BASE, addr)
#define HAL_SDR_READ8(addr) HAL_READ8(SDR_CTRL_BASE, addr)
#define HAL_SDRAM_WRITE32(addr, value32) HAL_WRITE32(SDR_SDRAM_BASE, addr, value32)
#define HAL_SDRAM_WRITE16(addr, value16) HAL_WRITE16(SDR_SDRAM_BASE, addr, value16)
#define HAL_SDRAM_WRITE8(addr, value8) HAL_WRITE8(SDR_SDRAM_BASE, addr, value8)
#define HAL_SDRAM_READ32(addr) HAL_READ32(SDR_SDRAM_BASE, addr)
#define HAL_SDRAM_READ16(addr) HAL_READ16(SDR_SDRAM_BASE, addr)
#define HAL_SDRAM_READ8(addr) HAL_READ8(SDR_SDRAM_BASE, addr)
#endif // CONFIG_SDR_EN
//extern unsigned int rand_x;
#endif // end of "#ifndef _HAL_SDR_CONTROLLER_H_"

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#ifndef _HAL_SOCPWR_
#define _HAL_SOCPWR_
#define MAX_BACKUP_SIZE 129
#define MAXFUNC 10
#define FSTREG 0xFF
#define REG_VDR_ANACK_CAL_CTRL 0xA0
#define PS_MASK 0xFFFFFFFF
//pwr state
#define HWACT 0
#define HWCG 1
#define HWINACT 2
#define UNDEF 3
#define ALLMET 0xff
//SLP
#define SLP_STIMER BIT0
#define SLP_GTIMER BIT1
#define SLP_GPIO BIT2
#define SLP_WL BIT3
#define SLP_NFC BIT4
#define SLP_SDIO BIT5
#define SLP_USB BIT6
#define SLP_TIMER33 BIT7
//DSTBY
#define DSTBY_STIMER BIT0
#define DSTBY_NFC BIT1
#define DSTBY_TIMER33 BIT2
#define DSTBY_GPIO BIT3
//DS wake event
#define DS_TIMER33 BIT0
#define DS_GPIO BIT1
enum power_state_idx{
ACT = 0,
WFE,
WFI,
SNOOZE,
SLPCG,
SLPPG,
DSTBY,
DSLP,
INACT,
MAXSTATE
};
enum clk_idx{
ANACK = 0,
A33CK = 1,
};
typedef struct _power_state_{
u8 FuncIdx;
u8 PowerState;
}POWER_STATE, *pPOWER_STATE;
typedef struct _reg_power_state_{
u8 FuncIdx;
u8 PwrState;
}REG_POWER_STATE, *pPREG_POWER_STATE;
#if 0
typedef struct _power_state_{
u8 FuncIdx;
u8 PowerState;
u32 ReqDuration;
u32 RegCount;
u32 RemainDuration;
}POWER_STATE, *pPOWER_STATE;
typedef struct _reg_power_state_{
u8 FuncIdx;
u8 PwrState;
u32 ReqDuration;
//u8 StateIdx;
}REG_POWER_STATE, *pPREG_POWER_STATE;
#endif
typedef struct _power_mgn_{
u8 ActFuncCount;
POWER_STATE PwrState[MAXFUNC];
u8 CurrentState;
u8 SDREn;
u32 MSPbackup[MAX_BACKUP_SIZE];
u32 CPURegbackup[25];
u32 CPUPSP;
u32 WakeEventFlag;
BOOL SleepFlag;
//u32 CPUReg[13];
//u32 MSBackUp[128];
}Power_Mgn, *pPower_Mgn;
typedef struct _SYS_ADAPTER_ {
u8 function;
}SYS_ADAPTER, *PSYS_ADAPTER;
extern Power_Mgn PwrAdapter;
u8 ChangeSoCPwrState(
IN u8 RequestState,
IN u32 ReqCount
);
VOID PrintCPU(VOID);
void WakeFromSLPPG(void);
VOID SOCPSTestApp(VOID *Data);
__inline static VOID
CPURegBackUp(
VOID
)
{
#if defined (__ICCARM__)
// TODO: IAR has different way using assembly
#elif defined (__GNUC__)
//backup cpu reg
#if 0
asm volatile
(
"PUSH {PSR, PC, LR, R12,R3,R2,R1,R0}\n"
);
#endif
#if 0
asm volatile
(
"PUSH {r0,r1,r2,r3,r4}\n"
);
#endif
asm volatile
(
"MOV %0, r0\n"
:"=r"(PwrAdapter.CPURegbackup[0])
::"memory"
);
asm volatile
(
"MOV %0, r1\n"
:"=r"(PwrAdapter.CPURegbackup[1])
::"memory"
);
asm volatile
(
"MOV %0, r2\n"
:"=r"(PwrAdapter.CPURegbackup[2])
::"memory"
);
asm volatile
(
"MOV %0, r3\n"
:"=r"(PwrAdapter.CPURegbackup[3])
::"memory"
);
asm volatile
(
"MOV %0, r4\n"
:"=r"(PwrAdapter.CPURegbackup[4])
::"memory"
);
asm volatile
(
"MOV %0, r5\n"
:"=r"(PwrAdapter.CPURegbackup[5])
::"memory"
);
asm volatile
(
"MOV %0, r6\n"
:"=r"(PwrAdapter.CPURegbackup[6])
::"memory"
);
asm volatile
(
"MOV %0, r7\n"
:"=r"(PwrAdapter.CPURegbackup[7])
::"memory"
);
asm volatile
(
"MOV %0, r8\n"
:"=r"(PwrAdapter.CPURegbackup[8])
::"memory"
);
asm volatile
(
"MOV %0, r9\n"
:"=r"(PwrAdapter.CPURegbackup[9])
::"memory"
);
asm volatile
(
"MOV %0, r10\n"
:"=r"(PwrAdapter.CPURegbackup[10])
::"memory"
);
asm volatile
(
"MOV %0, r11\n"
:"=r"(PwrAdapter.CPURegbackup[11])
::"memory"
);
asm volatile
(
"MOV %0, r12\n"
:"=r"(PwrAdapter.CPURegbackup[12])
::"memory"
);
asm volatile
(
"MOV %0, r13\n"
:"=r"(PwrAdapter.CPURegbackup[13])
::"memory"
);
asm volatile
(
//"MOV %0, r14\n"
"LDR %0, =SLPPG_WAKEUP_POINT\n"
"ADD %0, #1\n"
:"=r"(PwrAdapter.CPURegbackup[14])
::"memory"
);
asm volatile
(
"LDR %0, =SLPPG_WAKEUP_POINT\n"
"ADD %0, #1\n"
:"=r"(PwrAdapter.CPURegbackup[15])
::"memory"
);
asm volatile
(
"MRS %0, PSR\n"
:"=r"(PwrAdapter.CPURegbackup[16])
::"memory"
);
#if 1
asm volatile
(
"mov %0, r13\n"
"MOV %1, PC\n"
"MRS %2, CONTROL\n"
"MRS %3, PSP\n"
"MRS %4, MSP\n"
:"=r"(PwrAdapter.CPURegbackup[24]),"=r"(PwrAdapter.CPURegbackup[23]),"=r"(PwrAdapter.CPURegbackup[22]),"=r"(PwrAdapter.CPURegbackup[21]),"=r"(PwrAdapter.CPURegbackup[20])
::"memory"
);
#endif
#ifdef CONFIG_SOC_PS_VERIFY
PrintCPU();
#endif //#ifdef CONFIG_SOC_PS_VERIFY
#endif //#elif defined (__GNUC__)
}
extern VOID RegPowerState(REG_POWER_STATE RegPwrState);
extern VOID QueryRegPwrState( IN u8 FuncIdx, OUT u8* RegState, OUT u8* HwState);
#endif //_HAL_SOCPWR_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SPIFLASH__
#define _HAL_SPIFLASH__
//======================================================
// Header files
#define SPIC_CALIBRATION_IN_NVM 1 // if store the SPIC calibration data in the NVM
#ifndef CONFIG_IMAGE_SEPARATE // Store SPIC Calibration only for seprated image
#undef SPIC_CALIBRATION_IN_NVM
#define SPIC_CALIBRATION_IN_NVM 0
#endif
//======================================================
// Definition
#define HAL_SPI_WRITE32(addr, value32) HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32)
#define HAL_SPI_WRITE16(addr, value16) HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16)
#define HAL_SPI_WRITE8(addr, value8) HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8)
#define HAL_SPI_READ32(addr) HAL_READ32(SPI_FLASH_CTRL_BASE, addr)
#define HAL_SPI_READ16(addr) HAL_READ16(SPI_FLASH_CTRL_BASE, addr)
#define HAL_SPI_READ8(addr) HAL_READ8(SPI_FLASH_CTRL_BASE, addr)
typedef struct _SPIC_PARA_MODE_ {
u8 Valid :1; // valid
u8 CpuClk :3; // CPU clock
u8 BitMode :2; // Bit mode
u8 Reserved :2; // reserved
} SPIC_PARA_MODE, *PSPIC_PARA_MODE;
typedef struct _SPIC_INIT_PARA_ {
u8 BaudRate;
u8 RdDummyCyle;
u8 DelayLine;
union {
u8 Rsvd;
u8 Valid;
SPIC_PARA_MODE Mode;
};
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
u8 id[3];
u8 flashtype;
#endif
}SPIC_INIT_PARA, *PSPIC_INIT_PARA;
enum _SPIC_BIT_MODE_ {
SpicOneBitMode = 0,
SpicDualBitMode = 1,
SpicQuadBitMode = 2,
SpicMaxMode = 3
};
//======================================================
// Flash type used
#define FLASH_OTHERS 0
#define FLASH_MXIC 1
#define FLASH_MXIC_4IO 2
#define FLASH_WINBOND 3
#define FLASH_MICRON 4
#define FLASH_EON 5
//#define FLASH_MXIC_MX25L4006E 0
//#define FLASH_MXIC_MX25L8073E 1
//#define FLASH_MICRON_N25Q512A 1
// The below parts are based on the flash characteristics
//====== Flash Command Definition ======
//#if FLASH_MICRON_N25Q512A
/*Common command*/
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command 1-1-2
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command 1-2-2
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command 1-1-4
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command 1-4-4
#define FLASH_CMD_DPP 0xA2 // 1-1-2
#define FLASH_CMD_2PP 0xD2 // 1-2-2
#define FLASH_CMD_QPP 0x32 // 1-1-4
#define FLASH_CMD_4PP 0x38 //quad page program 1-4-4
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52)
#define FLASH_CMD_CE 0xC7 //Chip Erase(or 0xC7)
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
/*Micron Special command*/
#define FLASH_CMD_DE 0xC4 // DIE ERASE
#define FLASH_CMD_4PP2 0x12 // 4-BYTE PAGE PROGRAM
#define FLASH_CMD_RFSR 0x70 // READ FLAG STATUS REGISTER
#define FLASH_CMD_CFSR 0x50 // CLEAR FLAG STATUS REGISTER
#define FLASH_CMD_RNCR 0xB5 // READ NONVOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_WNCR 0xB1 // WRITE NONVOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_RVCR 0x85 // READ VOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_WVCR 0x81 // WRITE VOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_REVCR 0x65 // READ ENHANCED VOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_WEVCR 0x61 // WRITE ENHANCED VOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_REAR 0xC8 // READ EXTENDED ADDRESS REGISTER
#define FLASH_CMD_WEAR 0xC5 // WRITE EXTENDED ADDRESS REGISTER
#define FLASH_CMD_ENQUAD 0x35 // ENTER QUAD
#define FLASH_CMD_EXQUAD 0xF5 // EXIT QUAD
#define FLASH_CMD_ROTPA 0x4B // READ OTP ARRAY
#define FLASH_CMD_POTPA 0x42 // PROGRAM OTP ARRAY
/*MXIC Special command*/
#define FLASH_CMD_RDCR 0x15 //read configurate register
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
/* EON Special command*/
#define FLASH_CMD_EOTPM 0x3A // Enter OTP Mode (3Ah)
//#endif
#if 0
#if FLASH_MXIC_MX25L4006E
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52)
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_RDCR 0x15 //read configurate register
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#elif FLASH_MXIC_MX25L8073E
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0x52 //Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#else
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0x52 //Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#endif //#if FLASH_MXIC_MX25L4006E
#endif
// ============================
// ===== Flash Parameter Definition =====
//#if FLASH_MICRON_N25Q512A
#if 0
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 1
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 1
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 1
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 1
#endif
#define FLASH_DM_CYCLE_2O 0x08 // 1-1-2
#define FLASH_DM_CYCLE_2IO 0x04 // 1-2-2
#define FLASH_DM_CYCLE_4O 0x08 // 1-1-4
#define FLASH_DM_CYCLE_4IO 0x08 // 1-4-4
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I)// 1-1-2
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_RD_QUAD_IO)// 1-4-4
#define FLASH_VLD_QUAD_CMDS2 (BIT_WR_BLOCKING | BIT_RD_QUAD_O)// 1-1-4
//#endif
#if 0
#if FLASH_MXIC_MX25L4006E
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x04 // 1-1-2
#define FLASH_DM_CYCLE_2IO 0x08 // 1-2-2
#define FLASH_DM_CYCLE_4O 0x04 // 1-1-4
#define FLASH_DM_CYCLE_4IO 0x08 // 1-4-4
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_WR_DUAL_II | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#elif FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it,
//the code MUST be rechecked according to the flash spec.
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x04
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#else
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x04
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#endif
#endif
#if 0
//======================================================
// Function prototype
BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
_LONG_CALL_
extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
// spi-flash controller initialization
_LONG_CALL_
extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode);
// wait sr[0] = 0, wait transmission done
_LONG_CALL_
extern VOID SpicWaitBusyDoneRtl8195A(VOID);
// wait spi-flash status register[0] = 0
//_LONG_CALL_
//extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara);
#endif
//======================================================
// ROM Function prototype
_LONG_CALL_ VOID SpiFlashAppV02(IN VOID *Data);
_LONG_CALL_ROM_ VOID SpicInitRtl8195AV02(IN u8 InitBaudRate,IN u8 SpicBitMode);
_LONG_CALL_ROM_ VOID SpicEraseFlashRtl8195AV02(VOID);
_LONG_CALL_ROM_ VOID SpicLoadInitParaFromClockRtl8195AV02(IN u8 CpuClkMode,IN u8 BaudRate,IN PSPIC_INIT_PARA pSpicInitPara);
VOID SpicBlockEraseFlashRtl8195A(IN u32 Address);
VOID SpicSectorEraseFlashRtl8195A(IN u32 Address);
VOID SpicDieEraseFlashRtl8195A(IN u32 Address);
VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect);
VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicWaitOperationDoneRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara);
u8 SpicGetFlashStatusRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate, IN u8 SpicBitMode);
u32 SpicWaitWipRtl8195A(VOID); // IN SPIC_INIT_PARA SpicInitPara);
u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
VOID SpicDisableRtl8195A(VOID);
VOID SpicDeepPowerDownFlashRtl8195A(VOID);
VOID SpicUserProgramRtl8195A(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo);
VOID SpicUserReadRtl8195A(IN u32 Length, IN u32 addr, IN u8 * data, IN u8 BitMode);
VOID SpicUserReadFourByteRtl8195A(IN u32 Length, IN u32 addr, IN u32 * data, IN u8 BitMode);
VOID SpicReadIDRtl8195A(VOID);
VOID SpicSetFlashStatusRefinedRtl8195A(IN u32 data, IN SPIC_INIT_PARA SpicInitPara);
VOID SpicSetExtendAddrRtl8195A(IN u32 data, IN SPIC_INIT_PARA SpicInitPara);
u8 SpicGetExtendAddrRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
#if SPIC_CALIBRATION_IN_NVM
VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk);
VOID SpicNVMCalLoadAll(void);
VOID SpicNVMCalStore(u8 BitMode, u8 CpuClk);
#endif // #if SPIC_CALIBRATION_IN_NVM
#endif //_HAL_SPIFLASH__

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SSI_H_
#define _HAL_SSI_H_
#include "rtl8195a_ssi.h"
/**
* LOG Configurations
*/
extern u32 SSI_DBG_CONFIG;
extern uint8_t SPI0_IS_AS_SLAVE;
#define SSI_DBG_ENTRANCE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \
}while(0)
#define SSI_DBG_INIT(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INIT_V(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INIT_VV(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_PINMUX(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_ENDIS(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_V(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_HNDLR(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_READ(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_WRITE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_STATUS(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_FIFO(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_READ(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_WRITE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_SLV_CTRL(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
typedef enum _SSI_DBG_TYPE_LIST_ {
DBG_TYPE_ENTRANCE = 1 << 0,
DBG_TYPE_INIT = 1 << 1,
DBG_TYPE_INIT_V = 1 << 2,
DBG_TYPE_INIT_VV = 1 << 3,
DBG_TYPE_PINMUX = 1 << 4,
DBG_TYPE_ENDIS = 1 << 5,
DBG_TYPE_INT = 1 << 6,
DBG_TYPE_INT_V = 1 << 7,
DBG_TYPE_INT_HNDLR = 1 << 8,
DBG_TYPE_INT_READ = 1 << 9,
DBG_TYPE_INT_WRITE = 1 << 10,
DBG_TYPE_STATUS = 1 << 11,
DBG_TYPE_FIFO = 1 << 12,
DBG_TYPE_READ = 1 << 13,
DBG_TYPE_WRITE = 1 << 14,
DBG_TYPE_SLV_CTRL = 1 << 15
} SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST;
typedef struct _SSI_DMA_CONFIG_ {
VOID *pHalGdmaOp;
VOID *pTxHalGdmaAdapter;
VOID *pRxHalGdmaAdapter;
u8 RxDmaBurstSize;
u8 TxDmaBurstSize;
u8 RxDmaEnable;
u8 TxDmaEnable;
IRQ_HANDLE RxGdmaIrqHandle;
IRQ_HANDLE TxGdmaIrqHandle;
}SSI_DMA_CONFIG, *PSSI_DMA_CONFIG;
#ifdef CONFIG_GDMA_EN
typedef struct _HAL_SSI_DMA_MULTIBLK_ {
volatile GDMA_CH_LLI_ELE GdmaChLli[16];
struct GDMA_CH_LLI Lli[16];
struct BLOCK_SIZE_LIST BlockSizeList[16];
}SSI_DMA_MULTIBLK, *PSSI_DMA_MULTIBLK;
#endif
/**
* DesignWare SSI Configurations
*/
typedef struct _HAL_SSI_ADAPTOR_ {
SSI_DMA_CONFIG DmaConfig;
IRQ_HANDLE IrqHandle;
//
VOID (*RxCompCallback)(VOID *Para);
VOID *RxCompCbPara;
VOID *RxData;
VOID (*TxCompCallback)(VOID *Para);
VOID *TxCompCbPara;
VOID *TxData;
u32 DmaRxDataLevel;
u32 DmaTxDataLevel;
u32 InterruptPriority;
u32 RxLength;
u32 RxLengthRemainder;
u32 RxThresholdLevel;
u32 TxLength;
u32 TxThresholdLevel;
u32 SlaveSelectEnable;
//
u16 ClockDivider;
u16 DataFrameNumber;
//
u8 ControlFrameSize;
u8 DataFrameFormat;
u8 DataFrameSize;
u8 DmaControl;
u8 Index;
u8 InterruptMask;
u8 MicrowireDirection;
u8 MicrowireHandshaking;
u8 MicrowireTransferMode;
u8 PinmuxSelect;
u8 Role;
u8 SclkPhase;
u8 SclkPolarity;
u8 SlaveOutputEnable;
u8 TransferMode;
u8 TransferMechanism;
// Extend
u8 Reserve;
u8 HaveTxChannel;
u8 HaveRxChannel;
u8 DefaultRxThresholdLevel;
#ifdef CONFIG_GDMA_EN
SSI_DMA_MULTIBLK DmaTxMultiBlk, DmaRxMultiBlk;
#endif
u32 ReservedDummy;
VOID (*TxIdleCallback)(VOID *Para);
VOID *TxIdleCbPara;
}HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR;
typedef struct _HAL_SSI_OP_{
HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor);
HAL_Status (*HalSsiPinmuxDisable)(VOID *Adaptor);
HAL_Status (*HalSsiEnable)(VOID *Adaptor);
HAL_Status (*HalSsiDisable)(VOID *Adaptor);
HAL_Status (*HalSsiInit)(VOID *Adaptor);
HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor);
HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor);
HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value);
HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting);
HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor);
HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role);
HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor);
HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor);
HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length);
HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor);
HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor);
HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, u8 *TxData, u32 Length);
HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex);
u32 (*HalSsiBusy)(VOID *Adaptor);
u32 (*HalSsiReadable)(VOID *Adaptor);
u32 (*HalSsiWriteable)(VOID *Adaptor);
u32 (*HalSsiGetInterruptMask)(VOID *Adaptor);
u32 (*HalSsiGetRxFifoLevel)(VOID *Adaptor);
u32 (*HalSsiGetTxFifoLevel)(VOID *Adaptor);
u32 (*HalSsiGetStatus)(VOID *Adaptor);
u32 (*HalSsiGetInterruptStatus)(VOID *Adaptor);
u32 (*HalSsiRead)(VOID *Adaptor);
u32 (*HalSsiGetRawInterruptStatus)(VOID *Adaptor);
u32 (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor);
}HAL_SSI_OP, *PHAL_SSI_OP;
typedef struct _DW_SSI_DEFAULT_SETTING_ {
VOID (*RxCompCallback)(VOID *Para);
VOID *RxCompCbPara;
VOID *RxData;
VOID (*TxCompCallback)(VOID *Para);
VOID *TxCompCbPara;
VOID *TxData;
u32 DmaRxDataLevel;
u32 DmaTxDataLevel;
u32 InterruptPriority;
u32 RxLength;
u32 RxLengthRemainder;
u32 RxThresholdLevel;
u32 TxLength;
u32 TxThresholdLevel;
u32 SlaveSelectEnable;
//
u16 ClockDivider;
u16 DataFrameNumber;
//
u8 ControlFrameSize;
u8 DataFrameFormat;
u8 DataFrameSize;
u8 DmaControl;
//u8 Index;
u8 InterruptMask;
u8 MicrowireDirection;
u8 MicrowireHandshaking;
u8 MicrowireTransferMode;
//u8 PinmuxSelect;
//u8 Role;
u8 SclkPhase;
u8 SclkPolarity;
u8 SlaveOutputEnable;
u8 TransferMode;
u8 TransferMechanism;
} DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING;
struct spi_s {
HAL_SSI_ADAPTOR spi_adp;
HAL_SSI_OP spi_op;
u32 irq_handler;
u32 irq_id;
u32 dma_en;
u32 state;
u8 sclk;
#ifdef CONFIG_GDMA_EN
HAL_GDMA_ADAPTER spi_gdma_adp_tx;
HAL_GDMA_ADAPTER spi_gdma_adp_rx;
#endif
u32 bus_tx_done_handler;
u32 bus_tx_done_irq_id;
};
VOID HalSsiOpInit(VOID *Adaptor);
static __inline__ VOID HalSsiSetSclk(
IN PHAL_SSI_ADAPTOR pHalSsiAdapter,
IN u32 ClkRate)
{
HalSsiSetSclkRtl8195a((VOID*)pHalSsiAdapter, ClkRate);
}
HAL_Status HalSsiInit(VOID * Data);
HAL_Status HalSsiDeInit(VOID * Data);
HAL_Status HalSsiEnable(VOID * Data);
HAL_Status HalSsiDisable(VOID * Data);
HAL_Status HalSsiEnterCritical(VOID * Data);
HAL_Status HalSsiExitCritical(VOID * Data);
HAL_Status HalSsiTimeout(u32 StartCount, u32 TimeoutCnt);
HAL_Status HalSsiStopRecv(VOID * Data);
HAL_Status HalSsiSetFormat(VOID * Data);
#ifdef CONFIG_GDMA_EN
HAL_Status HalSsiTxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
VOID HalSsiTxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiRxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
VOID HalSsiRxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiRxMultiBlkChnl(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiDmaRecv(VOID * Adapter, u8 * pRxData, u32 Length);
HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length);
static __inline__ VOID
HalSsiDmaInit(
IN PHAL_SSI_ADAPTOR pHalSsiAdapter
)
{
#if CONFIG_CHIP_E_CUT
HalSsiDmaInitRtl8195a_V04((void *)pHalSsiAdapter);
#else
HalSsiDmaInitRtl8195a((void *)pHalSsiAdapter);
#endif
}
/*
static __inline__ HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length)
{
return (HalSsiDmaSendRtl8195a(Adapter, pTxData, Length));
}
static __inline__ HAL_Status HalSsiDmaRecv(VOID *Adapter, u8 *pRxData, u32 Length)
{
return (HalSsiDmaRecvRtl8195a(Adapter, pRxData, Length));
}
*/
#endif // end of "#ifdef CONFIG_GDMA_EN"
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_TIMER_H_
#define _HAL_TIMER_H_
#include "basic_types.h"
#include "hal_platform.h"
#include "rtl8195a_timer.h"
#define GTIMER_CLK_HZ (32768)
#define GTIMER_TICK_US (1000000/GTIMER_CLK_HZ)
typedef enum _TIMER_MODE_ {
FREE_RUN_MODE = 0,
USER_DEFINED = 1
}TIMER_MODE, *PTIMER_MODE;
typedef struct _TIMER_ADAPTER_ {
u32 TimerLoadValueUs; //+00
u32 TimerIrqPriority; //+04
TIMER_MODE TimerMode; //+08
IRQ_HANDLE IrqHandle; //+0c
u8 TimerId; //+1c?
u8 IrqDis; //+1d?
}TIMER_ADAPTER, *PTIMER_ADAPTER;
typedef struct _HAL_TIMER_OP_ {
u32 (*HalGetTimerId)(u32 *TimerId); //+00
BOOL (*HalTimerInit)(VOID *Data); //+04
u32 (*HalTimerReadCount)(u32 TimerId); //+08
VOID (*HalTimerIrqClear)(u32 TimerId); //+0c
VOID (*HalTimerDis)(u32 TimerId); //+10
VOID (*HalTimerEn)(u32 TimerId); //+14
VOID (*HalTimerDumpReg)(u32 TimerId); //+18
}HAL_TIMER_OP, *PHAL_TIMER_OP;
#ifdef CONFIG_TIMER_MODULE
// This variable declared in ROM code
extern HAL_TIMER_OP HalTimerOp;
#endif
VOID HalTimerOpInit_Patch(
IN VOID *Data
);
//======================================================
// ROM Function prototype
_LONG_CALL_ VOID HalTimerOpInitV02(IN VOID *Data);
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#define HalTimerOpInit HalTimerOpInit_Patch
#endif
#ifdef CONFIG_RELEASE_BUILD_LIBRARIES
void HalTimerOpInit(
void *Data
);
HAL_Status
HalTimerInit(
void *Data
);
void
HalTimerEnable(
uint32_t TimerId
);
void
HalTimerDisable(
uint32_t TimerId
);
void
HalTimerReLoad(
uint32_t TimerId,
uint32_t LoadUs
);
void
HalTimerDeInit(
void *Data
);
#endif // #ifdef CONFIG_RELEASE_BUILD_LIBRARIES
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_UART_H_
#define _HAL_UART_H_
#include "rtl8195a_uart.h"
/**
* RUART Configurations
*/
#define UART_WAIT_FOREVER 0xffffffff
#define UART_DMA_MBLK_NUM 16 // maximum block number for each DMA transfer, it must <= 16
#define UART_DMA_BLOCK_SIZE 4092 // the block size of multiple block DMA, it cann0t over 4095
typedef struct _HAL_UART_DMA_MULTIBLK_ {
volatile GDMA_CH_LLI_ELE GdmaChLli[UART_DMA_MBLK_NUM];
struct GDMA_CH_LLI Lli[UART_DMA_MBLK_NUM];
struct BLOCK_SIZE_LIST BlockSizeList[UART_DMA_MBLK_NUM];
}UART_DMA_MULTIBLK, *PUART_DMA_MULTIBLK;
typedef struct _UART_DMA_CONFIG_ {
u8 TxDmaEnable;
u8 RxDmaEnable;
u8 TxDmaBurstSize;
u8 RxDmaBurstSize;
VOID *pHalGdmaOp;
VOID *pTxHalGdmaAdapter;
VOID *pRxHalGdmaAdapter;
IRQ_HANDLE TxGdmaIrqHandle;
IRQ_HANDLE RxGdmaIrqHandle;
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
UART_DMA_MULTIBLK *pTxDmaBlkList; // point to multi-block list
UART_DMA_MULTIBLK *pRxDmaBlkList; // point to multi-block list
u8 TxDmaMBChnl; // is using DMA multiple block channel
u8 RxDmaMBChnl; // is using DMA multiple block channel
#endif
}UART_DMA_CONFIG, *PUART_DMA_CONFIG;
typedef struct _HAL_RUART_ADAPTER_ {
u32 BaudRate;
u32 FlowControl;
u32 FifoControl;
u32 Interrupts;
u32 TxCount; // how many byte to TX
u32 RxCount; // how many bytes to RX
u8 *pTxBuf;
u8 *pRxBuf;
HAL_UART_State State; // UART state
u8 Status; // Transfer Status
u8 Locked; // is UART locked for operation
u8 UartIndex;
u8 WordLen; // word length select: 0 -> 7 bits, 1 -> 8 bits
u8 StopBit; // word length select: 0 -> 1 stop bit, 1 -> 2 stop bit
u8 Parity; // parity check enable
u8 ParityType; // parity check type
u8 StickParity;
u8 ModemStatus; // the modem status
u8 DmaEnable;
u8 TestCaseNumber;
u8 PinmuxSelect;
BOOL PullMode;
IRQ_HANDLE IrqHandle;
PUART_DMA_CONFIG DmaConfig;
VOID (*ModemStatusInd)(VOID *pAdapter); // modem status indication interrupt handler
VOID (*TxTDCallback)(VOID *pAdapter); // User Tx Done callback function
VOID (*RxDRCallback)(VOID *pAdapter); // User Rx Data ready callback function
VOID (*TxCompCallback)(VOID *para); // User Tx complete callback function
VOID (*RxCompCallback)(VOID *para); // User Rx complete callback function
VOID *TxTDCbPara; // the pointer agrument for TxTDCallback
VOID *RxDRCbPara; // the pointer agrument for RxDRCallback
VOID *TxCompCbPara; // the pointer argument for TxCompCbPara
VOID *RxCompCbPara; // the pointer argument for RxCompCallback
VOID (*EnterCritical)(void);
VOID (*ExitCritical)(void);
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
//1 New member only can be added below: members above must be fixed for ROM code
u32 *pDefaultBaudRateTbl; // point to the table of pre-defined baud rate
u8 *pDefaultOvsrRTbl; // point to the table of OVSR for pre-defined baud rate
u16 *pDefaultDivTbl; // point to the table of DIV for pre-defined baud rate
u8 *pDefOvsrAdjBitTbl_10; // point to the table of OVSR-Adj bits for 10 bits
u8 *pDefOvsrAdjBitTbl_9; // point to the table of OVSR-Adj bits for 9 bits
u8 *pDefOvsrAdjBitTbl_8; // point to the table of OVSR-Adj bits for 8 bits
u16 *pDefOvsrAdjTbl_10; // point to the table of OVSR-Adj for pre-defined baud rate
u16 *pDefOvsrAdjTbl_9; // point to the table of OVSR-Adj for pre-defined baud rate
u16 *pDefOvsrAdjTbl_8; // point to the table of OVSR-Adj for pre-defined baud rate
PUART_DMA_MULTIBLK pTxDMAMBlk; // point to the Link List Table of the DMA Multiple Block
PUART_DMA_MULTIBLK pRxDMAMBlk; // point to the Link List Table of the DMA Multiple Block
u32 BaudRateUsing; // Current using Baud-Rate
u8 WordLenUsing; // Current using Word Length
u8 ParityUsing; // Current using Parity check
u8 RTSCtrl; // Software RTS Control
#if 0//CONFIG_CHIP_E_CUT
u8 TxState;
u8 RxState;
u32 TxInitSize; // how many byte to TX at atart
u32 RxInitSize; // how many bytes to RX at start
VOID (*RuartEnterCritical)(VOID *para); // enter critical: disable UART interrupt
VOID (*RuartExitCritical)(VOID *para); // exit critical: re-enable UART interrupt
VOID (*TaskYield)(VOID *para); // User Task Yield: do a context switch while waitting
VOID *TaskYieldPara; // the agrument (pointer) for TaskYield
#endif // #if CONFIG_CHIP_E_CUT
#endif
}HAL_RUART_ADAPTER, *PHAL_RUART_ADAPTER;
typedef struct _HAL_RUART_OP_ {
VOID (*HalRuartAdapterLoadDef)(VOID *pAdp, u8 UartIdx); // Load UART adapter default setting
VOID (*HalRuartTxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load TX GDMA default setting
VOID (*HalRuartRxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load RX GDMA default setting
HAL_Status (*HalRuartResetRxFifo)(VOID *Data);
HAL_Status (*HalRuartInit)(VOID *Data);
VOID (*HalRuartDeInit)(VOID *Data);
HAL_Status (*HalRuartPutC)(VOID *Data, u8 TxData);
u32 (*HalRuartSend)(VOID *Data, u8 *pTxData, u32 Length, u32 Timeout);
HAL_Status (*HalRuartIntSend)(VOID *Data, u8 *pTxData, u32 Length);
HAL_Status (*HalRuartDmaSend)(VOID *Data, u8 *pTxData, u32 Length);
HAL_Status (*HalRuartStopSend)(VOID *Data);
HAL_Status (*HalRuartGetC)(VOID *Data, u8 *pRxByte);
u32 (*HalRuartRecv)(VOID *Data, u8 *pRxData, u32 Length, u32 Timeout);
HAL_Status (*HalRuartIntRecv)(VOID *Data, u8 *pRxData, u32 Length);
HAL_Status (*HalRuartDmaRecv)(VOID *Data, u8 *pRxData, u32 Length);
HAL_Status (*HalRuartStopRecv)(VOID *Data);
u8 (*HalRuartGetIMR)(VOID *Data);
VOID (*HalRuartSetIMR)(VOID *Data);
u32 (*HalRuartGetDebugValue)(VOID *Data, u32 DbgSel);
VOID (*HalRuartDmaInit)(VOID *Data);
VOID (*HalRuartRTSCtrl)(VOID *Data, BOOLEAN RtsCtrl);
VOID (*HalRuartRegIrq)(VOID *Data);
VOID (*HalRuartIntEnable)(VOID *Data);
VOID (*HalRuartIntDisable)(VOID *Data);
}HAL_RUART_OP, *PHAL_RUART_OP;
typedef struct _RUART_DATA_ {
PHAL_RUART_ADAPTER pHalRuartAdapter;
BOOL PullMode;
u8 BinaryData;
u8 SendBuffer;
u8 RecvBuffer;
}RUART_DATA, *PRUART_DATA;
typedef struct _RUART_ADAPTER_ {
PHAL_RUART_OP pHalRuartOp;
PHAL_RUART_ADAPTER pHalRuartAdapter;
PUART_DMA_CONFIG pHalRuartDmaCfg;
}RUART_ADAPTER, *PRUART_ADAPTER;
extern VOID
HalRuartOpInit(
IN VOID *Data
);
extern HAL_Status
HalRuartTxGdmaInit(
PHAL_RUART_ADAPTER pHalRuartAdapter,
PUART_DMA_CONFIG pUartGdmaConfig,
u8 IsMultiBlk
);
extern VOID
HalRuartTxGdmaDeInit(
PUART_DMA_CONFIG pUartGdmaConfig
);
extern HAL_Status
HalRuartRxGdmaInit(
PHAL_RUART_ADAPTER pHalRuartAdapter,
PUART_DMA_CONFIG pUartGdmaConfig,
u8 IsMultiBlk
);
extern VOID
HalRuartRxGdmaDeInit(
PUART_DMA_CONFIG pUartGdmaConfig
);
extern HAL_Status
HalRuartResetTxFifo(
VOID *Data
);
extern HAL_Status HalRuartResetTRxFifo(IN VOID *Data);
extern HAL_Status
HalRuartResetRxFifo(
IN VOID *Data
);
extern HAL_Status
HalRuartSetBaudRate(
IN VOID *Data
);
extern HAL_Status
HalRuartInit(
IN VOID *Data
);
extern VOID
HalRuartDeInit(
IN VOID *Data
);
extern HAL_Status
HalRuartDisable(
IN VOID *Data
);
extern HAL_Status
HalRuartEnable(
IN VOID *Data
);
HAL_Status
HalRuartFlowCtrl(
IN VOID *Data
);
VOID
HalRuartEnterCritical(
IN VOID *Data
);
VOID
HalRuartExitCritical(
IN VOID *Data
);
HAL_Status
HalRuartDmaSend(
IN VOID *Data,
IN u8 *pTxBuf,
IN u32 Length
);
HAL_Status
HalRuartDmaRecv(
IN VOID *Data,
IN u8 *pRxBuf,
IN u32 Length
);
extern const HAL_RUART_OP _HalRuartOp;
extern HAL_Status RuartLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
extern VOID RuartUnLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_USB_H_
#define _HAL_USB_H_
#include "rtl8195a_usb.h"
#endif //_HAL_USB_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_UTIL_H_
#define _HAL_UTIL_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* Simple doubly linked list implementation.
*
* Some of the internal functions ("__xxx") are useful when
* manipulating whole lists rather than single entries, as
* sometimes we already know the next/prev entries and we can
* generate better code by using them directly rather than
* using the generic single-entry routines.
*/
struct LIST_HEADER {
struct LIST_HEADER *Next, *Prev;
};
typedef struct LIST_HEADER _LIST;
//#define RTL_LIST_HEAD_INIT(name) { &(name), &(name) }
#define RTL_INIT_LIST_HEAD(ptr) do { \
(ptr)->Next = (ptr); (ptr)->Prev = (ptr); \
} while (0)
/*
* Insert a new entry between two known consecutive entries.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline__ VOID
__List_Add(
IN struct LIST_HEADER * New,
IN struct LIST_HEADER * Prev,
IN struct LIST_HEADER * Next
)
{
Next->Prev = New;
New->Next = Next;
New->Prev = Prev;
Prev->Next = New;
}
/*
* Delete a list entry by making the prev/next entries
* point to each other.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline__ VOID
__List_Del(
IN struct LIST_HEADER * Prev,
IN struct LIST_HEADER * Next
)
{
Next->Prev = Prev;
Prev->Next = Next;
}
/**
* ListDel - deletes entry from list.
* @entry: the element to delete from the list.
* Note: list_empty on entry does not return true after this, the entry is in an undefined state.
*/
static __inline__ VOID
ListDel(
IN struct LIST_HEADER *Entry
)
{
__List_Del(Entry->Prev, Entry->Next);
}
/**
* ListDelInit - deletes entry from list and reinitialize it.
* @entry: the element to delete from the list.
*/
static __inline__ VOID
ListDelInit(
IN struct LIST_HEADER *Entry
)
{
__List_Del(Entry->Prev, Entry->Next);
RTL_INIT_LIST_HEAD(Entry);
}
/**
* ListEmpty - tests whether a list is empty
* @head: the list to test.
*/
static __inline__ u32
ListEmpty(
IN struct LIST_HEADER *Head
)
{
return Head->Next == Head;
}
/**
* ListSplice - join two lists
* @list: the new list to add.
* @head: the place to add it in the first list.
*/
static __inline__ VOID
ListSplice(
IN struct LIST_HEADER *List,
IN struct LIST_HEADER *Head
)
{
struct LIST_HEADER *First = List->Next;
if (First != List) {
struct LIST_HEADER *Last = List->Prev;
struct LIST_HEADER *At = Head->Next;
First->Prev = Head;
Head->Next = First;
Last->Next = At;
At->Prev = Last;
}
}
static __inline__ VOID
ListAdd(
IN struct LIST_HEADER *New,
IN struct LIST_HEADER *head
)
{
__List_Add(New, head, head->Next);
}
static __inline__ VOID
ListAddTail(
IN struct LIST_HEADER *New,
IN struct LIST_HEADER *head
)
{
__List_Add(New, head->Prev, head);
}
static __inline VOID
RtlInitListhead(
IN _LIST *list
)
{
RTL_INIT_LIST_HEAD(list);
}
/*
For the following list_xxx operations,
caller must guarantee the atomic context.
Otherwise, there will be racing condition.
*/
static __inline u32
RtlIsListEmpty(
IN _LIST *phead
)
{
if (ListEmpty(phead))
return _TRUE;
else
return _FALSE;
}
static __inline VOID
RtlListInsertHead(
IN _LIST *plist,
IN _LIST *phead
)
{
ListAdd(plist, phead);
}
static __inline VOID
RtlListInsertTail(
IN _LIST *plist,
IN _LIST *phead
)
{
ListAddTail(plist, phead);
}
static __inline _LIST
*RtlListGetNext(
IN _LIST *plist
)
{
return plist->Next;
}
static __inline VOID
RtlListDelete(
IN _LIST *plist
)
{
ListDelInit(plist);
}
#define RTL_LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#ifndef CONTAINER_OF
#define CONTAINER_OF(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#endif
#if 0
#define list_entry(ptr, type, member) \
CONTAINER_OF(ptr, type, member)
#define list_first_entry(ptr, type, member) \
list_entry((ptr)->Next, type, member)
#define list_next_entry(pos, member, type) \
list_entry((pos)->member.Next, type, member)
#define list_for_each_entry(pos, head, member, type) \
for (pos = list_first_entry(head, type, member); \
&pos->member != (head); \
pos = list_next_entry(pos, member, type))
#define list_for_each(pos, head) \
for (pos = (head)->Next; pos != (head); pos = pos->Next)
#endif
#ifndef BIT
#define BIT(x) ( 1 << (x))
#endif
#ifdef __cplusplus
}
#endif
#endif //_HAL_UTIL_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_VECTOR_TABLE_H_
#define _HAL_VECTOR_TABLE_H_
extern _LONG_CALL_ROM_ VOID
VectorTableInitRtl8195A(
IN u32 StackP
);
extern _LONG_CALL_ROM_ VOID
VectorTableInitForOSRtl8195A(
IN VOID *PortSVC,
IN VOID *PortPendSVH,
IN VOID *PortSysTick
);
extern _LONG_CALL_ROM_ BOOL
VectorIrqRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ BOOL
VectorIrqUnRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
VectorIrqEnRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
VectorIrqDisRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
HalPeripheralIntrHandle(VOID);
#endif //_HAL_VECTOR_TABLE_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2015 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "build_info.h"
#include "PinNames.h"
#include "serial_api.h"
extern void serial_init (serial_t *obj, PinName tx, PinName rx);
extern void serial_free (serial_t *obj);
extern void serial_baud (serial_t *obj, int baudrate);
extern void serial_format (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
extern int main(void);
void iar_data_init_fw_loader(void);
void fw_loader_main(void);// __attribute__ ((weak));
#pragma section=".image2.start.table1"
#pragma section=".fwloader_ram.bss"
FW_LOADER_START_RAM_FUN_SECTION
RAM_START_FUNCTION gFWLoaderEntryFun0 = {fw_loader_main};
u8* __image4_entry_func__;
u8* __image4_validate_code__;
u8* __fwloader_bss_start__;
u8* __fwloader_bss_end__;
FW_LOADER_VALID_PATTEN_SECTION const u8 RAM_FW_LOADER_VALID_PATTEN[20] = {
'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff),
(FW_CHIP_VER),
(FW_BUS_TYPE),
(FW_INFO_RSV1),
(FW_INFO_RSV2),
(FW_INFO_RSV3),
(FW_INFO_RSV4)
};
/**
* @brief Main program.
* @param None
* @retval None
*/
void fw_loader_main(void)
{
#if defined ( __ICCARM__ )
iar_data_init_fw_loader();
#endif
u32 Image2Len, Image2Addr, ImageIndex, SpicBitMode, SpicImageIndex;
u32 Image2LoadAddr = 0x13000;
DBG_8195A("===== Enter FW Loader Image ====\n");
#ifdef BOOTLOADER
main();
#endif
IGMAE4:
PRAM_START_FUNCTION Image4EntryFun=(PRAM_START_FUNCTION)__image4_entry_func__;
Image2Len = HAL_READ32(SPI_FLASH_BASE, Image2LoadAddr);
Image2Addr = HAL_READ32(SPI_FLASH_BASE, (Image2LoadAddr+0x4));
DBG_8195A("Flash FW Loader:Addr 0x%x, Len %d, Load to SRAM 0x%x\n", Image2LoadAddr, Image2Len, Image2Addr);
SpicImageIndex = 0;
for (ImageIndex = 0x10 + Image2LoadAddr; ImageIndex < (Image2Len + Image2LoadAddr + 0x10); ImageIndex = ImageIndex + 4) {
HAL_WRITE32(Image2Addr, SpicImageIndex,
HAL_READ32(SPI_FLASH_BASE, ImageIndex));
SpicImageIndex += 4;
}
#ifdef CONFIG_SDR_EN
u32 Image3LoadAddr;
u32 Image3Len;
u32 Image3Addr;
Image3LoadAddr = Image2LoadAddr + Image2Len+0x10;
Image3Len = HAL_READ32(SPI_FLASH_BASE, Image3LoadAddr);
Image3Addr = HAL_READ32(SPI_FLASH_BASE, Image3LoadAddr + 0x4);
if( (Image3Len==0xFFFFFFFF) || (Image3Len==0) || (Image3Addr!=0x30000000)){
DBG_8195A("No Image3\n\r");
}else{
DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",Image3Len, Image3Addr);
SpicImageIndex = 0;
for (ImageIndex = 0x10 + Image3LoadAddr;
ImageIndex < (Image3Len + Image3LoadAddr + 0x10);
ImageIndex = ImageIndex + 4) {
HAL_WRITE32(Image3Addr, SpicImageIndex,
HAL_READ32(SPI_FLASH_BASE, ImageIndex));
SpicImageIndex += 4;
}
}
#endif
//3 3) Jump to image 4
DBG_8195A("InfraStart: %p, Img2 Sign %s \n", __image4_entry_func__, (char*)__image4_validate_code__);
if (_strcmp((char *)__image4_validate_code__, "RTKWin")) {
while (1) {
DBG_8195A("Invalid Image4 Signature\n");
RtlConsolRom(1000);//each delay is 100us
}
}
#ifdef BOOTLOADER
deinit_platform_bootloader();
#endif
Image4EntryFun->RamStartFun();
}
void iar_data_init_fw_loader(void)
{
__image4_entry_func__ = (u8*)__section_begin(".image2.start.table1");
__image4_validate_code__ = __image4_entry_func__+4;//(u8*)__section_begin(".image2.start.table2");
__fwloader_bss_start__ = (u8*)__section_begin(".fwloader_ram.bss");
__fwloader_bss_end__ = (u8*)__section_end(".fwloader_ram.bss");
}

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#include "rtl8195a.h"
typedef struct _UART_LOG_BUF_ {
u8 BufCount; //record the input cmd char number.
u8 UARTLogBuf[127]; //record the input command.
} UART_LOG_BUF, *PUART_LOG_BUF;
typedef struct _UART_LOG_CTL_ {
u8 NewIdx;
u8 SeeIdx;
u8 RevdNo;
u8 EscSTS;
u8 ExecuteCmd;
u8 ExecuteEsc;
u8 BootRdy;
u8 Resvd;
PUART_LOG_BUF pTmpLogBuf;
VOID *pfINPUT;
PCOMMAND_TABLE pCmdTbl;
u32 CmdTblSz;
u32 CRSTS;
u8 (*pHistoryBuf)[127];
u32 TaskRdy;
u32 Sema;
} UART_LOG_CTL, *PUART_LOG_CTL;
volatile UART_LOG_CTL UartLogCtl;
volatile UART_LOG_CTL *pUartLogCtl;
u8 *ArgvArray[10];
UART_LOG_BUF UartLogBuf;
u8 UartLogHistoryBuf[5][127];
extern VOID
SpicLoadInitParaFromClockRtl8195A
(
IN u8 CpuClkMode,
IN u8 BaudRate,
IN PSPIC_INIT_PARA pSpicInitPara
);
VOID
PatchSpicInitRtl8195A
(
IN u8 InitBaudRate,
IN u8 SpicBitMode
)
{
u32 Value32;
SPIC_INIT_PARA SpicInitPara;
#ifdef CONFIG_FPGA
SpicInitPara.BaudRate = 1;//FPGASpicInitPara.BaudRate;
SpicInitPara.RdDummyCyle = 1;//FPGASpicInitPara.RdDummyCyle;
SpicInitPara.DelayLine = 0;//FPGASpicInitPara.DelayLine;
#else
u8 CpuClk;
CpuClk = (((u8)(HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70))) >> 4);
SpicLoadInitParaFromClockRtl8195A(CpuClk, InitBaudRate, &SpicInitPara);
#endif
// Disable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
HAL_SPI_WRITE32(REG_SPIC_BAUDR, BIT_SCKDV(InitBaudRate));
HAL_SPI_WRITE32(REG_SPIC_SER, BIT_SER);
Value32 = HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH);
HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH,
((Value32 & 0xFFFF0000) | BIT_RD_DUMMY_LENGTH(SpicInitPara.RdDummyCyle)));
HAL_WRITE32(PERI_ON_BASE, REG_PESOC_MEM_CTRL,
((HAL_READ32(PERI_ON_BASE, REG_PESOC_MEM_CTRL)&0xFFFFFF00)|
SpicInitPara.DelayLine));
HAL_SPI_WRITE32(REG_SPIC_CTRLR1, BIT_NDF(4));
switch (SpicBitMode) {
case SpicOneBitMode:
HAL_SPI_WRITE32(REG_SPIC_CTRLR0,
(HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~(BIT_ADDR_CH(3)|BIT_DATA_CH(3)))));
break;
case SpicDualBitMode:
HAL_SPI_WRITE32(REG_SPIC_CTRLR0,
((HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~(BIT_ADDR_CH(3)|BIT_DATA_CH(3)))) |
(BIT_ADDR_CH(1)|BIT_DATA_CH(1))));
break;
case SpicQuadBitMode:
HAL_SPI_WRITE32(REG_SPIC_CTRLR0,
((HAL_SPI_READ32(REG_SPIC_CTRLR0) & (~(BIT_ADDR_CH(3)|BIT_DATA_CH(3)))) |
(BIT_ADDR_CH(2)|BIT_DATA_CH(2))));
break;
}
// Enable SPI_FLASH User Mode
// HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN);
}
#include "hal_timer.h"
extern BOOL
HalTimerInitRtl8195a(
IN VOID *Data
);
VOID
PatchHalInitPlatformTimer(
VOID
)
{
TIMER_ADAPTER TimerAdapter;
OSC32K_CKGEN_CTRL(ON);
GTIMER_FCTRL(ON);
ACTCK_TIMER_CCTRL(ON);
SLPCK_TIMER_CCTRL(ON);
TimerAdapter.IrqDis = ON;
// TimerAdapter.IrqHandle = (IRQ_FUN)NULL;
TimerAdapter.TimerId = 1;
TimerAdapter.TimerIrqPriority = 0;
TimerAdapter.TimerLoadValueUs = 0;
TimerAdapter.TimerMode = FREE_RUN_MODE;
HalTimerInitRtl8195a((VOID*) &TimerAdapter);
}
#define UART_BAUD_RATE_2400 2400
#define UART_BAUD_RATE_4800 4800
#define UART_BAUD_RATE_9600 9600
#define UART_BAUD_RATE_19200 19200
#define UART_BAUD_RATE_38400 38400
#define UART_BAUD_RATE_57600 57600
#define UART_BAUD_RATE_115200 115200
#define UART_BAUD_RATE_921600 921600
#define UART_BAUD_RATE_1152000 1152000
#define UART_PARITY_ENABLE 0x08
#define UART_PARITY_DISABLE 0
#define UART_DATA_LEN_5BIT 0x0
#define UART_DATA_LEN_6BIT 0x1
#define UART_DATA_LEN_7BIT 0x2
#define UART_DATA_LEN_8BIT 0x3
#define UART_STOP_1BIT 0x0
#define UART_STOP_2BIT 0x4
extern u32
HalLogUartInit(
IN LOG_UART_ADAPTER UartAdapter
);
extern u32
HalGetCpuClk(
VOID
);
const u32 StartupCpkClkTbl[]= {
200000000,
100000000,
50000000,
25000000,
12500000,
4000000
};
u32
StartupHalGetCpuClk(
VOID
)
{
u32 CpuType = 0, CpuClk = 0, FreqDown = 0;
CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4);
FreqDown = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & BIT17;
CpuClk = StartupCpkClkTbl[CpuType];
if ( !FreqDown ) {
if ( CpuClk > 4000000 ){
CpuClk = (CpuClk*5/6);
}
}
return CpuClk;
}
u32
PatchHalLogUartInit(
IN LOG_UART_ADAPTER UartAdapter
)
{
u32 SetData;
u32 Divisor;
u32 Dlh;
u32 Dll;
u32 SysClock;
/*
Interrupt enable Register
7: THRE Interrupt Mode Enable
2: Enable Receiver Line Status Interrupt
1: Enable Transmit Holding Register Empty Interrupt
0: Enable Received Data Available Interrupt
*/
// disable all interrupts
HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, 0);
/*
Line Control Register
7: DLAB, enable reading and writing DLL and DLH register, and must be cleared after
initial baud rate setup
3: PEN, parity enable/disable
2: STOP, stop bit
1:0 DLS, data length
*/
// set DLAB bit to 1
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 0x80);
// set up buad rate division
#ifdef CONFIG_FPGA
SysClock = SYSTEM_CLK;
Divisor = (SysClock / (16 * (UartAdapter.BaudRate)));
#else
{
u32 SampleRate,Remaind;
//SysClock = (HalGetCpuClk()>>2);
SysClock = (StartupHalGetCpuClk()>>2);
SampleRate = (16 * (UartAdapter.BaudRate));
Divisor= SysClock/SampleRate;
Remaind = ((SysClock*10)/SampleRate) - (Divisor*10);
if (Remaind>4) {
Divisor++;
}
}
#endif
Dll = Divisor & 0xff;
Dlh = (Divisor & 0xff00)>>8;
HAL_UART_WRITE32(UART_DLL_OFF, Dll);
HAL_UART_WRITE32(UART_DLH_OFF, Dlh);
// clear DLAB bit
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 0);
// set data format
SetData = UartAdapter.Parity | UartAdapter.Stop | UartAdapter.DataLength;
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, SetData);
/* FIFO Control Register
7:6 level of receive data available interrupt
5:4 level of TX empty trigger
2 XMIT FIFO reset
1 RCVR FIFO reset
0 FIFO enable/disable
*/
// FIFO setting, enable FIFO and set trigger level (2 less than full when receive
// and empty when transfer
HAL_UART_WRITE32(UART_FIFO_CTL_REG_OFF, UartAdapter.FIFOControl);
/*
Interrupt Enable Register
7: THRE Interrupt Mode enable
2: Enable Receiver Line status Interrupt
1: Enable Transmit Holding register empty INT32
0: Enable received data available interrupt
*/
HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, UartAdapter.IntEnReg);
if (UartAdapter.IntEnReg) {
// Enable Peripheral_IRQ Setting for Log_Uart
HAL_WRITE32(VENDOR_REG_BASE, PERIPHERAL_IRQ_EN, 0x1000000);
// Enable ARM Cortex-M3 IRQ
NVIC_SetPriorityGrouping(0x3);
NVIC_SetPriority(PERIPHERAL_IRQ, 14);
NVIC_EnableIRQ(PERIPHERAL_IRQ);
}
return 0;
}
u32 log_uart_irq(VOID *Data)
{
return 0;
}
VOID
PatchHalInitPlatformLogUart(
VOID
)
{
IRQ_HANDLE UartIrqHandle;
LOG_UART_ADAPTER UartAdapter;
//4 Release log uart reset and clock
LOC_UART_FCTRL(OFF);
LOC_UART_FCTRL(ON);
ACTCK_LOG_UART_CCTRL(ON);
PinCtrl(LOG_UART,S0,ON);
//4 Register Log Uart Callback function
UartIrqHandle.Data = (u32)NULL;//(u32)&UartAdapter;
UartIrqHandle.IrqNum = UART_LOG_IRQ;
UartIrqHandle.IrqFun = (IRQ_FUN) log_uart_irq;//UartLogIrqHandleRam;
UartIrqHandle.Priority = 0;
//4 Inital Log uart
UartAdapter.BaudRate = DEFAULT_BAUDRATE;
UartAdapter.DataLength = UART_DATA_LEN_8BIT;
UartAdapter.FIFOControl = 0xC1;
UartAdapter.IntEnReg = 0x00;
UartAdapter.Parity = UART_PARITY_DISABLE;
UartAdapter.Stop = UART_STOP_1BIT;
//4 Initial Log Uart
PatchHalLogUartInit(UartAdapter);
//4 Register Isr handle
InterruptRegister(&UartIrqHandle);
UartAdapter.IntEnReg = 0x05;
//4 Initial Log Uart for Interrupt
PatchHalLogUartInit(UartAdapter);
//4 initial uart log parameters before any uartlog operation
//RtlConsolInit(ROM_STAGE,GetRomCmdNum(),(VOID*)&UartLogRomCmdTable);// executing boot seq.,
}

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/*
decompiled low_level_io.o
*/
#include ......
//-------------------------------------------------------------------------
// Function declarations
void mode_init();
void HalSerialPutcRtl8195a(int c, int a2, char a3);
signed int DiagPrintf(const char *fmt, ...);
void log_uart_enable_printf();
void log_uart_disable_printf();
//-------------------------------------------------------------------------
// Data declarations
uint32_t backupWarn;
uint32_t backupErr;
uint32_t backupInfo;
int disablePrintf;
// extern _UNKNOWN use_mode;
// extern _UNKNOWN ConfigDebugErr;
// extern _UNKNOWN ConfigDebugInfo;
// extern _UNKNOWN ConfigDebugWarn;
//-----
void mode_init()
{
use_mode = 1;
}
//-----
void HalSerialPutcRtl8195a(int c)
{
signed int v3; // r3@2
if ( disablePrintf != 1 )
{
v3 = 6540;
do
{
if ( !--v3 )
break;
a3 = v40003014;
}
while ( !(v40003014 & 0x60) );
if ( c == 10 ) a3 = 13;
v40003000 = c;
if ( c == 10 ) v40003000 = a3;
}
}
//-----
signed int DiagPrintf(const char *fmt, ...)
{
va_list va;
va_start(va, fmt);
if ( disablePrintf != 1 )
VSprintf(0, fmt, va);
return 1;
}
//-----
void log_uart_enable_printf()
{
disablePrintf = 0;
ConfigDebugErr = backupErr;
ConfigDebugInfo = backupInfo;
ConfigDebugWarn = backupWarn;
}
//-----
void log_uart_disable_printf()
{
disablePrintf = 1;
backupErr = ConfigDebugErr;
backupInfo = ConfigDebugInfo;
backupWarn = ConfigDebugWarn;
ConfigDebugErr = 0;
ConfigDebugInfo = 0;
ConfigDebugWarn = 0;
}

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/*
* rtl_bios_data.c
*
* Created on: 12/02/2017
* Author: pvvx
*
* This variables declared in ROM code!
* Variables use fixed addresses!
* (see *.ld script)
*/
#include "rtl_bios_data.h"
extern void * UartLogRomCmdTable;
/* ROM + startup.c */
RAM_DEDECATED_VECTOR_TABLE_SECTION IRQ_FUN NewVectorTable[64]; // 10000000
RAM_USER_IRQ_FUN_TABLE_SECTION IRQ_FUN UserIrqFunTable[64]; // 10000100
RAM_USER_IRQ_DATA_TABLE_SECTION u32 UserIrqDataTable[64]; // 10000200
/* ROM + ... */
HAL_RAM_BSS_SECTION PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter; // 10000354
/* ROM + hal_ssi.h */
HAL_RAM_BSS_SECTION u32 SSI_DBG_CONFIG; // 10000350
/* ROM + hal_timer.h & .. */
HAL_RAM_BSS_SECTION u32 gTimerRecord; // 1000034C
HAL_RAM_BSS_SECTION u16 GPIOState[11]; // 10000334
HAL_RAM_BSS_SECTION HAL_TIMER_OP HalTimerOp; // 10000318
/* ROM + diag.h */
HAL_RAM_BSS_SECTION u32 ConfigDebugErr; // 10000314
HAL_RAM_BSS_SECTION u32 ConfigDebugInfo; // 10000310
HAL_RAM_BSS_SECTION u32 ConfigDebugWarn; // 1000030C
HAL_RAM_BSS_SECTION u32 CfgSysDebugErr; // 10000308
HAL_RAM_BSS_SECTION u32 CfgSysDebugInfo; // 10000304
HAL_RAM_BSS_SECTION u32 CfgSysDebugWarn; // 10000300
/* ROM + rtl8195a_timer.c */
SECTION_RAM_TIMER2TO7_VECTOR_TABLE IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM]; // 10000358 Timer2To7VectorTable[6] !
/* ROM + Rand() */
INFRA_RAM_BSS_SECTION u32 _rand_z4, _rand_z3, _rand_z2, _rand_z1, _rand_first; // 10000370..
/* ROM + RTL_CONSOL */
MON_RAM_BSS_SECTION u8 *ArgvArray[MAX_ARGV]; // 100006AC *ArgvArray[10] !
MON_RAM_BSS_SECTION u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN]; // 10000430 UartLogHistoryBuf[5][127] !
MON_RAM_BSS_SECTION volatile UART_LOG_CTL UartLogCtl; // 10000408
/* = {
.NewIdx = 0,
.SeeIdx = 0,
.RevdNo = UART_LOG_HISTORY_LEN,
.EscSTS = 0,
.ExecuteCmd = 0,
.ExecuteEsc = 0,
.BootRdy = 0,
.Resvd = 0,
.pTmpLogBuf = &UartLogBuf,
.pfINPUT = (void*) &DiagPrintf,
.pCmdTbl = (PCOMMAND_TABLE) &UartLogRomCmdTable,
.CmdTblSz = 6,
.CRSTS = 0,
.pHistoryBuf = &UartLogHistoryBuf,
.TaskRdy = 0
// .Sema
}; */
MON_RAM_BSS_SECTION UART_LOG_BUF UartLogBuf; // 10000388
MON_RAM_BSS_SECTION volatile UART_LOG_CTL *pUartLogCtl = &UartLogCtl; // 10000384
/* ROM + LIB C */
LIBC_RAM_BSS_SECTION int __rtl_errno; // 10000bc4 __rtl_sread_v1_00(), __rtl_write_v1_00(), __rtl_lseek_v1_00(), __rtl_close_v1_00(), __rtl_sbrk_v1_00()..
LIBC_RAM_BSS_SECTION struct mallinfo __rtl_malloc_current_mallinfo; // 10000b9c __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION u32 __rtl_malloc_max_total_mem; // 10000b98 __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION u32 __rtl_malloc_max_sbrked_mem; // 10000b94 __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION u8 * __rtl_malloc_sbrk_base; // 10000b90 __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION u32 __rtl_malloc_top_pad; // 10000b8c __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION u32 __rtl_malloc_trim_threshold; // 10000b88 __rom_mallocr_init_v1_00()
LIBC_RAM_BSS_SECTION struct malloc_chunk *__rtl_malloc_av_[258]; // 0x10000780 __rom_mallocr_init_v1_00(), _rtl_free_r_v1_00()..
LIBC_RAM_BSS_SECTION __attribute__((aligned(0x10))) struct _rom_libgloss_ram_map rom_libgloss_ram_map; // 10000760
// 10000BA0..10000BC0: 9 x dw __rom_mallocr_init_v1_00()
/* ROM: ROM_odm_FalseAlarmCounterStatistics() + .. */
#define _WLAN_RAM_MAP_SECTION __attribute__((__section__(".ram.rom.wlanmap")))
_WLAN_RAM_MAP_SECTION CFO_TRACKING DM_CfoTrack; // 10000738
_WLAN_RAM_MAP_SECTION ROM_INFO ROMInfo; // 10000720
_WLAN_RAM_MAP_SECTION __attribute__((aligned(0x10))) FALSE_ALARM_STATISTICS FalseAlmCnt; // 100006E0
WLAN_RAM_MAP_SECTION struct _rom_wlan_ram_map rom_wlan_ram_map; // 100006D4
#ifndef PRESENT_IMAGE1
/* IMAGE1 HEAD */
START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__;
/*
START_RAM_FUN_A_SECTION RAM_START_FUNCTION gRamStartFun; // 10000bc8 = { PreProcessForVendor + 1 };
START_RAM_FUN_B_SECTION RAM_START_FUNCTION gRamPatchWAKE; // 10000bcc = { RtlBootToSram + 1 };
START_RAM_FUN_C_SECTION RAM_START_FUNCTION gRamPatchFun0; // 10000bd0 = { RtlBootToSram + 1 };
START_RAM_FUN_D_SECTION RAM_START_FUNCTION gRamPatchFun1; // 10000bd4 = { RtlBootToSram + 1 };
START_RAM_FUN_E_SECTION RAM_START_FUNCTION gRamPatchFun2; // 10000bd8 = { RtlBootToSram + 1 };
*/
#endif
IMAGE1_VALID_PATTEN_SECTION uint8 RAM_IMG1_VALID_PATTEN[8] = IMG1_VALID_PATTEN_INIT(); // 10000bdc
//#ifdef NOT_USE_LIBROM_A
/* ROM + hal_sdr_controller.c */
//HAL_FLASH_DATA_SECTION
//SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // SpicInitParaAllClk[3][6] !
/* ROM + hal_sdr_controller.c */
HAL_CUT_B_RAM_DATA_SECTION DRAM_INFO SdrDramDev = DRAM_INFO_INIT(); // 10001c4c
HAL_CUT_B_RAM_DATA_SECTION DRAM_MODE_REG_INFO SdrDramModeReg = DRAM_MODE_REG_INFO_INIT(); // 10001c30
HAL_CUT_B_RAM_DATA_SECTION DRAM_TIMING_INFO SdrDramTiming = DRAM_TIMING_INFO_INIT(); // 10001bfc
HAL_CUT_B_RAM_DATA_SECTION DRAM_DEVICE_INFO SdrDramInfo = DRAM_DEVICE_INFO_INIT(); // 10001be8
HAL_CUT_B_RAM_DATA_SECTION u32 AvaWds[2][REC_NUM]; // 10000be8
/* ROM + hal_sdr_controller.c: Sdr_Rand2() */
HAL_CUT_B_RAM_DATA_SECTION u32 rand_x = 123456789; // 10000be4
#define RTL_REENT_INIT(var) \
{ 0, \
&(var).__sf[0], \
&(var).__sf[1], \
&(var).__sf[2], \
0, \
"", \
0, \
0x0437DC, \
0, \
_NULL, \
_NULL, \
0, \
_NULL, \
_NULL, \
0, \
_NULL, \
{ \
{ \
0, \
_NULL, \
"", \
{0, 0, 0, 0, 0, 0, 0, 0, 0}, \
0, \
1, \
{ \
{_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, \
{_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, \
_RAND48_ADD \
}, \
{0, {0}}, \
{0, {0}}, \
{0, {0}}, \
"", \
"", \
0, \
{0, {0}}, \
{0, {0}}, \
{0, {0}}, \
{0, {0}}, \
{0, {0}} \
} \
}, \
_REENT_INIT_ATEXIT \
_NULL, \
{_NULL, 0, _NULL} \
}
// ROM: _rtl_impure_ptr + impure_reent in lib_rom.a ".hal.ram.data"
__attribute__((section(".libc.reent"))) struct _reent impure_reent = RTL_REENT_INIT(impure_reent); // 10001c60
__attribute__((section(".libc.reent"))) struct _reent * _rtl_impure_ptr = { &impure_reent }; // 10001c68
/* ROM ? */
__attribute__((__section__(".rom.unc.data"))) u32 _rom_unc_data[9]; // 100020e8
/* ROM + hal_sdr_controller.c: Sdr_Rand2() */
__attribute__((__section__(".sdr.rand2.data"))) u32 _sdr_rnd2_c = 7654321, _sdr_rnd2_z = 521288629, _sdr_rnd2_y = 362436;
// 100020BC, 100020B8, 100020B4
HAL_GPIO_ADAPTER PINMUX_RAM_DATA_SECTION gBoot_Gpio_Adapter; // 100020C0 [300=0x12c]
//SPIC_INIT_PARA HAL_FLASH_DATA_SECTION SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90]
#ifndef PRESENT_IMAGE2
IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0; //= { InfraStart + 1 };
#endif
IMAGE2_VALID_PATTEN_SECTION _RAM_IMG2_VALID_PATTEN RAM_IMG2_VALID_PATTEN = RAM_IMG2_VALID_PATTEN_INIT();

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/*
* BootLoader Ver 0.2
* Created on: 12/02/2017
* Author: pvvx
*/
#include "platform_autoconf.h"
#include "rtl_bios_data.h"
#include "diag.h"
#include "rtl8195a/rtl8195a_sys_on.h"
#include "hal_spi_flash.h"
//-------------------------------------------------------------------------
// Data declarations
#ifndef DEFAULT_BAUDRATE
#define DEFAULT_BAUDRATE 38400
#endif
/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
#define DEFAULT_BOOT_CLK_CPU 1 // Warning! If Start CLK > 100 MHz -> Errors SPIC function in Ameba SDK!
#ifdef DEFAULT_BOOT_CLK_CPU
#if DEFAULT_BOOT_CLK_CPU < 6
#define DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3 0
#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE DEFAULT_BOOT_CLK_CPU
#else
#define DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3 1
#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE (DEFAULT_BOOT_CLK_CPU-6)
#endif
#endif // DEFAULT_BOOT_CLK_CPU
#define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text")))
//-------------------------------------------------------------------------
typedef struct _seg_header {
uint32 size;
uint32 ldaddr;
} IMGSEGHEAD, *PIMGSEGHEAD;
typedef struct _img2_header {
IMGSEGHEAD seg;
uint32 sign[2];
void (*startfunc)(void);
uint8 rtkwin[7];
uint8 ver[13];
uint8 name[32];
} IMG2HEAD, *PIMG2HEAD;
#ifndef FLASH_SECTOR_SIZE
#define FLASH_SECTOR_SIZE 4096
#endif
//-------------------------------------------------------------------------
// Function declarations
LOCAL void RtlBootToFlash(void); // image1
LOCAL void RtlBoot1ToSram(void); // image1
LOCAL void RtlBoot2ToSram(void); // image1
LOCAL void RtlBoot3ToSram(void); // image1
LOCAL void RtlBoot4ToSram(void); // image1
extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType);
extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP);
extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID);
extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID);
//extern _LONG_CALL_ VOID DramInit_rom(IN DRAM_DEVICE_INFO *DramInfo);
//extern _LONG_CALL_ u32 SdrCalibration_rom(VOID);
extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo);
extern _LONG_CALL_ u32 SpicCmpDataForCalibrationRtl8195A(void); // compare read_data and golden_data
//extern _LONG_CALL_ VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); // wait spi-flash status register[0] = 0
//extern _LONG_CALL_ VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
//extern _LONG_CALL_ VOID RtlConsolInit(IN u32 Boot, IN u32 TBLSz, IN VOID *pTBL);
//#pragma arm section code = ".boot.text";
//#pragma arm section rodata = ".boot.rodata", rwdata = ".boot.data", zidata = ".boot.bss";
typedef void (*START_FUNC)(void);
//-------------------------------------------------------------------------
/* Start table: */
START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = {
RtlBootToFlash + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
RtlBoot1ToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 )
RtlBoot2ToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 )
RtlBoot3ToSram + 1, // PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
RtlBoot4ToSram + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
//-------------------------------------------------------------------------
/* Set Debug Flags */
LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
#if CONFIG_DEBUG_LOG > 3
CfgSysDebugWarn = -1;
CfgSysDebugInfo = -1;
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
ConfigDebugInfo = -1;
ConfigDebugErr = -1;
#elif CONFIG_DEBUG_LOG > 1
CfgSysDebugWarn = -1;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
// ConfigDebugInfo = 0;
ConfigDebugErr = -1;
#elif CONFIG_DEBUG_LOG > 0
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
ConfigDebugErr = -1;
#else
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
// CfgSysDebugErr = 0;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
// ConfigDebugErr = 0;
#endif
}
/* JTAG On */
LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
ACTCK_VENDOR_CCTRL(ON);
SLPCK_VENDOR_CCTRL(ON);
HalPinCtrlRtl8195A(JTAG, 0, 1);
}
/* GetChipId() */
LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
uint8 ChipId = CHIP_ID_8710AF;
if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
&ChipId, L25EOUTVOLTAGE) != 1)
DBG_8195A("Get Chip ID Failed\r");
return ChipId;
}
/*
* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
* (0.005/5)*166666666 = 166666.666 Tcpu
*/
LOCAL void INFRA_START_SECTION loguart_wait_tx_fifo_empty(void) {
if (HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_LOG_UART_EN) {
int x = 16384;
while ((!(HAL_READ8(LOG_UART_REG_BASE, 0x14) & BIT6)) && x--)
; // иначе глючит LogUART, если переключение CLK приходится на вывод символов !
}
}
extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90]
LOCAL uint32 InitTabParaAllClk[3 * CPU_CLK_TYPE_NO] = {
// SIO
0x01310102, // 72t/byte
0x03310101, // 0201 - 40t, 0101 - 39t, 0102 - 72t, 0103 - 104t
0x05310001, // 39t
0x07310001,
0x09310001,
0x0B310001,
// DIO
0x11311301, // BaudRate = 1, RdDummyCyle = 19, DelayLine = 63, DIO
0x13311201, // 1201 - 36t
0x15311101, // 1101 - 35t
0x17311101,
0x19311101,
0x1B311101
// QIO
/* MXIC Flash only DIO!
0x21311301, // BaudRate = 1, RdDummyCyle = 19, DelayLine = 63, DIO
0x23311201, // 1201 - 36t
0x25311101, // 1101 - 35t
0x27311101,
0x29311101,
0x2B311101
*/
};
struct spic_table_flash_type {
uint8 cmd[12];
uint8 strlr2;
uint8 fbaud;
uint8 addrlen;
uint8 fsize;
uint32 contrl;
uint16 validcmd[3];
uint8 manufacturerid;
uint8 memorytype;
};
//PSPIC_INIT_PARA pSpicInitPara;
struct spic_table_flash_type spic_table_flash = {
{ // for FLASH MX25L8006E/1606E
FLASH_CMD_FREAD, // REG_SPIC_READ_FAST_SINGLE 0x400060E0 0x0B
FLASH_CMD_DREAD, // REG_SPIC_READ_DUAL_DATA 0x400060E4 0x3B
FLASH_CMD_DREAD, // REG_SPIC_READ_DUAL_ADDR_DATA 0x400060E8 0x3B ?
FLASH_CMD_QREAD, // REG_SPIC_READ_QUAD_DATA 0x400060EC 0x6B
FLASH_CMD_4READ, // REG_SPIC_READ_QUAD_ADDR_DATA 0x400060F0 0xEB ?
FLASH_CMD_PP, // REG_SPIC_WRITE_SIGNLE 0x400060F4 0x02
FLASH_CMD_DPP, // REG_SPIC_WRITE_DUAL_DATA 0x400060F8 0xA2
FLASH_CMD_DPP, // REG_SPIC_WRITE_DUAL_ADDR_DATA 0x400060FC 0xA2 ?
FLASH_CMD_QPP, // REG_SPIC_WRITE_QUAD_DATA 0x40006100 0x32
FLASH_CMD_4PP, // REG_SPIC_WRITE_QUAD_ADDR_DATA 0x40006104 0x38
FLASH_CMD_WREN, // REG_SPIC_WRITE_ENABLE 0x40006108 0x06
FLASH_CMD_RDSR // REG_SPIC_READ_STATUS 0x4000610C 0x05
},
BIT_FIFO_ENTRY(5) | BIT_SO_DUM, // REG_SPIC_CTRLR2 0x40006110 0x51
BIT_FSCKDV(1), // REG_SPIC_FBAUDR 0x40006114 0x01
BIT_ADDR_PHASE_LENGTH(3), // REG_SPIC_ADDR_LENGTH 0x40006118 0x03
BIT_FLASE_SIZE(0x0F), // REG_SPIC_FLASE_SIZE 0x40006124 0x0E ?
BIT_CS_H_WR_DUM_LEN(2)| BIT_AUTO_ADDR__LENGTH(3) | BIT_RD_DUMMY_LENGTH(0x0), // REG_SPIC_AUTO_LENGTH 0x4000611C 0x20030001 ?
{
BIT_WR_BLOCKING, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode
BIT_WR_BLOCKING | BIT_RD_DUAL_I, // REG_SPIC_VALID_CMD 0x40006120 0x202 SpicDualBitMode
BIT_WR_BLOCKING | BIT_RD_DUAL_I, // REG_SPIC_VALID_CMD 0x40006120 0x202 SpicDualBitMode
// BIT_WR_BLOCKING | BIT_RD_QUAD_O, // REG_SPIC_VALID_CMD 0x40006120 0x208 SpicQuadBitMode MXIC not QIO
},
0xC2, 0x20 // MX25L8006/MX25L1606
};
LOCAL int BOOT_RAM_TEXT_SECTION SetSpicBitMode(uint8 BitMode) {
PSPIC_INIT_PARA pspic = &SpicInitParaAllClk[BitMode][((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7)];
if(pspic->Mode.Valid) {
// Disable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
HAL_SPI_WRITE32(REG_SPIC_VALID_CMD, spic_table_flash.validcmd[pspic->Mode.BitMode]);
HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, (HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH) & 0xFFFF0000) | pspic->RdDummyCyle);
HAL_SPI_WRITE32(REG_SPIC_BAUDR, pspic->BaudRate);
FLASH_DDL_FCTRL(pspic->DelayLine); // SPI_DLY_CTRL_ADDR [7:0]
// Enable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN);
}
SPI_FLASH_PIN_FCTRL(ON);
// Test Read Pattern
if(!SpicCmpDataForCalibrationRtl8195A()) {
FLASH_DDL_FCTRL(0x31); // SPI_DLY_CTRL_ADDR [7:0]
for(uint8 BaudRate = 1; BaudRate < 4; BaudRate++) {
for(uint8 RdDummyCyle = 0; RdDummyCyle < 63; RdDummyCyle++) {
// Disable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, (HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH) & 0xFFFF0000) | RdDummyCyle);
HAL_SPI_WRITE32(REG_SPIC_BAUDR, BaudRate);
// Enable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN);
// HAL_SPI_WRITE32(REG_SPIC_FLUSH_FIFO, 1);
if(SpicCmpDataForCalibrationRtl8195A()) {
DiagPrintf("Spic reinit %d:%d\n", BaudRate, RdDummyCyle);
pspic->BaudRate = BaudRate;
pspic->RdDummyCyle = RdDummyCyle;
pspic->DelayLine = 0x31;
pspic->Mode.Valid = 1;
return 1;
};
};
};
return 0;
};
return 1;
}
void BOOT_RAM_TEXT_SECTION InitSpicFlashType(struct spic_table_flash_type *ptable_flash) {
u8 * ptrb = &ptable_flash->cmd;
volatile u32 * ptrreg = (volatile u32 *)(SPI_FLASH_CTRL_BASE + REG_SPIC_READ_FAST_SINGLE);// 0x400060E0
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0); // Disable SPI_FLASH User Mode
do {
*ptrreg++ = *ptrb++;
} while(ptrb < (u8 *)(&ptable_flash->fsize));
ptrreg[0] = ptable_flash->contrl;
ptrreg[1] = ptable_flash->validcmd[SpicOneBitMode];
ptrreg[2] = ptable_flash->fsize;
HAL_SPI_WRITE32(REG_SPIC_SER, BIT_SER);
}
LOCAL int BOOT_RAM_TEXT_SECTION InitSpic(uint8 SpicBitMode) {
_memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk));
uint32 * ptr = InitTabParaAllClk;
uint8 x;
for(x = 0; x < SpicMaxMode; x++) {
*(uint32 *)&SpicInitParaAllClk[SpicOneBitMode][x].BaudRate = ptr[0];
*(uint32 *)&SpicInitParaAllClk[SpicDualBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO];
*(uint32 *)&SpicInitParaAllClk[SpicQuadBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO]; // MXIC not QIO
ptr++;
}
ACTCK_FLASH_CCTRL(1);
SLPCK_FLASH_CCTRL(1);
HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
InitSpicFlashType(&spic_table_flash);
return SetSpicBitMode(SpicBitMode);
}
/* SYSPlatformInit */
LOCAL void INFRA_START_SECTION SYSPlatformInit(void) {
__asm__ __volatile__ ("cpsid f\n");
JtagOn();
SetDebugFlgs();
//----- SYS Init
HAL_SYS_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0,
(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0) & (~(BIT_MASK_SYS_EEROM_LDO_PAR_07_04 << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04))) | BIT_SYS_EEROM_LDO_PAR_07_04(6)); // & 0xF0FFFFFF | 0x6000000
HAL_SYS_CTRL_WRITE32(REG_SYS_XTAL_CTRL1,
(HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1) & (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1))) | BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8;
//----- SDIO_Device_Off
HAL_PERI_ON_WRITE32(REG_PESOC_HCI_CLK_CTRL0,
HAL_PERI_ON_READ32(REG_PESOC_HCI_CLK_CTRL0) & (~BIT_SOC_ACTCK_SDIO_DEV_EN));
HAL_PERI_ON_WRITE32(REG_SOC_HCI_COM_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_HCI_COM_FUNC_EN) & (~(BIT_SOC_HCI_SDIOD_ON_EN | BIT_SOC_HCI_SDIOD_OFF_EN)));
HAL_PERI_ON_WRITE32(REG_HCI_PINMUX_CTRL,
HAL_PERI_ON_READ32(REG_HCI_PINMUX_CTRL) & (~(BIT_HCI_SDIOD_PIN_EN)));
//----- GPIO Adapter
extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
_memset(&gBoot_Gpio_Adapter, 0, sizeof(gBoot_Gpio_Adapter));
_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
#ifdef DEFAULT_BOOT_CLK_CPU
//----- CLK CPU
loguart_wait_tx_fifo_empty(); // иначе глючит LogUART, если переключение CLK приходится на вывод символов !
#if DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3
// 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz
HalCpuClkConfig(DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE);
*((int *)(SYSTEM_CTRL_BASE+REG_SYS_SYSPLL_CTRL1)) |= (1<<17);// REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3
#else
// 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
*((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3
HalCpuClkConfig(DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE);
#endif // CPU_CLOCK_SEL_DIV5_3
#endif // DEFAULT_CLK_CPU
//----- System
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
HalInitPlatformLogUartV02(); // Show "<RTL8195A>"... :(
HalInitPlatformTimerV02();
__asm__ __volatile__ ("cpsie f\n");
}
/*-------------------------------------------------------------------------------------
Копирует данные из области align(4) (flash, registers, ...) в область align(1) (ram)
--------------------------------------------------------------------------------------*/
LOCAL unsigned int BOOT_RAM_TEXT_SECTION flashcpy(unsigned int faddr,
void *dist, unsigned int size) {
union {
unsigned char uc[4];
unsigned int ud;
} tmp;
if (faddr < SPI_FLASH_BASE)
faddr += SPI_FLASH_BASE;
unsigned char * pd = (unsigned char *) dist;
unsigned int *p = (unsigned int *) ((unsigned int) faddr & (~3));
unsigned int xlen = (unsigned int) faddr & 3;
unsigned int len = size;
if (xlen) {
tmp.ud = *p++;
while (len) {
len--;
*pd++ = tmp.uc[xlen++];
if (xlen & 4)
break;
};
};
xlen = len >> 2;
while (xlen) {
tmp.ud = *p++;
*pd++ = tmp.uc[0];
*pd++ = tmp.uc[1];
*pd++ = tmp.uc[2];
*pd++ = tmp.uc[3];
xlen--;
};
if (len & 3) {
tmp.ud = *p;
pd[0] = tmp.uc[0];
if (len & 2) {
pd[1] = tmp.uc[1];
if (len & 1) {
pd[2] = tmp.uc[2];
};
};
};
return size;
}
typedef enum {
SEG_ID_ERR,
SEG_ID_SRAM,
SEG_ID_TCM,
SEG_ID_SDRAM,
SEG_ID_SOC,
SEG_ID_FLASH,
SEG_ID_CPU,
SEG_ID_ROM,
SEG_ID_MAX
} _SEG_ID;
LOCAL const char * const txt_tab_seg[] = {
"UNK", // 0
"SRAM", // 1
"TCM", // 2
"SDRAM", // 3
"SOC", // 4
"FLASH", // 5
"CPU", // 6
"ROM" // 7
};
LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000,
0x20000000, 0x30000000, 0x30200000, 0x40000000, 0x40800000, 0x98000000,
0xA0000000, 0xE0000000, 0xE0010000, 0x00000000, 0x00050000 };
LOCAL uint32 BOOT_RAM_TEXT_SECTION get_seg_id(uint32 addr, int32 size) {
uint32 ret = SEG_ID_ERR;
uint32 * ptr = &tab_seg_def;
if (size > 0) {
do {
ret++;
if (addr >= ptr[0] && addr + size <= ptr[1]) {
return ret;
};
ptr += 2;
} while (ret < SEG_ID_MAX);
};
return 0;
}
LOCAL uint32 BOOT_RAM_TEXT_SECTION load_img2_head(uint32 faddr, PIMG2HEAD hdr) {
flashcpy(faddr, hdr, sizeof(IMG2HEAD));
uint32 ret = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
if (hdr->sign[1] == IMG_SIGN2_RUN) {
if (hdr->sign[0] == IMG_SIGN1_RUN) {
ret |= 1 << 9;
} else if (hdr->sign[0] == IMG_SIGN1_SWP) {
ret |= 1 << 8;
};
}
if (*(u32 *) (&hdr->rtkwin) == IMG2_SIGN_DW1_TXT) {
ret |= 1 << 10;
};
return ret;
}
LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
uint8 flgload) {
uint32 fnextaddr = faddr;
uint8 segnum = 0;
while (1) {
uint32 seg_id = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
if (flgload
&& (seg_id == SEG_ID_SRAM || seg_id == SEG_ID_TCM
|| seg_id == SEG_ID_SDRAM)) {
#if CONFIG_DEBUG_LOG > 1
DBG_8195A("Load Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n",
segnum, faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr,
hdr->seg.size);
#endif
fnextaddr += flashcpy(fnextaddr, hdr->seg.ldaddr, hdr->seg.size);
} else if (seg_id) {
#if CONFIG_DEBUG_LOG > 2
DBG_8195A("Skip Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n", segnum,
faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr, hdr->seg.size);
#endif
fnextaddr += hdr->seg.size;
} else {
break;
}
fnextaddr += flashcpy(fnextaddr, &hdr->seg, sizeof(IMGSEGHEAD));
segnum++;
}
return fnextaddr;
}
/*-------------------------------------------------------------------------------------
* 0 - default image (config data + 0), 1 - image N1, 2 - image N2, ...
--------------------------------------------------------------------------------------*/
LOCAL int BOOT_RAM_TEXT_SECTION loadUserImges(int imgnum) {
IMG2HEAD hdr;
int imagenum = 1;
uint32 faddr = 0xb000; // start image2 in flash
DBG_8195A("Selected Image %d.\n", imgnum);
while (1) {
faddr = (faddr + FLASH_SECTOR_SIZE - 1) & (~(FLASH_SECTOR_SIZE - 1));
uint32 img_id = load_img2_head(faddr, &hdr);
if ((img_id >> 8) > 4 || (uint8) img_id != 0) {
faddr = load_segs(faddr + 0x10, &hdr.seg, imagenum == imgnum);
if (imagenum == imgnum) {
// DBG_8195A("Image%d: %s\n", imgnum, hdr.name);
break;
}
imagenum++;
} else if (imagenum) {
DBG_8195A("No Image%d! Trying Image0...\n", imgnum);
// пробуем загрузить image по умолчанию, по записи в секторе установок
flashcpy(FLASH_SYSTEM_DATA_ADDR, &faddr, sizeof(faddr));
if (faddr < 0x8000000)
faddr += SPI_FLASH_BASE;
if (get_seg_id(faddr, 0x100) == SEG_ID_FLASH) {
imagenum = 0;
imgnum = 0;
} else {
DBG_8195A("No Image0!\n");
imagenum = -1;
break;
};
} else {
imagenum = -1;
break;
}
};
return imagenum;
}
//----- IsForceLoadDefaultImg2
LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) {
uint8 gpio_pin[4];
HAL_GPIO_PIN GPIO_Pin;
HAL_GPIO_PIN_STATE flg;
int result = 0;
flashcpy(FLASH_SYSTEM_DATA_ADDR + 0x08, &gpio_pin, sizeof(gpio_pin)); // config data + 8
// _pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
for (int i = 1; i; i--) {
uint8 x = gpio_pin[i];
result <<= 1;
if (x != 0xff) {
GPIO_Pin.pin_name = HAL_GPIO_GetIPPinName_8195a(x & 0x7F);
if (x & 0x80) {
GPIO_Pin.pin_mode = DIN_PULL_LOW;
flg = GPIO_PIN_HIGH;
} else {
GPIO_Pin.pin_mode = DIN_PULL_HIGH;
flg = GPIO_PIN_LOW;
}
HAL_GPIO_Init_8195a(&GPIO_Pin);
if (HAL_GPIO_ReadPin_8195a(&GPIO_Pin) == flg) {
result |= 1;
}
HAL_GPIO_DeInit_8195a(&GPIO_Pin);
}
}
// _pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL;
return result;
}
/* RTL Console ROM */
LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) {
// DiagPrintf("\r\nRTL Console ROM\r\n");
// RtlConsolInit(ROM_STAGE, (u32) 6, (void*) &UartLogRomCmdTable);
pUartLogCtl->RevdNo = UART_LOG_HISTORY_LEN;
pUartLogCtl->BootRdy = 1;
pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?';
pUartLogCtl->pTmpLogBuf->BufCount = 1;
pUartLogCtl->ExecuteCmd = 1;
RtlConsolTaskRom(pUartLogCtl);
}
/* Enter Image 1.5 */
LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
if (flg)
_memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
SYSPlatformInit();
if (!flg)
DBG_8195A("\r===== Enter FLASH-Boot ====\n");
else
DBG_8195A("\r===== Enter SRAM-Boot %d ====\n", flg);
#if CONFIG_DEBUG_LOG > 1
DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(),
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
#endif
uint8 ChipId = _Get_ChipId();
if (ChipId < CHIP_ID_8195AM) {
//----- SDRAM Off
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
} else {
//----- SDRAM On
LDO25M_CTRL(ON);
HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
(HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e));
SDR_PIN_FCTRL(ON);
};
if (!InitSpic(SpicDualBitMode)) {
DBG_8195A("Spic Init Error!\n");
RtlConsolRam();
};
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена?
// extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz
if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz
DBG_8195A("SDR Controller Init fail!\n");
RtlConsolRam();
}
#if 0 // Test SDRAM
else {
uint32 *ptr = SDR_SDRAM_BASE;
uint32 tt = 0x55AA55AA;
for (int i = 0; i < 512 * 1024; i++) {
ptr[i] = tt++;
};
tt = 0x55AA55AA;
for (int i = 0; i < 512 * 1024; i++) {
if (ptr[i] != tt) {
DBG_8195A("SDR err %p %p != %p!\n", &ptr[i], ptr[i], tt);
RtlConsolRam();
}
tt++;
};
DBG_8195A("SDR tst end\n");
};
#endif // test
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
};
if (!flg)
loadUserImges(IsForceLoadDefaultImg2() + 1);
if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
DBG_8195A("Invalid Image Signature!\n");
RtlConsolRam();
}
DBG_8195A("Img Sign: %s, Go @ 0x%08x\r\n", &__image2_validate_code__,
__image2_entry_func__);
__image2_entry_func__();
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot1ToSram(void) {
EnterImage15(1);
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot2ToSram(void) {
EnterImage15(2);
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot3ToSram(void) {
EnterImage15(3);
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot4ToSram(void) {
EnterImage15(4);
}
LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToFlash(void) {
EnterImage15(0);
}

387
USDK/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot_min.c Normal file
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@ -0,0 +1,387 @@
/*
* (SRAM) Debug BootLoader
* Created on: 12/02/2017
* Author: pvvx
*/
#include "platform_autoconf.h"
#include "rtl_bios_data.h"
#include "diag.h"
#include "rtl8195a/rtl8195a_sys_on.h"
//-------------------------------------------------------------------------
// Data declarations
//extern u32 STACK_TOP;
//extern volatile UART_LOG_CTL * pUartLogCtl;
#ifndef DEFAULT_BAUDRATE
#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
#endif
#define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text")))
//#define BOOT_RAM_RODATA_SECTION __attribute__((section(".boot.rodata")))
//#define BOOT_RAM_DATA_SECTION __attribute__((section(".boot.data")))
//#define BOOT_RAM_BSS_SECTION __attribute__((section(".boot.bss")))
//-------------------------------------------------------------------------
typedef struct _seg_header {
uint32 size;
uint32 ldaddr;
} IMGSEGHEAD, *PIMGSEGHEAD;
typedef struct _img2_header {
IMGSEGHEAD seg;
uint32 sign[2];
void (*startfunc)(void);
uint8 rtkwin[7];
uint8 ver[13];
uint8 name[32];
} IMG2HEAD, *PIMG2HEAD;
#ifndef FLASH_SECTOR_SIZE
#define FLASH_SECTOR_SIZE 4096
#endif
//-------------------------------------------------------------------------
// Function declarations
LOCAL void RtlBootToFlash(void); // image1
LOCAL void RtlBootToSram(void); // image1
LOCAL void EnterImage15(void); // image1
LOCAL void JtagOn(void); // image1
extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType);
extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP);
extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID);
extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID);
//#pragma arm section code = ".boot.text";
//#pragma arm section rodata = ".boot.rodata", rwdata = ".boot.data", zidata = ".boot.bss";
typedef void (*START_FUNC)(void);
/* Start table: */
START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = {
RtlBootToFlash + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
RtlBootToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 )
RtlBootToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 )
RtlBootToSram + 1,// PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
RtlBootToFlash + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
// EnterImage15 + 1}; // PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
/* Set Debug Flags */
LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
#if CONFIG_DEBUG_LOG > 3
CfgSysDebugWarn = -1;
CfgSysDebugInfo = -1;
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
ConfigDebugInfo = -1;
ConfigDebugErr = -1;
#elif CONFIG_DEBUG_LOG > 1
CfgSysDebugWarn = -1;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
// ConfigDebugInfo = 0;
ConfigDebugErr = -1;
#elif CONFIG_DEBUG_LOG > 0
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
ConfigDebugErr = -1;
#else
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
// CfgSysDebugErr = 0;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
// ConfigDebugErr = 0;
#endif
}
/* RTL Console ROM */
LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) {
// DiagPrintf("\r\nRTL Console ROM\r\n");
pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?';
pUartLogCtl->pTmpLogBuf->BufCount = 1;
pUartLogCtl->ExecuteCmd = 1;
RtlConsolTaskRom(pUartLogCtl);
}
/* JTAG On */
LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
ACTCK_VENDOR_CCTRL(ON);
SLPCK_VENDOR_CCTRL(ON);
HalPinCtrlRtl8195A(JTAG, 0, 1);
}
/* Enter Image 1.5 */
LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(void) {
SetDebugFlgs();
DBG_8195A(
"\n===== Enter SRAM-Boot ====\nImg Sign: %s, Go @ 0x%08x\r\n",
&__image2_validate_code__, __image2_entry_func__);
#if CONFIG_DEBUG_LOG > 2
DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(),
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
#endif
if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
DBG_MISC_ERR("Invalid Image Signature!\n");
RtlConsolRam();
}
__image2_entry_func__();
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToSram(void) {
JtagOn(); /* JTAG On */
_memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
__asm__ __volatile__ ("cpsid f\n");
HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1,
HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & ( ~BIT_SYS_SYSPLL_DIV5_3));
HalCpuClkConfig(2); // 41.666666 MHz
// HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) | BIT_SYS_SYSPLL_DIV5_3); // 50.000 MHz
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
HalInitPlatformLogUartV02();
HalInitPlatformTimerV02();
__asm__ __volatile__ ("cpsie f\n");
// SdrPowerOff();
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
SpicInitRtl8195AV02(1, 0); // StartupSpicBaudRate InitBaudRate 1, SpicBitMode 1 StartupSpicBitMode
EnterImage15();
}
/*-------------------------------------------------------------------------------------
Копирует данные из области align(4) (flash, registers, ...) в область align(1) (ram)
--------------------------------------------------------------------------------------*/
LOCAL unsigned int BOOT_RAM_TEXT_SECTION flashcpy(unsigned int faddr,
void *dist, unsigned int size) {
union {
unsigned char uc[4];
unsigned int ud;
} tmp;
if (faddr < SPI_FLASH_BASE)
faddr += SPI_FLASH_BASE;
unsigned char * pd = (unsigned char *) dist;
unsigned int *p = (unsigned int *) ((unsigned int) faddr & (~3));
unsigned int xlen = (unsigned int) faddr & 3;
unsigned int len = size;
if (xlen) {
tmp.ud = *p++;
while (len) {
len--;
*pd++ = tmp.uc[xlen++];
if (xlen & 4)
break;
};
};
xlen = len >> 2;
while (xlen) {
tmp.ud = *p++;
*pd++ = tmp.uc[0];
*pd++ = tmp.uc[1];
*pd++ = tmp.uc[2];
*pd++ = tmp.uc[3];
xlen--;
};
if (len & 3) {
tmp.ud = *p;
pd[0] = tmp.uc[0];
if (len & 2) {
pd[1] = tmp.uc[1];
if (len & 1) {
pd[2] = tmp.uc[2];
};
};
};
return size;
}
enum {
SEG_ID_ERR,
SEG_ID_SRAM,
SEG_ID_TCM,
SEG_ID_SDRAM,
SEG_ID_SOC,
SEG_ID_FLASH,
SEG_ID_CPU,
SEG_ID_ROM,
SEG_ID_MAX
} SEG_ID;
LOCAL const char * const txt_tab_seg[] = {
"UNK", // 0
"SRAM", // 1
"TCM", // 2
"SDRAM", // 3
"SOC", // 4
"FLASH", // 5
"CPU", // 6
"ROM" // 7
};
LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000,
0x20000000, 0x30000000, 0x30200000, 0x40000000, 0x40800000, 0x98000000,
0xA0000000, 0xE0000000, 0xE0010000, 0x00000000, 0x00050000 };
LOCAL uint32 BOOT_RAM_TEXT_SECTION get_seg_id(uint32 addr, int32 size) {
uint32 ret = SEG_ID_ERR;
uint32 * ptr = &tab_seg_def;
if (size > 0) {
do {
ret++;
if (addr >= ptr[0] && addr + size <= ptr[1]) {
return ret;
};
ptr += 2;
} while (ret < SEG_ID_MAX);
};
return 0;
}
LOCAL uint32 BOOT_RAM_TEXT_SECTION load_img2_head(uint32 faddr, PIMG2HEAD hdr) {
flashcpy(faddr, hdr, sizeof(IMG2HEAD));
uint32 ret = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
if (hdr->sign[1] == IMG_SIGN2_RUN) {
if (hdr->sign[0] == IMG_SIGN1_RUN) {
ret |= 1 << 9;
} else if (hdr->sign[0] == IMG_SIGN1_SWP) {
ret |= 1 << 8;
};
}
if (*(u32 *) (&hdr->rtkwin) == IMG2_SIGN_DW1_TXT) {
ret |= 1 << 10;
};
return ret;
}
LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
uint8 flgload) {
uint32 fnextaddr = faddr;
uint8 segnum = 0;
while (1) {
uint32 seg_id = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
if (flgload && (seg_id == SEG_ID_SRAM || seg_id == SEG_ID_TCM)) {
#if CONFIG_DEBUG_LOG > 1
DBG_8195A("Load Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n",
segnum, faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr,
hdr->seg.size);
#endif
fnextaddr += flashcpy(fnextaddr, hdr->seg.ldaddr, hdr->seg.size);
} else if (seg_id) {
#if CONFIG_DEBUG_LOG > 2
DBG_8195A("Skip Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n", segnum,
faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr, hdr->seg.size);
#endif
fnextaddr += hdr->seg.size;
} else {
break;
}
fnextaddr += flashcpy(fnextaddr, &hdr->seg, sizeof(IMGSEGHEAD));
segnum++;
}
return fnextaddr;
}
/*-------------------------------------------------------------------------------------
* 0 - default image (config data + 0), 1 - image N1, 2 - image N2, ...
--------------------------------------------------------------------------------------*/
LOCAL int BOOT_RAM_TEXT_SECTION loadUserImges(int imgnum) {
IMG2HEAD hdr;
int imagenum = 1;
uint32 faddr = 0xb000; // start image2 in flash
DBG_8195A("Selected Image %d.\n", imgnum);
while (1) {
faddr = (faddr + FLASH_SECTOR_SIZE - 1) & (~(FLASH_SECTOR_SIZE - 1));
uint32 img_id = load_img2_head(faddr, &hdr);
if ((img_id >> 8) > 4 || (uint8) img_id != 0) {
faddr = load_segs(faddr + 0x10, &hdr.seg, imagenum == imgnum);
if (imagenum == imgnum) {
// DBG_8195A("Image%d: %s\n", imgnum, hdr.name);
break;
}
imagenum++;
} else if (imagenum) {
DBG_8195A("No Image%d! Trying Image0...\n", imgnum);
// пробуем загрузить image по умолчанию, по записи в секторе установок
flashcpy(FLASH_SYSTEM_DATA_ADDR, &faddr, sizeof(faddr));
if (faddr < 0x8000000)
faddr += SPI_FLASH_BASE;
if (get_seg_id(faddr, 0x100) == SEG_ID_FLASH) {
imagenum = 0;
imgnum = 0;
} else {
DBG_8195A("No Image0!\n");
imagenum = -1;
break;
};
} else {
imagenum = -1;
break;
}
};
return imagenum;
}
;
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
//----- IsForceLoadDefaultImg2
LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) {
uint8 gpio_pin[4];
HAL_GPIO_PIN GPIO_Pin;
HAL_GPIO_PIN_STATE flg;
int result = 0;
flashcpy(FLASH_SYSTEM_DATA_ADDR + 0x08, &gpio_pin, sizeof(gpio_pin)); // config data + 8
_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
for (int i = 1; i; i--) {
uint8 x = gpio_pin[i];
result <<= 1;
if (x != 0xff) {
GPIO_Pin.pin_name = HAL_GPIO_GetIPPinName_8195a(x & 0x7F);
if (x & 0x80) {
GPIO_Pin.pin_mode = DIN_PULL_LOW;
flg = GPIO_PIN_HIGH;
} else {
GPIO_Pin.pin_mode = DIN_PULL_HIGH;
flg = GPIO_PIN_LOW;
}
HAL_GPIO_Init_8195a(&GPIO_Pin);
if (HAL_GPIO_ReadPin_8195a(&GPIO_Pin) == flg) {
result |= 1;
}
HAL_GPIO_DeInit_8195a(&GPIO_Pin);
}
}
_pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL;
return result;
}
LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToFlash(void) {
JtagOn(); /* JTAG On */
SetDebugFlgs();
DBG_8195A("===== Enter FLASH-Boot ====\n");
if (HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (1 << BIT_SOC_FLASH_EN)) {
SPI_FLASH_PIN_FCTRL(ON);
/*
if(!SpicCmpDataForCalibrationRtl8195A()) {
DBG_8195A("ReInit Spic DIO...\n");
SpicInitRtl8195AV02(1, SpicDualBitMode);
}
*/
loadUserImges(IsForceLoadDefaultImg2() + 1);
};
if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
DBG_8195A("Invalid Image Signature!\n");
RtlConsolRam();
} else
DBG_8195A("Go @ 0x%08x\r\n", __image2_entry_func__);
__image2_entry_func__();
}

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/*
* (SRAM) Debug BootLoader
* Created on: 12/02/2017
* Author: pvvx
*/
#include "platform_autoconf.h"
#include "rtl_bios_data.h"
#include "diag.h"
#include "rtl8195a/rtl8195a_sys_on.h"
//-------------------------------------------------------------------------
// Data declarations
//extern u32 STACK_TOP;
//extern volatile UART_LOG_CTL * pUartLogCtl;
#ifndef DEFAULT_BAUDRATE
#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
#endif
#define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text")))
//#define BOOT_RAM_RODATA_SECTION __attribute__((section(".boot.rodata")))
//#define BOOT_RAM_DATA_SECTION __attribute__((section(".boot.data")))
//#define BOOT_RAM_BSS_SECTION __attribute__((section(".boot.bss")))
//-------------------------------------------------------------------------
// Function declarations
LOCAL void RtlBootToSram(void); // image1
LOCAL void EnterImage15(void); // image1
LOCAL void JtagOn(void); // image1
extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType);
extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP);
extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID);
extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID);
//#pragma arm section code = ".boot.text";
//#pragma arm section rodata = ".boot.rodata", rwdata = ".boot.data", zidata = ".boot.bss";
typedef void (*START_FUNC)(void);
/* Start table: */
START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = {
RtlBootToSram + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
RtlBootToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 )
RtlBootToSram + 1, //- PatchFun0(), Run if ( v40000210 & 0x10000000 )
RtlBootToSram + 1, //+ PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
EnterImage15 + 1}; // PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
/* Set Debug Flags */
LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
#if CONFIG_DEBUG_LOG > 3
CfgSysDebugWarn = -1;
CfgSysDebugInfo = -1;
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
ConfigDebugInfo = -1;
ConfigDebugErr = -1;
#elif CONFIG_DEBUG_LOG > 1
CfgSysDebugWarn = -1;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
// ConfigDebugInfo = 0;
ConfigDebugErr = -1;
#elif CONFIG_DEBUG_LOG > 0
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
ConfigDebugErr = -1;
#else
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
// CfgSysDebugErr = 0;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
// ConfigDebugErr = 0;
#endif
}
/* RTL Console ROM */
LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) {
// DiagPrintf("\r\nRTL Console ROM\r\n");
pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?';
pUartLogCtl->pTmpLogBuf->BufCount = 1;
pUartLogCtl->ExecuteCmd = 1;
RtlConsolTaskRom(pUartLogCtl);
}
/* JTAG On */
LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
ACTCK_VENDOR_CCTRL(ON);
SLPCK_VENDOR_CCTRL(ON);
HalPinCtrlRtl8195A(JTAG, 0, 1);
}
/* Enter Image 1.5 */
LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(void) {
SetDebugFlgs();
DBG_8195A("\rCPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
DBG_8195A("==!== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\r\n",
&__image2_validate_code__, __image2_entry_func__);
if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
DBG_MISC_ERR("Invalid Image2 Signature!\n");
RtlConsolRam();
}
__image2_entry_func__();
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToSram(void) {
JtagOn(); /* JTAG On */
_memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
__asm__ __volatile__ ("cpsid f\n");
HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & ( ~BIT_SYS_SYSPLL_DIV5_3));
HalCpuClkConfig(2); // 41.666666 MHz
// HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) | BIT_SYS_SYSPLL_DIV5_3); // 50.000 MHz
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
HalInitPlatformLogUartV02();
HalInitPlatformTimerV02();
__asm__ __volatile__ ("cpsie f\n");
SpicInitRtl8195AV02(1, 0); // StartupSpicBaudRate InitBaudRate 1, SpicBitMode 1 StartupSpicBitMode
// HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & 0x1FFFFF); // Clear debug flags
EnterImage15();
}

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/*
* BootLoader
* Created on: 12/02/2017
* Author: pvvx
*/
#include "platform_autoconf.h"
#include "rtl_bios_data.h"
#include "diag.h"
#include "rtl8195a/rtl8195a_sys_on.h"
#include "hal_spi_flash.h"
//-------------------------------------------------------------------------
// Data declarations
#ifndef DEFAULT_BAUDRATE
#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
#endif
/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
#define DEFAULT_BOOT_CLK_CPU 8 // Warning! If Start CLK > 100 MHz -> Errors SPIC function in Ameba SDK!
#ifdef DEFAULT_BOOT_CLK_CPU
#if DEFAULT_BOOT_CLK_CPU < 6
#define DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3 0
#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE DEFAULT_BOOT_CLK_CPU
#else
#define DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3 1
#define DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE (DEFAULT_BOOT_CLK_CPU-6)
#endif
#endif // DEFAULT_BOOT_CLK_CPU
#define BOOT_RAM_TEXT_SECTION // __attribute__((section(".boot.text")))
//#define BOOT_RAM_RODATA_SECTION __attribute__((section(".boot.rodata")))
//#define BOOT_RAM_DATA_SECTION __attribute__((section(".boot.data")))
//#define BOOT_RAM_BSS_SECTION __attribute__((section(".boot.bss")))
//extern u32 STACK_TOP;
//extern volatile UART_LOG_CTL * pUartLogCtl;
extern void * UartLogRomCmdTable;
//-------------------------------------------------------------------------
typedef struct _seg_header {
uint32 size;
uint32 ldaddr;
} IMGSEGHEAD, *PIMGSEGHEAD;
typedef struct _img2_header {
IMGSEGHEAD seg;
uint32 sign[2];
void (*startfunc)(void);
uint8 rtkwin[7];
uint8 ver[13];
uint8 name[32];
} IMG2HEAD, *PIMG2HEAD;
#ifndef FLASH_SECTOR_SIZE
#define FLASH_SECTOR_SIZE 4096
#endif
//-------------------------------------------------------------------------
// Function declarations
LOCAL void RtlBootToFlash(void); // image1
LOCAL void RtlBoot1ToSram(void); // image1
LOCAL void RtlBoot2ToSram(void); // image1
LOCAL void RtlBoot3ToSram(void); // image1
LOCAL void RtlBoot4ToSram(void); // image1
//LOCAL void EnterImage15(void); // image1
//LOCAL void JtagOn(void); // image1
extern _LONG_CALL_ VOID HalCpuClkConfig(unsigned char CpuType);
extern _LONG_CALL_ VOID VectorTableInitRtl8195A(u32 StackP);
extern _LONG_CALL_ VOID HalInitPlatformLogUartV02(VOID);
extern _LONG_CALL_ VOID HalInitPlatformTimerV02(VOID);
//extern _LONG_CALL_ VOID DramInit_rom(IN DRAM_DEVICE_INFO *DramInfo);
//extern _LONG_CALL_ u32 SdrCalibration_rom(VOID);
extern _LONG_CALL_ int SdrControllerInit_rom(PDRAM_DEVICE_INFO pDramInfo);
extern _LONG_CALL_ u32 SpicCmpDataForCalibrationRtl8195A(void); // compare read_data and golden_data
extern _LONG_CALL_ VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara); // wait spi-flash status register[0] = 0
extern _LONG_CALL_ VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
extern _LONG_CALL_ VOID RtlConsolInit(IN u32 Boot, IN u32 TBLSz, IN VOID *pTBL);
//#pragma arm section code = ".boot.text";
//#pragma arm section rodata = ".boot.rodata", rwdata = ".boot.data", zidata = ".boot.bss";
typedef void (*START_FUNC)(void);
//-------------------------------------------------------------------------
/* Start table: */
START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ = {
RtlBootToFlash + 1, // StartFun(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
RtlBoot1ToSram + 1, // PatchWAKE(), Run if ( v40000210 & 0x20000000 )
RtlBoot2ToSram + 1, // PatchFun0(), Run if ( v40000210 & 0x10000000 )
RtlBoot3ToSram + 1, // PatchFun1(), Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
RtlBoot4ToSram + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
//test RtlBootToFlash + 1 };// PatchFun2(), Run for Init console, if ( v40000210 & 0x4000000 )
//-------------------------------------------------------------------------
/* Set Debug Flags */
LOCAL void BOOT_RAM_TEXT_SECTION SetDebugFlgs() {
#if CONFIG_DEBUG_LOG > 3
CfgSysDebugWarn = -1;
CfgSysDebugInfo = -1;
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
ConfigDebugInfo = -1;
ConfigDebugErr = -1;
#elif CONFIG_DEBUG_LOG > 1
CfgSysDebugWarn = -1;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
ConfigDebugWarn = -1;
// ConfigDebugInfo = 0;
ConfigDebugErr = -1;
#elif CONFIG_DEBUG_LOG > 0
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
CfgSysDebugErr = -1;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
ConfigDebugErr = -1;
#else
// CfgSysDebugWarn = 0;
// CfgSysDebugInfo = 0;
// CfgSysDebugErr = 0;
// ConfigDebugWarn = 0;
// ConfigDebugInfo = 0;
// ConfigDebugErr = 0;
#endif
}
/* JTAG On */
LOCAL void BOOT_RAM_TEXT_SECTION JtagOn(void) {
ACTCK_VENDOR_CCTRL(ON);
SLPCK_VENDOR_CCTRL(ON);
HalPinCtrlRtl8195A(JTAG, 0, 1);
}
/* GetChipId() */
LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
uint8 ChipId = CHIP_ID_8710AF;
if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
&ChipId, L25EOUTVOLTAGE) != 1)
DBG_8195A("Get Chip ID Failed\r");
return ChipId;
}
/*
* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
* (0.005/5)*166666666 = 166666.666 Tcpu
*/
LOCAL void INFRA_START_SECTION loguart_wait_tx_fifo_empty(void) {
if (HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_LOG_UART_EN) {
int x = 16384;
while ((!(HAL_READ8(LOG_UART_REG_BASE, 0x14) & BIT6)) && x--)
; // иначе глючит LogUART, если переключение CLK приходится на вывод символов !
}
}
extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90]
LOCAL uint32 InitTabParaAllClk[3 * CPU_CLK_TYPE_NO] = {
0x01310102, // BaudRate = 2, RdDummyCyle = 2, DelayLine = 63, SIO
0x03310101, // 0201 - 40t, 0101 - 39t, 0102 - 72t, 0103 - 104t
0x05310001, // 39t
0x07310001,
0x09310001,
0x0B310001,
0x11311301, // BaudRate = 1, RdDummyCyle = 19, DelayLine = 63, DIO
0x13311201, // 1201 - 36t
0x15311101, // 1101 - 35t
0x17311101,
0x19311101,
0x1B311101,
0x21311301, // BaudRate = 1, RdDummyCyle = 19, DelayLine = 63, DIO
0x23311201, // 1201 - 36t
0x25311101, // 1101 - 35t
0x27311101,
0x29311101,
0x2B311101,
};
struct spic_table_flash_type {
uint8 cmd[12];
uint8 strlr2;
uint8 fbaud;
uint8 addrlen;
uint8 fsize;
uint32 contrl;
uint16 validcmd[3];
uint8 manufacturerid;
uint8 memorytype;
};
//PSPIC_INIT_PARA pSpicInitPara;
struct spic_table_flash_type spic_table_flash = {
{ // for FLASH MX25L8006E/1606E
FLASH_CMD_FREAD, // REG_SPIC_READ_FAST_SINGLE 0x400060E0 0x0B
FLASH_CMD_DREAD, // REG_SPIC_READ_DUAL_DATA 0x400060E4 0x3B
FLASH_CMD_DREAD, // REG_SPIC_READ_DUAL_ADDR_DATA 0x400060E8 0x3B ?
FLASH_CMD_QREAD, // REG_SPIC_READ_QUAD_DATA 0x400060EC 0x6B
FLASH_CMD_4READ, // REG_SPIC_READ_QUAD_ADDR_DATA 0x400060F0 0xEB ?
FLASH_CMD_PP, // REG_SPIC_WRITE_SIGNLE 0x400060F4 0x02
FLASH_CMD_DPP, // REG_SPIC_WRITE_DUAL_DATA 0x400060F8 0xA2
FLASH_CMD_DPP, // REG_SPIC_WRITE_DUAL_ADDR_DATA 0x400060FC 0xA2 ?
FLASH_CMD_QPP, // REG_SPIC_WRITE_QUAD_DATA 0x40006100 0x32
FLASH_CMD_4PP, // REG_SPIC_WRITE_QUAD_ADDR_DATA 0x40006104 0x38
FLASH_CMD_WREN, // REG_SPIC_WRITE_ENABLE 0x40006108 0x06
FLASH_CMD_RDSR // REG_SPIC_READ_STATUS 0x4000610C 0x05
},
BIT_FIFO_ENTRY(5) | BIT_SO_DUM, // REG_SPIC_CTRLR2 0x40006110 0x51
BIT_FSCKDV(1), // REG_SPIC_FBAUDR 0x40006114 0x01
BIT_ADDR_PHASE_LENGTH(3), // REG_SPIC_ADDR_LENGTH 0x40006118 0x03
BIT_FLASE_SIZE(0x0F), // REG_SPIC_FLASE_SIZE 0x40006124 0x0E ?
BIT_CS_H_WR_DUM_LEN(2)| BIT_AUTO_ADDR__LENGTH(3) | BIT_RD_DUMMY_LENGTH(0x0), // REG_SPIC_AUTO_LENGTH 0x4000611C 0x20030001 ?
{
BIT_WR_BLOCKING, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode
BIT_WR_BLOCKING | BIT_RD_DUAL_I, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode
BIT_WR_BLOCKING | BIT_RD_QUAD_O, // REG_SPIC_VALID_CMD 0x40006120 0x200 SpicOneBitMode
},
0xC2, 0x20 // MX25L8006/MX25L1606
};
LOCAL void BOOT_RAM_TEXT_SECTION InitSpicBdRDCDL(PSPIC_INIT_PARA pspic) {
// Disable SPI_FLASH User Mode
// HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
DBG_8195A("%p = %p, %p\n", 0x40006000+REG_SPIC_AUTO_LENGTH, HAL_SPI_READ32(REG_SPIC_BAUDR), pspic->RdDummyCyle);
HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, (HAL_SPI_READ32(REG_SPIC_AUTO_LENGTH) & 0xFFFF0000) | pspic->RdDummyCyle);
// DBG_8195A("%p = %p, %p\n", 0x40006000+REG_SPIC_SER, HAL_SPI_READ32(REG_SPIC_SER), BIT_SER);
// HAL_SPI_WRITE32(REG_SPIC_SER, BIT_SER);
FLASH_DDL_FCTRL(pspic->DelayLine); // SPI_DLY_CTRL_ADDR [7:0]
// DBG_8195A("%p = %p, %p\n", 0x40006000 + REG_SPIC_CTRLR1, HAL_SPI_READ32(REG_SPIC_CTRLR1), BIT_NDF(4));
// HAL_SPI_WRITE32(REG_SPIC_CTRLR1, BIT_NDF(4));
uint32 regval = HAL_SPI_READ32(REG_SPIC_CTRLR0)
& (~(BIT_CMD_CH(3) | BIT_DATA_CH(3) | BIT_ADDR_CH(3)));
if(pspic->Mode.BitMode == SpicDualBitMode) {
regval |= BIT_ADDR_CH(1) | BIT_DATA_CH(1);
}
else if(pspic->Mode.BitMode == SpicQuadBitMode) {
regval |= BIT_ADDR_CH(2) | BIT_DATA_CH(2);
}
DBG_8195A("%p = %p, %p\n", 0x40006000+REG_SPIC_CTRLR0, HAL_SPI_READ32(REG_SPIC_CTRLR0), regval);
HAL_SPI_WRITE32(REG_SPIC_CTRLR0, regval);
DBG_8195A("%p = %p, %p\n", 0x40006000+REG_SPIC_VALID_CMD, HAL_SPI_READ32(REG_SPIC_VALID_CMD), spic_table_flash.validcmd[pspic->Mode.BitMode]);
HAL_SPI_WRITE32(REG_SPIC_VALID_CMD, spic_table_flash.validcmd[pspic->Mode.BitMode]);
DBG_8195A("%p = %p, %p\n", 0x40006000+REG_SPIC_BAUDR, HAL_SPI_READ32(REG_SPIC_BAUDR), pspic->BaudRate);
HAL_SPI_WRITE32(REG_SPIC_BAUDR, pspic->BaudRate); // & 0x00000FFF));
// Enable SPI_FLASH User Mode
// HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN);
// SpicWaitWipDoneRtl8195A(SpicInitParaAllClk[1][0]);
}
void BOOT_RAM_TEXT_SECTION InitSpicFlashType(struct spic_table_flash_type *ptable_flash) {
u8 * ptrb = &ptable_flash->cmd;
volatile u32 * ptrreg = (volatile u32 *)(SPI_FLASH_CTRL_BASE + REG_SPIC_READ_FAST_SINGLE);// 0x400060E0
do {
DBG_8195A("%p = %p, %p\n", ptrreg, *ptrreg, *ptrb);
*ptrreg++ = *ptrb++;
} while(ptrb < (u8 *)(&ptable_flash->fsize));
DBG_8195A("%p = %p, %p\n", ptrreg, *ptrreg, ptable_flash->contrl);
ptrreg[0] = ptable_flash->contrl;
DBG_8195A("%p = %p, %p\n", &ptrreg[1], ptrreg[1], ptable_flash->validcmd[SpicOneBitMode]);
ptrreg[1] = ptable_flash->validcmd[SpicOneBitMode];
DBG_8195A("%p = %p, %p\n", &ptrreg[2], ptrreg[2], ptable_flash->fsize);
ptrreg[2] = ptable_flash->fsize;
}
LOCAL int BOOT_RAM_TEXT_SECTION InitSpic(uint8 SpicBitMode) {
#if 0
// *(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x1311301; // patch
SpicInitRtl8195AV02(CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7),
SpicDualBitMode);
#else
// SpicInitRtl8195AV02(1, SpicDualBitMode); // SpicOneBitMode); // 5-168, 4-136, 3-104, 2-72, 1-
// InitSpicBdRDCDL(&SpicInitParaAllClk[1][0]);
// SpicLoadInitParaFromClockRtl8195A(0, 1, &SpicInitParaAllClk[1][0]);
#endif
_memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk));
uint32 * ptr = InitTabParaAllClk;
uint8 x;
for(x = 0; x < SpicMaxMode; x++) {
*(uint32 *)&SpicInitParaAllClk[SpicOneBitMode][x].BaudRate = ptr[0];
*(uint32 *)&SpicInitParaAllClk[SpicDualBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO];
*(uint32 *)&SpicInitParaAllClk[SpicQuadBitMode][x].BaudRate = ptr[CPU_CLK_TYPE_NO + CPU_CLK_TYPE_NO];
ptr++;
}
ACTCK_FLASH_CCTRL(1);
SLPCK_FLASH_CCTRL(1);
// Disable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
InitSpicFlashType(&spic_table_flash);
InitSpicBdRDCDL(&SpicInitParaAllClk[SpicBitMode][((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7)]);
#if 0 // 72
HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, 0x20030002);
HAL_SPI_WRITE32(REG_SPIC_BAUDR, 2);
HAL_SPI_WRITE32(REG_SPIC_VALID_CMD, BIT_WR_BLOCKING);
#else // 36
// HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, 0x20030013);
// HAL_SPI_WRITE32(REG_SPIC_BAUDR, 1);
// HAL_SPI_WRITE32(REG_SPIC_VALID_CMD, BIT_WR_BLOCKING | BIT_RD_DUAL_I);
#endif
HAL_SPI_WRITE32(REG_SPIC_SER, BIT_SER);
SPI_FLASH_PIN_FCTRL(ON);
// Enable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN);
// if(!SpicCmpDataForCalibrationRtl8195A()) {
for(int i = 1; i < 4; i++) {
for(int x = 0; x < 63; x++) {
// Disable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
HAL_SPI_WRITE32(REG_SPIC_AUTO_LENGTH, 0x20030000 + x);
HAL_SPI_WRITE32(REG_SPIC_BAUDR, i);
// Enable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, BIT_SPIC_EN);
FLASH_DDL_FCTRL(49); // SPI_DLY_CTRL_ADDR [7:0]
// HAL_SPI_WRITE32(REG_SPIC_FLUSH_FIFO, 1);
if(SpicCmpDataForCalibrationRtl8195A()) {
DiagPrintf("Spic init %d:%d:49\n", i, x);
return 1;
};
};
};
return 0;
// };
// return 1;
}
/* SYSPlatformInit */
LOCAL void INFRA_START_SECTION SYSPlatformInit(void) {
__asm__ __volatile__ ("cpsid f\n");
JtagOn();
SetDebugFlgs();
//----- SYS Init
HAL_SYS_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0,
(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0) & (~(BIT_MASK_SYS_EEROM_LDO_PAR_07_04 << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04))) | BIT_SYS_EEROM_LDO_PAR_07_04(6)); // & 0xF0FFFFFF | 0x6000000
HAL_SYS_CTRL_WRITE32(REG_SYS_XTAL_CTRL1,
(HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1) & (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1))) | BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8;
//----- SDIO_Device_Off
HAL_PERI_ON_WRITE32(REG_PESOC_HCI_CLK_CTRL0,
HAL_PERI_ON_READ32(REG_PESOC_HCI_CLK_CTRL0) & (~BIT_SOC_ACTCK_SDIO_DEV_EN));
HAL_PERI_ON_WRITE32(REG_SOC_HCI_COM_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_HCI_COM_FUNC_EN) & (~(BIT_SOC_HCI_SDIOD_ON_EN | BIT_SOC_HCI_SDIOD_OFF_EN)));
HAL_PERI_ON_WRITE32(REG_HCI_PINMUX_CTRL,
HAL_PERI_ON_READ32(REG_HCI_PINMUX_CTRL) & (~(BIT_HCI_SDIOD_PIN_EN)));
//----- GPIO Adapter
extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
_memset(&gBoot_Gpio_Adapter, 0, sizeof(gBoot_Gpio_Adapter));
_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
#ifdef DEFAULT_BOOT_CLK_CPU
//----- CLK CPU
loguart_wait_tx_fifo_empty(); // иначе глючит LogUART, если переключение CLK приходится на вывод символов !
#if DEFAULT_BOOT_CPU_CLOCK_SEL_DIV5_3
// 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz
HalCpuClkConfig(DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE);
*((int *)(SYSTEM_CTRL_BASE+REG_SYS_SYSPLL_CTRL1)) |= (1<<17);// REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3
#else
// 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
*((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3
HalCpuClkConfig(DEFAULT_BOOT_CPU_CLOCK_SEL_VALUE);
#endif // CPU_CLOCK_SEL_DIV5_3
#endif // DEFAULT_CLK_CPU
//----- System
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
HalInitPlatformLogUartV02(); // Show "<RTL8195A>"... :(
HalInitPlatformTimerV02();
__asm__ __volatile__ ("cpsie f\n");
}
/*-------------------------------------------------------------------------------------
Копирует данные из области align(4) (flash, registers, ...) в область align(1) (ram)
--------------------------------------------------------------------------------------*/
LOCAL unsigned int BOOT_RAM_TEXT_SECTION flashcpy(unsigned int faddr,
void *dist, unsigned int size) {
union {
unsigned char uc[4];
unsigned int ud;
} tmp;
if (faddr < SPI_FLASH_BASE)
faddr += SPI_FLASH_BASE;
unsigned char * pd = (unsigned char *) dist;
unsigned int *p = (unsigned int *) ((unsigned int) faddr & (~3));
unsigned int xlen = (unsigned int) faddr & 3;
unsigned int len = size;
if (xlen) {
tmp.ud = *p++;
while (len) {
len--;
*pd++ = tmp.uc[xlen++];
if (xlen & 4)
break;
};
};
xlen = len >> 2;
while (xlen) {
tmp.ud = *p++;
*pd++ = tmp.uc[0];
*pd++ = tmp.uc[1];
*pd++ = tmp.uc[2];
*pd++ = tmp.uc[3];
xlen--;
};
if (len & 3) {
tmp.ud = *p;
pd[0] = tmp.uc[0];
if (len & 2) {
pd[1] = tmp.uc[1];
if (len & 1) {
pd[2] = tmp.uc[2];
};
};
};
return size;
}
enum {
SEG_ID_ERR,
SEG_ID_SRAM,
SEG_ID_TCM,
SEG_ID_SDRAM,
SEG_ID_SOC,
SEG_ID_FLASH,
SEG_ID_CPU,
SEG_ID_ROM,
SEG_ID_MAX
} SEG_ID;
LOCAL const char * const txt_tab_seg[] = {
"UNK", // 0
"SRAM", // 1
"TCM", // 2
"SDRAM", // 3
"SOC", // 4
"FLASH", // 5
"CPU", // 6
"ROM" // 7
};
LOCAL const uint32 tab_seg_def[] = { 0x10000000, 0x10070000, 0x1fff0000,
0x20000000, 0x30000000, 0x30200000, 0x40000000, 0x40800000, 0x98000000,
0xA0000000, 0xE0000000, 0xE0010000, 0x00000000, 0x00050000 };
LOCAL uint32 BOOT_RAM_TEXT_SECTION get_seg_id(uint32 addr, int32 size) {
uint32 ret = SEG_ID_ERR;
uint32 * ptr = &tab_seg_def;
if (size > 0) {
do {
ret++;
if (addr >= ptr[0] && addr + size <= ptr[1]) {
return ret;
};
ptr += 2;
} while (ret < SEG_ID_MAX);
};
return 0;
}
LOCAL uint32 BOOT_RAM_TEXT_SECTION load_img2_head(uint32 faddr, PIMG2HEAD hdr) {
flashcpy(faddr, hdr, sizeof(IMG2HEAD));
uint32 ret = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
if (hdr->sign[1] == IMG_SIGN2_RUN) {
if (hdr->sign[0] == IMG_SIGN1_RUN) {
ret |= 1 << 9;
} else if (hdr->sign[0] == IMG_SIGN1_SWP) {
ret |= 1 << 8;
};
}
if (*(u32 *) (&hdr->rtkwin) == IMG2_SIGN_DW1_TXT) {
ret |= 1 << 10;
};
return ret;
}
LOCAL uint32 BOOT_RAM_TEXT_SECTION load_segs(uint32 faddr, PIMG2HEAD hdr,
uint8 flgload) {
uint32 fnextaddr = faddr;
uint8 segnum = 0;
while (1) {
uint32 seg_id = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
if (flgload
&& (seg_id == SEG_ID_SRAM || seg_id == SEG_ID_TCM
|| seg_id == SEG_ID_SDRAM)) {
#if CONFIG_DEBUG_LOG > 1
DBG_8195A("Load Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n",
segnum, faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr,
hdr->seg.size);
#endif
fnextaddr += flashcpy(fnextaddr, hdr->seg.ldaddr, hdr->seg.size);
} else if (seg_id) {
#if CONFIG_DEBUG_LOG > 2
DBG_8195A("Skip Flash seg%d: 0x%08x -> %s: 0x%08x, size: %d\n", segnum,
faddr, txt_tab_seg[seg_id], hdr->seg.ldaddr, hdr->seg.size);
#endif
fnextaddr += hdr->seg.size;
} else {
break;
}
fnextaddr += flashcpy(fnextaddr, &hdr->seg, sizeof(IMGSEGHEAD));
segnum++;
}
return fnextaddr;
}
/*-------------------------------------------------------------------------------------
* 0 - default image (config data + 0), 1 - image N1, 2 - image N2, ...
--------------------------------------------------------------------------------------*/
LOCAL int BOOT_RAM_TEXT_SECTION loadUserImges(int imgnum) {
IMG2HEAD hdr;
int imagenum = 1;
uint32 faddr = 0xb000; // start image2 in flash
DBG_8195A("Selected Image %d.\n", imgnum);
while (1) {
faddr = (faddr + FLASH_SECTOR_SIZE - 1) & (~(FLASH_SECTOR_SIZE - 1));
uint32 img_id = load_img2_head(faddr, &hdr);
if ((img_id >> 8) > 4 || (uint8) img_id != 0) {
faddr = load_segs(faddr + 0x10, &hdr.seg, imagenum == imgnum);
if (imagenum == imgnum) {
// DBG_8195A("Image%d: %s\n", imgnum, hdr.name);
break;
}
imagenum++;
} else if (imagenum) {
DBG_8195A("No Image%d! Trying Image0...\n", imgnum);
// пробуем загрузить image по умолчанию, по записи в секторе установок
flashcpy(FLASH_SYSTEM_DATA_ADDR, &faddr, sizeof(faddr));
if (faddr < 0x8000000)
faddr += SPI_FLASH_BASE;
if (get_seg_id(faddr, 0x100) == SEG_ID_FLASH) {
imagenum = 0;
imgnum = 0;
} else {
DBG_8195A("No Image0!\n");
imagenum = -1;
break;
};
} else {
imagenum = -1;
break;
}
};
return imagenum;
}
//----- IsForceLoadDefaultImg2
LOCAL uint8 BOOT_RAM_TEXT_SECTION IsForceLoadDefaultImg2(void) {
uint8 gpio_pin[4];
HAL_GPIO_PIN GPIO_Pin;
HAL_GPIO_PIN_STATE flg;
int result = 0;
flashcpy(FLASH_SYSTEM_DATA_ADDR + 0x08, &gpio_pin, sizeof(gpio_pin)); // config data + 8
// _pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
for (int i = 1; i; i--) {
uint8 x = gpio_pin[i];
result <<= 1;
if (x != 0xff) {
GPIO_Pin.pin_name = HAL_GPIO_GetIPPinName_8195a(x & 0x7F);
if (x & 0x80) {
GPIO_Pin.pin_mode = DIN_PULL_LOW;
flg = GPIO_PIN_HIGH;
} else {
GPIO_Pin.pin_mode = DIN_PULL_HIGH;
flg = GPIO_PIN_LOW;
}
HAL_GPIO_Init_8195a(&GPIO_Pin);
if (HAL_GPIO_ReadPin_8195a(&GPIO_Pin) == flg) {
result |= 1;
}
HAL_GPIO_DeInit_8195a(&GPIO_Pin);
}
}
// _pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL;
return result;
}
/* RTL Console ROM */
LOCAL void BOOT_RAM_TEXT_SECTION RtlConsolRam(void) {
// DiagPrintf("\r\nRTL Console ROM\r\n");
// RtlConsolInit(ROM_STAGE, (u32) 6, (void*) &UartLogRomCmdTable);
pUartLogCtl->RevdNo = UART_LOG_HISTORY_LEN;
pUartLogCtl->BootRdy = 1;
pUartLogCtl->pTmpLogBuf->UARTLogBuf[0] = '?';
pUartLogCtl->pTmpLogBuf->BufCount = 1;
pUartLogCtl->ExecuteCmd = 1;
RtlConsolTaskRom(pUartLogCtl);
}
/* Enter Image 1.5 */
LOCAL void BOOT_RAM_TEXT_SECTION EnterImage15(int flg) {
if (flg)
_memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
SYSPlatformInit();
if (!flg)
DBG_8195A("\r===== Enter FLASH-Boot ====\n");
else
DBG_8195A("\r===== Enter SRAM-Boot %d ====\n", flg);
#if CONFIG_DEBUG_LOG > 1
DBG_8195A("CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(),
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
#endif
uint8 ChipId = _Get_ChipId();
if (ChipId < CHIP_ID_8195AM) {
//----- SDRAM Off
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
} else {
//----- SDRAM On
LDO25M_CTRL(ON);
HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
(HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x0e));
SDR_PIN_FCTRL(ON);
};
InitSpic(SpicDualBitMode); // SpicOneBitMode)
if (!SpicCmpDataForCalibrationRtl8195A()) {
DBG_8195A("Error Init Spic DIO!\n");
RtlConsolRam();
}
if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена?
// extern DRAM_DEVICE_INFO SdrDramInfo_rom; // 50 MHz
if (!SdrControllerInit_rom(&SdrDramInfo)) { // 100 MHz
DBG_8195A("SDR Controller Init fail!\n");
RtlConsolRam();
}
#if 0 // Test SDRAM
else {
uint32 *ptr = SDR_SDRAM_BASE;
uint32 tt = 0x55AA55AA;
for (int i = 0; i < 512 * 1024; i++) {
ptr[i] = tt++;
};
tt = 0x55AA55AA;
for (int i = 0; i < 512 * 1024; i++) {
if (ptr[i] != tt) {
DBG_8195A("SDR err %p %p != %p!\n", &ptr[i], ptr[i], tt);
RtlConsolRam();
}
tt++;
};
DBG_8195A("SDR tst end\n");
};
#endif // test
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
};
if (!flg)
loadUserImges(IsForceLoadDefaultImg2() + 1);
if (_strcmp((const char *) &__image2_validate_code__, IMG2_SIGN_TXT)) {
DBG_MISC_ERR("Invalid Image Signature!\n");
RtlConsolRam();
}
DBG_8195A("Img Sign: %s, Go @ 0x%08x\r\n", &__image2_validate_code__,
__image2_entry_func__);
__image2_entry_func__();
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot1ToSram(void) {
EnterImage15(1);
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot2ToSram(void) {
EnterImage15(2);
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot3ToSram(void) {
EnterImage15(3);
}
/* RtlBootToSram */
LOCAL void BOOT_RAM_TEXT_SECTION RtlBoot4ToSram(void) {
EnterImage15(4);
}
LOCAL void BOOT_RAM_TEXT_SECTION RtlBootToFlash(void) {
EnterImage15(0);
}

207
USDK/component/soc/realtek/8195a/fwlib/ram_lib/startup.c Normal file
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@ -0,0 +1,207 @@
/*
* StartUp SDK
* Created on: 02/03/2017
* Author: pvvx
*/
#include "rtl8195a.h"
#include "diag.h"
#include "hal_spi_flash.h"
#include "hal_api.h"
#include "hal_platform.h"
#include "diag.h"
#include "hal_diag.h"
#include "rtl8195a_uart.h"
#include "rtl8195a/rtl8195a_peri_on.h"
#include "hal_peri_on.h"
#include "rtl_bios_data.h"
#include "wifi_conf.h"
#include "rtl_consol.h"
//-------------------------------------------------------------------------
// Function declarations
void InfraStart(void);
//extern void HalWdgIntrHandle(void);
extern void xPortPendSVHandler(void);
extern void xPortSysTickHandler(void);
extern void vPortSVCHandler(void);
extern void rtl_libc_init(void);
//extern void ShowRamBuildInfo(void); // app_start.c: VOID ShowRamBuildInfo(VOID)
//void HalNMIHandler_Patch(void);
void SDIO_Device_Off(void);
//void VectorTableOverrideRtl8195A(u32 StackP);
void SYSPlatformInit(void);
//-------------------------------------------------------------------------
// Data declarations
extern u8 __bss_start__, __bss_end__;
extern const unsigned char cus_sig[32]; // images name
//extern HAL_TIMER_OP HalTimerOp;
IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 =
{ InfraStart + 1 };
/*
//----- HalNMIHandler_Patch
void HalNMIHandler_Patch(void) {
DBG_8195A_HAL("%s:NMI Error!\n", __func__);
if ( HAL_READ32(VENDOR_REG_BASE, 0) < 0)
HalWdgIntrHandle(); // ROM: HalWdgIntrHandle = 0x3485;
}
*/
/*
* 16 bytes FIFO ... 16*11/38400 = 0.004583 sec
* (0.005/5)*166666666 = 166666.666
*/
LOCAL void INFRA_START_SECTION loguart_wait_tx_fifo_empty(void) {
int x = 16384;
while((!(HAL_READ8(LOG_UART_REG_BASE, 0x14) & BIT6)) && x--);
}
//----- SDIO_Device_Off
void INFRA_START_SECTION SDIO_Device_Off(void) {
HAL_PERI_ON_WRITE32(REG_PESOC_HCI_CLK_CTRL0,
HAL_PERI_ON_READ32(REG_PESOC_HCI_CLK_CTRL0)
& (~BIT_SOC_ACTCK_SDIO_DEV_EN));
HAL_PERI_ON_WRITE32(REG_SOC_HCI_COM_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_HCI_COM_FUNC_EN)
& (~(BIT_SOC_HCI_SDIOD_ON_EN | BIT_SOC_HCI_SDIOD_OFF_EN)));
HAL_PERI_ON_WRITE32(REG_HCI_PINMUX_CTRL,
HAL_PERI_ON_READ32(REG_HCI_PINMUX_CTRL)
& (~(BIT_HCI_SDIOD_PIN_EN)));
}
//----- SYSPlatformInit
void INFRA_START_SECTION SYSPlatformInit(void) {
HAL_SYS_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0,
(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0)
& (~(BIT_MASK_SYS_EEROM_LDO_PAR_07_04 << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04)))
| BIT_SYS_EEROM_LDO_PAR_07_04(6)); // & 0xF0FFFFFF | 0x6000000
HAL_SYS_CTRL_WRITE32(REG_SYS_XTAL_CTRL1,
(HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1)
& (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1)))
| BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8;
}
// weak __low_level_init function!
__weak void __low_level_init(void) {
}
// weak main function!
__weak int main(void) {
DiagPrintf("\r\nRTL Console ROM: Start - press key 'Up', Help '?'\r\n");
while (pUartLogCtl->ExecuteEsc != 1);
pUartLogCtl->RevdNo = 0;
pUartLogCtl->BootRdy = 1;
DiagPrintf("\r<RTL>");
while (1) {
while (pUartLogCtl->ExecuteCmd != 1);
UartLogCmdExecute(pUartLogCtl);
DiagPrintf("\r<RTL>");
pUartLogCtl->ExecuteCmd = 0;
}
return 0;
}
//----- InfraStart
void INFRA_START_SECTION InfraStart(void) {
// NewVectorTable[2] = HalNMIHandler_Patch;
DBG_8195A("===== Enter Image: %s ====\n", cus_sig);
// ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID)
memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__);
rtl_libc_init(); // ROM Lib C init (rtl_printf!)
// SYSPlatformInit();
// SDIO_Device_Off();
//- Должно быть в boot
extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
memset(&gBoot_Gpio_Adapter, 0, sizeof(gBoot_Gpio_Adapter));
_pHAL_Gpio_Adapter = &gBoot_Gpio_Adapter;
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
loguart_wait_tx_fifo_empty(); // иначе глючит LogUART, если переключение CLK приходится на вывод символов !
#if 1 // if set CLK CPU
if(HalGetCpuClk() != PLATFORM_CLOCK) {
//----- CLK CPU
#if CPU_CLOCK_SEL_DIV5_3
// 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz
HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
*((int *)(SYSTEM_CTRL_BASE+REG_SYS_SYSPLL_CTRL1)) |= (1<<17);// REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3
#else
// 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
*((int *) (SYSTEM_CTRL_BASE + REG_SYS_SYSPLL_CTRL1)) &= ~(1 << 17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3
HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
#endif // CPU_CLOCK_SEL_DIV5_3
};
#endif
PSHalInitPlatformLogUart(); // HalInitPlatformLogUartV02(); // Show "<RTL8195A>"... :(
HalReInitPlatformTimer(); // HalInitPlatformTimerV02(); HalTimerOpInit_Patch((VOID*) (&HalTimerOp));
SystemCoreClockUpdate();
En32KCalibration();
//---- Spic
// _memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk));
*(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x01310202; // patch
*(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x11311301; // patch
// *(uint32 *)(&SpicInitParaAllClk[2][0].BaudRate) = 0x21311301; // patch
SPI_FLASH_PIN_FCTRL(ON);
/*
// uint8 SpicBaudRate = CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7);
uint8 SpicBaudRate = 3; // HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7;
DBG_8195A("SpicBaudRate = %d\n", SpicBaudRate);
SpicInitRtl8195AV02(SpicBaudRate, SpicDualBitMode);
if(!SpicCmpDataForCalibrationRtl8195A()) {
DBG_8195A("ReInit Spic to SIO...\n");
SpicInitRtl8195AV02(SpicBaudRate, SpicOneBitMode);
if(!SpicCmpDataForCalibrationRtl8195A()) {
DBG_8195A("Error Init Spic!\n");
};
};
*/
// SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode
//---- SDRAM
uint8 ChipId = HalGetChipId();
if (ChipId >= CHIP_ID_8195AM) {
#ifdef CONFIG_SDR_EN
if((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT(21)) == 0) { // уже загружена?
SdrCtrlInit();
if(SdrControllerInit()) {
DBG_8195A("SDR Controller Init fail!\n");
};
};
#endif
// clear SDRAM bss
extern uint8 __sdram_bss_start__[];
extern uint8 __sdram_bss_end__[];
if((uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__ > 0)
memset(__sdram_bss_start__, 0, (uint32)__sdram_bss_end__-(uint32)__sdram_bss_start__);
}
else
{
//----- SDRAM Off
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Off
};
//----- Close Flash
SPI_FLASH_PIN_FCTRL(OFF);
InitSoCPM();
VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler,
&xPortSysTickHandler);
#if CONFIG_DEBUG_LOG > 4
DBG_8195A("\rSet CPU CLK: %d Hz, SOC FUNC EN: %p\r\n", HalGetCpuClk(), HAL_PERI_ON_READ32(REG_SOC_FUNC_EN));
#endif
// force SP align to 8 byte not 4 byte (initial SP is 4 byte align)
__asm(
"mov r0, sp\n"
"bic r0, r0, #7\n"
"mov sp, r0\n"
);
__low_level_init();
main();
}

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/*
* BootLoader
* startup.o sdk-ameba-rtl8710af-v3.5a_without_NDA_GCC_V1.0.0
* pvvx 2016
*/
#include "rtl8195a.h"
#include "diag.h"
#include "hal_spi_flash.h"
#include "hal_api.h"
#include "hal_platform.h"
#include "diag.h"
#include "hal_diag.h"
#include "rtl8195a_uart.h"
#include "rtl8195a/rtl8195a_peri_on.h"
#include "hal_peri_on.h"
#include "wifi_conf.h"
#include "rtl_consol.h"
#ifndef USE_SRC_ONLY_BOOT
#define USE_SRC_ONLY_BOOT 0
#endif
#if USE_SRC_ONLY_BOOT
#define rtl_memset _memset
#define rtl_strcmp _strcmp
#define rtl_memcpy _memcpy
#endif
#define VREG32(addr) (*((volatile u32*)(addr)))
typedef void (*START_FUNC)(void);
#ifndef DEFAULT_BAUDRATE
#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
#endif
#define StartupSpicBitMode SpicDualBitMode // SpicOneBitMode
#define StartupSpicBaudRate 0
//-------------------------------------------------------------------------
// Function declarations
void PreProcessForVendor(void); // image1
void RtlBootToSram(void); // image1
u32 StartupHalLogUartInit(u32 uart_irq); // image1
void StartupHalInitPlatformLogUart(void); // image1
int IsForceLoadDefaultImg2(void); // image1
void StartupHalSpicInit(int InitBaudRate); // image1
int _GetChipId(void); // image1
void RtlConsolRam(void); // image1
extern VOID UartLogIrqHandle(VOID * Data); // in ROM
extern int RtlConsolRom(int); // in ROM
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
extern VOID SpicUserReadRtl8195A(IN u32 Length, IN u32 addr, IN u8 * data,
IN u8 BitMode);
#if !USE_SRC_ONLY_BOOT
void InfraStart(void);
extern void HalWdgIntrHandle(void);
extern int wifi_off(void); // in wifi_conf.c
extern void xPortPendSVHandler(void);
extern void xPortSysTickHandler(void);
extern void vPortSVCHandler(void);
extern void ShowRamBuildInfo(void); // app_start.c: VOID ShowRamBuildInfo(VOID)
void HalNMIHandler_Patch(void);
void SDIO_Device_Off(void);
void VectorTableOverrideRtl8195A(u32 StackP);
void SYSPlatformInit(void);
void HalHardFaultHandler_Patch_c(u32 HardDefaultArg);
void __HalReInitPlatformLogUart(void);
void _ReloadImg(void);
void _ReloadImg_user_define(void);
void _CPUResetHandler(void);
void _CPUReset(void);
void HalHardFaultHandler_user_define(u32 HardDefaultArg);
#endif
//-------------------------------------------------------------------------
// Data declarations
extern START_FUNC __image2_entry_func__;
extern u8 __image2_validate_code__;
extern u8 __image1_bss_start__, __image1_bss_end__;
extern u8 __rom_bss_start__, __rom_bss_end__;
//extern u32 STACK_TOP;
#define STACK_TOP 0x1FFFFFFC
#if !USE_SRC_ONLY_BOOT
extern u32 * NewVectorTable; // LD: NewVectorTable = 0x10000000;
extern u8 __bss_start__, __bss_end__;
#endif
//extern volatile UART_LOG_CTL * pUartLogCtl;
extern int UartLogCmdExecute(volatile u8 *);
/*
typedef struct __RAM_IMG2_VALID_PATTEN__ {
char rtkwin[7];
u8 x[13];
} _RAM_IMG2_VALID_PATTEN, *_PRAM_IMG2_VALID_PATTEN;
*/
const uint8_t IMAGE1_VALID_PATTEN_SECTION RAM_IMG1_VALID_PATTEN[8] =
{ 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
PRAM_FUNCTION_START_TABLE __attribute__((section(".data.pRamStartFun"))) pRamStartFun =
(PRAM_FUNCTION_START_TABLE) 0x10000BC8;
#include <reent.h>
struct _reent __attribute__((section(".libc.reent"))) impure_reent = _REENT_INIT(impure_reent);
//struct _reent * __attribute__((section(".libc.reent"))) _rtl_impure_ptr = { &impure_data };
//struct _reent * __attribute__((at(0x1098))) __attribute__((section(".libc.reent"))) _rtl_impure_ptr = { &impure_data };
struct _reent * __attribute__((at(0x10001c60))) __attribute__((section(".libc.reent"))) _rtl_impure_ptr = { &impure_reent };
/* ROM */
MON_RAM_BSS_SECTION
volatile UART_LOG_CTL *pUartLogCtl;
MON_RAM_BSS_SECTION
UART_LOG_BUF UartLogBuf;
MON_RAM_BSS_SECTION
volatile UART_LOG_CTL UartLogCtl;
MON_RAM_BSS_SECTION
u8 *ArgvArray[MAX_ARGV]; // *ArgvArray[10] !
MON_RAM_BSS_SECTION
u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN]; // UartLogHistoryBuf[5][127] !
RAM_START_FUNCTION START_RAM_FUN_A_SECTION gRamStartFun =
{ PreProcessForVendor + 1 };
RAM_START_FUNCTION START_RAM_FUN_B_SECTION gRamPatchWAKE =
{ RtlBootToSram + 1 };
RAM_START_FUNCTION START_RAM_FUN_C_SECTION gRamPatchFun0 =
{ RtlBootToSram + 1 };
RAM_START_FUNCTION START_RAM_FUN_D_SECTION gRamPatchFun1 =
{ RtlBootToSram + 1 };
RAM_START_FUNCTION START_RAM_FUN_E_SECTION gRamPatchFun2 =
{ RtlBootToSram + 1 };
#if !USE_SRC_ONLY_BOOT
RAM_START_FUNCTION IMAGE2_START_RAM_FUN_SECTION gImage2EntryFun0 =
{ InfraStart + 1 };
#else
RAM_START_FUNCTION IMAGE2_START_RAM_FUN_SECTION gImage2EntryFun0 =
{ 0x100 };
#endif // !USE_SRC_ONLY_BOOT
_RAM_IMG2_VALID_PATTEN IMAGE2_VALID_PATTEN_SECTION RAM_IMG2_VALID_PATTEN =
{ { IMG2_SIGN_TXT }, { 0xff, 0, 1, 1, 0, 0x95, 0x81, 1, 1, 0, 0, 0, 0 } }; // "RTKWin"
HAL_GPIO_ADAPTER PINMUX_RAM_DATA_SECTION gBoot_Gpio_Adapter;
#pragma arm section code = ".hal.ram.text"
#pragma arm section rodata = ".hal.ram.rodata", rwdata = ".hal.ram.data", zidata = ".hal.ram.bss"
#if !USE_SRC_ONLY_BOOT
//----- HalNMIHandler_Patch
void HalNMIHandler_Patch(void) {
DBG_8195A_HAL("RTL8195A[HAL]: %s:NMI Error!\n", __func__);
if ( HAL_READ32(VENDOR_REG_BASE, 0) < 0)
HalWdgIntrHandle(); // ROM: HalWdgIntrHandle = 0x3485;
}
#endif // !USE_SRC_ONLY_BOOT
void __attribute__((section(".hal.ram.text"))) SetDebugFlgs() {
#if CONFIG_DEBUG_LOG > 2
ConfigDebugErr = -1;
ConfigDebugWarn = -1;
ConfigDebugInfo = -1;
#elif CONFIG_DEBUG_LOG > 1
ConfigDebugErr = -1;
ConfigDebugWarn = -1;
ConfigDebugInfo = 0;
#elif CONFIG_DEBUG_LOG > 0
ConfigDebugErr = -1;
ConfigDebugWarn = 0;
ConfigDebugInfo = 0;
#else
ConfigDebugErr = 0;
ConfigDebugWarn = 0;
ConfigDebugInfo = 0;
#endif
}
void __attribute__((section(".hal.ram.text"))) InitSpic(void)
{
VREG32(0x40006000) = 0x01000300;
VREG32(0x40006004) = 0x1;
VREG32(0x400060E0) = 0x0B;
VREG32(0x400060E4) = 0x3B;
VREG32(0x400060E8) = 0x3B;
VREG32(0x400060EC) = 0x6B;
VREG32(0x400060F0) = 0xEB;
VREG32(0x400060F4) = 0x02;
VREG32(0x400060F8) = 0xA2;
VREG32(0x400060FC) = 0xA2;
VREG32(0x40006100) = 0x32;
VREG32(0x40006104) = 0x38;
VREG32(0x40006108) = 0x06;
VREG32(0x4000610C) = 0x05;
VREG32(0x40006110) = 0x51;
VREG32(0x40006114) = 0x01;
VREG32(0x40006118) = 0x03;
VREG32(0x4000611C) = 0x20030013;
VREG32(0x40006120) = 0x202;
VREG32(0x40006124) = 0x0E;
}
//----- StartupHalLogUartInit
u32 __attribute__((section(".hal.ram.text"))) StartupHalLogUartInit(u32 uart_irq) {
HAL_UART_WRITE32(UART_DLH_OFF, 0);
u32 SysClock = (HalGetCpuClk() >> 2);
u32 SampleRate = (16 * DEFAULT_BAUDRATE);
u32 Divisor = SysClock / SampleRate;
u32 Remaind = ((SysClock * 10) / SampleRate) - (Divisor * 10);
if (Remaind > 4) Divisor++;
// set DLAB bit to 1
// HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, 0);
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, RUART_LINE_CTL_REG_DLAB_ENABLE);
HAL_UART_WRITE32(UART_DLL_OFF, Divisor & 0xff);
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 3);
HAL_UART_WRITE32(UART_FIFO_CTL_REG_OFF, FIFO_CTL_DEFAULT_WITH_FIFO);
HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, uart_irq);
if (uart_irq) {
// Enable Peripheral_IRQ Setting for Log_Uart
HAL_WRITE32(VENDOR_REG_BASE, PERIPHERAL_IRQ_EN, 0x1000000);
// Cortex-M3 SCB->AIRCR
HAL_WRITE32(0xE000ED00, 0x0C,
(HAL_READ32(0xE000ED00, 0x0C) & 0x0F8FF) | 0x5FA0300);
HAL_WRITE8(0xE000E100, 0x313, 0xE0); // HAL_WRITE8(0xE000E100, 0x313, 0xE0);
HAL_WRITE32(0xE000E100, 0, 0x80000); // NVIC enable external interrupt[?] ?
}
return 0;
}
//----- StartupHalInitPlatformLogUart
void __attribute__((section(".hal.ram.text"))) StartupHalInitPlatformLogUart(
void) {
HAL_UART_READ32(UART_REV_BUF_OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~(BIT_SOC_LOG_UART_EN))); // 40000210 &= 0xFFFFEFFF; // ~(1<<12)
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_LOG_UART_EN); // 40000210 |= 0x1000u;
ACTCK_LOG_UART_CCTRL(ON); // 40000230 |= 0x1000u;
StartupHalLogUartInit(IER_ERBFI | IER_ELSI);
}
void __attribute__((section(".hal.ram.text"))) RtlConsolRam(void)
{
// __asm__ __volatile__ ("cpsid f\n");
// HalCpuClkConfig(0); // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
// ConfigDebugErr = -1;
// VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC);
// HalInitPlatformLogUartV02();
// HalReInitPlatformLogUartV02();
// HalInitPlatformTimerV02();
__asm__ __volatile__ ("cpsie f\n");
DiagPrintf("\r\nRTL Console ROM: Start - press 'ESC' key, Help '?'\r\n");
while(!pUartLogCtl->ExecuteEsc);
pUartLogCtl->EscSTS = 0;
pUartLogCtl->BootRdy = 1;
DiagPrintf("\r<RTL>");
while(1) {
while(!pUartLogCtl->ExecuteCmd);
UartLogCmdExecute(pUartLogCtl);
DiagPrintf("\r<RTL>");
pUartLogCtl->ExecuteCmd = 0;
}
}
//----- RtlBootToSram
void __attribute__((section(".hal.ram.text"))) RtlBootToSram(void) {
TIMER_ADAPTER tim_adapter;
/* JTAG On */
ACTCK_VENDOR_CCTRL(ON);
SLPCK_VENDOR_CCTRL(ON);
HalPinCtrlRtl8195A(JTAG, 0, 1);
memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
/* Flash & LogUart On */
HAL_PERI_ON_WRITE32(REG_GPIO_SHTDN_CTRL, 0x7FF);
SPI_FLASH_PIN_FCTRL(ON);
HAL_PERI_ON_WRITE32(REG_CPU_PERIPHERAL_CTRL,
HAL_PERI_ON_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_SPI_FLSH_PIN_EN); // 400002C0 |= 0x1u;
HAL_PERI_ON_WRITE32(REG_CPU_PERIPHERAL_CTRL,
HAL_PERI_ON_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_LOG_UART_PIN_EN); // 400002C0 |= 0x100000u;
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_FLASH_EN); // 40000210 |= 0x10u;
ACTCK_FLASH_CCTRL(ON);
SLPCK_FLASH_CCTRL(ON);
HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
SpicNVMCalLoadAll();
HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL1,
HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) & 0x8F); // VREG32(0x40000014) &= 0x8F;
SetDebugFlgs();
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~(BIT_SOC_LOG_UART_EN))); // 40000210 &= 0xFFFFEFFF; // ~(1<<12)
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_LOG_UART_EN); // 40000210 |= 0x1000u;
ACTCK_LOG_UART_CCTRL(ON);
// SLPCK_LOG_UART_CCTRL(ON);
tim_adapter.IrqHandle.IrqFun = &UartLogIrqHandle;
tim_adapter.IrqHandle.IrqNum = UART_LOG_IRQ;
tim_adapter.IrqHandle.Data = 0;
tim_adapter.IrqHandle.Priority = 5;
StartupHalLogUartInit(0);
VectorIrqRegisterRtl8195A(&tim_adapter.IrqHandle);
StartupHalLogUartInit(IER_ERBFI | IER_ELSI);
HAL_PERI_ON_WRITE32(REG_PON_ISO_CTRL, 3); // VREG32(0x40000204) = 3;
HAL_PERI_ON_WRITE32(REG_OSC32K_CTRL,
HAL_PERI_ON_READ32(REG_OSC32K_CTRL) | BIT_32K_POW_CKGEN_EN); // VREG32(0x40000270) |= 1u;
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_GTIMER_EN); // VREG32(0x40000210) |= 0x10000u;
ACTCK_TIMER_CCTRL(ON);
SLPCK_TIMER_CCTRL(ON);
tim_adapter.TimerIrqPriority = 0;
tim_adapter.TimerLoadValueUs = 0;
tim_adapter.TimerMode = FREE_RUN_MODE;
tim_adapter.IrqDis = 1;
tim_adapter.TimerId = 1;
HalTimerInitRtl8195a((PTIMER_ADAPTER) &tim_adapter);
SpicInitRtl8195A(1, StartupSpicBitMode); // StartupSpicBaudRate InitBaudRate 1, SpicBitMode 1 StartupSpicBitMode
SpicFlashInitRtl8195A(StartupSpicBitMode); // SpicBitMode 1 StartupSpicBitMode
DBG_8195A("==*== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\n",
&__image2_validate_code__, __image2_entry_func__);
if (strcmp((const char * )&__image2_validate_code__, IMG2_SIGN_TXT)) {
DBG_MISC_ERR("Invalid Image2 Signature!\n");
RtlConsolRam();
}
// InitSpic();
__image2_entry_func__();
}
//----- SYSCpuClkConfig
void __attribute__((section(".hal.ram.text"))) SYSCpuClkConfig(int ChipID, int SysCpuClk) {
int flg = 0;
DBG_SPIF_INFO("SYSCpuClkConfig(0x%x)\n", SysCpuClk);
if(HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) {
SpicWaitWipRtl8195A(); //_SpicWaitWipDoneRefinedRtl8195A(); ???
flg = 1;
}
// if (ChipID == CHIP_ID_8710AF && (!SysCpuClk)) SysCpuClk = 1;
HalCpuClkConfig(SysCpuClk);
HalDelayUs(1000);
StartupHalInitPlatformLogUart();
if (flg) {
SpicOneBitCalibrationRtl8195A(SysCpuClk); // extern u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
/*
// Disable SPI_FLASH User Mode
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
HAL_SPI_WRITE32(REG_SPIC_VALID_CMD,
(HAL_SPI_READ32(REG_SPIC_VALID_CMD)|(FLASH_VLD_DUAL_CMDS))); */
SpicCalibrationRtl8195A(StartupSpicBitMode, 0);
}
}
//----- IsForceLoadDefaultImg2
int __attribute__((section(".hal.ram.text"))) IsForceLoadDefaultImg2(void) {
u8 gpio_pin[4];
HAL_GPIO_PIN GPIO_Pin;
HAL_GPIO_PIN_STATE flg;
int result = 0;
*((u32 *) &gpio_pin) = HAL_READ32(SPI_FLASH_BASE, FLASH_SYSTEM_DATA_ADDR + 0x08); // config data + 8
_pHAL_Gpio_Adapter = (int) &gBoot_Gpio_Adapter;
for(int i = 0; i < 2; i++) {
u8 x = gpio_pin[i];
if (x != 0xff) {
GPIO_Pin.pin_name = HAL_GPIO_GetIPPinName_8195a(x & 0x7F);
if (x & 0x80) {
GPIO_Pin.pin_mode = DIN_PULL_LOW;
flg = GPIO_PIN_HIGH;
} else {
GPIO_Pin.pin_mode = DIN_PULL_HIGH;
flg = GPIO_PIN_LOW;
}
HAL_GPIO_Init_8195a(&GPIO_Pin);
result |= HAL_GPIO_ReadPin_8195a(&GPIO_Pin) == flg;
HAL_GPIO_DeInit_8195a(&GPIO_Pin);
}
}
_pHAL_Gpio_Adapter->IrqHandle.IrqFun = NULL;
return result;
}
//----- GetChipId
int __attribute__((section(".hal.ram.text"))) _GetChipId() {
u8 chip_id = CHIP_ID_8195AM;
if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
&chip_id, L25EOUTVOLTAGE) != 1)
DBG_MISC_INFO("Get Chip ID Failed\r");
return chip_id;
}
//----- StartupHalSpicInit
void __attribute__((section(".hal.ram.text"))) StartupHalSpicInit(
int InitBaudRate) {
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT4); // HAL_SYS_CTRL_READ32
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL,
HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_FLASH_EN | BIT_SOC_SLPCK_FLASH_EN);
HalPinCtrlRtl8195A(SPI_FLASH,
((HAL_SYS_CTRL_READ32(REG_SYS_SYSTEM_CFG1) & 0xF0000000)
== 0x30000000), 1);
SpicInitRtl8195A(InitBaudRate, StartupSpicBitMode);
}
void __attribute__((section(".hal.ram.text"))) flashcpy(u32 raddr, u32 faddr, s32 size) {
while(size > 0) {
HAL_WRITE32(0, raddr, HAL_READ32(SPI_FLASH_BASE, faddr));
raddr+=4;
faddr+=4;
size-=4;
}
}
//----- PreProcessForVendor
void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
START_FUNC entry_func;
u32 run_image;
u32 Image2Addr = *(u32 *)(0x1006FFFC);
u32 v16 = 0, v17;
#if 0
u8 efuse0xD3_data;
HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xD3,
&efuse0xD3_data, L25EOUTVOLTAGE);
if (efuse0xD3_data & 1)
#endif
HalPinCtrlRtl8195A(JTAG, 0, 1);
SetDebugFlgs();
int chip_id = _GetChipId();
int flash_enable = HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN; // v6 = ...
int spic_init = 0;
/// InitSpic();
if (flash_enable) {
entry_func = &__image2_entry_func__;
spic_init = 1;
} else {
entry_func = (START_FUNC) Image2Addr;
if (chip_id != CHIP_ID_8711AN) { // 0xFB
StartupHalSpicInit(StartupSpicBaudRate); // BaudRate 1
spic_init = 1;
}
}
DBG_8195A("BOOT from Flash: %s\n", (flash_enable) ? "YES" : "NO");
memset(&__image1_bss_start__, 0,
&__image1_bss_end__ - &__image1_bss_start__);
HalDelayUs(1000);
int sdr_enable = 0;
#ifdef CONFIG_SDR_EN
if (chip_id > CHIP_ID_8711AF || chip_id == CHIP_ID_8710AM) {
SdrCtrlInit();
sdr_enable = 1;
}
else {
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
}
#else
// SdrPowerOff();
SDR_PIN_FCTRL(OFF);
LDO25M_CTRL(OFF);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21));
#endif
if (spic_init) SpicNVMCalLoadAll();
SYSCpuClkConfig(chip_id, 0);
StartupHalInitPlatformLogUart(); // double !?
__asm__ __volatile__ ("cpsie f\n");
DBG_8195A("===== Enter Image 1 ====\n");
if (spic_init) {
SpicReadIDRtl8195A();
SpicFlashInitRtl8195A(StartupSpicBitMode); // SpicBitMode 1
}
#ifdef CONFIG_SDR_EN
if (sdr_enable) SdrControllerInit();
#endif
if (flash_enable) {
u32 img1size = (*(u16 *) (SPI_FLASH_BASE + 0x18)) << 10; // size in 1024 bytes
if (img1size == 0 || img1size >= 0x3FFFC00)
img1size = *(u32 *) (SPI_FLASH_BASE + 0x10) + 32;
u32 * prdflash = (u32 *) (img1size + SPI_FLASH_BASE + 8);
u32 sign1 = *prdflash++;
u32 sign2 = *prdflash;
{
v16 = -1;
v17 = -1;
if (sign2 == IMG_SIGN2_RUN) {
if (sign1 == IMG_SIGN1_RUN) {
v16 = img1size;
v17 = -1;
} else if (sign1 == IMG_SIGN1_SWP) {
v17 = img1size;
v16 = -1;
}
}
u32 OTA_addr = *(u32 *) (SPI_FLASH_BASE + FLASH_SYSTEM_DATA_ADDR); // config sector data
if (OTA_addr != -1) {
u32 image2size = *(u32 *) (img1size + SPI_FLASH_BASE);
if (OTA_addr >= (img1size + image2size)
&& !(OTA_addr & 0xFFF)) {
prdflash = (u32 *) (OTA_addr + SPI_FLASH_BASE + 8);
sign1 = *prdflash++;
sign2 = *prdflash;
if (sign2 == IMG_SIGN2_RUN) {
if (sign1 == IMG_SIGN1_RUN) v16 = OTA_addr;
else if (sign1 == IMG_SIGN1_SWP) v17 = OTA_addr;
}
LABEL_41: if (IsForceLoadDefaultImg2()) {
if (v17 != -1) run_image = v17;
else {
run_image = v16;
if (run_image == -1) {
DiagPrintf("Fatal: no fw\n");
RtlConsolRam();
}
}
} else {
if (v16 != -1) run_image = v16;
else {
run_image = v17;
if (run_image == -1) {
DiagPrintf("Fatal: no fw\n");
RtlConsolRam();
}
}
}
u8 * pstr;
if (run_image == v17)
pstr = "load OLD fw %d\n";
else {
if (run_image != v16) {
LABEL_55: prdflash = run_image + SPI_FLASH_BASE;
u32 img_size = *prdflash++;
u32 Image2Addr = *prdflash;
DBG_8195A("Flash Image2: Addr 0x%x, Len %d, Load to SRAM 0x%x\n", run_image, img_size, Image2Addr); // debug!
flashcpy(Image2Addr, run_image+16, img_size);
// SpicUserReadFourByteRtl8195A(img_size, run_image + 16, Image2Addr, StartupSpicBitMode); // SpicDualBitMode
prdflash = run_image + img_size + SPI_FLASH_BASE + 16;
u32 sdram_image_size = *prdflash++; // +0x10
u32 sdram_load_addr = *prdflash; // +0x14
DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",
sdram_image_size, sdram_load_addr);
if ((sdram_image_size - 1) <= 0xFFFFFFFD
&& *((u32 *)(sdram_load_addr)) == SDR_SDRAM_BASE) { // sdram_load_addr
if (!sdr_enable) {
DBG_MISC_ERR("FW/HW conflict. No DRAM on board.\n");
RtlConsolRam();
}
DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",
sdram_image_size, sdram_load_addr);
// SpicUserReadRtl8195A(sdram_image_size, run_image + img_size + 32, SDR_SDRAM_BASE, StartupSpicBitMode);
} else DBG_8195A("No Image3\n");
entry_func = *(u32 *)Image2Addr;
DBG_8195A("Img2 Sign: %s, InfaStart @ 0x%08x \n",
(const char * )(Image2Addr + 4),
entry_func); // *(u32 *)Image2Addr);
if (strcmp((const char * )(Image2Addr + 4),
IMG2_SIGN_TXT)) {
DBG_MISC_ERR("Invalid Image2 Signature\n");
RtlConsolRam();
}
#if 0
DBG_8195A("CLK CPU: %d Hz\n", HalGetCpuClk());
RtlConsolRam();
#else
#endif
(void) (entry_func)();
return;
}
pstr = "load NEW fw %d\n";
} // if (run_image == v17) else
DiagPrintf(pstr, ((run_image - OTA_addr) <= 0));
goto LABEL_55;
}
DBG_MISC_ERR("OTA addr 0x%x INVALID\n", OTA_addr);
}
OTA_addr = -1;
goto LABEL_41;
}
} // if (flash_enable)
if (strcmp((const char * )(Image2Addr + 4), IMG2_SIGN_TXT)) {
DBG_MISC_ERR("Invalid Image2 Signature\n", 2 * ConfigDebugErr);
RtlConsolRam();
}
(void) (entry_func)();
}
#if !USE_SRC_ONLY_BOOT
//----- HalHardFaultHandler_Patch_c
void HalHardFaultHandler_Patch_c(u32 HardDefaultArg) {
u32 v1;
int v2;
int v3;
v1 = HardDefaultArg;
if ((VREG32(0xE000ED28) & 0x82)
&& (unsigned int) (VREG32(0xE000ED38) - 0x40080000) < 0x40000) {
DBG_8195A("\n.");
v2 = *(u32 *) (v1 + 24);
if ((*(u16 *) v2 & 0xF800) <= 0xE000) v3 = v2 + 2;
else v3 = v2 + 4;
*(u32 *) (v1 + 24) = v3;
} else {
HalHardFaultHandler_user_define(HardDefaultArg);
HalHardFaultHandler(v1); // ROM: HalHardFaultHandler = 0x911;
}
}
//----- VectorTableOverrideRtl8195A
void __attribute__((section(".infra.ram.start"))) VectorTableOverrideRtl8195A(u32 StackP) {
NewVectorTable[2] = HalNMIHandler_Patch;
}
//----- SYSPlatformInit
void __attribute__((section(".infra.ram.start"))) SYSPlatformInit(void) {
HAL_SYS_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0,
(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0) & (~(BIT_MASK_SYS_EEROM_LDO_PAR_07_04 << BIT_SHIFT_SYS_EEROM_LDO_PAR_07_04))) | BIT_SYS_EEROM_LDO_PAR_07_04(6)); // & 0xF0FFFFFF | 0x6000000
HAL_SYS_CTRL_WRITE32(REG_SYS_XTAL_CTRL1,
(HAL_SYS_CTRL_READ32(REG_SYS_XTAL_CTRL1) & (~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1))) | BIT_SYS_XTAL_DRV_RF1(1)); // & 0xFFFFFFE7 | 8;
}
//----- InfraStart
void __attribute__((section(".infra.ram.start"))) InfraStart(void) {
NewVectorTable[2] = HalNMIHandler_Patch;
HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL0,
HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0) | BIT4);
if (HalCommonInit() != HAL_OK) DBG_8195A("Hal Common Init Failed.\n");
DBG_8195A("===== Enter Image 2 ====\n");
ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID)
memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__);
int flsh = (HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0)
>> BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) & 1;
if (flsh) {
SpicNVMCalLoadAll();
SpicReadIDRtl8195A();
}
SystemCoreClockUpdate();
SYSPlatformInit();
En32KCalibration();
InitSoCPM();
SDIO_Device_Off();
VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler, &xPortSysTickHandler);
if (flsh) SpicDisableRtl8195A();
_AppStart();
}
//----- SDIO_Device_Off
void SDIO_Device_Off(void) {
HAL_PERI_ON_WRITE32(REG_PESOC_HCI_CLK_CTRL0,
HAL_PERI_ON_READ32(REG_PESOC_HCI_CLK_CTRL0) & (~BIT_SOC_ACTCK_SDIO_DEV_EN));
HAL_PERI_ON_WRITE32(REG_SOC_HCI_COM_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_HCI_COM_FUNC_EN) & (~(BIT_SOC_HCI_SDIOD_ON_EN | BIT_SOC_HCI_SDIOD_OFF_EN)));
HAL_PERI_ON_WRITE32(REG_HCI_PINMUX_CTRL,
HAL_PERI_ON_READ32(REG_HCI_PINMUX_CTRL) & (~(BIT_HCI_SDIOD_PIN_EN)));
}
//----- __HalReInitPlatformLogUart
void __HalReInitPlatformLogUart(void) {
LOG_UART_ADAPTER UartAdapter;
UartAdapter.BaudRate = DEFAULT_BAUDRATE;
HalLogUartInit(UartAdapter);
}
void _ReloadImg_user_define(void) {
}
//----- ReloadImg
void _ReloadImg(void) {
u32 img1size;
u32 img1addr;
unsigned int i;
u32 img2addr;
u32 img_addr1;
u32 img_addr2;
u32 ota_addr;
const char * pstr;
img1size = *(u32 *) (SPI_FLASH_BASE + 0x10);
img1addr = *(u32 *) (SPI_FLASH_BASE + 0x14);
DBG_8195A("Image1 length: 0x%x, Image Addr: 0x%x\n", img1size,
img1addr);
for (i = 32; i < img1size + 32; i += 4)
*(u32 *) (img1addr - 32 + i) = *(u32 *) (i + SPI_FLASH_BASE);
img2addr = *(u16 *) (SPI_FLASH_BASE + 0x16) << 10;
if (!(img2addr)) img2addr = img1size + 32;
u32 * prdflash = (u32 *) (img1size + SPI_FLASH_BASE + 8);
u32 sign1 = *prdflash++; // v4 = *(u32 *)(img2addr + SPI_FLASH_BASE + 8);
u32 sign2 = *prdflash; // v5 = *(u32 *)(img2addr + SPI_FLASH_BASE + 12);
if (sign1 == IMG_SIGN1_RUN) {
if (sign2 == IMG_SIGN2_RUN) {
img_addr1 = img2addr;
LABEL_11: img_addr2 = -1;
goto LABEL_16;
}
LABEL_14: img_addr1 = -1;
goto LABEL_11;
}
if (sign1 != IMG_SIGN1_SWP || sign2 != IMG_SIGN2_RUN) goto LABEL_14;
img_addr2 = img2addr;
img_addr1 = -1;
LABEL_16: ota_addr = *(u32 *) (SPI_FLASH_BASE + 0x9000);
if (ota_addr == -1) {
LABEL_21: ota_addr = -1;
goto LABEL_22;
}
if (ota_addr < (img2addr + *(u32 *) (img2addr + SPI_FLASH_BASE))
|| (ota_addr & 0xFFF)) {
DBG_MISC_ERR("OTA addr 0x%x INVALID\n");
goto LABEL_21;
}
prdflash = (u32 *) (ota_addr + SPI_FLASH_BASE + 8);
sign1 = *prdflash++; // v9 = *(u32 *)(ota_addr + SPI_FLASH_BASE + 8);
sign2 = *prdflash; // v11 = *(u32 *)(ota_addr + SPI_FLASH_BASE + 12);
if (sign1 == IMG_SIGN1_RUN) {
sign1 = IMG_SIGN2_RUN;
if (sign2 == IMG_SIGN2_RUN) {
img_addr1 = ota_addr;
goto LABEL_33;
}
goto LABEL_22;
}
if (sign1 != IMG_SIGN1_SWP || (sign1 = IMG_SIGN2_RUN, sign2 != IMG_SIGN2_RUN)) {
LABEL_22: if (img_addr1 == -1) {
if (img_addr2 == -1) {
DBG_MISC_ERR("Fatal:no fw\n", ota_addr,
2 * ConfigDebugErr);
RtlConsolRam();
}
img_addr1 = img_addr2;
LABEL_28: pstr = "load OLD fw %d\n";
if (ConfigDebugErr & _DBG_MISC_) {
LABEL_36: DiagPrintf(pstr,
((unsigned int) (img_addr1 - ota_addr) <= 0));
}
goto IMG2_LOAD_START;
}
goto LABEL_33;
}
if (img_addr1 == -1) {
img_addr1 = *(u32 *) (SPI_FLASH_BASE + 0x9000); // ota_addr
goto LABEL_28;
}
img_addr2 = *(u32 *) (SPI_FLASH_BASE + 0x9000);
LABEL_33: if (img_addr1 == img_addr2)
goto LABEL_28;
if (ConfigDebugErr & _DBG_MISC_) // DBG_8195A
{
pstr = "load NEW fw %d\n";
goto LABEL_36;
}
u32 v13;
IMG2_LOAD_START:
v13 = *(u32 *) (img_addr1 + SPI_FLASH_BASE + 4);
u32 v15 = *(u32 *) (img_addr1 + SPI_FLASH_BASE) + img_addr1;
for (i = img_addr1 + 16;; i += 4) {
if (i >= (unsigned int) (v15 + 16)) break;
*(u32 *) (v13 - 16 - img_addr1 + i) = *(u32 *) (i + SPI_FLASH_BASE);
}
u32 v16 = *(u32 *) (v15 + SPI_FLASH_BASE);
if ((unsigned int) (v16 - 1) <= 0xFFFFFFFD
&& *(u32 *) (v15 + SPI_FLASH_BASE + 0x14) == 0x30000000) {
DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",
*(u32 *)(v15 + SPI_FLASH_BASE + 0x10));
for (i = v15 + 32; i < (v16 + v15 + 32); i += 4)
*(u32 *) (0x2FFFFFE0 - v15 + i) = *(u32 *) (i + SPI_FLASH_BASE);
} else
DBG_8195A("No Image3\n");
_ReloadImg_user_define();
}
//----- CPUResetHandler
void _CPUResetHandler(void) {
memset(&__rom_bss_start__, 0, &__rom_bss_end__ - &__rom_bss_start__);
ConfigDebugErr = -1;
HalCpuClkConfig(0);
VectorTableInitRtl8195A(STACK_TOP); // 0x1FFFFFFC
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT23);
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN);
HAL_PERI_ON_WRITE32(REG_SOC_PERI_BD_FUNC0_EN,
HAL_PERI_ON_READ32(REG_SOC_PERI_BD_FUNC0_EN) | BIT8 | BIT9);
HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
HalTimerOpInit_Patch(&HalTimerOp);
HalDelayUs(1000);
__HalReInitPlatformLogUart();
_ReloadImg();
InfraStart();
}
//----- CPUReset
void _CPUReset(void) // __noreturn
{
wifi_off();
pRamStartFun->RamPatchFun1 = _CPUResetHandler;
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN,
HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT27);
HAL_WRITE32(0xE000ED00, 0x0C, 0x5FA0003); //
while (1);
}
void HalHardFaultHandler_user_define(u32 HardDefaultArg) {
}
#endif // !USE_SRC_ONLY_BOOT

35
USDK/component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/Rtl8195a_otg_zero.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef RTL8195A_OTG_ZERO_H
#define RTL8195A_OTG_ZERO_H
#include "usb_ch9.h"
#include "usb_gadget.h"
struct zero_dev {
//ModifiedByJD spinlock_t lock;
struct usb_gadget *gadget;
struct usb_request *req; /* for control responses */
/* when configured, we have one of two configs:
* - source data (in to host) and sink it (out from host)
* - or loop it back (out from host back in to host)
*/
u8 config;
struct usb_ep *in_ep, *out_ep, *status_ep;//ModifiedByJD
const struct usb_endpoint_descriptor
*in, *out, *status; //ModifiedByJD
/* autoresume timer */
//ModifiedByJD struct timer_list resume;
};
#endif

211
USDK/component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/cdc.h Normal file
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//#include "../otg/osk/sys-support.h" //ModifiedByJD
/*
* USB Communications Device Class (CDC) definitions
*
* CDC says how to talk to lots of different types of network adapters,
* notably ethernet adapters and various modems. It's used mostly with
* firmware based USB peripherals.
*/
#define USB_CDC_SUBCLASS_ACM 0x02
#define USB_CDC_SUBCLASS_ETHERNET 0x06
#define USB_CDC_SUBCLASS_WHCM 0x08
#define USB_CDC_SUBCLASS_DMM 0x09
#define USB_CDC_SUBCLASS_MDLM 0x0a
#define USB_CDC_SUBCLASS_OBEX 0x0b
#define USB_CDC_PROTO_NONE 0
#define USB_CDC_ACM_PROTO_AT_V25TER 1
#define USB_CDC_ACM_PROTO_AT_PCCA101 2
#define USB_CDC_ACM_PROTO_AT_PCCA101_WAKE 3
#define USB_CDC_ACM_PROTO_AT_GSM 4
#define USB_CDC_ACM_PROTO_AT_3G 5
#define USB_CDC_ACM_PROTO_AT_CDMA 6
#define USB_CDC_ACM_PROTO_VENDOR 0xff
/*-------------------------------------------------------------------------*/
//#define UPACKED __attribute__ ((packed))
#define UPACKED
/*
* Class-Specific descriptors ... there are a couple dozen of them
*/
#define USB_CDC_HEADER_TYPE 0x00 /* header_desc */
#define USB_CDC_CALL_MANAGEMENT_TYPE 0x01 /* call_mgmt_descriptor */
#define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */
#define USB_CDC_UNION_TYPE 0x06 /* union_desc */
#define USB_CDC_COUNTRY_TYPE 0x07
#define USB_CDC_NETWORK_TERMINAL_TYPE 0x0a /* network_terminal_desc */
#define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */
#define USB_CDC_WHCM_TYPE 0x11
#define USB_CDC_MDLM_TYPE 0x12 /* mdlm_desc */
#define USB_CDC_MDLM_DETAIL_TYPE 0x13 /* mdlm_detail_desc */
#define USB_CDC_DMM_TYPE 0x14
#define USB_CDC_OBEX_TYPE 0x15
//ModifiedByJD (>>>) modify the data type to useable ones.
/* "Header Functional Descriptor" from CDC spec 5.2.3.1 */
struct usb_cdc_header_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u16 bcdCDC;
} UPACKED;
/* "Call Management Descriptor" from CDC spec 5.2.3.2 */
struct usb_cdc_call_mgmt_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bmCapabilities;
#define USB_CDC_CALL_MGMT_CAP_CALL_MGMT 0x01
#define USB_CDC_CALL_MGMT_CAP_DATA_INTF 0x02
u8 bDataInterface;
} UPACKED;
/* "Abstract Control Management Descriptor" from CDC spec 5.2.3.3 */
struct usb_cdc_acm_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bmCapabilities;
} UPACKED;
/* "Union Functional Descriptor" from CDC spec 5.2.3.8 */
struct usb_cdc_union_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bMasterInterface0;
u8 bSlaveInterface0;
/* ... and there could be other slave interfaces */
} UPACKED;
/* "Network Channel Terminal Functional Descriptor" from CDC spec 5.2.3.11 */
struct usb_cdc_network_terminal_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bEntityId;
u8 iName;
u8 bChannelIndex;
u8 bPhysicalInterface;
} UPACKED;
/* "Ethernet Networking Functional Descriptor" from CDC spec 5.2.3.16 */
struct usb_cdc_ether_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 iMACAddress;
u32 bmEthernetStatistics;
u16 wMaxSegmentSize;
u16 wNumberMCFilters;
u8 bNumberPowerFilters;
} UPACKED;
/* "MDLM Functional Descriptor" from CDC WMC spec 6.7.2.3 */
struct usb_cdc_mdlm_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u16 bcdVersion;
u8 bGUID[16];
}UPACKED;
/* "MDLM Detail Functional Descriptor" from CDC WMC spec 6.7.2.4 */
struct usb_cdc_mdlm_detail_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
/* type is associated with mdlm_desc.bGUID */
u8 bGuidDescriptorType;
u8 bDetailData[0];
} UPACKED;
/*-------------------------------------------------------------------------*/
/*
* Class-Specific Control Requests (6.2)
*
* section 3.6.2.1 table 4 has the ACM profile, for modems.
* section 3.8.2 table 10 has the ethernet profile.
*
* Microsoft's RNDIS stack for Ethernet is a vendor-specific CDC ACM variant,
* heavily dependent on the encapsulated (proprietary) command mechanism.
*/
#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00
#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01
#define USB_CDC_REQ_SET_LINE_CODING 0x20
#define USB_CDC_REQ_GET_LINE_CODING 0x21
#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22
#define USB_CDC_REQ_SEND_BREAK 0x23
#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER 0x41
#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER 0x42
#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43
#define USB_CDC_GET_ETHERNET_STATISTIC 0x44
/* Line Coding Structure from CDC spec 6.2.13 */
struct usb_cdc_line_coding {
u32 dwDTERate;
u8 bCharFormat;
#define USB_CDC_1_STOP_BITS 0
#define USB_CDC_1_5_STOP_BITS 1
#define USB_CDC_2_STOP_BITS 2
u8 bParityType;
#define USB_CDC_NO_PARITY 0
#define USB_CDC_ODD_PARITY 1
#define USB_CDC_EVEN_PARITY 2
#define USB_CDC_MARK_PARITY 3
#define USB_CDC_SPACE_PARITY 4
u8 bDataBits;
} UPACKED;
/* table 62; bits in multicast filter */
#define USB_CDC_PACKET_TYPE_PROMISCUOUS (1 << 0)
#define USB_CDC_PACKET_TYPE_ALL_MULTICAST (1 << 1) /* no filter */
#define USB_CDC_PACKET_TYPE_DIRECTED (1 << 2)
#define USB_CDC_PACKET_TYPE_BROADCAST (1 << 3)
#define USB_CDC_PACKET_TYPE_MULTICAST (1 << 4) /* filtered */
/*-------------------------------------------------------------------------*/
/*
* Class-Specific Notifications (6.3) sent by interrupt transfers
*
* section 3.8.2 table 11 of the CDC spec lists Ethernet notifications
* section 3.6.2.1 table 5 specifies ACM notifications, accepted by RNDIS
* RNDIS also defines its own bit-incompatible notifications
*/
#define USB_CDC_NOTIFY_NETWORK_CONNECTION 0x00
#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE 0x01
#define USB_CDC_NOTIFY_SERIAL_STATE 0x20
#define USB_CDC_NOTIFY_SPEED_CHANGE 0x2a
struct usb_cdc_notification {
u8 bmRequestType;
u8 bNotificationType;
u16 wValue;
u16 wIndex;
u16 wLength;
}UPACKED;
//ModifiedByJD (<<<)

594
USDK/component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_list.h Normal file
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@ -0,0 +1,594 @@
/* $OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $ */
/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */
/*
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)queue.h 8.5 (Berkeley) 8/20/94
*/
#ifndef _DWC_LIST_H_
#define _DWC_LIST_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @file
*
* This file defines linked list operations. It is derived from BSD with
* only the MACRO names being prefixed with DWC_. This is because a few of
* these names conflict with those on Linux. For documentation on use, see the
* inline comments in the source code. The original license for this source
* code applies and is preserved in the dwc_list.h source file.
*/
/*
* This file defines five types of data structures: singly-linked lists,
* lists, simple queues, tail queues, and circular queues.
*
*
* A singly-linked list is headed by a single forward pointer. The elements
* are singly linked for minimum space and pointer manipulation overhead at
* the expense of O(n) removal for arbitrary elements. New elements can be
* added to the list after an existing element or at the head of the list.
* Elements being removed from the head of the list should use the explicit
* macro for this purpose for optimum efficiency. A singly-linked list may
* only be traversed in the forward direction. Singly-linked lists are ideal
* for applications with large datasets and few or no removals or for
* implementing a LIFO queue.
*
* A list is headed by a single forward pointer (or an array of forward
* pointers for a hash table header). The elements are doubly linked
* so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before
* or after an existing element or at the head of the list. A list
* may only be traversed in the forward direction.
*
* A simple queue is headed by a pair of pointers, one the head of the
* list and the other to the tail of the list. The elements are singly
* linked to save space, so elements can only be removed from the
* head of the list. New elements can be added to the list before or after
* an existing element, at the head of the list, or at the end of the
* list. A simple queue may only be traversed in the forward direction.
*
* A tail queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or
* after an existing element, at the head of the list, or at the end of
* the list. A tail queue may be traversed in either direction.
*
* A circle queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or after
* an existing element, at the head of the list, or at the end of the list.
* A circle queue may be traversed in either direction, but has a more
* complex end of list detection.
*
* For details on the use of these macros, see the queue(3) manual page.
*/
/*
* Double-linked List.
*/
typedef struct dwc_list_link {
struct dwc_list_link *next;
struct dwc_list_link *prev;
} dwc_list_link_t;
#define DWC_LIST_INIT(link) do { \
(link)->next = (link); \
(link)->prev = (link); \
} while (0)
#define DWC_LIST_FIRST(link) ((link)->next)
#define DWC_LIST_LAST(link) ((link)->prev)
#define DWC_LIST_END(link) (link)
#define DWC_LIST_NEXT(link) ((link)->next)
#define DWC_LIST_PREV(link) ((link)->prev)
#define DWC_LIST_EMPTY(link) \
(DWC_LIST_FIRST(link) == DWC_LIST_END(link))
#define DWC_LIST_ENTRY(link, type, field) \
(type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
#if 0
#define DWC_LIST_INSERT_HEAD(list, link) do { \
(link)->next = (list)->next; \
(link)->prev = (list); \
(list)->next->prev = (link); \
(list)->next = (link); \
} while (0)
#define DWC_LIST_INSERT_TAIL(list, link) do { \
(link)->next = (list); \
(link)->prev = (list)->prev; \
(list)->prev->next = (link); \
(list)->prev = (link); \
} while (0)
#else
#define DWC_LIST_INSERT_HEAD(list, link) do { \
dwc_list_link_t *__next__ = (list)->next; \
__next__->prev = (link); \
(link)->next = __next__; \
(link)->prev = (list); \
(list)->next = (link); \
} while (0)
#define DWC_LIST_INSERT_TAIL(list, link) do { \
dwc_list_link_t *__prev__ = (list)->prev; \
(list)->prev = (link); \
(link)->next = (list); \
(link)->prev = __prev__; \
__prev__->next = (link); \
} while (0)
#endif
#if 0
static inline void __list_add(struct list_head *new,
struct list_head *prev,
struct list_head *next)
{
next->prev = new;
new->next = next;
new->prev = prev;
prev->next = new;
}
static inline void list_add(struct list_head *new, struct list_head *head)
{
__list_add(new, head, head->next);
}
static inline void list_add_tail(struct list_head *new, struct list_head *head)
{
__list_add(new, head->prev, head);
}
static inline void __list_del(struct list_head * prev, struct list_head * next)
{
next->prev = prev;
prev->next = next;
}
static inline void list_del(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
entry->next = LIST_POISON1;
entry->prev = LIST_POISON2;
}
#endif
#define DWC_LIST_REMOVE(link) do { \
(link)->next->prev = (link)->prev; \
(link)->prev->next = (link)->next; \
} while (0)
#define DWC_LIST_REMOVE_INIT(link) do { \
DWC_LIST_REMOVE(link); \
DWC_LIST_INIT(link); \
} while (0)
#define DWC_LIST_MOVE_HEAD(list, link) do { \
DWC_LIST_REMOVE(link); \
DWC_LIST_INSERT_HEAD(list, link); \
} while (0)
#define DWC_LIST_MOVE_TAIL(list, link) do { \
DWC_LIST_REMOVE(link); \
DWC_LIST_INSERT_TAIL(list, link); \
} while (0)
#define DWC_LIST_FOREACH(var, list) \
for((var) = DWC_LIST_FIRST(list); \
(var) != DWC_LIST_END(list); \
(var) = DWC_LIST_NEXT(var))
#define DWC_LIST_FOREACH_SAFE(var, var2, list) \
for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \
(var) != DWC_LIST_END(list); \
(var) = (var2), (var2) = DWC_LIST_NEXT(var2))
#define DWC_LIST_FOREACH_REVERSE(var, list) \
for((var) = DWC_LIST_LAST(list); \
(var) != DWC_LIST_END(list); \
(var) = DWC_LIST_PREV(var))
/*
* Singly-linked List definitions.
*/
#define DWC_SLIST_HEAD(name, type) \
struct name { \
struct type *slh_first; /* first element */ \
}
#define DWC_SLIST_HEAD_INITIALIZER(head) \
{ NULL }
#define DWC_SLIST_ENTRY(type) \
struct { \
struct type *sle_next; /* next element */ \
}
/*
* Singly-linked List access methods.
*/
#define DWC_SLIST_FIRST(head) ((head)->slh_first)
#define DWC_SLIST_END(head) NULL
#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head))
#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next)
#define DWC_SLIST_FOREACH(var, head, field) \
for((var) = SLIST_FIRST(head); \
(var) != SLIST_END(head); \
(var) = SLIST_NEXT(var, field))
#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \
for((varp) = &SLIST_FIRST((head)); \
((var) = *(varp)) != SLIST_END(head); \
(varp) = &SLIST_NEXT((var), field))
/*
* Singly-linked List functions.
*/
#define DWC_SLIST_INIT(head) { \
SLIST_FIRST(head) = SLIST_END(head); \
}
#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \
(elm)->field.sle_next = (slistelm)->field.sle_next; \
(slistelm)->field.sle_next = (elm); \
} while (0)
#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \
(elm)->field.sle_next = (head)->slh_first; \
(head)->slh_first = (elm); \
} while (0)
#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \
(elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \
} while (0)
#define DWC_SLIST_REMOVE_HEAD(head, field) do { \
(head)->slh_first = (head)->slh_first->field.sle_next; \
} while (0)
#define DWC_SLIST_REMOVE(head, elm, type, field) do { \
if ((head)->slh_first == (elm)) { \
SLIST_REMOVE_HEAD((head), field); \
} \
else { \
struct type *curelm = (head)->slh_first; \
while( curelm->field.sle_next != (elm) ) \
curelm = curelm->field.sle_next; \
curelm->field.sle_next = \
curelm->field.sle_next->field.sle_next; \
} \
} while (0)
/*
* Simple queue definitions.
*/
#define DWC_SIMPLEQ_HEAD(name, type) \
struct name { \
struct type *sqh_first; /* first element */ \
struct type **sqh_last; /* addr of last next element */ \
}
#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).sqh_first }
#define DWC_SIMPLEQ_ENTRY(type) \
struct { \
struct type *sqe_next; /* next element */ \
}
/*
* Simple queue access methods.
*/
#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first)
#define DWC_SIMPLEQ_END(head) NULL
#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
#define DWC_SIMPLEQ_FOREACH(var, head, field) \
for((var) = SIMPLEQ_FIRST(head); \
(var) != SIMPLEQ_END(head); \
(var) = SIMPLEQ_NEXT(var, field))
/*
* Simple queue functions.
*/
#define DWC_SIMPLEQ_INIT(head) do { \
(head)->sqh_first = NULL; \
(head)->sqh_last = &(head)->sqh_first; \
} while (0)
#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
(head)->sqh_last = &(elm)->field.sqe_next; \
(head)->sqh_first = (elm); \
} while (0)
#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
(elm)->field.sqe_next = NULL; \
*(head)->sqh_last = (elm); \
(head)->sqh_last = &(elm)->field.sqe_next; \
} while (0)
#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
(head)->sqh_last = &(elm)->field.sqe_next; \
(listelm)->field.sqe_next = (elm); \
} while (0)
#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \
if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
(head)->sqh_last = &(head)->sqh_first; \
} while (0)
/*
* Tail queue definitions.
*/
#define DWC_TAILQ_HEAD(name, type) \
struct name { \
struct type *tqh_first; /* first element */ \
struct type **tqh_last; /* addr of last next element */ \
}
#define DWC_TAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).tqh_first }
#define DWC_TAILQ_ENTRY(type) \
struct { \
struct type *tqe_next; /* next element */ \
struct type **tqe_prev; /* address of previous next element */ \
}
/*
* tail queue access methods
*/
#define DWC_TAILQ_FIRST(head) ((head)->tqh_first)
#define DWC_TAILQ_END(head) NULL
#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
#define DWC_TAILQ_LAST(head, headname) \
(*(((struct headname *)((head)->tqh_last))->tqh_last))
/* XXX */
#define DWC_TAILQ_PREV(elm, headname, field) \
(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
#define DWC_TAILQ_EMPTY(head) \
(TAILQ_FIRST(head) == TAILQ_END(head))
#define DWC_TAILQ_FOREACH(var, head, field) \
for((var) = TAILQ_FIRST(head); \
(var) != TAILQ_END(head); \
(var) = TAILQ_NEXT(var, field))
#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \
for((var) = TAILQ_LAST(head, headname); \
(var) != TAILQ_END(head); \
(var) = TAILQ_PREV(var, headname, field))
/*
* Tail queue functions.
*/
#define DWC_TAILQ_INIT(head) do { \
(head)->tqh_first = NULL; \
(head)->tqh_last = &(head)->tqh_first; \
} while (0)
#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \
if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
(head)->tqh_first->field.tqe_prev = \
&(elm)->field.tqe_next; \
else \
(head)->tqh_last = &(elm)->field.tqe_next; \
(head)->tqh_first = (elm); \
(elm)->field.tqe_prev = &(head)->tqh_first; \
} while (0)
#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \
(elm)->field.tqe_next = NULL; \
(elm)->field.tqe_prev = (head)->tqh_last; \
*(head)->tqh_last = (elm); \
(head)->tqh_last = &(elm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
(elm)->field.tqe_next->field.tqe_prev = \
&(elm)->field.tqe_next; \
else \
(head)->tqh_last = &(elm)->field.tqe_next; \
(listelm)->field.tqe_next = (elm); \
(elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
(elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
(elm)->field.tqe_next = (listelm); \
*(listelm)->field.tqe_prev = (elm); \
(listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_REMOVE(head, elm, field) do { \
if (((elm)->field.tqe_next) != NULL) \
(elm)->field.tqe_next->field.tqe_prev = \
(elm)->field.tqe_prev; \
else \
(head)->tqh_last = (elm)->field.tqe_prev; \
*(elm)->field.tqe_prev = (elm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \
if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \
(elm2)->field.tqe_next->field.tqe_prev = \
&(elm2)->field.tqe_next; \
else \
(head)->tqh_last = &(elm2)->field.tqe_next; \
(elm2)->field.tqe_prev = (elm)->field.tqe_prev; \
*(elm2)->field.tqe_prev = (elm2); \
} while (0)
/*
* Circular queue definitions.
*/
#define DWC_CIRCLEQ_HEAD(name, type) \
struct name { \
struct type *cqh_first; /* first element */ \
struct type *cqh_last; /* last element */ \
}
#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \
{ DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
#define DWC_CIRCLEQ_ENTRY(type) \
struct { \
struct type *cqe_next; /* next element */ \
struct type *cqe_prev; /* previous element */ \
}
/*
* Circular queue access methods
*/
#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first)
#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last)
#define DWC_CIRCLEQ_END(head) ((void *)(head))
#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
#define DWC_CIRCLEQ_EMPTY(head) \
(DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
#define DWC_CIRCLEQ_FOREACH(var, head, field) \
for((var) = DWC_CIRCLEQ_FIRST(head); \
(var) != DWC_CIRCLEQ_END(head); \
(var) = DWC_CIRCLEQ_NEXT(var, field))
#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \
for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
(var) != DWC_CIRCLEQ_END(head); \
(var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \
for((var) = DWC_CIRCLEQ_LAST(head); \
(var) != DWC_CIRCLEQ_END(head); \
(var) = DWC_CIRCLEQ_PREV(var, field))
/*
* Circular queue functions.
*/
#define DWC_CIRCLEQ_INIT(head) do { \
(head)->cqh_first = DWC_CIRCLEQ_END(head); \
(head)->cqh_last = DWC_CIRCLEQ_END(head); \
} while (0)
#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \
(elm)->field.cqe_next = NULL; \
(elm)->field.cqe_prev = NULL; \
} while (0)
#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
(elm)->field.cqe_next = (listelm)->field.cqe_next; \
(elm)->field.cqe_prev = (listelm); \
if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
(head)->cqh_last = (elm); \
else \
(listelm)->field.cqe_next->field.cqe_prev = (elm); \
(listelm)->field.cqe_next = (elm); \
} while (0)
#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
(elm)->field.cqe_next = (listelm); \
(elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
(head)->cqh_first = (elm); \
else \
(listelm)->field.cqe_prev->field.cqe_next = (elm); \
(listelm)->field.cqe_prev = (elm); \
} while (0)
#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
(elm)->field.cqe_next = (head)->cqh_first; \
(elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \
if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \
(head)->cqh_last = (elm); \
else \
(head)->cqh_first->field.cqe_prev = (elm); \
(head)->cqh_first = (elm); \
} while (0)
#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
(elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \
(elm)->field.cqe_prev = (head)->cqh_last; \
if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \
(head)->cqh_first = (elm); \
else \
(head)->cqh_last->field.cqe_next = (elm); \
(head)->cqh_last = (elm); \
} while (0)
#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \
if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
(head)->cqh_last = (elm)->field.cqe_prev; \
else \
(elm)->field.cqe_next->field.cqe_prev = \
(elm)->field.cqe_prev; \
if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
(head)->cqh_first = (elm)->field.cqe_next; \
else \
(elm)->field.cqe_prev->field.cqe_next = \
(elm)->field.cqe_next; \
} while (0)
#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \
DWC_CIRCLEQ_REMOVE(head, elm, field); \
DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
} while (0)
#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \
if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \
DWC_CIRCLEQ_END(head)) \
(head).cqh_last = (elm2); \
else \
(elm2)->field.cqe_next->field.cqe_prev = (elm2); \
if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \
DWC_CIRCLEQ_END(head)) \
(head).cqh_first = (elm2); \
else \
(elm2)->field.cqe_prev->field.cqe_next = (elm2); \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* _DWC_LIST_H_ */

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USDK/component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_adp.h Normal file
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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
* $Revision: #8 $
* $Date: 2013/04/09 $
* $Change: 2201932 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_ADP_H__
#define __DWC_OTG_ADP_H__
/**
* @file
*
* This file contains the Attach Detect Protocol interfaces and defines
* (functions) and structures for Linux.
*
*/
#define DWC_OTG_ADP_UNATTACHED 0
#define DWC_OTG_ADP_ATTACHED 1
#define DWC_OTG_ADP_UNKOWN 2
#define HOST_RTIM_THRESHOLD 5
#define DEVICE_RTIM_THRESHOLD 3
typedef struct dwc_otg_adp {
uint32_t adp_started;
uint32_t initial_probe;
int32_t probe_timer_values[2];
uint32_t probe_enabled;
uint32_t sense_enabled;
dwc_timer_t *sense_timer;
uint32_t sense_timer_started;
dwc_timer_t *vbuson_timer;
uint32_t vbuson_timer_started;
uint32_t attached;
uint32_t probe_counter;
uint32_t gpwrdn;
} dwc_otg_adp_t;
/**
* Attach Detect Protocol functions
*/
extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
#endif //__DWC_OTG_ADP_H__

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
* $Revision: #13 $
* $Date: 2010/06/21 $
* $Change: 1532021 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_OTG_ATTR_H__)
#define __DWC_OTG_ATTR_H__
#if 0
/** @file
* This file contains the interface to the Linux device attributes.
*/
extern struct device_attribute dev_attr_regoffset;
extern struct device_attribute dev_attr_regvalue;
extern struct device_attribute dev_attr_mode;
extern struct device_attribute dev_attr_hnpcapable;
extern struct device_attribute dev_attr_srpcapable;
extern struct device_attribute dev_attr_hnp;
extern struct device_attribute dev_attr_srp;
extern struct device_attribute dev_attr_buspower;
extern struct device_attribute dev_attr_bussuspend;
extern struct device_attribute dev_attr_mode_ch_tim_en;
extern struct device_attribute dev_attr_fr_interval;
extern struct device_attribute dev_attr_busconnected;
extern struct device_attribute dev_attr_gotgctl;
extern struct device_attribute dev_attr_gusbcfg;
extern struct device_attribute dev_attr_grxfsiz;
extern struct device_attribute dev_attr_gnptxfsiz;
extern struct device_attribute dev_attr_gpvndctl;
extern struct device_attribute dev_attr_ggpio;
extern struct device_attribute dev_attr_guid;
extern struct device_attribute dev_attr_gsnpsid;
extern struct device_attribute dev_attr_devspeed;
extern struct device_attribute dev_attr_enumspeed;
extern struct device_attribute dev_attr_hptxfsiz;
extern struct device_attribute dev_attr_hprt0;
#ifdef CONFIG_USB_DWC_OTG_LPM
extern struct device_attribute dev_attr_lpm_response;
extern struct device_attribute devi_attr_sleep_status;
#endif
void dwc_otg_attr_create(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif PCI_INTERFACE
struct pci_dev *dev
#endif
);
void dwc_otg_attr_remove(
#ifdef LM_INTERFACE
struct lm_device *dev
#elif PCI_INTERFACE
struct pci_dev *dev
#endif
);
#endif
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "basic_types.h"
#include <osdep_api.h>
//#include "va_list.h"
#include <stdarg.h>
#include "diag.h"
#include "dwc_otg_dbg.h"
#include "dwc_os.h"
typedef struct _RAM_OTG_FUNCTION_TABLE_ {
VOID* (*RamMemSet) (void *dest, int byte, SIZE_T size);
VOID* (*RamMemCpy) (void *dest, void const *src, SIZE_T size);
int (*RamMemCmp) (void const*m1, void const *m2, SIZE_T size);
int (*RamStrnCmp) (const char *s1, const char *s2, SIZE_T size);
int (*RamStrCmp) (const char *s1, const char *s2);
SIZE_T (*RamStrLen) (char const *str);
char* (*RamStrCpy) (char *to, char const *from);
char* (*RamStrDup) (char const *str);
int (*RamAtoi) (const char *str, int32_t *value);
int (*RamAtoui) (const char *str, uint32_t *value);
int (*RamVsnPrintf) (char *str, int size, const char *format, ...);
u32 (*RamSPrintf) (u8 *buf, const char *fmt, ...);
int (*RamSnPrintf) (char *dst, int count, const char * src, ...);
u8* (*RamZmalloc) (u32 sz);
u8* (*RamZmallocAtomic) (u32 sz);
VOID (*RamMfree) (u8 *pbuf, u32 sz);
dwc_spinlock_t* (*RamSpinlockAlloc) (void);
VOID (*RamSpinlockFree) (dwc_spinlock_t *lock);
VOID (*RamSpinlock) (dwc_spinlock_t *lock);
VOID (*RamSpinUnlock) (dwc_spinlock_t *lock);
VOID (*RamSpinIrqSave) (dwc_spinlock_t *lock, dwc_irqflags_t *flags);
VOID (*RamSpinIrqRestore) (dwc_spinlock_t *lock, dwc_irqflags_t flags);
dwc_mutex_t*(*RamMutexAlloc) (void);
VOID (*RamMutexFree) (dwc_mutex_t *mutex);
VOID (*RamMutexLock) (dwc_mutex_t *mutex);
int (*RamMutexTryLock) (dwc_mutex_t *mutex);
VOID (*RamMutexUnLock) (dwc_mutex_t *mutex);
uint32_t(*RamUDelay) (uint32_t usecs);
void (*RamMSleep) (uint32_t msecs);
VOID (*timer_callback) (unsigned long data);
dwc_timer_t *(*RamTimerAlloc) (char *name, dwc_timer_callback_t cb, void *data);
VOID (*RamTimerFree) (dwc_timer_t *timer);
VOID (*RamTimerSche) (dwc_timer_t *timer, uint32_t time_ms);
VOID (*RamTimerCancel) (dwc_timer_t *timer);
VOID (*RamEnterCritical) (void);
VOID (*RamExitCritical) (void);
}RAM_OTG_FUNCTION_TABLE, *PRAM_OTG_FUNCTION_TABLE;
// Global Variable
extern RAM_OTG_FUNCTION_TABLE gRamOTGFunTbl;
// Funtion Prototype
// ROM
_LONG_CALL_ void dwc_otg_wrapper_reset(IN VOID);
_LONG_CALL_ void dwc_otg_wrapper_init_boot(IN VOID);
_LONG_CALL_ void dwc_otg_power_init(IN VOID);
_LONG_CALL_ VOID RtlInitListhead_Otg(IN _LIST *list);
_LONG_CALL_ u32 RtlIsListEmpty_Otg(IN _LIST *phead);
_LONG_CALL_ VOID RtlListInsertHead_Otg(IN _LIST *plist,IN _LIST *phead);
_LONG_CALL_ VOID RtlListInsertTail_Otg(IN _LIST *plist,IN _LIST *phead);
_LONG_CALL_ _LIST *RtlListGetNext_Otg(IN _LIST *plist);
_LONG_CALL_ VOID RtlListDelete_Otg(IN _LIST *plist);
extern _LONG_CALL_ char *DWC_STRDUP_ROM(char const *str);
extern _LONG_CALL_ int DWC_ATOI_ROM(const char *str, int32_t *value);
extern _LONG_CALL_ int DWC_ATOUI_ROM(const char *str, uint32_t *value);
// RAM
extern void dwc_otg_wrapper_init(IN VOID);

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
* $Revision: #15 $
* $Date: 2012/12/10 $
* $Change: 2123206 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if !defined(__DWC_CORE_IF_H__)
#define __DWC_CORE_IF_H__
#include "dwc_os.h"
/** @file
* This file defines DWC_OTG Core API
*/
struct dwc_otg_core_if;
typedef struct dwc_otg_core_if dwc_otg_core_if_t;
/** Maximum number of Periodic FIFOs */
#define MAX_PERIO_FIFOS 15
/** Maximum number of Periodic FIFOs */
#define MAX_TX_FIFOS 15
/** Maximum number of Endpoints/HostChannels */
#define MAX_EPS_CHANNELS 8
extern _LONG_CALL_ dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr, int mode);
extern _LONG_CALL_ void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
/** This function should be called on every hardware interrupt. */
extern _LONG_CALL_ int32_t dwc_otg_handle_common_intr(void *otg_dev);
/** @name OTG Core Parameters */
/** @{ */
/**
* Specifies the OTG capabilities. The driver will automatically
* detect the value for this parameter if none is specified.
* 0 - HNP and SRP capable (default)
* 1 - SRP Only capable
* 2 - No HNP/SRP capable
*/
extern _LONG_CALL_ int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
extern _LONG_CALL_ int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
#define dwc_param_opt_default 1
/**
* Specifies whether to use slave or DMA mode for accessing the data
* FIFOs. The driver will automatically detect the value for this
* parameter if none is specified.
* 0 - Slave
* 1 - DMA (default, if available)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_dma_enable_default 1
/**
* When DMA mode is enabled specifies whether to use
* address DMA or DMA Descritor mode for accessing the data
* FIFOs in device mode. The driver will automatically detect
* the value for this parameter if none is specified.
* 0 - address DMA
* 1 - DMA Descriptor(default, if available)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_dma_desc_enable_default 1
/** The DMA Burst size (applicable only for External DMA
* Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
#define dwc_param_dma_burst_size_default 32
/**
* Specifies the maximum speed of operation in host and device mode.
* The actual speed depends on the speed of the attached device and
* the value of phy_type. The actual speed depends on the speed of the
* attached device.
* 0 - High Speed (default)
* 1 - Full Speed
*/
extern _LONG_CALL_ int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
#define dwc_param_speed_default 0
#define DWC_SPEED_PARAM_HIGH 0
#define DWC_SPEED_PARAM_FULL 1
/** Specifies whether low power mode is supported when attached
* to a Full Speed or Low Speed device in host mode.
* 0 - Don't support low power mode (default)
* 1 - Support low power mode
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
* core_if);
#define dwc_param_host_support_fs_ls_low_power_default 0
/** Specifies the PHY clock rate in low power mode when connected to a
* Low Speed device in host mode. This parameter is applicable only if
* HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
* then defaults to 6 MHZ otherwise 48 MHZ.
*
* 0 - 48 MHz
* 1 - 6 MHz
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
core_if);
#define dwc_param_host_ls_low_power_phy_clk_default 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
/**
* 0 - Use cC FIFO size parameters
* 1 - Allow dynamic FIFO sizing (default)
*/
extern _LONG_CALL_ int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
core_if);
#define dwc_param_enable_dynamic_fifo_default 1
/** Total number of 4-byte words in the data FIFO memory. This
* memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic
* Tx FIFOs.
* 32 to 32768 (default 8192)
* Note: The total FIFO memory depth in the FPGA configuration is 8192.
*/
extern _LONG_CALL_ int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
#define dwc_param_data_fifo_size_default 8192
/** Number of 4-byte words in the Rx FIFO in device mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1064)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
#define dwc_param_dev_rx_fifo_size_default 1064
/** Number of 4-byte words in the non-periodic Tx FIFO in device mode
* when dynamic FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
core_if);
#define dwc_param_dev_nperio_tx_fifo_size_default 1024
/** Number of 4-byte words in each of the periodic Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
extern _LONG_CALL_ int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
int32_t val, int fifo_num);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
core_if, int fifo_num);
#define dwc_param_dev_perio_tx_fifo_size_default 256
/** Number of 4-byte words in the Rx FIFO in host mode when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
#define dwc_param_host_rx_fifo_size_default 1024
/** Number of 4-byte words in the non-periodic Tx FIFO in host mode
* when Dynamic FIFO sizing is enabled in the core.
* 16 to 32768 (default 1024)
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
core_if);
#define dwc_param_host_nperio_tx_fifo_size_default 1024
/** Number of 4-byte words in the host periodic Tx FIFO when dynamic
* FIFO sizing is enabled.
* 16 to 32768 (default 1024)
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
core_if);
#define dwc_param_host_perio_tx_fifo_size_default 1024
/** The maximum transfer size supported in bytes.
* 2047 to 65,535 (default 65,535)
*/
extern _LONG_CALL_ int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
#define dwc_param_max_transfer_size_default 65535
/** The maximum number of packets in a transfer.
* 15 to 511 (default 511)
*/
extern _LONG_CALL_ int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
#define dwc_param_max_packet_count_default 511
/** The number of host channel registers to use.
* 1 to 16 (default 12)
* Note: The FPGA configuration supports a maximum of 12 host channels.
*/
extern _LONG_CALL_ int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
#define dwc_param_host_channels_default 12
/** The number of endpoints in addition to EP0 available for device
* mode operations.
* 1 to 15 (default 6 IN and OUT)
* Note: The FPGA configuration supports a maximum of 6 IN and OUT
* endpoints in addition to EP0.
*/
extern _LONG_CALL_ int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
#define dwc_param_dev_endpoints_default 6
/**
* Specifies the type of PHY interface to use. By default, the driver
* will automatically detect the phy_type.
*
* 0 - Full Speed PHY
* 1 - UTMI+ (default)
* 2 - ULPI
*/
extern _LONG_CALL_ int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
#define DWC_PHY_TYPE_PARAM_FS 0
#define DWC_PHY_TYPE_PARAM_UTMI 1
#define DWC_PHY_TYPE_PARAM_ULPI 2
#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
/**
* Specifies the UTMI+ Data Width. This parameter is
* applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
* PHY_TYPE, this parameter indicates the data width between
* the MAC and the ULPI Wrapper.) Also, this parameter is
* applicable only if the OTG_HSPHY_WIDTH cC parameter was set
* to "8 and 16 bits", meaning that the core has been
* configured to work at either data path width.
*
* 8 or 16 bits (default 16)
*/
extern _LONG_CALL_ int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
#define dwc_param_phy_utmi_width_default 16
/**
* Specifies whether the ULPI operates at double or single
* data rate. This parameter is only applicable if PHY_TYPE is
* ULPI.
*
* 0 - single data rate ULPI interface with 8 bit wide data
* bus (default)
* 1 - double data rate ULPI interface with 4 bit wide data
* bus
*/
extern _LONG_CALL_ int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
#define dwc_param_phy_ulpi_ddr_default 0
/**
* Specifies whether to use the internal or external supply to
* drive the vbus with a ULPI phy.
*/
extern _LONG_CALL_ int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
#define DWC_PHY_ULPI_INTERNAL_VBUS 0
#define DWC_PHY_ULPI_EXTERNAL_VBUS 1
#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
/**
* Specifies whether to use the I2Cinterface for full speed PHY. This
* parameter is only applicable if PHY_TYPE is FS.
* 0 - No (default)
* 1 - Yes
*/
extern _LONG_CALL_ int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_i2c_enable_default 0
extern _LONG_CALL_ int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
#define dwc_param_ulpi_fs_ls_default 0
extern _LONG_CALL_ int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
#define dwc_param_ts_dline_default 0
/**
* Specifies whether dedicated transmit FIFOs are
* enabled for non periodic IN endpoints in device mode
* 0 - No
* 1 - Yes
*/
extern _LONG_CALL_ int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
core_if);
#define dwc_param_en_multiple_tx_fifo_default 1
/** Number of 4-byte words in each of the Tx FIFOs in device
* mode when dynamic FIFO sizing is enabled.
* 4 to 768 (default 256)
*/
//extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
// int fifo_num, int32_t val);
extern _LONG_CALL_ int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
int fifo_num);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
int fifo_num);
#define dwc_param_dev_tx_fifo_size_default 256
/** Thresholding enable flag-
* bit 0 - enable non-ISO Tx thresholding
* bit 1 - enable ISO Tx thresholding
* bit 2 - enable Rx thresholding
*/
extern _LONG_CALL_ int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
#define dwc_param_thr_ctl_default 0
/** Thresholding length for Tx
* FIFOs in 32 bit DWORDs
*/
extern _LONG_CALL_ int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
#define dwc_param_tx_thr_length_default 64
/** Thresholding length for Rx
* FIFOs in 32 bit DWORDs
*/
extern _LONG_CALL_ int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
#define dwc_param_rx_thr_length_default 64
/**
* Specifies whether LPM (Link Power Management) support is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_lpm_enable_default 1
/**
* Specifies whether LPM Errata (Link Power Management) support is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_besl_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_besl_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_besl_enable_default 0
/**
* Specifies baseline_besl default value
*/
extern _LONG_CALL_ int dwc_otg_set_param_baseline_besl(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_baseline_besl(dwc_otg_core_if_t * core_if);
#define dwc_param_baseline_besl_default 0
/**
* Specifies deep_besl default value
*/
extern _LONG_CALL_ int dwc_otg_set_param_deep_besl(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_deep_besl(dwc_otg_core_if_t * core_if);
#define dwc_param_deep_besl_default 15
/**
* Specifies whether PTI enhancement is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_pti_enable_default 0
/**
* Specifies whether MPI enhancement is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_mpi_enable_default 0
/**
* Specifies whether ADP capability is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
#define dwc_param_adp_enable_default 0
/**
* Specifies whether IC_USB capability is enabled
*/
extern _LONG_CALL_ int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
#define dwc_param_ic_usb_cap_default 0
extern _LONG_CALL_ int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
#define dwc_param_ahb_thr_ratio_default 0
extern _LONG_CALL_ int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
#define dwc_param_power_down_default 0
extern _LONG_CALL_ int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
#define dwc_param_reload_ctl_default 0
extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
#define dwc_param_dev_out_nak_default 0
extern _LONG_CALL_ int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
#define dwc_param_cont_on_bna_default 0
extern _LONG_CALL_ int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
#define dwc_param_ahb_single_default 0
extern _LONG_CALL_ int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
extern _LONG_CALL_ int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
#define dwc_param_otg_ver_default 0
/** @} */
/** @name Access to registers and bit-fields */
/**
* Dump core registers and SPRAM
*/
extern _LONG_CALL_ void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
extern _LONG_CALL_ void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
/**
* Get host negotiation status.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
/**
* Get srp status
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
/**
* Set hnpreq bit in the GOTGCTL register.
*/
extern _LONG_CALL_ void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get Content of SNPSID register.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
/**
* Get current mode.
* Returns 0 if in device mode, and 1 if in host mode.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
/**
* Get value of hnpcapable field in the GUSBCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
/**
* Set value of hnpcapable field in the GUSBCFG register
*/
extern _LONG_CALL_ void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of srpcapable field in the GUSBCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
/**
* Set value of srpcapable field in the GUSBCFG register
*/
extern _LONG_CALL_ void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of devspeed field in the DCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
/**
* Set value of devspeed field in the DCFG register
*/
extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get the value of busconnected field from the HPRT0 register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
/**
* Gets the device enumeration Speed.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
/**
* Get value of prtpwr field from the HPRT0 register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
/**
* Get value of flag indicating core state - hibernated or not
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
/**
* Set value of prtpwr field from the HPRT0 register
*/
extern _LONG_CALL_ void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of prtsusp field from the HPRT0 regsiter
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
/**
* Set value of prtpwr field from the HPRT0 register
*/
extern _LONG_CALL_ void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of ModeChTimEn field from the HCFG regsiter
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
/**
* Set value of ModeChTimEn field from the HCFG regsiter
*/
extern _LONG_CALL_ void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of Fram Interval field from the HFIR regsiter
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
/**
* Set value of Frame Interval field from the HFIR regsiter
*/
extern _LONG_CALL_ void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Set value of prtres field from the HPRT0 register
*FIXME Remove?
*/
extern _LONG_CALL_ void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of rmtwkupsig bit in DCTL register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
/**
* Get value of besl_reject bit in DCTL register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_beslreject(dwc_otg_core_if_t * core_if);
/**
* Set value of besl_reject bit in DCTL register
*/
extern _LONG_CALL_ void dwc_otg_set_beslreject(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of prt_sleep_sts field from the GLPMCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
/**
* Get value of rem_wkup_en field from the GLPMCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
/**
* Get value of appl_resp field from the GLPMCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
/**
* Set value of appl_resp field from the GLPMCFG register
*/
extern _LONG_CALL_ void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of hsic_connect field from the GLPMCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
/**
* Set value of hsic_connect field from the GLPMCFG register
*/
extern _LONG_CALL_ void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of inv_sel_hsic field from the GLPMCFG register.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
/**
* Set value of inv_sel_hsic field from the GLPMFG register.
*/
extern _LONG_CALL_ void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Set value of hird_thresh field from the GLPMFG register.
*/
extern _LONG_CALL_ void dwc_otg_set_hirdthresh(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* Get value of hird_thresh field from the GLPMFG register.
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hirdthresh(dwc_otg_core_if_t * core_if);
/*
* Some functions for accessing registers
*/
/**
* GOTGCTL register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GUSBCFG register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GRXFSIZ register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GNPTXFSIZ register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
extern _LONG_CALL_ uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GGPIO register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GUID register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* HPRT0 register
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
extern _LONG_CALL_ void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
/**
* GHPTXFSIZE
*/
extern _LONG_CALL_ uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
/** @} */
#endif /* __DWC_CORE_IF_H__ */

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USDK/component/soc/realtek/8195a/fwlib/ram_lib/usb_otg/include/dwc_otg_dbg.h Normal file
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/* ==========================================================================
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_DBG_H__
#define __DWC_OTG_DBG_H__
#include "section_config.h"
//#define OTGDEBUG 1
#define VERBOSE 1
/** @file
* This file defines debug levels.
* Debugging support vanishes in non-debug builds.
*/
/**
* The Debug Level bit-mask variable.
*/
extern uint32_t g_dbg_lvl;
/**
* Set the Debug Level variable.
*/
extern _LONG_CALL_ uint32_t SET_DEBUG_LEVEL(const uint32_t new);
/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */
#define DBG_CIL (0x2)
/** When debug level has the DBG_CILV bit set, display CIL Verbose debug
* messages */
#define DBG_CILV (0x20)
/** When debug level has the DBG_PCD bit set, display PCD (Device) debug
* messages */
#define DBG_PCD (0x4)
/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug
* messages */
#define DBG_PCDV (0x40)
/** When debug level has the DBG_HCD bit set, display Host debug messages */
#define DBG_HCD (0x8)
/** When debug level has the DBG_HCDV bit set, display Verbose Host debug
* messages */
#define DBG_HCDV (0x80)
/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host
* mode. */
#define DBG_HCD_URB (0x800)
/** When debug level has any bit set, display debug messages */
#define DBG_ANY (0xFF)
/** All debug messages off */
#define DBG_OFF 0
/** Prefix string for DWC_DEBUG print macros. */
#define USB_DWC "DWC_otg: "
/**
* Print a debug message when the Global debug level variable contains
* the bit defined in <code>lvl</code>.
*
* @param[in] lvl - Debug level, use one of the DBG_ constants above.
* @param[in] x - like printf
*
* Example:<p>
* <code>
* DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
* </code>
* <br>
* results in:<br>
* <code>
* usb-DWC_otg: dwc_otg_cil_init(ca867000)
* </code>
*/
#ifdef OTGDEBUG
//# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)DBG_8195A_OTG(x); }while(0)
# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x )
# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
#else
# define DWC_DEBUGPL(lvl, x...) do{}while(0)
# define DWC_DEBUGP(x...)
# define CHK_DEBUG_LEVEL(level) (0)
#endif /*DEBUG*/
#endif

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
* $Revision: #19 $
* $Date: 2010/11/15 $
* $Change: 1627671 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_DRIVER_H__
#define __DWC_OTG_DRIVER_H__
/** @file
* This file contains the interface to the Linux driver.
*/
//#include "dwc_otg_os_dep.h"
#include "dwc_otg_core_if.h"
#include "osdep_service.h"
/* Type declarations */
struct dwc_otg_pcd;
struct dwc_otg_hcd;
/**
* This structure is a wrapper that encapsulates the driver components used to
* manage a single DWC_otg controller.
*/
typedef struct dwc_otg_device {
/** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE
* VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD
* require this. */
//struct os_dependent os_dep;
/** Base address returned from ioremap() */
void *base;
uint32_t reg_offset;
/** Pointer to the core interface structure. */
dwc_otg_core_if_t *core_if;
/** Pointer to the PCD structure. */
struct dwc_otg_pcd *pcd;
/** Pointer to the HCD structure. */
struct dwc_otg_hcd *hcd;
/** Flag to indicate whether the common IRQ handler is installed. */
uint8_t common_irq_installed;
} dwc_otg_device_t;
/*We must clear S3C24XX_EINTPEND external interrupt register
* because after clearing in this register trigerred IRQ from
* H/W core in kernel interrupt can be occured again before OTG
* handlers clear all IRQ sources of Core registers because of
* timing latencies and Low Level IRQ Type.
*/
#ifdef CONFIG_MACH_IPMATE
#define S3C2410X_CLEAR_EINTPEND() \
do { \
__raw_writel(1UL << 11,S3C24XX_EINTPEND); \
} while (0)
#else
#define S3C2410X_CLEAR_EINTPEND() do { } while (0)
#endif
typedef struct USB_OTG_DRV_ADP {
dwc_otg_device_t *otgdev;
IRQ_HANDLE *pIrqHnd;
#if !TASK_SCHEDULER_DISABLED
#if defined(DWC_WITH_WLAN_OSDEP)
_sema Sema;
#else
_Sema Sema;
#endif
#else
u32 Sema;
#endif
#if !TASK_SCHEDULER_DISABLED
#if defined(DWC_WITH_WLAN_OSDEP)
struct task_struct OTGTask;
#else
xTaskHandle OTGTask;
#endif
#else
u32 OTGTask;
#endif
}USB_OTG_DRV_ADP,*PUSB_OTG_DRV_ADP;
typedef struct _DWC_OTG_ADAPTER_ {
u32 temp0;
dwc_otg_device_t *otgdev;
u8 TestItem;
}DWC_OTG_ADAPTER, *PDWC_OTG_ADAPTER;
void dwc_otg_disable_irq(IN VOID);
void dwc_otg_enable_irq(IN VOID);
#endif

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
* $Revision: #58 $
* $Date: 2011/09/15 $
* $Change: 1846647 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_DEVICE_ONLY
#ifndef __DWC_HCD_H__
#define __DWC_HCD_H__
//#include "dwc_otg_os_dep.h"
#include "usb.h"
#include "dwc_otg_hcd_if.h"
#include "dwc_otg_core_if.h"
#include "dwc_list.h"
#include "dwc_otg_cil.h"
#undef DWC_HS_ELECT_TST
/**
* @file
*
* This file contains the structures, constants, and interfaces for
* the Host Contoller Driver (HCD).
*
* The Host Controller Driver (HCD) is responsible for translating requests
* from the USB Driver into the appropriate actions on the DWC_otg controller.
* It isolates the USBD from the specifics of the controller by providing an
* API to the USBD.
*/
struct dwc_otg_hcd_pipe_info {
uint8_t dev_addr;
uint8_t ep_num;
uint8_t pipe_type;
uint8_t pipe_dir;
uint16_t mps;
};
struct dwc_otg_hcd_iso_packet_desc {
uint32_t offset;
uint32_t length;
uint32_t actual_length;
uint32_t status;
};
struct dwc_otg_qtd;
struct dwc_otg_hcd_urb {
void *priv;
struct dwc_otg_qtd *qtd;
void *buf;
dwc_dma_t dma;
void *setup_packet;
dwc_dma_t setup_dma;
uint32_t length;
uint32_t actual_length;
uint32_t status;
uint32_t error_count;
uint32_t packet_count;
uint32_t flags;
uint16_t interval;
struct dwc_otg_hcd_pipe_info pipe_info;
struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
};
extern _LONG_CALL_
uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe);
extern _LONG_CALL_
uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
*pipe);
extern _LONG_CALL_
void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
uint8_t devaddr, uint8_t ep_num,
uint8_t pipe_type, uint8_t pipe_dir,
uint16_t mps);
/**
* Phases for control transfers.
*/
typedef enum dwc_otg_control_phase {
DWC_OTG_CONTROL_SETUP,
DWC_OTG_CONTROL_DATA,
DWC_OTG_CONTROL_STATUS
} dwc_otg_control_phase_e;
/** Transaction types. */
typedef enum dwc_otg_transaction_type {
DWC_OTG_TRANSACTION_NONE,
DWC_OTG_TRANSACTION_PERIODIC,
DWC_OTG_TRANSACTION_NON_PERIODIC,
DWC_OTG_TRANSACTION_ALL
} dwc_otg_transaction_type_e;
struct dwc_otg_qh;
/**
* A Queue Transfer Descriptor (QTD) holds the state of a bulk, control,
* interrupt, or isochronous transfer. A single QTD is created for each URB
* (of one of these types) submitted to the HCD. The transfer associated with
* a QTD may require one or multiple transactions.
*
* A QTD is linked to a Queue Head, which is entered in either the
* non-periodic or periodic schedule for execution. When a QTD is chosen for
* execution, some or all of its transactions may be executed. After
* execution, the state of the QTD is updated. The QTD may be retired if all
* its transactions are complete or if an error occurred. Otherwise, it
* remains in the schedule so more transactions can be executed later.
*/
typedef struct dwc_otg_qtd {
/**
* Determines the PID of the next data packet for the data phase of
* control transfers. Ignored for other transfer types.<br>
* One of the following values:
* - DWC_OTG_HC_PID_DATA0
* - DWC_OTG_HC_PID_DATA1
*/
uint8_t data_toggle;
/** Current phase for control transfers (Setup, Data, or Status). */
dwc_otg_control_phase_e control_phase;
/** Keep track of the current split type
* for FS/LS endpoints on a HS Hub */
uint8_t complete_split;
/** How many bytes transferred during SSPLIT OUT */
uint32_t ssplit_out_xfer_count;
/**
* Holds the number of bus errors that have occurred for a transaction
* within this transfer.
*/
uint8_t error_count;
/**
* Index of the next frame descriptor for an isochronous transfer. A
* frame descriptor describes the buffer position and length of the
* data to be transferred in the next scheduled (micro)frame of an
* isochronous transfer. It also holds status for that transaction.
* The frame index starts at 0.
*/
uint16_t isoc_frame_index;
/** Position of the ISOC split on full/low speed */
uint8_t isoc_split_pos;
/** Position of the ISOC split in the buffer for the current frame */
uint16_t isoc_split_offset;
/** URB for this transfer */
struct dwc_otg_hcd_urb *urb;
struct dwc_otg_qh *qh;
/** This list of QTDs */
DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
/** Indicates if this QTD is currently processed by HW. */
uint8_t in_process;
/** Number of DMA descriptors for this QTD */
uint8_t n_desc;
/**
* Last activated frame(packet) index.
* Used in Descriptor DMA mode only.
*/
uint16_t isoc_frame_index_last;
} dwc_otg_qtd_t;
DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
/**
* A Queue Head (QH) holds the static characteristics of an endpoint and
* maintains a list of transfers (QTDs) for that endpoint. A QH structure may
* be entered in either the non-periodic or periodic schedule.
*/
typedef struct dwc_otg_qh {
/**
* Endpoint type.
* One of the following values:
* - UE_CONTROL
* - UE_BULK
* - UE_INTERRUPT
* - UE_ISOCHRONOUS
*/
uint8_t ep_type;
uint8_t ep_is_in;
/** wMaxPacketSize Field of Endpoint Descriptor. */
uint16_t maxp;
/**
* Device speed.
* One of the following values:
* - DWC_OTG_EP_SPEED_LOW
* - DWC_OTG_EP_SPEED_FULL
* - DWC_OTG_EP_SPEED_HIGH
*/
uint8_t dev_speed;
/**
* Determines the PID of the next data packet for non-control
* transfers. Ignored for control transfers.<br>
* One of the following values:
* - DWC_OTG_HC_PID_DATA0
* - DWC_OTG_HC_PID_DATA1
*/
uint8_t data_toggle;
/** Ping state if 1. */
uint8_t ping_state;
/**
* List of QTDs for this QH.
*/
struct dwc_otg_qtd_list qtd_list;
/** Host channel currently processing transfers for this QH. */
struct dwc_hc *channel;
/** Full/low speed endpoint on high-speed hub requires split. */
uint8_t do_split;
/** @name Periodic schedule information */
/** @{ */
/** Bandwidth in microseconds per (micro)frame. */
uint16_t usecs;
/** Interval between transfers in (micro)frames. */
uint16_t interval;
/**
* (micro)frame to initialize a periodic transfer. The transfer
* executes in the following (micro)frame.
*/
uint16_t sched_frame;
/** (micro)frame at which last start split was initialized. */
uint16_t start_split_frame;
/** @} */
/**
* Used instead of original buffer if
* it(physical address) is not dword-aligned.
*/
uint8_t *dw_align_buf;
dwc_dma_t dw_align_buf_dma;
/** Entry for QH in either the periodic or non-periodic schedule. */
dwc_list_link_t qh_list_entry;
/** @name Descriptor DMA support */
/** @{ */
/** Descriptor List. */
dwc_otg_host_dma_desc_t *desc_list;
/** Descriptor List physical address. */
dwc_dma_t desc_list_dma;
/**
* Xfer Bytes array.
* Each element corresponds to a descriptor and indicates
* original XferSize size value for the descriptor.
*/
uint32_t *n_bytes;
/** Actual number of transfer descriptors in a list. */
uint16_t ntd;
/** First activated isochronous transfer descriptor index. */
uint8_t td_first;
/** Last activated isochronous transfer descriptor index. */
uint8_t td_last;
/** @} */
} dwc_otg_qh_t;
DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
/**
* This structure holds the state of the HCD, including the non-periodic and
* periodic schedules.
*/
struct dwc_otg_hcd {
/** The DWC otg device pointer */
struct dwc_otg_device *otg_dev;
/** DWC OTG Core Interface Layer */
dwc_otg_core_if_t *core_if;
/** Function HCD driver callbacks */
struct dwc_otg_hcd_function_ops *fops;
/** Internal DWC HCD Flags */
volatile union dwc_otg_hcd_internal_flags {
uint32_t d32;
struct {
unsigned port_connect_status_change:1;
unsigned port_connect_status:1;
unsigned port_reset_change:1;
unsigned port_enable_change:1;
unsigned port_suspend_change:1;
unsigned port_over_current_change:1;
unsigned port_l1_change:1;
unsigned reserved:26;
} b;
} flags;
/**
* Inactive items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are not
* currently assigned to a host channel.
*/
dwc_list_link_t non_periodic_sched_inactive;
/**
* Active items in the non-periodic schedule. This is a list of
* Queue Heads. Transfers associated with these Queue Heads are
* currently assigned to a host channel.
*/
dwc_list_link_t non_periodic_sched_active;
/**
* Pointer to the next Queue Head to process in the active
* non-periodic schedule.
*/
dwc_list_link_t *non_periodic_qh_ptr;
/**
* Inactive items in the periodic schedule. This is a list of QHs for
* periodic transfers that are _not_ scheduled for the next frame.
* Each QH in the list has an interval counter that determines when it
* needs to be scheduled for execution. This scheduling mechanism
* allows only a simple calculation for periodic bandwidth used (i.e.
* must assume that all periodic transfers may need to execute in the
* same frame). However, it greatly simplifies scheduling and should
* be sufficient for the vast majority of OTG hosts, which need to
* connect to a small number of peripherals at one time.
*
* Items move from this list to periodic_sched_ready when the QH
* interval counter is 0 at SOF.
*/
dwc_list_link_t periodic_sched_inactive;
/**
* List of periodic QHs that are ready for execution in the next
* frame, but have not yet been assigned to host channels.
*
* Items move from this list to periodic_sched_assigned as host
* channels become available during the current frame.
*/
dwc_list_link_t periodic_sched_ready;
/**
* List of periodic QHs to be executed in the next frame that are
* assigned to host channels.
*
* Items move from this list to periodic_sched_queued as the
* transactions for the QH are queued to the DWC_otg controller.
*/
dwc_list_link_t periodic_sched_assigned;
/**
* List of periodic QHs that have been queued for execution.
*
* Items move from this list to either periodic_sched_inactive or
* periodic_sched_ready when the channel associated with the transfer
* is released. If the interval for the QH is 1, the item moves to
* periodic_sched_ready because it must be rescheduled for the next
* frame. Otherwise, the item moves to periodic_sched_inactive.
*/
dwc_list_link_t periodic_sched_queued;
/**
* Total bandwidth claimed so far for periodic transfers. This value
* is in microseconds per (micro)frame. The assumption is that all
* periodic transfers may occur in the same (micro)frame.
*/
uint16_t periodic_usecs;
/**
* Frame number read from the core at SOF. The value ranges from 0 to
* DWC_HFNUM_MAX_FRNUM.
*/
uint16_t frame_number;
/**
* Count of periodic QHs, if using several eps. For SOF enable/disable.
*/
uint16_t periodic_qh_count;
/**
* Free host channels in the controller. This is a list of
* dwc_hc_t items.
*/
struct hc_list free_hc_list;
/**
* Number of host channels assigned to periodic transfers. Currently
* assuming that there is a dedicated host channel for each periodic
* transaction and at least one host channel available for
* non-periodic transactions.
*/
int periodic_channels;
/**
* Number of host channels assigned to non-periodic transfers.
*/
int non_periodic_channels;
/**
* Array of pointers to the host channel descriptors. Allows accessing
* a host channel descriptor given the host channel number. This is
* useful in interrupt handlers.
*/
struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
/**
* Buffer to use for any data received during the status phase of a
* control transfer. Normally no data is transferred during the status
* phase. This buffer is used as a bit bucket.
*/
uint8_t *status_buf;
/**
* DMA address for status_buf.
*/
dma_addr_t status_buf_dma;
#define DWC_OTG_HCD_STATUS_BUF_SIZE 64
/**
* Connection timer. An OTG host must display a message if the device
* does not connect. Started when the VBus power is turned on via
* sysfs attribute "buspower".
*/
dwc_timer_t *conn_timer;
/* Tasket to do a reset */
//dwc_tasklet_t *reset_tasklet;
/* */
dwc_spinlock_t *lock;
/**
* Private data that could be used by OS wrapper.
*/
void *priv;
uint8_t otg_port;
/** Frame List */
uint32_t *frame_list;
/** Frame List DMA address */
dma_addr_t frame_list_dma;
#ifdef OTGDEBUG
uint32_t frrem_samples;
uint64_t frrem_accum;
uint32_t hfnum_7_samples_a;
uint64_t hfnum_7_frrem_accum_a;
uint32_t hfnum_0_samples_a;
uint64_t hfnum_0_frrem_accum_a;
uint32_t hfnum_other_samples_a;
uint64_t hfnum_other_frrem_accum_a;
uint32_t hfnum_7_samples_b;
uint64_t hfnum_7_frrem_accum_b;
uint32_t hfnum_0_samples_b;
uint64_t hfnum_0_frrem_accum_b;
uint32_t hfnum_other_samples_b;
uint64_t hfnum_other_frrem_accum_b;
#endif
};
/** @name Transaction Execution Functions */
/** @{ */
extern _LONG_CALL_ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
* hcd);
extern _LONG_CALL_ void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
dwc_otg_transaction_type_e tr_type);
/** @} */
/** @name Interrupt Handler Functions */
/** @{ */
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
uint32_t num);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
dwc_otg_hcd);
/** @} */
/** @name Schedule Queue Functions */
/** @{ */
/* Implemented in dwc_otg_hcd_queue.c */
extern _LONG_CALL_ dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
dwc_otg_hcd_urb_t * urb, int atomic_alloc);
extern _LONG_CALL_ void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
int sched_csplit);
/** Remove and free a QH */
extern _LONG_CALL_
void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
dwc_otg_qh_t * qh);
/** Allocates memory for a QH structure.
* @return Returns the memory allocate or NULL on error. */
extern _LONG_CALL_
dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc);
extern _LONG_CALL_ dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
int atomic_alloc);
extern _LONG_CALL_ void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
extern _LONG_CALL_ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
dwc_otg_qh_t ** qh, int atomic_alloc);
/** Allocates memory for a QTD structure.
* @return Returns the memory allocate or NULL on error. */
extern _LONG_CALL_
dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc);
/** Frees the memory for a QTD structure. QTD should already be removed from
* list.
* @param qtd QTD to free.*/
extern _LONG_CALL_
void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd);
/** Removes a QTD from list.
* @param hcd HCD instance.
* @param qtd QTD to remove from list.
* @param qh QTD belongs to.
*/
extern _LONG_CALL_
void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
dwc_otg_qtd_t * qtd,
dwc_otg_qh_t * qh);
/** Remove and free a QTD
* Need to disable IRQ and hold hcd lock while calling this function out of
* interrupt servicing chain */
extern _LONG_CALL_
void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
dwc_otg_qtd_t * qtd,
dwc_otg_qh_t * qh);
/** @} */
/** @name Descriptor DMA Supporting Functions */
/** @{ */
extern _LONG_CALL_ void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
dwc_hc_t * hc,
dwc_otg_hc_regs_t * hc_regs,
dwc_otg_halt_status_e halt_status);
extern _LONG_CALL_ int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
extern _LONG_CALL_ void reset_tasklet_func(void *data);
/** @} */
/** @name Internal Functions */
/** @{ */
extern _LONG_CALL_ dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
/** @} */
#ifdef CONFIG_USB_DWC_OTG_LPM
extern _LONG_CALL_ int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
uint8_t devaddr);
extern _LONG_CALL_ void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
#endif
/** Gets the QH that contains the list_head */
#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
/** Gets the QTD that contains the list_head */
#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
/** Check if QH is non-periodic */
#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
(_qh_ptr_->ep_type == UE_CONTROL))
/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */
#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
/** Packet size for any kind of endpoint descriptor */
#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
/**
* Returns true if _frame1 is less than or equal to _frame2. The comparison is
* done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the
* frame number when the max frame number is reached.
*/
extern _LONG_CALL_
int dwc_frame_num_le(uint16_t frame1, uint16_t frame2);
/**
* Returns true if _frame1 is greater than _frame2. The comparison is done
* modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame
* number when the max frame number is reached.
*/
extern _LONG_CALL_
int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2);
/**
* Increments _frame by the amount specified by _inc. The addition is done
* modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value.
*/
extern _LONG_CALL_
uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc);
extern _LONG_CALL_
uint16_t dwc_full_frame_num(uint16_t frame);
extern _LONG_CALL_
uint16_t dwc_micro_frame_num(uint16_t frame);
extern _LONG_CALL_ void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
dwc_otg_hc_regs_t * hc_regs,
dwc_otg_qtd_t * qtd);
extern _LONG_CALL_ void dwc_hcd_data_init(void);
#ifdef OTGDEBUG
/**
* Macro to sample the remaining PHY clocks left in the current frame. This
* may be used during debugging to determine the average time it takes to
* execute sections of code. There are two possible sample points, "a" and
* "b", so the _letter argument must be one of these values.
*
* To dump the average sample times, read the "hcd_frrem" sysfs attribute. For
* example, "cat /sys/devices/lm0/hcd_frrem".
*/
#define dwc_sample_frrem(_hcd, _qh, _letter) \
{ \
hfnum_data_t hfnum; \
dwc_otg_qtd_t *qtd; \
qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
switch (hfnum.b.frnum & 0x7) { \
case 7: \
_hcd->hfnum_7_samples_##_letter++; \
_hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
case 0: \
_hcd->hfnum_0_samples_##_letter++; \
_hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
default: \
_hcd->hfnum_other_samples_##_letter++; \
_hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
break; \
} \
} \
}
#else
#define dwc_sample_frrem(_hcd, _qh, _letter)
#endif
#endif
#endif /* DWC_DEVICE_ONLY */

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
* $Revision: #12 $
* $Date: 2011/10/26 $
* $Change: 1873028 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_DEVICE_ONLY
#ifndef __DWC_HCD_IF_H__
#define __DWC_HCD_IF_H__
#include "dwc_otg_core_if.h"
/** @file
* This file defines DWC_OTG HCD Core API.
*/
struct dwc_otg_hcd;
typedef struct dwc_otg_hcd dwc_otg_hcd_t;
struct dwc_otg_hcd_urb;
typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
/** @name HCD Function Driver Callbacks */
/** @{ */
/** This function is called whenever core switches to host mode. */
typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
/** This function is called when device has been disconnected */
typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */
typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle,
uint32_t * hub_addr,
uint32_t * port_addr);
/** Via this function HCD core gets device speed */
typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle);
/** This function is called when urb is completed */
typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
void *urb_handle,
dwc_otg_hcd_urb_t * dwc_otg_urb,
int32_t status);
/** Via this function HCD core gets b_hnp_enable parameter */
typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
struct dwc_otg_hcd_function_ops {
dwc_otg_hcd_start_cb_t start;
dwc_otg_hcd_disconnect_cb_t disconnect;
dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
dwc_otg_hcd_speed_from_urb_cb_t speed;
dwc_otg_hcd_complete_urb_cb_t complete;
dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
};
/** @} */
/** @name HCD Core API */
/** @{ */
/** This function allocates dwc_otg_hcd structure and returns pointer on it. */
extern _LONG_CALL_ dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
/** This function should be called to initiate HCD Core.
*
* @param hcd The HCD
* @param core_if The DWC_OTG Core
*
* Returns -DWC_E_NO_MEMORY if no enough memory.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
/** Frees HCD
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
/** This function should be called on every hardware interrupt.
*
* @param dwc_otg_hcd The HCD
*
* Returns non zero if interrupt is handled
* Return 0 if interrupt is not handled
*/
extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
/**
* Returns private data set by
* dwc_otg_hcd_set_priv_data function.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
/**
* Set private data.
*
* @param hcd The HCD
* @param priv_data pointer to be stored in private data
*/
extern _LONG_CALL_ void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
/**
* This function initializes the HCD Core.
*
* @param hcd The HCD
* @param fops The Function Driver Operations data structure containing pointers to all callbacks.
*
* Returns -DWC_E_NO_DEVICE if Core is currently is in device mode.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
struct dwc_otg_hcd_function_ops *fops);
/**
* Halts the DWC_otg host mode operations in a clean manner. USB transfers are
* stopped.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
/**
* Handles hub class-specific requests.
*
* @param dwc_otg_hcd The HCD
* @param typeReq Request Type
* @param wValue wValue from control request
* @param wIndex wIndex from control request
* @param buf data buffer
* @param wLength data buffer length
*
* Returns -DWC_E_INVALID if invalid argument is passed
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
uint16_t typeReq, uint16_t wValue,
uint16_t wIndex, uint8_t * buf,
uint16_t wLength);
/**
* Returns otg port number.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
/**
* Returns OTG version - either 1.3 or 2.0.
*
* @param core_if The core_if structure pointer
*/
extern _LONG_CALL_ uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
/**
* Returns 1 if currently core is acting as B host, and 0 otherwise.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
/**
* Returns current frame number.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
/**
* Dumps hcd state.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
/**
* Dump the average frame remaining at SOF. This can be used to
* determine average interrupt latency. Frame remaining is also shown for
* start transfer and two additional sample points.
* Currently this function is not implemented.
*
* @param hcd The HCD
*/
extern _LONG_CALL_ void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
/**
* Sends LPM transaction to the local device.
*
* @param hcd The HCD
* @param devaddr Device Address
* @param hird Host initiated resume duration
* @param bRemoteWake Value of bRemoteWake field in LPM transaction
*
* Returns negative value if sending LPM transaction was not succeeded.
* Returns 0 on success.
*/
extern _LONG_CALL_ int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
uint8_t hird, uint8_t bRemoteWake);
/* URB interface */
/**
* Allocates memory for dwc_otg_hcd_urb structure.
* Allocated memory should be freed by call of DWC_FREE.
*
* @param hcd The HCD
* @param iso_desc_count Count of ISOC descriptors
* @param atomic_alloc Specefies whether to perform atomic allocation.
*/
extern _LONG_CALL_ dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
int iso_desc_count,
int atomic_alloc);
/**
* Set pipe information in URB.
*
* @param hcd_urb DWC_OTG URB
* @param devaddr Device Address
* @param ep_num Endpoint Number
* @param ep_type Endpoint Type
* @param ep_dir Endpoint Direction
* @param mps Max Packet Size
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
uint8_t devaddr, uint8_t ep_num,
uint8_t ep_type, uint8_t ep_dir,
uint16_t mps);
/* Transfer flags */
#define URB_GIVEBACK_ASAP 0x1
#define URB_SEND_ZERO_PACKET 0x2
/**
* Sets dwc_otg_hcd_urb parameters.
*
* @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
* @param urb_handle Unique handle for request, this will be passed back
* to function driver in completion callback.
* @param buf The buffer for the data
* @param dma The DMA buffer for the data
* @param buflen Transfer length
* @param sp Buffer for setup data
* @param sp_dma DMA address of setup data buffer
* @param flags Transfer flags
* @param interval Polling interval for interrupt or isochronous transfers.
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
void *urb_handle, void *buf,
dwc_dma_t dma, uint32_t buflen, void *sp,
dwc_dma_t sp_dma, uint32_t flags,
uint16_t interval);
/** Gets status from dwc_otg_hcd_urb
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
/** Gets actual length from dwc_otg_hcd_urb
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
dwc_otg_urb);
/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs
*
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
dwc_otg_urb);
/** Set ISOC descriptor offset and length
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
* @param offset Offset from beginig of buffer.
* @param length Transaction length
*/
extern _LONG_CALL_ void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
int desc_num, uint32_t offset,
uint32_t length);
/** Get status of ISOC descriptor, specified by desc_num
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
dwc_otg_urb, int desc_num);
/** Get actual length of ISOC descriptor, specified by desc_num
*
* @param dwc_otg_urb DWC_OTG URB
* @param desc_num ISOC descriptor number
*/
extern _LONG_CALL_ uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
dwc_otg_urb,
int desc_num);
/** Queue URB. After transfer is completes, the complete callback will be called with the URB status
*
* @param dwc_otg_hcd The HCD
* @param dwc_otg_urb DWC_OTG URB
* @param ep_handle Out parameter for returning endpoint handle
* @param atomic_alloc Flag to do atomic allocation if needed
*
* Returns -DWC_E_NO_DEVICE if no device is connected.
* Returns -DWC_E_NO_MEMORY if there is no enough memory.
* Returns 0 on success.
*/
extern _LONG_CALL_ int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
dwc_otg_hcd_urb_t * dwc_otg_urb,
void **ep_handle, int atomic_alloc);
/** De-queue the specified URB
*
* @param dwc_otg_hcd The HCD
* @param dwc_otg_urb DWC_OTG URB
*/
extern _LONG_CALL_ int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
dwc_otg_hcd_urb_t * dwc_otg_urb);
/** Frees resources in the DWC_otg controller related to a given endpoint.
* Any URBs for the endpoint must already be dequeued.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
* @param retry Number of retries if there are queued transfers.
*
* Returns -DWC_E_INVALID if invalid arguments are passed.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
int retry);
/* Resets the data toggle in qh structure. This function can be called from
* usb_clear_halt routine.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
*
* Returns -DWC_E_INVALID if invalid arguments are passed.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
/** Returns 1 if status of specified port is changed and 0 otherwise.
*
* @param hcd The HCD
* @param port Port number
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
/** Call this function to check if bandwidth was allocated for specified endpoint.
* Only for ISOC and INTERRUPT endpoints.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
void *ep_handle);
/** Call this function to check if bandwidth was freed for specified endpoint.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
/** Returns bandwidth allocated for specified endpoint in microseconds.
* Only for ISOC and INTERRUPT endpoints.
*
* @param hcd The HCD
* @param ep_handle Endpoint handle
*/
extern _LONG_CALL_ uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
void *ep_handle);
/** @} */
#endif /* __DWC_HCD_IF_H__ */
#endif /* DWC_DEVICE_ONLY */

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#ifndef _DWC_OS_DEP_H_
#define _DWC_OS_DEP_H_
#include "errno.h"
#endif /* _DWC_OS_DEP_H_ */

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
* $Revision: #49 $
* $Date: 2013/05/16 $
* $Change: 2231774 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_HOST_ONLY
#if !defined(__DWC_PCD_H__)
#define __DWC_PCD_H__
#include "dwc_otg_os_dep.h"
#include "usb.h"
#include "dwc_otg_cil.h"
#include "dwc_otg_pcd_if.h"
struct cfiobject;
/**
* @file
*
* This file contains the structures, constants, and interfaces for
* the Perpherial Contoller Driver (PCD).
*
* The Peripheral Controller Driver (PCD) for Linux will implement the
* Gadget API, so that the existing Gadget drivers can be used. For
* the Mass Storage Function driver the File-backed USB Storage Gadget
* (FBS) driver will be used. The FBS driver supports the
* Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only
* transports.
*
*/
/** Invalid DMA Address */
#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0)
/** Max Transfer size for any EP */
#define DDMA_MAX_TRANSFER_SIZE 65535
/**
* Get the pointer to the core_if from the pcd pointer.
*/
#define GET_CORE_IF( _pcd ) (_pcd->core_if)
/**
* States of EP0.
*/
typedef enum ep0_state {
EP0_DISCONNECT, /* no host */
EP0_IDLE,
EP0_IN_DATA_PHASE,
EP0_OUT_DATA_PHASE,
EP0_IN_STATUS_PHASE,
EP0_OUT_STATUS_PHASE,
EP0_STALL,
} ep0state_e;
/** Fordward declaration.*/
struct dwc_otg_pcd;
/** DWC_otg iso request structure.
*
*/
typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
#ifdef DWC_UTE_PER_IO
XXX
/**
* This shall be the exact analogy of the same type structure defined in the
* usb_gadget.h. Each descriptor contains
*/
struct dwc_iso_pkt_desc_port {
uint32_t offset;
uint32_t length; /* expected length */
uint32_t actual_length;
uint32_t status;
};
struct dwc_iso_xreq_port {
/** transfer/submission flag */
uint32_t tr_sub_flags;
/** Start the request ASAP */
#define DWC_EREQ_TF_ASAP 0x00000002
/** Just enqueue the request w/o initiating a transfer */
#define DWC_EREQ_TF_ENQUEUE 0x00000004
/**
* count of ISO packets attached to this request - shall
* not exceed the pio_alloc_pkt_count
*/
uint32_t pio_pkt_count;
/** count of ISO packets allocated for this request */
uint32_t pio_alloc_pkt_count;
/** number of ISO packet errors */
uint32_t error_count;
/** reserved for future extension */
uint32_t res;
/** Will be allocated and freed in the UTE gadget and based on the CFC value */
struct dwc_iso_pkt_desc_port *per_io_frame_descs;
};
#endif
/** DWC_otg request structure.
* This structure is a list of requests.
*/
typedef struct dwc_otg_pcd_request {
void *priv;
void *buf;
dwc_dma_t dma;
uint32_t length;
uint32_t actual;
unsigned sent_zlp:1;
/**
* Used instead of original buffer if
* it(physical address) is not dword-aligned.
**/
uint8_t *dw_align_buf;
dwc_dma_t dw_align_buf_dma;
DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
#ifdef DWC_UTE_PER_IO
struct dwc_iso_xreq_port ext_req;
//void *priv_ereq_nport; /* */
#endif
} dwc_otg_pcd_request_t;
DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
/** PCD EP structure.
* This structure describes an EP, there is an array of EPs in the PCD
* structure.
*/
typedef struct dwc_otg_pcd_ep {
/** USB EP Descriptor */
const usb_endpoint_descriptor_t *desc;
/** queue of dwc_otg_pcd_requests. */
struct req_list queue;
unsigned stopped:1;
unsigned disabling:1;
unsigned dma:1;
unsigned queue_sof:1;
#ifdef DWC_EN_ISOC
/** ISOC req handle passed */
void *iso_req_handle;
#endif //_EN_ISOC_
/** DWC_otg ep data. */
dwc_ep_t dwc_ep;
/** Pointer to PCD */
struct dwc_otg_pcd *pcd;
void *priv;
} dwc_otg_pcd_ep_t;
/** DWC_otg PCD Structure.
* This structure encapsulates the data for the dwc_otg PCD.
*/
struct dwc_otg_pcd {
const struct dwc_otg_pcd_function_ops *fops;
/** The DWC otg device pointer */
struct dwc_otg_device *otg_dev;
/** Core Interface */
dwc_otg_core_if_t *core_if;
/** State of EP0 */
ep0state_e ep0state;
/** EP0 Request is pending */
unsigned ep0_pending:1;
/** Indicates when SET CONFIGURATION Request is in process */
unsigned request_config:1;
/** The state of the Remote Wakeup Enable. */
unsigned remote_wakeup_enable:1;
/** The state of the B-Device HNP Enable. */
unsigned b_hnp_enable:1;
/** The state of A-Device HNP Support. */
unsigned a_hnp_support:1;
/** The state of the A-Device Alt HNP support. */
unsigned a_alt_hnp_support:1;
/** Count of pending Requests */
unsigned request_pending;
/** SETUP packet for EP0
* This structure is allocated as a DMA buffer on PCD initialization
* with enough space for up to 3 setup packets.
*/
union {
usb_device_request_t req;
uint32_t d32[2];
} *setup_pkt;
dwc_dma_t setup_pkt_dma_handle;
/* Additional buffer and flag for CTRL_WR premature case */
uint8_t *backup_buf;
unsigned data_terminated;
/** 2-byte dma buffer used to return status from GET_STATUS */
uint16_t *status_buf;
dwc_dma_t status_buf_dma_handle;
/** EP0 */
dwc_otg_pcd_ep_t ep0;
/** Array of IN EPs. */
dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
/** Array of OUT EPs. */
dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
/** number of valid EPs in the above array. */
// unsigned num_eps : 4;
dwc_spinlock_t *lock;
/** Tasklet to defer starting of TEST mode transmissions until
* Status Phase has been completed.
*/
dwc_tasklet_t *test_mode_tasklet;
/** Tasklet to delay starting of xfer in DMA mode */
dwc_tasklet_t *start_xfer_tasklet;
/** The test mode to enter when the tasklet is executed. */
unsigned test_mode;
/** The cfi_api structure that implements most of the CFI API
* and OTG specific core configuration functionality
*/
#ifdef DWC_UTE_CFI
struct cfiobject *cfi;
#endif
};
//FIXME this functions should be static, and this prototypes should be removed
extern _LONG_CALL_ void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
extern _LONG_CALL_ void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
dwc_otg_pcd_request_t * req, int32_t status);
_LONG_CALL_ void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
void *req_handle);
extern _LONG_CALL_ void dwc_otg_pcd_start_iso_ddma(dwc_otg_core_if_t * core_if,
dwc_otg_pcd_ep_t * ep);
extern _LONG_CALL_ void do_test_mode(void *data);
extern _LONG_CALL_ void dwc_pcd_data_init(VOID);
#endif
#endif /* DWC_HOST_ONLY */

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
* $Revision: #13 $
* $Date: 2012/12/12 $
* $Change: 2125019 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#if 1//ndef DWC_HOST_ONLY
#if !defined(__DWC_PCD_IF_H__)
#define __DWC_PCD_IF_H__
//#include "dwc_os.h"
#include "dwc_otg_core_if.h"
/** @file
* This file defines DWC_OTG PCD Core API.
*/
struct dwc_otg_pcd;
typedef struct dwc_otg_pcd dwc_otg_pcd_t;
/** Maxpacket size for EP0 */
#define MAX_EP0_SIZE 64
/** Maxpacket size for any EP */
#define MAX_PACKET_SIZE 2048
/** @name Function Driver Callbacks */
/** @{ */
/** This function will be called whenever a previously queued request has
* completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a
* failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset,
* or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid
* parameters. */
typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int32_t status,
uint32_t actual);
/**
* This function will be called whenever a previousle queued ISOC request has
* completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count
* function.
* The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_*
* functions.
*/
typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int proc_buf_num);
/** This function should handle any SETUP request that cannot be handled by the
* PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any
* class-specific requests, etc. The function must non-blocking.
*
* Returns 0 on success.
* Returns -DWC_E_NOT_SUPPORTED if the request is not supported.
* Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes.
* Returns -DWC_E_SHUTDOWN on any other error. */
typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
/** This is called whenever the device has been disconnected. The function
* driver should take appropriate action to clean up all pending requests in the
* PCD Core, remove all endpoints (except ep0), and initialize back to reset
* state. */
typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has been connected. */
typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
/** This function is called when device has been suspended */
typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has received LPM tokens, i.e.
* device has been sent to sleep state. */
typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called when device has been resumed
* from suspend(L2) or L1 sleep state. */
typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called whenever hnp params has been changed.
* User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions
* to get hnp parameters. */
typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
/** This function is called whenever USB RESET is detected. */
typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
/**
*
* @param ep_handle Void pointer to the usb_ep structure
* @param ereq_port Pointer to the extended request structure created in the
* portable part.
*/
typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle, int32_t status,
void *ereq_port);
/** Function Driver Ops Data Structure */
struct dwc_otg_pcd_function_ops {
dwc_connect_cb_t connect;
dwc_disconnect_cb_t disconnect;
dwc_setup_cb_t setup;
dwc_completion_cb_t complete;
dwc_isoc_completion_cb_t isoc_complete;
dwc_suspend_cb_t suspend;
dwc_sleep_cb_t sleep;
dwc_resume_cb_t resume;
dwc_reset_cb_t reset;
dwc_hnp_params_changed_cb_t hnp_changed;
cfi_setup_cb_t cfi_setup;
#ifdef DWC_UTE_PER_IO
xiso_completion_cb_t xisoc_complete;
#endif
};
/** @} */
/** @name Function Driver Functions */
/** @{ */
/** Call this function to get pointer on dwc_otg_pcd_t,
* this pointer will be used for all PCD API functions.
*
* @param core_if The DWC_OTG Core
*/
extern _LONG_CALL_ dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
/** Frees PCD allocated by dwc_otg_pcd_init
*
* @param pcd The PCD
*/
extern _LONG_CALL_ void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
/** Call this to bind the function driver to the PCD Core.
*
* @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
* @param fops The Function Driver Ops data structure containing pointers to all callbacks.
*/
extern _LONG_CALL_ void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
const struct dwc_otg_pcd_function_ops *fops);
/** Enables an endpoint for use. This function enables an endpoint in
* the PCD. The endpoint is described by the ep_desc which has the
* same format as a USB ep descriptor. The ep_handle parameter is used to refer
* to the endpoint from other API functions and in callbacks. Normally this
* should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the
* core for that interface.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success.
*
* @param pcd The PCD
* @param ep_desc Endpoint descriptor
* @param ep_handle Handle on endpoint, that will be used to identify endpoint.
*/
extern _LONG_CALL_ int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
const uint8_t * ep_desc, void *ep_handle);
/** Disable the endpoint referenced by ep_handle.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error occurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
/** Queue a data transfer request on the endpoint referenced by ep_handle.
* After the transfer is completes, the complete callback will be called with
* the request status.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param buf The buffer for the data
* @param dma_buf The DMA buffer for the data
* @param buflen The length of the data transfer
* @param zero Specifies whether to send zero length last packet.
* @param req_handle Set this handle to any value to use to reference this
* request in the ep_dequeue function or from the complete callback
* @param atomic_alloc If driver need to perform atomic allocations
* for internal data structures.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf, dwc_dma_t dma_buf,
uint32_t buflen, int zero, void *req_handle,
int atomic_alloc);
#ifdef DWC_UTE_PER_IO
XXXX
/**
*
* @param ereq_nonport Pointer to the extended request part of the
* usb_request structure defined in usb_gadget.h file.
*/
extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf, dwc_dma_t dma_buf,
uint32_t buflen, int zero,
void *req_handle, int atomic_alloc,
void *ereq_nonport);
#endif
/** De-queue the specified data transfer that has not yet completed.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle);
/** Halt (STALL) an endpoint or clear it.
*
* Returns -DWC_E_INVALID if invalid parameters were passed.
* Returns -DWC_E_SHUTDOWN if any other error ocurred.
* Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later
* Returns 0 on success. */
extern _LONG_CALL_ int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
/** This function should be called on every hardware interrupt */
extern _LONG_CALL_ int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
/** This function returns current frame number */
extern _LONG_CALL_ int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
/**
* Start isochronous transfers on the endpoint referenced by ep_handle.
* For isochronous transfers duble buffering is used.
* After processing each of buffers comlete callback will be called with
* status for each transaction.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param buf0 The virtual address of first data buffer
* @param buf1 The virtual address of second data buffer
* @param dma0 The DMA address of first data buffer
* @param dma1 The DMA address of second data buffer
* @param sync_frame Data pattern frame number
* @param dp_frame Data size for pattern frame
* @param data_per_frame Data size for regular frame
* @param start_frame Frame number to start transfers, if -1 then start transfers ASAP.
* @param buf_proc_intrvl Interval of ISOC Buffer processing
* @param req_handle Handle of ISOC request
* @param atomic_alloc Specefies whether to perform atomic allocation for
* internal data structures.
*
* Returns -DWC_E_NO_MEMORY if there is no enough memory.
* Returns -DWC_E_INVALID if incorrect arguments are passed to the function.
* Returns -DW_E_SHUTDOWN for any other error.
* Returns 0 on success
*/
extern _LONG_CALL_ int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
uint8_t * buf0, uint8_t * buf1,
dwc_dma_t dma0, dwc_dma_t dma1,
int sync_frame, int dp_frame,
int data_per_frame, int start_frame,
int buf_proc_intrvl, void *req_handle,
int atomic_alloc);
/** Stop ISOC transfers on endpoint referenced by ep_handle.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param req_handle Handle of ISOC request
*
* Returns -DWC_E_INVALID if incorrect arguments are passed to the function
* Returns 0 on success
*/
_LONG_CALL_ int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
void *req_handle);
/** Get ISOC packet status.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param iso_req_handle Isochronoush request handle
* @param packet Number of packet
* @param status Out parameter for returning status
* @param actual Out parameter for returning actual length
* @param offset Out parameter for returning offset
*
*/
extern _LONG_CALL_ void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
void *ep_handle,
void *iso_req_handle, int packet,
int *status, int *actual,
int *offset);
/** Get ISOC packet count.
*
* @param pcd The PCD
* @param ep_handle The handle of the endpoint
* @param iso_req_handle
*/
extern _LONG_CALL_ int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
void *ep_handle,
void *iso_req_handle);
/** This function starts the SRP Protocol if no session is in progress. If
* a session is already in progress, but the device is suspended,
* remote wakeup signaling is started.
*/
extern _LONG_CALL_ int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
/** This function returns 1 if LPM support is enabled, and 0 otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
/** This function returns 1 if LPM Errata support is enabled, and 0 otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_is_besl_enabled(dwc_otg_pcd_t * pcd);
/** This function returns baseline_besl module parametr. */
extern _LONG_CALL_ int dwc_otg_pcd_get_param_baseline_besl(dwc_otg_pcd_t * pcd);
/** This function returns deep_besl module parametr. */
extern _LONG_CALL_ int dwc_otg_pcd_get_param_deep_besl(dwc_otg_pcd_t * pcd);
/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */
extern _LONG_CALL_ int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
/** Initiate SRP */
extern _LONG_CALL_ void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
/** Starts remote wakeup signaling. */
extern _LONG_CALL_ void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
/** Starts micorsecond soft disconnect. */
extern _LONG_CALL_ void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
/** This function returns whether device is dualspeed.*/
extern _LONG_CALL_ uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
/** This function returns whether device is otg. */
extern _LONG_CALL_ uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
/** These functions allow to get hnp parameters */
extern _LONG_CALL_ uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
extern _LONG_CALL_ uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
extern _LONG_CALL_ uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
/** CFI specific Interface functions */
/** Allocate a cfi buffer */
extern _LONG_CALL_ uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
dwc_dma_t * addr, size_t buflen,
int flags);
/******************************************************************************/
/** @} */
#endif /* __DWC_PCD_IF_H__ */
#endif /* DWC_HOST_ONLY */

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#ifndef _GENERIC_ERRNO_H
#define _GENERIC_ERRNO_H
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Argument list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define EDEADLK 35 /* Resource deadlock would occur */
#define ENAMETOOLONG 36 /* File name too long */
#define ENOLCK 37 /* No record locks available */
#define ENOSYS 38 /* Function not implemented */
#define ENOTEMPTY 39 /* Directory not empty */
#define ELOOP 40 /* Too many symbolic links encountered */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define ENOMSG 42 /* No message of desired type */
#define EIDRM 43 /* Identifier removed */
#define ECHRNG 44 /* Channel number out of range */
#define EL2NSYNC 45 /* Level 2 not synchronized */
#define EL3HLT 46 /* Level 3 halted */
#define EL3RST 47 /* Level 3 reset */
#define ELNRNG 48 /* Link number out of range */
#define EUNATCH 49 /* Protocol driver not attached */
#define ENOCSI 50 /* No CSI structure available */
#define EL2HLT 51 /* Level 2 halted */
#define EBADE 52 /* Invalid exchange */
#define EBADR 53 /* Invalid request descriptor */
#define EXFULL 54 /* Exchange full */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
#define EDEADLOCK EDEADLK
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EMULTIHOP 72 /* Multihop attempted */
#define EDOTDOT 73 /* RFS specific error */
#define EBADMSG 74 /* Not a data message */
#define EOVERFLOW 75 /* Value too large for defined data type */
#define ENOTUNIQ 76 /* Name not unique on network */
#define EBADFD 77 /* File descriptor in bad state */
#define EREMCHG 78 /* Remote address changed */
#define ELIBACC 79 /* Can not access a needed shared library */
#define ELIBBAD 80 /* Accessing a corrupted shared library */
#define ELIBSCN 81 /* .lib section in a.out corrupted */
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
#define EILSEQ 84 /* Illegal byte sequence */
#define ERESTART 85 /* Interrupted system call should be restarted */
#define ESTRPIPE 86 /* Streams pipe error */
#define EUSERS 87 /* Too many users */
#define ENOTSOCK 88 /* Socket operation on non-socket */
#define EDESTADDRREQ 89 /* Destination address required */
#define EMSGSIZE 90 /* Message too long */
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
#define ENOPROTOOPT 92 /* Protocol not available */
#define EPROTONOSUPPORT 93 /* Protocol not supported */
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 96 /* Protocol family not supported */
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
#define EADDRINUSE 98 /* Address already in use */
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
#define ENETDOWN 100 /* Network is down */
#define ENETUNREACH 101 /* Network is unreachable */
#define ENETRESET 102 /* Network dropped connection because of reset */
#define ECONNABORTED 103 /* Software caused connection abort */
#define ECONNRESET 104 /* Connection reset by peer */
#define ENOBUFS 105 /* No buffer space available */
#define EISCONN 106 /* Transport endpoint is already connected */
#define ENOTCONN 107 /* Transport endpoint is not connected */
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
#define ETIMEDOUT 110 /* Connection timed out */
#define ECONNREFUSED 111 /* Connection refused */
#define EHOSTDOWN 112 /* Host is down */
#define EHOSTUNREACH 113 /* No route to host */
#define EALREADY 114 /* Operation already in progress */
#define EINPROGRESS 115 /* Operation now in progress */
#define ESTALE 116 /* Stale NFS file handle */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
#define ECANCELED 125 /* Operation Canceled */
#define ENOKEY 126 /* Required key not available */
#define EKEYEXPIRED 127 /* Key has expired */
#define EKEYREVOKED 128 /* Key has been revoked */
#define EKEYREJECTED 129 /* Key was rejected by service */
/* for robust mutexes */
#define EOWNERDEAD 130 /* Owner died */
#define ENOTRECOVERABLE 131 /* State not recoverable */
#define ERFKILL 132 /* Operation not possible due to RF-kill */
#define EHWPOISON 133 /* Memory page has hardware error */
#define ENOTSUPP 524 /* Operation is not supported */
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_OTG_H_
#define _HAL_OTG_H_
#include "rtl8195a_otg.h"
#include "dwc_otg_regs.h"
#endif

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#ifndef _HCD_H_
#define _HCD_H_
struct hc_driver {
const char *description; /* "ehci-hcd" etc */
const char *product_desc; /* product/vendor string */
size_t hcd_priv_size; /* size of private data */
/* irq handler */
//irqreturn_t (*irq) (struct usb_hcd *hcd);
int flags;
#define HCD_MEMORY 0x0001 /* HC regs use memory (else I/O) */
#define HCD_LOCAL_MEM 0x0002 /* HC needs local memory */
#define HCD_SHARED 0x0004 /* Two (or more) usb_hcds share HW */
#define HCD_USB11 0x0010 /* USB 1.1 */
#define HCD_USB2 0x0020 /* USB 2.0 */
#define HCD_USB3 0x0040 /* USB 3.0 */
#define HCD_MASK 0x0070
/* called to init HCD and root hub */
int (*reset) (struct usb_hcd *hcd);
int (*start) (struct usb_hcd *hcd);
/* NOTE: these suspend/resume calls relate to the HC as
* a whole, not just the root hub; they're for PCI bus glue.
*/
/* called after suspending the hub, before entering D3 etc */
// int (*pci_suspend)(struct usb_hcd *hcd, bool do_wakeup);
/* called after entering D0 (etc), before resuming the hub */
// int (*pci_resume)(struct usb_hcd *hcd, bool hibernated);
/* cleanly make HCD stop writing memory and doing I/O */
void (*stop) (struct usb_hcd *hcd);
/* shutdown HCD */
// void (*shutdown) (struct usb_hcd *hcd);
/* return current frame number */
int (*get_frame_number) (struct usb_hcd *hcd);
/* manage i/o requests, device state */
int (*urb_enqueue)(struct usb_hcd *hcd,
struct urb *urb);//, gfp_t mem_flags);
int (*urb_dequeue)(struct usb_hcd *hcd,
struct urb *urb, int status);
/*
* (optional) these hooks allow an HCD to override the default DMA
* mapping and unmapping routines. In general, they shouldn't be
* necessary unless the host controller has special DMA requirements,
* such as alignment contraints. If these are not specified, the
* general usb_hcd_(un)?map_urb_for_dma functions will be used instead
* (and it may be a good idea to call these functions in your HCD
* implementation)
*/
#if 0
int (*map_urb_for_dma)(struct usb_hcd *hcd, struct urb *urb,
gfp_t mem_flags);
void (*unmap_urb_for_dma)(struct usb_hcd *hcd, struct urb *urb);
#endif
/* hw synch, freeing endpoint resources that urb_dequeue can't */
void (*endpoint_disable)(struct usb_hcd *hcd,
struct usb_host_endpoint *ep);
/* (optional) reset any endpoint state such as sequence number
and current window */
void (*endpoint_reset)(struct usb_hcd *hcd,
struct usb_host_endpoint *ep);
/* root hub support */
int (*hub_status_data) (struct usb_hcd *hcd, char *buf);
int (*hub_control) (struct usb_hcd *hcd,
u16 typeReq, u16 wValue, u16 wIndex,
char *buf, u16 wLength);
#if 0
int (*bus_suspend)(struct usb_hcd *);
int (*bus_resume)(struct usb_hcd *);
int (*start_port_reset)(struct usb_hcd *, unsigned port_num);
/* force handover of high-speed port to full-speed companion */
void (*relinquish_port)(struct usb_hcd *, int);
/* has a port been handed over to a companion? */
int (*port_handed_over)(struct usb_hcd *, int);
/* CLEAR_TT_BUFFER completion callback */
void (*clear_tt_buffer_complete)(struct usb_hcd *,
struct usb_host_endpoint *);
/* xHCI specific functions */
/* Called by usb_alloc_dev to alloc HC device structures */
int (*alloc_dev)(struct usb_hcd *, struct usb_device *);
/* Called by usb_disconnect to free HC device structures */
void (*free_dev)(struct usb_hcd *, struct usb_device *);
/* Change a group of bulk endpoints to support multiple stream IDs */
int (*alloc_streams)(struct usb_hcd *hcd, struct usb_device *udev,
struct usb_host_endpoint **eps, unsigned int num_eps,
unsigned int num_streams, gfp_t mem_flags);
/* Reverts a group of bulk endpoints back to not using stream IDs.
* Can fail if we run out of memory.
*/
int (*free_streams)(struct usb_hcd *hcd, struct usb_device *udev,
struct usb_host_endpoint **eps, unsigned int num_eps,
gfp_t mem_flags);
/* Bandwidth computation functions */
/* Note that add_endpoint() can only be called once per endpoint before
* check_bandwidth() or reset_bandwidth() must be called.
* drop_endpoint() can only be called once per endpoint also.
* A call to xhci_drop_endpoint() followed by a call to
* xhci_add_endpoint() will add the endpoint to the schedule with
* possibly new parameters denoted by a different endpoint descriptor
* in usb_host_endpoint. A call to xhci_add_endpoint() followed by a
* call to xhci_drop_endpoint() is not allowed.
*/
/* Allocate endpoint resources and add them to a new schedule */
int (*add_endpoint)(struct usb_hcd *, struct usb_device *,
struct usb_host_endpoint *);
/* Drop an endpoint from a new schedule */
int (*drop_endpoint)(struct usb_hcd *, struct usb_device *,
struct usb_host_endpoint *);
/* Check that a new hardware configuration, set using
* endpoint_enable and endpoint_disable, does not exceed bus
* bandwidth. This must be called before any set configuration
* or set interface requests are sent to the device.
*/
int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
/* Reset the device schedule to the last known good schedule,
* which was set from a previous successful call to
* check_bandwidth(). This reverts any add_endpoint() and
* drop_endpoint() calls since that last successful call.
* Used for when a check_bandwidth() call fails due to resource
* or bandwidth constraints.
*/
void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
/* Returns the hardware-chosen device address */
int (*address_device)(struct usb_hcd *, struct usb_device *udev);
/* Notifies the HCD after a hub descriptor is fetched.
* Will block.
*/
int (*update_hub_device)(struct usb_hcd *, struct usb_device *hdev,
struct usb_tt *tt, gfp_t mem_flags);
int (*reset_device)(struct usb_hcd *, struct usb_device *);
/* Notifies the HCD after a device is connected and its
* address is set
*/
int (*update_device)(struct usb_hcd *, struct usb_device *);
int (*set_usb2_hw_lpm)(struct usb_hcd *, struct usb_device *, int);
/* USB 3.0 Link Power Management */
/* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
int (*enable_usb3_lpm_timeout)(struct usb_hcd *,
struct usb_device *, enum usb3_link_state state);
/* The xHCI host controller can still fail the command to
* disable the LPM timeouts, so this can return an error code.
*/
int (*disable_usb3_lpm_timeout)(struct usb_hcd *,
struct usb_device *, enum usb3_link_state state);
int (*find_raw_port_number)(struct usb_hcd *, int);
#endif
};
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_OTG_H_
#define _RTL8195A_OTG_H_
#include "rtl8195a.h"
#define OTG_FAST_INIT 1
#define HAL_OTG_READ32(addr) HAL_READ32(USB_OTG_REG_BASE, (u32)addr)
#define HAL_OTG_WRITE32(addr, value) HAL_WRITE32(USB_OTG_REG_BASE, (u32)addr, value)
#define HAL_OTG_MODIFY32(addr, clrmsk, setmsk) HAL_WRITE32(USB_OTG_REG_BASE,(u32)addr,\
((HAL_READ32(USB_OTG_REG_BASE, (u32)addr) & (~clrmsk)) | setmsk))
#define DWC_READ_REG32(_reg_) HAL_OTG_READ32((u32)_reg_)
#define DWC_WRITE_REG32(_reg_, _val_) HAL_OTG_WRITE32((u32)_reg_,_val_)
#define DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_) HAL_OTG_MODIFY32((u32)_reg_,_cmsk_,_smsk_)
//This part is added for RTK power sequence
//3 SYS_ON reg
//#define REG_SYS_FUNC_EN 0x08
#define BIT_SHIFT_SOC_SYSPEON_EN 4
#define BIT_MASK_SOC_SYSPEON_EN 0x1
#define BIT_SOC_SYSPEON_EN_OTG(x)(((x) & BIT_MASK_SOC_SYSPEON_EN) << BIT_SHIFT_SOC_SYSPEON_EN)
#define BIT_INVC_SOC_SYSPEON_EN (~(BIT_MASK_SOC_SYSPEON_EN << BIT_SHIFT_SOC_SYSPEON_EN))
//3 Peri_ON reg
#define REG_OTG_PWCSEQ_OFFSET_OTG 0x40000000
#define REG_OTG_PWCSEQ_PWC_OTG 0x200
#define REG_OTG_PWCSEQ_ISO_OTG 0x204
#define REG_SOC_HCI_COM_FUNC_EN_OTG 0x214
#define REG_PESOC_HCI_CLK_CTRL0_OTG 0x240
//#define REG_PON_ISO_CTRL 0x204
#define REG_OTG_PWCSEQ_IP_OFF 0x30004 //This is in OTG IP
#define REG_OTG_PS_INTR_STS 0x30008 //This is in OTG IP
#define REG_OTG_PS_INTR_MSK 0x3000C //This is in OTG IP
//4 REG_OTG_PWCSEQ_PWC
#define BIT_SHIFT_PWC_USBD_EN 0
#define BIT_MASK_PWC_USBD_EN 0x1
#define BIT_PWC_USBD_EN(x)(((x) & BIT_MASK_PWC_USBD_EN) << BIT_SHIFT_PWC_USBD_EN)
#define BIT_INVC_PWC_USBD_EN (~(BIT_MASK_PWC_USBD_EN << BIT_SHIFT_PWC_USBD_EN))
#define BIT_SHIFT_PWC_UPLV_EN 1
#define BIT_MASK_PWC_UPLV_EN 0x1
#define BIT_PWC_UPLV_EN(x)(((x) & BIT_MASK_PWC_UPLV_EN) << BIT_SHIFT_PWC_UPLV_EN)
#define BIT_INVC_PWC_UPLV_EN (~(BIT_MASK_PWC_UPLV_EN << BIT_SHIFT_PWC_UPLV_EN))
#define BIT_SHIFT_PWC_UPHV_EN 2
#define BIT_MASK_PWC_UPHV_EN 0x1
#define BIT_PWC_UPHV_EN(x)(((x) & BIT_MASK_PWC_UPHV_EN) << BIT_SHIFT_PWC_UPHV_EN)
#define BIT_INVC_PWC_UPHV_EN (~(BIT_MASK_PWC_UPHV_EN << BIT_SHIFT_PWC_UPHV_EN))
//4 REG_OTG_PWCSEQ_ISO
#define BIT_SHIFT_ISO_USBD_EN 0
#define BIT_MASK_ISO_USBD_EN 0x1
#define BIT_ISO_USBD_EN(x)(((x) & BIT_MASK_ISO_USBD_EN) << BIT_SHIFT_ISO_USBD_EN)
#define BIT_INVC_ISO_USBD_EN (~(BIT_MASK_ISO_USBD_EN << BIT_SHIFT_ISO_USBD_EN))
#define BIT_SHIFT_ISO_USBA_EN 1
#define BIT_MASK_ISO_USBA_EN 0x1
#define BIT_ISO_USBA_EN(x)(((x) & BIT_MASK_ISO_USBA_EN) << BIT_SHIFT_ISO_USBA_EN)
#define BIT_INVC_ISO_USBA_EN (~(BIT_MASK_ISO_USBA_EN << BIT_SHIFT_ISO_USBA_EN))
//4 REG_SOC_HCI_COM_FUNC_EN
#define BIT_SHIFT_SOC_HCI_OTG_EN 4
#define BIT_MASK_SOC_HCI_OTG_EN 0x1
#define BIT_SOC_HCI_OTG_EN_OTG(x)(((x) & BIT_MASK_SOC_HCI_OTG_EN) << BIT_SHIFT_SOC_HCI_OTG_EN)
#define BIT_INVC_SOC_HCI_OTG_EN (~(BIT_MASK_SOC_HCI_OTG_EN << BIT_SHIFT_SOC_HCI_OTG_EN))
//4 REG_PESOC_HCI_CLK_CTRL0
#define BIT_SHIFT_SOC_ACTCK_OTG_EN 4
#define BIT_MASK_SOC_ACTCK_OTG_EN 0x1
#define BIT_SOC_ACTCK_OTG_EN_OTG(x)(((x) & BIT_MASK_SOC_ACTCK_OTG_EN) << BIT_SHIFT_SOC_ACTCK_OTG_EN)
#define BIT_INVC_SOC_ACTCK_OTG_EN (~(BIT_MASK_SOC_ACTCK_OTG_EN << BIT_SHIFT_SOC_ACTCK_OTG_EN))
//4 REG_OTG_PWCSEQ_OTG
#define BIT_SHIFT_USBOTG_PS_EN 0
#define BIT_MASK_USBOTG_PS_EN 0x1
#define BIT_USBOTG_PS_EN(x)(((x) & BIT_MASK_USBOTG_PS_EN) << BIT_SHIFT_USBOTG_PS_EN)
#define BIT_INVC_USBOTG_PS_EN (~(BIT_MASK_USBOTG_PS_EN << BIT_SHIFT_USBOTG_PS_EN))
#define BIT_SHIFT_USBOTG_DIS_SUSB 1
#define BIT_MASK_USBOTG_DIS_SUSB 0x1
#define BIT_USBOTG_DIS_SUSB(x)(((x) & BIT_MASK_USBOTG_DIS_SUSB) << BIT_SHIFT_USBOTG_DIS_SUSB)
#define BIT_INVC_USBOTG_DIS_SUSB (~(BIT_MASK_USBOTG_DIS_SUSB << BIT_SHIFT_USBOTG_DIS_SUSB))
#define BIT_SHIFT_USBOTG_SUSBM 4
#define BIT_MASK_USBOTG_SUSBM 0x1
#define BIT_USBOTG_SUSBM(x)(((x) & BIT_MASK_USBOTG_SUSBM) << BIT_SHIFT_USBOTG_SUSBM)
#define BIT_INVC_USBOTG_SUSBM (~(BIT_MASK_USBOTG_SUSBM << BIT_SHIFT_USBOTG_SUSBM))
#define BIT_SHIFT_UPLL_CKRDY 5
#define BIT_MASK_UPLL_CKRDY 0x1
#define BIT_UPLL_CKRDY(x)(((x) & BIT_MASK_UPLL_CKRDY) << BIT_SHIFT_UPLL_CKRDY)
#define BIT_INVC_UPLL_CKRDY (~(BIT_MASK_UPLL_CKRDY << BIT_SHIFT_UPLL_CKRDY))
#define BIT_SHIFT_USB_LS 6
#define BIT_MASK_USB_LS 0x3
#define BIT_USB_LS(x)(((x) & BIT_MASK_USB_LS) << BIT_SHIFT_USB_LS)
#define BIT_INVC_USB_LS (~(BIT_MASK_USB_LS << BIT_SHIFT_USB_LS))
#define BIT_SHIFT_USBOTG_EN 8
#define BIT_MASK_USBOTG_EN 0x1
#define BIT_USBOTG_EN(x)(((x) & BIT_MASK_USBOTG_EN) << BIT_SHIFT_USBOTG_EN)
#define BIT_INVC_USBOTG_EN (~(BIT_MASK_USBOTG_EN << BIT_SHIFT_USBOTG_EN))
#define BIT_SHIFT_USBPHY_EN 9
#define BIT_MASK_USBPHY_EN 0x1
#define BIT_USBPHY_EN(x)(((x) & BIT_MASK_USBPHY_EN) << BIT_SHIFT_USBPHY_EN)
#define BIT_INVC_USBPHY_EN (~(BIT_MASK_USBPHY_EN << BIT_SHIFT_USBPHY_EN))
#define BIT_SHIFT_USB_GT_LS_EN 10
#define BIT_MASK_USB_GT_LS_EN 0x1
#define BIT_USB_GT_LS_EN(x)(((x) & BIT_MASK_USB_GT_LS_EN) << BIT_SHIFT_USB_GT_LS_EN)
#define BIT_INVC_USB_GT_LS_EN (~(BIT_MASK_USB_GT_LS_EN << BIT_SHIFT_USB_GT_LS_EN))
#endif

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/*
* This file holds USB constants and structures that are needed for USB
* device APIs. These are used by the USB device model, which is defined
* in chapter 9 of the USB 2.0 specification. Linux has several APIs in C
* that need these:
*
* - the master/host side Linux-USB kernel driver API;
* - the "usbfs" user space API; and
* - the Linux "gadget" slave/device/peripheral side driver API.
*
* USB 2.0 adds an additional "On The Go" (OTG) mode, which lets systems
* act either as a USB master/host or as a USB slave/device. That means
* the master and slave side APIs benefit from working well together.
*
* There's also "Wireless USB", using low power short range radios for
* peripheral interconnection but otherwise building on the USB framework.
*/
#ifndef _USB_CH9_H_
#define _USB_CH9_H_
#include "basic_types.h"
//#include <linux/types.h> /* __u8 etc */
//#include "../otg/osk/sys-support.h"
/*-------------------------------------------------------------------------*/
/* CONTROL REQUEST SUPPORT */
/*
* USB directions
*
* This bit flag is used in endpoint descriptors' bEndpointAddress field.
* It's also one of three fields in control requests bRequestType.
*/
//#define USB_DIR_OUT 0 /* to device */
//#define USB_DIR_IN 0x80 /* to host */
/*
* USB types, the second of three bRequestType fields
*/
#define USB_TYPE_MASK (0x03 << 5)
#define USB_TYPE_STANDARD (0x00 << 5)
#define USB_TYPE_CLASS (0x01 << 5)
#define USB_TYPE_VENDOR (0x02 << 5)
#define USB_TYPE_RESERVED (0x03 << 5)
/*
* USB recipients, the third of three bRequestType fields
*/
#define USB_RECIP_MASK 0x1f
#define USB_RECIP_DEVICE 0x00
#define USB_RECIP_INTERFACE 0x01
#define USB_RECIP_ENDPOINT 0x02
#define USB_RECIP_OTHER 0x03
/* From Wireless USB 1.0 */
#define USB_RECIP_PORT 0x04
#define USB_RECIP_RPIPE 0x05
/*
* Standard requests, for the bRequest field of a SETUP packet.
*
* These are qualified by the bRequestType field, so that for example
* TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved
* by a GET_STATUS request.
*/
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */
#define USB_REQ_GET_ENCRYPTION 0x0E
#define USB_REQ_RPIPE_ABORT 0x0E
#define USB_REQ_SET_HANDSHAKE 0x0F
#define USB_REQ_RPIPE_RESET 0x0F
#define USB_REQ_GET_HANDSHAKE 0x10
#define USB_REQ_SET_CONNECTION 0x11
#define USB_REQ_SET_SECURITY_DATA 0x12
#define USB_REQ_GET_SECURITY_DATA 0x13
#define USB_REQ_SET_WUSB_DATA 0x14
#define USB_REQ_LOOPBACK_DATA_WRITE 0x15
#define USB_REQ_LOOPBACK_DATA_READ 0x16
#define USB_REQ_SET_INTERFACE_DS 0x17
/*
* USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and
* are read as a bit array returned by USB_REQ_GET_STATUS. (So there
* are at most sixteen features of each type.)
*/
#define USB_DEVICE_SELF_POWERED 0 /* (read only) */
#define USB_DEVICE_REMOTE_WAKEUP 1 /* dev may initiate wakeup */
#define USB_DEVICE_TEST_MODE 2 /* (wired high speed only) */
#define USB_DEVICE_BATTERY 2 /* (wireless) */
#define USB_DEVICE_B_HNP_ENABLE 3 /* (otg) dev may initiate HNP */
#define USB_DEVICE_WUSB_DEVICE 3 /* (wireless)*/
#define USB_DEVICE_A_HNP_SUPPORT 4 /* (otg) RH port supports HNP */
#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /* (otg) other RH port does */
#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
#define USB_ENDPOINT_HALT 0 /* IN/OUT will STALL */
/**
* struct usb_ctrlrequest - SETUP data for a USB device control request
* @bRequestType: matches the USB bmRequestType field
* @bRequest: matches the USB bRequest field
* @wValue: matches the USB wValue field (le16 byte order)
* @wIndex: matches the USB wIndex field (le16 byte order)
* @wLength: matches the USB wLength field (le16 byte order)
*
* This structure is used to send control requests to a USB device. It matches
* the different fields of the USB 2.0 Spec section 9.3, table 9-2. See the
* USB spec for a fuller description of the different fields, and what they are
* used for.
*
* Note that the driver for any interface can issue control requests.
* For most devices, interfaces don't coordinate with each other, so
* such requests may be made at any time.
*/
struct usb_ctrlrequest {
u8 bRequestType;
u8 bRequest;
u16 wValue;
u16 wIndex;
u16 wLength;
};
/*-------------------------------------------------------------------------*/
/*
* STANDARD DESCRIPTORS ... as returned by GET_DESCRIPTOR, or
* (rarely) accepted by SET_DESCRIPTOR.
*
* Note that all multi-byte values here are encoded in little endian
* byte order "on the wire". But when exposed through Linux-USB APIs,
* they've been converted to cpu byte order.
*/
/*
* Descriptor types ... USB 2.0 spec table 9.5
*/
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
#define USB_DT_DEVICE_QUALIFIER 0x06
#define USB_DT_OTHER_SPEED_CONFIG 0x07
#define USB_DT_INTERFACE_POWER 0x08
/* these are from a minor usb 2.0 revision (ECN) */
#define USB_DT_OTG 0x09
#define USB_DT_DEBUG 0x0a
#define USB_DT_INTERFACE_ASSOCIATION 0x0b
/* these are from the Wireless USB spec */
#define USB_DT_SECURITY 0x0c
#define USB_DT_KEY 0x0d
#define USB_DT_ENCRYPTION_TYPE 0x0e
#define USB_DT_BOS 0x0f
#define USB_DT_DEVICE_CAPABILITY 0x10
#define USB_DT_WIRELESS_ENDPOINT_COMP 0x11
#define USB_DT_WIRE_ADAPTER 0x21
#define USB_DT_RPIPE 0x22
/* conventional codes for class-specific descriptors */
#define USB_DT_CS_DEVICE 0x21
#define USB_DT_CS_CONFIG 0x22
#define USB_DT_CS_STRING 0x23
#define USB_DT_CS_INTERFACE 0x24
#define USB_DT_CS_ENDPOINT 0x25
/* All standard descriptors have these 2 fields at the beginning */
struct usb_descriptor_header {
u8 bLength;
u8 bDescriptorType;
};
/*-------------------------------------------------------------------------*/
/* USB_DT_DEVICE: Device descriptor */
struct usb_device_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 bcdUSB;
u8 bDeviceClass;
u8 bDeviceSubClass;
u8 bDeviceProtocol;
u8 bMaxPacketSize0;
u16 idVendor;
u16 idProduct;
u16 bcdDevice;
u8 iManufacturer;
u8 iProduct;
u8 iSerialNumber;
u8 bNumConfigurations;
};
#define USB_DT_DEVICE_SIZE 18
/*
* Device and/or Interface Class codes
* as found in bDeviceClass or bInterfaceClass
* and defined by www.usb.org documents
*/
#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */
#define USB_CLASS_AUDIO 1
#define USB_CLASS_COMM 2
#define USB_CLASS_HID 3
#define USB_CLASS_PHYSICAL 5
#define USB_CLASS_STILL_IMAGE 6
#define USB_CLASS_PRINTER 7
#define USB_CLASS_MASS_STORAGE 8
#define USB_CLASS_HUB 9
#define USB_CLASS_CDC_DATA 0x0a
#define USB_CLASS_CSCID 0x0b /* chip+ smart card */
#define USB_CLASS_CONTENT_SEC 0x0d /* content security */
#define USB_CLASS_VIDEO 0x0e
#define USB_CLASS_WIRELESS_CONTROLLER 0xe0
#define USB_CLASS_APP_SPEC 0xfe
#define USB_CLASS_VENDOR_SPEC 0xff
/*-------------------------------------------------------------------------*/
/* USB_DT_CONFIG: Configuration descriptor information.
*
* USB_DT_OTHER_SPEED_CONFIG is the same descriptor, except that the
* descriptor type is different. Highspeed-capable devices can look
* different depending on what speed they're currently running. Only
* devices with a USB_DT_DEVICE_QUALIFIER have any OTHER_SPEED_CONFIG
* descriptors.
*/
struct usb_config_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 wTotalLength;
u8 bNumInterfaces;
u8 bConfigurationValue;
u8 iConfiguration;
u8 bmAttributes;
u8 bMaxPower;
};
#define USB_DT_CONFIG_SIZE 9
/* from config descriptor bmAttributes */
#define USB_CONFIG_ATT_ONE (1 << 7) /* must be set */
#define USB_CONFIG_ATT_SELFPOWER (1 << 6) /* self powered */
#define USB_CONFIG_ATT_WAKEUP (1 << 5) /* can wakeup */
#define USB_CONFIG_ATT_BATTERY (1 << 4) /* battery powered */
/*-------------------------------------------------------------------------*/
/* USB_DT_STRING: String descriptor */
struct usb_string_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 wData[1]; /* UTF-16LE encoded */
};
/* note that "string" zero is special, it holds language codes that
* the device supports, not Unicode characters.
*/
/*-------------------------------------------------------------------------*/
/* USB_DT_INTERFACE: Interface descriptor */
struct usb_interface_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bInterfaceNumber;
u8 bAlternateSetting;
u8 bNumEndpoints;
u8 bInterfaceClass;
u8 bInterfaceSubClass;
u8 bInterfaceProtocol;
u8 iInterface;
};
#define USB_DT_INTERFACE_SIZE 9
/*-------------------------------------------------------------------------*/
/* Endpoint descriptor */
struct usb_endpoint_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bEndpointAddress;
u8 bmAttributes;
u16 wMaxPacketSize;
u8 bInterval;
u8 bRefresh;
u8 bSynchAddress;
unsigned char *extra; /* Extra descriptors */
int extralen;
};
#define USB_DT_ENDPOINT_SIZE 7
#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */
/*
* Endpoints
*/
#if 0
#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
#define USB_ENDPOINT_DIR_MASK 0x80
#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_MAX_ADJUSTABLE 0x80
#endif
/*-------------------------------------------------------------------------*/
/* USB_DT_DEVICE_QUALIFIER: Device Qualifier descriptor */
struct usb_qualifier_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 bcdUSB;
u8 bDeviceClass;
u8 bDeviceSubClass;
u8 bDeviceProtocol;
u8 bMaxPacketSize0;
u8 bNumConfigurations;
u8 bRESERVED;
};
/*-------------------------------------------------------------------------*/
/* USB_DT_OTG (from OTG 1.0a supplement) */
struct usb_otg_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bmAttributes; /* support for HNP, SRP, etc */
};
/* from usb_otg_descriptor.bmAttributes */
#define USB_OTG_SRP (1 << 0)
#define USB_OTG_HNP (1 << 1) /* swap host/device roles */
/*-------------------------------------------------------------------------*/
/* USB_DT_DEBUG: for special highspeed devices, replacing serial console */
struct usb_debug_descriptor {
u8 bLength;
u8 bDescriptorType;
/* bulk endpoints with 8 byte maxpacket */
u8 bDebugInEndpoint;
u8 bDebugOutEndpoint;
};
/*-------------------------------------------------------------------------*/
/* USB_DT_INTERFACE_ASSOCIATION: groups interfaces */
struct usb_interface_assoc_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bFirstInterface;
u8 bInterfaceCount;
u8 bFunctionClass;
u8 bFunctionSubClass;
u8 bFunctionProtocol;
u8 iFunction;
};
/*-------------------------------------------------------------------------*/
/* USB_DT_SECURITY: group of wireless security descriptors, including
* encryption types available for setting up a CC/association.
*/
struct usb_security_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 wTotalLength;
u8 bNumEncryptionTypes;
};
/*-------------------------------------------------------------------------*/
/* USB_DT_KEY: used with {GET,SET}_SECURITY_DATA; only public keys
* may be retrieved.
*/
struct usb_key_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 tTKID[3];
u8 bReserved;
u8 bKeyData[0];
};
/*-------------------------------------------------------------------------*/
/* USB_DT_ENCRYPTION_TYPE: bundled in DT_SECURITY groups */
struct usb_encryption_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bEncryptionType;
#define USB_ENC_TYPE_UNSECURE 0
#define USB_ENC_TYPE_WIRED 1 /* non-wireless mode */
#define USB_ENC_TYPE_CCM_1 2 /* aes128/cbc session */
#define USB_ENC_TYPE_RSA_1 3 /* rsa3072/sha1 auth */
u8 bEncryptionValue; /* use in SET_ENCRYPTION */
u8 bAuthKeyIndex;
};
/*-------------------------------------------------------------------------*/
/* USB_DT_BOS: group of wireless capabilities */
struct usb_bos_descriptor {
u8 bLength;
u8 bDescriptorType;
u16 wTotalLength;
u8 bNumDeviceCaps;
};
/*-------------------------------------------------------------------------*/
/* USB_DT_DEVICE_CAPABILITY: grouped with BOS */
struct usb_dev_cap_header {
u8 bLength;
u8 bDescriptorType;
u8 bDevCapabilityType;
};
#define USB_CAP_TYPE_WIRELESS_USB 1
struct usb_wireless_cap_descriptor { /* Ultra Wide Band */
u8 bLength;
u8 bDescriptorType;
u8 bDevCapabilityType;
u8 bmAttributes;
#define USB_WIRELESS_P2P_DRD (1 << 1)
#define USB_WIRELESS_BEACON_MASK (3 << 2)
#define USB_WIRELESS_BEACON_SELF (1 << 2)
#define USB_WIRELESS_BEACON_DIRECTED (2 << 2)
#define USB_WIRELESS_BEACON_NONE (3 << 2)
u16 wPHYRates; /* bit rates, Mbps */
#define USB_WIRELESS_PHY_53 (1 << 0) /* always set */
#define USB_WIRELESS_PHY_80 (1 << 1)
#define USB_WIRELESS_PHY_107 (1 << 2) /* always set */
#define USB_WIRELESS_PHY_160 (1 << 3)
#define USB_WIRELESS_PHY_200 (1 << 4) /* always set */
#define USB_WIRELESS_PHY_320 (1 << 5)
#define USB_WIRELESS_PHY_400 (1 << 6)
#define USB_WIRELESS_PHY_480 (1 << 7)
u8 bmTFITXPowerInfo; /* TFI power levels */
u8 bmFFITXPowerInfo; /* FFI power levels */
u16 bmBandGroup;
u8 bReserved;
};
/*-------------------------------------------------------------------------*/
/* USB_DT_WIRELESS_ENDPOINT_COMP: companion descriptor associated with
* each endpoint descriptor for a wireless device
*/
struct usb_wireless_ep_comp_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bMaxBurst;
u8 bMaxSequence;
u16 wMaxStreamDelay;
u16 wOverTheAirPacketSize;
u8 bOverTheAirInterval;
u8 bmCompAttributes;
#define USB_ENDPOINT_SWITCH_MASK 0x03 /* in bmCompAttributes */
#define USB_ENDPOINT_SWITCH_NO 0
#define USB_ENDPOINT_SWITCH_SWITCH 1
#define USB_ENDPOINT_SWITCH_SCALE 2
};
/*-------------------------------------------------------------------------*/
/* USB_REQ_SET_HANDSHAKE is a four-way handshake used between a wireless
* host and a device for connection set up, mutual authentication, and
* exchanging short lived session keys. The handshake depends on a CC.
*/
struct usb_handshake {
u8 bMessageNumber;
u8 bStatus;
u8 tTKID[3];
u8 bReserved;
u8 CDID[16];
u8 nonce[16];
u8 MIC[8];
};
/*-------------------------------------------------------------------------*/
/* USB_REQ_SET_CONNECTION modifies or revokes a connection context (CC).
* A CC may also be set up using non-wireless secure channels (including
* wired USB!), and some devices may support CCs with multiple hosts.
*/
struct usb_connection_context {
u8 CHID[16]; /* persistent host id */
u8 CDID[16]; /* device id (unique w/in host context) */
u8 CK[16]; /* connection key */
};
/*-------------------------------------------------------------------------*/
#if 1
enum usb_device_state {
/* NOTATTACHED isn't in the USB spec, and this state acts
* the same as ATTACHED ... but it's clearer this way.
*/
USB_STATE_NOTATTACHED = 0,
/* chapter 9 and authentication (wireless) device states */
USB_STATE_ATTACHED,
USB_STATE_POWERED, /* wired */
USB_STATE_UNAUTHENTICATED, /* auth */
USB_STATE_RECONNECTING, /* auth */
USB_STATE_DEFAULT, /* limited function */
USB_STATE_ADDRESS,
USB_STATE_CONFIGURED, /* most functions */
USB_STATE_SUSPENDED
/* NOTE: there are actually four different SUSPENDED
* states, returning to POWERED, DEFAULT, ADDRESS, or
* CONFIGURED respectively when SOF tokens flow again.
*/
};
#endif
#endif /* __LINUX_USB_CH9_H */

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/*
* (C) Copyright 2001
* Denis Peter, MPL AG Switzerland
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* Note: Part of this code has been derived from linux
*
*/
#ifndef _USB_DEFS_H_
#define _USB_DEFS_H_
/* USB constants */
/* Device and/or Interface Class codes */
#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */
#define USB_CLASS_AUDIO 1
#define USB_CLASS_COMM 2
#define USB_CLASS_HID 3
#define USB_CLASS_PHYSICAL 5
#define USB_CLASS_STILL_IMAGE 6
#define USB_CLASS_PRINTER 7
#define USB_CLASS_MASS_STORAGE 8
#define USB_CLASS_HUB 9
#define USB_CLASS_CDC_DATA 0x0a
#define USB_CLASS_DATA 10
#define USB_CLASS_CSCID 0x0b /* chip+ smart card */
#define USB_CLASS_CONTENT_SEC 0x0d /* content security */
#define USB_CLASS_VIDEO 0x0e
#define USB_CLASS_WIRELESS_CONTROLLER 0xe0
#define USB_CLASS_APP_SPEC 0xfe
#define USB_CLASS_VENDOR_SPEC 0xff
/* some HID sub classes */
#define USB_SUB_HID_NONE 0
#define USB_SUB_HID_BOOT 1
/* some UID Protocols */
#define USB_PROT_HID_NONE 0
#define USB_PROT_HID_KEYBOARD 1
#define USB_PROT_HID_MOUSE 2
/* Sub STORAGE Classes */
#define US_SC_RBC 1 /* Typically, flash devices */
#define US_SC_8020 2 /* CD-ROM */
#define US_SC_QIC 3 /* QIC-157 Tapes */
#define US_SC_UFI 4 /* Floppy */
#define US_SC_8070 5 /* Removable media */
#define US_SC_SCSI 6 /* Transparent */
#define US_SC_MIN US_SC_RBC
#define US_SC_MAX US_SC_SCSI
/* STORAGE Protocols */
#define US_PR_CB 1 /* Control/Bulk w/o interrupt */
#define US_PR_CBI 0 /* Control/Bulk/Interrupt */
#define US_PR_BULK 0x50 /* bulk only */
/* USB types */
#define USB_TYPE_STANDARD (0x00 << 5)
#define USB_TYPE_CLASS (0x01 << 5)
#define USB_TYPE_VENDOR (0x02 << 5)
#define USB_TYPE_RESERVED (0x03 << 5)
/* USB recipients */
#define USB_RECIP_DEVICE 0x00
#define USB_RECIP_INTERFACE 0x01
#define USB_RECIP_ENDPOINT 0x02
#define USB_RECIP_OTHER 0x03
#define USB_DT_CS_DEVICE 0x21
#define USB_DT_CS_CONFIG 0x22
#define USB_DT_CS_STRING 0x23
#define USB_DT_CS_INTERFACE 0x24
#define USB_DT_CS_ENDPOINT 0x25
/* USB directions */
#define USB_DIR_OUT 0 /* to device */
#define USB_DIR_IN 0x80 /* to host */
#if 0
enum usb_device_speed {
USB_SPEED_UNKNOWN = 0, /* enumerating */
USB_SPEED_LOW,
USB_SPEED_FULL, /* usb 1.1 */
USB_SPEED_HIGH, /* usb 2.0 */
};
#else
enum usb_device_speed {
USB_SPEED_UNKNOWN = 0, /* enumerating */
USB_SPEED_LOW, USB_SPEED_FULL, /* usb 1.1 */
USB_SPEED_HIGH, /* usb 2.0 */
USB_SPEED_VARIABLE, /* wireless (usb 2.5) */
};
#endif
/* Descriptor types */
#define USB_DT_DEVICE 0x01
#define USB_DT_CONFIG 0x02
#define USB_DT_STRING 0x03
#define USB_DT_INTERFACE 0x04
#define USB_DT_ENDPOINT 0x05
#define USB_DT_DEVICE_QUALIFIER 0x06
#define USB_DT_OTHER_SPEED_CONFIG 0x07
#define USB_DT_INTERFACE_POWER 0x08
/* these are from a minor usb 2.0 revision (ECN) */
#define USB_DT_OTG 0x09
#define USB_DT_DEBUG 0x0a
#define USB_DT_INTERFACE_ASSOCIATION 0x0b
/* these are from the Wireless USB spec */
#define USB_DT_SECURITY 0x0c
#define USB_DT_KEY 0x0d
#define USB_DT_ENCRYPTION_TYPE 0x0e
#define USB_DT_BOS 0x0f
#define USB_DT_DEVICE_CAPABILITY 0x10
#define USB_DT_WIRELESS_ENDPOINT_COMP 0x11
#define USB_DT_WIRE_ADAPTER 0x21
#define USB_DT_RPIPE 0x22
//#define USB_DT_INTERFACE_ASSOCIATION 0x0b
#define USB_DT_HID (USB_TYPE_CLASS | 0x01)
#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02)
#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
#define USB_DT_HUB (USB_TYPE_CLASS | 0x09)
/* Descriptor sizes per descriptor type */
#define USB_DT_DEVICE_SIZE 18
#define USB_DT_CONFIG_SIZE 9
#define USB_DT_INTERFACE_SIZE 9
#define USB_DT_ENDPOINT_SIZE 7
#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */
#define USB_DT_HUB_NONVAR_SIZE 7
#define USB_DT_HID_SIZE 9
/* Endpoints */
#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
#define USB_ENDPOINT_DIR_MASK 0x80
#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
#define USB_ENDPOINT_XFER_CONTROL 0
#define USB_ENDPOINT_XFER_ISOC 1
#define USB_ENDPOINT_XFER_BULK 2
#define USB_ENDPOINT_XFER_INT 3
#define USB_ENDPOINT_HALT 0 /* IN/OUT will STALL */
/* USB Packet IDs (PIDs) */
#define USB_PID_UNDEF_0 0xf0
#define USB_PID_OUT 0xe1
#define USB_PID_ACK 0xd2
#define USB_PID_DATA0 0xc3
#define USB_PID_UNDEF_4 0xb4
#define USB_PID_SOF 0xa5
#define USB_PID_UNDEF_6 0x96
#define USB_PID_UNDEF_7 0x87
#define USB_PID_UNDEF_8 0x78
#define USB_PID_IN 0x69
#define USB_PID_NAK 0x5a
#define USB_PID_DATA1 0x4b
#define USB_PID_PREAMBLE 0x3c
#define USB_PID_SETUP 0x2d
#define USB_PID_STALL 0x1e
#define USB_PID_UNDEF_F 0x0f
/* Standard requests */
#define USB_REQ_GET_STATUS 0x00
#define USB_REQ_CLEAR_FEATURE 0x01
#define USB_REQ_SET_FEATURE 0x03
#define USB_REQ_SET_ADDRESS 0x05
#define USB_REQ_GET_DESCRIPTOR 0x06
#define USB_REQ_SET_DESCRIPTOR 0x07
#define USB_REQ_GET_CONFIGURATION 0x08
#define USB_REQ_SET_CONFIGURATION 0x09
#define USB_REQ_GET_INTERFACE 0x0A
#define USB_REQ_SET_INTERFACE 0x0B
#define USB_REQ_SYNCH_FRAME 0x0C
/* HID requests */
#define USB_REQ_GET_REPORT 0x01
#define USB_REQ_GET_IDLE 0x02
#define USB_REQ_GET_PROTOCOL 0x03
#define USB_REQ_SET_REPORT 0x09
#define USB_REQ_SET_IDLE 0x0A
#define USB_REQ_SET_PROTOCOL 0x0B
/* "pipe" definitions */
#define PIPE_ISOCHRONOUS 0
#define PIPE_INTERRUPT 1
#define PIPE_CONTROL 2
#define PIPE_BULK 3
#define PIPE_DEVEP_MASK 0x0007ff00
#define USB_ISOCHRONOUS 0
#define USB_INTERRUPT 1
#define USB_CONTROL 2
#define USB_BULK 3
/* USB-status codes: */
#define USB_ST_ACTIVE 0x1 /* TD is active */
#define USB_ST_STALLED 0x2 /* TD is stalled */
#define USB_ST_BUF_ERR 0x4 /* buffer error */
#define USB_ST_BABBLE_DET 0x8 /* Babble detected */
#define USB_ST_NAK_REC 0x10 /* NAK Received*/
#define USB_ST_CRC_ERR 0x20 /* CRC/timeout Error */
#define USB_ST_BIT_ERR 0x40 /* Bitstuff error */
#define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */
/*************************************************************************
* Hub defines
*/
/*
* Hub request types
*/
#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)
#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
/*
* Hub Class feature numbers
*/
#define C_HUB_LOCAL_POWER 0
#define C_HUB_OVER_CURRENT 1
/*
* Port feature numbers
*/
#define USB_PORT_FEAT_CONNECTION 0
#define USB_PORT_FEAT_ENABLE 1
#define USB_PORT_FEAT_SUSPEND 2
#define USB_PORT_FEAT_OVER_CURRENT 3
#define USB_PORT_FEAT_RESET 4
#define USB_PORT_FEAT_POWER 8
#define USB_PORT_FEAT_LOWSPEED 9
#define USB_PORT_FEAT_HIGHSPEED 10
#define USB_PORT_FEAT_C_CONNECTION 16
#define USB_PORT_FEAT_C_ENABLE 17
#define USB_PORT_FEAT_C_SUSPEND 18
#define USB_PORT_FEAT_C_OVER_CURRENT 19
#define USB_PORT_FEAT_C_RESET 20
/* wPortStatus bits */
#define USB_PORT_STAT_CONNECTION 0x0001
#define USB_PORT_STAT_ENABLE 0x0002
#define USB_PORT_STAT_SUSPEND 0x0004
#define USB_PORT_STAT_OVERCURRENT 0x0008
#define USB_PORT_STAT_RESET 0x0010
#define USB_PORT_STAT_POWER 0x0100
#define USB_PORT_STAT_LOW_SPEED 0x0200
#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */
#define USB_PORT_STAT_SPEED \
(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
/* wPortChange bits */
#define USB_PORT_STAT_C_CONNECTION 0x0001
#define USB_PORT_STAT_C_ENABLE 0x0002
#define USB_PORT_STAT_C_SUSPEND 0x0004
#define USB_PORT_STAT_C_OVERCURRENT 0x0008
#define USB_PORT_STAT_C_RESET 0x0010
/* wHubCharacteristics (masks) */
#define HUB_CHAR_LPSM 0x0003
#define HUB_CHAR_COMPOUND 0x0004
#define HUB_CHAR_OCPM 0x0018
/*
*Hub Status & Hub Change bit masks
*/
#define HUB_STATUS_LOCAL_POWER 0x0001
#define HUB_STATUS_OVERCURRENT 0x0002
#define HUB_CHANGE_LOCAL_POWER 0x0001
#define HUB_CHANGE_OVERCURRENT 0x0002
/* Struct USB_HCD defination */
// for flags
#define HCD_FLAG_HW_ACCESSIBLE 0 /* at full power */
#define HCD_FLAG_POLL_RH 2 /* poll for rh status? */
#define HCD_FLAG_POLL_PENDING 3 /* status has changed? */
#define HCD_FLAG_WAKEUP_PENDING 4 /* root hub is resuming? */
#define HCD_FLAG_RH_RUNNING 5 /* root hub is running? */
#define HCD_FLAG_DEAD 6 /* controller has died? */
/* The flags can be tested using these macros; they are likely to
* be slightly faster than test_bit().
*/
#define HCD_HW_ACCESSIBLE(hcd) ((hcd)->flags & (1U << HCD_FLAG_HW_ACCESSIBLE))
#define HCD_POLL_RH(hcd) ((hcd)->flags & (1U << HCD_FLAG_POLL_RH))
#define HCD_POLL_PENDING(hcd) ((hcd)->flags & (1U << HCD_FLAG_POLL_PENDING))
#define HCD_WAKEUP_PENDING(hcd) ((hcd)->flags & (1U << HCD_FLAG_WAKEUP_PENDING))
#define HCD_RH_RUNNING(hcd) ((hcd)->flags & (1U << HCD_FLAG_RH_RUNNING))
#define HCD_DEAD(hcd) ((hcd)->flags & (1U << HCD_FLAG_DEAD))
// for state
#define __ACTIVE 0x01
#define __SUSPEND 0x04
#define __TRANSIENT 0x80
#define HC_STATE_HALT 0
#define HC_STATE_RUNNING (__ACTIVE)
#define HC_STATE_QUIESCING (__SUSPEND|__TRANSIENT|__ACTIVE)
#define HC_STATE_RESUMING (__SUSPEND|__TRANSIENT)
#define HC_STATE_SUSPENDED (__SUSPEND)
#define HC_IS_RUNNING(state) ((state) & __ACTIVE)
#define HC_IS_SUSPENDED(state) ((state) & __SUSPEND)
/*
* USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and
* are read as a bit array returned by USB_REQ_GET_STATUS. (So there
* are at most sixteen features of each type.) Hubs may also support a
* new USB_REQ_TEST_AND_SET_FEATURE to put ports into L1 suspend.
*/
#define USB_DEVICE_SELF_POWERED 0 /* (read only) */
#define USB_DEVICE_REMOTE_WAKEUP 1 /* dev may initiate wakeup */
#define USB_DEVICE_TEST_MODE 2 /* (wired high speed only) */
#define USB_DEVICE_BATTERY 2 /* (wireless) */
#define USB_DEVICE_B_HNP_ENABLE 3 /* (otg) dev may initiate HNP */
#define USB_DEVICE_WUSB_DEVICE 3 /* (wireless)*/
#define USB_DEVICE_A_HNP_SUPPORT 4 /* (otg) RH port supports HNP */
#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /* (otg) other RH port does */
#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */
/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
#define DeviceRequest \
((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
#define DeviceOutRequest \
((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_DEVICE)<<8)
#define InterfaceRequest \
((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE)<<8)
#define EndpointRequest \
((USB_DIR_IN|USB_TYPE_STANDARD|USB_RECIP_INTERFACE)<<8)
#define EndpointOutRequest \
((USB_DIR_OUT|USB_TYPE_STANDARD|USB_RECIP_INTERFACE)<<8)
/* class requests from the USB 2.0 hub spec, table 11-15 */
/* GetBusState and SetHubDescriptor are optional, omitted */
#define ClearHubFeature (0x2000 | USB_REQ_CLEAR_FEATURE)
#define ClearPortFeature (0x2300 | USB_REQ_CLEAR_FEATURE)
#define GetHubDescriptor (0xa000 | USB_REQ_GET_DESCRIPTOR)
#define GetHubStatus (0xa000 | USB_REQ_GET_STATUS)
#define GetPortStatus (0xa300 | USB_REQ_GET_STATUS)
#define SetHubFeature (0x2000 | USB_REQ_SET_FEATURE)
#define SetPortFeature (0x2300 | USB_REQ_SET_FEATURE)
/* from config descriptor bmAttributes */
#define USB_CONFIG_ATT_ONE (1 << 7) /* must be set */
#define USB_CONFIG_ATT_SELFPOWER (1 << 6) /* self powered */
#define USB_CONFIG_ATT_WAKEUP (1 << 5) /* can wakeup */
#define USB_CONFIG_ATT_BATTERY (1 << 4) /* battery powered */
#endif /*_USB_DEFS_H_ */

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/*
* <linux/usb_gadget.h>
*
* We call the USB code inside a Linux-based peripheral device a "gadget"
* driver, except for the hardware-specific bus glue. One USB host can
* master many USB gadgets, but the gadgets are only slaved to one host.
*
*
* (C) Copyright 2002-2004 by David Brownell
* All Rights Reserved.
*
* This software is licensed under the GNU GPL version 2.
*/
#ifndef __USB_GADGET_H
#define __USB_GADGET_H
//#include "xlinux.h"
//#ifdef __KERNEL__
#include "osdep_api.h"
#include "usb_ch9.h"
#if 1//defined(CONFIG_RTL_ULINKER)
#include "usb_ulinker.h"
#endif
#include "usb.h"
#include "dwc_list.h"
typedef unsigned int gfp_t;
//struct usb_ep;
/**
* struct usb_ep - device side representation of USB endpoint
* @name:identifier for the endpoint, such as "ep-a" or "ep9in-bulk"
* @ops: Function pointers used to access hardware-specific operations.
* @ep_list:the gadget's ep_list holds all of its endpoints
* @maxpacket:The maximum packet size used on this endpoint. The initial
* value can sometimes be reduced (hardware allowing), according to
* the endpoint descriptor used to configure the endpoint.
* @driver_data:for use by the gadget driver. all other fields are
* read-only to gadget drivers.
*
* the bus controller driver lists all the general purpose endpoints in
* gadget->ep_list. the control endpoint (gadget->ep0) is not in that list,
* and is accessed only in response to a driver setup() callback.
*/
struct usb_ep {
void *driver_data;
const char *name;
const struct usb_ep_ops *ops;
//_LIST ep_list;//ModifiedByJD
dwc_list_link_t ep_list;// by jimmy
unsigned maxpacket:16;
const struct usb_endpoint_descriptor *desc;
};
struct usb_request;
typedef void (*usb_req_complete_t)(struct usb_ep *, struct usb_request *);
/**
* struct usb_request - describes one i/o request
* @buf: Buffer used for data. Always provide this; some controllers
* only use PIO, or don't use DMA for some endpoints.
* @dma: DMA address corresponding to 'buf'. If you don't set this
* field, and the usb controller needs one, it is responsible
* for mapping and unmapping the buffer.
* @length: Length of that data
* @no_interrupt: If true, hints that no completion irq is needed.
* Helpful sometimes with deep request queues that are handled
* directly by DMA controllers.
* @zero: If true, when writing data, makes the last packet be "short"
* by adding a zero length packet as needed;
* @short_not_ok: When reading data, makes short packets be
* treated as errors (queue stops advancing till cleanup).
* @complete: Function called when request completes, so this request and
* its buffer may be re-used.
* Reads terminate with a short packet, or when the buffer fills,
* whichever comes first. When writes terminate, some data bytes
* will usually still be in flight (often in a hardware fifo).
* Errors (for reads or writes) stop the queue from advancing
* until the completion function returns, so that any transfers
* invalidated by the error may first be dequeued.
* @context: For use by the completion callback
* @list: For use by the gadget driver.
* @status: Reports completion code, zero or a negative errno.
* Normally, faults block the transfer queue from advancing until
* the completion callback returns.
* Code "-ESHUTDOWN" indicates completion caused by device disconnect,
* or when the driver disabled the endpoint.
* @actual: Reports bytes transferred to/from the buffer. For reads (OUT
* transfers) this may be less than the requested length. If the
* short_not_ok flag is set, short reads are treated as errors
* even when status otherwise indicates successful completion.
* Note that for writes (IN transfers) some data bytes may still
* reside in a device-side FIFO when the request is reported as
* complete.
*
* These are allocated/freed through the endpoint they're used with. The
* hardware's driver can add extra per-request data to the memory it returns,
* which often avoids separate memory allocations (potential failures),
* later when the request is queued.
*
* Request flags affect request handling, such as whether a zero length
* packet is written (the "zero" flag), whether a short read should be
* treated as an error (blocking request queue advance, the "short_not_ok"
* flag), or hinting that an interrupt is not required (the "no_interrupt"
* flag, for use with deep request queues).
*
* Bulk endpoints can use any size buffers, and can also be used for interrupt
* transfers. interrupt-only endpoints can be much less functional.
*/
// NOTE this is analagous to 'struct urb' on the host side,
// except that it's thinner and promotes more pre-allocation.
struct usb_request {
void *buf;
unsigned length;
dma_addr_t dma;
unsigned no_interrupt:1;
unsigned zero:1;
unsigned short_not_ok:1;
usb_req_complete_t complete;
void *context;
//_LIST list;//ModifiedByJD
dwc_list_link_t list;// by jimmy
int status;
unsigned actual;
};
/*-------------------------------------------------------------------------*/
/* endpoint-specific parts of the api to the usb controller hardware.
* unlike the urb model, (de)multiplexing layers are not required.
* (so this api could slash overhead if used on the host side...)
*
* note that device side usb controllers commonly differ in how many
* endpoints they support, as well as their capabilities.
*/
struct usb_ep_ops {
int (*enable) (struct usb_ep *ep,
const struct usb_endpoint_descriptor *desc);
int (*disable) (struct usb_ep *ep);
struct usb_request *(*alloc_request) (struct usb_ep *ep,
gfp_t gfp_flags);
void (*free_request) (struct usb_ep *ep, struct usb_request *req);
void *(*alloc_buffer) (struct usb_ep *ep, unsigned bytes,
dma_addr_t *dma, gfp_t gfp_flags);
void (*free_buffer) (struct usb_ep *ep, void *buf, dma_addr_t dma,
unsigned bytes);
// NOTE: on 2.6, drivers may also use dma_map() and
// dma_sync_single_*() to directly manage dma overhead.
int (*queue) (struct usb_ep *ep, struct usb_request *req,
gfp_t gfp_flags);
int (*dequeue) (struct usb_ep *ep, struct usb_request *req);
int (*set_halt) (struct usb_ep *ep, int value);
int (*fifo_status) (struct usb_ep *ep);
void (*fifo_flush) (struct usb_ep *ep);
};
/*-------------------------------------------------------------------------*/
/**
* usb_ep_enable - configure endpoint, making it usable
* @ep:the endpoint being configured. may not be the endpoint named "ep0".
* drivers discover endpoints through the ep_list of a usb_gadget.
* @desc:descriptor for desired behavior. caller guarantees this pointer
* remains valid until the endpoint is disabled; the data byte order
* is little-endian (usb-standard).
*
* when configurations are set, or when interface settings change, the driver
* will enable or disable the relevant endpoints. while it is enabled, an
* endpoint may be used for i/o until the driver receives a disconnect() from
* the host or until the endpoint is disabled.
*
* the ep0 implementation (which calls this routine) must ensure that the
* hardware capabilities of each endpoint match the descriptor provided
* for it. for example, an endpoint named "ep2in-bulk" would be usable
* for interrupt transfers as well as bulk, but it likely couldn't be used
* for iso transfers or for endpoint 14. some endpoints are fully
* configurable, with more generic names like "ep-a". (remember that for
* USB, "in" means "towards the USB master".)
*
* returns zero, or a negative error code.
*/
extern _LONG_CALL_
int usb_ep_enable (struct usb_ep *ep, const struct usb_endpoint_descriptor *desc);
/**
* usb_ep_disable - endpoint is no longer usable
* @ep:the endpoint being unconfigured. may not be the endpoint named "ep0".
*
* no other task may be using this endpoint when this is called.
* any pending and uncompleted requests will complete with status
* indicating disconnect (-ESHUTDOWN) before this call returns.
* gadget drivers must call usb_ep_enable() again before queueing
* requests to the endpoint.
*
* returns zero, or a negative error code.
*/
extern _LONG_CALL_
int usb_ep_disable (struct usb_ep *ep);
/**
* usb_ep_alloc_request - allocate a request object to use with this endpoint
* @ep:the endpoint to be used with with the request
* @gfp_flags:GFP_* flags to use
*
* Request objects must be allocated with this call, since they normally
* need controller-specific setup and may even need endpoint-specific
* resources such as allocation of DMA descriptors.
* Requests may be submitted with usb_ep_queue(), and receive a single
* completion callback. Free requests with usb_ep_free_request(), when
* they are no longer needed.
*
* Returns the request, or null if one could not be allocated.
*/
extern _LONG_CALL_ struct usb_request *
usb_ep_alloc_request (struct usb_ep *ep, gfp_t gfp_flags);
/**
* usb_ep_free_request - frees a request object
* @ep:the endpoint associated with the request
* @req:the request being freed
*
* Reverses the effect of usb_ep_alloc_request().
* Caller guarantees the request is not queued, and that it will
* no longer be requeued (or otherwise used).
*/
extern _LONG_CALL_ void
usb_ep_free_request (struct usb_ep *ep, struct usb_request *req);
#if 0
/**
* usb_ep_alloc_buffer - allocate an I/O buffer
* @ep:the endpoint associated with the buffer
* @len:length of the desired buffer
* @dma:pointer to the buffer's DMA address; must be valid
* @gfp_flags:GFP_* flags to use
*
* Returns a new buffer, or null if one could not be allocated.
* The buffer is suitably aligned for dma, if that endpoint uses DMA,
* and the caller won't have to care about dma-inconsistency
* or any hidden "bounce buffer" mechanism. No additional per-request
* DMA mapping will be required for such buffers.
* Free it later with usb_ep_free_buffer().
*
* You don't need to use this call to allocate I/O buffers unless you
* want to make sure drivers don't incur costs for such "bounce buffer"
* copies or per-request DMA mappings.
*/
static inline void *
usb_ep_alloc_buffer (struct usb_ep *ep, unsigned len, dma_addr_t *dma,
gfp_t gfp_flags)
{
return ep->ops->alloc_buffer (ep, len, dma, gfp_flags);
}
/**
* usb_ep_free_buffer - frees an i/o buffer
* @ep:the endpoint associated with the buffer
* @buf:CPU view address of the buffer
* @dma:the buffer's DMA address
* @len:length of the buffer
*
* reverses the effect of usb_ep_alloc_buffer().
* caller guarantees the buffer will no longer be accessed
*/
static inline void
usb_ep_free_buffer (struct usb_ep *ep, void *buf, dma_addr_t dma, unsigned len)
{
ep->ops->free_buffer (ep, buf, dma, len);
}
#endif
/**
* usb_ep_queue - queues (submits) an I/O request to an endpoint.
* @ep:the endpoint associated with the request
* @req:the request being submitted
* @gfp_flags: GFP_* flags to use in case the lower level driver couldn't
* pre-allocate all necessary memory with the request.
*
* This tells the device controller to perform the specified request through
* that endpoint (reading or writing a buffer). When the request completes,
* including being canceled by usb_ep_dequeue(), the request's completion
* routine is called to return the request to the driver. Any endpoint
* (except control endpoints like ep0) may have more than one transfer
* request queued; they complete in FIFO order. Once a gadget driver
* submits a request, that request may not be examined or modified until it
* is given back to that driver through the completion callback.
*
* Each request is turned into one or more packets. The controller driver
* never merges adjacent requests into the same packet. OUT transfers
* will sometimes use data that's already buffered in the hardware.
* Drivers can rely on the fact that the first byte of the request's buffer
* always corresponds to the first byte of some USB packet, for both
* IN and OUT transfers.
*
* Bulk endpoints can queue any amount of data; the transfer is packetized
* automatically. The last packet will be short if the request doesn't fill it
* out completely. Zero length packets (ZLPs) should be avoided in portable
* protocols since not all usb hardware can successfully handle zero length
* packets. (ZLPs may be explicitly written, and may be implicitly written if
* the request 'zero' flag is set.) Bulk endpoints may also be used
* for interrupt transfers; but the reverse is not true, and some endpoints
* won't support every interrupt transfer. (Such as 768 byte packets.)
*
* Interrupt-only endpoints are less functional than bulk endpoints, for
* example by not supporting queueing or not handling buffers that are
* larger than the endpoint's maxpacket size. They may also treat data
* toggle differently.
*
* Control endpoints ... after getting a setup() callback, the driver queues
* one response (even if it would be zero length). That enables the
* status ack, after transfering data as specified in the response. Setup
* functions may return negative error codes to generate protocol stalls.
* (Note that some USB device controllers disallow protocol stall responses
* in some cases.) When control responses are deferred (the response is
* written after the setup callback returns), then usb_ep_set_halt() may be
* used on ep0 to trigger protocol stalls.
*
* For periodic endpoints, like interrupt or isochronous ones, the usb host
* arranges to poll once per interval, and the gadget driver usually will
* have queued some data to transfer at that time.
*
* Returns zero, or a negative error code. Endpoints that are not enabled
* report errors; errors will also be
* reported when the usb peripheral is disconnected.
*/
extern _LONG_CALL_ int
usb_ep_queue (struct usb_ep *ep, struct usb_request *req, gfp_t gfp_flags);
/**
* usb_ep_dequeue - dequeues (cancels, unlinks) an I/O request from an endpoint
* @ep:the endpoint associated with the request
* @req:the request being canceled
*
* if the request is still active on the endpoint, it is dequeued and its
* completion routine is called (with status -ECONNRESET); else a negative
* error code is returned.
*
* note that some hardware can't clear out write fifos (to unlink the request
* at the head of the queue) except as part of disconnecting from usb. such
* restrictions prevent drivers from supporting configuration changes,
* even to configuration zero (a "chapter 9" requirement).
*/
extern _LONG_CALL_ int usb_ep_dequeue (struct usb_ep *ep, struct usb_request *req);
/**
* usb_ep_set_halt - sets the endpoint halt feature.
* @ep: the non-isochronous endpoint being stalled
*
* Use this to stall an endpoint, perhaps as an error report.
* Except for control endpoints,
* the endpoint stays halted (will not stream any data) until the host
* clears this feature; drivers may need to empty the endpoint's request
* queue first, to make sure no inappropriate transfers happen.
*
* Note that while an endpoint CLEAR_FEATURE will be invisible to the
* gadget driver, a SET_INTERFACE will not be. To reset endpoints for the
* current altsetting, see usb_ep_clear_halt(). When switching altsettings,
* it's simplest to use usb_ep_enable() or usb_ep_disable() for the endpoints.
*
* Returns zero, or a negative error code. On success, this call sets
* underlying hardware state that blocks data transfers.
* Attempts to halt IN endpoints will fail (returning -EAGAIN) if any
* transfer requests are still queued, or if the controller hardware
* (usually a FIFO) still holds bytes that the host hasn't collected.
*/
extern _LONG_CALL_ int usb_ep_set_halt (struct usb_ep *ep);
/**
* usb_ep_clear_halt - clears endpoint halt, and resets toggle
* @ep:the bulk or interrupt endpoint being reset
*
* Use this when responding to the standard usb "set interface" request,
* for endpoints that aren't reconfigured, after clearing any other state
* in the endpoint's i/o queue.
*
* Returns zero, or a negative error code. On success, this call clears
* the underlying hardware state reflecting endpoint halt and data toggle.
* Note that some hardware can't support this request (like pxa2xx_udc),
* and accordingly can't correctly implement interface altsettings.
*/
extern _LONG_CALL_ int usb_ep_clear_halt (struct usb_ep *ep);
#if 0
/**
* usb_ep_fifo_status - returns number of bytes in fifo, or error
* @ep: the endpoint whose fifo status is being checked.
*
* FIFO endpoints may have "unclaimed data" in them in certain cases,
* such as after aborted transfers. Hosts may not have collected all
* the IN data written by the gadget driver (and reported by a request
* completion). The gadget driver may not have collected all the data
* written OUT to it by the host. Drivers that need precise handling for
* fault reporting or recovery may need to use this call.
*
* This returns the number of such bytes in the fifo, or a negative
* errno if the endpoint doesn't use a FIFO or doesn't support such
* precise handling.
*/
static inline int
usb_ep_fifo_status (struct usb_ep *ep)
{
if (ep->ops->fifo_status)
return ep->ops->fifo_status (ep);
else
return -EOPNOTSUPP;
}
/**
* usb_ep_fifo_flush - flushes contents of a fifo
* @ep: the endpoint whose fifo is being flushed.
*
* This call may be used to flush the "unclaimed data" that may exist in
* an endpoint fifo after abnormal transaction terminations. The call
* must never be used except when endpoint is not being used for any
* protocol translation.
*/
static inline void
usb_ep_fifo_flush (struct usb_ep *ep)
{
if (ep->ops->fifo_flush)
ep->ops->fifo_flush (ep);
}
#endif
/*-------------------------------------------------------------------------*/
/**
* struct usb_gadget - represents a usb slave device
* @ops: Function pointers used to access hardware-specific operations.
* @ep0: Endpoint zero, used when reading or writing responses to
* driver setup() requests
* @ep_list: List of other endpoints supported by the device.
* @speed: Speed of current connection to USB host.
* @is_dualspeed: True if the controller supports both high and full speed
* operation. If it does, the gadget driver must also support both.
* @is_otg: True if the USB device port uses a Mini-AB jack, so that the
* gadget driver must provide a USB OTG descriptor.
* @is_a_peripheral: False unless is_otg, the "A" end of a USB cable
* is in the Mini-AB jack, and HNP has been used to switch roles
* so that the "A" device currently acts as A-Peripheral, not A-Host.
* @a_hnp_support: OTG device feature flag, indicating that the A-Host
* supports HNP at this port.
* @a_alt_hnp_support: OTG device feature flag, indicating that the A-Host
* only supports HNP on a different root port.
* @b_hnp_enable: OTG device feature flag, indicating that the A-Host
* enabled HNP support.
* @name: Identifies the controller hardware type. Used in diagnostics
* and sometimes configuration.
* @dev: Driver model state for this abstract device.
*
* Gadgets have a mostly-portable "gadget driver" implementing device
* functions, handling all usb configurations and interfaces. Gadget
* drivers talk to hardware-specific code indirectly, through ops vectors.
* That insulates the gadget driver from hardware details, and packages
* the hardware endpoints through generic i/o queues. The "usb_gadget"
* and "usb_ep" interfaces provide that insulation from the hardware.
*
* Except for the driver data, all fields in this structure are
* read-only to the gadget driver. That driver data is part of the
* "driver model" infrastructure in 2.6 (and later) kernels, and for
* earlier systems is grouped in a similar structure that's not known
* to the rest of the kernel.
*
* Values of the three OTG device feature flags are updated before the
* setup() call corresponding to USB_REQ_SET_CONFIGURATION, and before
* driver suspend() calls. They are valid only when is_otg, and when the
* device is acting as a B-Peripheral (so is_a_peripheral is false).
*/
#include"rtl8195a_otg_zero.h"
struct usb_gadget {
/* readonly to gadget driver */
const struct usb_gadget_ops *ops;
struct usb_ep *ep0;
// _LIST ep_list; /* of usb_ep */ //ModifiedByJD
dwc_list_link_t ep_list; // by jimmy
enum usb_device_speed speed;
enum usb_device_speed max_speed;
enum usb_device_state state;
unsigned is_dualspeed:1;
unsigned is_otg:1;
unsigned is_a_peripheral:1;
unsigned b_hnp_enable:1;
unsigned a_hnp_support:1;
unsigned a_alt_hnp_support:1;
const char *name;
void *driver_data;
void *device;
};
//struct usb_gadget;
/* the rest of the api to the controller hardware: device operations,
* which don't involve endpoints (or i/o).
*/
struct usb_gadget_ops {
int (*get_frame)(struct usb_gadget *);
int (*wakeup)(struct usb_gadget *);
int (*set_selfpowered) (struct usb_gadget *, int is_selfpowered);
int (*vbus_session) (struct usb_gadget *, int is_active);
int (*vbus_draw) (struct usb_gadget *, unsigned mA);
int (*pullup) (struct usb_gadget *, int is_on);
int (*ioctl)(struct usb_gadget *,
unsigned code, unsigned long param);
};
#if 0 //wei add
static inline void *
dev_get_drvdata (struct device *dev)
{
return dev->driver_data;
}
static inline void
dev_set_drvdata (struct device *dev, void *data)
{
dev->driver_data = data;
}
#endif
#if 0
static inline void set_gadget_data (struct usb_gadget *gadget, void *data)
{ dev_set_drvdata (gadget->dev, data); }
// { gadget->dev->driver_data = data; }
static inline void *get_gadget_data (struct usb_gadget *gadget)
{ return dev_get_drvdata (gadget->dev); }
// { return gadget->dev->driver_data;}
#endif
/* iterates the non-control endpoints; 'tmp' is a struct usb_ep pointer */
#define gadget_for_each_ep(tmp,gadget) \
list_for_each_entry(tmp, &(gadget)->ep_list, ep_list)
#if 0
/**
* usb_gadget_frame_number - returns the current frame number
* @gadget: controller that reports the frame number
*
* Returns the usb frame number, normally eleven bits from a SOF packet,
* or negative errno if this device doesn't support this capability.
*/
static inline int usb_gadget_frame_number (struct usb_gadget *gadget)
{
return gadget->ops->get_frame(gadget);
}
/**
* usb_gadget_wakeup - tries to wake up the host connected to this gadget
* @gadget: controller used to wake up the host
*
* Returns zero on success, else negative error code if the hardware
* doesn't support such attempts, or its support has not been enabled
* by the usb host. Drivers must return device descriptors that report
* their ability to support this, or hosts won't enable it.
*
* This may also try to use SRP to wake the host and start enumeration,
* even if OTG isn't otherwise in use. OTG devices may also start
* remote wakeup even when hosts don't explicitly enable it.
*/
static inline int usb_gadget_wakeup (struct usb_gadget *gadget)
{
if (!gadget->ops->wakeup)
return -EOPNOTSUPP;
return gadget->ops->wakeup (gadget);
}
/**
* usb_gadget_set_selfpowered - sets the device selfpowered feature.
* @gadget:the device being declared as self-powered
*
* this affects the device status reported by the hardware driver
* to reflect that it now has a local power supply.
*
* returns zero on success, else negative errno.
*/
static inline int
usb_gadget_set_selfpowered (struct usb_gadget *gadget)
{
xprintf("%s %s[%d]\n",__FILE__,__FUNCTION__,__LINE__);
if (!gadget->ops->set_selfpowered)
return -EOPNOTSUPP;
return gadget->ops->set_selfpowered (gadget, 1);
}
/**
* usb_gadget_clear_selfpowered - clear the device selfpowered feature.
* @gadget:the device being declared as bus-powered
*
* this affects the device status reported by the hardware driver.
* some hardware may not support bus-powered operation, in which
* case this feature's value can never change.
*
* returns zero on success, else negative errno.
*/
static inline int
usb_gadget_clear_selfpowered (struct usb_gadget *gadget)
{
if (!gadget->ops->set_selfpowered)
return -EOPNOTSUPP;
return gadget->ops->set_selfpowered (gadget, 0);
}
/**
* usb_gadget_vbus_connect - Notify controller that VBUS is powered
* @gadget:The device which now has VBUS power.
*
* This call is used by a driver for an external transceiver (or GPIO)
* that detects a VBUS power session starting. Common responses include
* resuming the controller, activating the D+ (or D-) pullup to let the
* host detect that a USB device is attached, and starting to draw power
* (8mA or possibly more, especially after SET_CONFIGURATION).
*
* Returns zero on success, else negative errno.
*/
static inline int
usb_gadget_vbus_connect(struct usb_gadget *gadget)
{
if (!gadget->ops->vbus_session)
return -EOPNOTSUPP;
return gadget->ops->vbus_session (gadget, 1);
}
#endif
/**
* usb_gadget_vbus_draw - constrain controller's VBUS power usage
* @gadget:The device whose VBUS usage is being described
* @mA:How much current to draw, in milliAmperes. This should be twice
* the value listed in the configuration descriptor bMaxPower field.
*
* This call is used by gadget drivers during SET_CONFIGURATION calls,
* reporting how much power the device may consume. For example, this
* could affect how quickly batteries are recharged.
*
* Returns zero on success, else negative errno.
*/
extern _LONG_CALL_ int
usb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA);
#if 0
/**
* usb_gadget_vbus_disconnect - notify controller about VBUS session end
* @gadget:the device whose VBUS supply is being described
*
* This call is used by a driver for an external transceiver (or GPIO)
* that detects a VBUS power session ending. Common responses include
* reversing everything done in usb_gadget_vbus_connect().
*
* Returns zero on success, else negative errno.
*/
static inline int
usb_gadget_vbus_disconnect(struct usb_gadget *gadget)
{
if (!gadget->ops->vbus_session)
return -EOPNOTSUPP;
return gadget->ops->vbus_session (gadget, 0);
}
/**
* usb_gadget_connect - software-controlled connect to USB host
* @gadget:the peripheral being connected
*
* Enables the D+ (or potentially D-) pullup. The host will start
* enumerating this gadget when the pullup is active and a VBUS session
* is active (the link is powered). This pullup is always enabled unless
* usb_gadget_disconnect() has been used to disable it.
*
* Returns zero on success, else negative errno.
*/
static inline int
usb_gadget_connect (struct usb_gadget *gadget)
{
if (!gadget->ops->pullup)
return -EOPNOTSUPP;
return gadget->ops->pullup (gadget, 1);
}
/**
* usb_gadget_disconnect - software-controlled disconnect from USB host
* @gadget:the peripheral being disconnected
*
* Disables the D+ (or potentially D-) pullup, which the host may see
* as a disconnect (when a VBUS session is active). Not all systems
* support software pullup controls.
*
* This routine may be used during the gadget driver bind() call to prevent
* the peripheral from ever being visible to the USB host, unless later
* usb_gadget_connect() is called. For example, user mode components may
* need to be activated before the system can talk to hosts.
*
* Returns zero on success, else negative errno.
*/
static inline int
usb_gadget_disconnect (struct usb_gadget *gadget)
{
if (!gadget->ops->pullup)
return -EOPNOTSUPP;
return gadget->ops->pullup (gadget, 0);
}
#endif
/*-------------------------------------------------------------------------*/
/**
* struct usb_gadget_driver - driver for usb 'slave' devices
* @function: String describing the gadget's function
* @speed: Highest speed the driver handles.
* @bind: Invoked when the driver is bound to a gadget, usually
* after registering the driver.
* At that point, ep0 is fully initialized, and ep_list holds
* the currently-available endpoints.
* Called in a context that permits sleeping.
* @setup: Invoked for ep0 control requests that aren't handled by
* the hardware level driver. Most calls must be handled by
* the gadget driver, including descriptor and configuration
* management. The 16 bit members of the setup data are in
* USB byte order. Called in_interrupt; this may not sleep. Driver
* queues a response to ep0, or returns negative to stall.
* @disconnect: Invoked after all transfers have been stopped,
* when the host is disconnected. May be called in_interrupt; this
* may not sleep. Some devices can't detect disconnect, so this might
* not be called except as part of controller shutdown.
* @unbind: Invoked when the driver is unbound from a gadget,
* usually from rmmod (after a disconnect is reported).
* Called in a context that permits sleeping.
* @suspend: Invoked on USB suspend. May be called in_interrupt.
* @resume: Invoked on USB resume. May be called in_interrupt.
* @driver: Driver model state for this driver.
*
* Devices are disabled till a gadget driver successfully bind()s, which
* means the driver will handle setup() requests needed to enumerate (and
* meet "chapter 9" requirements) then do some useful work.
*
* If gadget->is_otg is true, the gadget driver must provide an OTG
* descriptor during enumeration, or else fail the bind() call. In such
* cases, no USB traffic may flow until both bind() returns without
* having called usb_gadget_disconnect(), and the USB host stack has
* initialized.
*
* Drivers use hardware-specific knowledge to configure the usb hardware.
* endpoint addressing is only one of several hardware characteristics that
* are in descriptors the ep0 implementation returns from setup() calls.
*
* Except for ep0 implementation, most driver code shouldn't need change to
* run on top of different usb controllers. It'll use endpoints set up by
* that ep0 implementation.
*
* The usb controller driver handles a few standard usb requests. Those
* include set_address, and feature flags for devices, interfaces, and
* endpoints (the get_status, set_feature, and clear_feature requests).
*
* Accordingly, the driver's setup() callback must always implement all
* get_descriptor requests, returning at least a device descriptor and
* a configuration descriptor. Drivers must make sure the endpoint
* descriptors match any hardware constraints. Some hardware also constrains
* other descriptors. (The pxa250 allows only configurations 1, 2, or 3).
*
* The driver's setup() callback must also implement set_configuration,
* and should also implement set_interface, get_configuration, and
* get_interface. Setting a configuration (or interface) is where
* endpoints should be activated or (config 0) shut down.
*
* (Note that only the default control endpoint is supported. Neither
* hosts nor devices generally support control traffic except to ep0.)
*
* Most devices will ignore USB suspend/resume operations, and so will
* not provide those callbacks. However, some may need to change modes
* when the host is not longer directing those activities. For example,
* local controls (buttons, dials, etc) may need to be re-enabled since
* the (remote) host can't do that any longer; or an error state might
* be cleared, to make the device behave identically whether or not
* power is maintained.
*/
struct usb_gadget_driver {
char *function;
enum usb_device_speed max_speed;
int (*bind)(struct usb_gadget *,
struct usb_gadget_driver *);
void (*unbind)(struct usb_gadget *);
int (*setup)(struct usb_gadget *, const struct usb_ctrlrequest *);
//CommentedByJD int (*setup)(dwc_otg_pcd_t *, const struct usb_ctrlrequest *);//ModifiedByJD
void (*disconnect)(struct usb_gadget *);
void (*suspend)(struct usb_gadget *);
void (*resume)(struct usb_gadget *);
// FIXME support safe rmmod
// struct device_driver *driver;
void * driver;
};
#include "dwc_otg_pcd_if.h"
struct gadget_wrapper {
dwc_otg_pcd_t *pcd;
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
struct usb_ep ep0;
struct usb_ep in_ep[16];
struct usb_ep out_ep[16];
};
/*-------------------------------------------------------------------------*/
/* driver modules register and unregister, as usual.
* these calls must be made in a context that can sleep.
*
* these will usually be implemented directly by the hardware-dependent
* usb bus interface driver, which will only support a single driver.
*/
/**
* usb_gadget_register_driver - register a gadget driver
* @driver:the driver being registered
*
* Call this in your gadget driver's module initialization function,
* to tell the underlying usb controller driver about your driver.
* The driver's bind() function will be called to bind it to a
* gadget before this registration call returns. It's expected that
* the bind() functions will be in init sections.
* This function must be called in a context that can sleep.
*/
extern _LONG_CALL_ int usb_gadget_register_driver (struct usb_gadget_driver *driver);
/**
* usb_gadget_unregister_driver - unregister a gadget driver
* @driver:the driver being unregistered
*
* Call this in your gadget driver's module cleanup function,
* to tell the underlying usb controller that your driver is
* going away. If the controller is connected to a USB host,
* it will first disconnect(). The driver is also requested
* to unbind() and clean up any device state, before this procedure
* finally returns. It's expected that the unbind() functions
* will in in exit sections, so may not be linked in some kernels.
* This function must be called in a context that can sleep.
*/
extern _LONG_CALL_ int usb_gadget_unregister_driver (struct usb_gadget_driver *driver);
/**
* usb_free_descriptors - free descriptors returned by usb_copy_descriptors()
* @v: vector of descriptors
*/
extern _LONG_CALL_ void usb_free_descriptors(struct usb_descriptor_header **v);
/*-------------------------------------------------------------------------*/
/* utility to simplify dealing with string descriptors */
/**
* struct usb_string - wraps a C string and its USB id
* @id:the (nonzero) ID for this string
* @s:the string, in UTF-8 encoding
*
* If you're using usb_gadget_get_string(), use this to wrap a string
* together with its ID.
*/
struct usb_string {
u8 id;
const char *s;
};
/**
* struct usb_gadget_strings - a set of USB strings in a given language
* @language:identifies the strings' language (0x0409 for en-us)
* @strings:array of strings with their ids
*
* If you're using usb_gadget_get_string(), use this to wrap all the
* strings for a given language.
*/
struct usb_gadget_strings {
u16 language; /* 0x0409 for en-us */
struct usb_string *strings;
};
/**
* gadget_is_dualspeed - return true iff the hardware handles high speed
* @g: controller that might support both high and full speeds
*/
extern _LONG_CALL_ int gadget_is_dualspeed(struct usb_gadget *g);
#if 0
/**
* gadget_is_superspeed() - return true if the hardware handles superspeed
* @g: controller that might support superspeed
*/
static inline int gadget_is_superspeed(struct usb_gadget *g)
{
return g->max_speed >= USB_SPEED_SUPER;
}
#endif
/* put descriptor for string with that id into buf (buflen >= 256) */
extern _LONG_CALL_ int usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf);
/*-------------------------------------------------------------------------*/
/* utility to simplify managing config descriptors */
/* write vector of descriptors into buffer */
extern _LONG_CALL_ int usb_descriptor_fillbuf(void *, unsigned,
const struct usb_descriptor_header **);
/* build config descriptor from single descriptor vector */
extern _LONG_CALL_ int usb_gadget_config_buf(const struct usb_config_descriptor *config,
void *buf, unsigned buflen, const struct usb_descriptor_header **desc);
/*-------------------------------------------------------------------------*/
extern _LONG_CALL_ void set_gadget_data(struct usb_gadget *gadget, void *data);
extern _LONG_CALL_ void *get_gadget_data(struct usb_gadget *gadget);
/* utility wrapping a simple endpoint selection policy */
#if 1
extern _LONG_CALL_ struct usb_ep *usb_ep_autoconfig (struct usb_gadget *,
struct usb_endpoint_descriptor *);// ULINKER_DEVINIT;
extern _LONG_CALL_ void usb_ep_autoconfig_reset (struct usb_gadget *);// ULINKER_DEVINIT;
#endif
//#endif /* __KERNEL__ */
#endif /* __LINUX_USB_GADGET_H */

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#ifndef _GENERIC_ERRNO_H
#define _GENERIC_ERRNO_H
#define EPERM 1 /* Operation not permitted */
#define ENOENT 2 /* No such file or directory */
#define ESRCH 3 /* No such process */
#define EINTR 4 /* Interrupted system call */
#define EIO 5 /* I/O error */
#define ENXIO 6 /* No such device or address */
#define E2BIG 7 /* Argument list too long */
#define ENOEXEC 8 /* Exec format error */
#define EBADF 9 /* Bad file number */
#define ECHILD 10 /* No child processes */
#define EAGAIN 11 /* Try again */
#define ENOMEM 12 /* Out of memory */
#define EACCES 13 /* Permission denied */
#define EFAULT 14 /* Bad address */
#define ENOTBLK 15 /* Block device required */
#define EBUSY 16 /* Device or resource busy */
#define EEXIST 17 /* File exists */
#define EXDEV 18 /* Cross-device link */
#define ENODEV 19 /* No such device */
#define ENOTDIR 20 /* Not a directory */
#define EISDIR 21 /* Is a directory */
#define EINVAL 22 /* Invalid argument */
#define ENFILE 23 /* File table overflow */
#define EMFILE 24 /* Too many open files */
#define ENOTTY 25 /* Not a typewriter */
#define ETXTBSY 26 /* Text file busy */
#define EFBIG 27 /* File too large */
#define ENOSPC 28 /* No space left on device */
#define ESPIPE 29 /* Illegal seek */
#define EROFS 30 /* Read-only file system */
#define EMLINK 31 /* Too many links */
#define EPIPE 32 /* Broken pipe */
#define EDOM 33 /* Math argument out of domain of func */
#define ERANGE 34 /* Math result not representable */
#define EDEADLK 35 /* Resource deadlock would occur */
#define ENAMETOOLONG 36 /* File name too long */
#define ENOLCK 37 /* No record locks available */
#define ENOSYS 38 /* Function not implemented */
#define ENOTEMPTY 39 /* Directory not empty */
#define ELOOP 40 /* Too many symbolic links encountered */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define ENOMSG 42 /* No message of desired type */
#define EIDRM 43 /* Identifier removed */
#define ECHRNG 44 /* Channel number out of range */
#define EL2NSYNC 45 /* Level 2 not synchronized */
#define EL3HLT 46 /* Level 3 halted */
#define EL3RST 47 /* Level 3 reset */
#define ELNRNG 48 /* Link number out of range */
#define EUNATCH 49 /* Protocol driver not attached */
#define ENOCSI 50 /* No CSI structure available */
#define EL2HLT 51 /* Level 2 halted */
#define EBADE 52 /* Invalid exchange */
#define EBADR 53 /* Invalid request descriptor */
#define EXFULL 54 /* Exchange full */
#define ENOANO 55 /* No anode */
#define EBADRQC 56 /* Invalid request code */
#define EBADSLT 57 /* Invalid slot */
#define EDEADLOCK EDEADLK
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EMULTIHOP 72 /* Multihop attempted */
#define EDOTDOT 73 /* RFS specific error */
#define EBADMSG 74 /* Not a data message */
#define EOVERFLOW 75 /* Value too large for defined data type */
#define ENOTUNIQ 76 /* Name not unique on network */
#define EBADFD 77 /* File descriptor in bad state */
#define EREMCHG 78 /* Remote address changed */
#define ELIBACC 79 /* Can not access a needed shared library */
#define ELIBBAD 80 /* Accessing a corrupted shared library */
#define ELIBSCN 81 /* .lib section in a.out corrupted */
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
#define EILSEQ 84 /* Illegal byte sequence */
#define ERESTART 85 /* Interrupted system call should be restarted */
#define ESTRPIPE 86 /* Streams pipe error */
#define EUSERS 87 /* Too many users */
#define ENOTSOCK 88 /* Socket operation on non-socket */
#define EDESTADDRREQ 89 /* Destination address required */
#define EMSGSIZE 90 /* Message too long */
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
#define ENOPROTOOPT 92 /* Protocol not available */
#define EPROTONOSUPPORT 93 /* Protocol not supported */
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 96 /* Protocol family not supported */
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
#define EADDRINUSE 98 /* Address already in use */
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
#define ENETDOWN 100 /* Network is down */
#define ENETUNREACH 101 /* Network is unreachable */
#define ENETRESET 102 /* Network dropped connection because of reset */
#define ECONNABORTED 103 /* Software caused connection abort */
#define ECONNRESET 104 /* Connection reset by peer */
#define ENOBUFS 105 /* No buffer space available */
#define EISCONN 106 /* Transport endpoint is already connected */
#define ENOTCONN 107 /* Transport endpoint is not connected */
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
#define ETIMEDOUT 110 /* Connection timed out */
#define ECONNREFUSED 111 /* Connection refused */
#define EHOSTDOWN 112 /* Host is down */
#define EHOSTUNREACH 113 /* No route to host */
#define EALREADY 114 /* Operation already in progress */
#define EINPROGRESS 115 /* Operation now in progress */
#define ESTALE 116 /* Stale NFS file handle */
#define EUCLEAN 117 /* Structure needs cleaning */
#define ENOTNAM 118 /* Not a XENIX named type file */
#define ENAVAIL 119 /* No XENIX semaphores available */
#define EISNAM 120 /* Is a named type file */
#define EREMOTEIO 121 /* Remote I/O error */
#define EDQUOT 122 /* Quota exceeded */
#define ENOMEDIUM 123 /* No medium found */
#define EMEDIUMTYPE 124 /* Wrong medium type */
#define ECANCELED 125 /* Operation Canceled */
#define ENOKEY 126 /* Required key not available */
#define EKEYEXPIRED 127 /* Key has expired */
#define EKEYREVOKED 128 /* Key has been revoked */
#define EKEYREJECTED 129 /* Key was rejected by service */
/* for robust mutexes */
#define EOWNERDEAD 130 /* Owner died */
#define ENOTRECOVERABLE 131 /* State not recoverable */
#define ERFKILL 132 /* Operation not possible due to RF-kill */
#define EHWPOISON 133 /* Memory page has hardware error */
#define ENOTSUPP 524 /* Operation is not supported */
#endif

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#ifndef __LINUX_USB_ULINKER_H
#define __LINUX_USB_ULINKER_H
//#include "linux/autoconf.h"
//#ifndef CONFIG_RTL_ULINKER_CUSTOMIZATION
#if 1//ModifiedByJD
#define ULINKER_ETHER_VID 0x0BDA
#define ULINKER_ETHER_PID 0x8195
#define ULINKER_MANUFACTURER "Realtek Semicoonductor Corp."
#define ULINKER_WINTOOLS_GUID "1CACC490-055C-4035-A026-1DAB0BDA8196"
#define ULINKER_WINTOOLS_DISPLAY_NAME "Realtek RTL8196EU Universal Linker"
#define ULINKER_WINTOOLS_CONTACT "nicfae@realtek.com.tw"
#define ULINKER_WINTOOLS_DISPLAY_VERSION "v1.0.0.0"
#define ULINKER_WINTOOLS_HELP_LINK "http://www.realtek.com.tw"
#define ULINKER_WINTOOLS_PUBLISHER ULINKER_MANUFACTURER
#define ULINKER_WINTOOLS_TARGET_DIR ULINKER_WINTOOLS_DISPLAY_NAME
#else
#define ULINKER_ETHER_VID CONFIG_RTL_ULINKER_VID
#define ULINKER_ETHER_PID CONFIG_RTL_ULINKER_PID
#define ULINKER_STORAGE_VID CONFIG_RTL_ULINKER_VID_S
#define ULINKER_STORAGE_PID CONFIG_RTL_ULINKER_PID_S
#define ULINKER_MANUFACTURER CONFIG_RTL_ULINKER_MANUFACTURE
#define ULINKER_WINTOOLS_GUID CONFIG_RTL_ULINKER_WINTOOLS_GUID
#define ULINKER_WINTOOLS_DISPLAY_NAME CONFIG_RTL_ULINKER_WINTOOLS_DISPLAY_NAME
#define ULINKER_WINTOOLS_CONTACT CONFIG_RTL_ULINKER_WINTOOLS_CONTACT
#define ULINKER_WINTOOLS_DISPLAY_VERSION CONFIG_RTL_ULINKER_WINTOOLS_DISPLAY_VERSION
#define ULINKER_WINTOOLS_HELP_LINK CONFIG_RTL_ULINKER_WINTOOLS_HELP_LINK
#define ULINKER_WINTOOLS_PUBLISHER ULINKER_MANUFACTURER
#define ULINKER_WINTOOLS_TARGET_DIR ULINKER_WINTOOLS_DISPLAY_NAME
#endif
//------------------------------------------------
// if you don't have a specific PID for storage, don't change following define of storage mode.
//
// begin: don't change
#ifndef ULINKER_STORAGE_VID
#define ULINKER_STORAGE_VID 0x0BDA
#define ULINKER_STORAGE_PID 0x8197
#endif
#define ULINKER_STORAGE_VID_STR "USB Ether "
#define ULINKER_STORAGE_PID_DISK_STR "Driver DISC"
#define ULINKER_STORAGE_PID_CDROM_STR "Driver CDROM"
#define ULINKER_WINTOOLS_DRIVER_PATH "Driver"
// end: don't change
//------------------------------------------------
//----------------------------------------------------------------------
#if defined(CONFIG_RTL_ULINKER)
#define ULINKER_DEVINIT
#define ULINKER_DEVINITDATA
#define ULINKER_DEVINITCONST
#define ULINKER_DEVEXIT
#define ULINKER_DEVEXITDATA
#define ULINKER_DEVEXITCONST
#else
#define ULINKER_DEVINIT __devinit
#define ULINKER_DEVINITDATA __devinitdata
#define ULINKER_DEVINITCONST __devinitconst
#define ULINKER_DEVEXIT __devexit
#define ULINKER_DEVEXITDATA __devexitdata
#define ULINKER_DEVEXITCONST __devexitconst
#endif
#endif /* __LINUX_USB_ULINKER_H */

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USDK/component/soc/realtek/8195a/fwlib/ram_lib/wlan/realtek/wlan_ram_map/rom/rom_wlan_ram_map.h Normal file
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#ifndef ROM_WLAN_RAM_MAP_H
#define ROM_WLAN_RAM_MAP_H
struct _rom_wlan_ram_map {
unsigned char * (*rtw_malloc)(unsigned int sz);
void (*rtw_mfree)(unsigned char *pbuf, unsigned int sz);
};
#endif /* ROM_WLAN_RAM_MAP_H */

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USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
*/
#ifndef _HAL_8195A_H_
#define _HAL_8195A_H_
#include "platform_autoconf.h"
#include "basic_types.h"
#include "section_config.h"
#include "rtl8195a_sys_on.h"
#include "rtl8195a_peri_on.h"
#include "hal_platform.h"
#include "hal_pinmux.h"
#include "hal_api.h"
#include "hal_peri_on.h"
#include "hal_misc.h"
#include "hal_irqn.h"
#include "hal_vector_table.h"
#include "hal_diag.h"
#include "hal_spi_flash.h"
#include "rtl8195a_spi_flash.h"
#include "hal_timer.h"
#include "hal_util.h"
#include "hal_efuse.h"
#include "hal_soc_ps_monitor.h"
#include "diag.h"
#include "hal_common.h"
#include "hal_soc_ps_monitor.h"
/* ----------------------------------------------------------------------------
-- Cortex M3 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
* @{
*/
#define __CM3_REV 0x0200 /**< Core revision r0p0 */
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */
#include "core_cm3.h"
#ifdef CONFIG_TIMER_EN
#include "hal_timer.h"
#endif
#ifdef CONFIG_GDMA_EN
#include "hal_gdma.h"
#include "rtl8195a_gdma.h"
#endif
#ifdef CONFIG_GPIO_EN
#include "hal_gpio.h"
#include "rtl8195a_gpio.h"
#endif
#ifdef CONFIG_SPI_COM_EN
#include "hal_ssi.h"
#include "rtl8195a_ssi.h"
#endif
#ifdef CONFIG_UART_EN
#include "hal_uart.h"
#include "rtl8195a_uart.h"
#endif
#ifdef CONFIG_I2C_EN
#include "hal_i2c.h"
#include "rtl8195a_i2c.h"
#endif
#ifdef CONFIG_PCM_EN
#include "hal_pcm.h"
#include "rtl8195a_pcm.h"
#endif
#ifdef CONFIG_PWM_EN
#include "hal_pwm.h"
#include "rtl8195a_pwm.h"
#endif
#ifdef CONFIG_I2S_EN
#include "hal_i2s.h"
#include "rtl8195a_i2s.h"
#endif
#ifdef CONFIG_DAC_EN
#include "hal_dac.h"
#include "rtl8195a_dac.h"
#endif
#ifdef CONFIG_ADC_EN
#include "hal_adc.h"
#include "rtl8195a_adc.h"
#endif
#ifdef CONFIG_SDR_EN
#endif
#ifdef CONFIG_SPIC_EN
#endif
#ifdef CONFIG_SDIO_DEVICE_EN
#include "hal_sdio.h"
#endif
#ifdef CONFIG_NFC_EN
#include "hal_nfc.h"
#include "rtl8195a_nfc.h"
#endif
#ifdef CONFIG_WDG
#include "rtl8195a_wdt.h"
#endif
#ifdef CONFIG_USB_EN
#include "hal_usb.h"
#include "rtl8195a_usb.h"
#endif
#include "hal_log_uart.h"
#ifdef CONFIG_MII_EN
#include "hal_mii.h"
#include "rtl8195a_mii.h"
#endif
// firmware information, located at the header of Image2
#define FW_VERSION (0x0100)
#define FW_SUBVERSION (0x0001)
#define FW_CHIP_ID (0x8195)
#define FW_CHIP_VER (0x01)
#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO
#define FW_INFO_RSV1 (0x00) // the firmware information reserved
#define FW_INFO_RSV2 (0x00) // the firmware information reserved
#define FW_INFO_RSV3 (0x00) // the firmware information reserved
#define FW_INFO_RSV4 (0x00) // the firmware information reserved
#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1
#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data
// Flash Map for Calibration data
#define FLASH_CAL_DATA_BASE 0xA000
#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset)
#define FLASH_CAL_DATA_SIZE 0x1000
#define FLASH_SECTOR_SIZE 0x1000
// SPIC Calibration Data
#define FLASH_SPIC_PARA_OFFSET 0x80
#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET)
// SDRC Calibration Data
#define FLASH_SDRC_PARA_OFFSET 0x180
#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET)
// ADC Calibration Data
#define FLASH_ADC_PARA_OFFSET 0x200
#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET)
#define IMG_SIGN_RUN "81958711"
#define IMG_SIGN_SWP "01958711"
#define IMG_SIGN1_RUN 0x35393138 // "8195"
#define IMG_SIGN1_SWP 0x35393130 // "0195"
#define IMG_SIGN2_RUN 0x31313738 // "8711"
#define IMG_SIGN2_SWP IMG_SIGN2_RUN // "8711"
#define IMG2_SIGN_TXT "RTKWin"
#define IMG2_SIGN_DW1_TXT 0x574b5452 // "RTKW"
#define IMG2_SIGN_SW2_TXT 0x6e69 // "in"
typedef struct _RAM_FUNCTION_START_TABLE_ {
VOID (*RamStartFun) (VOID); // Run for Init console, Run if ( v40000210 & 0x4000000 )
VOID (*RamWakeupFun) (VOID); // Run if ( v40000210 & 0x20000000 )
VOID (*RamPatchFun0) (VOID); // Run if ( v40000210 & 0x10000000 )
VOID (*RamPatchFun1) (VOID); // Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
VOID (*RamPatchFun2) (VOID); // Run for Init console, if ( v40000210 & 0x4000000 )
}RAM_FUNCTION_START_TABLE, *PRAM_FUNCTION_START_TABLE;
// START_RAM_FUN_SECTION RAM_FUNCTION_START_TABLE __ram_start_table_start__ =
// {RamStartFun + 1, RamWakeupFun + 1, RamPatchFun0 + 1, RamPatchFun1 + 1, RamPatchFun2 + 1 };
#define IMG1_VALID_PATTEN_INIT() { 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff }
// IMAGE1_VALID_PATTEN_SECTION uint8 RAM_IMG1_VALID_PATTEN[8] = IMG1_VALID_PATTEN_INIT();
typedef struct _RAM_START_FUNCTION_ {
VOID (*RamStartFun) (VOID);
}RAM_START_FUNCTION, *PRAM_START_FUNCTION;
// IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 = { InfraStart + 1 };
typedef struct __RAM_IMG2_VALID_PATTEN__ {
char rtkwin[7];
u8 x[13];
} _RAM_IMG2_VALID_PATTEN, *_PRAM_IMG2_VALID_PATTEN;
// IMAGE2_VALID_PATTEN_SECTION _RAM_IMG2_VALID_PATTEN RAM_IMG2_VALID_PATTEN = RAM_IMG2_VALID_PATTEN_INIT();
#define RAM_IMG2_VALID_PATTEN_INIT() { \
{ IMG2_SIGN_TXT }, { 0xff, \
(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff), \
(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff), \
(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff), \
(FW_CHIP_VER), (FW_BUS_TYPE), \
(FW_INFO_RSV1), (FW_INFO_RSV2), (FW_INFO_RSV3), (FW_INFO_RSV4)}}
#endif //_HAL_8195A_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_ADC_H_
#define _RTL8195A_ADC_H_
//================ Register Bit Field ==========================
//2 REG_ADC_FIFO_READ
#define BIT_SHIFT_ADC_FIFO_RO 0
#define BIT_MASK_ADC_FIFO_RO 0xffffffffL
#define BIT_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
#define BIT_CTRL_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
#define BIT_GET_ADC_FIFO_RO(x) (((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO)
//2 REG_ADC_CONTROL
#define BIT_SHIFT_ADC_DBG_SEL 24
#define BIT_MASK_ADC_DBG_SEL 0x7
#define BIT_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
#define BIT_CTRL_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
#define BIT_GET_ADC_DBG_SEL(x) (((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL)
#define BIT_SHIFT_ADC_THRESHOLD 16
#define BIT_MASK_ADC_THRESHOLD 0x3f
#define BIT_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
#define BIT_CTRL_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
#define BIT_GET_ADC_THRESHOLD(x) (((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD)
#define BIT_SHIFT_ADC_BURST_SIZE 8
#define BIT_MASK_ADC_BURST_SIZE 0x1f
#define BIT_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
#define BIT_CTRL_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
#define BIT_GET_ADC_BURST_SIZE(x) (((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE)
#define BIT_ADC_ENDIAN BIT(3)
#define BIT_SHIFT_ADC_ENDIAN 3
#define BIT_MASK_ADC_ENDIAN 0x1
#define BIT_CTRL_ADC_ENDIAN(x) (((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN)
#define BIT_ADC_OVERWRITE BIT(2)
#define BIT_SHIFT_ADC_OVERWRITE 2
#define BIT_MASK_ADC_OVERWRITE 0x1
#define BIT_CTRL_ADC_OVERWRITE(x) (((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE)
#define BIT_ADC_ONESHOT BIT(1)
#define BIT_SHIFT_ADC_ONESHOT 1
#define BIT_MASK_ADC_ONESHOT 0x1
#define BIT_CTRL_ADC_ONESHOT(x) (((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT)
#define BIT_ADC_COMP_ONLY BIT(0)
#define BIT_SHIFT_ADC_COMP_ONLY 0
#define BIT_MASK_ADC_COMP_ONLY 0x1
#define BIT_CTRL_ADC_COMP_ONLY(x) (((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY)
//2 REG_ADC_INTR_EN
#define BIT_ADC_AWAKE_CPU_EN BIT(7)
#define BIT_SHIFT_ADC_AWAKE_CPU_EN 7
#define BIT_MASK_ADC_AWAKE_CPU_EN 0x1
#define BIT_CTRL_ADC_AWAKE_CPU_EN(x) (((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN)
#define BIT_ADC_FIFO_RD_ERROR_EN BIT(6)
#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN 6
#define BIT_MASK_ADC_FIFO_RD_ERROR_EN 0x1
#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN)
#define BIT_ADC_FIFO_RD_REQ_EN BIT(5)
#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN 5
#define BIT_MASK_ADC_FIFO_RD_REQ_EN 0x1
#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN)
#define BIT_ADC_FIFO_FULL_EN BIT(4)
#define BIT_SHIFT_ADC_FIFO_FULL_EN 4
#define BIT_MASK_ADC_FIFO_FULL_EN 0x1
#define BIT_CTRL_ADC_FIFO_FULL_EN(x) (((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN)
#define BIT_ADC_COMP_3_EN BIT(3)
#define BIT_SHIFT_ADC_COMP_3_EN 3
#define BIT_MASK_ADC_COMP_3_EN 0x1
#define BIT_CTRL_ADC_COMP_3_EN(x) (((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN)
#define BIT_ADC_COMP_2_EN BIT(2)
#define BIT_SHIFT_ADC_COMP_2_EN 2
#define BIT_MASK_ADC_COMP_2_EN 0x1
#define BIT_CTRL_ADC_COMP_2_EN(x) (((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN)
#define BIT_ADC_COMP_1_EN BIT(1)
#define BIT_SHIFT_ADC_COMP_1_EN 1
#define BIT_MASK_ADC_COMP_1_EN 0x1
#define BIT_CTRL_ADC_COMP_1_EN(x) (((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN)
#define BIT_ADC_COMP_0_EN BIT(0)
#define BIT_SHIFT_ADC_COMP_0_EN 0
#define BIT_MASK_ADC_COMP_0_EN 0x1
#define BIT_CTRL_ADC_COMP_0_EN(x) (((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN)
//2 REG_ADC_INTR_STS
#define BIT_ADC_FIFO_THRESHOLD BIT(7)
#define BIT_SHIFT_ADC_FIFO_THRESHOLD 7
#define BIT_MASK_ADC_FIFO_THRESHOLD 0x1
#define BIT_CTRL_ADC_FIFO_THRESHOLD(x) (((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD)
#define BIT_ADC_FIFO_RD_ERROR_ST BIT(6)
#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST 6
#define BIT_MASK_ADC_FIFO_RD_ERROR_ST 0x1
#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST)
#define BIT_ADC_FIFO_RD_REQ_ST BIT(5)
#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST 5
#define BIT_MASK_ADC_FIFO_RD_REQ_ST 0x1
#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST)
#define BIT_ADC_FIFO_FULL_ST BIT(4)
#define BIT_SHIFT_ADC_FIFO_FULL_ST 4
#define BIT_MASK_ADC_FIFO_FULL_ST 0x1
#define BIT_CTRL_ADC_FIFO_FULL_ST(x) (((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST)
#define BIT_ADC_COMP_3_ST BIT(3)
#define BIT_SHIFT_ADC_COMP_3_ST 3
#define BIT_MASK_ADC_COMP_3_ST 0x1
#define BIT_CTRL_ADC_COMP_3_ST(x) (((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST)
#define BIT_ADC_COMP_2_ST BIT(2)
#define BIT_SHIFT_ADC_COMP_2_ST 2
#define BIT_MASK_ADC_COMP_2_ST 0x1
#define BIT_CTRL_ADC_COMP_2_ST(x) (((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST)
#define BIT_ADC_COMP_1_ST BIT(1)
#define BIT_SHIFT_ADC_COMP_1_ST 1
#define BIT_MASK_ADC_COMP_1_ST 0x1
#define BIT_CTRL_ADC_COMP_1_ST(x) (((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST)
#define BIT_ADC_COMP_0_ST BIT(0)
#define BIT_SHIFT_ADC_COMP_0_ST 0
#define BIT_MASK_ADC_COMP_0_ST 0x1
#define BIT_CTRL_ADC_COMP_0_ST(x) (((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST)
//2 REG_ADC_COMP_VALUE_L
#define BIT_SHIFT_ADC_COMP_TH_1 16
#define BIT_MASK_ADC_COMP_TH_1 0xffff
#define BIT_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
#define BIT_CTRL_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
#define BIT_GET_ADC_COMP_TH_1(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1)
#define BIT_SHIFT_ADC_COMP_TH_0 0
#define BIT_MASK_ADC_COMP_TH_0 0xffff
#define BIT_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
#define BIT_CTRL_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
#define BIT_GET_ADC_COMP_TH_0(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0)
//2 REG_ADC_COMP_VALUE_H
#define BIT_SHIFT_ADC_COMP_TH_3 16
#define BIT_MASK_ADC_COMP_TH_3 0xffff
#define BIT_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
#define BIT_CTRL_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
#define BIT_GET_ADC_COMP_TH_3(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3)
#define BIT_SHIFT_ADC_COMP_TH_2 0
#define BIT_MASK_ADC_COMP_TH_2 0xffff
#define BIT_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
#define BIT_CTRL_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
#define BIT_GET_ADC_COMP_TH_2(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2)
//2 REG_ADC_COMP_SET
#define BIT_SHIFT_ADC_GREATER_THAN 0
#define BIT_MASK_ADC_GREATER_THAN 0xf
#define BIT_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
#define BIT_CTRL_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
#define BIT_GET_ADC_GREATER_THAN(x) (((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN)
//2 REG_ADC_POWER
#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16
#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff
#define BIT_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
#define BIT_CTRL_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
#define BIT_GET_ADC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR)
#define BIT_ADC_FIFO_ON_ST BIT(11)
#define BIT_SHIFT_ADC_FIFO_ON_ST 11
#define BIT_MASK_ADC_FIFO_ON_ST 0x1
#define BIT_CTRL_ADC_FIFO_ON_ST(x) (((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST)
#define BIT_ADC_ISO_ON_ST BIT(10)
#define BIT_SHIFT_ADC_ISO_ON_ST 10
#define BIT_MASK_ADC_ISO_ON_ST 0x1
#define BIT_CTRL_ADC_ISO_ON_ST(x) (((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST)
#define BIT_ADC_PWR33_ON_ST BIT(9)
#define BIT_SHIFT_ADC_PWR33_ON_ST 9
#define BIT_MASK_ADC_PWR33_ON_ST 0x1
#define BIT_CTRL_ADC_PWR33_ON_ST(x) (((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST)
#define BIT_ADC_PWR12_ON_ST BIT(8)
#define BIT_SHIFT_ADC_PWR12_ON_ST 8
#define BIT_MASK_ADC_PWR12_ON_ST 0x1
#define BIT_CTRL_ADC_PWR12_ON_ST(x) (((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST)
#define BIT_ADC_ISO_MANUAL BIT(3)
#define BIT_SHIFT_ADC_ISO_MANUAL 3
#define BIT_MASK_ADC_ISO_MANUAL 0x1
#define BIT_CTRL_ADC_ISO_MANUAL(x) (((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL)
#define BIT_ADC_PWR33_MANUAL BIT(2)
#define BIT_SHIFT_ADC_PWR33_MANUAL 2
#define BIT_MASK_ADC_PWR33_MANUAL 0x1
#define BIT_CTRL_ADC_PWR33_MANUAL(x) (((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL)
#define BIT_ADC_PWR12_MANUAL BIT(1)
#define BIT_SHIFT_ADC_PWR12_MANUAL 1
#define BIT_MASK_ADC_PWR12_MANUAL 0x1
#define BIT_CTRL_ADC_PWR12_MANUAL(x) (((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL)
#define BIT_ADC_PWR_AUTO BIT(0)
#define BIT_SHIFT_ADC_PWR_AUTO 0
#define BIT_MASK_ADC_PWR_AUTO 0x1
#define BIT_CTRL_ADC_PWR_AUTO(x) (((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO)
//2 REG_ADC_ANAPAR_AD0
#define BIT_SHIFT_ADC_ANAPAR_AD0 2
#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff
#define BIT_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
#define BIT_CTRL_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
#define BIT_GET_ADC_ANAPAR_AD0(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0)
#define BIT_ADC_AUDIO_EN BIT(1)
#define BIT_SHIFT_ADC_AUDIO_EN 1
#define BIT_MASK_ADC_AUDIO_EN 0x1
#define BIT_CTRL_ADC_AUDIO_EN(x) (((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN)
#define BIT_ADC_EN_MANUAL BIT(0)
#define BIT_SHIFT_ADC_EN_MANUAL 0
#define BIT_MASK_ADC_EN_MANUAL 0x1
#define BIT_CTRL_ADC_EN_MANUAL(x) (((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL)
//2 REG_ADC_ANAPAR_AD1
#define BIT_SHIFT_ADC_ANAPAR_AD1 0
#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL
#define BIT_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
#define BIT_CTRL_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
#define BIT_GET_ADC_ANAPAR_AD1(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1)
//2 REG_ADC_ANAPAR_AD2
#define BIT_SHIFT_ADC_ANAPAR_AD2 0
#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL
#define BIT_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
#define BIT_CTRL_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
#define BIT_GET_ADC_ANAPAR_AD2(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2)
//2 REG_ADC_ANAPAR_AD3
#define BIT_SHIFT_ADC_ANAPAR_AD3 0
#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL
#define BIT_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
#define BIT_CTRL_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
#define BIT_GET_ADC_ANAPAR_AD3(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3)
//2 REG_ADC_ANAPAR_AD4
#define BIT_SHIFT_ADC_ANAPAR_AD4 0
#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL
#define BIT_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
#define BIT_CTRL_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
#define BIT_GET_ADC_ANAPAR_AD4(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4)
//2 REG_ADC_ANAPAR_AD5
#define BIT_SHIFT_ADC_ANAPAR_AD5 0
#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL
#define BIT_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
#define BIT_CTRL_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
#define BIT_GET_ADC_ANAPAR_AD5(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5)
//2 REG_ADC_CALI_DATA
#define BIT_SHIFT_ADC_CALI_DATA_6 16
#define BIT_MASK_ADC_CALI_DATA_6 0xffff
#define BIT_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
#define BIT_CTRL_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
#define BIT_GET_ADC_CALI_DATA_6(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6)
#define BIT_SHIFT_ADC_CALI_DATA_0 0
#define BIT_MASK_ADC_CALI_DATA_0 0xffff
#define BIT_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
#define BIT_CTRL_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
#define BIT_GET_ADC_CALI_DATA_0(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0)
//================ Register Reg Field =========================
#define REG_ADC_FIFO_READ 0x0000
#define REG_ADC_CONTROL 0x0004
#define REG_ADC_INTR_EN 0x0008
#define REG_ADC_INTR_STS 0x000C
#define REG_ADC_COMP_VALUE_L 0x0010
#define REG_ADC_COMP_VALUE_H 0x0014
#define REG_ADC_COMP_SET 0x0018
#define REG_ADC_POWER 0x001C
#define REG_ADC_ANAPAR_AD0 0x0020
#define REG_ADC_ANAPAR_AD1 0x0024
#define REG_ADC_ANAPAR_AD2 0x0028
#define REG_ADC_ANAPAR_AD3 0x002C
#define REG_ADC_ANAPAR_AD4 0x0030
#define REG_ADC_ANAPAR_AD5 0x0034
#define REG_ADC_CALI_DATA 0x0038
//================ ADC HAL related enumeration ==================
//================ ADC Function Prototypes =====================
#define HAL_ADC_WRITE32(addr, value) HAL_WRITE32(ADC_REG_BASE,addr,value)
#define HAL_ADC_READ32(addr) HAL_READ32(ADC_REG_BASE,addr)
RTK_STATUS HalADCInit8195a(IN VOID *Data);
RTK_STATUS HalADCDeInit8195a(IN VOID *Data);
RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data);
RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data);
u32 HalADCReceiveRtl8195a(IN VOID *Data);
u32 HalADCReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
#endif

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#ifndef _RTL8195A_DAC_H_
#define _RTL8195A_DAC_H_
//================ Register Bit Field ==========================
//2 REG_DAC0_FIFO_WR
#define BIT_SHIFT_DAC0_FIFO_WO 0
#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL
#define BIT_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
#define BIT_CTRL_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
#define BIT_GET_DAC0_FIFO_WO(x) (((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO)
//2 REG_DAC_CTRL
#define BIT_SHIFT_DAC_DELTA_SIGMA 25
#define BIT_MASK_DAC_DELTA_SIGMA 0x7
#define BIT_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
#define BIT_CTRL_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
#define BIT_GET_DAC_DELTA_SIGMA(x) (((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA)
#define BIT_DAC_BYPASS_DSC BIT(24)
#define BIT_SHIFT_DAC_BYPASS_DSC 24
#define BIT_MASK_DAC_BYPASS_DSC 0x1
#define BIT_CTRL_DAC_BYPASS_DSC(x) (((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC)
#define BIT_SHIFT_DAC_DSC_DBG_SEL 19
#define BIT_MASK_DAC_DSC_DBG_SEL 0x3
#define BIT_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
#define BIT_CTRL_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
#define BIT_GET_DAC_DSC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL)
#define BIT_SHIFT_DAC_DBG_SEL 16
#define BIT_MASK_DAC_DBG_SEL 0x7
#define BIT_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
#define BIT_CTRL_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
#define BIT_GET_DAC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL)
#define BIT_SHIFT_DAC_BURST_SIZE 8
#define BIT_MASK_DAC_BURST_SIZE 0xf
#define BIT_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
#define BIT_CTRL_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
#define BIT_GET_DAC_BURST_SIZE(x) (((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE)
#define BIT_DAC_FILTER_SETTLE BIT(4)
#define BIT_SHIFT_DAC_FILTER_SETTLE 4
#define BIT_MASK_DAC_FILTER_SETTLE 0x1
#define BIT_CTRL_DAC_FILTER_SETTLE(x) (((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE)
#define BIT_DAC_OV_OPTION BIT(3)
#define BIT_SHIFT_DAC_OV_OPTION 3
#define BIT_MASK_DAC_OV_OPTION 0x1
#define BIT_CTRL_DAC_OV_OPTION(x) (((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION)
#define BIT_DAC_ENDIAN BIT(2)
#define BIT_SHIFT_DAC_ENDIAN 2
#define BIT_MASK_DAC_ENDIAN 0x1
#define BIT_CTRL_DAC_ENDIAN(x) (((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN)
#define BIT_DAC_SPEED BIT(1)
#define BIT_SHIFT_DAC_SPEED 1
#define BIT_MASK_DAC_SPEED 0x1
#define BIT_CTRL_DAC_SPEED(x) (((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED)
#define BIT_DAC_FIFO_EN BIT(0)
#define BIT_SHIFT_DAC_FIFO_EN 0
#define BIT_MASK_DAC_FIFO_EN 0x1
#define BIT_CTRL_DAC_FIFO_EN(x) (((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN)
//2 REG_DAC_INTR_CTRL
#define BIT_DAC_DSC_OVERFLOW1_EN BIT(6)
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN 6
#define BIT_MASK_DAC_DSC_OVERFLOW1_EN 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN)
#define BIT_DAC_DSC_OVERFLOW0_EN BIT(5)
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN 5
#define BIT_MASK_DAC_DSC_OVERFLOW0_EN 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN)
#define BIT_DAC__WRITE_ERROR_EN BIT(4)
#define BIT_SHIFT_DAC__WRITE_ERROR_EN 4
#define BIT_MASK_DAC__WRITE_ERROR_EN 0x1
#define BIT_CTRL_DAC__WRITE_ERROR_EN(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN)
#define BIT_DAC_FIFO_STOP_EN BIT(3)
#define BIT_SHIFT_DAC_FIFO_STOP_EN 3
#define BIT_MASK_DAC_FIFO_STOP_EN 0x1
#define BIT_CTRL_DAC_FIFO_STOP_EN(x) (((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN)
#define BIT_DAC_FIFO_OVERFLOW_EN BIT(2)
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN 2
#define BIT_MASK_DAC_FIFO_OVERFLOW_EN 0x1
#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN)
#define BIT_DAC_FIFO_WR_REQ_EN BIT(1)
#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN 1
#define BIT_MASK_DAC_FIFO_WR_REQ_EN 0x1
#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN)
#define BIT_DAC_FIFO_FULL_EN BIT(0)
#define BIT_SHIFT_DAC_FIFO_FULL_EN 0
#define BIT_MASK_DAC_FIFO_FULL_EN 0x1
#define BIT_CTRL_DAC_FIFO_FULL_EN(x) (((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN)
//2 REG_DAC_INTR_STS
#define BIT_DAC_DSC_OVERFLOW1_ST BIT(6)
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST 6
#define BIT_MASK_DAC_DSC_OVERFLOW1_ST 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST)
#define BIT_DAC_DSC_OVERFLOW0_ST BIT(5)
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST 5
#define BIT_MASK_DAC_DSC_OVERFLOW0_ST 0x1
#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST)
#define BIT_DAC__WRITE_ERROR_ST BIT(4)
#define BIT_SHIFT_DAC__WRITE_ERROR_ST 4
#define BIT_MASK_DAC__WRITE_ERROR_ST 0x1
#define BIT_CTRL_DAC__WRITE_ERROR_ST(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST)
#define BIT_DAC_FIFO_STOP_ST BIT(3)
#define BIT_SHIFT_DAC_FIFO_STOP_ST 3
#define BIT_MASK_DAC_FIFO_STOP_ST 0x1
#define BIT_CTRL_DAC_FIFO_STOP_ST(x) (((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST)
#define BIT_DAC_FIFO_OVERFLOW_ST BIT(2)
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST 2
#define BIT_MASK_DAC_FIFO_OVERFLOW_ST 0x1
#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST)
#define BIT_DAC_FIFO_WR_REQ_ST BIT(1)
#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST 1
#define BIT_MASK_DAC_FIFO_WR_REQ_ST 0x1
#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST)
#define BIT_DAC_FIFO_FULL_ST BIT(0)
#define BIT_SHIFT_DAC_FIFO_FULL_ST 0
#define BIT_MASK_DAC_FIFO_FULL_ST 0x1
#define BIT_CTRL_DAC_FIFO_FULL_ST(x) (((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST)
//2 REG_DAC_PWR_CTRL
#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16
#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff
#define BIT_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
#define BIT_CTRL_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
#define BIT_GET_DAC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR)
#define BIT_ST_DAC_FIFO_ON BIT(11)
#define BIT_SHIFT_ST_DAC_FIFO_ON 11
#define BIT_MASK_ST_DAC_FIFO_ON 0x1
#define BIT_CTRL_ST_DAC_FIFO_ON(x) (((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON)
#define BIT_ST_DAC_ISO_ON BIT(10)
#define BIT_SHIFT_ST_DAC_ISO_ON 10
#define BIT_MASK_ST_DAC_ISO_ON 0x1
#define BIT_CTRL_ST_DAC_ISO_ON(x) (((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON)
#define BIT_ST_DAC_PWR33_ON BIT(9)
#define BIT_SHIFT_ST_DAC_PWR33_ON 9
#define BIT_MASK_ST_DAC_PWR33_ON 0x1
#define BIT_CTRL_ST_DAC_PWR33_ON(x) (((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON)
#define BIT_ST_DAC_PWR12_ON BIT(8)
#define BIT_SHIFT_ST_DAC_PWR12_ON 8
#define BIT_MASK_ST_DAC_PWR12_ON 0x1
#define BIT_CTRL_ST_DAC_PWR12_ON(x) (((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON)
#define BIT_DAC_ISO_MANU BIT(3)
#define BIT_SHIFT_DAC_ISO_MANU 3
#define BIT_MASK_DAC_ISO_MANU 0x1
#define BIT_CTRL_DAC_ISO_MANU(x) (((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU)
#define BIT_DAC_PWR33_MANU BIT(2)
#define BIT_SHIFT_DAC_PWR33_MANU 2
#define BIT_MASK_DAC_PWR33_MANU 0x1
#define BIT_CTRL_DAC_PWR33_MANU(x) (((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU)
#define BIT_DAC_PWR12_MANU BIT(1)
#define BIT_SHIFT_DAC_PWR12_MANU 1
#define BIT_MASK_DAC_PWR12_MANU 0x1
#define BIT_CTRL_DAC_PWR12_MANU(x) (((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU)
#define BIT_DAC_PWR_AUTO BIT(0)
#define BIT_SHIFT_DAC_PWR_AUTO 0
#define BIT_MASK_DAC_PWR_AUTO 0x1
#define BIT_CTRL_DAC_PWR_AUTO(x) (((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO)
//2 REG_DAC_ANAPAR_DA0
#define BIT_SHIFT_PWR_ALL_CNTR 12
#define BIT_MASK_PWR_ALL_CNTR 0xfffff
#define BIT_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
#define BIT_CTRL_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
#define BIT_GET_PWR_ALL_CNTR(x) (((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR)
#define BIT_SHIFT_PWR_FUP_CNTR 0
#define BIT_MASK_PWR_FUP_CNTR 0xfff
#define BIT_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
#define BIT_CTRL_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
#define BIT_GET_PWR_FUP_CNTR(x) (((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR)
//2 REG_DAC_ANAPAR_DA1
#define BIT_FUP_EN BIT(31)
#define BIT_SHIFT_FUP_EN 31
#define BIT_MASK_FUP_EN 0x1
#define BIT_CTRL_FUP_EN(x) (((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN)
#define BIT_SHIFT_ANAPAR_DA 8
#define BIT_MASK_ANAPAR_DA 0x7fffff
#define BIT_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
#define BIT_CTRL_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
#define BIT_GET_ANAPAR_DA(x) (((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA)
#define BIT_D_POW_DACVREF BIT(7)
#define BIT_SHIFT_D_POW_DACVREF 7
#define BIT_MASK_D_POW_DACVREF 0x1
#define BIT_CTRL_D_POW_DACVREF(x) (((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF)
#define BIT_D_POW_VREF2 BIT(6)
#define BIT_SHIFT_D_POW_VREF2 6
#define BIT_MASK_D_POW_VREF2 0x1
#define BIT_CTRL_D_POW_VREF2(x) (((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2)
#define BIT_D_POW_MBIAS BIT(5)
#define BIT_SHIFT_D_POW_MBIAS 5
#define BIT_MASK_D_POW_MBIAS 0x1
#define BIT_CTRL_D_POW_MBIAS(x) (((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS)
#define BIT_D_POW_DIV4 BIT(4)
#define BIT_SHIFT_D_POW_DIV4 4
#define BIT_MASK_D_POW_DIV4 0x1
#define BIT_CTRL_D_POW_DIV4(x) (((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4)
#define BIT_D_POW_DF1SE_R BIT(3)
#define BIT_SHIFT_D_POW_DF1SE_R 3
#define BIT_MASK_D_POW_DF1SE_R 0x1
#define BIT_CTRL_D_POW_DF1SE_R(x) (((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R)
#define BIT_D_POW_DF2SE_L BIT(2)
#define BIT_SHIFT_D_POW_DF2SE_L 2
#define BIT_MASK_D_POW_DF2SE_L 0x1
#define BIT_CTRL_D_POW_DF2SE_L(x) (((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L)
#define BIT_D_POW_DAC_R BIT(1)
#define BIT_SHIFT_D_POW_DAC_R 1
#define BIT_MASK_D_POW_DAC_R 0x1
#define BIT_CTRL_D_POW_DAC_R(x) (((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R)
#define BIT_D_POW_DAC_L BIT(0)
#define BIT_SHIFT_D_POW_DAC_L 0
#define BIT_MASK_D_POW_DAC_L 0x1
#define BIT_CTRL_D_POW_DAC_L(x) (((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L)
//================ Register Reg Field =========================
#define REG_DAC0_FIFO_WR 0x0000
#define REG_DAC_CTRL 0x0004
#define REG_DAC_INTR_CTRL 0x0008
#define REG_DAC_INTR_STS 0x000C
#define REG_DAC_PWR_CTRL 0x0010
#define REG_DAC_ANAPAR_DA0 0x0014
#define REG_DAC_ANAPAR_DA1 0x0018
//================ DAC HAL related enumeration ==================
//================ DAC HAL Macro ===========================
#define HAL_DAC_WRITE32(dacidx, addr, value) HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \
,addr,value)
#define HAL_DAC_READ32(dacidx, addr) HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr)
//================ DAC Function Prototypes =====================
RTK_STATUS HalDACInit8195a(IN VOID *Data);
RTK_STATUS HalDACDeInit8195a(IN VOID *Data);
RTK_STATUS HalDACEnableRtl8195a(IN VOID *Data);
RTK_STATUS HalDACIntrCtrl8195a(IN VOID *Data);
u8 HalDACSendRtl8195a(IN VOID *Data);
u32 HalDACReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
#endif

528
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gdma.h Normal file
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@ -0,0 +1,528 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_GDMA_H_
#define _RTL8195A_GDMA_H_
// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1
// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL
#define GDMA_HANDSHAKE_UART0_TX 0
#define GDMA_HANDSHAKE_UART0_RX 1
#define GDMA_HANDSHAKE_UART1_TX 2
#define GDMA_HANDSHAKE_UART1_RX 3
#define GDMA_HANDSHAKE_UART2_TX 14 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_UART2_RX 14 // Only on GDMA 1, hardware fixed
#define GDMA_HANDSHAKE_SSI0_TX 4
#define GDMA_HANDSHAKE_SSI0_RX 5
#define GDMA_HANDSHAKE_SSI1_TX 6
#define GDMA_HANDSHAKE_SSI1_RX 7
#define GDMA_HANDSHAKE_SSI2_TX 15 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_SSI2_RX 15 // Only on GDMA 1, hardware fixed
#define GDMA_HANDSHAKE_I2C0_TX 8
#define GDMA_HANDSHAKE_I2C0_RX 9
#define GDMA_HANDSHAKE_I2C1_TX 10
#define GDMA_HANDSHAKE_I2C1_RX 11
#define GDMA_HANDSHAKE_ADC 12
#define GDMA_HANDSHAKE_DAC0 13 // Only on GDMA 0, hardware fixed
#define GDMA_HANDSHAKE_DAC1 13 // Only on GDMA 1, hardware fixed
#define HAL_GDMAX_READ32(GdmaIndex, addr) \
HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value) \
HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value)
#define HAL_GDMAX_READ16(GdmaIndex, addr) \
HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value) \
HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
#define HAL_GDMAX_READ8(GdmaIndex, addr) \
HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value) \
HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
#define GDMA_CH_MAX 0x06
#define REG_GDMA_CH_OFF 0x058
#define REG_GDMA_CH_SAR 0x000
#define REG_GDMA_CH_DAR 0x008
#define REG_GDMA_CH_LLP 0x010
#define REG_GDMA_CH_CTL 0x018
#define REG_GDMA_CH_SSTAT 0x020
#define REG_GDMA_CH_DSTAT 0x028
#define REG_GDMA_CH_SSTATAR 0x030
#define REG_GDMA_CH_DSTATAR 0x038
#define REG_GDMA_CH_CFG 0x040
#define REG_GDMA_CH_SGR 0x048
#define REG_GDMA_CH_DSR 0x050
#define MAX_DMA_BLOCK_SIZE 4092
//3 Interrupt Registers
#define REG_GDMA_RAW_INT_BASE 0x2C0
#define REG_GDMA_RAW_INT_TFR 0x2C0
#define REG_GDMA_RAW_INT_BLOCK 0x2c8
#define REG_GDMA_RAW_INT_SRC_TRAN 0x2D0
#define REG_GDMA_RAW_INT_DST_TRAN 0x2D8
#define REG_GDMA_RAW_INT_ERR 0x2E0
#define REG_GDMA_STATUS_INT_BASE 0x2E8
#define REG_GDMA_STATUS_INT_TFR 0x2E8
#define REG_GDMA_STATUS_INT_BLOCK 0x2F0
#define REG_GDMA_STATUS_INT_SRC_TRAN 0x2F8
#define REG_GDMA_STATUS_INT_DST_TRAN 0x300
#define REG_GDMA_STATUS_INT_ERR 0x308
#define REG_GDMA_MASK_INT_BASE 0x310
#define REG_GDMA_MASK_INT_TFR 0x310
#define REG_GDMA_MASK_INT_BLOCK 0x318
#define REG_GDMA_MASK_INT_SRC_TRAN 0x320
#define REG_GDMA_MASK_INT_DST_TRAN 0x328
#define REG_GDMA_MASK_INT_INT_ERR 0x330
#define REG_GDMA_CLEAR_INT_BASE 0x338
#define REG_GDMA_CLEAR_INT_TFR 0x338
#define REG_GDMA_CLEAR_INT_BLOCK 0x340
#define REG_GDMA_CLEAR_INT_SRC_TRAN 0x348
#define REG_GDMA_CLEAR_INT_DST_TRAN 0x350
#define REG_GDMA_CLEAR_INT_ERR 0x358
#define REG_GDMA_STATUS_INT 0x360
//3 Software handshaking Registers
#define REG_GDMA_REQ_SRC 0x368
#define REG_GDMA_REQ_DST 0x370
#define REG_GDMA_REQ_SGL_REQ 0x378
#define REG_GDMA_REQ_DST_REQ 0x380
#define REG_GDMA_REQ_LST_SRC 0x388
#define REG_GDMA_REQ_LST_DST 0x390
//3 Miscellaneous Registers
#define REG_GDMA_DMAC_CFG 0x398
#define REG_GDMA_CH_EN 0x3A0
#define REG_GDMA_DMA_ID 0x3A8
#define REG_GDMA_DMA_TEST 0x3B0
#define REG_GDMA_DMA_COM_PARAMS6 0x3C8
#define REG_GDMA_DMA_COM_PARAMS5 0x3D0
#define REG_GDMA_DMA_COM_PARAMS4 0x3D8
#define REG_GDMA_DMA_COM_PARAMS3 0x3E0
#define REG_GDMA_DMA_COM_PARAMS2 0x3E8
#define REG_GDMA_DMA_COM_PARAMS1 0x3F0
#define REG_GDMA_DMA_COM_PARAMS0 0x3F8
//3 CTL Register Bit Control
#define BIT_SHIFT_CTLX_LO_INT_EN 0
#define BIT_MASK_CTLX_LO_INT_EN 0x1
#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN)
#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN))
#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1
#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7
#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)
#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH))
#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4
#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7
#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)
#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH))
#define BIT_SHIFT_CTLX_LO_DINC 7
#define BIT_MASK_CTLX_LO_DINC 0x3
#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC)
#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC))
#define BIT_SHIFT_CTLX_LO_SINC 9
#define BIT_MASK_CTLX_LO_SINC 0x3
#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC)
#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC))
#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11
#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7
#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE)
#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE))
#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14
#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7
#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE)
#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE))
#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17
#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1
#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)
#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN))
#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18
#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1
#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)
#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN))
#define BIT_SHIFT_CTLX_LO_TT_FC 20
#define BIT_MASK_CTLX_LO_TT_FC 0x7
#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC)
#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC))
#define BIT_SHIFT_CTLX_LO_DMS 23
#define BIT_MASK_CTLX_LO_DMS 0x3
#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS)
#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS))
#define BIT_SHIFT_CTLX_LO_SMS 25
#define BIT_MASK_CTLX_LO_SMS 0x3
#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS)
#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS))
#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27
#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1
#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN)
#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN))
#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28
#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1
#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)
#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN))
#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0
#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF
#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS)
#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS))
#define BIT_SHIFT_CTLX_UP_DONE 12
#define BIT_MASK_CTLX_UP_DONE 0x1
#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE)
#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE))
//3 CFG Register Bit Control
#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5
#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7
#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR)
#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR))
#define BIT_SHIFT_CFGX_LO_CH_SUSP 8
#define BIT_MASK_CFGX_LO_CH_SUSP 0x1
#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP)
#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP))
#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9
#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1
#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)
#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY))
#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10
#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1
#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST)
#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST))
#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11
#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1
#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)
#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC))
#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12
#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3
#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L)
#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L))
#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14
#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3
#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L)
#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L))
#define BIT_SHIFT_CFGX_LO_LOCK_CH 16
#define BIT_MASK_CFGX_LO_LOCK_CH 0x1
#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH)
#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH))
#define BIT_SHIFT_CFGX_LO_LOCK_B 17
#define BIT_MASK_CFGX_LO_LOCK_B 0x1
#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B)
#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B))
#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18
#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1
#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL)
#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL))
#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19
#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1
#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL)
#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL))
#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20
#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF
#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST)
#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST))
#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30
#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1
#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC)
#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC))
#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31
#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1
#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST)
#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST))
#define BIT_SHIFT_CFGX_UP_FCMODE 0
#define BIT_MASK_CFGX_UP_FCMODE 0x1
#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE)
#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE))
#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1
#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1
#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE)
#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE))
#define BIT_SHIFT_CFGX_UP_PROTCTL 2
#define BIT_MASK_CFGX_UP_PROTCTL 0x7
#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL)
#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL))
#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5
#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1
#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN)
#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN))
#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6
#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1
#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN)
#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN))
#define BIT_SHIFT_CFGX_UP_SRC_PER 7
#define BIT_MASK_CFGX_UP_SRC_PER 0xF
#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER)
#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER))
#define BIT_SHIFT_CFGX_UP_DEST_PER 11
#define BIT_MASK_CFGX_UP_DEST_PER 0xF
#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER)
#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER))
typedef enum _GDMA_CHANNEL_NUM_ {
GdmaNoCh = 0x0000,
GdmaCh0 = 0x0101,
GdmaCh1 = 0x0202,
GdmaCh2 = 0x0404,
GdmaCh3 = 0x0808,
GdmaCh4 = 0x1010,
GdmaCh5 = 0x2020,
GdmaCh6 = 0x4040,
GdmaCh7 = 0x8080,
GdmaAllCh = 0xffff
}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM;
//3 CTL register struct
typedef enum _GDMA_CTL_TT_FC_TYPE_ {
TTFCMemToMem = 0x00,
TTFCMemToPeri = 0x01,
TTFCPeriToMem = 0x02
}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE;
//Max type = Bus Width
typedef enum _GDMA_CTL_TR_WIDTH_ {
TrWidthOneByte = 0x00,
TrWidthTwoBytes = 0x01,
TrWidthFourBytes = 0x02
}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH;
typedef enum _GDMA_CTL_MSIZE_ {
MsizeOne = 0x00,
MsizeFour = 0x01,
MsizeEight = 0x02
}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE;
typedef enum _GDMA_INC_TYPE_ {
IncType = 0x00,
DecType = 0x01,
NoChange = 0x02
}GDMA_INC_TYPE, *PGDMA_INC_TYPE;
typedef struct _GDMA_CTL_REG_ {
GDMA_CTL_TT_FC_TYPE TtFc;
GDMA_CTL_TR_WIDTH DstTrWidth;
GDMA_CTL_TR_WIDTH SrcTrWidth;
GDMA_INC_TYPE Dinc;
GDMA_INC_TYPE Sinc;
GDMA_CTL_MSIZE DestMsize;
GDMA_CTL_MSIZE SrcMsize;
u8 IntEn :1; // Bit 0
u8 SrcGatherEn :1; // Bit 1
u8 DstScatterEn :1; // Bit 2
u8 LlpDstEn :1; // Bit 3
u8 LlpSrcEn :1; // Bit 4
u8 Done :1; // Bit 5
u8 Rsvd6To7 :2; //Bit 6 -7
u16 BlockSize;
}GDMA_CTL_REG, *PGDMA_CTL_REG;
//3 CFG Register Structure
typedef enum _GDMA_CH_PRIORITY_ {
Prior0 = 0,
Prior1 = 1,
Prior2 = 2,
Prior3 = 3,
Prior4 = 4,
Prior5 = 5,
Prior6 = 6,
Prior7 = 7
}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY;
typedef enum _GDMA_LOCK_LEVEL_ {
OverComplDmaTransfer = 0x00,
OverComplDmaBlockTransfer = 0x01,
OverComplDmaTransation = 0x02
}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL;
typedef struct _GDMA_CFG_REG_ {
GDMA_CH_PRIORITY ChPrior;
GDMA_LOCK_LEVEL LockBL;
GDMA_LOCK_LEVEL LockChL;
u16 MaxAbrst;
u8 SrcPer;
u8 DestPer;
u16 ChSusp :1; //Bit 0
u16 FifoEmpty :1; //Bit 1
u16 HsSelDst :1; //Bit 2
u16 HsSelSrc :1; //Bit 3
u16 LockCh :1; //Bit 4
u16 LockB :1; //Bit 5
u16 DstHsPol :1; //Bit 6
u16 SrcHsPol :1; //Bit 7
u16 ReloadSrc :1; //Bit 8
u16 ReloadDst :1; //Bit 9
u16 FifoMode :1; //Bit 10
u16 DsUpdEn :1; //Bit 11
u16 SsUpdEn :1; //Bit 12
u16 Rsvd13To15 :3;
}GDMA_CFG_REG, *PGDMA_CFG_REG;
typedef enum _GDMA_ISR_TYPE_ {
TransferType = 0x1,
BlockType = 0x2,
SrcTransferType = 0x4,
DstTransferType = 0x8,
ErrType = 0x10
}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE;
VOID
HalGdmaOnOffRtl8195a (
IN VOID *Data
);
BOOL
HalGdamChInitRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChSetingRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChBlockSetingRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaChBlockSetingRtl8195a_Patch(
IN VOID *Data
);
VOID
HalGdmaChDisRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChEnRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChIsrEnAndDisRtl8195a (
IN VOID *Data
);
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
);
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
);
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
);
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
);
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
);
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ BOOL
HalGdmaChBlockSetingRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u32
HalGdmaQueryDArRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u32
HalGdmaQuerySArRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ BOOL
HalGdmaQueryChEnRtl8195a_V04 (
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
#endif

398
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h Normal file
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@ -0,0 +1,398 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_GPIO_H_
#define _RTL8195A_GPIO_H_
#include "hal_api.h"
#include "hal_gpio.h"
#define GPIO_PORTA_DR 0x00 // data register
#define GPIO_PORTA_DDR 0x04 // data direction
#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
#define GPIO_PORTB_DR 0x0c // data register
#define GPIO_PORTB_DDR 0x10 // data direction
#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
#define GPIO_PORTC_DR 0x18 // data register
#define GPIO_PORTC_DDR 0x1c // data direction
#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
//1 Only the PORTA can be configured to generate interrupts
#define GPIO_INT_EN 0x30 // Interrupt enable register
#define GPIO_INT_MASK 0x34 // Interrupt mask
#define GPIO_INT_TYPE 0x38 // Interrupt type(level/edge) register
#define GPIO_INT_POLARITY 0x3C // Interrupt polarity(Active low/high) register
#define GPIO_INT_STATUS 0x40 // Interrupt status
#define GPIO_INT_RAWSTATUS 0x44 // Interrupt status without mask
#define GPIO_DEBOUNCE 0x48 // Interrupt signal debounce
#define GPIO_PORTA_EOI 0x4c // Clear interrupt
#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back
#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back
#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back
#define GPIO_INT_SYNC 0x60 // Is level-sensitive interrupt being sync sith PCLK
enum {
HAL_GPIO_HIGHZ = 0,
HAL_GPIO_PULL_LOW = 1,
HAL_GPIO_PULL_HIGH = 2
};
typedef enum
{
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
GPIO_Mode_INT = 0x02, /*!< GPIO Interrupt Mode */
GPIO_Mode_MAX = 0x03,
}GPIOMode_TypeDef;
/**
* @brief GPIO Configuration PullUp PullDown enumeration
*/
typedef enum
{
GPIO_PuPd_NOPULL = 0x00, /*!< GPIO Interrnal HIGHZ */
GPIO_PuPd_DOWN = 0x01, /*!< GPIO Interrnal Pull DOWN */
GPIO_PuPd_UP = 0x02, /*!< GPIO Interrnal Pull UP */
}GPIOPuPd_TypeDef;
/**
* @brief Setting interrupt's trigger type
*
* Setting interrupt's trigger type
*/
typedef enum
{
GPIO_INT_Trigger_LEVEL = 0x0, /**< This interrupt is level trigger */
GPIO_INT_Trigger_EDGE = 0x1, /**< This interrupt is edge trigger */
}GPIOIT_LevelType;
/**
* @brief Setting interrupt active mode
*
* Setting interrupt active mode
*/
typedef enum
{
GPIO_INT_POLARITY_ACTIVE_LOW = 0x0, /**< Setting interrupt to low active: falling edge or low level */
GPIO_INT_POLARITY_ACTIVE_HIGH = 0x1, /**< Setting interrupt to high active: rising edge or high level */
}GPIOIT_PolarityType;
/**
* @brief Enable/Disable interrupt debounce mode
*
* Enable/Disable interrupt debounce mode
*/
typedef enum
{
GPIO_INT_DEBOUNCE_DISABLE = 0x0, /**< Disable interrupt debounce */
GPIO_INT_DEBOUNCE_ENABLE = 0x1, /**< Enable interrupt debounce */
}GPIOIT_DebounceType;
typedef struct {
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. */
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. */
GPIOIT_LevelType GPIO_ITTrigger; /**< Interrupt mode is level or edge trigger */
GPIOIT_PolarityType GPIO_ITPolarity; /**< Interrupt mode is high or low active trigger */
GPIOIT_DebounceType GPIO_ITDebounce; /**< Enable or disable de-bounce for interrupt */
u32 GPIO_Pin; // Pin: [7:5]: port number, [4:0]: pin number
}GPIO_InitTypeDef;
//======================================================
// ROM Function prototype
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
static __inline HAL_Status
GPIO_Lock (
VOID
)
{
HAL_Status Status;
if (_pHAL_Gpio_Adapter->EnterCritical) {
_pHAL_Gpio_Adapter->EnterCritical();
}
if(_pHAL_Gpio_Adapter->Locked) {
Status = HAL_BUSY;
}
else {
_pHAL_Gpio_Adapter->Locked = 1;
Status = HAL_OK;
}
if (_pHAL_Gpio_Adapter->ExitCritical) {
_pHAL_Gpio_Adapter->ExitCritical();
}
return Status;
}
static __inline VOID
GPIO_UnLock (
VOID
)
{
if (_pHAL_Gpio_Adapter->EnterCritical) {
_pHAL_Gpio_Adapter->EnterCritical();
}
_pHAL_Gpio_Adapter->Locked = 0;
if (_pHAL_Gpio_Adapter->ExitCritical) {
_pHAL_Gpio_Adapter->ExitCritical();
}
}
#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES
_LONG_CALL_ extern u32
HAL_GPIO_IrqHandler_8195a(
IN VOID *pData
);
_LONG_CALL_ extern u32
HAL_GPIO_MbedIrqHandler_8195a(
IN VOID *pData
);
_LONG_CALL_ HAL_Status
HAL_GPIO_IntCtrl_8195a(
HAL_GPIO_PIN *GPIO_Pin,
u32 En
);
_LONG_CALL_ HAL_Status
HAL_GPIO_Init_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_DeInit_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_GPIO_PIN_STATE
HAL_GPIO_ReadPin_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_WritePin_8195a(
HAL_GPIO_PIN *GPIO_Pin,
HAL_GPIO_PIN_STATE Pin_State
);
_LONG_CALL_ HAL_Status
HAL_GPIO_RegIrq_8195a(
IN PIRQ_HANDLE pIrqHandle
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UnRegIrq_8195a(
IN PIRQ_HANDLE pIrqHandle
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UserRegIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin,
VOID *IrqHandler,
VOID *IrqData
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UserUnRegIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_MaskIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_UnMaskIrq_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_IntDebounce_8195a(
HAL_GPIO_PIN *GPIO_Pin,
u8 Enable
);
_LONG_CALL_ u32
HAL_GPIO_GetIPPinName_8195a(
u32 chip_pin
);
_LONG_CALL_ HAL_Status
HAL_GPIO_PullCtrl_8195a(
u32 chip_pin,
u8 pull_type
);
_LONG_CALL_ u32
GPIO_GetChipPinName_8195a(
u32 port,
u32 pin
);
_LONG_CALL_ VOID
GPIO_PullCtrl_8195a(
u32 chip_pin,
u8 pull_type
);
_LONG_CALL_ VOID
GPIO_Int_SetType_8195a(
u8 pin_num,
u8 int_mode
);
_LONG_CALL_ HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN *GPIO_Pin, u32 En);
_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr);
HAL_Status
HAL_GPIO_ClearISR_8195a(
HAL_GPIO_PIN *GPIO_Pin
);
/********** HAL In-Line Functions **********/
/**
* @brief Reads the specified input port pin.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval The input port pin current status(High or Low).
*/
static __inline s32
HAL_GPIO_ReadPin(
HAL_GPIO_PIN *GPIO_Pin
)
{
return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin);
}
/**
* @brief Write the specified output port pin.
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @param Pin_State: The state going to be set to the assigned GPIO pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_WritePin(
HAL_GPIO_PIN *GPIO_Pin,
u32 Value
)
{
HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value);
}
/**
* @brief To register a user interrupt handler for a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @param IrqHandler: The IRQ handler to be assigned to the specified pin
*
* @param IrqData: The pointer will be pass the the IRQ handler
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UserRegIrq(
HAL_GPIO_PIN *GPIO_Pin,
VOID *IrqHandler,
VOID *IrqData
)
{
HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData);
}
/**
* @brief To un-register a user interrupt handler for a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UserUnRegIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin);
}
/**
* @brief Enable/Disable GPIO interrupt
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
*
* @param En: Enable (1) or Disable (0)
*
* @retval HAL_Status
*/
static __inline VOID
HAL_GPIO_IntCtrl(
HAL_GPIO_PIN *GPIO_Pin,
u32 En
)
{
HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En);
}
/**
* @brief Mask the interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_MaskIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
}
/**
* @brief UnMask the interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
static __inline VOID
HAL_GPIO_UnMaskIrq(
HAL_GPIO_PIN *GPIO_Pin
)
{
HAL_GPIO_ClearISR_8195a(GPIO_Pin);
HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin);
}
#endif // end of "#define _RTL8195A_GPIO_H_"

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/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*******************************************************************************/
#ifndef __RTL8195A_GSPI_H__
#define __RTL8195A_GSPI_H__
#define SPI_LOCAL_DOMAIN 0x0
#define SPI_TXFIFO_DOMAIN 0xc
#define SPI_RXFIFO_DOMAIN 0x1f
//IO Bus domain address mapping
#define DEFUALT_OFFSET 0x0
#define SPI_LOCAL_OFFSET 0x10250000
#define SPI_TX_FIFO_OFFSET 0x10310000
#define SPI_RX_FIFO_OFFSET 0x10340000
#define SPI_LOCAL_DEVICE_ID 0
#define SPI_TXQ_FIFO_DEVICE_ID 3
#define SPI_RXQ_FIFO_DEVICE_ID 7
#define SPI_UNDEFINED_DEVICE_ID (-1)
//SPI Local registers
#define SPI_REG_INT_CTRL 0x0004 // 4 bytes, SPI INT Control
#define SPI_REG_INT_TIMEOUT 0x0006 // 2 bytes, SPI 32us INT timout
#define SPI_REG_HIMR 0x0014 // 4 bytes, SPI Host Interrupt Mask
#define SPI_REG_HISR 0x0018 // 4 bytes, SPI Host Interrupt Service Routine
#define SPI_REG_RX0_REQ_LEN 0x001C // 4 bytes, RXDMA Request Length
#define SPI_REG_FREE_TX_SPACE 0x0020 // 4 bytes, Free Tx Buffer Page
#define SPI_REG_TX_SEQNUM 0x0024 // 1 byte, TX Sequence Number Definition
#define SPI_REG_HCPWM 0x0038 // 1 byte, HCI Current Power Mode
#define SPI_REG_HCPWM2 0x003A // 2 bytes, HCI Current Power Mode 2
#define SPI_REG_AVAI_PATH_L 0x0040 // 4 bytes, SPI TX Available Low Size reg
#define SPI_REG_AVAI_PATH_H 0x0044 // 4 bytes, SPI TX Available High Size reg
#define SPI_REG_RX_AGG_CTL 0x0048 // 4 bytes, SPI RX AGG control
#define SPI_REG_H2C_MSG 0x004C // 4 bytes, SPI_REG_H2C_MSG
#define SPI_REG_C2H_MSG 0x0050 // 4 bytes, SPI_REG_C2H_MSG
#define SPI_REG_HRPWM 0x0080 // 1 byte, SPI_REG_HRPWM
#define SPI_REG_HPS_CLKR 0x0084 // 1 byte, not uesd
#define SPI_REG_CPU_IND 0x0087 // 1 byte, firmware indication to host
#define SPI_REG_32K_TRANS_CTL 0x0088 // 1 byte, 32K transparent control, BIT0 EN32K_TRANS
#define SPI_REG_32K_IDLE_TIME 0x008B // 1 byte, 32K idle time,
#define SPI_REG_DELY_LINE_SEL 0x008C // 1 byte, Delay line selection,
#define SPI_REG_SPI_CFG 0x00F0 // 1 byte, SPI configuration,
#define LOCAL_REG_FREE_TX_SPACE (SPI_LOCAL_OFFSET | SPI_REG_FREE_TX_SPACE)
// Register SPI_REG_CPU_IND
#define SPI_CPU_RDY_IND (BIT0)
/************************************************/
// SPI_REG_HISR: SDIO Host Interrupt Service Routine
#define SPI_HISR_RX_REQUEST (BIT0)
#define SPI_HISR_AVAL_INT (BIT1)
#define SPI_HISR_TXPKT_OVER_BUFF (BIT2)
#define SPI_HISR_TX_AGG_SIZE_MISMATCH (BIT3)
#define SPI_HISR_TXBD_OVF (BIT4)
//BIT5~16 not used
#define SPI_HISR_C2H_MSG_INT (BIT17)
#define SPI_HISR_CPWM1_INT (BIT18)
#define SPI_HISR_CPWM2_INT (BIT19)
//BIT20~31 not used
#define SPI_HISR_CPU_NOT_RDY (BIT22)
#define MASK_SPI_HISR_CLEAR (SPI_HISR_RX_REQUEST |\
SPI_HISR_AVAL_INT |\
SPI_HISR_TXPKT_OVER_BUFF |\
SPI_HISR_TX_AGG_SIZE_MISMATCH |\
SPI_HISR_TXBD_OVF |\
SPI_HISR_C2H_MSG_INT |\
SPI_HISR_CPWM1_INT |\
SPI_HISR_CPWM2_INT)
// RTL8195A SPI Host Interrupt Mask Register
#define SPI_HIMR_RX_REQUEST_MSK (BIT0)
#define SPI_HIMR_AVAL_MSK (BIT1)
#define SPI_HIMR_TXPKT_SIZE_OVER_BUFF_MSK (BIT2)
#define SPI_HIMR_AGG_SIZE_MISMATCH_MSK (BIT3)
#define SPI_HIMR_TXBD_OVF_MSK (BIT4)
//BIT5~16 not used
#define SPI_HIMR_C2H_MSG_INT_MSK (BIT17)
#define SPI_HIMR_CPWM1_INT_MSK (BIT18)
#define SPI_HIMR_CPWM2_INT_MSK (BIT19)
//BIT20~31 not used
#define SPI_HIMR_DISABLED 0
// Register SPI_REG_HCPWM
#define SPI_HCPWM_WLAN_TRX (BIT1)
enum{
SPI_LITTLE_ENDIAN = 2,
SPI_BIG_ENDIAN = 0
};
enum{
SPI_WORD_LEN_16 = 0,
SPI_WORD_LEN_32 = 1
};
typedef enum{
SPI_LITTLE_ENDIAN_16 = SPI_LITTLE_ENDIAN|SPI_WORD_LEN_16,
SPI_LITTLE_ENDIAN_32 = SPI_LITTLE_ENDIAN|SPI_WORD_LEN_32, // default configure
SPI_BIG_ENDIAN_16 = SPI_BIG_ENDIAN|SPI_WORD_LEN_16,
SPI_BIG_ENDIAN_32 = SPI_BIG_ENDIAN|SPI_WORD_LEN_32
}_gspi_conf_t;
#define GSPI_CMD_LEN 4
#define GSPI_STATUS_LEN 8
#define FILL_SPI_CMD(byte_en, addr, domain_id, fun, write_flag) ((byte_en & 0xff) | ((addr & 0xffff) << 8) \
| ((domain_id & 0x1f) << 24) | ((fun & 0x3) << 29) | ((write_flag & 0x1) << 31))
#define GET_STATUS_HISR(status) ((((*(u32*)status)) & 0x3) |((((*(u32*)status) >> 2) & 0x7) << 17))
#define GET_STATUS_FREE_TX(status) ((((*(u32*)status) >> 5) & 0x7ffffff) << 2)
#define GET_STATUS_RXQ_REQ_LEN(status) (((*(u32*)((u8 *)status + 4))) & 0xffffff)
#define GET_STATUS_TX_SEQ(status) (((*(u32*)((u8 *)status + 4)) >> 24) & 0xff)
#define GSPI_CMD_TX 0x83 //
#define GSPI_CMD_RX 0X82
// define transmit packat type
#define GPSI_TX_PACKET_802_3 (0x83)
#define GSPI_TX_PACKET_802_11 (0x81)
#define GSPI_TX_H2C_CMD (0x11)
#define GSPI_TX_MEM_READ (0x51)
#define GSPI_TX_MEM_WRITE (0x53)
#define GSPI_TX_MEM_SET (0x55)
#define GSPI_TX_FM_FREETOGO (0x61)
//define receive packet type
#define GSPI_RX_PACKET_802_3 (0x82)
#define GSPI_RX_PACKET_802_11 (0x80)
#define GSPI_RX_C2H_CMD (0x10)
#define GSPI_RX_MEM_READ (0x50)
#define GSPI_RX_MEM_WRITE (0x52)
#define GSPI_RX_MEM_SET (0x54)
#define GSPI_RX_FM_FREETOGO (0x60)
typedef struct _GSPI_TX_DESC{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 rsvd0:24;
#else
u32 rsvd0:24;
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 rsvd1;
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} GSPI_TX_DESC, *PGSPI_TX_DESC;
typedef struct _GSPI_RX_DESC{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:6; // bit[29:24]
u32 icv:1; // bit[30], ICV error
u32 crc:1; // bit[31], CRC error
#else
u32 crc:1; // bit[31], CRC error
u32 icv:1; // bit[30], ICV error
u32 rsvd0:6; // bit[29:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 rsvd2;
// u4Byte 3
u32 rsvd3;
// u4Byte 4
u32 rsvd4;
// u4Byte 5
u32 rsvd5;
} GSPI_RX_DESC, *PGSPI_RX_DESC;
#define SIZE_TX_DESC (sizeof(GSPI_TX_DESC))
#define SIZE_RX_DESC (sizeof(GSPI_RX_DESC))
// For memory read command
typedef struct _GSPI_DESC_MR{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:8; // bit[31:24]
#else
u32 rsvd0:8; // bit[31:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 start_addr;
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} GSPI_DESC_MR, *PGSPI_DESC_MR;
// For memory write reply command
typedef struct _GSPI_DESC_MW{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 reply:1; // bit[8], request to send a reply message
u32 rsvd0:23;
#else
u32 rsvd0:23;
u32 reply:1; // bit[8], request to send a reply message
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_addr; // memory write start address
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 write_len:16; // bit[15:0], the length to write
u32 rsvd2:16; // bit[31:16]
#else
u32 rsvd2:16; // bit[31:16]
u32 write_len:16; // bit[15:0], the length to write
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} GSPI_DESC_MW, *PGSPI_DESC_MW;
// For memory set command
typedef struct _GSPI_DESC_MS{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 data:8; // bit[8:15], the value to be written to the memory
u32 reply:1; // bit[16], request to send a reply message
u32 rsvd0:15;
#else
u32 rsvd0:15;
u32 reply:1; // bit[16], request to send a reply message
u32 data:8; // bit[8:15], the value to be written to the memory
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_addr; // memory write start address
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 write_len:16; // bit[15:0], the length to write
u32 rsvd2:16; // bit[31:16]
#else
u32 rsvd2:16; // bit[31:16]
u32 write_len:16; // bit[15:0], the length to write
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} GSPI_DESC_MS, *PGSPI_DESC_MS;
// TX Desc for Jump to Start command
typedef struct _GSPI_DESC_JS{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 rsvd0:24;
#else
u32 rsvd0:24;
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_fun; // the pointer of the startup function
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} GSPI_DESC_JS, *PGSPI_DESC_JS;
// CCPWM2 bit map definition for Firmware download
#define GSPI_INIT_DONE (BIT0)
#define GSPI_MEM_WR_DONE (BIT1)
#define GSPI_MEM_RD_DONE (BIT2)
#define GSPI_MEM_ST_DONE (BIT3)
#define GSPI_CPWM2_TOGGLE (BIT15)
// Register REG_SPDIO_CPU_IND
#define GPSI_SYSTEM_TRX_RDY_IND (BIT0)
#endif //__GSPI_REG_H__

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_I2C_H_
#define _RTL8195A_I2C_H_
#include "hal_api.h"
//================ Register Bit Field ==================
//2 REG_DW_I2C_IC_CON
#define BIT_IC_CON_IC_SLAVE_DISABLE BIT(6)
#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE 6
#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE 0x1
#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x) (((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE)
#define BIT_IC_CON_IC_RESTART_EN BIT(5)
#define BIT_SHIFT_IC_CON_IC_RESTART_EN 5
#define BIT_MASK_IC_CON_IC_RESTART_EN 0x1
#define BIT_CTRL_IC_CON_IC_RESTART_EN(x) (((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN)
#define BIT_IC_CON_IC_10BITADDR_MASTER BIT(4)
#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER 4
#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER 0x1
#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER)
#define BIT_IC_CON_IC_10BITADDR_SLAVE BIT(3)
#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE 3
#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE 0x1
#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE)
#define BIT_SHIFT_IC_CON_SPEED 1
#define BIT_MASK_IC_CON_SPEED 0x3
#define BIT_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
#define BIT_CTRL_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
#define BIT_GET_IC_CON_SPEED(x) (((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED)
#define BIT_IC_CON_MASTER_MODE BIT(0)
#define BIT_SHIFT_IC_CON_MASTER_MODE 0
#define BIT_MASK_IC_CON_MASTER_MODE 0x1
#define BIT_CTRL_IC_CON_MASTER_MODE(x) (((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE)
//2 REG_DW_I2C_IC_TAR
#define BIT_IC_TAR_IC_10BITADDR_MASTER BIT(12)
#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER 12
#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER 0x1
#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER)
#define BIT_IC_TAR_SPECIAL BIT(11)
#define BIT_SHIFT_IC_TAR_SPECIAL 11
#define BIT_MASK_IC_TAR_SPECIAL 0x1
#define BIT_CTRL_IC_TAR_SPECIAL(x) (((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL)
#define BIT_IC_TAR_GC_OR_START BIT(10)
#define BIT_SHIFT_IC_TAR_GC_OR_START 10
#define BIT_MASK_IC_TAR_GC_OR_START 0x1
#define BIT_CTRL_IC_TAR_GC_OR_START(x) (((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START)
#define BIT_SHIFT_IC_TAR 0
#define BIT_MASK_IC_TAR 0x3ff
#define BIT_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
#define BIT_CTRL_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
#define BIT_GET_IC_TAR(x) (((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR)
//2 REG_DW_I2C_IC_SAR
#define BIT_SHIFT_IC_SAR 0
#define BIT_MASK_IC_SAR 0x3ff
#define BIT_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
#define BIT_CTRL_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
#define BIT_GET_IC_SAR(x) (((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR)
//2 REG_DW_I2C_IC_HS_MADDR
#define BIT_SHIFT_IC_HS_MADDR 0
#define BIT_MASK_IC_HS_MADDR 0x7
#define BIT_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
#define BIT_CTRL_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
#define BIT_GET_IC_HS_MADDR(x) (((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR)
//2 REG_DW_I2C_IC_DATA_CMD
#define BIT_IC_DATA_CMD_RESTART BIT(10)
#define BIT_SHIFT_IC_DATA_CMD_RESTART 10
#define BIT_MASK_IC_DATA_CMD_RESTART 0x1
#define BIT_CTRL_IC_DATA_CMD_RESTART(x) (((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART)
#define BIT_IC_DATA_CMD_STOP BIT(9)
#define BIT_SHIFT_IC_DATA_CMD_STOP 9
#define BIT_MASK_IC_DATA_CMD_STOP 0x1
#define BIT_CTRL_IC_DATA_CMD_STOP(x) (((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP)
#define BIT_IC_DATA_CMD_CMD BIT(8)
#define BIT_SHIFT_IC_DATA_CMD_CMD 8
#define BIT_MASK_IC_DATA_CMD_CMD 0x1
#define BIT_CTRL_IC_DATA_CMD_CMD(x) (((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD)
#define BIT_SHIFT_IC_DATA_CMD_DAT 0
#define BIT_MASK_IC_DATA_CMD_DAT 0xff
#define BIT_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
#define BIT_CTRL_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
#define BIT_GET_IC_DATA_CMD_DAT(x) (((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT)
//2 REG_DW_I2C_IC_SS_SCL_HCNT
#define BIT_SHIFT_IC_SS_SCL_HCNT 0
#define BIT_MASK_IC_SS_SCL_HCNT 0xffff
#define BIT_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
#define BIT_CTRL_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
#define BIT_GET_IC_SS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT)
//2 REG_DW_I2C_IC_SS_SCL_LCNT
#define BIT_SHIFT_IC_SS_SCL_LCNT 0
#define BIT_MASK_IC_SS_SCL_LCNT 0xffff
#define BIT_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
#define BIT_CTRL_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
#define BIT_GET_IC_SS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT)
//2 REG_DW_I2C_IC_FS_SCL_HCNT
#define BIT_SHIFT_IC_FS_SCL_HCNT 0
#define BIT_MASK_IC_FS_SCL_HCNT 0xffff
#define BIT_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
#define BIT_CTRL_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
#define BIT_GET_IC_FS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT)
//2 REG_DW_I2C_IC_FS_SCL_LCNT
#define BIT_SHIFT_IC_FS_SCL_LCNT 0
#define BIT_MASK_IC_FS_SCL_LCNT 0xffff
#define BIT_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
#define BIT_CTRL_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
#define BIT_GET_IC_FS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT)
//2 REG_DW_I2C_IC_HS_SCL_HCNT
#define BIT_SHIFT_IC_HS_SCL_HCNT 0
#define BIT_MASK_IC_HS_SCL_HCNT 0xffff
#define BIT_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
#define BIT_CTRL_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
#define BIT_GET_IC_HS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT)
//2 REG_DW_I2C_IC_HS_SCL_LCNT
#define BIT_SHIFT_IC_HS_SCL_LCNT 0
#define BIT_MASK_IC_HS_SCL_LCNT 0xffff
#define BIT_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
#define BIT_CTRL_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
#define BIT_GET_IC_HS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT)
//2 REG_DW_I2C_IC_INTR_STAT
#define BIT_IC_INTR_STAT_R_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL 11
#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL 0x1
#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL)
#define BIT_IC_INTR_STAT_R_START_DET BIT(10)
#define BIT_SHIFT_IC_INTR_STAT_R_START_DET 10
#define BIT_MASK_IC_INTR_STAT_R_START_DET 0x1
#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET)
#define BIT_IC_INTR_STAT_R_STOP_DET BIT(9)
#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET 9
#define BIT_MASK_IC_INTR_STAT_R_STOP_DET 0x1
#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET)
#define BIT_IC_INTR_STAT_R_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY 8
#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY 0x1
#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY)
#define BIT_IC_INTR_STAT_R_RX_DONE BIT(7)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE 7
#define BIT_MASK_IC_INTR_STAT_R_RX_DONE 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE)
#define BIT_IC_INTR_STAT_R_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT 6
#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT)
#define BIT_IC_INTR_STAT_R_RD_REQ BIT(5)
#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ 5
#define BIT_MASK_IC_INTR_STAT_R_RD_REQ 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ)
#define BIT_IC_INTR_STAT_R_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY 4
#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY)
#define BIT_IC_INTR_STAT_R_TX_OVER BIT(3)
#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER 3
#define BIT_MASK_IC_INTR_STAT_R_TX_OVER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER)
#define BIT_IC_INTR_STAT_R_RX_FULL BIT(2)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL 2
#define BIT_MASK_IC_INTR_STAT_R_RX_FULL 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL)
#define BIT_IC_INTR_STAT_R_RX_OVER BIT(1)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER 1
#define BIT_MASK_IC_INTR_STAT_R_RX_OVER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER)
#define BIT_IC_INTR_STAT_R_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER 0
#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER 0x1
#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER)
//2 REG_DW_I2C_IC_INTR_MASK
#define BIT_IC_INTR_MASK_M_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL 11
#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL 0x1
#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL)
#define BIT_IC_INTR_MASK_M_START_DET BIT(10)
#define BIT_SHIFT_IC_INTR_MASK_M_START_DET 10
#define BIT_MASK_IC_INTR_MASK_M_START_DET 0x1
#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET)
#define BIT_IC_INTR_MASK_M_STOP_DET BIT(9)
#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET 9
#define BIT_MASK_IC_INTR_MASK_M_STOP_DET 0x1
#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET)
#define BIT_IC_INTR_MASK_M_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY 8
#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY 0x1
#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY)
#define BIT_IC_INTR_MASK_M_RX_DONE BIT(7)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE 7
#define BIT_MASK_IC_INTR_MASK_M_RX_DONE 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE)
#define BIT_IC_INTR_MASK_M_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT 6
#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT)
#define BIT_IC_INTR_MASK_M_RD_REQ BIT(5)
#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ 5
#define BIT_MASK_IC_INTR_MASK_M_RD_REQ 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ)
#define BIT_IC_INTR_MASK_M_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY 4
#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY)
#define BIT_IC_INTR_MASK_M_TX_OVER BIT(3)
#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER 3
#define BIT_MASK_IC_INTR_MASK_M_TX_OVER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER)
#define BIT_IC_INTR_MASK_M_RX_FULL BIT(2)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL 2
#define BIT_MASK_IC_INTR_MASK_M_RX_FULL 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL)
#define BIT_IC_INTR_MASK_M_RX_OVER BIT(1)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER 1
#define BIT_MASK_IC_INTR_MASK_M_RX_OVER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER)
#define BIT_IC_INTR_MASK_M_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER 0
#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER 0x1
#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER)
//2 REG_DW_I2C_IC_RAW_INTR_STAT
#define BIT_IC_RAW_INTR_STAT_GEN_CALL BIT(11)
#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL 11
#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL)
#define BIT_IC_RAW_INTR_STAT_START_DET BIT(10)
#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET 10
#define BIT_MASK_IC_RAW_INTR_STAT_START_DET 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET)
#define BIT_IC_RAW_INTR_STAT_STOP_DET BIT(9)
#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET 9
#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET)
#define BIT_IC_RAW_INTR_STAT_ACTIVITY BIT(8)
#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY 8
#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY)
#define BIT_IC_RAW_INTR_STAT_RX_DONE BIT(7)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE 7
#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE)
#define BIT_IC_RAW_INTR_STAT_TX_ABRT BIT(6)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT 6
#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT)
#define BIT_IC_RAW_INTR_STAT_RD_REQ BIT(5)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ 5
#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ)
#define BIT_IC_RAW_INTR_STAT_TX_EMPTY BIT(4)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY 4
#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY)
#define BIT_IC_RAW_INTR_STAT_TX_OVER BIT(3)
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER 3
#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER)
#define BIT_IC_RAW_INTR_STAT_RX_FULL BIT(2)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL 2
#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL)
#define BIT_IC_RAW_INTR_STAT_RX_OVER BIT(1)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER 1
#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER)
#define BIT_IC_RAW_INTR_STAT_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER 0
#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER 0x1
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER)
//2 REG_DW_I2C_IC_RX_TL
#define BIT_SHIFT_IC_RX_TL 0
#define BIT_MASK_IC_RX_TL 0xff
#define BIT_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
#define BIT_CTRL_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
#define BIT_GET_IC_RX_TL(x) (((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL)
//2 REG_DW_I2C_IC_TX_TL
#define BIT_SHIFT_IC_TX_TL 0
#define BIT_MASK_IC_TX_TL 0xff
#define BIT_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
#define BIT_CTRL_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
#define BIT_GET_IC_TX_TL(x) (((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL)
//2 REG_DW_I2C_IC_CLR_INTR
#define BIT_IC_CLR_INTR BIT(0)
#define BIT_SHIFT_IC_CLR_INTR 0
#define BIT_MASK_IC_CLR_INTR 0x1
#define BIT_CTRL_IC_CLR_INTR(x) (((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR)
//2 REG_DW_I2C_IC_CLR_RX_UNDER
#define BIT_IC_CLR_RX_UNDER BIT(0)
#define BIT_SHIFT_IC_CLR_RX_UNDER 0
#define BIT_MASK_IC_CLR_RX_UNDER 0x1
#define BIT_CTRL_IC_CLR_RX_UNDER(x) (((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER)
//2 REG_DW_I2C_IC_CLR_RX_OVER
#define BIT_IC_CLR_RX_OVER BIT(0)
#define BIT_SHIFT_IC_CLR_RX_OVER 0
#define BIT_MASK_IC_CLR_RX_OVER 0x1
#define BIT_CTRL_IC_CLR_RX_OVER(x) (((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER)
//2 REG_DW_I2C_IC_CLR_TX_OVER
#define BIT_IC_CLR_TX_OVER BIT(0)
#define BIT_SHIFT_IC_CLR_TX_OVER 0
#define BIT_MASK_IC_CLR_TX_OVER 0x1
#define BIT_CTRL_IC_CLR_TX_OVER(x) (((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER)
//2 REG_DW_I2C_IC_CLR_RD_REQ
#define BIT_IC_CLR_RD_REQ BIT(0)
#define BIT_SHIFT_IC_CLR_RD_REQ 0
#define BIT_MASK_IC_CLR_RD_REQ 0x1
#define BIT_CTRL_IC_CLR_RD_REQ(x) (((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ)
//2 REG_DW_I2C_IC_CLR_TX_ABRT
#define BIT_CLR_RD_REQ BIT(0)
#define BIT_SHIFT_CLR_RD_REQ 0
#define BIT_MASK_CLR_RD_REQ 0x1
#define BIT_CTRL_CLR_RD_REQ(x) (((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ)
//2 REG_DW_I2C_IC_CLR_RX_DONE
#define BIT_IC_CLR_RX_DONE BIT(0)
#define BIT_SHIFT_IC_CLR_RX_DONE 0
#define BIT_MASK_IC_CLR_RX_DONE 0x1
#define BIT_CTRL_IC_CLR_RX_DONE(x) (((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE)
//2 REG_DW_I2C_IC_CLR_ACTIVITY
#define BIT_IC_CLR_ACTIVITY BIT(0)
#define BIT_SHIFT_IC_CLR_ACTIVITY 0
#define BIT_MASK_IC_CLR_ACTIVITY 0x1
#define BIT_CTRL_IC_CLR_ACTIVITY(x) (((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY)
//2 REG_DW_I2C_IC_CLR_STOP_DET
#define BIT_IC_CLR_STOP_DET BIT(0)
#define BIT_SHIFT_IC_CLR_STOP_DET 0
#define BIT_MASK_IC_CLR_STOP_DET 0x1
#define BIT_CTRL_IC_CLR_STOP_DET(x) (((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET)
//2 REG_DW_I2C_IC_CLR_START_DET
#define BIT_IC_CLR_START_DET BIT(0)
#define BIT_SHIFT_IC_CLR_START_DET 0
#define BIT_MASK_IC_CLR_START_DET 0x1
#define BIT_CTRL_IC_CLR_START_DET(x) (((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET)
//2 REG_DW_I2C_IC_CLR_GEN_CALL
#define BIT_IC_CLR_GEN_CALL BIT(0)
#define BIT_SHIFT_IC_CLR_GEN_CALL 0
#define BIT_MASK_IC_CLR_GEN_CALL 0x1
#define BIT_CTRL_IC_CLR_GEN_CALL(x) (((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL)
//2 REG_DW_I2C_IC_ENABLE
#define BIT_IC_ENABLE BIT(0)
#define BIT_SHIFT_IC_ENABLE 0
#define BIT_MASK_IC_ENABLE 0x1
#define BIT_CTRL_IC_ENABLE(x) (((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE)
//2 REG_DW_I2C_IC_STATUS
#define BIT_IC_STATUS_SLV_ACTIVITY BIT(6)
#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY 6
#define BIT_MASK_IC_STATUS_SLV_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY)
#define BIT_IC_STATUS_MST_ACTIVITY BIT(5)
#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY 5
#define BIT_MASK_IC_STATUS_MST_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY)
#define BIT_IC_STATUS_RFF BIT(4)
#define BIT_SHIFT_IC_STATUS_RFF 4
#define BIT_MASK_IC_STATUS_RFF 0x1
#define BIT_CTRL_IC_STATUS_RFF(x) (((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF)
#define BIT_IC_STATUS_RFNE BIT(3)
#define BIT_SHIFT_IC_STATUS_RFNE 3
#define BIT_MASK_IC_STATUS_RFNE 0x1
#define BIT_CTRL_IC_STATUS_RFNE(x) (((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE)
#define BIT_IC_STATUS_TFE BIT(2)
#define BIT_SHIFT_IC_STATUS_TFE 2
#define BIT_MASK_IC_STATUS_TFE 0x1
#define BIT_CTRL_IC_STATUS_TFE(x) (((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE)
#define BIT_IC_STATUS_TFNF BIT(1)
#define BIT_SHIFT_IC_STATUS_TFNF 1
#define BIT_MASK_IC_STATUS_TFNF 0x1
#define BIT_CTRL_IC_STATUS_TFNF(x) (((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF)
#define BIT_IC_STATUS_ACTIVITY BIT(0)
#define BIT_SHIFT_IC_STATUS_ACTIVITY 0
#define BIT_MASK_IC_STATUS_ACTIVITY 0x1
#define BIT_CTRL_IC_STATUS_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY)
//2 REG_DW_I2C_IC_TXFLR
#define BIT_SHIFT_IC_TXFLR 0
#define BIT_MASK_IC_TXFLR 0x3f
#define BIT_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
#define BIT_CTRL_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
#define BIT_GET_IC_TXFLR(x) (((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR)
//2 REG_DW_I2C_IC_RXFLR
#define BIT_SHIFT_IC_RXFLR 0
#define BIT_MASK_IC_RXFLR 0x1f
#define BIT_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
#define BIT_CTRL_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
#define BIT_GET_IC_RXFLR(x) (((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR)
//2 REG_DW_I2C_IC_SDA_HOLD
#define BIT_SHIFT_IC_SDA_HOLD 0
#define BIT_MASK_IC_SDA_HOLD 0xffff
#define BIT_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
#define BIT_CTRL_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
#define BIT_GET_IC_SDA_HOLD(x) (((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD)
//2 REG_DW_I2C_IC_TX_ABRT_SOURCE
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX BIT(15)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 15
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST BIT(14)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 14
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO BIT(13)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 13
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO)
#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST 12
#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS BIT(11)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 11
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT BIT(10)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 10
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 9
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT BIT(8)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 8
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET BIT(7)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 7
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET BIT(6)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 6
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ BIT(5)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 5
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK BIT(4)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 4
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK BIT(3)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 3
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK BIT(2)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 2
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK BIT(1)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 1
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK)
#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK BIT(0)
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0x1
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK)
//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY
#define BIT_IC_SLV_DATA_NACK_ONLY BIT(0)
#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY 0
#define BIT_MASK_IC_SLV_DATA_NACK_ONLY 0x1
#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x) (((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY)
//2 REG_DW_I2C_IC_DMA_CR
#define BIT_IC_DMA_CR_TDMAE BIT(1)
#define BIT_SHIFT_IC_DMA_CR_TDMAE 1
#define BIT_MASK_IC_DMA_CR_TDMAE 0x1
#define BIT_CTRL_IC_DMA_CR_TDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE)
#define BIT_IC_DMA_CR_RDMAE BIT(0)
#define BIT_SHIFT_IC_DMA_CR_RDMAE 0
#define BIT_MASK_IC_DMA_CR_RDMAE 0x1
#define BIT_CTRL_IC_DMA_CR_RDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE)
//2 REG_DW_I2C_IC_DMA_TDLR
#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0
#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f
#define BIT_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
#define BIT_GET_IC_DMA_TDLR_DMATDL(x) (((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL)
//2 REG_DW_I2C_IC_DMA_RDLR
#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0
#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf
#define BIT_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
#define BIT_GET_IC_DMA_RDLR_DMARDL(x) (((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL)
//2 REG_DW_I2C_IC_SDA_SETUP
#define BIT_SHIFT_IC_SDA_SETUP 0
#define BIT_MASK_IC_SDA_SETUP 0xff
#define BIT_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
#define BIT_CTRL_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
#define BIT_GET_IC_SDA_SETUP(x) (((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP)
//2 REG_DW_I2C_IC_ACK_GENERAL_CALL
#define BIT_IC_ACK_GENERAL_CALL BIT(0)
#define BIT_SHIFT_IC_ACK_GENERAL_CALL 0
#define BIT_MASK_IC_ACK_GENERAL_CALL 0x1
#define BIT_CTRL_IC_ACK_GENERAL_CALL(x) (((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL)
//2 REG_DW_I2C_IC_ENABLE_STATUS
#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST BIT(2)
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 2
#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST)
#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY BIT(1)
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 1
#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY)
#define BIT_IC_ENABLE_STATUS_IC_EN BIT(0)
#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN 0
#define BIT_MASK_IC_ENABLE_STATUS_IC_EN 0x1
#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN)
//2 REG_DW_I2C_IC_COMP_PARAM_1
#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16
#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff
#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8
#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff
#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS BIT(7)
#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 7
#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS)
#define BIT_IC_COMP_PARAM_1_HAS_DMA BIT(6)
#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA 6
#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA)
#define BIT_IC_COMP_PARAM_1_INTR_IO BIT(5)
#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO 5
#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO)
#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES BIT(4)
#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES 4
#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES 0x1
#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES)
#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2
#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3
#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE)
#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0
#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3
#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH)
//2 REG_DW_I2C_IC_COMP_VERSION
#define BIT_SHIFT_IC_COMP_VERSION 0
#define BIT_MASK_IC_COMP_VERSION 0xffffffffL
#define BIT_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
#define BIT_CTRL_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
#define BIT_GET_IC_COMP_VERSION(x) (((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION)
//2 REG_DW_I2C_IC_COMP_TYPE
#define BIT_SHIFT_IC_COMP_TYPE 0
#define BIT_MASK_IC_COMP_TYPE 0xffffffffL
#define BIT_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
#define BIT_CTRL_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
#define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE)
//======================== Register Address Definition ========================
#define REG_DW_I2C_IC_CON 0x0000 // Control Register
#define REG_DW_I2C_IC_TAR 0x0004 // Master Target Address
#define REG_DW_I2C_IC_SAR 0x0008 // Slave Address
#define REG_DW_I2C_IC_HS_MADDR 0x000C // High Speed Master ID
#define REG_DW_I2C_IC_DATA_CMD 0x0010 // Data Buffer and Command
#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014 // Standard Speed Clock SCL High Count
#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018 // Standard Speed Clock SCL Low Count
#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C // Fast Speed Clock SCL High Count
#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020 // Fast Speed I2C Clock SCL Low Count
#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024 // High Speed I2C Clock SCL High Count
#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028 // High Speed I2C Clock SCL Low Count
#define REG_DW_I2C_IC_INTR_STAT 0x002C // Interrupt Status
#define REG_DW_I2C_IC_INTR_MASK 0x0030 // Interrupt Mask
#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034 // Raw Interrupt Status
#define REG_DW_I2C_IC_RX_TL 0x0038 // Receive FIFO Threshold Level
#define REG_DW_I2C_IC_TX_TL 0x003C // Transmit FIFO Threshold Level
#define REG_DW_I2C_IC_CLR_INTR 0x0040 // Clear Combined and Individual Interrupt
#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044 // Clear RX_UNDER Interrupt
#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048 // Clear RX_OVER Interrupt
#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C // Clear TX_OVER Interrupt
#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050 // Clear RD_REQ Interrupt
#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054 // Clear TX_ABRT Interrupt
#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058 // Clear RX_DONE Interrupt
#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C // Clear ACTIVITY Interrupt
#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060 // Clear STOP_DET Interrupt
#define REG_DW_I2C_IC_CLR_START_DET 0x0064 // Clear START_DET Interrupt
#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068 // Clear GEN_CALL Interrupt
#define REG_DW_I2C_IC_ENABLE 0x006C // Enable
#define REG_DW_I2C_IC_STATUS 0x0070 // Status
#define REG_DW_I2C_IC_TXFLR 0x0074 // Transmit FIFO Level
#define REG_DW_I2C_IC_RXFLR 0x0078 // Receive FIFO Level
#define REG_DW_I2C_IC_SDA_HOLD 0x007C // SDA Hold
#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080 // Transmit Abort Source
#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084 //
#define REG_DW_I2C_IC_DMA_CR 0x0088 //
#define REG_DW_I2C_IC_DMA_TDLR 0x008C // DMA Transmit Data Level Register
#define REG_DW_I2C_IC_DMA_RDLR 0x0090 // I2C Receive Data Level Register
#define REG_DW_I2C_IC_SDA_SETUP 0x0094 // SDA Setup
#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098 // General Call Ack
#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C // Enable Status
#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4 // Configuration Parameters
#define REG_DW_I2C_IC_COMP_VERSION 0x00F8 // Component Version
#define REG_DW_I2C_IC_COMP_TYPE 0x00FC // Component Type
//======================================================
// I2C related enumeration
// I2C Address Mode
typedef enum _I2C_ADDR_MODE_ {
I2C_ADDR_7BIT = 0,
I2C_ADDR_10BIT = 1,
}I2C_ADDR_MODE,*PI2C_ADDR_MODE;
// I2C Speed Mode
typedef enum _I2C_SPD_MODE_ {
I2C_SS_MODE = 1,
I2C_FS_MODE = 2,
I2C_HS_MODE = 3,
}I2C_SPD_MODE,*PI2C_SPD_MODE;
//I2C Timing Parameters
#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns.
#define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns.
#define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns.
#define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns.
#define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf
#define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf
#define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf
#define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf
//======================================================
//I2C Essential functions and macros
_LONG_CALL_ROM_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal);
_LONG_CALL_ROM_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg);
#define HAL_I2C_WRITE32(I2CIdx, addr, value) HalI2CWrite32(I2CIdx,addr,value)
#define HAL_I2C_READ32(I2CIdx, addr) HalI2CRead32(I2CIdx,addr)
// Rtl8195a I2C function prototypes
_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data);
_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data);
_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg);
_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal);
//Rtl8195a I2C V02 function prototype
_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN VOID *Data);
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
#elif defined(CONFIG_CHIP_E_CUT)
_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
#endif
//Rtl8195a I2C V02 function prototype END
//Rtl8195a I2C V04 function prototype
_LONG_CALL_ HAL_Status HalI2CSendRtl8195a_V04(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a_V04(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CInit8195a_V04(IN VOID *Data);
_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195a_V04(IN VOID *Data);
//Rtl8195a I2C V04 function prototype END
HAL_Status HalI2CInit8195a_Patch(IN VOID *Data);
HAL_Status HalI2CSendRtl8195a_Patch(IN VOID *Data);
HAL_Status HalI2CSetCLKRtl8195a_Patch(IN VOID *Data);
HAL_Status HalI2CMassSendRtl8195a_Patch(IN VOID *Data);
HAL_Status HalI2CEnableRtl8195a_Patch(IN VOID *Data);
#endif

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USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2s.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_I2S_H_
#define _RTL8195A_I2S_H_
//=============== Register Bit Field Definition ====================
// REG_I2S_CONTROL
#define BIT_CTLX_I2S_EN BIT(0)
#define BIT_SHIFT_CTLX_I2S_EN 0
#define BIT_MASK_CTLX_I2S_EN 0x1
#define BIT_CTRL_CTLX_I2S_EN(x) (((x) & BIT_MASK_CTLX_I2S_EN) << BIT_SHIFT_CTLX_I2S_EN)
#define BIT_SHIFT_CTLX_I2S_TRX_ACT 1
#define BIT_MASK_CTLX_I2S_TRX_ACT 0x3
#define BIT_CTRL_CTLX_I2S_TRX_ACT(x) (((x) & BIT_MASK_CTLX_I2S_TRX_ACT) << BIT_SHIFT_CTLX_I2S_TRX_ACT)
#define BIT_GET_CTLX_I2S_TRX_ACT(x) (((x) >> BIT_SHIFT_CTLX_I2S_TRX_ACT) & BIT_MASK_CTLX_I2S_TRX_ACT)
#define BIT_SHIFT_CTLX_I2S_CH_NUM 3
#define BIT_MASK_CTLX_I2S_CH_NUM 0x3
#define BIT_CTRL_CTLX_I2S_CH_NUM(x) (((x) & BIT_MASK_CTLX_I2S_CH_NUM) << BIT_SHIFT_CTLX_I2S_CH_NUM)
#define BIT_GET_CTLX_I2S_CH_NUM(x) (((x) >> BIT_SHIFT_CTLX_I2S_CH_NUM) & BIT_MASK_CTLX_I2S_CH_NUM)
//pvvx?
#define BIT_CTLX_I2S_EDGE_SW 5
#define BIT_MASK_CTLX_EDGE_SW 0x1
#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW)
#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW))
#define BIT_CTLX_I2S_WL BIT(6)
#define BIT_SHIFT_CTLX_I2S_WL 6
#define BIT_MASK_CTLX_I2S_WL 0x1
#define BIT_CTRL_CTLX_I2S_WL(x) (((x) & BIT_MASK_CTLX_I2S_WL) << BIT_SHIFT_CTLX_I2S_WL)
//pvvx?
#define BIT_CTLX_I2S_LOOP_BACK 7
#define BIT_MASK_CTLX_LOOP_BACK 0x1
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_CTLX_I2S_LOOP_BACK)
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_CTLX_I2S_LOOP_BACK))
//pvvx?
#define BIT_CTLX_I2S_FORMAT 8
#define BIT_MASK_CTLX_FORMAT 0x3
#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_CTLX_I2S_FORMAT)
#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_CTLX_I2S_FORMAT))
#define BIT_CTLX_I2S_LRSWAP BIT(10)
#define BIT_SHIFT_CTLX_I2S_LRSWAP 10
#define BIT_MASK_CTLX_I2S_LRSWAP 0x1
#define BIT_CTRL_CTLX_I2S_LRSWAP(x) (((x) & BIT_MASK_CTLX_I2S_LRSWAP) << BIT_SHIFT_CTLX_I2S_LRSWAP)
#define BIT_CTLX_I2S_SCK_INV BIT(11)
#define BIT_SHIFT_CTLX_I2S_SCK_INV 11
#define BIT_MASK_CTLX_I2S_SCK_INV 0x1
#define BIT_CTRL_CTLX_I2S_SCK_INV(x) (((x) & BIT_MASK_CTLX_I2S_SCK_INV) << BIT_SHIFT_CTLX_I2S_SCK_INV)
#define BIT_CTLX_I2S_ENDIAN_SWAP BIT(12)
#define BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP 12
#define BIT_MASK_CTLX_I2S_ENDIAN_SWAP 0x1
#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_I2S_ENDIAN_SWAP) << BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP)
#define BIT_CTLX_I2S_SLAVE_MODE BIT(29)
#define BIT_SHIFT_CTLX_I2S_SLAVE_MODE 29
#define BIT_MASK_CTLX_I2S_SLAVE_MODE 0x1
#define BIT_CTRL_CTLX_I2S_SLAVE_MODE(x) (((x) & BIT_MASK_CTLX_I2S_SLAVE_MODE) << BIT_SHIFT_CTLX_I2S_SLAVE_MODE)
#define BIT_CTLX_I2S_CLK_SRC BIT(30)
#define BIT_SHIFT_CTLX_I2S_CLK_SRC 30
#define BIT_MASK_CTLX_I2S_CLK_SRC 0x1
#define BIT_CTRL_CTLX_I2S_CLK_SRC(x) (((x) & BIT_MASK_CTLX_I2S_CLK_SRC) << BIT_SHIFT_CTLX_I2S_CLK_SRC)
#define BIT_CTLX_I2S_SW_RSTN BIT(31)
#define BIT_SHIFT_CTLX_I2S_SW_RSTN 31
#define BIT_MASK_CTLX_I2S_SW_RSTN 0x1
#define BIT_CTRL_CTLX_I2S_SW_RSTN(x) (((x) & BIT_MASK_CTLX_I2S_SW_RSTN) << BIT_SHIFT_CTLX_I2S_SW_RSTN)
// REG_I2S_SETTING
#define BIT_SHIFT_SETTING_I2S_PAGE_SZ 0
#define BIT_MASK_SETTING_I2S_PAGE_SZ 0xFFF
#define BIT_CTRL_SETTING_I2S_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_SZ) << BIT_SHIFT_SETTING_I2S_PAGE_SZ)
#define BIT_GET_SETTING_I2S_PAGE_SZ(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_SZ) & BIT_MASK_SETTING_I2S_PAGE_SZ)
#define BIT_SHIFT_SETTING_I2S_PAGE_NUM 12
#define BIT_MASK_SETTING_I2S_PAGE_NUM 0x3
#define BIT_CTRL_SETTING_I2S_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_NUM) << BIT_SHIFT_SETTING_I2S_PAGE_NUM)
#define BIT_GET_SETTING_I2S_PAGE_NUM(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_NUM) & BIT_MASK_SETTING_I2S_PAGE_NUM)
#define BIT_SHIFT_SETTING_I2S_SAMPLE_RATE 14
#define BIT_MASK_SETTING_I2S_SAMPLE_RATE 0x7
#define BIT_CTRL_SETTING_I2S_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE)
#define BIT_GET_SETTING_I2S_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) & BIT_MASK_SETTING_I2S_SAMPLE_RATE)
// i2s trx page own bit
#define BIT_PAGE_I2S_OWN_BIT BIT(31)
#define BIT_SHIFT_PAGE_I2S_OWN_BIT 31
#define BIT_MASK_PAGE_I2S_OWN_BIT 0x1
#define BIT_CTRL_PAGE_I2S_OWN_BIT(x) (((x) & BIT_MASK_PAGE_I2S_OWN_BIT) << BIT_SHIFT_PAGE_I2S_OWN_BIT)
//=============== Register Address Definition ====================
#define REG_I2S_PAGE_OWN_OFF 0x004
#define REG_I2S_CTL 0x000
#define REG_I2S_TX_PAGE_PTR 0x004
#define REG_I2S_RX_PAGE_PTR 0x008
#define REG_I2S_SETTING 0x00C
#define REG_I2S_TX_MASK_INT 0x010
#define REG_I2S_TX_STATUS_INT 0x014
#define REG_I2S_RX_MASK_INT 0x018
#define REG_I2S_RX_STATUS_INT 0x01c
#define REG_I2S_TX_PAGE0_OWN 0x020
#define REG_I2S_TX_PAGE1_OWN 0x024
#define REG_I2S_TX_PAGE2_OWN 0x028
#define REG_I2S_TX_PAGE3_OWN 0x02C
#define REG_I2S_RX_PAGE0_OWN 0x030
#define REG_I2S_RX_PAGE1_OWN 0x034
#define REG_I2S_RX_PAGE2_OWN 0x038
#define REG_I2S_RX_PAGE3_OWN 0x03C
/*I2S Essential Functions and Macros*/
VOID
HalI2SWrite32(
IN u8 I2SIdx,
IN u8 I2SReg,
IN u32 I2SVal
);
u32
HalI2SRead32(
IN u8 I2SIdx,
IN u8 I2SReg
);
/*
#define HAL_I2SX_READ32(I2sIndex, addr) \
HAL_READ32(I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF), addr)
#define HAL_I2SX_WRITE32(I2sIndex, addr, value) \
HAL_WRITE32((I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF)), addr, value)
*/
#define HAL_I2S_WRITE32(I2SIdx, addr, value) HalI2SWrite32(I2SIdx,addr,value)
#define HAL_I2S_READ32(I2SIdx, addr) HalI2SRead32(I2SIdx,addr)
/* I2S debug output*/
#define I2S_PREFIX "RTL8195A[i2s]: "
#define I2S_PREFIX_LVL " [i2s_DBG]: "
typedef enum _I2S_DBG_LVL_ {
HAL_I2S_LVL = 0x01,
SAL_I2S_LVL = 0x02,
VERI_I2S_LVL = 0x03,
}I2S_DBG_LVL,*PI2S_DBG_LVL;
#if CONFIG_DEBUG_LOG > 0
#ifdef CONFIG_DEBUG_LOG_I2S_HAL
#define DBG_8195A_I2S(...) do{ \
_DbgDump(I2S_PREFIX __VA_ARGS__);\
}while(0)
#define I2SDBGLVL 0xFF
#define DBG_8195A_I2S_LVL(LVL,...) do{\
if (LVL&I2SDBGLVL){\
_DbgDump(I2S_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_I2S_LOG_PERD 100
#define DBG_8195A_I2S(...)
#define DBG_8195A_I2S_LVL(...)
#endif
#else
#define DBG_I2S_LOG_PERD 100
#define DBG_8195A_I2S(...)
#define DBG_8195A_I2S_LVL(...)
#endif
/*
#define REG_I2S_PAGE_OWN_OFF 0x004
#define REG_I2S_CTL 0x000
#define REG_I2S_TX_PAGE_PTR 0x004
#define REG_I2S_RX_PAGE_PTR 0x008
#define REG_I2S_SETTING 0x00C
#define REG_I2S_TX_MASK_INT 0x010
#define REG_I2S_TX_STATUS_INT 0x014
#define REG_I2S_RX_MASK_INT 0x018
#define REG_I2S_RX_STATUS_INT 0x01c
#define REG_I2S_TX_PAGE0_OWN 0x020
#define REG_I2S_TX_PAGE1_OWN 0x024
#define REG_I2S_TX_PAGE2_OWN 0x028
#define REG_I2S_TX_PAGE3_OWN 0x02C
#define REG_I2S_RX_PAGE0_OWN 0x030
#define REG_I2S_RX_PAGE1_OWN 0x034
#define REG_I2S_RX_PAGE2_OWN 0x038
#define REG_I2S_RX_PAGE3_OWN 0x03C
*/
/* template
#define BIT_SHIFT_CTLX_ 7
#define BIT_MASK_CTLX_ 0x1
#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
*//*
#define BIT_SHIFT_CTLX_IIS_EN 0
#define BIT_MASK_CTLX_IIS_EN 0x1
#define BIT_CTLX_IIS_EN(x) (((x) & BIT_MASK_CTLX_IIS_EN) << BIT_SHIFT_CTLX_IIS_EN)
#define BIT_INV_CTLX_IIS_EN (~(BIT_MASK_CTLX_IIS_EN << BIT_SHIFT_CTLX_IIS_EN))
#define BIT_SHIFT_CTLX_TRX 1
#define BIT_MASK_CTLX_TRX 0x3
#define BIT_CTLX_TRX(x) (((x) & BIT_MASK_CTLX_TRX) << BIT_SHIFT_CTLX_TRX)
#define BIT_INV_CTLX_TRX (~(BIT_MASK_CTLX_TRX << BIT_SHIFT_CTLX_TRX))
#define BIT_SHIFT_CTLX_CH_NUM 3
#define BIT_MASK_CTLX_CH_NUM 0x3
#define BIT_CTLX_CH_NUM(x) (((x) & BIT_MASK_CTLX_CH_NUM) << BIT_SHIFT_CTLX_CH_NUM)
#define BIT_INV_CTLX_CH_NUM (~(BIT_MASK_CTLX_CH_NUM << BIT_SHIFT_CTLX_CH_NUM))
#define BIT_SHIFT_CTLX_EDGE_SW 5
#define BIT_MASK_CTLX_EDGE_SW 0x1
#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW)
#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW))
#define BIT_SHIFT_CTLX_WL 6
#define BIT_MASK_CTLX_WL 0x1
#define BIT_CTLX_WL(x) (((x) & BIT_MASK_CTLX_WL) << BIT_SHIFT_CTLX_WL)
#define BIT_INV_CTLX_WL (~(BIT_MASK_CTLX_WL << BIT_SHIFT_CTLX_WL))
#define BIT_SHIFT_CTLX_LOOP_BACK 7
#define BIT_MASK_CTLX_LOOP_BACK 0x1
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
#define BIT_SHIFT_CTLX_FORMAT 8
#define BIT_MASK_CTLX_FORMAT 0x3
#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_SHIFT_CTLX_FORMAT)
#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_SHIFT_CTLX_FORMAT))
#define BIT_SHIFT_CTLX_LRSWAP 10
#define BIT_MASK_CTLX_LRSWAP 0x1
#define BIT_CTLX_LRSWAP(x) (((x) & BIT_MASK_CTLX_LRSWAP) << BIT_SHIFT_CTLX_LRSWAP)
#define BIT_INV_CTLX_LRSWAP (~(BIT_MASK_CTLX_LRSWAP << BIT_SHIFT_CTLX_LRSWAP))
#define BIT_SHIFT_CTLX_SCK_INV 11
#define BIT_MASK_CTLX_SCK_INV 0x1
#define BIT_CTLX_SCK_INV(x) (((x) & BIT_MASK_CTLX_SCK_INV) << BIT_SHIFT_CTLX_SCK_INV)
#define BIT_INV_CTLX_SCK_INV (~(BIT_MASK_CTLX_SCK_INV << BIT_SHIFT_CTLX_SCK_INV))
#define BIT_SHIFT_CTLX_ENDIAN_SWAP 12
#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1
#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
#define BIT_SHIFT_CTLX_DEBUG_SWITCH 15
#define BIT_MASK_CTLX_DEBUG_SWITCH 0x3
#define BIT_CTLX_DEBUG_SWITCH(x) (((x) & BIT_MASK_CTLX_DEBUG_SWITCH) << BIT_SHIFT_CTLX_DEBUG_SWITCH)
#define BIT_INV_CTLX_DEBUG_SWITCH (~(BIT_MASK_CTLX_DEBUG_SWITCH << BIT_SHIFT_CTLX_DEBUG_SWITCH))
#define BIT_SHIFT_CTLX_SLAVE_SEL 29
#define BIT_MASK_CTLX_SLAVE_SEL 0x1
#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
#define BIT_SHIFT_CTLX_CLK_SRC 30
#define BIT_MASK_CTLX_CLK_SRC 0x1
#define BIT_CTLX_CLK_SRC(x) (((x) & BIT_MASK_CTLX_CLK_SRC) << BIT_SHIFT_CTLX_CLK_SRC)
#define BIT_INV_CTLX_CLK_SRC (~(BIT_MASK_CTLX_CLK_SRC << BIT_SHIFT_CTLX_CLK_SRC))
#define BIT_SHIFT_CTLX_SW_RSTN 31
#define BIT_MASK_CTLX_SW_RSTN 0x1
#define BIT_CTLX_SW_RSTN(x) (((x) & BIT_MASK_CTLX_SW_RSTN) << BIT_SHIFT_CTLX_SW_RSTN)
#define BIT_INV_CTLX_SW_RSTN (~(BIT_MASK_CTLX_SW_RSTN << BIT_SHIFT_CTLX_SW_RSTN))
#define BIT_SHIFT_SETTING_PAGE_SZ 0
#define BIT_MASK_SETTING_PAGE_SZ 0xFFF
#define BIT_SETTING_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_PAGE_SZ) << BIT_SHIFT_SETTING_PAGE_SZ)
#define BIT_INV_SETTING_PAGE_SZ (~(BIT_MASK_SETTING_PAGE_SZ << BIT_SHIFT_SETTING_PAGE_SZ))
#define BIT_SHIFT_SETTING_PAGE_NUM 12
#define BIT_MASK_SETTING_PAGE_NUM 0x3
#define BIT_SETTING_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_PAGE_NUM) << BIT_SHIFT_SETTING_PAGE_NUM)
#define BIT_INV_SETTING_PAGE_NUM (~(BIT_MASK_SETTING_PAGE_NUM << BIT_SHIFT_SETTING_PAGE_NUM))
#define BIT_SHIFT_SETTING_SAMPLE_RATE 14
#define BIT_MASK_SETTING_SAMPLE_RATE 0x7
#define BIT_SETTING_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_SAMPLE_RATE) << BIT_SHIFT_SETTING_SAMPLE_RATE)
#define BIT_INV_SETTING_SAMPLE_RATE (~(BIT_MASK_SETTING_SAMPLE_RATE << BIT_SHIFT_SETTING_SAMPLE_RATE))
*/
typedef enum _I2S_CTL_FORMAT {
FormatI2s = 0x00,
FormatLeftJustified = 0x01,
FormatRightJustified = 0x02
}I2S_CTL_FORMAT, *PI2S_CTL_FORMAT;
typedef enum _I2S_CTL_CHNUM {
ChannelStereo = 0x00,
Channel5p1 = 0x01,
ChannelMono = 0x02
}I2S_CTL_CHNUM, *PI2S_CTL_CHNUM;
typedef enum _I2S_CTL_TRX_ACT {
RxOnly = 0x00,
TxOnly = 0x01,
TXRX = 0x02
}I2S_CTL_TRX_ACT, *PI2S_CTL_TRX_ACT;
/*
typedef struct _I2S_CTL_REG_ {
I2S_CTL_FORMAT Format;
I2S_CTL_CHNUM ChNum;
I2S_CTL_TRX_ACT TrxAct;
u32 I2s_En :1; // Bit 0
u32 Rsvd1to4 :4; // Bit 1-4 is TrxAct, ChNum
u32 EdgeSw :1; // Bit 5 Edge switch
u32 WordLength :1; // Bit 6
u32 LoopBack :1; // Bit 7
u32 Rsvd8to9 :2; // Bit 8-9 is Format
u32 DacLrSwap :1; // Bit 10
u32 SckInv :1; // Bit 11
u32 EndianSwap :1; // Bit 12
u32 Rsvd13to14 :2; // Bit 11-14
u32 DebugSwitch :2; // Bit 15-16
u32 Rsvd17to28 :12; // Bit 17-28
u32 SlaveMode :1; // Bit 29
u32 SR44p1KHz :1; // Bit 30
u32 SwRstn :1; // Bit 31
} I2S_CTL_REG, *PI2S_CTL_REG;
*/
typedef enum _I2S_SETTING_PAGE_NUM {
I2s1Page = 0x00,
I2s2Page = 0x01,
I2s3Page = 0x02,
I2s4Page = 0x03
}I2S_SETTING_PAGE_NUM, *PI2S_SETTING_PAGE_NUM;
//sampling rate
typedef enum _I2S_SETTING_SR {
I2sSR8K = 0x00,
I2sSR16K = 0x01,
I2sSR24K = 0x02,
I2sSR32K = 0x03,
I2sSR48K = 0x05,
I2sSR44p1K = 0x15,
I2sSR96K = 0x06,
I2sSR88p2K = 0x16
}I2S_SETTING_SR, *PI2S_SETTING_SR;
/*
typedef struct _I2S_SETTING_REG_ {
I2S_SETTING_PAGE_NUM PageNum;
I2S_SETTING_SR SampleRate;
u32 PageSize:12; // Bit 0-11
}I2S_SETTING_REG, *PI2S_SETTING_REG;
typedef enum _I2S_TX_ISR {
I2sTxP0OK = 0x01,
I2sTxP1OK = 0x02,
I2sTxP2OK = 0x04,
I2sTxP3OK = 0x08,
I2sTxPageUn = 0x10,
I2sTxFifoEmpty = 0x20
}I2S_TX_ISR, *PI2S_TX_ISR;
typedef enum _I2S_RX_ISR {
I2sRxP0OK = 0x01,
I2sRxP1OK = 0x02,
I2sRxP2OK = 0x04,
I2sRxP3OK = 0x08,
I2sRxPageUn = 0x10,
I2sRxFifoFull = 0x20
}I2S_RX_ISR, *PI2S_RX_ISR;
*/
/* Hal I2S function prototype*/
RTK_STATUS
HalI2SInitRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SInitRtl8195a_Patch(
IN VOID *Data
);
RTK_STATUS
HalI2SDeInitRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2STxRtl8195a(
IN VOID *Data,
IN u8 *pBuff
);
RTK_STATUS
HalI2SRxRtl8195a(
IN VOID *Data,
OUT u8 *pBuff
);
RTK_STATUS
HalI2SEnableRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SIntrCtrlRtl8195a(
IN VOID *Data
);
u32
HalI2SReadRegRtl8195a(
IN VOID *Data,
IN u8 I2SReg
);
RTK_STATUS
HalI2SSetRateRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetWordLenRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetChNumRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetPageNumRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetPageSizeRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetDirectionRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SSetDMABufRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SClrIntrRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SClrAllIntrRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SDMACtrlRtl8195a(
IN VOID *Data
);
u8
HalI2SGetTxPageRtl8195a(
IN VOID *Data
);
u8
HalI2SGetRxPageRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SPageSendRtl8195a(
IN VOID *Data,
IN u8 PageIdx
);
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data
);
RTK_STATUS
HalI2SClearAllOwnBitRtl8195a(
IN VOID *Data
);
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ RTK_STATUS
HalI2SInitRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ RTK_STATUS
HalI2SSetRateRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ RTK_STATUS
HalI2SSetWordLenRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ RTK_STATUS
HalI2SSetChNumRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ RTK_STATUS
HalI2SSetPageNumRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ RTK_STATUS
HalI2SSetPageSizeRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ RTK_STATUS
HalI2SSetDirectionRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ RTK_STATUS
HalI2SSetDMABufRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u8
HalI2SGetTxPageRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u8
HalI2SGetRxPageRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ RTK_STATUS
HalI2SPageSendRtl8195a_V04(
IN VOID *Data,
IN u8 PageIdx
);
_LONG_CALL_ RTK_STATUS
HalI2SPageRecvRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ RTK_STATUS
HalI2SClearAllOwnBitRtl8195a_V04(
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
// HAL functions Wrapper
static __inline VOID
HalI2SSetRate(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
HalI2SSetRateRtl8195a(Data);
#else
HalI2SSetRateRtl8195a_V04(Data);
#endif
}
static __inline VOID
HalI2SSetWordLen(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
HalI2SSetWordLenRtl8195a(Data);
#else
HalI2SSetWordLenRtl8195a_V04(Data);
#endif
}
static __inline VOID
HalI2SSetChNum(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
HalI2SSetChNumRtl8195a(Data);
#else
HalI2SSetChNumRtl8195a_V04(Data);
#endif
}
static __inline VOID
HalI2SSetPageNum(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
HalI2SSetPageNumRtl8195a(Data);
#else
HalI2SSetPageNumRtl8195a_V04(Data);
#endif
}
static __inline VOID
HalI2SSetPageSize(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
HalI2SSetPageSizeRtl8195a(Data);
#else
HalI2SSetPageSizeRtl8195a_V04(Data);
#endif
}
static __inline VOID
HalI2SSetDirection(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
HalI2SSetDirectionRtl8195a(Data);
#else
HalI2SSetDirectionRtl8195a_V04(Data);
#endif
}
static __inline VOID
HalI2SSetDMABuf(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
HalI2SSetDMABufRtl8195a(Data);
#else
HalI2SSetDMABufRtl8195a_V04(Data);
#endif
}
static __inline u8
HalI2SGetTxPage(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
return HalI2SGetTxPageRtl8195a(Data);
#else
return HalI2SGetTxPageRtl8195a_V04(Data);
#endif
}
static __inline u8
HalI2SGetRxPage(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
return HalI2SGetRxPageRtl8195a(Data);
#else
return HalI2SGetRxPageRtl8195a_V04(Data);
#endif
}
static __inline VOID
HalI2SPageSend(
IN VOID *Data,
IN u8 PageIdx
)
{
#ifndef CONFIG_CHIP_E_CUT
HalI2SPageSendRtl8195a(Data, PageIdx);
#else
HalI2SPageSendRtl8195a_V04(Data, PageIdx);
#endif
}
static __inline VOID
HalI2SPageRecv(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
HalI2SPageRecvRtl8195a(Data);
#else
HalI2SPageRecvRtl8195a_V04(Data);
#endif
}
static __inline VOID
HalI2SClearAllOwnBit(
IN VOID *Data
)
{
#ifndef CONFIG_CHIP_E_CUT
HalI2SClearAllOwnBitRtl8195a(Data);
#else
HalI2SClearAllOwnBitRtl8195a_V04(Data);
#endif
}
#endif /* _RTL8195A_I2S_H_ */

675
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_mii.h Normal file
View file

@ -0,0 +1,675 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_MII_H_
#define _RTL8195A_MII_H_
#include "basic_types.h"
#include "hal_api.h"
#define MII_TX_DESC_NO 8
#define MII_RX_DESC_NO 8
#define MII_BUF_SIZE 1536
#define MAX_FRAME_SIZE 1514
#define HAL_MII_READ32(addr) HAL_READ32(MII_REG_BASE, addr)
#define HAL_MII_WRITE32(addr, value) HAL_WRITE32(MII_REG_BASE, addr, value)
#define HAL_MII_READ16(addr) HAL_READ16(MII_REG_BASE, addr)
#define HAL_MII_WRITE16(addr, value) HAL_WRITE16(MII_REG_BASE, addr, value)
#define HAL_MII_READ8(addr) HAL_READ8(MII_REG_BASE, addr)
#define HAL_MII_WRITE8(addr, value) HAL_WRITE8(MII_REG_BASE, addr, value)
/* =============== MAC Register Offset Definition =============== */
#define REG_MII_IDR0 0x0000
#define REG_MII_IDR4 0x0004
#define REG_MII_COM 0x0038
#define REG_MII_ISRIMR 0x003C
#define REG_MII_TC 0x0040
#define REG_MII_RC 0x0044
#define REG_MII_MS 0x0058
#define REG_MII_MIIA 0x005C
#define REG_MII_TXFDP1 0x1300
#define REG_MII_RXFDP1 0x13F0
#define REG_MII_ETNRXCPU1 0x1430
#define REG_MII_IOCMD 0x1434
#define REG_MII_IOCMD1 0x1438
/* =============== MAC Register BIT Definition =============== */
/* Command Register (0x38) */
#define COM_RST BIT0
#define COM_RXCHKSUM BIT1
#define COM_RXJUMBO BIT3
/* Interrupt Status & Interrupt Mask Register (0x3C & 0x3E) */
#define ISR_RXOK BIT0
#define ISR_RER_RUNT BIT2
#define ISR_RER_OVF BIT4
#define ISR_RDU BIT5
#define ISR_TXOK BIT6
#define ISR_TER BIT7
#define ISR_LINKCHG BIT8
#define ISR_TDU BIT9
#define ISR_CLR_ALL 0x0000FFFF
#define IMR_RXOK BIT16
#define IMR_RER_RUNT BIT18
#define IMR_RER_OVF BIT20
#define IMR_RDU BIT21
#define IMR_TXOK BIT22
#define IMR_TER BIT23
#define IMR_LINKCHG BIT24
#define IMR_TDU BIT25
/* Transmit Configuration Register (0x40) */
#define TC_TX_NOPADDING BIT0
#define TC_NORMAL_MODE 0
#define TC_LBK_R2T 1
#define TC_LBK_T2R 3
#define TC_LBK_MASK 0x00000300 // bit[9:8]
#define TC_IFG_TIME 3 // 9.6 us for 10Mbps, 960 ns for 100Mbps
#define TC_IFG_MASK 0x00001C00 // bit[12:10]
/* Receive Configuration Register (0x44) */
#define RC_AAP BIT0
#define RC_APM BIT1
#define RC_AM BIT2
#define RC_AB BIT3
#define RC_AR BIT4
#define RC_AER BIT5
/* Media Status Register (0x58) */
#define MS_LINKB BIT26
/* MII Access Register (0x5C) */
#define MIIA_FLAG BIT31 // 1: Write, 0: Read
#define MIIA_PHY_ADDR_MASK 0x7C000000 // bit[30:26]
#define MIIA_PHY_REG_ADDR_MASK 0x001F0000 // bit[20:16]
/* IO Command Register (0x1434) */
#define IOCMD_TXFN1ST BIT0
#define IOCMD_TE BIT4
#define IOCMD_RE BIT5
#define IOCMD_RXFTH_1024 0
#define IOCMD_RXFTH_128 1
#define IOCMD_RXFTH_256 2
#define IOCMD_RXFTH_512 3
#define IOCMD_RXFTH_MASK 0x00001800 // bit[12:11]
#define IOCMD_TXFTH_128 0
#define IOCMD_TXFTH_256 1
#define IOCMD_TXFTH_512 2
#define IOCMD_TXFTH_1024 3
#define IOCMD_TXFTH_MASK 0x00180000 // bit[20:19]
#define IOCMD_SHORT_DES_FMT BIT30
/* IO Command1 Register (0x1438) */
#define IOCMD1_RXRING1 BIT16
#define IOCMD1_EN_1GB BIT24
#define IOCMD1_DSC_FMT_EXTRA 0x3 // 011
#define IOCMD1_DSCFMTEXTRA_MASK 0x70000000 // bit[30:28]
/* =============== PHY (RTL8201F) Register Bit Definition =============== */
#define PHY_ADDRESS 0x1 // 5 bits
#define PHY_REG0_ADDR 0x0 // 5 bits
#define PHY_REG1_ADDR 0x1 // 5 bits
/* Register 0 */
#define PHY_SPEED_MSB BIT6
#define PHY_DUPLEX_MODE BIT8
#define PHY_RESTART_NWAY BIT9
#define PHY_NWAY_EN BIT12
#define PHY_SPEED_LSB BIT13
#define PHY_SW_RESET BIT15
/* Register 1 */
#define PHY_LINK_STATUS BIT2
#define PHY_NWAY_COMPLETE BIT5
/* =============== Tx/Rx Descriptor Bit Definition =============== */
#define TX_DESC_OWN BIT31
#define TX_DESC_EOR BIT30
#define TX_DESC_FS BIT29
#define TX_DESC_LS BIT28
#define TX_DESC_CRC BIT23
#define TX_DESC_DATA_LEN_MASK 0x1FFFF // bit[16:0]
#define TX_DESC_VLAN_INTACT 0
#define TX_DESC_VLAN_INSERT 1
#define TX_DESC_VLAN_REMOVE 2
#define TX_DESC_VLAN_REMARKING 3
#define TX_DESC_VLAN_ACT_MASK 0x06000000
#define C_VLAN_HDR 0x8100279F
#define S_VLAN_HDR 0x88A8279F
#define TX_DESC_VLAN_TAG_MASK 0x0000FFFF
#define RX_DESC_OWN BIT31
#define RX_DESC_EOR BIT30
#define RX_DESC_PKT_TYPE_MASK 0x001E0000 // bit[20:17]
#define RX_DESC_DATA_LEN_MASK 0xFFF // bit[11:0]
typedef struct _TX_DESC_FMT_
{
u32 dw1; // offset 0
u32 addr; // offset 4
u32 dw2; // offset 8
u32 dw3; // offset 12
u32 dw4; // offset 16
}TX_DESC_FMT, *PTX_DESC_FMT;
typedef struct _RX_DESC_FMT_
{
u32 dw1; // offset 0
u32 addr; // offset 4
u32 dw2; // offset 8
u32 dw3; // offset 12
}RX_DESC_FMT, *PRX_DESC_FMT;
VOID
HalMiiInitIrqRtl8195a(
IN VOID *Data
);
s32
HalMiiInitRtl8195a(
IN VOID
);
VOID
HalMiiDeInitRtl8195a(
IN VOID
);
s32
HalMiiWriteDataRtl8195a(
IN const char *Data,
IN u32 Size
);
u32
HalMiiSendPacketRtl8195a(
IN VOID
);
u32
HalMiiReceivePacketRtl8195a(
IN VOID
);
u32
HalMiiReadDataRtl8195a(
IN u8 *Data,
IN u32 Size
);
VOID
HalMiiGetMacAddressRtl8195a(
IN u8 *Addr
);
u32
HalMiiGetLinkStatusRtl8195a(
IN VOID
);
VOID
HalMiiForceLinkRtl8195a(
IN s32 Speed,
IN s32 Duplex
);
#ifdef CONFIG_MII_VERIFY
/* Ethernet Module registers */
#define REG_RTL_MII_IDR0 0x0000 // Table 2 IDR0 (Offset 0000h-0003h, R/W)
#define REG_RTL_MII_IDR4 0x0004 // Table 3 IDR4 (Offset 0004h-0007h, R/W)
#define REG_RTL_MII_MAR0 0x0008 // Table 4 MAR0 (Offset 0008h-000bh, R/W)
#define REG_RTL_MII_MAR4 0x000C // Table 5 MAR4 (Offset 000ch-000fh, R/W)
#define REG_RTL_MII_CR 0x0038 // Table 21 Command Register (COM_REG, Offset 0038-003Bh, R/W)
#define REG_RTL_MII_IMRISR 0x003C // Table 22 + Table 23
#define REG_RTL_MII_TCR 0x0040 // Table 24 Transmit Configuration Register (TC_REG, Offset 0040h-0043h, R/W)
#define REG_RTL_MII_RCR 0x0044 // Table 25 Receive Configuration Register (RC_REG, Offset 0044h-0047h, R/W)
#define REG_RTL_MII_CTCR 0x0048 // Table 26 CPU Tag Control Register (CPUTAG_REG, Offset 0048h-004bh, R/W)
#define REG_RTL_MII_CONFIG 0x004C // Table 27 Configuration Register (CONFIG_REG, Offset 004ch-004fh, R/W)
#define REG_RTL_MII_CTCR1 0x0050 // Table 28 CPUTAG1 Register (CPUTAG1_REG, Offset 0050h-0053h, R/W)
#define REG_RTL_MII_MSR 0x0058 // Table 29 Media Status Register (MS_reg: Offset 0058h ??005bh, R/W)
#define REG_RTL_MII_MIIAR 0x005C // Table 30 MII Access Register (MIIA_REG, Offset 005c-005fh, R/W)
#define REG_RTL_MII_VR 0x0064 // Table 32 VLAN Register (VLAN_REG, Offset 0064-0067h, R/W)
#define REG_RTL_MII_IMR0 0x00D0 // Table 50 IMR0_REG (IMR0_REG, Offset D0h-D3h)
#define REG_RTL_MII_IMR1 0x00D4 // Table 51 IMR1_REG (IMR1_REG, Offset d4h-d7h)
#define REG_RTL_MII_ISR1 0x00D8 // Table 52 ISR1 Register (ISR1_REG, Offset D8h-DBh)
#define REG_RTL_MII_INTR 0x00DC // Table 53 Interrupt routing register (INTR_REG, Offset DCh-DFh)
#define REG_RTL_MII_CCR 0x00E4 // Table xx Clock Control Register (CLKCTL_REG, Offset E4h-E7h)
/* CPU Interface registers */
#define REG_RTL_MII_TXFDP1 0x1300 // Table 55 TxFDP1 register (TXFDP1_REG, offset 1300h-1303h)
#define REG_RTL_MII_TXCDO1 0x1304 // Table 56 TxCDO1 register (TXCDO1_REG, offset 1304h-1305h)
#define REG_RTL_MII_TXFDP2 0x1310 // Table 57 TxFDP2 register (TXFDP2_REG, offset 1310h-1313h)
#define REG_RTL_MII_TXCDO2 0x1314 // Table 58 TxCDO2 register (TXCDO2_REG, offset 1314h-1315h)
#define REG_RTL_MII_TXFDP3 0x1320 // Table 59 TxFDP3 register (TXFDP3_REG, offset 1320h-1323h)
#define REG_RTL_MII_TXCDO3 0x1324 // Table 60 TxCDO3 register (TXCDO3_REG, offset 1324h-1325h)
#define REG_RTL_MII_TXFDP4 0x1330 // Table 61 TxFDP4 register (TXFDP4_REG, offset 1330h-1333h)
#define REG_RTL_MII_TXCDO4 0x1334 // Table 62 TxCDO4 register (TXCDO4_REG, offset 1334h-1335h)
#define REG_RTL_MII_TXFDP5 0x1340 // Table 63 TxFDP5 register (TXFDP5_REG, offset 1340h-1343h)
#define REG_RTL_MII_TXCDO5 0x1344 // Table 64 TxCDO5 register (TXCDO5_REG, offset 1344h-1345h)
#define REG_RTL_MII_RXFDP2 0x1390 // Table 66 RxFDP2 register (RXFDP#_REG, offset 1390h-1393h)
#define REG_RTL_MII_RXFDP1 0x13F0 // Table 71 RxFDP1 register (RXFDP1_REG, offset 13F0h-13F3h)
#define REG_RTL_MII_RXRS1 0x13F6 // Table 73 Rx Ring Size1 register (RX_RS1_REG, offset 13F6h-13F7h)
#define REG_RTL_MII_RX_PSE1 0x142C // Table 77 Rx_Pse_Des_Thres_1_h (RX_PSE1_REG, Offset 142ch)
#define REG_RTL_MII_ETNRXCPU1 0x1430 // Table 79 EhtrntRxCPU_Des_Num1 (ETNRXCPU1_REG, Offset 1430h-1433h)
#define REG_RTL_MII_IOCMD 0x1434 // Table 80 Ethernet_IO_CMD (ETN_IO_CMD_REG, Offset 1434h-1437h)
#define REG_RTL_MII_IOCMD1 0x1438 // Table 81 Ethernet_IO_CMD1 (IO_CMD1_REG: Offset 1438h-143bh)
#define CMD_CONFIG 0x00081000
//2014-04-29 yclin (disable [27] r_en_precise_dma)
// #define CMD1_CONFIG 0x39000000
#define CMD1_CONFIG 0x31000000
// #define MAX_RX_DESC_SIZE 6
#define MAX_RX_DESC_SIZE 1
#define MAX_TX_DESC_SIZE 5
// 0058h
#define BIT_SHIFT_MSR_FORCE_SPEED_SELECT 16
#define BIT_MASK_MSR_FORCE_SPEED_SELECT 0x3
#define BIT_MSR_FORCE_SPEED_SELECT(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_SELECT) << BIT_SHIFT_MSR_FORCE_SPEED_SELECT)
#define BIT_INVC_MSR_FORCE_SPEED_SELECT (~(BIT_MASK_MSR_FORCE_SPEED_SELECT << BIT_SHIFT_MSR_FORCE_SPEED_SELECT))
#define BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE 10
#define BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE 0x1
#define BIT_MSR_FORCE_SPEED_MODE_ENABLE(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE) << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE)
#define BIT_INVC_MSR_FORCE_SPEED_MODE_ENABLE (~(BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE))
// 1434h
#define BIT_SHIFT_IOCMD_RXENABLE 5
#define BIT_MASK_IOCMD_RXENABLE 0x1
#define BIT_IOCMD_RXENABLE(x)(((x) & BIT_MASK_IOCMD_RXENABLE) << BIT_SHIFT_IOCMD_RXENABLE)
#define BIT_INVC_IOCMD_RXENABLE (~(BIT_MASK_IOCMD_RXENABLE << BIT_SHIFT_IOCMD_RXENABLE))
#define BIT_SHIFT_IOCMD_TXENABLE 4
#define BIT_MASK_IOCMD_TXENABLE 0x1
#define BIT_IOCMD_TXENABLE(x)(((x) & BIT_MASK_IOCMD_TXENABLE) << BIT_SHIFT_IOCMD_TXENABLE)
#define BIT_INVC_IOCMD_TXENABLE (~(BIT_MASK_IOCMD_TXENABLE << BIT_SHIFT_IOCMD_TXENABLE))
#define BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE 0
#define BIT_MASK_IOCMD_FIRST_DMATX_ENABLE 0x1
#define BIT_IOCMD_FIRST_DMATX_ENABLE(x)(((x) & BIT_MASK_IOCMD_FIRST_DMATX_ENABLE) << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE)
#define BIT_INVC_IOCMD_FIRST_DMATX_ENABLE (~(BIT_MASK_IOCMD_FIRST_DMATX_ENABLE << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE))
// 1438h
#define BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE 16
#define BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE 0x1
#define BIT_IOCMD1_FIRST_DMARX_ENABLE(x)(((x) & BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE) << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE)
#define BIT_INVC_IOCMD1_FIRST_DMARX_ENABLE (~(BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE))
/**
* 1.4.1.7 Tx command descriptor used in RL6266
* 5 dobule words
*/
typedef struct _TX_INFO_ {
union {
struct {
u32 own:1; //31
u32 eor:1; //30
u32 fs:1; //29
u32 ls:1; //28
u32 ipcs:1; //27
u32 l4cs:1; //26
u32 keep:1; //25
u32 blu:1; //24
u32 crc:1; //23
u32 vsel:1; //22
u32 dislrn:1; //21
u32 cputag_ipcs:1; //20
u32 cputag_l4cs:1; //19
u32 cputag_psel:1; //18
u32 rsvd:1; //17
u32 data_length:17; //0~16
} bit;
u32 dw; //double word
} opts1;
u32 addr;
union {
struct {
u32 cputag:1; //31
u32 aspri:1; //30
u32 cputag_pri:3; //27~29
u32 tx_vlan_action:2; //25~26
u32 tx_pppoe_action:2; //23~24
u32 tx_pppoe_idx:3; //20~22
u32 efid:1; //19
u32 enhance_fid:3; //16~18
u32 vidl:8; // 8~15
u32 prio:3; // 5~7
u32 cfi:1; // 4
u32 vidh:4; // 0~3
} bit;
u32 dw; //double word
} opts2;
union {
struct {
u32 extspa:3; //29~31
u32 tx_portmask:6; //23~28
u32 tx_dst_stream_id:7; //16~22
u32 rsvd:14; // 2~15
u32 l34keep:1; // 1
u32 ptp:1; // 0
} bit;
u32 dw; //double word
} opts3;
union {
struct {
u32 lgsen:1; //31
u32 lgmss:11; //20~30
u32 rsvd:20; // 0~19
} bit;
u32 dw; //double word
} opts4;
} TX_INFO, *PTX_INFO;
typedef struct _RX_INFO_ {
union{
struct{
u32 own:1; //31
u32 eor:1; //30
u32 fs:1; //29
u32 ls:1; //28
u32 crcerr:1; //27
u32 ipv4csf:1; //26
u32 l4csf:1; //25
u32 rcdf:1; //24
u32 ipfrag:1; //23
u32 pppoetag:1; //22
u32 rwt:1; //21
u32 pkttype:4; //20-17
u32 l3routing:1; //16
u32 origformat:1; //15
u32 pctrl:1; //14
#ifdef CONFIG_RG_JUMBO_FRAME
u32 data_length:14; //13~0
#else
u32 rsvd:2; //13~12
u32 data_length:12; //11~0
#endif
}bit;
u32 dw; //double word
}opts1;
u32 addr;
union{
struct{
u32 cputag:1; //31
u32 ptp_in_cpu_tag_exist:1; //30
u32 svlan_tag_exist:1; //29
u32 rsvd_2:2; //27~28
u32 pon_stream_id:7; //20~26
u32 rsvd_1:3; //17~19
u32 ctagva:1; //16
u32 cvlan_tag:16; //15~0
}bit;
u32 dw; //double word
}opts2;
union{
struct{
u32 src_port_num:5; //27~31
u32 dst_port_mask:6; //21~26
u32 reason:8; //13~20
u32 internal_priority:3; //10~12
u32 ext_port_ttl_1:5; //5~9
u32 rsvd:5; //4~0
}bit;
u32 dw; //double word
}opts3;
} RX_INFO, *PRX_INFO;
/**
* GMAC_STATUS_REGS
*/
// TX/RX Descriptor Common
#define BIT_SHIFT_GMAC_DESCOWN 31
#define BIT_MASK_GMAC_DESCOWN 0x1
#define BIT_GMAC_DESCOWN(x)(((x) & BIT_MASK_GMAC_DESCOWN) << BIT_SHIFT_GMAC_DESCOWN)
#define BIT_INVC_GMAC_DESCOWN (~(BIT_MASK_GMAC_DESCOWN << BIT_SHIFT_GMAC_DESCOWN))
#define BIT_SHIFT_GMAC_RINGEND 30
#define BIT_MASK_GMAC_RINGEND 0x1
#define BIT_GMAC_RINGEND(x)(((x) & BIT_MASK_GMAC_RINGEND) << BIT_SHIFT_GMAC_RINGEND)
#define BIT_INVC_GMAC_RINGEND (~(BIT_MASK_GMAC_RINGEND << BIT_SHIFT_GMAC_RINGEND))
#define BIT_SHIFT_GMAC_FIRSTFRAG 29
#define BIT_MASK_GMAC_FIRSTFRAG 0x1
#define BIT_GMAC_FIRSTFRAG(x)(((x) & BIT_MASK_GMAC_FIRSTFRAG) << BIT_SHIFT_GMAC_FIRSTFRAG)
#define BIT_INVC_GMAC_FIRSTFRAG (~(BIT_MASK_GMAC_FIRSTFRAG << BIT_SHIFT_GMAC_FIRSTFRAG))
#define BIT_SHIFT_GMAC_LASTFRAG 28
#define BIT_MASK_GMAC_LASTFRAG 0x1
#define BIT_GMAC_LASTFRAG(x)(((x) & BIT_MASK_GMAC_LASTFRAG) << BIT_SHIFT_GMAC_LASTFRAG)
#define BIT_INVC_GMAC_LASTFRAG (~(BIT_MASK_GMAC_LASTFRAG << BIT_SHIFT_GMAC_LASTFRAG))
// TX Descriptor opts1
#define BIT_SHIFT_GMAC_IPCS 27
#define BIT_MASK_GMAC_IPCS 0x1
#define BIT_GMAC_IPCS(x)(((x) & BIT_MASK_GMAC_IPCS) << BIT_SHIFT_GMAC_IPCS)
#define BIT_INVC_GMAC_IPCS (~(BIT_MASK_GMAC_IPCS << BIT_SHIFT_GMAC_IPCS))
#define BIT_SHIFT_GMAC_L4CS 26
#define BIT_MASK_GMAC_L4CS 0x1
#define BIT_GMAC_L4CS(x)(((x) & BIT_MASK_GMAC_L4CS) << BIT_SHIFT_GMAC_L4CS)
#define BIT_INVC_GMAC_L4CS (~(BIT_MASK_GMAC_L4CS << BIT_SHIFT_GMAC_L4CS))
#define BIT_SHIFT_GMAC_KEEP 25
#define BIT_MASK_GMAC_KEEP 0x1
#define BIT_GMAC_KEEP(x)(((x) & BIT_MASK_GMAC_KEEP) << BIT_SHIFT_GMAC_KEEP)
#define BIT_INVC_GMAC_KEEP (~(BIT_MASK_GMAC_KEEP << BIT_SHIFT_GMAC_KEEP))
#define BIT_SHIFT_GMAC_BLU 24
#define BIT_MASK_GMAC_BLU 0x1
#define BIT_GMAC_BLU(x)(((x) & BIT_MASK_GMAC_BLU) << BIT_SHIFT_GMAC_BLU)
#define BIT_INVC_GMAC_BLU (~(BIT_MASK_GMAC_BLU << BIT_SHIFT_GMAC_BLU))
#define BIT_SHIFT_GMAC_TXCRC 23
#define BIT_MASK_GMAC_TXCRC 0x1
#define BIT_GMAC_TXCRC(x)(((x) & BIT_MASK_GMAC_TXCRC) << BIT_SHIFT_GMAC_TXCRC)
#define BIT_INVC_GMAC_TXCRC (~(BIT_MASK_GMAC_TXCRC << BIT_SHIFT_GMAC_TXCRC))
#define BIT_SHIFT_GMAC_VSEL 22
#define BIT_MASK_GMAC_VSEL 0x1
#define BIT_GMAC_VSEL(x)(((x) & BIT_MASK_GMAC_VSEL) << BIT_SHIFT_GMAC_VSEL)
#define BIT_INVC_GMAC_VSEL (~(BIT_MASK_GMAC_VSEL << BIT_SHIFT_GMAC_VSEL))
#define BIT_SHIFT_GMAC_DISLRN 21
#define BIT_MASK_GMAC_DISLRN 0x1
#define BIT_GMAC_DISLRN(x)(((x) & BIT_MASK_GMAC_DISLRN) << BIT_SHIFT_GMAC_DISLRN)
#define BIT_INVC_GMAC_DISLRN (~(BIT_MASK_GMAC_DISLRN << BIT_SHIFT_GMAC_DISLRN))
#define BIT_SHIFT_GMAC_CPUTAG_IPCS 20
#define BIT_MASK_GMAC_CPUTAG_IPCS 0x1
#define BIT_GMAC_CPUTAG_IPCS(x)(((x) & BIT_MASK_GMAC_CPUTAG_IPCS) << BIT_SHIFT_GMAC_CPUTAG_IPCS)
#define BIT_INVC_GMAC_CPUTAG_IPCS (~(BIT_MASK_GMAC_CPUTAG_IPCS << BIT_SHIFT_GMAC_CPUTAG_IPCS))
#define BIT_SHIFT_GMAC_CPUTAG_L4CS 19
#define BIT_MASK_GMAC_CPUTAG_L4CS 0x1
#define BIT_GMAC_CPUTAG_L4CS(x)(((x) & BIT_MASK_GMAC_CPUTAG_L4CS) << BIT_SHIFT_GMAC_CPUTAG_L4CS)
#define BIT_INVC_GMAC_CPUTAG_L4CS (~(BIT_MASK_GMAC_CPUTAG_L4CS << BIT_SHIFT_GMAC_CPUTAG_L4CS))
#define BIT_SHIFT_GMAC_CPUTAG_PSEL 18
#define BIT_MASK_GMAC_CPUTAG_PSEL 0x1
#define BIT_GMAC_CPUTAG_PSEL(x)(((x) & BIT_MASK_GMAC_CPUTAG_PSEL) << BIT_SHIFT_GMAC_CPUTAG_PSEL)
#define BIT_INVC_GMAC_CPUTAG_PSEL (~(BIT_MASK_GMAC_CPUTAG_PSEL << BIT_SHIFT_GMAC_CPUTAG_PSEL))
typedef struct _PHY_MODE_INFO_ {
u8 PhyAddress;
u8 PhyMode;
u8 PhyInterface;
} PHY_MODE_INFO, *PPHY_MODE_INFO;
typedef enum _PHY_MODE_SWITCH_ {
PHY_MODE_DISABLE = 0,
PHY_MODE_ENABLE = 1
} PHY_MODE_SWITCH, *PPHY_MODE_SWITCH;
typedef enum _PHY_INTERFACE_SELECT_ {
PHY_INTERFACE_ONE_WORKS = 0,
PHY_INTERFACE_ZERO_WORKS = 1
} PHY_INTERFACE_SELECT, *PPHY_INTERFACE_SELECT;
typedef enum _GMAC_MSR_FORCE_SPEED_ {
FORCE_SPD_100M = 0,
FORCE_SPD_10M = 1,
FORCE_SPD_GIGA = 2,
NO_FORCE_SPD = 3
}GMAC_MSR_FORCE_SPEED, *PGMAC_MSR_FORCE_SPEED;
typedef enum _GMAC_INTERRUPT_MASK_ {
GMAC_IMR_ROK = BIT16,
GMAC_IMR_CNT_WRAP = BIT17,
GMAC_IMR_RER_RUNT = BIT18,
// BIT19 Reserved
GMAC_IMR_RER_OVF = BIT20,
GMAC_IMR_RDU = BIT21,
GMAC_IMR_TOK_TI = BIT22,
GMAC_IMR_TER = BIT23,
GMAC_IMR_LINKCHG = BIT24,
GMAC_IMR_TDU = BIT25,
GMAC_IMR_SWINT = BIT26,
GMAC_IMR_RDU2 = BIT27,
GMAC_IMR_RDU3 = BIT28,
GMAC_IMR_RDU4 = BIT29,
GMAC_IMR_RDU5 = BIT30,
GMAC_IMR_RDU6 = BIT31,
} GMAC_INTERRUPT_MASK, *PGMAC_INTERRUPT_MASK;
typedef enum _GMAC_INTERRUPT_STATUS_ {
GMAC_ISR_ROK = BIT0,
GMAC_ISR_CNT_WRAP = BIT1,
GMAC_ISR_RER_RUNT = BIT2,
// BIT3 Reserved
GMAC_ISR_RER_OVF = BIT4,
GMAC_ISR_RDU = BIT5,
GMAC_ISR_TOK_TI = BIT6,
GMAC_ISR_TER = BIT7,
GMAC_ISR_LINKCHG = BIT8,
GMAC_ISR_TDU = BIT9,
GMAC_ISR_SWINT = BIT10,
GMAC_ISR_RDU2 = BIT11,
GMAC_ISR_RDU3 = BIT12,
GMAC_ISR_RDU4 = BIT13,
GMAC_ISR_RDU5 = BIT14,
GMAC_ISR_RDU6 = BIT15,
} GMAC_INTERRUPT_STATUS, *PGMAC_INTERRUPT_STATUS;
typedef enum _GMAC_TX_VLAN_ACTION_ {
INTACT = 0,
INSERT_VLAN_HDR = 1,
REMOVE_VLAN_HDR = 2,
REMARKING_VID = 3
}GMAC_TX_VLAN_ACTION, *PGMAC_TX_VLAN_ACTION;
typedef enum _GMAC_RX_PACKET_TYPE_ {
TYPE_ETHERNET = 0,
TYPE_IPV4 = 1,
TYPE_IPV4_PPTP = 2,
TYPE_IPV4_ICMP = 3,
TYPE_IPV4_IGMP = 4,
TYPE_IPV4_TCP = 5,
TYPE_IPV4_UDP = 6,
TYPE_IPV6 = 7,
TYPE_ICMPV6 = 8,
TYPE_IPV6_TCP = 9,
TYPE_IPV6_UDP = 10
}GMAC_RX_PACKET_TYPE, *PGMAC_RX_PACKET_TYPE;
BOOL
HalMiiGmacInitRtl8195a(
IN VOID *Data
);
BOOL
HalMiiGmacResetRtl8195a(
IN VOID *Data
);
BOOL
HalMiiGmacEnablePhyModeRtl8195a(
IN VOID *Data
);
u32
HalMiiGmacXmitRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacCleanTxRingRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacFillTxInfoRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacFillRxInfoRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacTxRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacRxRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacSetDefaultEthIoCmdRtl8195a(
IN VOID *Data
);
VOID
HalMiiGmacInitIrqRtl8195a(
IN VOID *Data
);
u32
HalMiiGmacGetInterruptStatusRtl8195a(
VOID
);
VOID
HalMiiGmacClearInterruptStatusRtl8195a(
u32 IsrStatus
);
#endif // #ifdef CONFIG_MII_VERIFY
#endif // #ifndef _RTL8195A_MII_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_NFC_H_
#define _RTL8195A_NFC_H_
#include "hal_api.h"
//#include "osdep_api.h"
#ifdef CONFIG_NFC_VERIFY
#include "../test/nfc/rtl8195a_nfc_test.h"
#endif
#if CONFIG_NFC_NORMAL
//===================== Register Bit Field Definition =====================
// TODO:
//===================== Register Address Definition =====================
//TODO:
//#include "osdep_api.h"
#define N2A_Q_LENGTH 10
#define N2ARLENGTH 4
//#define NFCTAGLENGTH 36 // maximum 36*4=144 bytes
#define NFCTAG_BASE 0x7F000
#define NFCTAG_PAGESIZE 256
#define NFCTAG_MAXPAGEIDX 16//(4*(1024/NFCTAG_PAGESIZE))
#define A2NWCLENGTH 4
#define FLASHAPPLENGTH 31
#define FLASHAPP_BASE 0x7E000
#define FLASH_PAGESIZE 128
#define FLASH_MAXPAGEIDX 32//(4*(1024/FLASH_PAGESIZE))
typedef struct _A2N_CATCH_W_ {
//u8 Vaild;
u8 A2NCatchRPage;
u32 A2NCatchWData[A2NWCLENGTH];
}A2N_CATCH_W_QUEUE, *PA2N_CATCH_W_QUEUE;
typedef struct _A2N_MAILBOX_Q_ {
u8 Length;
u8 Response;
u32 Content[A2NWCLENGTH+1];
}A2N_MAILBOX_Q,*PA2N_MAILBOX_Q;
typedef struct _N2A_CATCH_R_ {
u8 Vaild;
u8 N2ACatchRPage;
u32 N2ACatchRData[N2ARLENGTH];
}N2A_CATCH_R_QUEUE, *PN2A_CATCH_R_QUEUE;
typedef struct _N2A_R_ {
u8 Vaild;
u8 N2ARPage;
}N2A_R_QUEUE, *PN2A_R_QUEUE;
typedef struct _N2A_W_ {
u8 Vaild;
u8 N2AWPage;
u32 N2AWData;
}N2A_W_QUEUE, *PN2A_W_QUEUE;
typedef struct _NFC_ADAPTER_ {
u8 Function;
u32 NFCIsr;
u8 N2ABoxOpen;
u8 A2NSeq;
//u8 NFCTagFlashWIdx;
//u8 NFCTagFlashRIdx;
// u32 NFCTag[NFCTAGLENGTH];
#if !TASK_SCHEDULER_DISABLED
void * VeriSema;
#else
u32 VeriSema;
#endif
#ifdef PLATFORM_FREERTOS
void * NFCTask;
#else
u32 NFCTask;
#endif
#ifdef CONFIG_NFC_VERIFY
//N2A Write Tag
u8 N2AWQRIdx;
u8 N2AWQWIdx;
N2A_W_QUEUE N2AWQ[N2A_Q_LENGTH];
//N2A Read Tag
u8 N2ARQRIdx;
u8 N2ARQWIdx;
N2A_R_QUEUE N2ARQ[N2A_Q_LENGTH];
//N2A Read Catch
u8 N2ARCRIdx;
u8 N2ARCWIdx;
N2A_CATCH_R_QUEUE N2ACatchR[N2A_Q_LENGTH];
#endif
//A2N Write Catch
//u8 A2NWCRIdx;
//u8 A2NWCWIdx;
//A2N_CATCH_W_QUEUE A2NCatchW[N2A_Q_LENGTH];
//A2N Write mailbox queue
u8 A2NWMailBox;
u8 A2NWQRIdx;
u8 A2NWQWIdx;
A2N_MAILBOX_Q A2NMAILQ[N2A_Q_LENGTH];
u8 TaskStop;
void *nfc_obj;
}NFC_ADAPTER, *PNFC_ADAPTER;
typedef enum _N2A_CMD_ {
TAG_READ = 0,
TAG_WRITE = 1,
CATCH_READ_DATA = 2,
NFC_R_PRESENT = 4,
N2A_MAILBOX_STATE = 5,
EXT_CLK_REQ = 6,
MAX_N2ACMD
} N2A_CMD, *PN2A_CMD;
typedef enum _A2N_CMD_ {
TAG_READ_DATA = 0,
CATCH_READ = 2,
CATCH_WRITE = 3,
A2N_MAILBOX_STATE = 4,
CONFIRM_N2A_BOX_STATE = 5,
EXT_CLK_RSP = 6,
MAX_A2NCMD
} A2N_CMD, *PA2N_CMD;
// Callback event defination
typedef enum _NFC_HAL_EVENT_ {
NFC_HAL_READER_PRESENT = (1<<0),
NFC_HAL_READ = (1<<1),
NFC_HAL_WRITE = (1<<2),
NFC_HAL_ERR = (1<<3),
NFC_HAL_CACHE_RD = (1<<4)
}NFC_CB_EVENT, *PNFC_CB_EVENT;
VOID A2NWriteCatch(IN VOID *pNFCAdapte, IN u8 N2AWPage,
IN u8 Length, IN u32 *WData);
VOID A2NReadCatch(IN VOID *pNFCAdapte, IN u8 A2NRPage);
VOID HalNFCDmemInit(IN u32 *pTagData, IN u32 TagLen);
VOID HalNFCInit(PNFC_ADAPTER pNFCAdp);
VOID HalNFCDeinit(PNFC_ADAPTER pNFCAdp);
VOID HalNFCFwDownload(VOID);
u32 HalNFCDbgRead32(IN u32 Addr);
VOID HalNFCDbgWrite32(IN u32 Addr, IN u32 Data);
#endif //CONFIG_NFC_NORMAL
#endif // #ifndef _RTL8195A_NFC_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PCM_H_
#define _RTL8195A_PCM_H_
#include "basic_types.h"
#include "hal_api.h"
#define HAL_PCMX_READ32(PcmIndex, addr) \
HAL_READ32(PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF), addr)
#define HAL_PCMX_WRITE32(PcmIndex, addr, value) \
HAL_WRITE32((PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF)), addr, value)
#define REG_PCM_TRXBSA_OFF 0x004
#define REG_PCM_CTL 0x000
#define REG_PCM_CHCNR03 0x004
#define REG_PCM_TSR03 0x008
#define REG_PCM_BSIZE03 0x00C
#define REG_PCM_CH0TXBSA 0x010
#define REG_PCM_CH1TXBSA 0x014
#define REG_PCM_CH2TXBSA 0x018
#define REG_PCM_CH3TXBSA 0x01c
#define REG_PCM_CH0RXBSA 0x020
#define REG_PCM_CH1RXBSA 0x024
#define REG_PCM_CH2RXBSA 0x028
#define REG_PCM_CH3RXBSA 0x02c
#define REG_PCM_IMR03 0x030
#define REG_PCM_ISR03 0x034
#define REG_PCM_CHCNR47 0x038
#define REG_PCM_TSR47 0x03c
#define REG_PCM_BSIZE47 0x040
#define REG_PCM_CH4TXBSA 0x044
#define REG_PCM_CH5TXBSA 0x048
#define REG_PCM_CH6TXBSA 0x04c
#define REG_PCM_CH7TXBSA 0x050
#define REG_PCM_CH4RXBSA 0x054
#define REG_PCM_CH5RXBSA 0x058
#define REG_PCM_CH6RXBSA 0x05c
#define REG_PCM_CH7RXBSA 0x060
#define REG_PCM_IMR47 0x064
#define REG_PCM_ISR47 0x068
#define REG_PCM_CHCNR811 0x06c
#define REG_PCM_TSR811 0x070
#define REG_PCM_BSIZE811 0x074
#define REG_PCM_CH8TXBSA 0x078
#define REG_PCM_CH9TXBSA 0x07c
#define REG_PCM_CH10TXBSA 0x080
#define REG_PCM_CH11TXBSA 0x084
#define REG_PCM_CH8RXBSA 0x088
#define REG_PCM_CH9RXBSA 0x08c
#define REG_PCM_CH10RXBSA 0x090
#define REG_PCM_CH11RXBSA 0x094
#define REG_PCM_IMR811 0x098
#define REG_PCM_ISR811 0x09c
#define REG_PCM_CHCNR1215 0x0a0
#define REG_PCM_TSR1215 0x0a4
#define REG_PCM_BSIZE1215 0x0a8
#define REG_PCM_CH12TXBSA 0x0ac
#define REG_PCM_CH13TXBSA 0x0b0
#define REG_PCM_CH14TXBSA 0x0b4
#define REG_PCM_CH15TXBSA 0x0b8
#define REG_PCM_CH12RXBSA 0x0bc
#define REG_PCM_CH13RXBSA 0x0c0
#define REG_PCM_CH14RXBSA 0x0c4
#define REG_PCM_CH15RXBSA 0x0c8
#define REG_PCM_IMR1215 0x0cc
#define REG_PCM_ISR1215 0x0d0
#define REG_PCM_INTMAP 0x0d4
#define REG_PCM_WTSR03 0x0d8
#define REG_PCM_WTSR47 0x0dc
#define REG_PCM_RX_BUFOW 0x0e0
/* template
#define BIT_SHIFT_CTLX_ 7
#define BIT_MASK_CTLX_ 0x1
#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
*/
#define BIT_SHIFT_CTLX_SLAVE_SEL 8
#define BIT_MASK_CTLX_SLAVE_SEL 0x1
#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
#define BIT_SHIFT_CTLX_FSINV 9
#define BIT_MASK_CTLX_FSINV 0x1
#define BIT_CTLX_FSINV(x) (((x) & BIT_MASK_CTLX_FSINV) << BIT_SHIFT_CTLX_FSINV)
#define BIT_INV_CTLX_FSINV (~(BIT_MASK_CTLX_FSINV << BIT_SHIFT_CTLX_FSINV))
#define BIT_SHIFT_CTLX_PCM_EN 12
#define BIT_MASK_CTLX_PCM_EN 0x1
#define BIT_CTLX_PCM_EN(x) (((x) & BIT_MASK_CTLX_PCM_EN) << BIT_SHIFT_CTLX_PCM_EN)
#define BIT_INV_CTLX_PCM_EN (~(BIT_MASK_CTLX_PCM_EN << BIT_SHIFT_CTLX_PCM_EN))
#define BIT_SHIFT_CTLX_LINEARMODE 13
#define BIT_MASK_CTLX_LINEARMODE 0x1
#define BIT_CTLX_LINEARMODE(x) (((x) & BIT_MASK_CTLX_LINEARMODE) << BIT_SHIFT_CTLX_LINEARMODE)
#define BIT_INV_CTLX_LINEARMODE (~(BIT_MASK_CTLX_LINEARMODE << BIT_SHIFT_CTLX_LINEARMODE))
#define BIT_SHIFT_CTLX_LOOP_BACK 14
#define BIT_MASK_CTLX_LOOP_BACK 0x1
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
#define BIT_SHIFT_CTLX_ENDIAN_SWAP 17
#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1
#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
#define BIT_SHIFT_CHCNR03_CH0RE 24
#define BIT_MASK_CHCNR03_CH0RE 0x1
#define BIT_CHCNR03_CH0RE(x) (((x) & BIT_MASK_CHCNR03_CH0RE) << BIT_SHIFT_CHCNR03_CH0RE)
#define BIT_INV_CHCNR03_CH0RE (~(BIT_MASK_CHCNR03_CH0RE << BIT_SHIFT_CHCNR03_CH0RE))
#define BIT_SHIFT_CHCNR03_CH0TE 25
#define BIT_MASK_CHCNR03_CH0TE 0x1
#define BIT_CHCNR03_CH0TE(x) (((x) & BIT_MASK_CHCNR03_CH0TE) << BIT_SHIFT_CHCNR03_CH0TE)
#define BIT_INV_CHCNR03_CH0TE (~(BIT_MASK_CHCNR03_CH0TE << BIT_SHIFT_CHCNR03_CH0TE))
#define BIT_SHIFT_CHCNR03_CH1RE 16
#define BIT_MASK_CHCNR03_CH1RE 0x1
#define BIT_CHCNR03_CH1RE(x) (((x) & BIT_MASK_CHCNR03_CH1RE) << BIT_SHIFT_CHCNR03_CH1RE)
#define BIT_INV_CHCNR03_CH1RE (~(BIT_MASK_CHCNR03_CH1RE << BIT_SHIFT_CHCNR03_CH1RE))
#define BIT_SHIFT_CHCNR03_CH1TE 17
#define BIT_MASK_CHCNR03_CH1TE 0x1
#define BIT_CHCNR03_CH1TE(x) (((x) & BIT_MASK_CHCNR03_CH1TE) << BIT_SHIFT_CHCNR03_CH1TE)
#define BIT_INV_CHCNR03_CH1TE (~(BIT_MASK_CHCNR03_CH1TE << BIT_SHIFT_CHCNR03_CH1TE))
#define BIT_SHIFT_CHCNR03_CH2RE 8
#define BIT_MASK_CHCNR03_CH2RE 0x1
#define BIT_CHCNR03_CH2RE(x) (((x) & BIT_MASK_CHCNR03_CH2RE) << BIT_SHIFT_CHCNR03_CH2RE)
#define BIT_INV_CHCNR03_CH2RE (~(BIT_MASK_CHCNR03_CH2RE << BIT_SHIFT_CHCNR03_CH2RE))
#define BIT_SHIFT_CHCNR03_CH2TE 9
#define BIT_MASK_CHCNR03_CH2TE 0x1
#define BIT_CHCNR03_CH2TE(x) (((x) & BIT_MASK_CHCNR03_CH2TE) << BIT_SHIFT_CHCNR03_CH2TE)
#define BIT_INV_CHCNR03_CH2TE (~(BIT_MASK_CHCNR03_CH2TE << BIT_SHIFT_CHCNR03_CH2TE))
#define BIT_SHIFT_CHCNR03_CH3RE 0
#define BIT_MASK_CHCNR03_CH3RE 0x1
#define BIT_CHCNR03_CH3RE(x) (((x) & BIT_MASK_CHCNR03_CH3RE) << BIT_SHIFT_CHCNR03_CH3RE)
#define BIT_INV_CHCNR03_CH3RE (~(BIT_MASK_CHCNR03_CH3RE << BIT_SHIFT_CHCNR03_CH3RE))
#define BIT_SHIFT_CHCNR03_CH3TE 1
#define BIT_MASK_CHCNR03_CH3TE 0x1
#define BIT_CHCNR03_CH3TE(x) (((x) & BIT_MASK_CHCNR03_CH3TE) << BIT_SHIFT_CHCNR03_CH3TE)
#define BIT_INV_CHCNR03_CH3TE (~(BIT_MASK_CHCNR03_CH3TE << BIT_SHIFT_CHCNR03_CH3TE))
#define BIT_SHIFT_CHCNR03_CH0MUA 26
#define BIT_MASK_CHCNR03_CH0MUA 0x1
#define BIT_CHCNR03_CH0MUA(x) (((x) & BIT_MASK_CHCNR03_CH0MUA) << BIT_SHIFT_CHCNR03_CH0MUA)
#define BIT_INV_CHCNR03_CH0MUA (~(BIT_MASK_CHCNR03_CH0MUA << BIT_SHIFT_CHCNR03_CH0MUA))
#define BIT_SHIFT_CHCNR03_CH0BAND 27
#define BIT_MASK_CHCNR03_CH0BAND 0x1
#define BIT_CHCNR03_CH0BAND(x) (((x) & BIT_MASK_CHCNR03_CH0BAND) << BIT_SHIFT_CHCNR03_CH0BAND)
#define BIT_INV_CHCNR03_CH0BAND (~(BIT_MASK_CHCNR03_CH0BAND << BIT_SHIFT_CHCNR03_CH0BAND))
#define BIT_SHIFT_TSR03_CH0TSA 24
#define BIT_MASK_TSR03_CH0TSA 0x1F
#define BIT_TSR03_CH0TSA(x) (((x) & BIT_MASK_TSR03_CH0TSA) << BIT_SHIFT_TSR03_CH0TSA)
#define BIT_INV_TSR03_CH0TSA (~(BIT_MASK_TSR03_CH0TSA << BIT_SHIFT_TSR03_CH0TSA))
#define BIT_SHIFT_BSIZE03_CH0BSIZE 24
#define BIT_MASK_BSIZE03_CH0BSIZE 0xFF
#define BIT_BSIZE03_CH0BSIZE(x) (((x) & BIT_MASK_BSIZE03_CH0BSIZE) << BIT_SHIFT_BSIZE03_CH0BSIZE)
#define BIT_INV_BSIZE03_CH0BSIZE (~(BIT_MASK_BSIZE03_CH0BSIZE << BIT_SHIFT_BSIZE03_CH0BSIZE))
typedef struct _PCM_CTL_REG_ {
u32 FCNT :8; // Bit 0-7
u32 SlaveMode :1; // Bit 8
u32 FsInv :1; // Bit 9
u32 Rsvd10to11 :1; // Bit 10-11
u32 Pcm_En :1; // Bit 12
u32 LinearMode :1; // Bit 13
u32 LoopBack :1; // Bit 14
u32 Rsvd15to16 :2; // Bit 15-16
u32 EndianSwap :1; // Bit 17
u32 Rsvd18to31 :14; // Bit 18-31
} PCM_CTL_REG, *PPCM_CTL_REG;
typedef struct _PCM_CHCNR03_REG_ {
u32 CH3RE :1; // Bit 0
u32 CH3TE :1; // Bit 1
u32 CH3MuA :1; // Bit 2
u32 CH3Band :1; // Bit 3
u32 CH3SlicSel:4; // Bit 4-7
u32 CH2RE :1; // Bit 8
u32 CH2TE :1; // Bit 9
u32 CH2MuA :1; // Bit 10
u32 CH2Band :1; // Bit 11
u32 CH2SlicSel:4; // Bit 12-15
u32 CH1RE :1; // Bit 16
u32 CH1TE :1; // Bit 17
u32 CH1MuA :1; // Bit 18
u32 CH1Band :1; // Bit 19
u32 CH1SlicSel:4; // Bit 20-23
u32 CH0RE :1; // Bit 24
u32 CH0TE :1; // Bit 25
u32 CH0MuA :1; // Bit 26
u32 CH0Band :1; // Bit 27
u32 CH0SlicSel:4; // Bit 28-31
}PCM_CHCNR03_REG, *PPCM_CHCNR03_REG;
typedef struct _PCM_TSR03_REG_ {
u32 CH3TSA :5; // Bit 0-4
u32 Rsvd5to7 :3; // Bit 5-7
u32 CH2TSA :5; // Bit 8-12
u32 Rsvd13to15:3; // Bit 13-15
u32 CH1TSA :5; // Bit 16-20
u32 Rsvd21to23:3; // Bit 21-23
u32 CH0TSA :5; // Bit 24-28
u32 Rsvd29to31:3; // Bit 29-31
}PCM_TSR03_REG, *PPCM_TSR03_REG;
typedef struct _PCM_BSIZE03_REG_ {
u32 CH3BSize :8; // Bit 0-7
u32 CH2BSize :8; // Bit 8-15
u32 CH1BSize :8; // Bit 16-23
u32 CH0BSize :8; // Bit 24-31
}PCM_BSIZE03_REG, *PPCM_BSIZE03_REG;
typedef struct _PCM_ISR03_REG_ {
u32 CH3RXP1UA :1; // Bit 0
u32 CH3RXP0UA :1; // Bit 1
u32 CH3TXP1UA :1; // Bit 2
u32 CH3TXP0UA :1; // Bit 3
u32 CH3RXP1IP :1; // Bit 4
u32 CH3RXP0IP :1; // Bit 5
u32 CH3TXP1IP :1; // Bit 6
u32 CH3TXP0IP :1; // Bit 7
u32 CH2RXP1UA :1; // Bit 8
u32 CH2RXP0UA :1; // Bit 9
u32 CH2TXP1UA :1; // Bit 10
u32 CH2TXP0UA :1; // Bit 11
u32 CH2RXP1IP :1; // Bit 12
u32 CH2RXP0IP :1; // Bit 13
u32 CH2TXP1IP :1; // Bit 14
u32 CH2TXP0IP :1; // Bit 15
u32 CH1RXP1UA :1; // Bit 16
u32 CH1RXP0UA :1; // Bit 17
u32 CH1TXP1UA :1; // Bit 18
u32 CH1TXP0UA :1; // Bit 19
u32 CH1RXP1IP :1; // Bit 20
u32 CH1RXP0IP :1; // Bit 21
u32 CH1TXP1IP :1; // Bit 22
u32 CH1TXP0IP :1; // Bit 23
u32 CH0RXP1UA :1; // Bit 24
u32 CH0RXP0UA :1; // Bit 25
u32 CH0TXP1UA :1; // Bit 26
u32 CH0TXP0UA :1; // Bit 27
u32 CH0RXP1IP :1; // Bit 28
u32 CH0RXP0IP :1; // Bit 29
u32 CH0TXP1IP :1; // Bit 30
u32 CH0TXP0IP :1; // Bit 31
}PCM_ISR03_REG, *PPCM_ISR03_REG;
typedef enum _PCM_ISR015 {
PcmCh3P1RBU = 0x00000001, //ch0-3
PcmCh3P0RBU = 0x00000002,
PcmCh3P1TBU = 0x00000004,
PcmCh3P0TBU = 0x00000008,
PcmCh3P1ROK = 0x00000010,
PcmCh3P0ROK = 0x00000020,
PcmCh3P1TOK = 0x00000040,
PcmCh3P0TOK = 0x00000080,
PcmCh2P1RBU = 0x00000100,
PcmCh2P0RBU = 0x00000200,
PcmCh2P1TBU = 0x00000400,
PcmCh2P0TBU = 0x00000800,
PcmCh2P1ROK = 0x00001000,
PcmCh2P0ROK = 0x00002000,
PcmCh2P1TOK = 0x00004000,
PcmCh2P0TOK = 0x00008000,
PcmCh1P1RBU = 0x00010000,
PcmCh1P0RBU = 0x00020000,
PcmCh1P1TBU = 0x00040000,
PcmCh1P0TBU = 0x00080000,
PcmCh1P1ROK = 0x00100000,
PcmCh1P0ROK = 0x00200000,
PcmCh1P1TOK = 0x00400000,
PcmCh1P0TOK = 0x00800000,
PcmCh0P1RBU = 0x01000000,
PcmCh0P0RBU = 0x02000000,
PcmCh0P1TBU = 0x04000000,
PcmCh0P0TBU = 0x08000000,
PcmCh0P1ROK = 0x10000000,
PcmCh0P0ROK = 0x20000000,
PcmCh0P1TOK = 0x40000000,
PcmCh0P0TOK = 0x80000000,
PcmCh7P1RBU = 0x00000001, //ch4-7
PcmCh7P0RBU = 0x00000002,
PcmCh7P1TBU = 0x00000004,
PcmCh7P0TBU = 0x00000008,
PcmCh7P1ROK = 0x00000010,
PcmCh7P0ROK = 0x00000020,
PcmCh7P1TOK = 0x00000040,
PcmCh7P0TOK = 0x00000080,
PcmCh6P1RBU = 0x00000100,
PcmCh6P0RBU = 0x00000200,
PcmCh6P1TBU = 0x00000400,
PcmCh6P0TBU = 0x00000800,
PcmCh6P1ROK = 0x00001000,
PcmCh6P0ROK = 0x00002000,
PcmCh6P1TOK = 0x00004000,
PcmCh6P0TOK = 0x00008000,
PcmCh5P1RBU = 0x00010000,
PcmCh5P0RBU = 0x00020000,
PcmCh5P1TBU = 0x00040000,
PcmCh5P0TBU = 0x00080000,
PcmCh5P1ROK = 0x00100000,
PcmCh5P0ROK = 0x00200000,
PcmCh5P1TOK = 0x00400000,
PcmCh5P0TOK = 0x00800000,
PcmCh4P1RBU = 0x01000000,
PcmCh4P0RBU = 0x02000000,
PcmCh4P1TBU = 0x04000000,
PcmCh4P0TBU = 0x08000000,
PcmCh4P1ROK = 0x10000000,
PcmCh4P0ROK = 0x20000000,
PcmCh4P1TOK = 0x40000000,
PcmCh4P0TOK = 0x80000000,
PcmCh11P1RBU = 0x00000001, //ch8-11
PcmCh11P0RBU = 0x00000002,
PcmCh11P1TBU = 0x00000004,
PcmCh11P0TBU = 0x00000008,
PcmCh11P1ROK = 0x00000010,
PcmCh11P0ROK = 0x00000020,
PcmCh11P1TOK = 0x00000040,
PcmCh11P0TOK = 0x00000080,
PcmCh10P1RBU = 0x00000100,
PcmCh10P0RBU = 0x00000200,
PcmCh10P1TBU = 0x00000400,
PcmCh10P0TBU = 0x00000800,
PcmCh10P1ROK = 0x00001000,
PcmCh10P0ROK = 0x00002000,
PcmCh10P1TOK = 0x00004000,
PcmCh10P0TOK = 0x00008000,
PcmCh9P1RBU = 0x00010000,
PcmCh9P0RBU = 0x00020000,
PcmCh9P1TBU = 0x00040000,
PcmCh9P0TBU = 0x00080000,
PcmCh9P1ROK = 0x00100000,
PcmCh9P0ROK = 0x00200000,
PcmCh9P1TOK = 0x00400000,
PcmCh9P0TOK = 0x00800000,
PcmCh8P1RBU = 0x01000000,
PcmCh8P0RBU = 0x02000000,
PcmCh8P1TBU = 0x04000000,
PcmCh8P0TBU = 0x08000000,
PcmCh8P1ROK = 0x10000000,
PcmCh8P0ROK = 0x20000000,
PcmCh8P1TOK = 0x40000000,
PcmCh8P0TOK = 0x80000000,
PcmCh15P1RBU = 0x00000001, //ch12-15
PcmCh15P0RBU = 0x00000002,
PcmCh15P1TBU = 0x00000004,
PcmCh15P0TBU = 0x00000008,
PcmCh15P1ROK = 0x00000010,
PcmCh15P0ROK = 0x00000020,
PcmCh15P1TOK = 0x00000040,
PcmCh15P0TOK = 0x00000080,
PcmCh14P1RBU = 0x00000100,
PcmCh14P0RBU = 0x00000200,
PcmCh14P1TBU = 0x00000400,
PcmCh14P0TBU = 0x00000800,
PcmCh14P1ROK = 0x00001000,
PcmCh14P0ROK = 0x00002000,
PcmCh14P1TOK = 0x00004000,
PcmCh14P0TOK = 0x00008000,
PcmCh13P1RBU = 0x00010000,
PcmCh13P0RBU = 0x00020000,
PcmCh13P1TBU = 0x00040000,
PcmCh13P0TBU = 0x00080000,
PcmCh13P1ROK = 0x00100000,
PcmCh13P0ROK = 0x00200000,
PcmCh13P1TOK = 0x00400000,
PcmCh13P0TOK = 0x00800000,
PcmCh12P1RBU = 0x01000000,
PcmCh12P0RBU = 0x02000000,
PcmCh12P1TBU = 0x04000000,
PcmCh12P0TBU = 0x08000000,
PcmCh12P1ROK = 0x10000000,
PcmCh12P0ROK = 0x20000000,
PcmCh12P1TOK = 0x40000000,
PcmCh12P0TOK = 0x80000000
}PCM_ISR015, *PPCM_ISR015;
VOID
HalPcmOnOffRtl8195a(
IN VOID *Data
);
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
);
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
);
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
);
BOOL
HalPcmIsrEnAndDisRtl8195a(
IN VOID *Data
);
BOOL
HalPcmDumpRegRtl8195a(
IN VOID *Data
);
BOOL
HalPcmRtl8195a(
IN VOID *Data
);
#endif /* _RTL8195A_PCM_H_ */

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USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_PWM_H_
#define _RTL8195A_PWM_H_
#include "basic_types.h"
extern void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
);
#ifdef CONFIG_CHIP_E_CUT
extern _LONG_CALL_ void
HAL_Pwm_SetDuty_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
);
extern _LONG_CALL_ HAL_Status
HAL_Pwm_Init_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Enable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
extern _LONG_CALL_ void
HAL_Pwm_Disable_8195a_V04(
HAL_PWM_ADAPTER *pPwmAdapt
);
#endif
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_SDIO_HOST_H_
#define _RTL8195A_SDIO_HOST_H_
#include "hal_api.h"
#include "osdep_api.h"
#define HAL_SDIO_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
#define HAL_SDIO_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
#define HAL_SDIO_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
#define HAL_SDIO_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
#define HAL_SDIO_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
#define HAL_SDIO_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
/* =============== Register Offset Definition =============== */
#define REG_SDIO_HOST_SDMA_SYS_ADDR 0x00 // 4byte
#define REG_SDIO_HOST_BLK_SIZE 0x04 // 2byte
#define REG_SDIO_HOST_BLK_CNT 0x06 // 2byte
#define REG_SDIO_HOST_ARG 0x08 // 4byte
#define REG_SDIO_HOST_XFER_MODE 0x0C // 2byte
#define REG_SDIO_HOST_CMD 0x0E // 2byte
#define REG_SDIO_HOST_RSP0 0x10 // 4byte
#define REG_SDIO_HOST_RSP2 0x14 // 4byte
#define REG_SDIO_HOST_RSP4 0x18 // 4byte
#define REG_SDIO_HOST_RSP6 0x1C // 4byte
#define REG_SDIO_HOST_BUF_DATA_PORT 0x20 // 4byte
#define REG_SDIO_HOST_PRESENT_STATE 0x24 // 4byte
#define REG_SDIO_HOST_HOST_CTRL 0x28 // 1byte
#define REG_SDIO_HOST_PWR_CTRL 0x29 // 1byte
#define REG_SDIO_HOST_BLK_GAP_CTRL 0x2A // 1byte
#define REG_SDIO_HOST_WAKEUP_CTRL 0x2B // 1byte
#define REG_SDIO_HOST_CLK_CTRL 0x2C // 2byte
#define REG_SDIO_HOST_TIMEOUT_CTRL 0x2E // 1byte
#define REG_SDIO_HOST_SW_RESET 0x2F // 1byte
#define REG_SDIO_HOST_NORMAL_INT_STATUS 0x30 // 2byte
#define REG_SDIO_HOST_ERROR_INT_STATUS 0x32 // 2byte
#define REG_SDIO_HOST_NORMAL_INT_STATUS_EN 0x34 // 2byte
#define REG_SDIO_HOST_ERROR_INT_STATUS_EN 0x36 // 2byte
#define REG_SDIO_HOST_NORMAL_INT_SIG_EN 0x38 // 2byte
#define REG_SDIO_HOST_ERROR_INT_SIG_EN 0x3A // 2byte
#define REG_SDIO_HOST_CAPABILITIES 0x40 // 8byte
#define REG_SDIO_HOST_ADMA_SYS_ADDR 0x58 // 8byte
/* =============================================== */
/* Block Count Register (0x06) */
#define BLK_CNT_REG_MAX 0xFFFF // 65535 blocks
/* Transfer Mode Register (0x0C) */
#define XFER_MODE_DMA_EN BIT0
#define XFER_MODE_BLK_CNT_EN BIT1
#define XFER_MODE_AUTO_CMD12_EN BIT2
#define XFER_MODE_DATA_XFER_DIR BIT4
#define XFER_MODE_MULT_SINGLE_BLK BIT5
/* Present State Register (0x24) */
#define PRES_STATE_CMD_INHIBIT_CMD BIT0
#define PRES_STATE_CMD_INHIBIT_DAT BIT1
#define PRES_STATE_DAT_LINE_ACTIVE BIT2
#define PRES_STATE_CARD_INSERTED BIT16
#define PRES_STATE_DAT0_SIGNAL_LEVEL BIT20
/* Power Control Register (0x29) */
#define PWR_CTRL_SD_BUS_PWR BIT0
/* Clock Control Register (0x2C) */
#define CLK_CTRL_INTERAL_CLK_EN BIT0
#define CLK_CTRL_INTERAL_CLK_STABLE BIT1
#define CLK_CTRL_SD_CLK_EN BIT2
/* Software Reset Register (0x2F) */
#define SW_RESET_FOR_ALL BIT0
#define SW_RESET_FOR_CMD BIT1
#define SW_RESET_FOR_DAT BIT2
/* Normal Interrupt Status (0x30) */
#define NOR_INT_STAT_CMD_COMP BIT0
#define NOR_INT_STAT_XFER_COMP BIT1
#define NOR_INT_STAT_BLK_GAP_EVENT BIT2
#define NOR_INT_STAT_DMA_INT BIT3
#define NOR_INT_STAT_BUF_WR_RDY BIT4
#define NOR_INT_STAT_BUF_RD_RDY BIT5
#define NOR_INT_STAT_CARD_INSERT BIT6
#define NOR_INT_STAT_CARD_REMOVAL BIT7
#define NOR_INT_STAT_CARD_INT BIT8
#define NOR_INT_STAT_ERR_INT BIT15
/* Error Interrupt Status (0x32) */
#define ERR_INT_STAT_CMD_TIMEOUT BIT0
#define ERR_INT_STAT_CMD_CRC BIT1
#define ERR_INT_STAT_CMD_END_BIT BIT2
#define ERR_INT_STAT_CMD_IDX BIT3
#define ERR_INT_STAT_DATA_TIMEOUT BIT4
#define ERR_INT_STAT_DATA_CRC BIT5
#define ERR_INT_STAT_DATA_END_BIT BIT6
#define ERR_INT_STAT_CUR_LIMIT BIT7
#define ERR_INT_STAT_AUTO_CMD12 BIT8
#define ERR_INT_STAT_ADMA BIT9
/* Normal Interrupt Status Enable (0x34) */
#define NOR_INT_STAT_EN_CMD_COMP BIT0
#define NOR_INT_STAT_EN_XFER_COMP BIT1
#define NOR_INT_STAT_EN_BLK_GAP_EVENT BIT2
#define NOR_INT_STAT_EN_DMA_INT BIT3
#define NOR_INT_STAT_EN_BUF_WR_RDY BIT4
#define NOR_INT_STAT_EN_BUF_RD_RDY BIT5
#define NOR_INT_STAT_EN_CARD_INSERT BIT6
#define NOR_INT_STAT_EN_CARD_REMOVAL BIT7
#define NOR_INT_STAT_EN_CARD_INT BIT8
/* Error Interrupt Status Enable (0x36) */
#define ERR_INT_STAT_EN_CMD_TIMEOUT BIT0
#define ERR_INT_STAT_EN_CMD_CRC BIT1
#define ERR_INT_STAT_EN_CMD_END_BIT BIT2
#define ERR_INT_STAT_EN_CMD_IDX BIT3
#define ERR_INT_STAT_EN_DATA_TIMEOUT BIT4
#define ERR_INT_STAT_EN_DATA_CRC BIT5
#define ERR_INT_STAT_EN_DATA_END_BIT BIT6
#define ERR_INT_STAT_EN_CUR_LIMIT BIT7
#define ERR_INT_STAT_EN_AUTO_CMD BIT8
#define ERR_INT_STAT_EN_ADMA BIT9
/* Normal Interrupt Signal Enable (0x38) */
#define NOR_INT_SIG_EN_CMD_COMP BIT0
#define NOR_INT_SIG_EN_XFER_COMP BIT1
#define NOR_INT_SIG_EN_BLK_GAP_EVENT BIT2
#define NOR_INT_SIG_EN_DMA_INT BIT3
#define NOR_INT_SIG_EN_BUF_WR_RDY BIT4
#define NOR_INT_SIG_EN_BUF_RD_RDY BIT5
#define NOR_INT_SIG_EN_CARD_INSERT BIT6
#define NOR_INT_SIG_EN_CARD_REMOVAL BIT7
#define NOR_INT_SIG_EN_CARD_INT BIT8
/* Error Interrupt Signal Enable (0x3A) */
#define ERR_INT_SIG_EN_CMD_TIMEOUT BIT0
#define ERR_INT_SIG_EN_CMD_CRC BIT1
#define ERR_INT_SIG_EN_CMD_END_BIT BIT2
#define ERR_INT_SIG_EN_CMD_IDX BIT3
#define ERR_INT_SIG_EN_DATA_TIMEOUT BIT4
#define ERR_INT_SIG_EN_DATA_CRC BIT5
#define ERR_INT_SIG_EN_DATA_END_BIT BIT6
#define ERR_INT_SIG_EN_CUR_LIMIT BIT7
#define ERR_INT_SIG_EN_AUTO_CMD BIT8
#define ERR_INT_SIG_EN_ADMA BIT9
/* Capabilities Register (0x40) */
#define CAPA_TIMEOUT_CLK_UNIT BIT7
#define CAPA_ADMA2_SUPPORT BIT19
#define CAPA_HIGH_SPEED_SUPPORT BIT21
#define CAPA_VOLT_SUPPORT_33V BIT24
#define CAPA_VOLT_SUPPORT_30V BIT25
#define CAPA_VOLT_SUPPORT_18V BIT26
#define DATA_BLK_LEN 512
#define SCR_REG_LEN 8 // 64 bits
#define SWITCH_FN_STATUS_LEN 64 // 512 bits
#define SD_STATUS_LEN 64 // 512 bits
#define CSD_REG_LEN 16 // 128 bits
/* Switch Function (CMD6) Group */
#define SWITCH_FN_GRP1_DEFAULT BIT0
#define SWITCH_FN_GRP1_HIGH_SPEED BIT1
#define SWITCH_FN_GRP2_DEFAULT BIT0
#define SWITCH_FN_GRP2_FOR_EC BIT1
#define SWITCH_FN_GRP2_VENDOR_SPECIFIC BIT14
/* Operating Condition (ACMD41) */
#define ACMD41_POLL_INTERVAL 10000 // 10 ms
#define ACMD41_INIT_TIMEOUT 1000000 // 1 sec
/* Card Status (R1) */
#define R1_APP_CMD BIT5
#define R1_WP_VIOLATION BIT26
/* Error Interrupt Recovery */
#define HAL_SDH_RECOVERED 0x10
/* 0x0C */
typedef enum
{
WRITE_OP = 0,
READ_OP = 1
}DATA_OPERATION;
/* 0x0E */
typedef enum
{
CMD_GO_IDLE_STATE = 0,
CMD_ALL_SEND_CID = 2,
CMD_SEND_RELATIVE_ADDR = 3,
CMD_SET_DSR = 4,
CMD_SWITCH_FUNC = 6,
CMD_SELECT_DESELECT_CARD = 7,
CMD_SEND_IF_COND = 8,
CMD_SEND_CSD = 9,
CMD_SEND_CID = 10,
CMD_VOLTAGE_SWITCH = 11,
CMD_STOP_TRANSMISSION = 12,
CMD_SEND_STATUS = 13,
CMD_GO_INACTIVE_STATE = 15,
CMD_SET_BLOCKLEN = 16,
CMD_READ_SINGLE_BLOCK = 17,
CMD_READ_MULTIPLE_BLOCK = 18,
CMD_SET_BLOCK_COUNT = 23,
CMD_WRITE_BLOCK = 24,
CMD_WRITE_MULTIPLE_BLOCK = 25,
CMD_PROGRAM_CSD = 27,
CMD_ERASE_WR_BLK_START = 32,
CMD_ERASE_WR_BLK_END = 33,
CMD_ERASE = 38,
CMD_SD_SEND_OP_COND = 41,
CMD_LOCK_UNLOCK = 42,
CMD_SEND_SCR = 51,
CMD_APP_CMD = 55
}CMD_IDX;
typedef enum
{
NORMAL, // 00b
SUSPEND, // 01b
RESUME, // 10b
ABORT // 11b
}CMD_TYPE;
typedef enum
{
NO_DATA, // 00b
WITH_DATA // 01b
}DATA_PRESENT_SEL;
typedef enum
{
NO_RSP, // 00b
RSP_LEN_136, // 01b
RSP_LEN_48, // 10b
RSP_LEN_48_CHK_BUSY // 11b
}RSP_TYPE;
/* 0x28 */
typedef enum
{
SDMA, // 00b
RESERVED, // 01b
ADMA2_32BIT, // 10b
ADMA2_64BIT // 11b
}HOST_DMA_SELECT;
typedef enum
{
MODE_1_BIT = 0,
MODE_4_BIT = 1
}HOST_DATA_WIDTH;
/* 0x29 */
typedef enum
{
VOLT_33V = 7,// 111b
VOLT_30V = 6,// 110b
VOLT_18V = 5 // 101b
}HOST_SD_BUS_VOLT;
/* 0x2C */
typedef enum
{
BASE_CLK = 0x00, // 41.6 MHz
BASE_CLK_DIVIDED_BY_2 = 0x01, // 20.8 MHz
BASE_CLK_DIVIDED_BY_4 = 0x02, // 10.4 MHz
BASE_CLK_DIVIDED_BY_8 = 0x04, // 5.2 MHZ
BASE_CLK_DIVIDED_BY_16 = 0x08, // 2.6 MHz
BASE_CLK_DIVIDED_BY_32 = 0x10, // 1.3 MHz
BASE_CLK_DIVIDED_BY_64 = 0x20, // 650 kHz
BASE_CLK_DIVIDED_BY_128 = 0x40, // 325 kHz
BASE_CLK_DIVIDED_BY_256 = 0x80 // 162 kHz
}SD_CLK_DIVISOR;
typedef enum
{
SD_CLK_162KHZ,
SD_CLK_325KHZ,
SD_CLK_650KHZ,
SD_CLK_1_3MHZ,
SD_CLK_2_6MHZ,
SD_CLK_5_2MHZ,
SD_CLK_10_4MHZ,
SD_CLK_20_8MHZ,
SD_CLK_41_6MHZ
}SD_CLK_FREQUENCY;
/* Card Status Register */
typedef enum
{
IDLE, // 0
READY, // 1
IDENTIFICATION, // 2
STAND_BY, // 3
TRANSFER, // 4
SENDING_DATA, // 5
RECEIVE_DATA, // 6
PROGRAMMING, // 7
DISCONNECT, // 8
UNKNOWN = 0xFF
}CURRENT_STATE;
/* OCR Register */
typedef enum
{
VDD_27_28 = BIT15,
VDD_28_29 = BIT16,
VDD_29_30 = BIT17,
VDD_30_31 = BIT18,
VDD_31_32 = BIT19,
VDD_32_33 = BIT20,
VDD_33_34 = BIT21,
VDD_34_35 = BIT22,
VDD_35_36 = BIT23,
CARD_CAPA_STATUS = BIT30,
CARD_PWR_UP_STATUS = BIT31
}OCR_VOLTAGE_PROFILE;
/* SCR Register */
typedef enum
{
SD_VER_10 = 0,
SD_VER_110 = 1,
SD_VER_200 = 2
}PHYSICAL_LAYER_SPEC_VER;
/* CSD Register */
typedef enum
{
CLEAR_WRITE_PROTECT = 0,
SET_WRITE_PROTECT = 1
}TEMPORARY_WRITE_PROTECT_STATUS;
/* Switch Function (CMD6) Status Data Structure Version */
typedef enum
{
BUSY_STATUS_UNDEFINED = 0, // bits [511:376] are defined
BUSY_STATUS_DEFINED = 1 // bits [511:272] are defined
}SWITCH_FN_STATUS_DATA_STRUCTURE_VER;
/* Switch Function (CMD6) Busy Status */
typedef enum
{
READY_STATUS = 0,
BUSY_STATUS = 1
}SWITCH_FN_BUSY_STATUS;
/* Switch Function (CMD6) Mode */
typedef enum
{
CHECK_FN = 0x0,
SWITCH_FN = 0x1
}SWITCH_FN_MODE;
/* Switch Function (CMD6) Group 1 */
typedef enum
{
FN1_DEFAULT = 0x0,
FN1_HIGH_SPEED = 0x1,
FN1_KEEP_CURRENT = 0xF
}SWITCH_FN_GROUP_1;
/* Switch Function (CMD6) Group 2 */
typedef enum
{
FN2_DEFAULT = 0x0,
FN2_FOR_EC = 0x1,
FN2_VENDOR_SPECIFIC = 0xE,
FN2_KEEP_CURRENT = 0xF
}SWITCH_FN_GROUP_2;
typedef enum
{
DESEL_CARD = 0,
SEL_CARD = 1
}CARD_SELECTION;
typedef enum
{
SDSC_ONLY = 0,
SDHC_SUPPORT = 1
}HOST_CAPACITY_SUPPORT;
typedef enum
{
BUS_1_BIT = 0,
BUS_4_BIT = 2
}DATA_BUS_WIDTH;
typedef struct _ADMA2_ATTRIB_
{
u16 Valid:1;
u16 End:1;
u16 Int:1;
u16 Rsvd1:1;
u16 Act1:1;
u16 Act2:1;
u16 Rsvd2:10;
}ADMA2_ATTRIB, *PADMA2_ATTRIB;
typedef struct _ADMA2_DESC_FMT_
{
ADMA2_ATTRIB Attrib1;
u16 Len1;
u32 Addr1;
/* Link to next descriptor (if needed) */
ADMA2_ATTRIB Attrib2;
u16 Len2;
u32 Addr2;
}ADMA2_DESC_FMT, *PADMA2_DESC_FMT;
/* 0x0E */
typedef struct _SDIO_HOST_CMD_FMT_
{
u16 RespType:2;
u16 Rsvd0:1;
u16 CmdCrcChkEn:1;
u16 CmdIdxChkEn:1;
u16 DataPresent:1;
u16 CmdType:2;
u16 CmdIdx:6;
u16 Rsvd1:2;
}SDIO_HOST_CMD_FMT, *PSDIO_HOST_CMD_FMT;
typedef struct _SDIO_HOST_CMD_
{
SDIO_HOST_CMD_FMT CmdFmt;
u32 Arg;
}SDIO_HOST_CMD, *PSDIO_HOST_CMD;
HAL_Status
HalSdioHostInitHostRtl8195a(
IN VOID *Data
);
HAL_Status
HalSdioHostInitCardRtl8195a(
IN VOID *Data
);
HAL_Status
HalSdioHostDeInitRtl8195a(
IN VOID *Data
);
HAL_Status
HalSdioHostEnableRtl8195a(
IN VOID *Data
);
HAL_Status
HalSdioHostDisableRtl8195a(
IN VOID *Data
);
HAL_Status
HalSdioHostIrqInitRtl8195a(
IN VOID *Data
);
HAL_Status
HalSdioHostReadBlocksDmaRtl8195a(
IN VOID *Data,
IN u64 ReadAddr,
IN u32 BlockCnt
);
HAL_Status
HalSdioHostWriteBlocksDmaRtl8195a(
IN VOID *Data,
IN u64 WriteAddr,
IN u32 BlockCnt
);
HAL_Status
HalSdioHostStopTransferRtl8195a(
IN VOID *Data
);
HAL_Status
HalSdioHostGetCardStatusRtl8195a(
IN VOID *Data
);
HAL_Status
HalSdioHostGetSdStatusRtl8195a(
IN VOID *Data
);
HAL_Status
HalSdioHostChangeSdClockRtl8195a(
IN VOID *Data,
IN u8 Frequency
);
HAL_Status
HalSdioHostEraseRtl8195a(
IN VOID *Data,
IN u64 StartAddr,
IN u64 EndAddr
);
HAL_Status
HalSdioHostGetWriteProtectRtl8195a(
IN VOID *Data
);
HAL_Status
HalSdioHostSetWriteProtectRtl8195a(
IN VOID *Data,
IN u8 Setting
);
#ifdef CONFIG_SDIO_HOST_VERIFY
#define HAL_MMC_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
#define HAL_MMC_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
#define HAL_MMC_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
#define HAL_MMC_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
/* RTL8195A Register */
// REG_SOC_HCI_COM_FUNC_EN (0x214)
#define SD_DEVICE_IP_ON_BLK BIT0
#define SD_DEVICE_IP_OFF_BLK BIT1
#define SD_HOST_IP_BLK BIT2
// REG_PESOC_HCI_CLK_CTRL0 (0x240)
#define SD_HOST_CLKEN_IN_CPU_RUN_MODE BIT2
// REG_HCI_PINMUX_CTRL (0x2A0)
#define SD_DEVICE_MODE_PINMUX_EN BIT0
#define SD_HOST_MODE_PINMUX_EN BIT1
// 0x40059000
#define SD_HOST_CARD_DETECT_CIRCUIT BIT10
/* SD Host Register */
#define REG_SDMA_SYS_ADDR_ARG 0x00 // 4byte
#define REG_BLOCK_SIZE 0x04 // 2byte
#define REG_BLOCK_COUNT 0x06 // 2byte
#define REG_ARGUMENT1 0x08 // 4byte
#define REG_TRANSFER_MODE 0x0C // 2byte
#define REG_COMMAND 0x0E // 2byte
#define REG_RESPONSE0 0x10 // 4byte
#define REG_RESPONSE2 0x14 // 4byte
#define REG_RESPONSE4 0x18 // 4byte
#define REG_RESPONSE6 0x1C // 4byte
#define REG_BUFFER_DATA_PORT 0x20 // 4byte
#define REG_PRESENT_STATE 0x24 // 4byte
#define REG_HOST_CONTROL1 0x28 // 1byte
#define REG_POWER_CONTROL 0x29 // 1byte
#define REG_BLOCK_GAP_CONTROL 0x2A // 1byte
#define REG_WAKEUP_CONTROL 0x2B // 1byte
#define REG_CLOCK_CONTROL 0x2C // 2byte
#define REG_TIMEOUT_CONTROL 0x2E // 1byte
#define REG_SW_RESET 0x2F // 1byte
#define REG_NORMAL_INT_STATUS 0x30 // 2byte
#define REG_ERROR_INT_STATUS 0x32 // 2byte
#define REG_NORMAL_INT_STATUS_ENABLE 0x34 // 2byte
#define REG_ERROR_INT_STATUS_ENABLE 0x36 // 2byte
#define REG_NORMAL_INT_SIGNAL_ENABLE 0x38 // 2byte
#define REG_ERROR_INT_SIGNAL_ENABLE 0x3A // 2byte
#define REG_CAPABILITIES 0x40 // 8byte
#define REG_ADMA_ADDRESS 0x58 // 8byte
// Transfer Mode (0x0C)
#define BIT_DMA_EN BIT0
#define BIT_BLK_CNT_EN BIT1
#define BIT_AUTO_CMD12_EN BIT2
#define BIT_AUTO_CMD23_EN BIT3
#define BIT_READ_TRANS BIT4
#define BIT_MULTI_BLK BIT5
// Present State (0x24)
#define BIT_CMD_INHIBIT_CMD BIT0
#define BIT_CMD_INHIBIT_DAT BIT1
#define BIT_CARD_INSERTED BIT16
#define BIT_WRITE_PROTECT_SWITCH_PIN BIT19
// Power Control (0x29)
#define BIT_POWER_33 0xE
#define BIT_POWER_30 0xC
#define BIT_POWER_18 0xA
// Clock Control (0x2C)
#define BIT_INTERNAL_CLK_EN BIT0
#define BIT_INTERNAL_CLK_STABLE BIT1
#define BIT_SD_CLK_EN BIT2
// Software Reset (0x2F)
#define BIT_SW_RESET_ALL BIT0
#define BIT_SW_RESET_CMD_LINE BIT1
#define BIT_SW_RESET_DAT_LINE BIT2
// Norma Interrupt Status (0x30)
#define BIT_COMMAND_COMPLETE BIT0
#define BIT_TRANSFER_COMPLETE BIT1
#define BIT_BLOCK_GAP_EVENT BIT2
#define BIT_DMA_INT BIT3
#define BIT_BUFFER_WRITE_RDY BIT4
#define BIT_BUFFER_READ_RDY BIT5
#define BIT_CARD_INSERTION BIT6
#define BIT_CARD_REMOVAL BIT7
#define BIT_CARD_INT BIT8
#define BIT_ERROR_INT BIT15
// Error Interrupt Status (0x32)
#define BIT_DATA_TIME_OUT_ERROR BIT4
#define BIT_DATA_CRC_ERROR BIT5
#define BIT_ADMA_ERROR BIT9
// Capabilities (0x40)
#define BIT_VDD_33 BIT24
#define BIT_VDD_30 BIT25
#define BIT_VDD_18 BIT26
#define ENABLE 1
#define DISABLE 0
#define ADMA_DESC_NUM 50
#define BUFFER_UNIT_SIZE 512
typedef enum _MMC_HOST_TEST_FUNC_ {
MMC_HOST_TEST_HW_INIT, // 0
MMC_HOST_TEST_CARD_INIT, // 1
MMC_HOST_TEST_SEND_CMD, // 2
MMC_HOST_TEST_DEBUG, // 3
MMC_HOST_TEST_SW_RESET, // 4
MMC_HOST_TEST_READ_SINGLE, // 5
MMC_HOST_TEST_WRITE_SINGLE, // 6
MMC_HOST_TEST_READ_MULTI, // 7
MMC_HOST_TEST_WRITE_MULTI, // 8
MMC_HOST_TEST_SINGLE_LONGRUN, // 9
MMC_HOST_TEST_MULTI_LONGRUN, // 10
MMC_HOST_TEST_CARD_DETECTION, // 11
MMC_HOST_TEST_WRITE_PROTECT, // 12
MMC_HOST_TEST_REGISTER_RW, // 13
SD_HOST_HAL_API_VERIFY = 20,
SD_HOST_ERASE_TEST = 21,
SD_HOST_WP_TEST = 22,
SD_HOST_MB_TEST = 23,
SD_HOST_ADMA_MAX_TEST = 24
}MMC_HOST_TEST_FUNC;
typedef enum _RESPONSE_TYPE_ {
No_Response, // 00b
Response_136, // 01b
Response_48, // 10b
Response_48_Busy // 11b
}RESPONSE_TYPE;
typedef enum _COMMAND_TYPE_ {
Normal, // 00b
Suspend, // 01b
Resume, // 10b
Abort // 11b
}COMMAND_TYPE;
typedef enum _DATA_PRESENT_ {
No_Data_Present, // 00b
Data_Present, // 01b
}DATA_PRESENT;
typedef enum _SUPPLY_VOLTAGE_ {
MMC_VDD_27_28 = BIT15,
MMC_VDD_28_29 = BIT16,
MMC_VDD_29_30 = BIT17,
MMC_VDD_30_31 = BIT18,
MMC_VDD_31_32 = BIT19,
MMC_VDD_32_33 = BIT20,
MMC_VDD_33_34 = BIT21,
MMC_VDD_34_35 = BIT22,
MMC_VDD_35_36 = BIT23,
}SUPPLY_VOLTAGE;
typedef enum _COMMAND_INDEX_ {
GO_IDLE_STATE = 0,
ALL_SEND_CID = 2,
SEND_RELATIVE_ADDR = 3,
SET_BUS_WIDTH = 6,
SELECT_CARD = 7,
SEND_IF_COND = 8,
SEND_CSD = 9,
STOP_TRANSMISSION = 12,
SEND_STATUS = 13,
READ_SINGLE_BLOCK = 17,
READ_MULTIPLE_BLOCK = 18,
WRITE_BLOCK = 24,
WRITE_MULTIPLE_BLOCK = 25,
SD_SEND_OP_COND = 41,
APP_CMD = 55,
}COMMAND_INDEX;
typedef enum _TRANSFER_CONFIG_ {
Read_Data = 0,
Write_Data = 1,
Single_Block = 0,
Multiple_Block = 1,
}TRANSFER_CONFIG;
typedef enum _ERROR_STATUS_ {
General_Error, // 0
CRC_Error, // 1
TIME_OUT_ERROR, // 2
CRC_Error_NeedCMD12, // 3
Transfer_OK // 4
}ERROR_STATUS;
typedef enum _CARD_CURRENT_STATE_ {
IDLE_STATE,
READY_STATE,
IDENT_STATE,
STBY_STATE,
TRAN_STATE,
DATA_STATE,
RCV_STATE,
PRG_STATE,
DIS_STATE,
UNKNOWN_STATE
}CARD_CURRENT_STATE;
typedef struct _COMMAND_FORMAT_
{
u16 Resp_Type:2;
u16 Rsvd0:1;
u16 CMD_CRC_Chk:1;
u16 CMD_Idx_Chk:1;
u16 Data_Present:1;
u16 CMD_Type:2;
u16 CMD_Idx:6;
u16 Rsvd1:2;
}COMMAND_FORMAT, *PCOMMAND_FPRMAT;
typedef struct _MMC_COMMAND
{
COMMAND_FORMAT Cmd_Format;
u32 Arg;
}MMC_COMMAND;
typedef struct _MMC_HOST_
{
u32 OCR_Avail;
u32 Resp[4];
u32 CID[4];
u32 RCA;
}MMC_HOST, *PMMC_HOST;
typedef struct _ADMA_ATTR_
{
u16 Valid:1;
u16 End:1;
u16 Int:1;
u16 Rsvd1:1;
u16 Act1:1;
u16 Act2:1;
u16 Rsvd2:10;
}ADMA_ATTR, *PADMA_ATTR;
// 24 bytes
typedef struct _ADMA_DESC_TABLE_
{
// 1st buffer desc
ADMA_ATTR Attribute1;
u16 Length1;
u32 Address1;
// 2nd buffer desc
ADMA_ATTR Attribute2;
u16 Length2;
u32 Address2;
// 3rd buffer desc
ADMA_ATTR Attribute3;
u16 Length3;
u32 Address3;
}ADMA_DESC_TABLE, *PADMA_DESC_TABLE;
// 1024 bytes
typedef struct _ADMA_BUFFER_
{
u8 Data1[512]; /* 1st buffer */
u8 Data2[512]; /* 2nd buffer */
}ADMA_BUFFER, *PADMA_BUFFER;
VOID
SdHostTestApp(
IN u8 *argv[]
);
#endif // end of "#ifdef CONFIG_SDIO_HOST_VERIFY"
#endif /* #ifndef _RTL8195A_SDIO_HOST_H_ */

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#ifndef _RTL8195A_SDR_H
#define _RTL8195A_SDR_H
#define MS_0_CTRL_BASE BSP_MS_I_DRAMC_0_BASE
#define MS_0_CTRL_PHY_BASE (BSP_MS_I_DRAMC_0_BASE)
#define MS_0_WRAP_BASE (MS_0_CTRL_BASE + 0x200)
#define MS_1_CTRL_BASE BSP_MS_I_DRAMC_1_BASE
#define MS_1_CTRL_PHY_BASE (BSP_MS_I_DRAMC_1_BASE)
#define MS_1_WRAP_BASE (MS_1_CTRL_BASE + 0x200)
#define MS_PCTL_CCR_OFFSET 0x000
#define MS_PCTL_DCR_OFFSET 0x004
#define MS_PCTL_IOCR_OFFSET 0x008
#define MS_PCTL_CSR_OFFSET 0x00c
#define MS_PCTL_DRR_OFFSET 0x010
#define MS_PCTL_TPR0_OFFSET 0x014
#define MS_PCTL_TPR1_OFFSET 0x018
#define MS_PCTL_TPR2_OFFSET 0x01c
#define MS_PCTL_MR_OFFSET 0x020
#define MS_PCTL_EMR1_OFFSET 0x024
#define MS_PCTL_EMR2_OFFSET 0x028
#define MS_PCTL_EMR3_OFFSET 0x02c
#define MS_PCTL_CSR2_OFFSET 0x030
#define MS_PCTL_SRST_OFFSET 0x034
#define MS_PCTL_DTR2_OFFSET 0x038
#define MS_PCTL_DTR3_OFFSET 0x03c
#define MS_PCTL_GDLLCR_OFFSET 0x040
#define MS_PCTL_DLLCR0_OFFSET 0x044
#define MS_PCTL_DLLCR1_OFFSET 0x048
#define MS_PCTL_DLLCR2_OFFSET 0x04c
#define MS_PCTL_DLLCR3_OFFSET 0x050
#define MS_PCTL_DLLCR4_OFFSET 0x054
#define MS_PCTL_DLLCR5_OFFSET 0x058
#define MS_PCTL_DLLCR6_OFFSET 0x05c
#define MS_PCTL_DLLCR7_OFFSET 0x060
#define MS_PCTL_DLLCR8_OFFSET 0x064
#define MS_PCTL_DQTR0_OFFSET 0x068
#define MS_PCTL_DQTR1_OFFSET 0x06c
#define MS_PCTL_DQTR2_OFFSET 0x070
#define MS_PCTL_DQTR3_OFFSET 0x074
#define MS_PCTL_DQTR4_OFFSET 0x078
#define MS_PCTL_DQTR5_OFFSET 0x07c
#define MS_PCTL_DQTR6_OFFSET 0x080
#define MS_PCTL_DQTR7_OFFSET 0x084
#define MS_PCTL_DQSTR_OFFSET 0x088
#define MS_PCTL_DQSBTR_OFFSET 0x08c
#define MS_PCTL_ODTCR_OFFSET 0x090
#define MS_PCTL_DTR0_OFFSET 0x094
#define MS_PCTL_DTR1_OFFSET 0x098
#define MS_PCTL_DTAR_OFFSET 0x09c
#define MS_PCTL_ZQCR0_OFFSET 0x0a0
#define MS_PCTL_ZQCR1_OFFSET 0x0a4
#define MS_PCTL_ZQSR_OFFSET 0x0a8
#define MS_PCTL_RSLR0_OFFSET 0x0ac
#define MS_PCTL_RSLR1_OFFSET 0x0b0
#define MS_PCTL_RSLR2_OFFSET 0x0b4
#define MS_PCTL_RSLR3_OFFSET 0x0b8
#define MS_PCTL_RDGR0_OFFSET 0x0bc
#define MS_PCTL_RDGR1_OFFSET 0x0c0
#define MS_PCTL_RDGR2_OFFSET 0x0c4
#define MS_PCTL_RDGR3_OFFSET 0x0c8
#define MS_PCTL_MXSL_OFFSET 0x0cc
#define MS_PCTL_BCR_OFFSET 0x0d0
#define MS_PCTL_BALR0_OFFSET 0x0d4
#define MS_PCTL_BALR1_OFFSET 0x0d8
#define MS_PCTL_BDR0_OFFSET 0x0dc
#define MS_PCTL_BDR1_OFFSET 0x0e0
#define MS_PCTL_BBR_OFFSET 0x0e4
#define MS_PCTL_BSR_OFFSET 0x0e8
#define MS_PCTL_BYR_OFFSET 0x0ec
#define MS_PCTL_BFA_OFFSET 0x0f0
#define MS_PCTL_IDR_OFFSET 0x0f8
#define MS_PCTL_ERR_OFFSET 0x0fc
#define MS_WRAP_SCR_OFFSET 0x224
#define MS_WRAP_QCR_OFFSET 0x230
#define MS_WRAP_PCR_OFFSET 0x234
#define MS_WRAP_QTR0_OFFSET 0x240
#define MS_WRAP_QTR1_OFFSET 0x244
#define MS_WRAP_QTR2_OFFSET 0x248
#define MS_WRAP_QTR3_OFFSET 0x24c
#define MS_WRAP_QTR4_OFFSET 0x250
#define MS_WRAP_QTR5_OFFSET 0x254
#define MS_WRAP_QTR6_OFFSET 0x258
#define MS_WRAP_QTR7_OFFSET 0x25c
#define MS_WRAP_QTR8_OFFSET 0x260
#define MS_WRAP_QTR9_OFFSET 0x264
#define MS_WRAP_QTR10_OFFSET 0x268
#define MS_WRAP_QTR11_OFFSET 0x26c
#define MS_WRAP_QTR12_OFFSET 0x270
#define MS_WRAP_QTR13_OFFSET 0x274
#define MS_WRAP_QTR14_OFFSET 0x278
#define MS_WRAP_QTR15_OFFSET 0x27c
#define MS_PHY_DLY0 0x100
#define MS_PHY_DLY1_RST 0x104
#define MS_PHY_DLY_CLK 0x108
#define MS_PHY_DLY_ST 0x10c
#define MS_PHY_DLY_NUM 0x100
#define PCTL_CCR_INIT_BFO 0
#define PCTL_CCR_INIT_BFW 1
#define PCTL_CCR_DTT_BFO 1
#define PCTL_CCR_DTT_BFW 1
#define PCTL_CCR_BTT_BFO 2
#define PCTL_CCR_BTT_BFW 1
#define PCTL_CCR_DPIT_BFO 3
#define PCTL_CCR_DPIT_BFW 1
#define PCTL_CCR_FLUSH_FIFO_BFO 8
#define PCTL_CCR_FLUSH_FIFO_BFW 1
#define PCTL_DCR_DDR3_BFO 0
#define PCTL_DCR_DDR3_BFW 1
#define PCTL_DCR_SDR_BFO 1
#define PCTL_DCR_SDR_BFW 1
#define PCTL_DCR_DQ32_BFO 4
#define PCTL_DCR_DQ32_BFW 1
#define PCTL_DCR_DFI_RATE_BFO 8
#define PCTL_DCR_DFI_RATE_BFW 3
#define PCTL_IOCR_RD_PIPE_BFO 8
#define PCTL_IOCR_RD_PIPE_BFW 4
#define PCTL_IOCR_TPHY_WD_BFO 12
#define PCTL_IOCR_TPHY_WD_BFW 5
#define PCTL_IOCR_TPHY_WL_BFO 17
#define PCTL_IOCR_TPHY_WL_BFW 3
#define PCTL_IOCR_TPHY_RD_EN_BFO 20
#define PCTL_IOCR_TPHY_RD_EN_BFW 5
#define PCTL_CSR_MEM_IDLE_BFO 8
#define PCTL_CSR_MEM_IDLE_BFW 1
#define PCTL_CSR_DT_IDLE_BFO 9
#define PCTL_CSR_DT_IDLE_BFW 1
#define PCTL_CSR_BIST_IDLE_BFO 10
#define PCTL_CSR_BIST_IDLE_BFW 1
#define PCTL_CSR_DT_FAIL_BFO 11
#define PCTL_CSR_DT_FAIL_BFW 1
#define PCTL_CSR_BT_FAIL_BFO 12
#define PCTL_CSR_BT_FAIL_BFW 1
#define PCTL_DRR_TRFC_BFO 0
#define PCTL_DRR_TRFC_BFW 7
#define PCTL_DRR_TREF_BFO 8
#define PCTL_DRR_TREF_BFW 24
#define PCTL_DRR_REF_NUM_BFO 24
#define PCTL_DRR_REF_NUM_BFW 4
#define PCTL_DRR_REF_DIS_BFO 28
#define PCTL_DRR_REF_DIS_BFW 1
#define PCTL_TPR0_TRP_BFO 0
#define PCTL_TPR0_TRP_BFW 4
#define PCTL_TPR0_TRAS_BFO 4
#define PCTL_TPR0_TRAS_BFW 5
#define PCTL_TPR0_TWR_BFO 9
#define PCTL_TPR0_TWR_BFW 4
#define PCTL_TPR0_TRTP_BFO 13
#define PCTL_TPR0_TRTP_BFW 3
#define PCTL_TPR1_TRRD_BFO 0
#define PCTL_TPR1_TRRD_BFW 4
#define PCTL_TPR1_TRC_BFO 4
#define PCTL_TPR1_TRC_BFW 6
#define PCTL_TPR1_TRCD_BFO 10
#define PCTL_TPR1_TRCD_BFW 4
#define PCTL_TPR1_TCCD_BFO 14
#define PCTL_TPR1_TCCD_BFW 3
#define PCTL_TPR1_TWTR_BFO 17
#define PCTL_TPR1_TWTR_BFW 3
#define PCTL_TPR1_TRTW_BFO 20
#define PCTL_TPR1_TRTW_BFW 4
#define PCTL_TPR2_INIT_REF_NUM_BFO 0
#define PCTL_TPR2_INIT_REF_NUM_BFW 4
#define PCTL_TPR2_INIT_NS_EN_BFO 4
#define PCTL_TPR2_INIT_NS_EN_BFW 1
#define PCTL_TPR2_TMRD_BFO 5
#define PCTL_TPR2_TMRD_BFW 2
#define PCTL_MR_BL_BFO 0
#define PCTL_MR_BL_BFW 3
#define PCTL_MR_BT_BFO 3
#define PCTL_MR_BT_BFW 1
#define PCTL_MR_CAS_BFO 4
#define PCTL_MR_CAS_BFW 3
#define PCTL_MR_OP_BFO 8
#define PCTL_MR_OP_BFW 12
#define PCTL_EMR1_ADDLAT_BFO 3
#define PCTL_EMR1_ADDLAT_BFW 3
#define PCTL_CMD_DPIN_RSTN_BFO 0
#define PCTL_CMD_DPIN_RSTN_BFW 1
#define PCTL_CMD_DPIN_CKE_BFO 1
#define PCTL_CMD_DPIN_CKE_BFW 1
#define PCTL_CMD_DPIN_ODT_BFO 2
#define PCTL_CMD_DPIN_ODT_BFW 1
#define PCTL_BCR_STOP_BFO 0
#define PCTL_BCR_STOP_BFW 1
#define PCTL_BCR_CMP_BFO 1
#define PCTL_BCR_CMP_BFW 1
#define PCTL_BCR_LOOP_BFO 2
#define PCTL_BCR_LOOP_BFW 1
#define PCTL_BCR_DIS_MASK_BFO 3
#define PCTL_BCR_DIS_MASK_BFW 1
#define PCTL_BCR_AT_STOP_BFO 4
#define PCTL_BCR_AT_STOP_BFW 1
#define PCTL_BCR_FLUSH_CMD_BFO 8
#define PCTL_BCR_FLUSH_CMD_BFW 1
#define PCTL_BCR_FLUSH_WD_BFO 9
#define PCTL_BCR_FLUSH_WD_BFW 1
#define PCTL_BCR_FLUSH_RGD_BFO 10
#define PCTL_BCR_FLUSH_RGD_BFW 1
#define PCTL_BCR_FLUSH_RD_BFO 11
#define PCTL_BCR_FLUSH_RD_BFW 1
#define PCTL_BCR_FLUSH_RD_EXPC_BFO 16
#define PCTL_BCR_FLUSH_RD_EXPC_BFW 14
#define PCTL_BST_ERR_FST_TH_BFO 0
#define PCTL_BST_ERR_FST_TH_BFW 12
#define PCTL_BST_ERR_CNT_BFO 16
#define PCTL_BST_ERR_CNT_BFW 14
#define PCTL_BSRAM0_CMD_LEVEL_BFO 0
#define PCTL_BSRAM0_CMD_LEVEL_BFW 12
#define PCTL_BSRAM0_WD_LEVEL_BFO 16
#define PCTL_BSRAM0_WD_LEVEL_BFW 14
#define PCTL_BSRAM1_RG_LEVEL_BFO 0
#define PCTL_BSRAM1_RG_LEVEL_BFW 14
#define PCTL_BSRAM1_RD_LEVEL_BFO 16
#define PCTL_BSRAM1_RD_LEVEL_BFW 14
#define WRAP_MISC_PAGE_SIZE_BFO 0
#define WRAP_MISC_PAGE_SIZE_BFW 4
#define WRAP_MISC_BANK_SIZE_BFO 4
#define WRAP_MISC_BANK_SIZE_BFW 2
#define WRAP_MISC_BST_SIZE_BFO 6
#define WRAP_MISC_BST_SIZE_BFW 2
#define WRAP_MISC_DDR_PARAL_BFO 8
#define WRAP_MISC_DDR_PARAL_BFW 1
struct ms_rxi310_portmap {
volatile unsigned int ccr; /* 0x000 */
volatile unsigned int dcr; /* 0x004 */
volatile unsigned int iocr; /* 0x008 */
volatile unsigned int csr; /* 0x00c */
volatile unsigned int drr; /* 0x010 */
volatile unsigned int tpr0; /* 0x014 */
volatile unsigned int tpr1; /* 0x018 */
volatile unsigned int tpr2; /* 0x01c */
volatile unsigned int mr; /* 0x020 */
volatile unsigned int emr1; /* 0x024 */
volatile unsigned int emr2; /* 0x028 */
volatile unsigned int emr3; /* 0x02c */
volatile unsigned int cdpin; /* 0x030 */
volatile unsigned int tdpin; /* 0x034 */
volatile unsigned int dtr2; /* 0x038 */
volatile unsigned int dtr3; /* 0x03c */
volatile unsigned int gdllcr; /* 0x040 */
volatile unsigned int dllcr0; /* 0x044 */
volatile unsigned int dllcr1; /* 0x048 */
volatile unsigned int dllcr2; /* 0x04c */
volatile unsigned int dllcr3; /* 0x050 */
volatile unsigned int dllcr4; /* 0x054 */
volatile unsigned int dllcr5; /* 0x058 */
volatile unsigned int dllcr6; /* 0x05c */
volatile unsigned int dllcr7; /* 0x060 */
volatile unsigned int dllcr8; /* 0x064 */
volatile unsigned int dqtr0; /* 0x068 */
volatile unsigned int dqtr1; /* 0x06c */
volatile unsigned int dqtr2; /* 0x070 */
volatile unsigned int dqtr3; /* 0x074 */
volatile unsigned int dqtr4; /* 0x078 */
volatile unsigned int dqtr5; /* 0x07c */
volatile unsigned int dqtr6; /* 0x080 */
volatile unsigned int dqtr7; /* 0x084 */
volatile unsigned int dqstr; /* 0x088 */
volatile unsigned int dqsbtr; /* 0x08c */
volatile unsigned int odtcr; /* 0x090 */
volatile unsigned int dtr0; /* 0x094 */
volatile unsigned int dtr1; /* 0x098 */
volatile unsigned int dtar; /* 0x09c */
volatile unsigned int zqcr0; /* 0x0a0 */
volatile unsigned int zqcr1; /* 0x0a4 */
volatile unsigned int zqsr; /* 0x0a8 */
volatile unsigned int rslr0; /* 0x0ac */
volatile unsigned int rslr1; /* 0x0b0 */
volatile unsigned int rslr2; /* 0x0b4 */
volatile unsigned int rslr3; /* 0x0b8 */
volatile unsigned int rdgr0; /* 0x0bc */
volatile unsigned int rdgr1; /* 0x0c0 */
volatile unsigned int rdgr2; /* 0x0c4 */
volatile unsigned int rdgr3; /* 0x0c8 */
volatile unsigned int mxsl; /* 0x0cc */
volatile unsigned int bcr; /* 0x0d0 */
volatile unsigned int bst; /* 0x0d4 */
volatile unsigned int bsram0; /* 0x0d8 */
volatile unsigned int bsram1; /* 0x0dc */
volatile unsigned int bdr1; /* 0x0e0 */
volatile unsigned int bbr; /* 0x0e4 */
volatile unsigned int bsr; /* 0x0e8 */
volatile unsigned int byr; /* 0x0ec */
volatile unsigned int bfa; /* 0x0f0 */
volatile unsigned int pctl_svn; /* 0x0f4 */
volatile unsigned int pctl_idr; /* 0x0f8 */
volatile unsigned int err; /* 0x0fc */
// SDR_PHY CONTROL REGISTER
volatile unsigned int phy_dly0; /* 0x100 */
volatile unsigned int phy_dly1_rst; /* 0x104 */
volatile unsigned int phy_dly_clk; /* 0x108 */
volatile unsigned int phy_dly_st; /* 0x10c */
volatile unsigned int phy_dly_num; /* 0x110 */
volatile unsigned int reserved0[68];
// WRAP CONTROL REGISTER
volatile unsigned int misc; /* 0x224 */
volatile unsigned int cq_ver; /* 0x228 */
volatile unsigned int cq_mon; /* 0x22c */
volatile unsigned int wq_ver; /* 0x230 */
volatile unsigned int wq_mon; /* 0x234 */
volatile unsigned int rq_ver; /* 0x240 */
volatile unsigned int rq_mon; /* 0x244 */
volatile unsigned int reserved1[22];
volatile unsigned int wwrap_idr; /* 0x2a0 */
volatile unsigned int wrap_svn; /* 0x2a4 */
}; //ms_rxi310_portmap
#define QFIFO_CMD_BANK_BFO (35 - QFIFO_CMD_WRRD_BFO) // [38:35]
#define QFIFO_CMD_BANK_BFW 4
#define QFIFO_CMD_PAGE_BFO (20 - QFIFO_CMD_WRRD_BFO) // [34:20]
#define QFIFO_CMD_PAGE_BFW 15
#define QFIFO_CMD_COLU_BFO (7 - QFIFO_CMD_WRRD_BFO) // [19: 7]
#define QFIFO_CMD_COLU_BFW 13 // [19: 7]
#define QFIFO_BST_LEN_BFO (3 - QFIFO_CMD_WRRD_BFO) // [6:3]
#define QFIFO_BST_LEN_BFW 4 // [6:3]
#define QFIFO_CMD_WRRD_BFO 2 // [2], remove bit[1:0]
#define QFIFO_CMD_WRRD_BFW 1 // [2], remove bit[1:0]
//====================================================//
#define REG_SDR_CCR 0x00
#define REG_SDR_DCR 0x04
#define REG_SDR_IOCR 0x08
#define REG_SDR_CSR 0x0C
#define REG_SDR_DRR 0x10
#define REG_SDR_TPR0 0x14
#define REG_SDR_TPR1 0x18
#define REG_SDR_TPR2 0x1C
#define REG_SDR_MR 0x20
#define REG_SDR_EMR1 0x24
#define REG_SDR_EMR2 0x28
#define REG_SDR_EMR3 0x2C
#define REG_SDR_CMD_DPIN 0x30
#define REG_SDR_TIE_DPIN 0x34
#define REG_SDR_BCR 0xD0
#define REG_SDR_BST 0xD4
#define REG_SDR_BSRAM0 0xD8
#define REG_SDR_BSRAM1 0xDC
#define REG_SDR_PCTL_SVN_ID 0xF4
#define REG_SDR_PCTL_IDR 0xF8
#define REG_SDR_DLY0 0x100
#define REG_SDR_DLY1 0x104
#define REG_SDR_DCM_RST 0x104
#define REG_SDR_DLY_CLK_PHA 0x108
#define REG_SDR_DLY_ST 0x10C
#define REG_SDR_MISC 0x224
#define REG_SDR_OCP_WRAP_IDR 0x2A0
#define REG_SDR_OCP_WRAP_VERSION 0x2A4
#endif // end of "#ifndef _RTL8195A_SDR_H"

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USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h Normal file
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USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_ssi.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_SSI_H_
#define _RTL8195A_SSI_H_
#define SSI_DUMMY_DATA 0x00 // for master mode, we need to push a Dummy data to TX FIFO for read
#define SSI_CLK_SPI1 (PLATFORM_CLOCK/2)
#define SSI_CLK_SPI0_2 (PLATFORM_CLOCK/4)
/* Parameters of DW_apb_ssi for RTL8195A */
#define SSI_TX_FIFO_DEPTH 64
#define TX_ABW 6 // 1-8, log2(SSI_TX_FIFO_DEPTH)
#define SSI_RX_FIFO_DEPTH 64
#define RX_ABW 6 // 1-8, log2(SSI_RX_FIFO_DEPTH)
#define SSI0_REG_BASE 0x40042000
#define SSI1_REG_BASE 0x40042400
#define SSI2_REG_BASE 0x40042800
/* Memory Map of DW_apb_ssi */
#define REG_DW_SSI_CTRLR0 0x00 // 16 bits
#define REG_DW_SSI_CTRLR1 0x04 // 16 bits
#define REG_DW_SSI_SSIENR 0x08 // 1 bit
#define REG_DW_SSI_MWCR 0x0C // 3 bits
#define REG_DW_SSI_SER 0x10 //
#define REG_DW_SSI_BAUDR 0x14 // 16 bits
#define REG_DW_SSI_TXFTLR 0x18 // TX_ABW
#define REG_DW_SSI_RXFTLR 0x1C // RX_ABW
#define REG_DW_SSI_TXFLR 0x20 //
#define REG_DW_SSI_RXFLR 0x24 //
#define REG_DW_SSI_SR 0x28 // 7 bits
#define REG_DW_SSI_IMR 0x2C //
#define REG_DW_SSI_ISR 0x30 // 6 bits
#define REG_DW_SSI_RISR 0x34 // 6 bits
#define REG_DW_SSI_TXOICR 0x38 // 1 bits
#define REG_DW_SSI_RXOICR 0x3C // 1 bits
#define REG_DW_SSI_RXUICR 0x40 // 1 bits
#define REG_DW_SSI_MSTICR 0x44 // 1 bits
#define REG_DW_SSI_ICR 0x48 // 1 bits
#define REG_DW_SSI_DMACR 0x4C // 2 bits
#define REG_DW_SSI_DMATDLR 0x50 // TX_ABW
#define REG_DW_SSI_DMARDLR 0x54 // RX_ABW
#define REG_DW_SSI_IDR 0x58 // 32 bits
#define REG_DW_SSI_COMP_VERSION 0x5C // 32 bits
#define REG_DW_SSI_DR 0x60 // 16 bits 0x60-0xEC
#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits
#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits
#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits
#define REG_DW_SSI_RSVD_2 0xFC // 32 bits
// CTRLR0 0x00 // 16 bits, 6.2.1
// DFS Reset Value: 0x7
#define BIT_SHIFT_CTRLR0_DFS 0
#define BIT_MASK_CTRLR0_DFS 0xF
#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
#define BIT_SHIFT_CTRLR0_FRF 4
#define BIT_MASK_CTRLR0_FRF 0x3
#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
#define BIT_SHIFT_CTRLR0_SCPH 6
#define BIT_MASK_CTRLR0_SCPH 0x1
#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
#define BIT_SHIFT_CTRLR0_SCPOL 7
#define BIT_MASK_CTRLR0_SCPOL 0x1
#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL)
#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL))
#define BIT_SHIFT_CTRLR0_TMOD 8
#define BIT_MASK_CTRLR0_TMOD 0x3
#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD)
#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD))
#define BIT_SHIFT_CTRLR0_SLV_OE 10
#define BIT_MASK_CTRLR0_SLV_OE 0x1
#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE)
#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE))
#define BIT_SHIFT_CTRLR0_SRL 11
#define BIT_MASK_CTRLR0_SRL 0x1
#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL)
#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL))
#define BIT_SHIFT_CTRLR0_CFS 12
#define BIT_MASK_CTRLR0_CFS 0xF
#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS)
#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS))
// CTRLR1 0x04 // 16 bits
#define BIT_SHIFT_CTRLR1_NDF 0
#define BIT_MASK_CTRLR1_NDF 0xFFFF
#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
// SSIENR 0x08 // 1 bit
#define BIT_SHIFT_SSIENR_SSI_EN 0
#define BIT_MASK_SSIENR_SSI_EN 0x1
#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN)
#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN))
// MWCR 0x0c // 3 bits
#define BIT_SHIFT_MWCR_MWMOD 0
#define BIT_MASK_MWCR_MWMOD 0x1
#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD)
#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD))
#define BIT_SHIFT_MWCR_MDD 1
#define BIT_MASK_MWCR_MDD 0x1
#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD)
#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD))
#define BIT_SHIFT_MWCR_MHS 2
#define BIT_MASK_MWCR_MHS 0x1
#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS)
#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS))
// SER 0x10 // Variable Length
#define BIT_SHIFT_SER_SER 0
#define BIT_MASK_SER_SER 0xFF
#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER)
#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER))
// BAUDR 0x14 // 16 bits
#define BIT_SHIFT_BAUDR_SCKDV 0
#define BIT_MASK_BAUDR_SCKDV 0xFFFF
#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV)
#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV))
// TXFLTR 0x18 // Variable Length
#define BIT_SHIFT_TXFTLR_TFT 0
#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0
#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
// RXFLTR 0x1c // Variable Length
#define BIT_SHIFT_RXFTLR_RFT 0
#define BIT_MASK_RXFTLR_RFT 0x3F // (RX_ABW-1):0
#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT)
#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT))
// TXFLR 0x20 // see [READ ONLY]
#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0
// RXFLR 0x24 // see [READ ONLY]
#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0
// SR 0x28 // 7 bits [READ ONLY]
#define BIT_SR_BUSY BIT0
#define BIT_SR_TFNF BIT1
#define BIT_SR_TFE BIT2
#define BIT_SR_RFNE BIT3
#define BIT_SR_RFF BIT4
#define BIT_SR_TXE BIT5
#define BIT_SR_DCOL BIT6
// IMR 0x2c // see
#define BIT_SHIFT_IMR_TXEIM 0
#define BIT_MASK_IMR_TXEIM 0x1
// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM)
#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM))
#define BIT_SHIFT_IMR_TXOIM 1
#define BIT_MASK_IMR_TXOIM 0x1
// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM)
#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM))
#define BIT_SHIFT_IMR_RXUIM 2
#define BIT_MASK_IMR_RXUIM 0x1
// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM)
#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM))
#define BIT_SHIFT_IMR_RXOIM 3
#define BIT_MASK_IMR_RXOIM 0x1
// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM)
#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM))
#define BIT_SHIFT_IMR_RXFIM 4
#define BIT_MASK_IMR_RXFIM 0x1
// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM)
#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM))
#define BIT_SHIFT_IMR_MSTIM 5
#define BIT_MASK_IMR_MSTIM 0x1
// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM)
#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM))
#define BIT_IMR_TXEIM BIT0
#define BIT_IMR_TXOIM BIT1
#define BIT_IMR_RXUIM BIT2
#define BIT_IMR_RXOIM BIT3
#define BIT_IMR_RXFIM BIT4
#define BIT_IMR_MSTIM BIT5
// ISR 0x30 // 6 bits [READ ONLY]
#define BIT_ISR_TXEIS BIT0
#define BIT_ISR_TXOIS BIT1
#define BIT_ISR_RXUIS BIT2
#define BIT_ISR_RXOIS BIT3
#define BIT_ISR_RXFIS BIT4
#define BIT_ISR_MSTIS BIT5
// RISR 0x34 // 6 bits [READ ONLY]
#define BIT_RISR_TXEIR BIT0
#define BIT_RISR_TXOIR BIT1
#define BIT_RISR_RXUIR BIT2
#define BIT_RISR_RXOIR BIT3
#define BIT_RISR_RXFIR BIT4
#define BIT_RISR_MSTIR BIT5
// TXOICR 0x38 // 1 bits [READ ONLY]
// RXOICR 0x3c // 1 bits [READ ONLY]
// RXUICR 0x40 // 1 bits [READ ONLY]
// MSTICR 0x44 // 1 bits [READ ONLY]
// ICR 0x48 // 1 bits [READ ONLY]
// DMACR 0x4c // 2 bits
#define BIT_SHIFT_DMACR_RDMAE 0
#define BIT_MASK_DMACR_RDMAE 0x1
#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE)
#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE))
#define BIT_SHIFT_DMACR_TDMAE 1
#define BIT_MASK_DMACR_TDMAE 0x1
#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE)
#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE))
// DMATDLR 0x50
#define BIT_SHIFT_DMATDLR_DMATDL 0
#define BIT_MASK_DMATDLR_DMATDL 0x3F // (TX_ABW-1):0
#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL)
#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL))
// DMARDLR 0x54
#define BIT_SHIFT_DMARDLR_DMARDL 0
#define BIT_MASK_DMARDLR_DMARDL 0x3F // (RX_ABW-1):0
#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL)
#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL))
// IDR 0x58 // 32 bits [READ ONLY]
// COMP_VERSION 0x5c // 32 bits [READ ONLY]
// DR 0x60 // 16 bits 0x60-0xEC
#define BIT_SHIFT_DR_DR 0
#define BIT_MASK_DR_DR 0xFFFF
#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR)
#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR))
// RX_SAMPLE_DLY 0xF0 // 8 bits
#define BIT_SHIFT_RX_SAMPLE_DLY_RSD 0
#define BIT_MASK_RX_SAMPLE_DLY_RSD 0xFFFF
#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD)
#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD))
// RSVD_0 0xF4 // 32 bits
// RSVD_1 0xF8 // 32 bits
// RSVD_2 0xFC // 32 bits
// SSI0 Pinmux
#define BIT_SHIFT_SSI0_PIN_EN 0
#define BIT_MASK_SSI0_PIN_EN 0x1
#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN)
#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN))
#define BIT_SHIFT_SSI0_PIN_SEL 1
#define BIT_MASK_SSI0_PIN_SEL 0x7
#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL)
#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL))
// SSI1 Pinmux
#define BIT_SHIFT_SSI1_PIN_EN 4
#define BIT_MASK_SSI1_PIN_EN 0x1
#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN)
#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN))
#define BIT_SHIFT_SSI1_PIN_SEL 5
#define BIT_MASK_SSI1_PIN_SEL 0x7
#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL)
#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL))
// SSI2 Pinmux
#define BIT_SHIFT_SSI2_PIN_EN 8
#define BIT_MASK_SSI2_PIN_EN 0x1
#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN)
#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN))
#define BIT_SHIFT_SSI2_PIN_SEL 9
#define BIT_MASK_SSI2_PIN_SEL 0x7
#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL)
#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL))
// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL)
#define BIT_SHIFT_SSI0_MULTI_CS_EN 28
#define BIT_MASK_SSI0_MULTI_CS_EN 0x1
#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN)
#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN))
#define HAL_SSI_READ32(SsiIndex, addr) \
HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE32(SsiIndex, addr, value) \
HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
#define HAL_SSI_READ16(SsiIndex, addr) \
HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE16(SsiIndex, addr, value) \
HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
#define HAL_SSI_READ8(SsiIndex, addr) \
HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
#define HAL_SSI_WRITE8(SsiIndex, addr, value) \
HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
// SSI Pinmux Select
typedef enum _SSI0_PINMUX_SELECT_ {
SSI0_MUX_TO_GPIOE = S0,
SSI0_MUX_TO_GPIOC = S1
}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT;
typedef enum _SSI1_PINMUX_SELECT_ {
SSI1_MUX_TO_GPIOA = S0,
SSI1_MUX_TO_GPIOB = S1,
SSI1_MUX_TO_GPIOD = S2
}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT;
typedef enum _SSI2_PINMUX_SELECT_ {
SSI2_MUX_TO_GPIOG = S0,
SSI2_MUX_TO_GPIOE = S1,
SSI2_MUX_TO_GPIOD = S2
}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT;
typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
SSI0_CS_MUX_TO_GPIOE = S0,
SSI0_CS_MUX_TO_GPIOC = S1
}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT;
typedef enum _SSI_CTRLR0_TMOD_ {
TMOD_TR = 0,
TMOD_TO = 1,
TMOD_RO = 2,
TMOD_EEPROM_R = 3
}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD;
typedef enum _SSI_CTRLR0_SCPOL_ {
SCPOL_INACTIVE_IS_LOW = 0,
SCPOL_INACTIVE_IS_HIGH = 1
}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL;
typedef enum _SSI_CTRLR0_SCPH_ {
SCPH_TOGGLES_IN_MIDDLE = 0,
SCPH_TOGGLES_AT_START = 1
}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH;
typedef enum _SSI_CTRLR0_DFS_ {
DFS_4_BITS = 3,
DFS_5_BITS = 4,
DFS_6_BITS = 5,
DFS_7_BITS = 6,
DFS_8_BITS = 7,
DFS_9_BITS = 8,
DFS_10_BITS = 9,
DFS_11_BITS = 10,
DFS_12_BITS = 11,
DFS_13_BITS = 12,
DFS_14_BITS = 13,
DFS_15_BITS = 14,
DFS_16_BITS = 15,
}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS;
typedef enum _SSI_CTRLR0_CFS_ {
CFS_1_BIT = 0,
CFS_2_BITS = 1,
CFS_3_BITS = 2,
CFS_4_BITS = 3,
CFS_5_BITS = 4,
CFS_6_BITS = 5,
CFS_7_BITS = 6,
CFS_8_BITS = 7,
CFS_9_BITS = 8,
CFS_10_BITS = 9,
CFS_11_BITS = 10,
CFS_12_BITS = 11,
CFS_13_BITS = 12,
CFS_14_BITS = 13,
CFS_15_BITS = 14,
CFS_16_BITS = 15
}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS;
typedef enum _SSI_CTRLR0_SLV_OE_ {
SLV_TXD_ENABLE = 0,
SLV_TXD_DISABLE = 1
}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE;
typedef enum _SSI_ROLE_SELECT_ {
SSI_SLAVE = 0,
SSI_MASTER = 1
}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT;
typedef enum _SSI_FRAME_FORMAT_ {
FRF_MOTOROLA_SPI = 0,
FRF_TI_SSP = 1,
FRF_NS_MICROWIRE = 2,
FRF_RSVD = 3
}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT;
typedef enum _SSI_DMACR_ENABLE_ {
SSI_NODMA = 0,
SSI_RXDMA_ENABLE = 1,
SSI_TXDMA_ENABLE = 2,
SSI_TRDMA_ENABLE = 3
}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE;
typedef enum _SSI_MWCR_HANDSHAKE_ {
MW_HANDSHAKE_DISABLE = 0,
MW_HANDSHAKE_ENABLE = 1
}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE;
typedef enum _SSI_MWCR_DIRECTION_ {
MW_DIRECTION_SLAVE_TO_MASTER = 0,
MW_DIRECTION_MASTER_TO_SLAVE = 1
}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION;
typedef enum _SSI_MWCR_TMOD_ {
MW_TMOD_NONSEQUENTIAL = 0,
MW_TMOD_SEQUENTIAL = 1
}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD;
typedef enum _SSI_DATA_TRANSFER_MECHANISM_ {
SSI_DTM_BASIC,
SSI_DTM_INTERRUPT,
SSI_DTM_DMA
}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM;
_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value);
_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting);
_LONG_CALL_ROM_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role);
_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length);
_LONG_CALL_ROM_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length);
_LONG_CALL_ROM_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex);
_LONG_CALL_ROM_ u32 HalSsiBusyRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiReadableRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor);
_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor);
_LONG_CALL_ROM_ VOID _SsiReadInterrupt(VOID *Adaptor);
_LONG_CALL_ROM_ VOID _SsiWriteInterrupt(VOID *Adaptor);
_LONG_CALL_ u32 _SsiIrqHandle(VOID *Adaptor);
// ROM code patch
VOID _SsiReadInterruptRtl8195a(VOID *Adapter);
VOID _SsiWriteInterruptRtl8195a(VOID *Adapter);
HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter);
HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter);
HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter);
VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
VOID HalSsiTxFIFOThresholdRtl8195a(VOID *Adaptor, u32 txftl);
HAL_Status HalSsiEnterCriticalRtl8195a(VOID * Data);
HAL_Status HalSsiExitCriticalRtl8195a(VOID * Data);
HAL_Status HalSsiIsTimeoutRtl8195a(u32 StartCount, u32 TimeoutCnt);
HAL_Status HalSsiStopRecvRtl8195a(VOID * Data);
#if CONFIG_CHIP_E_CUT
HAL_Status HalSsiPinmuxEnableRtl8195a_V04(VOID *Adaptor);
HAL_Status HalSsiPinmuxDisableRtl8195a_V04(VOID * Adaptor);
VOID _SsiReadInterruptRtl8195a_V04(VOID *Adapter);
VOID _SsiWriteInterruptRtl8195a_V04(VOID *Adapter);
HAL_Status HalSsiInitRtl8195a_V04(VOID *Adaptor);
HAL_Status HalSsiSetFormatRtl8195a_V04(VOID * Adaptor);
HAL_Status HalSsiDeInitRtl8195a_V04(VOID *Adapter);
HAL_Status HalSsiIntReadRtl8195a_V04(VOID *Adapter, VOID *RxData, u32 Length);
HAL_Status HalSsiIntWriteRtl8195a_V04(VOID *Adapter, u8 *pTxData, u32 Length);
HAL_Status HalSsiClockOffRtl8195a_V04(VOID * Adapter);
HAL_Status HalSsiClockOnRtl8195a_V04(VOID * Adapter);
VOID HalSsiSetSclkRtl8195a_V04(VOID *Adapter, u32 ClkRate);
VOID HalSsiTxGdmaLoadDefRtl8195a_V04(IN VOID * Adapter);
VOID HalSsiRxGdmaLoadDefRtl8195a_V04(IN VOID * Adapter);
VOID HalSsiDmaInitRtl8195a_V04(VOID *Adapter);
HAL_Status HalSsiDmaSendRtl8195a_V04(IN VOID * Adapter, IN u8 * pTxData, IN u32 Length);
HAL_Status HalSsiDmaRecvRtl8195a_V04(IN VOID * Adapter, IN u8 * pRxData, IN u32 Length);
HAL_Status HalSsiDmaSendMultiBlockRtl8195a_V04(VOID * Adapter, u8 * pTxData, u32 Length);
HAL_Status HalSsiDmaRecvMultiBlockRtl8195a_V04(VOID * Adapter, u8 * pRxData, u32 Length);
#endif
#ifdef CONFIG_GDMA_EN
VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter);
VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter);
VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length);
HAL_Status HalSsiDmaSendMultiBlockRtl8195a(VOID * Adapter, u8 * pRxData, u32 Length);
HAL_Status HalSsiDmaRecvMultiBlockRtl8195a(VOID * Adapter, u8 * pRxData, u32 Length);
#endif // end of "#ifdef CONFIG_GDMA_EN"
#endif

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USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h Normal file
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USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_timer.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_TIMER_H_
#define _RTL8195A_TIMER_H_
#define TIMER_TICK_US 31
#define TIMER_LOAD_COUNT_OFF 0x00
#define TIMER_CURRENT_VAL_OFF 0x04
#define TIMER_CTL_REG_OFF 0x08
#define TIMER_EOI_OFF 0x0c
#define TIMER_INT_STATUS_OFF 0x10
#define TIMER_INTERVAL 0x14
#define TIMERS_INT_STATUS_OFF 0xa0
#define TIMERS_EOI_OFF 0xa4
#define TIMERS_RAW_INT_STATUS_OFF 0xa8
#define TIMERS_COMP_VER_OFF 0xac
#define MAX_TIMER_VECTOR_TABLE_NUM 6
#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
_LONG_CALL_ u32
HalGetTimerIdRtl8195a(
IN u32 *TimerID
);
_LONG_CALL_ BOOL
HalTimerInitRtl8195a(
IN VOID *Data
);
_LONG_CALL_ u32
HalTimerReadCountRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerIrqClearRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDisRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerEnRtl8195a(
IN u32 TimerId
);
_LONG_CALL_ VOID
HalTimerDumpRegRtl8195a(
IN u32 TimerId
);
// ROM Code patch
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
);
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
);
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
);
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
);
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
);
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
);
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
__weak _LONG_CALL_
VOID
HalTimerIrq2To7HandleV02(
IN VOID *Data
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
HAL_Status
HalTimerInitRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
u32
HalTimerReadCountRtl8195aV02(
IN u32 TimerId
);
__weak _LONG_CALL_
VOID
HalTimerReLoadRtl8195aV02(
IN u32 TimerId,
IN u32 LoadUs
);
__weak _LONG_CALL_ROM_
HAL_Status
HalTimerIrqUnRegisterRtl8195aV02(
IN VOID *Data
);
__weak _LONG_CALL_
VOID
HalTimerDeInitRtl8195aV02(
IN VOID *Data
);
#endif // end of "#ifdef CONFIG_CHIP_C_CUT"
#ifdef CONFIG_CHIP_E_CUT
_LONG_CALL_ VOID
HalTimerReLoadRtl8195a_V04(
IN u32 TimerId,
IN u32 LoadUs
);
_LONG_CALL_ HAL_Status
HalTimerInitRtl8195a_V04(
IN VOID *Data
);
#endif // #ifdef CONFIG_CHIP_E_CUT
// HAL functions wrapper
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
static __inline HAL_Status
HalTimerInit(
IN VOID *Data
)
{
#ifdef CONFIG_CHIP_E_CUT
return (HalTimerInitRtl8195a_V04(Data));
#else
return (HalTimerInitRtl8195a_Patch(Data));
#endif
}
static __inline VOID
HalTimerEnable(
IN u32 TimerId
)
{
HalTimerIrqEnRtl8195a(TimerId);
HalTimerEnRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerDisable(
IN u32 TimerId
)
{
HalTimerDisRtl8195a_Patch(TimerId);
}
static __inline VOID
HalTimerClearIsr(
IN u32 TimerId
)
{
HalTimerClearIsrRtl8195a(TimerId);
}
static __inline VOID
HalTimerReLoad(
IN u32 TimerId,
IN u32 LoadUs
)
{
#ifdef CONFIG_CHIP_E_CUT
HalTimerReLoadRtl8195a_V04(TimerId, LoadUs);
#else
HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
#endif
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195a_Patch(Data);
}
#else
static __inline VOID
HalTimerDeInit(
IN VOID *Data
)
{
HalTimerDeInitRtl8195aV02(Data);
}
#endif // end of "#ifndef CONFIG_CHIP_C_CUT"
#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#endif //_RTL8195A_TIMER_H_

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USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h Normal file
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@ -0,0 +1,716 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_UART_H_
#define _RTL8195A_UART_H_
#define MAX_UART_INDEX 2
#define RUART_DLL_OFF 0x00
#define RUART_DLM_OFF 0x04 //RW, DLAB = 1
#define RUART_INTERRUPT_EN_REG_OFF 0x04 //RW, DLAB = 0
// Define Interrupt Enable Bit
typedef enum {
RU_IER_ERBFI = BIT0, // Enable Received Data Available Interrupt
RU_IER_ETBEI = BIT1, // Enable Transmit Holding Register Empty Interrupt
RU_IER_ELSI = BIT2, // Enable Receiver Line Status Interrupt
RU_IER_EDSSI = BIT3, // Enable Modem Status Interrupt
RU_IER_PTIME = BIT7 // Programmable THRE Interrupt Mode Enable
} RUART_INT_EN;
#define RUART_IER_ERBI BIT0 //BIT0, Enable Received Data Available Interrupt (rx trigger)
#define RUART_IER_ETBEI BIT1 //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty)
#define RUART_IER_ELSI BIT2 //BIT2, Enable Receiver Line Status Interrupt (receiver line status)
#define RUART_IER_EDSSI BIT3 //BIT3, Enable Modem Status Interrupt (modem status transition)
#define RUART_IER_PTIME BIT7 //*BIT7 PTIME, Programmable THRE Interrupt Mode Enable
#define RUART_INT_ID_REG_OFF 0x08 //[R]
// define Log UART Interrupt Indication ID
/*
IIR[3:0]:
0000 = modem status
0001 = no interrupt pending
0010 = THR empty
0100 = received data available
0110 = receiver line status
0111 = busy detect
1100 = character timeout
*/
typedef enum {
RU_IIR_MODEM_STATUS = 0, //Clear to send or data set ready or ring indicator or data carrier detect.
RU_IIR_NO_PENDING = 1,
RU_IIR_THR_EMPTY = 2, // TX FIFO level lower than threshold or FIFO empty
RU_IIR_RX_RDY = 4, // RX data ready
RU_IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt
RU_IIR_BUSY = 7,
RU_IIR_CHAR_TIMEOUT = 12 // timeout: Rx data ready but no read
} RUART_INT_ID;
#define RUART_IIR_INT_PEND 0x01
#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0)
#define RUART_FIFO_CTL_REG_OFF 0x08 //[W]
// Define FIFO Control Register Bits
typedef enum {
RU_FCR_FIFO_EN = BIT0, // FIFO Enable.
RU_FCR_RST_RX = BIT1, // RCVR FIFO Reset, self clear
RU_FCR_RST_TX = BIT2, // XMIT FIFO Reset, self clear
RU_FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty
RU_FCR_TX_TRIG_2CH = BIT4, // TX Empty Trigger: 2 characters in the FIFO
RU_FCR_TX_TRIG_QF = BIT5, // TX Empty Trigger: FIFO 1/4 full
RU_FCR_TX_TRIG_HF = (BIT5|BIT4), // TX Empty Trigger: FIFO 1/2 full
RU_FCR_TX_TRIG_MASK = (BIT5|BIT4), // TX Empty Trigger Bit Mask
RU_FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO
RU_FCR_RX_TRIG_QF = BIT6, // RCVR Trigger: FIFO 1/4 full
RU_FCR_RX_TRIG_HF = BIT7, // RCVR Trigger: FIFO 1/2 full
RU_FCR_RX_TRIG_AF = (BIT7|BIT6), // RCVR Trigger: FIFO 2 less than full
RU_FCR_RX_TRIG_MASK = (BIT7|BIT6) // RCVR Trigger bits Mask
} RUART_FIFO_CTRL;
#define RUART_FIFO_CTL_REG_FIFO_ENABLE BIT0 //BIT0, FIFO Enable
#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO BIT1 //BIT1, Write 1 clear
#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO BIT2 //BIT2, Write 1 clear
#define RUART_FIFO_CTL_REG_DMA_ENABLE BIT3 //BIT3 DMAM, DMA Mode
#define RUART_FIFO_CTL_REG_TET (0x03<<4) //BIT4..5 TET, TX Empty Trigger: 00 = FIFO empty, 01 = 2 characters in the FIFO, 10 = FIFO 1/4 full, 11 = FIFO 1/2 full
#define RUART_FIFO_CTL_REG_RT (0x03<<6) //BIT6..7 RT, RCVR Trigger: 00 = FIFO empty, 01 = 2 characters in the FIFO, 10 = FIFO 1/4 full, 11 = FIFO 1/2 full
#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9
#define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1
#define RUART_MODEM_CTL_REG_OFF 0x10
#define RUART_MCR_DTR BIT0 //BIT0, Data Terminal Ready (DTR)
#define RUART_MCR_RTS BIT1 //*BIT1 Request to Send (RTS)
#define RUART_MCR_OUT1 BIT2 //*BIT2 User designated Output 1 (OUT1)
#define RUART_MCR_OUT2 BIT3 //*BIT3 User designated Output 2 (OUT2)
#define RUART_MCR_LOOPBACK BIT4 //*BIT4, LoopBack Bit (LOOPBACK)
#define RUART_MCL_AUTOFLOW_ENABLE BIT5 //BIT5, 0x20
#define RUART_LINE_CTL_REG_OFF 0x0C
// Define Line Control Register Bits
typedef enum {
RU_LCR_DLS_5B = 0, // Data Length: 5 bits
RU_LCR_DLS_6B = BIT0, // Data Length: 6 bits
RU_LCR_DLS_7B = BIT1, // Data Length: 7 bits
RU_LCR_DLS_8B = (BIT1|BIT0), // Data Length: 7 bits
RU_LCR_STOP_1B = 0, // Number of stop bits: 1
RU_LCR_STOP_2B = BIT2, // Number of stop bits: 1.5(data len=5) or 2
RU_LCR_PARITY_NONE = 0, // Parity Enable: 0
RU_LCR_PARITY_ODD = BIT3, // Parity Enable: 1, Even Parity: 0
RU_LCR_PARITY_EVEN = (BIT4|BIT3), // Parity Enable: 1, Even Parity: 1
RU_LCR_BC = BIT6, // Break Control Bit
RU_LCR_DLAB = BIT7 // Divisor Latch Access Bit
} RUART_LINE_CTRL;
//*BIT6 Break Control Bit (BC)
//*BIT4 Even Parity Select (EPS)
//*BIT3 Parity Enable (PEN)
//*BIT2 Number of stop bits (STOP)
//*BIT1..0 Data Length Select (DLS)
#define RUART_LINE_CTL_REG_DLAB_ENABLE BIT7 //BIT7, 0x80
#define RUART_LINE_STATUS_REG_OFF 0x14
// Define Line Status Bit
typedef enum {
RU_LSR_DR = BIT0, // Data Ready bit
RU_LSR_OE = BIT1, // Overrun error bit
RU_LSR_PE = BIT2, // Parity Error bit
RU_LSR_FE = BIT3, // Framing Error bit
RU_LSR_BI = BIT4, // Break Interrupt bit
RU_LSR_THRE = BIT5, // Transmit Holding Register Empty bit(IER_PTIME=0)
RU_LSR_FIFOF = BIT5, // Transmit FIFO Full bit(IER_PTIME=1)
RU_LSR_TEMT = BIT6, // Transmitter Empty bit
RU_LSR_RFE = BIT7 // Receiver FIFO Error bit
} RUART_LINE_STATUS;
#define RUART_LINE_STATUS_REG_DR BIT0 //BIT0, Data Ready indicator
#define RUART_LINE_STATUS_ERR_OVERRUN BIT1 //BIT1, Over Run
#define RUART_LINE_STATUS_ERR_PARITY BIT2 //BIT2, Parity error
#define RUART_LINE_STATUS_ERR_FRAMING BIT3 //BIT3, Framing error
#define RUART_LINE_STATUS_ERR_BREAK BIT4 //BIT4, Break interrupt error
#define RUART_LINE_STATUS_REG_THRE BIT5 //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable
#define RUART_LINE_STATUS_REG_TEMT BIT6 //BIT6, 0x40, Transmitter Empty indicator(bit)
#define RUART_LINE_STATUS_ERR_RXFIFO BIT7 //BIT7, RX FIFO error
#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \
RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
RUART_LINE_STATUS_ERR_RXFIFO) //Line status error
#define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register
//* BIT7 Data Carrier Detect (DCD)
//* BIT6 Ring Indicator (RI)
//* BIT5 Data Set Ready (DSR)
//* BIT4 Clear to Send (CTS)
//* BIT3 Delta Data Carrier Detect (DDCD)
//* BIT2 Trailing Edge of Ring Indicator (TERI)
//* BIT1 Delta Data Set Ready (DDSR)
//* BIT0 Delta Clear to Send (DCTS)
#define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register
#define RUART_SP_REG_RXBREAK_INT_STATUS BIT7 //BIT7, 0x80, Write 1 clear
#define RUART_SP_REG_DBG_SEL (0x0F<<8) //[11:8], Debug port selection
#define RUART_SP_REG_XFACTOR_ADJ (0x7FF<<16) //[26:16]
#define RUART_STS_REG_OFF 0x20
#define RUART_STS_REG_RESET_RCV BIT3 //BIT3, 0x08, Reset Uart Receiver
#define RUART_STS_REG_XFACTOR 0xF<<4
#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register
#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register
#define RUART_MISC_CTL_REG_OFF 0x28
#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3
#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8
#define RUART_DEBUG_REG_OFF 0x3C
// RUART_LINE_CTL_REG_OFF (0x0C)
#define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits
#define BIT_MASK_LCR_WLS_8BITS 0x1
#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS)
#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS))
#define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit
#define BIT_MASK_LCR_STB_EN 0x1
#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB)
#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB))
#define BIT_SHIFT_LCR_PARITY_EN 3
#define BIT_MASK_LCR_PARITY_EN 0x1
#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN)
#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN))
#define BIT_SHIFT_LCR_PARITY_TYPE 4
#define BIT_MASK_LCR_PARITY_TYPE 0x1
#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE)
#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE))
#define BIT_SHIFT_LCR_STICK_PARITY_EN 5
#define BIT_MASK_LCR_STICK_PARITY_EN 0x1
#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN)
#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN))
#define BIT_SHIFT_LCR_BREAK_CTRL 6
#define BIT_MASK_LCR_BREAK_CTRL 0x1
#define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL)
#define RUART_BAUD_RATE_2400 2400
#define RUART_BAUD_RATE_4800 4800
#define RUART_BAUD_RATE_9600 9600
#define RUART_BAUD_RATE_19200 19200
#define RUART_BAUD_RATE_38400 38400
#define RUART_BAUD_RATE_57600 57600
#define RUART_BAUD_RATE_115200 115200
#define RUART_BAUD_RATE_921600 921600
#define RUART_BAUD_RATE_1152000 1152000
#define HAL_RUART_READ32(UartIndex, addr) \
HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE32(UartIndex, addr, value) \
HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define HAL_RUART_READ16(UartIndex, addr) \
HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE16(UartIndex, addr, value) \
HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define HAL_RUART_READ8(UartIndex, addr) \
HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
#define HAL_RUART_WRITE8(UartIndex, addr, value) \
HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
#define UART_OVSR_POOL_MIN 1000
#define UART_OVSR_POOL_MAX 2090
#define DIVISOR_RESOLUTION 10
#define JITTER_LIMIT 100
#define UART_SCLK ((HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & (1<<17))? (100000000) : (200000000*5/12))
typedef struct _RUART_SPEED_SETTING_ {
u32 BaudRate;
u32 Ovsr;
u32 Div;
u32 Ovsr_adj;
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
u8 Ovsr_adj_max_bits; // 9: No parity, 10: with Parity
u8 Ovsr_adj_bits;
u16 *Ovsr_adj_map;
u32 max_err; // 10 ~ 100: 30
u32 Ovsr_min; // 10 ~ 20: 1000
u32 Ovsr_max; // 10 ~ 20: 2000
u32 divisor_resolution; // 1 ~ 20: 10
u32 jitter_lim; // 50 ~ 100: 100
u32 sclk; // 83.33333 MHz
#endif
}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING;
typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ {
OneByte = 0x00, // 1
FourBytes = 0x01, // 4
EightBytes = 0x10, // 8
FourteenBytes = 0x11 // 14
}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL;
typedef enum _RUART0_PINMUX_SELECT_ {
RUART0_MUX_TO_GPIOC = S0,
RUART0_MUX_TO_GPIOE = S1,
RUART0_MUX_TO_GPIOA = S2
}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT;
typedef enum _RUART1_PINMUX_SELECT_ {
RUART1_MUX_TO_GPIOD = S0,
RUART1_MUX_TO_GPIOE = S1,
RUART1_MUX_TO_GPIOB = S2
}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT;
typedef enum _RUART2_PINMUX_SELECT_ {
RUART2_MUX_TO_GPIOA = S0,
RUART2_MUX_TO_GPIOC = S1,
RUART2_MUX_TO_GPIOD = S2
}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT;
typedef enum _RUART_FLOW_CONTROL_ {
AUTOFLOW_DISABLE = 0,
AUTOFLOW_ENABLE = 1
}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL;
typedef enum _RUART_WORD_LEN_SEL_ {
RUART_WLS_7BITS = 0,
RUART_WLS_8BITS = 1
}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL;
typedef enum _RUART_STOP_BITS_ {
RUART_STOP_BIT_1 = 0,
RUART_STOP_BIT_2 = 1
}RUART_STOP_BITS, *PRUART_STOP_BITS;
typedef enum _RUART_PARITY_CONTROL_ {
RUART_PARITY_DISABLE = 0,
RUART_PARITY_ENABLE = 1
}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL;
typedef enum _RUART_PARITY_TYPE_ {
RUART_ODD_PARITY = 0,
RUART_EVEN_PARITY = 1
}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE;
typedef enum _RUART_STICK_PARITY_CONTROL_ {
RUART_STICK_PARITY_DISABLE = 0,
RUART_STICK_PARITY_ENABLE = 1
}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL;
typedef enum _UART_INT_ID_ {
ModemStatus = 0,
TxFifoEmpty = 1,
ReceiverDataAvailable = 2,
ReceivLineStatus = 3,
TimeoutIndication = 6
}UART_INT_ID, *PUART_INT_ID;
typedef enum _HAL_UART_State_
{
HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet
HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use
HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration
HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX
HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX
HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX
HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout
HAL_UART_STATE_ERROR = 0x40 // UART Error
}HAL_UART_State, *PHAL_UART_State;
typedef enum _HAL_UART_Status_
{
HAL_UART_STATUS_OK = 0x00, // Transfer OK
HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout
HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run
HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error
HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error
HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt
HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error
HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error
}HAL_UART_Status, *PHAL_UART_Status;
u32
HalRuartGetDebugValueRtl8195a(
IN VOID* Data,
IN u32 DbgSel
);
#if 0
u32
FindElementIndex(
u32 Element,
u32* Array
);
#endif
VOID
RuartResetRxFifoRtl8195a(
IN u8 UartIndex
);
#if 0
VOID
RuartBusDomainEnableRtl8195a(
IN u8 UartIndex
);
#endif
HAL_Status
HalRuartResetRxFifoRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartInitRtl8195a(
IN VOID *Data
);
VOID
HalRuartDeInitRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartPutCRtl8195a(
IN VOID *Data,
IN u8 TxData
);
u32
HalRuartSendRtl8195a(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length,
IN u32 Timeout
);
HAL_Status
HalRuartIntSendRtl8195a(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
HAL_Status
HalRuartDmaSendRtl8195a(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
HAL_Status
HalRuartStopSendRtl8195a(
IN VOID *Data // PHAL_RUART_ADAPTER
);
HAL_Status
HalRuartGetCRtl8195a(
IN VOID *Data,
OUT u8 *pRxByte
);
u32
HalRuartRecvRtl8195a(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length,
IN u32 Timeout
);
HAL_Status
HalRuartIntRecvRtl8195a(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
HAL_Status
HalRuartDmaRecvRtl8195a(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
HAL_Status
HalRuartStopRecvRtl8195a(
IN VOID *Data // PHAL_RUART_ADAPTER
);
u8
HalRuartGetIMRRtl8195a(
IN VOID *Data
);
_LONG_CALL_ROM_ VOID
HalRuartSetIMRRtl8195a(
IN VOID *Data
);
VOID
HalRuartDmaInitRtl8195a(
IN VOID *Data
);
VOID
HalRuartRTSCtrlRtl8195a(
IN VOID *Data,
IN BOOLEAN RtsCtrl
);
VOID
HalRuartRegIrqRtl8195a(
IN VOID *Data
);
VOID
HalRuartIntEnableRtl8195a(
IN VOID *Data
);
VOID
HalRuartIntDisableRtl8195a(
IN VOID *Data
);
VOID
HalRuartAdapterLoadDefRtl8195a(
IN VOID *pAdp,
IN u8 UartIdx
);
VOID
HalRuartTxGdmaLoadDefRtl8195a(
IN VOID *pAdp,
IN VOID *pCfg
);
VOID
HalRuartRxGdmaLoadDefRtl8195a(
IN VOID *pAdp,
IN VOID *pCfg
);
_LONG_CALL_ HAL_Status HalRuartIntSendRtl8195aV02(
IN VOID *Data, // PHAL_RUART_ADAPTER
IN u8 *pTxData, // the Buffer to be send
IN u32 Length // the length of data to be send
);
_LONG_CALL_ HAL_Status
HalRuartIntRecvRtl8195aV02(
IN VOID *Data, ///< RUART Adapter
IN u8 *pRxData, ///< Rx buffer
IN u32 Length // buffer length
);
_LONG_CALL_ s32
FindElementIndex_v02(
u32 Element, ///< RUART Baudrate
u32* Array, ///< Pre-defined Baudrate Array
u32 ElementNo
);
_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data);
// New added function 2015/04/20
HAL_Status
HalRuartResetTxFifoRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartResetRxFifoRtl8195a_Patch(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartResetTRxFifoRtl8195a(
IN VOID *Data ///< RUART Adapter
);
HAL_Status
HalRuartSetBaudRateRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartEnableRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartDisableRtl8195a(
IN VOID *Data
);
HAL_Status
HalRuartFlowCtrlRtl8195a(
IN VOID *Data
);
u32
_UartTxDmaIrqHandle_Patch(
IN VOID *Data
);
u32
_UartRxDmaIrqHandle_Patch(
IN VOID *Data
);
HAL_Status
HalRuartDmaSendRtl8195a_Patch(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
HAL_Status
HalRuartDmaRecvRtl8195a_Patch(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length
);
HAL_Status
HalRuartMultiBlkDmaSendRtl8195a(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
HAL_Status
HalRuartMultiBlkDmaRecvRtl8195a(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length
);
HAL_Status
RuartIsTimeout (
u32 StartCount,
u32 TimeoutCnt
);
HAL_Status
HalRuartStopRecvRtl8195a_Patch(
IN VOID *Data
);
HAL_Status
HalRuartStopSendRtl8195a_Patch(
IN VOID *Data
);
VOID
HalRuartEnterCriticalRtl8195a(
IN VOID *Data
);
VOID
HalRuartExitCriticalRtl8195a(
IN VOID *Data
);
#if CONFIG_CHIP_E_CUT
_LONG_CALL_ HAL_Status
HalRuartResetTxFifoRtl8195a_V04(
IN VOID *Data ///< RUART Adapter
);
_LONG_CALL_ HAL_Status
HalRuartResetRxFifoRtl8195a_V04(
IN VOID *Data ///< RUART Adapter
);
_LONG_CALL_ HAL_Status
HalRuartResetTRxFifoRtl8195a_V04(
IN VOID *Data ///< RUART Adapter
);
_LONG_CALL_ HAL_Status
HalRuartSetBaudRateRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartInitRtl8195a_V04(
IN VOID *Data ///< RUART Adapter
);
_LONG_CALL_ HAL_Status
HalRuartEnableRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartDisableRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartFlowCtrlRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ u32
_UartTxDmaIrqHandle_V04(
IN VOID *Data
);
_LONG_CALL_ u32
_UartRxDmaIrqHandle_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartDmaSendRtl8195a_V04(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
_LONG_CALL_ HAL_Status
HalRuartDmaRecvRtl8195a_V04(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length
);
_LONG_CALL_ HAL_Status
HalRuartMultiBlkDmaSendRtl8195a_V04(
IN VOID *Data,
IN u8 *pTxData,
IN u32 Length
);
_LONG_CALL_ HAL_Status
HalRuartMultiBlkDmaRecvRtl8195a_V04(
IN VOID *Data,
IN u8 *pRxData,
IN u32 Length
);
_LONG_CALL_ HAL_Status
HalRuartStopRecvRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ HAL_Status
HalRuartStopSendRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartEnterCriticalRtl8195a_V04(
IN VOID *Data
);
_LONG_CALL_ VOID
HalRuartExitCriticalRtl8195a_V04(
IN VOID *Data
);
#endif // #if CONFIG_CHIP_E_CUT
#endif

432
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_USB_H_
#define _RTL8195A_USB_H_
// common command for USB
#define USB_CMD_TX_ETH 0x83 // request to TX a 802.3 packet
#define USB_CMD_TX_WLN 0x81 // request to TX a 802.11 packet
#define USB_CMD_H2C 0x11 // H2C(host to device) command packet
#define USB_CMD_MEMRD 0x51 // request to read a block of memory data
#define USB_CMD_MEMWR 0x53 // request to write a block of memory
#define USB_CMD_MEMST 0x55 // request to set a block of memory with a value
#define USB_CMD_STARTUP 0x61 // request to jump to the start up function
#define USB_CMD_RX_ETH 0x82 // indicate a RX 802.3 packet
#define USB_CMD_RX_WLN 0x80 // indicate a RX 802.11 packet
#define USB_CMD_C2H 0x10 // C2H(device to host) command packet
#define USB_CMD_MEMRD_RSP 0x50 // response to memory block read command
#define USB_CMD_MEMWR_RSP 0x52 // response to memory write command
#define USB_CMD_MEMST_RSP 0x54 // response to memory set command
#define USB_CMD_STARTED 0x60 // indicate the program has jumped to the given function
// TODO: This data structer just for test, we should modify it for the normal driver
typedef struct _USB_TX_DESC{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 rsvd0:24;
#else
u32 rsvd0:24;
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 rsvd1;
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} USB_TX_DESC, *PUSB_TX_DESC;
#define SIZE_USB_TX_DESC sizeof(USB_TX_DESC)
// TX Desc for Memory Write command
typedef struct _USB_TX_DESC_MW{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 reply:1; // bit[8], request to send a reply message
u32 rsvd0:23;
#else
u32 rsvd0:23;
u32 reply:1; // bit[8], request to send a reply message
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_addr; // memory write start address
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 write_len:16; // bit[15:0], the length to write
u32 rsvd2:16; // bit[31:16]
#else
u32 rsvd2:16; // bit[31:16]
u32 write_len:16; // bit[15:0], the length to write
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} USB_TX_DESC_MW, *PUSB_TX_DESC_MW;
// TX Desc for Memory Read command
typedef struct _USB_TX_DESC_MR{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 rsvd0:24;
#else
u32 rsvd0:24;
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_addr; // memory write start address
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 read_len:16; // bit[15:0], the length to read
u32 rsvd2:16; // bit[31:16]
#else
u32 rsvd2:16; // bit[31:16]
u32 read_len:16; // bit[15:0], the length to read
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} USB_TX_DESC_MR, *PUSB_TX_DESC_MR;
// TX Desc for Memory Set command
typedef struct _USB_TX_DESC_MS{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 data:8; // bit[8:15], the value to be written to the memory
u32 reply:1; // bit[16], request to send a reply message
u32 rsvd0:15;
#else
u32 rsvd0:15;
u32 reply:1; // bit[16], request to send a reply message
u32 data:8; // bit[8:15], the value to be written to the memory
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_addr; // memory write start address
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 write_len:16; // bit[15:0], the length to write
u32 rsvd2:16; // bit[31:16]
#else
u32 rsvd2:16; // bit[31:16]
u32 write_len:16; // bit[15:0], the length to write
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} USB_TX_DESC_MS, *PUSB_TX_DESC_MS;
// TX Desc for Jump to Start command
typedef struct _USB_TX_DESC_JS{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 txpktsize:16; // bit[15:0]
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
#else
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
u32 txpktsize:16; // bit[15:0]
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the packet type
u32 rsvd0:24;
#else
u32 rsvd0:24;
u32 type:8; // bit[7:0], the packet type
#endif
// u4Byte 2
u32 start_fun; // the pointer of the startup function
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} USB_TX_DESC_JS, *PUSB_TX_DESC_JS;
typedef struct _USB_RX_DESC{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:6; // bit[29:24]
u32 icv:1; // bit[30], ICV error
u32 crc:1; // bit[31], CRC error
#else
u32 crc:1; // bit[31], CRC error
u32 icv:1; // bit[30], ICV error
u32 rsvd0:6; // bit[29:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 rsvd2;
// u4Byte 3
u32 rsvd3;
// u4Byte 4
u32 rsvd4;
// u4Byte 5
u32 rsvd5;
} USB_RX_DESC, *PUSB_RX_DESC;
// For memory read command
typedef struct _USB_RX_DESC_MR{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:8; // bit[31:24]
#else
u32 rsvd0:8; // bit[31:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 start_addr;
// u4Byte 3
u32 rsvd2;
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} USB_RX_DESC_MR, *PUSB_RX_DESC_MR;
// For memory write reply command
typedef struct _USB_RX_DESC_MW{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:8; // bit[31:24]
#else
u32 rsvd0:8; // bit[31:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 start_addr;
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 write_len:16; // bit[15:0], the type of this packet
u32 result:8; // bit[23:16], the result of memory write command
u32 rsvd2:8; // bit[31:24]
#else
u32 rsvd2:8; // bit[31:24]
u32 result:8; // bit[23:16], the result of memory write command
u32 write_len:16; // bit[15:0], the type of this packet
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} USB_RX_DESC_MW, *PUSB_RX_DESC_MW;
// For memory set reply command
typedef struct _USB_RX_DESC_MS{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:8; // bit[31:24]
#else
u32 rsvd0:8; // bit[31:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 start_addr;
// u4Byte 3
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 write_len:16; // bit[15:0], the type of this packet
u32 result:8; // bit[23:16], the result of memory write command
u32 rsvd2:8; // bit[31:24]
#else
u32 rsvd2:8; // bit[31:24]
u32 result:8; // bit[23:16], the result of memory write command
u32 write_len:16; // bit[15:0], the type of this packet
#endif
// u4Byte 4
u32 rsvd3;
// u4Byte 5
u32 rsvd4;
} USB_RX_DESC_MS, *PUSB_RX_DESC_MS;
// For firmware ready reply command
typedef struct _USB_RX_DESC_FS{
// u4Byte 0
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 pkt_len:16; // bit[15:0], the packet size
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 rsvd0:8; // bit[31:24]
#else
u32 rsvd0:8; // bit[31:24]
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
u32 pkt_len:16; // bit[15:0], the packet size
#endif
// u4Byte 1
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
u32 type:8; // bit[7:0], the type of this packet
u32 rsvd1:24; // bit[31:8]
#else
u32 rsvd1:24; // bit[31:8]
u32 type:8; // bit[7:0], the type of this packet
#endif
// u4Byte 2
u32 rsvd2;
// u4Byte 3
u32 rsvd3;
// u4Byte 4
u32 rsvd4;
// u4Byte 5
u32 rsvd5;
} USB_RX_DESC_FS, *PUSB_RX_DESC_FS;
#define SIZE_USB_RX_DESC sizeof(USB_RX_DESC)
#endif // #ifndef _RTL8195A_USB_H_

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USDK/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_wdt.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2014 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTL8195A_WDT_H_
#define _RTL8195A_WDT_H_
#define WDGTIMERELY (10*1024) //us
typedef struct _WDG_REG_ {
u16 WdgScalar;
u8 WdgEnByte;
u8 WdgClear:1;
u8 WdgCunLimit:4;
u8 Rsvd:1;
u8 WdgMode:1;
u8 WdgToISR:1;
}WDG_REG, *PWDG_REG;
typedef struct _WDG_ADAPTER_ {
WDG_REG Ctrl;
IRQ_HANDLE IrqHandle;
TIMER_ADAPTER WdgGTimer;
VOID (*UserCallback)(u32 callback_id); // User callback function
u32 callback_id;
}WDG_ADAPTER, *PWDG_ADAPTER;
typedef enum _WDG_CNTLMT_ {
CNT1H = 0,
CNT3H = 1,
CNT7H = 2,
CNTFH = 3,
CNT1FH = 4,
CNT3FH = 5,
CNT7FH = 6,
CNTFFH = 7,
CNT1FFH = 8,
CNT3FFH = 9,
CNT7FFH = 10,
CNTFFFH = 11
}WDG_CNTLMT, *PWDG_CNTLMT;
typedef enum _WDG_MODE_ {
INT_MODE = 0,
RESET_MODE = 1
}WDG_MODE, *PWDG_MODE;
extern VOID
WDGInitial(
IN u32 Period
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGIrqInitial(
VOID
);
extern VOID
WDGStop(
VOID
);
extern VOID
WDGRefresh(
VOID
);
extern VOID
WDGIrqCallBackReg(
IN VOID *CallBack,
IN u32 Id
);
#endif //_RTL8195A_WDT_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "platform_autoconf.h"
#include "diag.h"
#include "rtl8195a_adc.h"
#include "hal_adc.h"
#ifdef CONFIG_ADC_EN
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCInit8195a(
IN VOID *Data
)
{
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
u32 AdcTempDat;
u8 AdcTempIdx = pHalAdcInitData->ADCIdx;
/* Enable ADC power cut */
/*
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat |= BIT_ADC_PWR_AUTO;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
*/
/* ADC Control register set-up*/
AdcTempDat = 0;
AdcTempDat |= (BIT_CTRL_ADC_COMP_ONLY(pHalAdcInitData->ADCCompOnly) |
BIT_CTRL_ADC_ONESHOT(pHalAdcInitData->ADCOneShotEn) |
BIT_CTRL_ADC_OVERWRITE(pHalAdcInitData->ADCOverWREn) |
BIT_CTRL_ADC_ENDIAN(pHalAdcInitData->ADCEndian) |
BIT_CTRL_ADC_BURST_SIZE(pHalAdcInitData->ADCBurstSz) |
BIT_CTRL_ADC_THRESHOLD(pHalAdcInitData->ADCOneShotTD) |
BIT_CTRL_ADC_DBG_SEL(pHalAdcInitData->ADCDbgSel));
HAL_ADC_WRITE32(REG_ADC_CONTROL,AdcTempDat);
DBG_8195A_ADC_LVL(HAL_ADC_LVL,"REG_ADC_CONTROL:%x\n", HAL_ADC_READ32(REG_ADC_CONTROL));
/* ADC compare value and compare method setting*/
switch (AdcTempIdx) {
case ADC0_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
AdcTempDat &= ~(BIT_ADC_COMP_TH_0(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_0(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
break;
case ADC1_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
AdcTempDat &= ~(BIT_ADC_COMP_TH_1(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_1(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
break;
case ADC2_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
AdcTempDat &= ~(BIT_ADC_COMP_TH_2(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_2(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
break;
case ADC3_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
AdcTempDat &= ~(BIT_ADC_COMP_TH_3(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_3(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
break;
default:
return _EXIT_FAILURE;
}
/* ADC compare mode setting */
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_SET);
AdcTempDat &= (~(0x01 << pHalAdcInitData->ADCIdx));
AdcTempDat |= (BIT_CTRL_ADC_COMP_0_EN(pHalAdcInitData->ADCCompCtrl) <<
pHalAdcInitData->ADCIdx);
HAL_ADC_WRITE32(REG_ADC_COMP_SET, AdcTempDat);
/* ADC audio mode set-up */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
AdcTempDat &= ~(BIT_ADC_AUDIO_EN);
AdcTempDat |= BIT_CTRL_ADC_AUDIO_EN(pHalAdcInitData->ADCAudioEn);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
/* ADC enable manually setting */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
AdcTempDat &= ~(BIT_ADC_EN_MANUAL);
AdcTempDat |= BIT_CTRL_ADC_EN_MANUAL(pHalAdcInitData->ADCEnManul);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
/* ADC analog parameter 0 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
//AdcTempDat |= (BIT0);
if (pHalAdcInitData->ADCInInput == 1){
AdcTempDat &= (~BIT14);
}
else {
AdcTempDat |= (BIT14);
}
AdcTempDat &= (~(BIT3|BIT2));
/* Adjust VCM for C-Cut*/
#ifdef CONFIG_CHIP_C_CUT
AdcTempDat |= (BIT22);
#endif
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
/* ADC analog parameter 1 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
AdcTempDat &= (~BIT1);
AdcTempDat |= (BIT2|BIT0);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
DBG_ADC_INFO("AD1:%x\n", AdcTempDat);
/* ADC analog parameter 2 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
AdcTempDat = 0x67884400;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD2, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
/* ADC analog parameter 3 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
AdcTempDat = 0x77780039;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD3, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
/* ADC analog parameter 4 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
AdcTempDat = 0x0004d501;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD4, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
/* ADC analog parameter 5 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
AdcTempDat = 0x1E010800;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD5, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCDeInit8195a(
IN VOID *Data
)
{
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat &= ~(BIT_ADC_PWR_AUTO);
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCEnableRtl8195a(
IN VOID *Data
){
//PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
u32 AdcTempDat;
DBG_ADC_INFO("HalADCEnableRtl8195a\n");
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat &= (~BIT_ADC_PWR_AUTO);
AdcTempDat |= 0x02;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat |= 0x04;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat &= (~0x08);
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER);
DBG_ADC_INFO("HalADCEnableRtl8195a, power reg:%x\n",AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCIntrCtrl8195a(
IN VOID *Data
){
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
HAL_ADC_WRITE32(REG_ADC_INTR_EN, pHalAdcInitData->ADCIntrMSK);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReceiveRtl8195a
//
// Description:
// Directly read one data byte a I2C data fifo.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The first data fifo content.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u32
HalADCReceiveRtl8195a(
IN VOID *Data
){
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(REG_ADC_FIFO_READ);
return (AdcTempDat);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReadRegRtl8195a
//
// Description:
// Directly read a I2C register according to the register offset.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
// [in] I2CReg -
// The I2C register offset.
//
// Return:
// The register content in u32 format.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u32
HalADCReadRegRtl8195a(
IN VOID *Data,
IN u8 I2CReg
){
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(I2CReg);
return (AdcTempDat);
}
#endif // CONFIG_ADC_EN

269
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_dac.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_dac.h"
#include "hal_dac.h"
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalDACInit8195a
//
// Description:
// To initialize DAC module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The DAC parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-15.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACInit8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
u8 DacTempIdx = pHalDacInitData->DACIdx;
/* Enable DAC power cut */
DacTempDat = HAL_DAC_READ32(0, REG_DAC_PWR_CTRL);
DacTempDat |= BIT_DAC_PWR_AUTO;
HAL_DAC_WRITE32(0, REG_DAC_PWR_CTRL, DacTempDat);
/* Disable DAC module first */
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, 0);
/* Setup DAC module */
DacTempDat = 0;
DacTempDat |= (BIT_CTRL_DAC_SPEED(pHalDacInitData->DACDataRate) |
BIT_CTRL_DAC_ENDIAN(pHalDacInitData->DACEndian) |
BIT_CTRL_DAC_FILTER_SETTLE(pHalDacInitData->DACFilterSet) |
BIT_CTRL_DAC_BURST_SIZE(pHalDacInitData->DACBurstSz) |
BIT_CTRL_DAC_DBG_SEL(pHalDacInitData->DACDbgSel) |
BIT_CTRL_DAC_DSC_DBG_SEL(pHalDacInitData->DACDscDbgSel) |
BIT_CTRL_DAC_BYPASS_DSC(pHalDacInitData->DACBPDsc) |
BIT_CTRL_DAC_DELTA_SIGMA(pHalDacInitData->DACDeltaSig));
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACDeInit8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
DacTempDat = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL);
DacTempDat &= (~BIT_DAC_FIFO_EN);
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL ,DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACEnableRtl8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
u8 DacTempIdx = pHalDacInitData->DACIdx;
DacTempDat = HAL_DAC_READ32(DacTempIdx, REG_DAC_CTRL);
DacTempDat &= (~BIT_DAC_FIFO_EN);
DacTempDat |= BIT_CTRL_DAC_FIFO_EN(pHalDacInitData->DACEn);
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACIntrCtrl8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, pHalDacInitData->DACIntrMSK);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReceiveRtl8195a
//
// Description:
// Directly read one data byte a I2C data fifo.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The first data fifo content.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u8
HalDACSendRtl8195a(
IN VOID *Data
){
return (0);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalDACReadRegRtl8195a
//
// Description:
//
//
// Arguments:
// [in] VOID *Data -
// The DAC parameter data struct.
// [in] I2CReg -
// The DAC register offset.
//
// Return:
// The DAC register content in u32 format.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-15.
//
//---------------------------------------------------------------------------------------------------
u32
HalDACReadRegRtl8195a(
IN VOID *Data,
IN u8 I2CReg
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
//DBG_8195A_DAC("dac read reg idx:%x\n",pHalDacInitData->DACIdx);
//DBG_8195A_DAC("dac read reg offset:%x\n",I2CReg);
return (u32)HAL_DAC_READ32(pHalDacInitData->DACIdx, I2CReg);
}

295
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_gdma.h"
#include "hal_gdma.h"
#ifdef CONFIG_GDMA_EN
#ifndef CONFIG_CHIP_E_CUT
BOOL
HalGdmaChBlockSetingRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 ChEn = pHalGdmaAdapter->ChEn;
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
u8 PendingIsrIndex;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!\n");
HalGdmaChDisRtl8195a(Data);
}
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
u32 PendRaw, PendStstus;
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
//4 Clear Pending Isr
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
(PendStstus & (GdmaChIsrBitmap))
);
}
}
//4 Fill in SARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChSar)
);
//4 Fill in DARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChDar)
);
//4 3) Process CTLx
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
//4 Clear Config low register bits
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
BIT_INVC_CTLX_LO_DINC &
BIT_INVC_CTLX_LO_SINC &
BIT_INVC_CTLX_LO_DEST_MSIZE &
BIT_INVC_CTLX_LO_SRC_MSIZE &
BIT_INVC_CTLX_LO_TT_FC &
BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
//4 Clear Config upper register bits
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
BIT_INVC_CTLX_UP_DONE);
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
CtlxLow;
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
CtlxUp;
//4 Fill in CTLx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
CtlxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
CtlxUp
);
//4 4) Program CFGx
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
BIT_INVC_CFGX_LO_CH_SUSP &
BIT_INVC_CFGX_LO_HS_SEL_DST &
BIT_INVC_CFGX_LO_HS_SEL_SRC &
BIT_INVC_CFGX_LO_LOCK_CH_L &
BIT_INVC_CFGX_LO_LOCK_B_L &
BIT_INVC_CFGX_LO_LOCK_CH &
BIT_INVC_CFGX_LO_LOCK_B &
BIT_INVC_CFGX_LO_RELOAD_SRC &
BIT_INVC_CFGX_LO_RELOAD_DST);
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
BIT_INVC_CFGX_UP_DS_UPD_EN &
BIT_INVC_CFGX_UP_SS_UPD_EN &
BIT_INVC_CFGX_UP_SRC_PER &
BIT_INVC_CFGX_UP_DEST_PER);
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
CfgxLow;
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
CfgxUp;
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
CfgxUp
);
//4 Check 4 Bytes Alignment
if ((u32)(pLliEle) & 0x3) {
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!\n",
pHalGdmaAdapter->pLli);
return _FALSE;
}
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
pLliEle
);
//4 Update the first llp0
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
while (MultiBlockCount > 1) {
MultiBlockCount--;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pLliEle = pGdmaChLli->pLliEle;
if (NULL == pLliEle) {
DBG_GDMA_ERR("pLliEle Null Point!\n");
return _FALSE;
}
//4 Clear the last element llp enable bit
if (1 == MultiBlockCount) {
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
}
}
//4 Update block size for transfer
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
//4 Update tje Lli and Block size list point to next llp
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
//4 Updatethe Llpx context
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
}
return _TRUE;
}
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
return 1;
} else {
return 0;
}
}
#endif
#endif // CONFIG_GDMA_EN

56
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gpio.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_gpio.h"
#include "rtl8195a_gpio.h"
#include "gpio_irq_api.h"
#ifdef CONFIG_GPIO_EN
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
/**
* @brief Clear the pending interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
HAL_Status
HAL_GPIO_ClearISR_8195a(
HAL_GPIO_PIN *GPIO_Pin
)
{
u8 port_num;
u8 pin_num;
HAL_GPIO_PIN_MODE pin_mode;
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
pin_mode = GPIO_Pin->pin_mode;
if ((pin_mode & HAL_GPIO_PIN_INT_MODE)==0 || (port_num != GPIO_PORT_A)) {
DBG_GPIO_WARN("HAL_GPIO_ClearISR_8195a: This pin(%x:%x) is'nt an interrupt pin\n", GPIO_Pin->pin_name, GPIO_Pin->pin_mode);
return HAL_ERR_PARA;
}
if (GPIO_Lock() != HAL_OK) {
return HAL_BUSY;
}
// Clear pending interrupt before unmask it
HAL_WRITE32(GPIO_REG_BASE, GPIO_PORTA_EOI, (1<<pin_num));
GPIO_UnLock();
return HAL_OK;
}
#endif // CONFIG_GPIO_EN

543
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_i2c.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#ifdef CONFIG_I2C_EN
/* Used only for A~C Version */
#ifndef CONFIG_CHIP_E_CUT
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CSendRtl8195a
//
// Description:
// Send one byte to the I2C internal fifo, it will generate START and STOP bit
// automatically.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// _EXIT_SUCCESS if the sending succeeded.
// _EXIT_FAILURE if the sending failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CSendRtl8195a_Patch(
IN VOID *Data
){
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 I2CIdx = pHalI2CInitData->I2CIdx;
u8 *pDat = pHalI2CInitData->I2CRWData;
u8 I2CCmd = pHalI2CInitData->I2CCmd;
u8 I2CStop = pHalI2CInitData->I2CStop;
u8 I2CReSTR= pHalI2CInitData->I2CReSTR;
DBG_I2C_INFO("HalI2CSendRtl8195a\n");
DBG_I2C_INFO("I2C Index: %x\n",I2CIdx);
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DATA_CMD,
*(pDat) |
BIT_CTRL_IC_DATA_CMD_RESTART(I2CReSTR)|
BIT_CTRL_IC_DATA_CMD_CMD(I2CCmd) |
BIT_CTRL_IC_DATA_CMD_STOP(I2CStop));
return (HAL_OK);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CMassSendRtl8195a_Patch(
IN VOID *Data
){
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 I2CIdx = pHalI2CInitData->I2CIdx;
u8 I2CCmd = pHalI2CInitData->I2CCmd;
u8 I2CDatLen = pHalI2CInitData->I2CDataLen;
u8 *pDat = pHalI2CInitData->I2CRWData;
u8 I2CStopSet = pHalI2CInitData->I2CStop;
u8 I2CSTP;
u8 I2CReSRT = 0;
u8 DatCnt = 0;
/* Send I2C data one by one. The STOP bit is only used for the last byte.*/
for (DatCnt = 0; DatCnt < I2CDatLen; DatCnt++)
{
I2CSTP = 0;
if ((DatCnt == (I2CDatLen - 1)) && (I2CStopSet != 0)) {
I2CSTP = 1;
}
if ((DatCnt == 0) && ((pHalI2CInitData->RSVD0 & BIT0) != 0)) {
I2CReSRT = 1;
}
else {
I2CReSRT = 0;
}
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DATA_CMD,
*(pDat+DatCnt) |
BIT_CTRL_IC_DATA_CMD_CMD(I2CCmd) |
BIT_CTRL_IC_DATA_CMD_RESTART(I2CReSRT) |
BIT_CTRL_IC_DATA_CMD_STOP(I2CSTP));
}
return HAL_OK;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CInit8195a_Patch(
IN VOID *Data
)
{
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 Master;
u8 I2CIdx;
u8 SpdMd;
u8 AddrMd;
u8 ReSTR;
u8 StartByte;
u8 Specical;
u8 GC;
u16 I2CAckAddr;
u16 SdaHd;
u8 SdaSetup;
u8 RXTL;
u8 TXTL;
u8 SlvNoAck;
u32 INTRMsk;
u8 TxDMARqLv;
u8 RxDMARqLv;
u32 I2CTmp;
/* Get the I2C parameters*/
I2CIdx = pHalI2CInitData->I2CIdx;
SpdMd = pHalI2CInitData->I2CSpdMod;
AddrMd = pHalI2CInitData->I2CAddrMod;
I2CAckAddr = pHalI2CInitData->I2CAckAddr;
Master = pHalI2CInitData->I2CMaster;
SdaHd = pHalI2CInitData->I2CSdaHd;
SdaSetup = pHalI2CInitData->I2CSetup;
ReSTR = pHalI2CInitData->I2CReSTR;
GC = pHalI2CInitData->I2CGC;
StartByte = pHalI2CInitData->I2CStartB;
SlvNoAck = pHalI2CInitData->I2CSlvNoAck;
RXTL = pHalI2CInitData->I2CRXTL;
TXTL = pHalI2CInitData->I2CTXTL;
TxDMARqLv = pHalI2CInitData->I2CTxDMARqLv;
RxDMARqLv = pHalI2CInitData->I2CRxDMARqLv;
/* Disable the IC first */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_ENABLE,BIT_CTRL_IC_ENABLE(0));
/* Master case*/
if (Master) {
/*RESTART MUST be set in these condition in Master mode.
But it might be NOT compatible in old slaves.*/
if ((AddrMd == I2C_ADDR_10BIT) || (SpdMd == I2C_HS_MODE))
ReSTR = 1;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_CON,
(BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(1) |
BIT_CTRL_IC_CON_IC_RESTART_EN(ReSTR) |
BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(AddrMd) |
BIT_CTRL_IC_CON_SPEED(SpdMd) |
BIT_CTRL_IC_CON_MASTER_MODE(Master)));
DBG_I2C_INFO("Init master, IC_CON%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_CON, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON));
/* To set target addr.*/
Specical = 0;
if ((GC!=0) || (StartByte!=0))
Specical = 1;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_TAR,
(BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(AddrMd) |
BIT_CTRL_IC_TAR_SPECIAL(Specical) |
BIT_CTRL_IC_TAR_GC_OR_START(StartByte) |
BIT_CTRL_IC_TAR(I2CAckAddr)));
/* To Set I2C clock*/
HalI2CSetCLKRtl8195a_Patch(pHalI2CInitData);
DBG_I2C_INFO("Init master, IC_TAR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_TAR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_TAR));
} /*if (Master)*/
else {
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_CON,
BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(AddrMd) |
BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(Master) |
BIT_CTRL_IC_CON_SPEED(SpdMd)|
BIT_CTRL_IC_CON_MASTER_MODE(Master));
DBG_I2C_INFO("Init slave, IC_CON%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_CON, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON));
/* To set slave addr. */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SAR,BIT_CTRL_IC_SAR(I2CAckAddr));
DBG_I2C_INFO("Init slave, IC_SAR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_SAR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SAR));
/* To set slave no ack */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SLV_DATA_NACK_ONLY,BIT_CTRL_IC_SLV_DATA_NACK_ONLY(SlvNoAck));
/* Set ack general call. */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_ACK_GENERAL_CALL,BIT_CTRL_IC_ACK_GENERAL_CALL(pHalI2CInitData->I2CSlvAckGC));
DBG_I2C_INFO("Init slave, I2C_IC_ACK_GC%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_ACK_GENERAL_CALL, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_ACK_GENERAL_CALL));
/* to set SDA hold time */
//HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd));
//4
/* to set SDA setup time */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_SETUP,BIT_CTRL_IC_SDA_SETUP(SdaSetup));
}
/* to set SDA hold time */
INTRMsk = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON);
if (BIT_GET_IC_CON_SPEED(INTRMsk) == I2C_SS_MODE) {
I2CTmp = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT);
} else if (BIT_GET_IC_CON_SPEED(INTRMsk) == I2C_FS_MODE) {
I2CTmp = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT);
} else {
I2CTmp = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT);
}
if (Master) {
if (SdaHd > (I2CTmp -2)) {
I2CTmp = I2CTmp -2;
if (I2CTmp < 1) {
I2CTmp = 1 + 1;
}
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(I2CTmp));
} else {
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd));
}
} else {
if (SdaHd > (I2CTmp -2)) {
I2CTmp = I2CTmp -2;
if (I2CTmp < 7) {
I2CTmp = 7 + 1;
}
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(I2CTmp));
} else {
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd));
}
}
//DBG_8195A("SDA:%x\n", HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD));
/* To set TX_Empty Level */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_TX_TL,TXTL);
/* To set RX_Full Level */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_RX_TL,RXTL);
/* To set TX/RX FIFO level */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DMA_TDLR,TxDMARqLv);
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DMA_RDLR,RxDMARqLv);
DBG_I2C_INFO("Init i2c dev, I2C_IC_DMA_TDLR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_DMA_TDLR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_DMA_TDLR));
DBG_I2C_INFO("Init i2c dev, I2C_IC_DMA_RDLR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_DMA_RDLR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_DMA_RDLR));
/*I2C Clear all interrupts first*/
HalI2CClrAllIntrRtl8195a(pHalI2CInitData);
/*I2C Disable all interrupts first*/
INTRMsk = pHalI2CInitData->I2CIntrMSK;
pHalI2CInitData->I2CIntrMSK = 0;
HalI2CIntrCtrl8195a(pHalI2CInitData);
pHalI2CInitData->I2CIntrMSK = INTRMsk;
return HAL_OK;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CSetCLKRtl8195a
//
// Description:
// To set I2C bus clock rate.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CSetCLKRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 SpdMd = pHalI2CInitData->I2CSpdMod;
u32 I2CClk = pHalI2CInitData->I2CClk;
u8 I2CIdx = pHalI2CInitData->I2CIdx;
u32 ICHLcnt;
u32 ICHtime;
u32 ICLtime;
/* Get the IC-Clk setting first for the following process*/
#ifdef CONFIG_FPGA
u32 IcClk = SYSTEM_CLK/1000000;
#else
u32 IcClk;
u32 ClkSELTmp = 0;
u32 CpuClkTmp = 0;
#if defined(CONFIG_CHIP_A_CUT)
CpuClkTmp = StartupHalGetCpuClk();
#elif (defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT))
CpuClkTmp = HalGetCpuClk();
#endif
DBG_I2C_INFO("%s, CPU Clk:%x\n",__func__, CpuClkTmp);
ClkSELTmp = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_SEL);
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
IcClk = (CpuClkTmp/1000000)>>1;
#if 0
if ((I2CClk > 0) && (I2CClk <= 400)) {
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
IcClk = ClkSELTmp/1000000; /*actually it's 12.5MHz*/
}
else {
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
IcClk = 100;
}
#endif
#endif
switch (SpdMd)
{
case I2C_SS_MODE:
{
ICHtime = ((1000000/I2CClk)*I2C_SS_MIN_SCL_HTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2CClk)*I2C_SS_MIN_SCL_LTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IcClk)/1000;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT,ICHLcnt);
DBG_I2C_INFO("IC_SS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_SS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT));
ICHLcnt = (ICLtime * IcClk)/1000;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT,ICHLcnt);
DBG_I2C_INFO("IC_SS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_SS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT));
break;
}
case I2C_FS_MODE:
{
ICHtime = ((1000000/I2CClk)*I2C_FS_MIN_SCL_HTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2CClk)*I2C_FS_MIN_SCL_LTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IcClk)/1000;
if (ICHLcnt>4)/*this part is according to the fine-tune result*/
ICHLcnt -= 4;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT,ICHLcnt);
DBG_I2C_INFO("IC_FS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_FS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT));
ICHLcnt = (ICLtime * IcClk)/1000;
if (ICHLcnt>3)/*this part is according to the fine-tune result*/
ICHLcnt -= 3;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT,ICHLcnt);
DBG_I2C_INFO("IC_FS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_FS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT));
break;
}
case I2C_HS_MODE:
{
ICHLcnt = 400;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT,ICHLcnt);
ICHLcnt = 470;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT,ICHLcnt);
ICHLcnt = 60;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT,ICHLcnt);
ICHLcnt = 130;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT,ICHLcnt);
ICHtime = ((1000000/I2CClk)*I2C_HS_MIN_SCL_HTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
ICLtime = ((1000000/I2CClk)*I2C_HS_MIN_SCL_LTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
DBG_I2C_INFO("ICHtime:%x\n",ICHtime);
DBG_I2C_INFO("ICLtime:%x\n",ICLtime);
ICHLcnt = (ICHtime * IcClk)/1000;
if (ICHLcnt>8)/*this part is according to the fine-tune result*/
ICHLcnt -= 3;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_HS_SCL_HCNT,ICHLcnt);
DBG_I2C_INFO("IC_HS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_HS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_HCNT));
ICHLcnt = (ICLtime * IcClk)/1000;
if (ICHLcnt>6)/*this part is according to the fine-tune result*/
ICHLcnt -= 6;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT,ICHLcnt);
DBG_I2C_INFO("IC_HS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_HS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT));
break;
}
default:
break;
}
return HAL_OK;
}
HAL_Status
HalI2CEnableRtl8195a_Patch(
IN VOID *Data
){
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 I2CIdx = pHalI2CInitData->I2CIdx;
u8 I2CICEn = pHalI2CInitData->I2CEn;
u32 I2CTimeoutCount;
u32 I2CStartCount;
/* Enable I2C module */
HAL_I2C_WRITE32(I2CIdx, REG_DW_I2C_IC_ENABLE, BIT_CTRL_IC_ENABLE(I2CICEn));
I2CTimeoutCount = ((10000/pHalI2CInitData->I2CClk) /TIMER_TICK_US) +1;
I2CStartCount = HalTimerOp.HalTimerReadCount(1);
if (!I2CICEn) {
while (HAL_I2C_READ32(I2CIdx, REG_DW_I2C_IC_ENABLE_STATUS) & BIT_IC_ENABLE_STATUS_IC_EN) {
if (HAL_TIMEOUT == I2CIsTimeout(I2CStartCount, I2CTimeoutCount)) {
return HAL_TIMEOUT;
}
}
} else {
while (!(HAL_I2C_READ32(I2CIdx, REG_DW_I2C_IC_ENABLE_STATUS) & BIT_IC_ENABLE_STATUS_IC_EN)) {
if (HAL_TIMEOUT == I2CIsTimeout(I2CStartCount, I2CTimeoutCount)) {
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
#endif
#endif // CONFIG_I2C_EN

398
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_i2s.c Normal file
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@ -0,0 +1,398 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_i2s.h"
#include "hal_i2s.h"
#ifdef CONFIG_I2S_EN
extern void *
_memset( void *s, int c, SIZE_T n );
RTK_STATUS
HalI2SInitRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
//u8 I2SEn;
u8 I2SMaster;
u8 I2SWordLen;
u8 I2SChNum;
u8 I2SPageNum;
u16 I2SPageSize;
u16 I2SRate;
u32 I2STxIntrMSK;
u32 I2SRxIntrMSK;
u8 I2STRxAct;
u8 *I2STxData;
u8 *I2SRxData;
u32 Tmp;
I2SIdx = pHalI2SInitData->I2SIdx;
//I2SEn = pHalI2SInitData->I2SEn;
I2SMaster = pHalI2SInitData->I2SMaster;
I2SWordLen = pHalI2SInitData->I2SWordLen;
I2SChNum = pHalI2SInitData->I2SChNum;
I2SPageNum = pHalI2SInitData->I2SPageNum;
I2SPageSize = pHalI2SInitData->I2SPageSize;
I2SRate = pHalI2SInitData->I2SRate;
I2STRxAct = pHalI2SInitData->I2STRxAct;
I2STxData = pHalI2SInitData->I2STxData;
I2SRxData = pHalI2SInitData->I2SRxData;
/* Disable the I2S first, and reset to default */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(0));
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
Tmp = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
Tmp |= BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(1);
if (I2SRate & 0x10)
{
Tmp |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
}
Tmp |= (BIT_CTRL_CTLX_I2S_WL(I2SWordLen) | BIT_CTRL_CTLX_I2S_CH_NUM(I2SChNum) |
BIT_CTRL_CTLX_I2S_SLAVE_MODE(I2SMaster) | BIT_CTRL_CTLX_I2S_TRX_ACT(I2STRxAct));
/* set 44.1khz clock source, word length, channel number, master or slave, trx act */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, Tmp);
Tmp = BIT_CTRL_SETTING_I2S_PAGE_SZ(I2SPageSize) | BIT_CTRL_SETTING_I2S_PAGE_NUM(I2SPageNum) |
BIT_CTRL_SETTING_I2S_SAMPLE_RATE(I2SRate);
/* set page size, page number, sample rate */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, Tmp);
/* need tx rx buffer? need rx page own bit */
if (I2STxData != NULL) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (u32)I2STxData);
}
if (I2SRxData != NULL) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (u32)I2SRxData);
}
pHalI2SInitData->I2STxIdx = 0;
pHalI2SInitData->I2SRxIdx = 0;
pHalI2SInitData->I2SHWTxIdx = 0;
pHalI2SInitData->I2SHWRxIdx = 0;
/* I2S Clear all interrupts first */
HalI2SClrAllIntrRtl8195a(pHalI2SInitData);
/* I2S Disable all interrupts first */
I2STxIntrMSK = pHalI2SInitData->I2STxIntrMSK;
I2SRxIntrMSK = pHalI2SInitData->I2SRxIntrMSK;
pHalI2SInitData->I2STxIntrMSK = 0;
pHalI2SInitData->I2SRxIntrMSK = 0;
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
pHalI2SInitData->I2STxIntrMSK = I2STxIntrMSK;
pHalI2SInitData->I2SRxIntrMSK = I2SRxIntrMSK;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetRateRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_CLK_SRC << BIT_SHIFT_CTLX_I2S_CLK_SRC);
if (pHalI2SInitData->I2SRate & 0x10)
{
reg_value |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
}
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_SAMPLE_RATE << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE);
reg_value |= BIT_CTRL_SETTING_I2S_SAMPLE_RATE(pHalI2SInitData->I2SRate);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetWordLenRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_WL << BIT_SHIFT_CTLX_I2S_WL);
reg_value |= BIT_CTRL_CTLX_I2S_WL(pHalI2SInitData->I2SWordLen);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetChNumRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_CH_NUM << BIT_SHIFT_CTLX_I2S_CH_NUM);
reg_value |= BIT_CTRL_CTLX_I2S_CH_NUM(pHalI2SInitData->I2SChNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetPageNumRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetPageSizeRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetDirectionRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_TRX_ACT << BIT_SHIFT_CTLX_I2S_TRX_ACT);
reg_value |= BIT_CTRL_CTLX_I2S_TRX_ACT(pHalI2SInitData->I2STRxAct);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetDMABufRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
u32 page_num;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
page_num = pHalI2SInitData->I2SPageNum + 1;
if (pHalI2SInitData->I2STxData) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2STxData);
pHalI2SInitData->I2STxIntrMSK = (1<<page_num) - 1;
} else {
pHalI2SInitData->I2STxIntrMSK = 0;
}
if (pHalI2SInitData->I2SRxData) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2SRxData);
pHalI2SInitData->I2SRxIntrMSK = (1<<page_num) - 1;
} else {
pHalI2SInitData->I2SRxIntrMSK = 0;
}
// According to the page number to modify the ISR mask
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
return _EXIT_SUCCESS;
}
u8
HalI2SGetTxPageRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
u32 reg;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(I2STxIdx<<2));
if ((reg & (1<<31)) == 0) {
return I2STxIdx;
} else {
return 0xFF;
}
}
u8
HalI2SGetRxPageRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
u32 reg;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
if ((reg & (1<<31)) == 0) {
return I2SRxIdx;
} else {
return 0xFF;
}
}
RTK_STATUS
HalI2SPageSendRtl8195a(
IN VOID *Data,
IN u8 PageIdx
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
u8 I2SIdx;
if (I2STxIdx != PageIdx) {
DBG_I2S_ERR("HalI2SPageSendRtl8195a: UnExpected Page Index. TxPage=%d, Expected:%d\r\n",
PageIdx, I2STxIdx);
}
I2SIdx = pHalI2SInitData->I2SIdx;
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN + 4 * PageIdx, BIT_PAGE_I2S_OWN_BIT);
I2STxIdx = PageIdx + 1;
if (I2STxIdx > I2SPageNum) {
I2STxIdx = 0;
}
pHalI2SInitData->I2STxIdx = I2STxIdx;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
u32 reg;
u8 I2SIdx;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
if ((reg & (1<<31)) != 0) {
DBG_I2S_ERR("HalI2SPageRecvRtl8195a: No Idle Rx Page\r\n");
return _EXIT_FAILURE;
}
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx<<2), 1<<31);
I2SRxIdx += 1;
if (I2SRxIdx > I2SPageNum) {
I2SRxIdx = 0;
}
pHalI2SInitData->I2SRxIdx = I2SRxIdx;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SClearAllOwnBitRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 i;
I2SIdx = pHalI2SInitData->I2SIdx;
for (i=0;i<4;i++) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(i<<2), 0);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(i<<2), 0);
}
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SDMACtrlRtl8195a(
IN VOID *Data
)
{
return _EXIT_SUCCESS;
}
#endif // CONFIG_I2S_EN

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