j3d1/RTL00_WEB
1
0
Fork 0
mirror of https://github.com/pvvx/RTL00_WEB.git synced 2025-07-31 20:31:05 +00:00
Code Issues Projects Releases Packages Wiki Activity

update

Browse source
This commit is contained in:
pvvx 2017-06-21 03:00:20 +03:00
parent 34d3652711
commit 39f77eb92b
1844 changed files with 899433 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

32
USDK/component/common/drivers/wlan/realtek/src/core/option/rtw_opt_skbuf.c Normal file
View file

@ -0,0 +1,32 @@
#include <section_config.h>
#include <osdep_service.h>
#include <skbuff.h>
#define MAX_SKB_BUF_SIZE 1650 // should >= the size in wlan driver
#define MAX_SKB_BUF_NUM 8
#define MAX_LOCAL_SKB_NUM (MAX_SKB_BUF_NUM + 2)
/* DO NOT modify skb_buf and skb_data structure */
struct skb_buf {
struct list_head list;
struct sk_buff skb;
};
struct skb_data {
struct list_head list;
unsigned char buf[MAX_SKB_BUF_SIZE];
atomic_t ref;
};
unsigned int nr_xmitframe = MAX_SKB_BUF_NUM;
unsigned int nr_xmitbuff = MAX_SKB_BUF_NUM;
int max_local_skb_num = MAX_LOCAL_SKB_NUM;
int max_skb_buf_num = MAX_SKB_BUF_NUM;
/* DO NOT access skb_pool and skb_data_pool out of wlan driver */
struct skb_buf skb_pool[MAX_LOCAL_SKB_NUM];
// SRAM_BD_DATA_SECTION default in SRAM. Can modify image2.icf to link to the end of SDRAM
SRAM_BD_DATA_SECTION
struct skb_data skb_data_pool[MAX_SKB_BUF_NUM];

102
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/HalPhyRf.h Normal file
View file

@ -0,0 +1,102 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_H__
#define __HAL_PHY_RF_H__
typedef enum _SPUR_CAL_METHOD {
PLL_RESET,
AFE_PHASE_SEL
} SPUR_CAL_METHOD;
typedef enum _PWRTRACK_CONTROL_METHOD {
BBSWING,
TXAGC,
MIX_MODE
} PWRTRACK_METHOD;
typedef VOID (*FuncSetPwr)(PDM_ODM_T, PWRTRACK_METHOD, u1Byte, u1Byte);
typedef VOID (*FuncIQK)(PDM_ODM_T, u1Byte, u1Byte, u1Byte);
#if !defined(CONFIG_PLATFORM_8195A) && !defined(CONFIG_PLATFORM_8711B)
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
typedef VOID (*FuncLCK)(PDM_ODM_T);
#else
typedef VOID (*FuncLCK)(PADAPTER);
#endif
#else
typedef VOID (*FuncLCK)(PDM_ODM_T);
#endif
typedef VOID (*FuncSwing)(PDM_ODM_T, ps1Byte*, ps1Byte*, ps1Byte*, ps1Byte*);
typedef VOID (*FuncSwingXtal)(PDM_ODM_T, ps1Byte*, ps1Byte*);
typedef VOID (*FuncSetXtal)(PDM_ODM_T);
typedef struct _TXPWRTRACK_CFG {
u1Byte SwingTableSize_CCK;
u1Byte SwingTableSize_OFDM;
u1Byte Threshold_IQK;
u1Byte AverageThermalNum;
u1Byte RfPathCount;
u4Byte ThermalRegAddr;
FuncSetPwr ODM_TxPwrTrackSetPwr;
FuncIQK DoIQK;
FuncLCK PHY_LCCalibrate;
FuncSwing GetDeltaSwingTable;
FuncSwingXtal GetDeltaSwingXtalTable;
FuncSetXtal ODM_TxXtalTrackSetXtal;
} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG;
void ConfigureTxpowerTrack(
IN PDM_ODM_T pDM_Odm,
OUT PTXPWRTRACK_CFG pConfig
);
VOID
ODM_ClearTxPowerTrackingState(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_TXPowerTrackingCallback_ThermalMeter(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER Adapter
#endif
);
#define ODM_TARGET_CHNL_NUM_2G_5G 59
VOID
ODM_ResetIQKResult(
IN PDM_ODM_T pDM_Odm
);
u1Byte
ODM_GetRightChnlPlaceforIQK(
IN u1Byte chnl
);
#endif // #ifndef __HAL_PHY_RF_H__

162
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/PhyDM_Adaptivity.h Normal file
View file

@ -0,0 +1,162 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMADAPTIVITY_H__
#define __PHYDMADAPTIVITY_H__
#define ADAPTIVITY_VERSION "8.4"
#define PwdBUpperBound 7
#define DFIRloss 5
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
typedef enum _tag_PhyDM_REGULATION_Type {
REGULATION_FCC = 0,
REGULATION_MKK = 1,
REGULATION_ETSI = 2,
REGULATION_WW = 3,
MAX_REGULATION_NUM = 4
} PhyDM_REGULATION_TYPE;
#endif
typedef enum tag_PhyDM_TRx_MUX_Type
{
PhyDM_SHUTDOWN = 0,
PhyDM_STANDBY_MODE = 1,
PhyDM_TX_MODE = 2,
PhyDM_RX_MODE = 3
}PhyDM_Trx_MUX_Type;
typedef enum tag_PhyDM_MACEDCCA_Type
{
PhyDM_IGNORE_EDCCA = 0,
PhyDM_DONT_IGNORE_EDCCA = 1
}PhyDM_MACEDCCA_Type;
typedef struct _ADAPTIVITY_STATISTICS {
s1Byte TH_L2H_ini_mode2;
s1Byte TH_EDCCA_HL_diff_mode2;
s1Byte TH_EDCCA_HL_diff_backup;
s1Byte IGI_Base;
u1Byte IGI_target;
u1Byte NHMWait;
s1Byte H2L_lb;
s1Byte L2H_lb;
BOOLEAN bFirstLink;
BOOLEAN bCheck;
BOOLEAN DynamicLinkAdaptivity;
u1Byte APNumTH;
u1Byte AdajustIGILevel;
BOOLEAN bStopEDCCA;
} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS;
VOID
Phydm_CheckAdaptivity(
IN PVOID pDM_VOID
);
VOID
Phydm_CheckEnvironment(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
Phydm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
);
VOID
Phydm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
Phydm_MACEDCCAState(
IN PVOID pDM_VOID,
IN PhyDM_MACEDCCA_Type State
);
VOID
Phydm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
);
VOID
Phydm_SetTRxMux(
IN PVOID pDM_VOID,
IN PhyDM_Trx_MUX_Type txMode,
IN PhyDM_Trx_MUX_Type rxMode
);
BOOLEAN
Phydm_CalNHMcnt(
IN PVOID pDM_VOID
);
VOID
Phydm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
);
VOID
Phydm_AdaptivityInit(
IN PVOID pDM_VOID
);
VOID
Phydm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
Phydm_DisableEDCCA(
IN PVOID pDM_VOID
);
VOID
Phydm_DynamicEDCCA(
IN PVOID pDM_VOID
);
VOID
Phydm_AdaptivityBSOD(
IN PVOID pDM_VOID
);
#endif
#endif

24
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/mp_precomp.h Normal file
View file

@ -0,0 +1,24 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//#include <Precomp.h>
//#include "phydm_precomp.h"
//#include "../phydm_precomp.h"

2088
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm.h Normal file
View file

File diff suppressed because it is too large Load diff

97
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_ACS.h Normal file
View file

@ -0,0 +1,97 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMACS_H__
#define __PHYDMACS_H__
#include "phydm_types.h"
#define ACS_VERSION "1.1" /*20150729 by YuChen*/
#define CLM_VERSION "1.0"
#define ODM_MAX_CHANNEL_2G 14
#define ODM_MAX_CHANNEL_5G 24
// For phydm_AutoChannelSelectSettingAP()
#define STORE_DEFAULT_NHM_SETTING 0
#define RESTORE_DEFAULT_NHM_SETTING 1
#define ACS_NHM_SETTING 2
#define ODM_REG_CLM_TIME_PERIOD_11AC 0x990
#define ODM_REG_CLM_TIME_PERIOD_11N 0x894
#define ODM_REG_CLM_RESULT_11AC 0xfa4
#define ODM_REG_CLM_RESULT_11N 0x8d0
#define ODM_REG_CLM_11AC 0x994
#define ODM_REG_CLM_11N 0x890
#define ODM_REG_CLM_READY_11N 0x8b4
typedef struct _ACS_
{
BOOLEAN bForceACSResult;
u1Byte CleanChannel_2G;
u1Byte CleanChannel_5G;
u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times
u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G];
#if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
u1Byte ACS_Step;
// NHM Count 0-11
u1Byte NHM_Cnt[14][11];
// AC-Series, for storing previous setting
u4Byte Reg0x990;
u4Byte Reg0x994;
u4Byte Reg0x998;
u4Byte Reg0x99C;
u1Byte Reg0x9A0; // u1Byte
// N-Series, for storing previous setting
u4Byte Reg0x890;
u4Byte Reg0x894;
u4Byte Reg0x898;
u4Byte Reg0x89C;
u1Byte Reg0xE28; // u1Byte
#endif
}ACS, *PACS;
VOID
phydm_CLMInit(
IN PVOID pDM_VOID,
IN u2Byte sampleNum
);
VOID
phydm_CLMtrigger(
IN PVOID pDM_VOID
);
BOOLEAN
phydm_checkCLMready(
IN PVOID pDM_VOID
);
u2Byte
phydm_getCLMresult(
IN PVOID pDM_VOID
);
#endif //#ifndef __PHYDMACS_H__

76
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_AntDect.h Normal file
View file

@ -0,0 +1,76 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDECT_H__
#define __PHYDMANTDECT_H__
#define ANTDECT_VERSION "1.0"
#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE))
//1 [1. Single Tone Method] ===================================================
VOID
ODM_SingleDualAntennaDefaultSetting(
IN PDM_ODM_T pDM_Odm
);
BOOLEAN
ODM_SingleDualAntennaDetection(
IN PDM_ODM_T pDM_Odm,
IN u1Byte mode
);
//1 [2. Scan AP RSSI Method] ==================================================
VOID
odm_SwAntDetectInit(
IN PDM_ODM_T pDM_Odm
);
#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink
BOOLEAN
ODM_SwAntDivCheckBeforeLink(
IN PDM_ODM_T pDM_Odm
);
//1 [3. PSD Method] ==========================================================
VOID
ODM_SingleDualAntennaDetection_PSD(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif

144
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_AntDiv.h Normal file
View file

@ -0,0 +1,144 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMANTDIV_H__
#define __PHYDMANTDIV_H__
#define ANTDIV_VERSION "1.0"
#define ANT1_2G 0 // = ANT2_5G
#define ANT2_2G 1 // = ANT1_5G
//Antenna Diversty Control Type
#define ODM_AUTO_ANT 0
#define ODM_FIX_MAIN_ANT 1
#define ODM_FIX_AUX_ANT 2
#define TX_BY_REG 0
#if (DM_ODM_SUPPORT_TYPE != ODM_AP)
#define ODM_RTL8881A 0 //Just for windows driver to jointly use ODM-driver
#endif
#define ODM_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B)
#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E)
#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A)
#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812)
#define ODM_ANTDIV_2G BIT0
#define ODM_ANTDIV_5G BIT1
#define ANTDIV_ON 1
#define ANTDIV_OFF 0
#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
VOID ODM_SwAntDivRestAfterLink( IN PDM_ODM_T pDM_Odm);
VOID
odm_AntennaDiversityReset(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_AntDivInit(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_AntDiv(
IN PDM_ODM_T pDM_Odm
);
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_UpdateRxIdleAnt(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Ant
);
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
ODM_SW_AntDiv_Callback(
IN PRT_TIMER pTimer
);
VOID
ODM_SW_AntDiv_WorkitemCallback(
IN PVOID pContext
);
#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
VOID
ODM_SW_AntDiv_Callback(void *FunctionContext);
#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_CE)
#endif
#if(RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)
#if ( !(DM_ODM_SUPPORT_TYPE == ODM_CE))
VOID
odm_FastAntTraining(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingCallback(
IN PDM_ODM_T pDM_Odm
);
VOID
odm_FastAntTrainingWorkItemCallback(
IN PDM_ODM_T pDM_Odm
);
#endif
#endif
VOID
ODM_Process_RSSIForAntDiv(
IN OUT PDM_ODM_T pDM_Odm,
IN PODM_PHY_INFO_T pPhyInfo,
IN PODM_PACKET_INFO_T pPktinfo
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
ODM_SetTxAntByTxInfo(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
);
#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)
VOID
ODM_SetTxAntByTxInfo(
//IN PDM_ODM_T pDM_Odm,
struct rtl8192cd_priv *priv,
struct tx_desc *pdesc,
struct tx_insn *txcfg,
unsigned short aid
);
#endif
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
#endif //#ifndef __ODMANTDIV_H__

73
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_CfoTracking.h Normal file
View file

@ -0,0 +1,73 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMCFOTRACK_H__
#define __PHYDMCFOTRACK_H__
#define CFO_TRACKING_VERSION "1.0"
//#define CFO_TH_XTAL_HIGH 20 // kHz
//#define CFO_TH_XTAL_LOW 10 // kHz
//#define CFO_TH_ATC 80 // kHz
#if ((RTL8195A_SUPPORT==0) && (RTL8711B_SUPPORT == 0))
typedef struct _CFO_TRACKING_
{
BOOLEAN bATCStatus;
BOOLEAN largeCFOHit;
BOOLEAN bAdjust;
u1Byte CrystalCap;
u1Byte DefXCap;
int CFO_tail[2];
int CFO_ave_pre;
u4Byte packetCount;
u4Byte packetCount_pre;
BOOLEAN bForceXtalCap;
BOOLEAN bReset;
u1Byte CFO_TH_XTAL_HIGH;
u1Byte CFO_TH_XTAL_LOW;
u1Byte CFO_TH_ATC;
}CFO_TRACKING, *PCFO_TRACKING;
#endif
VOID
ODM_CfoTrackingReset(
IN PVOID pDM_VOID
);
VOID
ODM_CfoTrackingInit(
IN PVOID pDM_VOID
);
VOID
ODM_CfoTracking(
IN PVOID pDM_VOID
);
VOID
ODM_ParsingCFO(
IN PVOID pDM_VOID,
IN PVOID pPktinfo_VOID,
IN s1Byte* pcfotail,
IN u1Byte num_ss
);
#endif

476
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DIG.h Normal file
View file

@ -0,0 +1,476 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODMDIG_H__
#define __ODMDIG_H__
typedef struct _Dynamic_Initial_Gain_Threshold_
{
BOOLEAN bStopDIG; // for debug
BOOLEAN bPauseDIG;
BOOLEAN bIgnoreDIG;
BOOLEAN bPSDInProgress;
u1Byte Dig_Enable_Flag;
u1Byte Dig_Ext_Port_Stage;
int RssiLowThresh;
int RssiHighThresh;
u4Byte FALowThresh;
u4Byte FAHighThresh;
u1Byte CurSTAConnectState;
u1Byte PreSTAConnectState;
u1Byte CurMultiSTAConnectState;
u1Byte PreIGValue;
u1Byte CurIGValue;
u1Byte BackupIGValue; //MP DIG
u1Byte BT30_CurIGI;
u1Byte IGIBackup;
s1Byte BackoffVal;
s1Byte BackoffVal_range_max;
s1Byte BackoffVal_range_min;
u1Byte rx_gain_range_max;
u1Byte rx_gain_range_min;
u1Byte Rssi_val_min;
u1Byte PreCCK_CCAThres;
u1Byte CurCCK_CCAThres;
u1Byte PreCCKPDState;
u1Byte CurCCKPDState;
u1Byte CCKPDBackup;
u1Byte LargeFAHit;
u1Byte ForbiddenIGI;
u4Byte Recover_cnt;
u1Byte DIG_Dynamic_MIN_0;
u1Byte DIG_Dynamic_MIN_1;
BOOLEAN bMediaConnect_0;
BOOLEAN bMediaConnect_1;
u4Byte AntDiv_RSSI_max;
u4Byte RSSI_max;
u1Byte *pbP2pLinkInProgress;
u4Byte cckFaMa;
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
BOOLEAN bTpTarget;
BOOLEAN bNoiseEst;
u4Byte TpTrainTH_min;
u1Byte IGIOffset_A;
u1Byte IGIOffset_B;
#endif
}DIG_T,*pDIG_T;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_ADSL))
typedef struct _FALSE_ALARM_STATISTICS{
u4Byte Cnt_Parity_Fail;
u4Byte Cnt_Rate_Illegal;
u4Byte Cnt_Crc8_fail;
u4Byte Cnt_Mcs_fail;
u4Byte Cnt_Ofdm_fail;
u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A
u4Byte Cnt_Cck_fail;
u4Byte Cnt_all;
u4Byte Cnt_Fast_Fsync;
u4Byte Cnt_SB_Search_fail;
u4Byte Cnt_OFDM_CCA;
u4Byte Cnt_CCK_CCA;
u4Byte Cnt_CCA_all;
u4Byte Cnt_BW_USC; //Gary
u4Byte Cnt_BW_LSC; //Gary
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
#endif
typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition
{
DIG_TYPE_THRESH_HIGH = 0,
DIG_TYPE_THRESH_LOW = 1,
DIG_TYPE_BACKOFF = 2,
DIG_TYPE_RX_GAIN_MIN = 3,
DIG_TYPE_RX_GAIN_MAX = 4,
DIG_TYPE_ENABLE = 5,
DIG_TYPE_DISABLE = 6,
DIG_OP_TYPE_MAX
}DM_DIG_OP_E;
typedef enum tag_ODM_PauseDIG_Type {
ODM_PAUSE_DIG = BIT0,
ODM_RESUME_DIG = BIT1
} ODM_Pause_DIG_TYPE;
typedef enum tag_ODM_PauseCCKPD_Type {
ODM_PAUSE_CCKPD = BIT0,
ODM_RESUME_CCKPD = BIT1
} ODM_Pause_CCKPD_TYPE;
typedef enum tag_ODM_TRx_MUX_Type
{
ODM_SHUTDOWN = 0,
ODM_STANDBY_MODE = 1,
ODM_TX_MODE = 2,
ODM_RX_MODE = 3
}ODM_Trx_MUX_Type;
typedef enum tag_ODM_MACEDCCA_Type
{
ODM_IGNORE_EDCCA = 0,
ODM_DONT_IGNORE_EDCCA = 1
}ODM_MACEDCCA_Type;
/*
typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition
{
CCK_PD_STAGE_LowRssi = 0,
CCK_PD_STAGE_HighRssi = 1,
CCK_PD_STAGE_MAX = 3,
}DM_CCK_PDTH_E;
typedef enum tag_DIG_EXT_PORT_ALGO_Definition
{
DIG_EXT_PORT_STAGE_0 = 0,
DIG_EXT_PORT_STAGE_1 = 1,
DIG_EXT_PORT_STAGE_2 = 2,
DIG_EXT_PORT_STAGE_3 = 3,
DIG_EXT_PORT_STAGE_MAX = 4,
}DM_DIG_EXT_PORT_ALG_E;
typedef enum tag_DIG_Connect_Definition
{
DIG_STA_DISCONNECT = 0,
DIG_STA_CONNECT = 1,
DIG_STA_BEFORE_CONNECT = 2,
DIG_MultiSTA_DISCONNECT = 3,
DIG_MultiSTA_CONNECT = 4,
DIG_CONNECT_MAX
}DM_DIG_CONNECT_E;
#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}
#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT)
#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \
DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT)
*/
#define DM_DIG_THRESH_HIGH 40
#define DM_DIG_THRESH_LOW 35
#define DM_FALSEALARM_THRESH_LOW 400
#define DM_FALSEALARM_THRESH_HIGH 1000
#define DM_DIG_MAX_NIC 0x3e
#define DM_DIG_MIN_NIC 0x20 //0x1e
#define DM_DIG_MAX_OF_MIN_NIC 0x3e
#define DM_DIG_MAX_AP 0x3e
#define DM_DIG_MIN_AP 0x1c
#define DM_DIG_MAX_OF_MIN 0x2A //0x32
#define DM_DIG_MIN_AP_DFS 0x20
#define DM_DIG_MAX_NIC_HP 0x46
#define DM_DIG_MIN_NIC_HP 0x2e
#define DM_DIG_MAX_AP_HP 0x42
#define DM_DIG_MIN_AP_HP 0x30
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#define DM_DIG_MAX_AP_COVERAGR 0x26
#define DM_DIG_MIN_AP_COVERAGE 0x1c
#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22
#define DM_DIG_TP_Target_TH0 500
#define DM_DIG_TP_Target_TH1 1000
#define DM_DIG_TP_Training_Period 10
#endif
//vivi 92c&92d has different definition, 20110504
//this is for 92c
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT))
#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
#define DM_DIG_FA_TH0 0x80//0x20
#else
#define DM_DIG_FA_TH0 0x200//0x20
#endif
#else
#define DM_DIG_FA_TH0 0x200//0x20
#endif
#define DM_DIG_FA_TH1 0x300
#define DM_DIG_FA_TH2 0x400
//this is for 92d
#define DM_DIG_FA_TH0_92D 0x100
#define DM_DIG_FA_TH1_92D 0x400
#define DM_DIG_FA_TH2_92D 0x600
#define DM_DIG_BACKOFF_MAX 12
#define DM_DIG_BACKOFF_MIN -4
#define DM_DIG_BACKOFF_DEFAULT 10
#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps
#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps
#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps
#define RSSI_OFFSET_DIG 0x05
VOID
odm_CheckAdaptivity(
IN PVOID pDM_VOID
);
VOID
odm_CheckEnvironment(
IN PVOID pDM_VOID
);
VOID
ODM_ChangeDynamicInitGainThresh(
IN PVOID pDM_VOID,
IN u4Byte DM_Type,
IN u4Byte DM_Value
);
VOID
odm_NHMCounterStatisticsInit(
IN PVOID pDM_VOID
);
VOID
odm_NHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
odm_NHMBBInit(
IN PVOID pDM_VOID
);
VOID
odm_NHMBB(
IN PVOID pDM_VOID
);
VOID
odm_NHMCounterStatisticsReset(
IN PVOID pDM_VOID
);
VOID
odm_GetNHMCounterStatistics(
IN PVOID pDM_VOID
);
VOID
odm_MACEDCCAState(
IN PVOID pDM_VOID,
IN ODM_MACEDCCA_Type State
);
VOID
odm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
);
VOID
odm_SetTRxMux(
IN PVOID pDM_VOID,
IN ODM_Trx_MUX_Type txMode,
IN ODM_Trx_MUX_Type rxMode
);
BOOLEAN
odm_CalNHMcnt(
IN PVOID pDM_VOID
);
VOID
odm_SearchPwdBLowerBound(
IN PVOID pDM_VOID
);
VOID
odm_AdaptivityInit(
IN PVOID pDM_VOID
);
BOOLEAN
odm_Adaptivity(
IN PVOID pDM_VOID,
IN u1Byte IGI
);
VOID
ODM_Write_DIG(
IN PVOID pDM_VOID,
IN u1Byte CurrentIGI
);
VOID
odm_PauseDIG(
IN PVOID pDM_VOID,
IN ODM_Pause_DIG_TYPE PauseType,
IN u1Byte IGIValue
);
VOID
odm_DIGInit(
IN PVOID pDM_VOID
);
VOID
odm_DIG(
IN PVOID pDM_VOID
);
VOID
odm_DIGbyRSSI_LPS(
IN PVOID pDM_VOID
);
VOID
odm_DigForBtHsMode(
IN PVOID pDM_VOID
);
VOID
odm_FalseAlarmCounterStatistics(
IN PVOID pDM_VOID
);
#if (DM_ODM_SUPPORT_TYPE & ODM_IOT)
VOID
odm_FAThresholdCheck(
IN PVOID pDM_VOID,
OUT u4Byte* dm_FA_thres
);
#else
VOID
odm_FAThresholdCheck(
IN PVOID pDM_VOID,
IN BOOLEAN bDFSBand,
IN BOOLEAN bPerformance,
IN u4Byte RxTp,
IN u4Byte TxTp,
OUT u4Byte* dm_FA_thres
);
#endif
u1Byte
odm_ForbiddenIGICheck(
IN PVOID pDM_VOID,
IN u1Byte DIG_Dynamic_MIN,
IN u1Byte CurrentIGI
);
VOID
odm_InbandNoiseCalculate (
IN PVOID pDM_VOID
);
BOOLEAN
odm_DigAbort(
IN PVOID pDM_VOID
);
VOID
odm_PauseCCKPacketDetection(
IN PVOID pDM_VOID,
IN ODM_Pause_CCKPD_TYPE PauseType,
IN u1Byte CCKPDThreshold
);
VOID
odm_CCKPacketDetectionThresh(
IN PVOID pDM_VOID
);
VOID
ODM_Write_CCK_CCA_Thres(
IN PVOID pDM_VOID,
IN u1Byte CurCCK_CCAThres
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
odm_DisableEDCCA(
IN PVOID pDM_VOID
);
VOID
odm_DynamicEDCCA(
IN PVOID pDM_VOID
);
VOID
odm_MPT_DIGCallback(
PRT_TIMER pTimer
);
VOID
odm_MPT_DIGWorkItemCallback(
IN PVOID pContext
);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
VOID
odm_MPT_DIGCallback(
IN PVOID pDM_VOID
);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL))
VOID
ODM_MPT_DIG(
IN PVOID pDM_VOID
);
#endif
#endif
VOID
odm_DIGInit_8195A(
IN PVOID pDM_VOID
);
VOID
odm_DIG_8195A(
IN PVOID pDM_VOID
);
VOID
odm_FalseAlarmCounterStatistics_8195A(
IN PVOID pDM_VOID
);
VOID
odm_CCKPacketDetectionThresh_8195A(
IN PVOID pDM_VOID
);

63
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DynamicBBPowerSaving.h Normal file
View file

@ -0,0 +1,63 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__
#define __PHYDMDYNAMICBBPOWERSAVING_H__
#define DYNAMIC_BBPWRSAV_VERSION "1.0"
typedef struct _Dynamic_Power_Saving_
{
u1Byte PreCCAState;
u1Byte CurCCAState;
u1Byte PreRFState;
u1Byte CurRFState;
int Rssi_val_min;
u1Byte initialize;
u4Byte Reg874,RegC70,Reg85C,RegA74;
}PS_T,*pPS_T;
#define dm_RF_Saving ODM_RF_Saving
void ODM_RF_Saving(
IN PVOID pDM_VOID,
IN u1Byte bForceInNormal
);
VOID
odm_DynamicBBPowerSavingInit(
IN PVOID pDM_VOID
);
VOID
odm_DynamicBBPowerSaving(
IN PVOID pDM_VOID
);
VOID
odm_1R_CCA(
IN PVOID pDM_VOID
);
#endif

89
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_DynamicTxPower.h Normal file
View file

@ -0,0 +1,89 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMDYNAMICTXPOWER_H__
#define __PHYDMDYNAMICTXPOWER_H__
#define DYNAMIC_TXPWR_VERSION "1.0"
#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
#define TX_POWER_NEAR_FIELD_THRESH_8812 60
#define TxHighPwrLevel_Normal 0
#define TxHighPwrLevel_Level1 1
#define TxHighPwrLevel_Level2 2
#define TxHighPwrLevel_BT1 3
#define TxHighPwrLevel_BT2 4
#define TxHighPwrLevel_15 5
#define TxHighPwrLevel_35 6
#define TxHighPwrLevel_50 7
#define TxHighPwrLevel_70 8
#define TxHighPwrLevel_100 9
VOID
odm_DynamicTxPowerInit(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerRestorePowerIndex(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerNIC(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
VOID
odm_DynamicTxPowerSavePowerIndex(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerWritePowerIndex(
IN PVOID pDM_VOID,
IN u1Byte Value);
VOID
odm_DynamicTxPower_92C(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPower_92D(
IN PVOID pDM_VOID
);
#endif
VOID
odm_DynamicTxPower(
IN PVOID pDM_VOID
);
VOID
odm_DynamicTxPowerAP(
IN PVOID pDM_VOID
);
#endif

152
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_EdcaTurboCheck.h Normal file
View file

@ -0,0 +1,152 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMEDCATURBOCHECK_H__
#define __PHYDMEDCATURBOCHECK_H__
#define EDCATURBO_VERSION "1.0"
typedef struct _EDCA_TURBO_
{
BOOLEAN bCurrentTurboEDCA;
BOOLEAN bIsCurRDLState;
#if(DM_ODM_SUPPORT_TYPE == ODM_CE )
u4Byte prv_traffic_idx; // edca turbo
#endif
}EDCA_T,*pEDCA_T;
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx)
{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322};
static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx)
{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b};
static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] =
// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP
{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b};
//============================================================
// EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22
//============================================================
#elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL)
enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG };
static const struct ParaRecord rtl_ap_EDCA[] =
{
//ACM,AIFSN, ECWmin, ECWmax, TXOplimit
{0, 7, 4, 10, 0}, //BK
{0, 3, 4, 6, 0}, //BE
{0, 1, 3, 4, 188}, //VI
{0, 1, 2, 3, 102}, //VO
{0, 1, 3, 4, 94}, //VI_AG
{0, 1, 2, 3, 47}, //VO_AG
};
static const struct ParaRecord rtl_sta_EDCA[] =
{
//ACM,AIFSN, ECWmin, ECWmax, TXOplimit
{0, 7, 4, 10, 0},
{0, 3, 4, 10, 0},
{0, 2, 3, 4, 188},
{0, 2, 2, 3, 102},
{0, 2, 3, 4, 94},
{0, 2, 2, 3, 47},
};
#endif
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#ifdef WIFI_WMM
VOID
ODM_IotEdcaSwitch(
IN PVOID pDM_VOID,
IN unsigned char enable
);
#endif
BOOLEAN
ODM_ChooseIotMainSTA(
IN PVOID pDM_VOID,
IN PSTA_INFO_T pstat
);
#endif
VOID
odm_EdcaTurboCheck(
IN PVOID pDM_VOID
);
VOID
ODM_EdcaTurboInit(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
VOID
odm_EdcaTurboCheckMP(
IN PVOID pDM_VOID
);
//check if edca turbo is disabled
BOOLEAN
odm_IsEdcaTurboDisable(
IN PVOID pDM_VOID
);
//choose edca paramter for special IOT case
VOID
ODM_EdcaParaSelByIot(
IN PVOID pDM_VOID,
OUT u4Byte *EDCA_BE_UL,
OUT u4Byte *EDCA_BE_DL
);
//check if it is UL or DL
VOID
odm_EdcaChooseTrafficIdx(
IN PVOID pDM_VOID,
IN u8Byte cur_tx_bytes,
IN u8Byte cur_rx_bytes,
IN BOOLEAN bBiasOnRx,
OUT BOOLEAN *pbIsCurRDLState
);
#elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
VOID
odm_EdcaTurboCheckCE(
IN PVOID pDM_VOID
);
#else
VOID
odm_IotEngine(
IN PVOID pDM_VOID
);
VOID
odm_EdcaParaInit(
IN PVOID pDM_VOID
);
#endif
#endif

508
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_HWConfig.h Normal file
View file

@ -0,0 +1,508 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HALHWOUTSRC_H__
#define __HALHWOUTSRC_H__
/*--------------------------Define -------------------------------------------*/
//#define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte)))
#define AGC_DIFF_CONFIG(ic, band) do {\
if (pDM_Odm->bIsMPChip)\
AGC_DIFF_CONFIG_MP(ic,band);\
else\
AGC_DIFF_CONFIG_TC(ic,band);\
} while(0)
//============================================================
// structure and define
//============================================================
typedef struct _Phy_Rx_AGC_Info
{
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte gain:7,trsw:1;
#else
u1Byte trsw:1,gain:7;
#endif
} PHY_RX_AGC_INFO_T,*pPHY_RX_AGC_INFO_T;
typedef struct _Phy_Status_Rpt_8192cd
{
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_corr[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_rpt_b_ofdm_cfosho_b;
u1Byte rsvd_1;//ch_corr_msb;
u1Byte noise_power_db_msb;
s1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte noise_power_db_lsb;
u1Byte rsvd_2[3];
u1Byte stream_csi[2];
u1Byte stream_target_csi[2];
s1Byte sig_evm;
u1Byte rsvd_3;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
u1Byte sgi_en:1;
u1Byte rxsc:2;
u1Byte idle_long:1;
u1Byte r_ant_train_en:1;
u1Byte ant_sel_b:1;
u1Byte ant_sel:1;
#else // _BIG_ENDIAN_
u1Byte ant_sel:1;
u1Byte ant_sel_b:1;
u1Byte r_ant_train_en:1;
u1Byte idle_long:1;
u1Byte rxsc:2;
u1Byte sgi_en:1;
u1Byte antsel_rx_keep_2:1; //ex_intf_flg:1;
#endif
} PHY_STATUS_RPT_8192CD_T,*PPHY_STATUS_RPT_8192CD_T;
typedef struct _Phy_Status_Rpt_8812
{
#if 0
PHY_RX_AGC_INFO_T path_agc[2];
u1Byte ch_num[2];
u1Byte cck_sig_qual_ofdm_pwdb_all;
u1Byte cck_agc_rpt_ofdm_cfosho_a;
u1Byte cck_bb_pwr_ofdm_cfosho_b;
u1Byte cck_rx_path; //CCK_RX_PATH [3:0] (with regA07[3:0] definition)
u1Byte rsvd_1;
u1Byte path_cfotail[2];
u1Byte pcts_mask[2];
s1Byte stream_rxevm[2];
u1Byte path_rxsnr[2];
u1Byte rsvd_2[2];
u1Byte stream_snr[2];
u1Byte stream_csi[2];
u1Byte rsvd_3[2];
s1Byte sig_evm;
u1Byte rsvd_4;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte rsvd_5:2;
#else // _BIG_ENDIAN_
u1Byte rsvd_5:2;
u1Byte antidx_antb:3;
u1Byte antidx_anta:3;
#endif
#endif
//2012.05.24 LukeLee: This structure should take big/little endian in consideration later.....
//DWORD 0
u1Byte gain_trsw[2];
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u2Byte chl_num:10;
u2Byte sub_chnl:4;
u2Byte r_RFMOD:2;
#else // _BIG_ENDIAN_
u2Byte r_RFMOD:2;
u2Byte sub_chnl:4;
u2Byte chl_num:10;
#endif
//DWORD 1
u1Byte pwdb_all;
u1Byte cfosho[4]; // DW 1 byte 1 DW 2 byte 0
//DWORD 2
s1Byte cfotail[4]; // DW 2 byte 1 DW 3 byte 0
//DWORD 3
s1Byte rxevm[2]; // DW 3 byte 1 DW 3 byte 2
s1Byte rxsnr[2]; // DW 3 byte 3 DW 4 byte 0
//DWORD 4
u1Byte PCTS_MSK_RPT[2];
u1Byte pdsnr[2]; // DW 4 byte 3 DW 5 Byte 0
//DWORD 5
u1Byte csi_current[2];
u1Byte rx_gain_c;
//DWORD 6
u1Byte rx_gain_d;
s1Byte sigevm;
u1Byte resvd_0;
u1Byte antidx_anta:3;
u1Byte antidx_antb:3;
u1Byte resvd_1:2;
} PHY_STATUS_RPT_8812_T,*PPHY_STATUS_RPT_8812_T;
VOID
odm_Init_RSSIForDM(
IN OUT PDM_ODM_T pDM_Odm
);
VOID
ODM_PhyStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
OUT PODM_PHY_INFO_T pPhyInfo,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo
);
VOID
ODM_MacStatusQuery(
IN OUT PDM_ODM_T pDM_Odm,
IN pu1Byte pMacStatus,
IN u1Byte MacID,
IN BOOLEAN bPacketMatchBSSID,
IN BOOLEAN bPacketToSelf,
IN BOOLEAN bPacketBeacon
);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_IOT))
HAL_STATUS
ODM_ConfigRFWithTxPwrTrackHeaderFile(
IN PDM_ODM_T pDM_Odm
);
HAL_STATUS
ODM_ConfigRFWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_Config_Type ConfigType,
IN ODM_RF_RADIO_PATH_E eRFPath
);
HAL_STATUS
ODM_ConfigBBWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_BB_Config_Type ConfigType
);
HAL_STATUS
ODM_ConfigMACWithHeaderFile(
IN PDM_ODM_T pDM_Odm
);
HAL_STATUS
ODM_ConfigFWWithHeaderFile(
IN PDM_ODM_T pDM_Odm,
IN ODM_FW_Config_Type ConfigType,
OUT u1Byte *pFirmware,
OUT u4Byte *pSize
);
u4Byte
ODM_GetHWImgVersion(
IN PDM_ODM_T pDM_Odm
);
s4Byte
odm_SignalScaleMapping(
IN OUT PDM_ODM_T pDM_Odm,
IN s4Byte CurrSig
);
#endif
#if(ODM_PHY_STATUS_NEW_TYPE_SUPPORT == 1)
//For New RX PHY Status Report Format, include 8723D/8710B
VOID
phydm_RxPhyStatusNewType(
IN PDM_ODM_T pPhydm,
IN pu1Byte pPhyStatus,
IN PODM_PACKET_INFO_T pPktinfo,
OUT PODM_PHY_INFO_T pPhyInfo
);
typedef struct _Phy_Status_Rpt_Jaguar2_Type0 {
/* DW0 */
u1Byte page_num;
u1Byte pwdb;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte gain: 6;
u1Byte rsvd_0: 1;
u1Byte trsw: 1;
#else
u1Byte trsw: 1;
u1Byte rsvd_0: 1;
u1Byte gain: 6;
#endif
u1Byte rsvd_1;
/* DW1 */
u1Byte rsvd_2;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte rxsc: 4;
u1Byte agc_table: 4;
#else
u1Byte agc_table: 4;
u1Byte rxsc: 4;
#endif
u1Byte channel;
u1Byte band;
/* DW2 */
u2Byte length;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_a: 3;
u1Byte antidx_b: 3;
u1Byte rsvd_3: 2;
u1Byte antidx_c: 3;
u1Byte antidx_d: 3;
u1Byte rsvd_4:2;
#else
u1Byte rsvd_3: 2;
u1Byte antidx_b: 3;
u1Byte antidx_a: 3;
u1Byte rsvd_4:2;
u1Byte antidx_d: 3;
u1Byte antidx_c: 3;
#endif
/* DW3 */
u1Byte signal_quality;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte vga:5;
u1Byte lna_l:3;
u1Byte bb_power:6;
u1Byte rsvd_9:1;
u1Byte lna_h:1;
#else
u1Byte lna_l:3;
u1Byte vga:5;
u1Byte lna_h:1;
u1Byte rsvd_9:1;
u1Byte bb_power:6;
#endif
u1Byte rsvd_5;
/* DW4 */
u4Byte rsvd_6;
/* DW5 */
u4Byte rsvd_7;
/* DW6 */
u4Byte rsvd_8;
} PHY_STATUS_RPT_JAGUAR2_TYPE0, *PPHY_STATUS_RPT_JAGUAR2_TYPE0; //for CCK Format
typedef struct _Phy_Status_Rpt_Jaguar2_Type1 {
/* DW0 and DW1 */
u1Byte page_num;
u1Byte pwdb[4];
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte l_rxsc: 4;
u1Byte ht_rxsc: 4;
#else
u1Byte ht_rxsc: 4;
u1Byte l_rxsc: 4;
#endif
u1Byte channel;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte band: 2;
u1Byte rsvd_0: 1;
u1Byte hw_antsw_occu: 1;
u1Byte gnt_bt: 1;
u1Byte ldpc: 1;
u1Byte stbc: 1;
u1Byte beamformed: 1;
#else
u1Byte beamformed: 1;
u1Byte stbc: 1;
u1Byte ldpc: 1;
u1Byte gnt_bt: 1;
u1Byte hw_antsw_occu: 1;
u1Byte rsvd_0: 1;
u1Byte band: 2;
#endif
/* DW2 */
u2Byte lsig_length;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte antidx_a: 3;
u1Byte antidx_b: 3;
u1Byte rsvd_1: 2;
u1Byte antidx_c: 3;
u1Byte antidx_d: 3;
u1Byte rsvd_2: 2;
#else
u1Byte rsvd_1: 2;
u1Byte antidx_b: 3;
u1Byte antidx_a: 3;
u1Byte rsvd_2: 2;
u1Byte antidx_d: 3;
u1Byte antidx_c: 3;
#endif
/* DW3 */
u1Byte paid;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte paid_msb: 1;
u1Byte gid: 6;
u1Byte rsvd_3: 1;
#else
u1Byte rsvd_3: 1;
u1Byte gid: 6;
u1Byte paid_msb: 1;
#endif
u1Byte intf_pos;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte intf_pos_msb: 1;
u1Byte rsvd_4: 2;
u1Byte nb_intf_flag: 1;
u1Byte rf_mode: 2;
u1Byte rsvd_5: 2;
#else
u1Byte rsvd_5: 2;
u1Byte rf_mode: 2;
u1Byte nb_intf_flag: 1;
u1Byte rsvd_4: 2;
u1Byte intf_pos_msb: 1;
#endif
/* DW4 */
s1Byte rxevm[4]; /* s(8,1) */
/* DW5 */
s1Byte cfo_tail[4]; /* s(8,7) */
/* DW6 */
s1Byte rxsnr[4]; /* s(8,1) */
} PHY_STATUS_RPT_JAGUAR2_TYPE1, *PPHY_STATUS_RPT_JAGUAR2_TYPE1;//for OFDM Format
typedef struct _Phy_Status_Rpt_Jaguar2_Type2 {
/* DW0 ane DW1 */
u1Byte page_num;
u1Byte pwdb[4];
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte l_rxsc: 4;
u1Byte ht_rxsc: 4;
#else
u1Byte ht_rxsc: 4;
u1Byte l_rxsc: 4;
#endif
u1Byte channel;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte band: 2;
u1Byte rsvd_0: 1;
u1Byte hw_antsw_occu: 1;
u1Byte gnt_bt: 1;
u1Byte ldpc: 1;
u1Byte stbc: 1;
u1Byte beamformed: 1;
#else
u1Byte beamformed: 1;
u1Byte stbc: 1;
u1Byte ldpc: 1;
u1Byte gnt_bt: 1;
u1Byte hw_antsw_occu: 1;
u1Byte rsvd_0: 1;
u1Byte band: 2;
#endif
/* DW2 */
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte shift_l_map: 6;
u1Byte rsvd_1: 2;
#else
u1Byte rsvd_1: 2;
u1Byte shift_l_map: 6;
#endif
u1Byte cnt_pw2cca;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte agc_table_a: 4;
u1Byte agc_table_b: 4;
u1Byte agc_table_c: 4;
u1Byte agc_table_d: 4;
#else
u1Byte agc_table_b: 4;
u1Byte agc_table_a: 4;
u1Byte agc_table_d: 4;
u1Byte agc_table_c: 4;
#endif
/* DW3 ~ DW6*/
u1Byte cnt_cca2agc_rdy;
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte gain_a: 6;
u1Byte rsvd_2: 1;
u1Byte trsw_a: 1;
u1Byte gain_b: 6;
u1Byte rsvd_3: 1;
u1Byte trsw_b: 1;
u1Byte gain_c: 6;
u1Byte rsvd_4: 1;
u1Byte trsw_c: 1;
u1Byte gain_d: 6;
u1Byte rsvd_5: 1;
u1Byte trsw_d: 1;
u1Byte aagc_step_a: 2;
u1Byte aagc_step_b: 2;
u1Byte aagc_step_c: 2;
u1Byte aagc_step_d: 2;
#else
u1Byte trsw_a: 1;
u1Byte rsvd_2: 1;
u1Byte gain_a: 6;
u1Byte trsw_b: 1;
u1Byte rsvd_3: 1;
u1Byte gain_b: 6;
u1Byte trsw_c: 1;
u1Byte rsvd_4: 1;
u1Byte gain_c: 6;
u1Byte trsw_d: 1;
u1Byte rsvd_5: 1;
u1Byte gain_d: 6;
u1Byte aagc_step_d: 2;
u1Byte aagc_step_c: 2;
u1Byte aagc_step_b: 2;
u1Byte aagc_step_a: 2;
#endif
u1Byte ht_aagc_gain[4];
u1Byte dagc_gain[4];
#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
u1Byte counter: 6;
u1Byte rsvd_6: 2;
u1Byte syn_count: 5;
u1Byte rsvd_7:3;
#else
u1Byte rsvd_6: 2;
u1Byte counter: 6;
u1Byte rsvd_7:3;
u1Byte syn_count: 5;
#endif
} PHY_STATUS_RPT_JAGUAR2_TYPE2, *PPHY_STATUS_RPT_JAGUAR2_TYPE2;//for debug mode: AGC&SBD
#endif
#endif /*#ifndef __HALHWOUTSRC_H__*/

49
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_NoiseMonitor.h Normal file
View file

@ -0,0 +1,49 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
*****************************************************************************/
#ifndef __ODMNOISEMONITOR_H__
#define __ODMNOISEMONITOR_H__
#define ODM_MAX_CHANNEL_NUM 38//14+24
struct noise_level
{
//u1Byte value_a, value_b;
u1Byte value[MAX_RF_PATH];
//s1Byte sval_a, sval_b;
s1Byte sval[MAX_RF_PATH];
//s4Byte noise_a=0, noise_b=0,sum_a=0, sum_b=0;
//s4Byte noise[ODM_RF_PATH_MAX];
s4Byte sum[MAX_RF_PATH];
//u1Byte valid_cnt_a=0, valid_cnt_b=0,
u1Byte valid[MAX_RF_PATH];
u1Byte valid_cnt[MAX_RF_PATH];
};
typedef struct _ODM_NOISE_MONITOR_
{
s1Byte noise[MAX_RF_PATH];
s2Byte noise_all;
}ODM_NOISE_MONITOR;
s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time);
#endif

193
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_PathDiv.h Normal file
View file

@ -0,0 +1,193 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMPATHDIV_H__
#define __PHYDMPATHDIV_H__
#define PATHDIV_VERSION "1.0"
VOID
odm_PathDiversityInit(
IN PVOID pDM_VOID
);
VOID
odm_PathDiversity(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
//#define PATHDIV_ENABLE 1
#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi
#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C
typedef struct _PathDiv_Parameter_define_
{
u4Byte org_5g_RegE30;
u4Byte org_5g_RegC14;
u4Byte org_5g_RegCA0;
u4Byte swt_5g_RegE30;
u4Byte swt_5g_RegC14;
u4Byte swt_5g_RegCA0;
//for 2G IQK information
u4Byte org_2g_RegC80;
u4Byte org_2g_RegC4C;
u4Byte org_2g_RegC94;
u4Byte org_2g_RegC14;
u4Byte org_2g_RegCA0;
u4Byte swt_2g_RegC80;
u4Byte swt_2g_RegC4C;
u4Byte swt_2g_RegC94;
u4Byte swt_2g_RegC14;
u4Byte swt_2g_RegCA0;
}PATHDIV_PARA,*pPATHDIV_PARA;
VOID
odm_PathDiversityInit_92C(
IN PADAPTER Adapter
);
VOID
odm_2TPathDiversityInit_92C(
IN PADAPTER Adapter
);
VOID
odm_1TPathDiversityInit_92C(
IN PADAPTER Adapter
);
BOOLEAN
odm_IsConnected_92C(
IN PADAPTER Adapter
);
BOOLEAN
ODM_PathDiversityBeforeLink92C(
//IN PADAPTER Adapter
IN PDM_ODM_T pDM_Odm
);
VOID
odm_PathDiversityAfterLink_92C(
IN PADAPTER Adapter
);
VOID
odm_SetRespPath_92C(
IN PADAPTER Adapter,
IN u1Byte DefaultRespPath
);
VOID
odm_OFDMTXPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_CCKTXPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_ResetPathDiversity_92C(
IN PADAPTER Adapter
);
VOID
odm_CCKTXPathDiversityCallback(
PRT_TIMER pTimer
);
VOID
odm_CCKTXPathDiversityWorkItemCallback(
IN PVOID pContext
);
VOID
odm_PathDivChkAntSwitchCallback(
PRT_TIMER pTimer
);
VOID
odm_PathDivChkAntSwitchWorkitemCallback(
IN PVOID pContext
);
VOID
odm_PathDivChkAntSwitch(
PDM_ODM_T pDM_Odm
);
VOID
ODM_CCKPathDiversityChkPerPktRssi(
PADAPTER Adapter,
BOOLEAN bIsDefPort,
BOOLEAN bMatchBSSID,
PRT_WLAN_STA pEntry,
PRT_RFD pRfd,
pu1Byte pDesc
);
VOID
ODM_PathDivChkPerPktRssi(
PADAPTER Adapter,
BOOLEAN bIsDefPort,
BOOLEAN bMatchBSSID,
PRT_WLAN_STA pEntry,
PRT_RFD pRfd
);
VOID
ODM_PathDivRestAfterLink(
IN PDM_ODM_T pDM_Odm
);
VOID
ODM_FillTXPathInTXDESC(
IN PADAPTER Adapter,
IN PRT_TCB pTcb,
IN pu1Byte pDesc
);
VOID
odm_PathDivInit_92D(
IN PDM_ODM_T pDM_Odm
);
u1Byte
odm_SwAntDivSelectScanChnl(
IN PADAPTER Adapter
);
VOID
odm_SwAntDivConstructScanChnl(
IN PADAPTER Adapter,
IN u1Byte ScanChnl
);
#endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
#endif //#ifndef __ODMPATHDIV_H__

306
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_PowerTracking.h Normal file
View file

@ -0,0 +1,306 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMPOWERTRACKING_H__
#define __PHYDMPOWERTRACKING_H__
#define POWRTRACKING_VERSION "1.0"
#define DPK_DELTA_MAPPING_NUM 13
#define index_mapping_HP_NUM 15
#define OFDM_TABLE_SIZE 43
#define CCK_TABLE_SIZE 33
#define TXSCALE_TABLE_SIZE 37
#define TXPWR_TRACK_TABLE_SIZE 30
#define DELTA_SWINGIDX_SIZE 30
#define BAND_NUM 4
#define CCK_TABLE_SIZE_8711B 41
#define AVG_THERMAL_NUM 8
#define HP_THERMAL_NUM 8
#define IQK_MAC_REG_NUM 4
#define IQK_ADDA_REG_NUM 16
#define IQK_BB_REG_NUM_MAX 10
#if (RTL8192D_SUPPORT==1)
#define IQK_BB_REG_NUM 10
#else
#define IQK_BB_REG_NUM 9
#endif
#define IQK_Matrix_REG_NUM 8
#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8195A) || defined (CONFIG_RTL8711B)
#define IQK_Matrix_Settings_NUM 14
#else
#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G
#endif
//extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE];
//extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
//extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];
#if (RTL8195A_SUPPORT == 1)
extern const u1Byte CCKSwingTable_Ch1_Ch13_8195A[CCK_TABLE_SIZE][9];
extern const u1Byte CCKSwingTable_Ch14_8195A[CCK_TABLE_SIZE][9];
extern const u1Byte CCKFCCTable_8195A[16];
extern const u1Byte CCKCETable_8195A[16];
extern const u1Byte CCKFCCTable_Ch14_8195A[16];
#endif
#if (RTL8711B_SUPPORT == 1)
extern const u1Byte CCKFCCTable_8711B[16];
extern const u1Byte CCKCETable_8711B[16];
extern const u1Byte CCKFCCTable_Ch14_8711B[16];
extern const u4Byte CCKSwingTable_Ch1_Ch14_8711B[CCK_TABLE_SIZE_8711B];
#endif
extern const u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE];
extern const u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
extern const u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8];
//extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table.
//static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9};
//static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11};
#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
typedef struct _IQK_MATRIX_REGS_SETTING{
BOOLEAN bIQKDone;
#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)
s4Byte Value[1][IQK_Matrix_REG_NUM];
#else
s4Byte Value[3][IQK_Matrix_REG_NUM];
BOOLEAN bBWIqkResultSaved[3];
#endif
}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING;
typedef struct ODM_RF_Calibration_Structure
{
//for tx power tracking
u4Byte RegA24; // for TempCCK
s4Byte RegE94;
s4Byte RegE9C;
s4Byte RegEB4;
s4Byte RegEBC;
u1Byte TXPowercount;
BOOLEAN bTXPowerTrackingInit;
BOOLEAN bTXPowerTracking;
u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u1Byte TM_Trigger;
u1Byte InternalPA5G[2]; //pathA / pathB
u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
u1Byte ThermalValue;
u1Byte ThermalValue_LCK;
u1Byte ThermalValue_IQK;
u1Byte ThermalValue_DPK;
u1Byte ThermalValue_AVG[AVG_THERMAL_NUM];
u1Byte ThermalValue_AVG_index;
u1Byte ThermalValue_RxGain;
u1Byte ThermalValue_Crystal;
u1Byte ThermalValue_DPKstore;
u1Byte ThermalValue_DPKtrack;
BOOLEAN TxPowerTrackingInProgress;
BOOLEAN bReloadtxpowerindex;
u1Byte bRfPiEnable;
u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug
//------------------------- Tx power Tracking -------------------------//
u1Byte bCCKinCH14;
u1Byte CCK_index[MAX_RF_PATH];
s1Byte PowerIndexOffset_CCK[MAX_RF_PATH];
s1Byte DeltaPowerIndex_CCK[MAX_RF_PATH];
s1Byte DeltaPowerIndexLast_CCK[MAX_RF_PATH];
u1Byte OFDM_index[MAX_RF_PATH];
s1Byte PowerIndexOffset_OFDM[MAX_RF_PATH];
s1Byte DeltaPowerIndex_OFDM[MAX_RF_PATH];
s1Byte DeltaPowerIndexLast_OFDM[MAX_RF_PATH];
BOOLEAN bTxPowerChanged;
s1Byte XtalOffset;
s1Byte XtalOffsetLast;
u1Byte ThermalValue_HP[HP_THERMAL_NUM];
u1Byte ThermalValue_HP_index;
IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
u1Byte Delta_LCK;
s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB
s1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
#if !defined(NOT_SUPPORT_RF_MULTIPATH)
s1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE];
#endif
s1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
#if !defined(NOT_SUPPORT_RF_MULTIPATH)
s1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE];
#endif
#if !defined(NOT_SUPPORT_5G)
s1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
#endif
// u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
// u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableXtal_P[DELTA_SWINGIDX_SIZE];
s1Byte DeltaSwingTableXtal_N[DELTA_SWINGIDX_SIZE];
//--------------------------------------------------------------------//
//for IQK
u4Byte RegC04;
u4Byte Reg874;
u4Byte RegC08;
u4Byte RegB68;
u4Byte RegB6C;
u4Byte Reg870;
u4Byte Reg860;
u4Byte Reg864;
BOOLEAN bIQKInitialized;
BOOLEAN bLCKInProgress;
BOOLEAN bAntennaDetected;
BOOLEAN bNeedIQK;
BOOLEAN bIQKInProgress;
u1Byte Delta_IQK;
u4Byte ADDA_backup[IQK_ADDA_REG_NUM];
u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM];
u4Byte IQK_BB_backup_recover[9];
u4Byte IQK_BB_backup[IQK_BB_REG_NUM];
u4Byte TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}
u4Byte RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}
// <James> IQK time measurement
u8Byte IQK_StartTime;
u8Byte IQK_ProgressingTime;
u4Byte LOK_Result;
//for APK
u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a
u1Byte bAPKdone;
u1Byte bAPKThermalMeterIgnore;
// DPK
BOOLEAN bDPKFail;
u1Byte bDPdone;
u1Byte bDPPathAOK;
u1Byte bDPPathBOK;
u4Byte TxLOK[2];
u4Byte DpkTxAGC;
s4Byte DpkGain;
u4Byte DpkThermal[4];
}ODM_RF_CAL_T,*PODM_RF_CAL_T;
VOID
ODM_TXPowerTrackingCheck(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingInit(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingCheckAP(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingThermalMeterInit(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingInit(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingCheckMP(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingCheckCE(
IN PVOID pDM_VOID
);
VOID
odm_TXPowerTrackingCheckIOT(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
VOID
odm_TXPowerTrackingCallbackThermalMeter92C(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingCallbackRXGainThermalMeter92D(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingCallbackThermalMeter92D(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingDirectCall92C(
IN PADAPTER Adapter
);
VOID
odm_TXPowerTrackingThermalMeterCheck(
IN PADAPTER Adapter
);
#endif
#endif

105
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RXHP.h Normal file
View file

@ -0,0 +1,105 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMRXHP_H__
#define __PHYDMRXHP_H__
#define RXHP_VERSION "1.0"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD
#define MODE_40M 0 //0:20M, 1:40M
#define PSD_TH2 3
#define PSD_CHMIN 20 // Minimum channel number for BT AFH
#define SIR_STEP_SIZE 3
#define Smooth_Size_1 5
#define Smooth_TH_1 3
#define Smooth_Size_2 10
#define Smooth_TH_2 4
#define Smooth_Size_3 20
#define Smooth_TH_3 4
#define Smooth_Step_Size 5
#define Adaptive_SIR 1
#define PSD_RESCAN 4
#define PSD_SCAN_INTERVAL 700 //ms
typedef struct _RX_High_Power_
{
u1Byte RXHP_flag;
u1Byte PSD_func_trigger;
u1Byte PSD_bitmap_RXHP[80];
u1Byte Pre_IGI;
u1Byte Cur_IGI;
u1Byte Pre_pw_th;
u1Byte Cur_pw_th;
BOOLEAN First_time_enter;
BOOLEAN RXHP_enable;
u1Byte TP_Mode;
RT_TIMER PSDTimer;
#if USE_WORKITEM
RT_WORK_ITEM PSDTimeWorkitem;
#endif
}RXHP_T, *pRXHP_T;
#define dm_PSDMonitorCallback odm_PSDMonitorCallback
VOID odm_PSDMonitorCallback(PRT_TIMER pTimer);
VOID
odm_PSDMonitorInit(
IN PVOID pDM_VOID
);
void odm_RXHPInit(
IN PVOID pDM_VOID);
void odm_RXHP(
IN PVOID pDM_VOID);
VOID
odm_PSD_RXHPCallback(
PRT_TIMER pTimer
);
VOID
ODM_PSDDbgControl(
IN PADAPTER Adapter,
IN u4Byte mode,
IN u4Byte btRssi
);
VOID
odm_PSD_RXHPCallback(
PRT_TIMER pTimer
);
VOID
odm_PSD_RXHPWorkitemCallback(
IN PVOID pContext
);
VOID
odm_PSDMonitorWorkItemCallback(
IN PVOID pContext
);
#endif
#endif

210
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RaInfo.h Normal file
View file

@ -0,0 +1,210 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __PHYDMRAINFO_H__
#define __PHYDMRAINFO_H__
#define RAINFO_VERSION "1.0"
#define H2C_0X42_LENGTH 5
#define H2C_MAX_LENGTH 7
#define RA_FLOOR_UP_GAP 3
#define RA_FLOOR_TABLE_SIZE 7
#define ACTIVE_TP_THRESHOLD 150
#define RA_RETRY_DESCEND_NUM 2
#define RA_RETRY_LIMIT_LOW 4
#define RA_RETRY_LIMIT_HIGH 32
#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL
#define RAINFO_STBC_STATE BIT1
//#define RAINFO_LDPC_STATE BIT2
#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection
#define RAINFO_SHURTCUT_STATE BIT3
#define RAINFO_SHURTCUT_FLAG BIT4
#define RAINFO_INIT_RSSI_RATE_STATE BIT5
#define RAINFO_BF_STATE BIT6
#define RAINFO_BE_TX_STATE BIT7 // 1:TX
#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit
#define DM_RATR_STA_INIT 0
#define DM_RATR_STA_HIGH 1
#define DM_RATR_STA_MIDDLE 2
#define DM_RATR_STA_LOW 3
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
#define DM_RATR_STA_ULTRA_LOW 4
#endif
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_IOT))
typedef struct _Rate_Adaptive_Table_{
u1Byte firstconnect;
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
BOOLEAN PT_collision_pre;
#endif
//u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];
u1Byte highest_client_tx_order;
u2Byte highest_client_tx_rate_order;
u1Byte power_tracking_flag;
u1Byte RA_threshold_offset;
u1Byte RA_offset_direction;
}RA_T, *pRA_T;
#endif
typedef struct _ODM_RATE_ADAPTIVE
{
u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver
u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH
u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW
u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW
#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_IOT))
u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC
BOOLEAN bLowerRtsRate;
#endif
#if(DM_ODM_SUPPORT_TYPE & ODM_WIN)
u1Byte RtsThres;
#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT))
BOOLEAN bUseLdpc;
#else
u1Byte UltraLowRSSIThresh;
u4Byte LastRATR; // RATR Register Content
#endif
} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
VOID
odm_RSSIMonitorInit(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorCheck(
IN PVOID pDM_VOID
);
#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
VOID
odm_RSSIDumpToRegister(
IN PVOID pDM_VOID
);
#endif
VOID
odm_RSSIMonitorCheckMP(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorCheckCE(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorCheckIOT(
IN PVOID pDM_VOID
);
VOID
odm_RSSIMonitorCheckAP(
IN PVOID pDM_VOID
);
VOID
odm_RateAdaptiveMaskInit(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMask(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMaskMP(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMaskCE(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMaskIOT(
IN PVOID pDM_VOID
);
VOID
odm_RefreshRateAdaptiveMaskAPADSL(
IN PVOID pDM_VOID
);
BOOLEAN
ODM_RAStateCheck(
IN PVOID pDM_VOID,
IN s4Byte RSSI,
IN BOOLEAN bForceUpdate,
OUT pu1Byte pRATRState
);
VOID
odm_RefreshBasicRateMask(
IN PVOID pDM_VOID
);
VOID
phydm_ra_info_init(
IN PVOID pDM_VOID
);
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
VOID
ODM_DynamicARFBSelect(
IN PVOID pDM_VOID,
IN u1Byte rate,
IN BOOLEAN Collision_State
);
VOID
ODM_RateAdaptiveStateApInit(
IN PVOID PADAPTER_VOID,
IN PRT_WLAN_STA pEntry
);
#endif
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT))
u4Byte
ODM_Get_Rate_Bitmap(
IN PVOID pDM_VOID,
IN u4Byte macid,
IN u4Byte ra_mask,
IN u1Byte rssi_level
);
#endif
#endif //#ifndef __ODMRAINFO_H__

81
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RegDefine11AC.h Normal file
View file

@ -0,0 +1,81 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11AC_H__
#define __ODM_REGDEFINE11AC_H__
//2 RF REG LIST
//2 BB REG LIST
//PAGE 8
#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804
#define ODM_REG_BB_RX_PATH_11AC 0x808
#define ODM_REG_BB_TX_PATH_11AC 0x80c
#define ODM_REG_BB_ATC_11AC 0x860
#define ODM_REG_EDCCA_POWER_CAL 0x8dc
#define ODM_REG_DBG_RPT_11AC 0x8fc
//PAGE 9
#define ODM_REG_EDCCA_DOWN_OPT 0x900
#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944
#define ODM_REG_OFDM_FA_RST_11AC 0x9A4
#define ODM_REG_NHM_TIMER_11AC 0x990
#define ODM_REG_NHM_TH9_TH10_11AC 0x994
#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998
#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c
#define ODM_REG_NHM_TH8_11AC 0x9a0
#define ODM_REG_NHM_9E8_11AC 0x9e8
//PAGE A
#define ODM_REG_CCK_CCA_11AC 0xA0A
#define ODM_REG_CCK_FA_RST_11AC 0xA2C
#define ODM_REG_CCK_FA_11AC 0xA5C
//PAGE B
#define ODM_REG_RST_RPT_11AC 0xB58
//PAGE C
#define ODM_REG_TRMUX_11AC 0xC08
#define ODM_REG_IGI_A_11AC 0xC50
//PAGE E
#define ODM_REG_IGI_B_11AC 0xE50
#define ODM_REG_TRMUX_11AC_B 0xE08
//PAGE F
#define ODM_REG_CCK_CCA_CNT_11AC 0xF08
#define ODM_REG_OFDM_FA_11AC 0xF48
#define ODM_REG_RPT_11AC 0xfa0
#define ODM_REG_NHM_CNT_11AC 0xfa8
//PAGE 18
#define ODM_REG_IGI_C_11AC 0x1850
//PAGE 1A
#define ODM_REG_IGI_D_11AC 0x1A50
//2 MAC REG LIST
#define ODM_REG_RESP_TX_11AC 0x6D8
//DIG Related
#define ODM_BIT_IGI_11AC 0xFFFFFFFF
#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16
#define ODM_BIT_BB_RX_PATH_11AC 0xF
#define ODM_BIT_BB_TX_PATH_11AC 0xF
#define ODM_BIT_BB_ATC_11AC BIT14
#endif

186
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_RegDefine11N.h Normal file
View file

@ -0,0 +1,186 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_REGDEFINE11N_H__
#define __ODM_REGDEFINE11N_H__
//2 RF REG LIST
#define ODM_REG_RF_MODE_11N 0x00
#define ODM_REG_RF_0B_11N 0x0B
#define ODM_REG_CHNBW_11N 0x18
#define ODM_REG_T_METER_11N 0x24
#define ODM_REG_RF_25_11N 0x25
#define ODM_REG_RF_26_11N 0x26
#define ODM_REG_RF_27_11N 0x27
#define ODM_REG_RF_2B_11N 0x2B
#define ODM_REG_RF_2C_11N 0x2C
#define ODM_REG_RXRF_A3_11N 0x3C
#define ODM_REG_T_METER_92D_11N 0x42
#define ODM_REG_T_METER_88E_11N 0x42
//2 BB REG LIST
//PAGE 8
#define ODM_REG_BB_CTRL_11N 0x800
#define ODM_REG_RF_PIN_11N 0x804
#define ODM_REG_PSD_CTRL_11N 0x808
#define ODM_REG_TX_ANT_CTRL_11N 0x80C
#define ODM_REG_BB_PWR_SAV5_11N 0x818
#define ODM_REG_CCK_RPT_FORMAT_11N 0x824
#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C
#define ODM_REG_RX_DEFUALT_A_11N 0x858
#define ODM_REG_RX_DEFUALT_B_11N 0x85A
#define ODM_REG_BB_PWR_SAV3_11N 0x85C
#define ODM_REG_ANTSEL_CTRL_11N 0x860
#define ODM_REG_RX_ANT_CTRL_11N 0x864
#define ODM_REG_PIN_CTRL_11N 0x870
#define ODM_REG_BB_PWR_SAV1_11N 0x874
#define ODM_REG_ANTSEL_PATH_11N 0x878
#define ODM_REG_BB_3WIRE_11N 0x88C
#define ODM_REG_SC_CNT_11N 0x8C4
#define ODM_REG_PSD_DATA_11N 0x8B4
#define ODM_REG_PSD_DATA_11N 0x8B4
#define ODM_REG_NHM_TIMER_11N 0x894
#define ODM_REG_NHM_TH9_TH10_11N 0x890
#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898
#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c
#define ODM_REG_NHM_CNT_11N 0x8d8
//PAGE 9
#define ODM_REG_DBG_RPT_11N 0x908
#define ODM_REG_BB_TX_PATH_11N 0x90c
#define ODM_REG_ANT_MAPPING1_11N 0x914
#define ODM_REG_ANT_MAPPING2_11N 0x918
#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948
//PAGE A
#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00
#define ODM_REG_CCK_CCA_11N 0xA0A
#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C
#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10
#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14
#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22
#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23
#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24
#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25
#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26
#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27
#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28
#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29
#define ODM_REG_CCK_FA_RST_11N 0xA2C
#define ODM_REG_CCK_FA_MSB_11N 0xA58
#define ODM_REG_CCK_FA_LSB_11N 0xA5C
#define ODM_REG_CCK_CCA_CNT_11N 0xA60
#define ODM_REG_BB_PWR_SAV4_11N 0xA74
//PAGE B
#define ODM_REG_LNA_SWITCH_11N 0xB2C
#define ODM_REG_PATH_SWITCH_11N 0xB30
#define ODM_REG_RSSI_CTRL_11N 0xB38
#define ODM_REG_CONFIG_ANTA_11N 0xB68
#define ODM_REG_RSSI_BT_11N 0xB9C
//PAGE C
#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00
#define ODM_REG_BB_RX_PATH_11N 0xC04
#define ODM_REG_TRMUX_11N 0xC08
#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C
#define ODM_REG_RXIQI_MATRIX_11N 0xC14
#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C
#define ODM_REG_IGI_A_11N 0xC50
#define ODM_REG_ANTDIV_PARA2_11N 0xC54
#define ODM_REG_IGI_B_11N 0xC58
#define ODM_REG_ANTDIV_PARA3_11N 0xC5C
#define ODM_REG_L1SBD_PD_CH_11N 0XC6C
#define ODM_REG_BB_PWR_SAV2_11N 0xC70
#define ODM_REG_RX_OFF_11N 0xC7C
#define ODM_REG_TXIQK_MATRIXA_11N 0xC80
#define ODM_REG_TXIQK_MATRIXB_11N 0xC88
#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94
#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C
#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0
#define ODM_REG_ANTDIV_PARA1_11N 0xCA4
#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0
//PAGE D
#define ODM_REG_OFDM_FA_RSTD_11N 0xD00
#define ODM_REG_BB_ATC_11N 0xD2C
#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0
#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4
#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8
#define ODM_REG_RPT_11N 0xDF4
//PAGE E
#define ODM_REG_TXAGC_A_6_18_11N 0xE00
#define ODM_REG_TXAGC_A_24_54_11N 0xE04
#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08
#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10
#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14
#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18
#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C
#define DOM_REG_EDCCA_DCNF_11N 0xE24
#define ODM_REG_FPGA0_IQK_11N 0xE28
#define ODM_REG_TXIQK_TONE_A_11N 0xE30
#define ODM_REG_RXIQK_TONE_A_11N 0xE34
#define ODM_REG_TXIQK_PI_A_11N 0xE38
#define ODM_REG_RXIQK_PI_A_11N 0xE3C
#define ODM_REG_TXIQK_11N 0xE40
#define ODM_REG_RXIQK_11N 0xE44
#define ODM_REG_IQK_AGC_PTS_11N 0xE48
#define ODM_REG_IQK_AGC_RSP_11N 0xE4C
#define ODM_REG_BLUETOOTH_11N 0xE6C
#define ODM_REG_RX_WAIT_CCA_11N 0xE70
#define ODM_REG_TX_CCK_RFON_11N 0xE74
#define ODM_REG_TX_CCK_BBON_11N 0xE78
#define ODM_REG_OFDM_RFON_11N 0xE7C
#define ODM_REG_OFDM_BBON_11N 0xE80
#define ODM_REG_TX2RX_11N 0xE84
#define ODM_REG_TX2TX_11N 0xE88
#define ODM_REG_RX_CCK_11N 0xE8C
#define ODM_REG_RX_OFDM_11N 0xED0
#define ODM_REG_RX_WAIT_RIFS_11N 0xED4
#define ODM_REG_RX2RX_11N 0xED8
#define ODM_REG_STANDBY_11N 0xEDC
#define ODM_REG_SLEEP_11N 0xEE0
#define ODM_REG_PMPD_ANAEN_11N 0xEEC
#define ODM_REG_IGI_C_11N 0xF84
#define ODM_REG_IGI_D_11N 0xF88
//2 MAC REG LIST
#define ODM_REG_BB_RST_11N 0x02
#define ODM_REG_ANTSEL_PIN_11N 0x4C
#define ODM_REG_EARLY_MODE_11N 0x4D0
#define ODM_REG_RSSI_MONITOR_11N 0x4FE
#define ODM_REG_EDCA_VO_11N 0x500
#define ODM_REG_EDCA_VI_11N 0x504
#define ODM_REG_EDCA_BE_11N 0x508
#define ODM_REG_EDCA_BK_11N 0x50C
#define ODM_REG_TXPAUSE_11N 0x522
#define ODM_REG_RESP_TX_11N 0x6D8
#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0
#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4
//DIG Related
#define ODM_BIT_IGI_11N 0x0000007F
#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9
#define ODM_BIT_BB_RX_PATH_11N 0xF
#define ODM_BIT_BB_TX_PATH_11N 0xF
#define ODM_BIT_BB_ATC_11N BIT11
#endif

900
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_debug.h Normal file
View file

@ -0,0 +1,900 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_DBG_H__
#define __ODM_DBG_H__
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE()!
//
#define ODM_DBG_OFF 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define ODM_DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define ODM_DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define ODM_DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define ODM_DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
//BB Functions
#define ODM_COMP_DIG BIT0
#define ODM_COMP_RA_MASK BIT1
#define ODM_COMP_DYNAMIC_TXPWR BIT2
#define ODM_COMP_FA_CNT BIT3
#define ODM_COMP_RSSI_MONITOR BIT4
#define ODM_COMP_CCK_PD BIT5
#define ODM_COMP_ANT_DIV BIT6
#define ODM_COMP_PWR_SAVE BIT7
#define ODM_COMP_PWR_TRAIN BIT8
#define ODM_COMP_RATE_ADAPTIVE BIT9
#define ODM_COMP_PATH_DIV BIT10
#define ODM_COMP_PSD BIT11
#define ODM_COMP_DYNAMIC_PRICCA BIT12
#define ODM_COMP_RXHP BIT13
#define ODM_COMP_MP BIT14
#define ODM_COMP_CFO_TRACKING BIT15
#define ODM_COMP_ACS BIT16
#define PHYDM_COMP_ADAPTIVITY BIT17
//MAC Functions
#define ODM_COMP_EDCA_TURBO BIT18
#define ODM_COMP_EARLY_MODE BIT19
//RF Functions
#define ODM_COMP_TX_PWR_TRACK BIT24
#define ODM_COMP_RX_GAIN_TRACK BIT25
#define ODM_COMP_CALIBRATION BIT26
//Common Functions
#define ODM_COMP_INIT BIT29
#define ODM_COMP_COMMON BIT30
#define ODM_COMP_FIX BIT31
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define RT_PRINTK DbgPrint
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#define DbgPrint printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#define RT_DISP(dbgtype, dbgflag, printstr)
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#define DbgPrint printf
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#define RT_DISP(dbgtype, dbgflag, printstr)
#else
#define DbgPrint panic_printk
#define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args);
#endif
#ifndef ASSERT
#define ASSERT(expr)
#endif
#if DBG
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \
if(((comp) & ROMInfo.DebugComponents) && (level <= ROMInfo.DebugLevel || level == ODM_DBG_SERIOUS)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \
if(((comp) & ROMInfo.DebugComponents) && (level <= ROMInfo.DebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \
if(!(expr)) { \
DbgPrint( "Assertion failed! %s at ......\n", #expr); \
DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
RT_PRINTK fmt; \
ASSERT(FALSE); \
}
#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); }
#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); }
#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); }
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \
if(((comp) & ROMInfo.DebugComponents) && (level <= ROMInfo.DebugLevel)) \
{ \
int __i; \
pu1Byte __ptr = (pu1Byte)ptr; \
DbgPrint("[ODM] "); \
DbgPrint(title_str); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#else
#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt)
#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt)
#define ODM_RT_ASSERT(pDM_Odm, expr, fmt)
#define ODM_dbg_enter()
#define ODM_dbg_exit()
#define ODM_dbg_trace(str)
#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr)
#endif
VOID
ODM_InitDebugSetting(
IN PDM_ODM_T pDM_Odm
);
#if 0
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if(((_Comp) & ODM_GlobalDebugComponents) && (_Level <= ODM_GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif
#if 0
/* Define debug print header for every service module.*/
typedef struct tag_ODM_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}ODM_DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_ODM_DBGP_Flag_Type_Definition
{
ODM_FTX = 0,
ODM_FRX ,
ODM_FPHY ,
ODM_FPWR ,
ODM_FDM ,
ODM_FC2H ,
ODM_FBT ,
ODM_DBGP_TYPE_MAX
}ODM_DBGP_FLAG_E;
// Define TX relative debug bit --> FTX
#define ODM_TX_DESC BIT0
#define ODM_TX_DESC_TID BIT1
#define ODM_TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define ODM_RX_DATA BIT0
#define ODM_RX_PHY_STS BIT1
#define ODM_RX_PHY_SS BIT2
#define ODM_RX_PHY_SQ BIT3
#define ODM_RX_PHY_ASTS BIT4
#define ODM_RX_ERR_LEN BIT5
#define ODM_RX_DEFRAG BIT6
#define ODM_RX_ERR_RATE BIT7
#define ODM_RX_PATH BIT8
#define ODM_RX_BEACON BIT9
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define ODM_PHY_BBR BIT0
#define ODM_PHY_BBW BIT1
#define ODM_PHY_RFR BIT2
#define ODM_PHY_RFW BIT3
#define ODM_PHY_MACR BIT4
#define ODM_PHY_MACW BIT5
#define ODM_PHY_ALLR BIT6
#define ODM_PHY_ALLW BIT7
#define ODM_PHY_TXPWR BIT8
#define ODM_PHY_PWRDIFF BIT9
#define ODM_PHY_SICR BIT10
#define ODM_PHY_SICW BIT11
extern u4Byte ODM_GlobalDebugLevel;
#if DBG
extern u8Byte ODM_GlobalDebugComponents;
#endif
#endif
#if 0
//-----------------------------------------------------------------------------
// Define the debug levels
//
// 1. DBG_TRACE and DBG_LOUD are used for normal cases.
// So that, they can help SW engineer to develope or trace states changed
// and also help HW enginner to trace every operation to and from HW,
// e.g IO, Tx, Rx.
//
// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases,
// which help us to debug SW or HW.
//
//-----------------------------------------------------------------------------
//
// Never used in a call to ODM_RT_TRACE(pDM_Odm,)!
//
#define DBG_OFF 0
//
// Deprecated! Don't use it!
// TODO: fix related debug message!
//
//#define DBG_SEC 1
//
// Fatal bug.
// For example, Tx/Rx/IO locked up, OS hangs, memory access violation,
// resource allocation failed, unexpected HW behavior, HW BUG and so on.
//
#define DBG_SERIOUS 2
//
// Abnormal, rare, or unexpeted cases.
// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on.
//
#define DBG_WARNING 3
//
// Normal case with useful information about current SW or HW state.
// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status,
// SW protocol state change, dynamic mechanism state change and so on.
//
#define DBG_LOUD 4
//
// Normal case with detail execution flow or information.
//
#define DBG_TRACE 5
//-----------------------------------------------------------------------------
// Define the tracing components
//
//-----------------------------------------------------------------------------
#define COMP_TRACE BIT0 // For function call tracing.
#define COMP_DBG BIT1 // Only for temporary debug message.
#define COMP_INIT BIT2 // during driver initialization / halt / reset.
#define COMP_OID_QUERY BIT3 // Query OID.
#define COMP_OID_SET BIT4 // Set OID.
#define COMP_RECV BIT5 // Reveive part data path.
#define COMP_SEND BIT6 // Send part path.
#define COMP_IO BIT7 // I/O Related. Added by Annie, 2006-03-02.
#define COMP_POWER BIT8 // 802.11 Power Save mode or System/Device Power state related.
#define COMP_MLME BIT9 // 802.11 link related: join/start BSS, leave BSS.
#define COMP_SCAN BIT10 // For site survey.
#define COMP_SYSTEM BIT11 // For general platform function.
#define COMP_SEC BIT12 // For Security.
#define COMP_AP BIT13 // For AP mode related.
#define COMP_TURBO BIT14 // For Turbo Mode related. By Annie, 2005-10-21.
#define COMP_QOS BIT15 // For QoS.
#define COMP_AUTHENTICATOR BIT16 // For AP mode Authenticator. Added by Annie, 2006-01-30.
#define COMP_BEACON BIT17 // For Beacon related, by rcnjko.
#define COMP_ANTENNA BIT18 // For Antenna diversity related, by rcnjko.
#define COMP_RATE BIT19 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
#define COMP_EVENTS BIT20 // Event handling
#define COMP_FPGA BIT21 // For FPGA verfication
#define COMP_RM BIT22 // For Radio Measurement.
#define COMP_MP BIT23 // For mass production test, by shien chang, 2006.07.13
#define COMP_RXDESC BIT24 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
#define COMP_CKIP BIT25 // For CCX 1 S13: CKIP. Added by Annie, 2006-08-14.
#define COMP_DIG BIT26 // For DIG, 2006.09.25, by rcnjko.
#define COMP_TXAGC BIT27 // For Tx power, 060928, by rcnjko.
#define COMP_HIPWR BIT28 // For High Power Mechanism, 060928, by rcnjko.
#define COMP_HALDM BIT29 // For HW Dynamic Mechanism, 061010, by rcnjko.
#define COMP_RSNA BIT30 // For RSNA IBSS , 061201, by CCW.
#define COMP_INDIC BIT31 // For link indication
#define COMP_LED BIT32 // For LED.
#define COMP_RF BIT33 // For RF.
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
//1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
//1!!!!!!!!!!!!!!!!!!!!!!!!!!!
#define COMP_HT BIT34 // For 802.11n HT related information. by Emily 2006-8-11
#define COMP_POWER_TRACKING BIT35 //FOR 8190 TX POWER TRACKING
#define COMP_RX_REORDER BIT36 // 8190 Rx Reorder
#define COMP_AMSDU BIT37 // For A-MSDU Debugging
#define COMP_WPS BIT38 //WPS Debug Message
#define COMP_RATR BIT39
#define COMP_RESET BIT40
// For debug command to print on dbgview!!
#define COMP_CMD BIT41
#define COMP_EFUSE BIT42
#define COMP_MESH_INTERWORKING BIT43
#define COMP_CCX BIT44 //CCX Debug Flag
#define COMP_IOCTL BIT45 // IO Control
#define COMP_GP BIT46 // For generic parser.
#define COMP_TXAGG BIT47
#define COMP_HVL BIT48 // For Ndis 6.2 Context Swirch and Hardware Virtualiztion Layer
#define COMP_TEST BIT49
#define COMP_BB_POWERSAVING BIT50
#define COMP_SWAS BIT51 // For SW Antenna Switch
#define COMP_P2P BIT52
#define COMP_MUX BIT53
#define COMP_FUNC BIT54
#define COMP_TDLS BIT55
#define COMP_OMNIPEEK BIT56
#define COMP_DUALMACSWITCH BIT60 // 2010/12/27 Add for Dual mac mode debug
#define COMP_EASY_CONCURRENT BIT61 // 2010/12/27 Add for easy cncurrent mode debug
#define COMP_PSD BIT63 //2011/3/9 Add for WLAN PSD for BT AFH
#define COMP_DFS BIT62
#define COMP_ALL UINT64_C(0xFFFFFFFFFFFFFFFF) // All components
// For debug print flag to use
/*------------------------------Define structure----------------------------*/
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/* Defnie structure to store different debug flag variable. Every debug flag
is a UINT32 integer and you can assign 32 different events. */
typedef struct tag_DBGP_Debug_Flag_Structure
{
u4Byte Mans; /* Main Scheduler module. */
u4Byte Rtos; /* RTOS module. */
u4Byte Alarm; /* Alarm module. */
u4Byte Pm; /* Performance monitor module. */
}DBGP_FLAG_T;
/* Define debug print header for every service module.*/
typedef struct tag_DBGP_Service_Module_Header_Name_Structure
{
const char *pMANS;
const char *pRTOS;
const char *pALM;
const char *pPEM;
const char *pCMPK;
const char *pRAPD;
const char *pTXPB;
const char *pQUMG;
}DBGP_HEAD_T;
/* Define different debug flag for dedicated service modules in debug flag array. */
// Each module has independt 32 bit debug flag you cnn define the flag as yout require.
typedef enum tag_DBGP_Flag_Type_Definition
{
FQoS = 0,
FTX = 1,
FRX = 2,
FSEC = 3,
FMGNT = 4,
FMLME = 5,
FRESOURCE = 6,
FBEACON = 7,
FISR = 8,
FPHY = 9,
FMP = 10,
FEEPROM = 11,
FPWR = 12,
FDM = 13,
FDBG_CTRL = 14,
FC2H = 15,
FBT = 16,
FINIT = 17,
FIOCTL = 18,
FSHORT_CUT = 19,
DBGP_TYPE_MAX
}DBGP_FLAG_E;
// Define Qos Relative debug flag bit --> FQoS
#define QoS_INIT BIT0
#define QoS_VISTA BIT1
// Define TX relative debug bit --> FTX
#define TX_DESC BIT0
#define TX_DESC_TID BIT1
#define TX_PATH BIT2
// Define RX relative debug bit --> FRX
#define RX_DATA BIT0
#define RX_PHY_STS BIT1
#define RX_PHY_SS BIT2
#define RX_PHY_SQ BIT3
#define RX_PHY_ASTS BIT4
#define RX_ERR_LEN BIT5
#define RX_DEFRAG BIT6
#define RX_ERR_RATE BIT7
#define RX_PATH BIT8
#define RX_BEACON BIT9
// Define Security relative debug bit --> FSEC
// Define MGNT relative debug bit --> FMGNT
// Define MLME relative debug bit --> FMLME
#define MEDIA_STS BIT0
#define LINK_STS BIT1
// Define OS resource check module bit --> FRESOURCE
#define OS_CHK BIT0
// Define beacon content check module bit --> FBEACON
#define BCN_SHOW BIT0
#define BCN_PEER BIT1
// Define ISR/IMR check module bit --> FISR
#define ISR_CHK BIT0
// Define PHY-BB/RF/MAC check module bit --> FPHY
#define PHY_BBR BIT0
#define PHY_BBW BIT1
#define PHY_RFR BIT2
#define PHY_RFW BIT3
#define PHY_MACR BIT4
#define PHY_MACW BIT5
#define PHY_ALLR BIT6
#define PHY_ALLW BIT7
#define PHY_TXPWR BIT8
#define PHY_PWRDIFF BIT9
#define PHY_SICR BIT10
#define PHY_SICW BIT11
// Define MPT driver check module bit --> FMP
#define MP_RX BIT0
#define MP_SWICH_CH BIT1
// Define EEPROM and EFUSE check module bit --> FEEPROM
#define EEPROM_W BIT0
#define EFUSE_PG BIT1
#define EFUSE_READ_ALL BIT2
#define EFUSE_ANALYSIS BIT3
#define EFUSE_PG_DETAIL BIT4
// Define power save check module bit --> FPWR
#define LPS BIT0
#define IPS BIT1
#define PWRSW BIT2
#define PWRHW BIT3
#define PWRHAL BIT4
// Define Dynamic Mechanism check module bit --> FDM
#define WA_IOT BIT0
#define DM_PWDB BIT1
#define DM_Monitor BIT2
#define DM_DIG BIT3
#define DM_EDCA_Turbo BIT4
#define DM_BT30 BIT5
// Define Dbg Control module bit --> FDBG_CTRL
#define DBG_CTRL_TRACE BIT0
#define DBG_CTRL_INBAND_NOISE BIT1
// Define FW C2H Cmd check module bit --> FC2H
#define C2H_Summary BIT0
#define C2H_PacketData BIT1
#define C2H_ContentData BIT2
// Define BT Cmd check module bit --> FBT
#define BT_TRACE BIT0
#define BT_RFPoll BIT1
// Define init check for module bit --> FINIT
#define INIT_EEPROM BIT0
#define INIT_TxPower BIT1
#define INIT_IQK BIT2
#define INIT_RF BIT3
// Define IOCTL Cmd check module bit --> FIOCTL
// section 1 : IRP related
#define IOCTL_IRP BIT0
#define IOCTL_IRP_DETAIL BIT1
#define IOCTL_IRP_STATISTICS BIT2
#define IOCTL_IRP_HANDLE BIT3
// section 2 : HCI command/event
#define IOCTL_BT_HCICMD BIT8
#define IOCTL_BT_HCICMD_DETAIL BIT9
#define IOCTL_BT_HCICMD_EXT BIT10
#define IOCTL_BT_EVENT BIT11
#define IOCTL_BT_EVENT_DETAIL BIT12
#define IOCTL_BT_EVENT_PERIODICAL BIT13
// section 3 : BT tx/rx data and throughput
#define IOCTL_BT_TX_ACLDATA BIT16
#define IOCTL_BT_TX_ACLDATA_DETAIL BIT17
#define IOCTL_BT_RX_ACLDATA BIT18
#define IOCTL_BT_RX_ACLDATA_DETAIL BIT19
#define IOCTL_BT_TP BIT20
// section 4 : BT connection state machine.
#define IOCTL_STATE BIT21
#define IOCTL_BT_LOGO BIT22
// section 5 : BT function trace
#define IOCTL_CALLBACK_FUN BIT24
#define IOCTL_PARSE_BT_PKT BIT25
#define IOCTL_BT_TX_PKT BIT26
#define IOCTL_BT_FLAG_MON BIT27
//
// Define init check for module bit --> FSHORT_CUT
// 2011/07/20 MH Add for short but definition.
//
#define SHCUT_TX BIT0
#define SHCUT_RX BIT1
/* 2007/07/13 MH *//*------For DeBuG Print modeue------*/
/*------------------------------Define structure----------------------------*/
/*------------------------Export Marco Definition---------------------------*/
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define RT_PRINTK(fmt, args...) printk( "%s(): " fmt, __FUNCTION__, ## args);
#if DBG
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt) \
if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_TRACE_F(comp, level, fmt) \
if(((comp) & GlobalDebugComponents) && (level <= GlobalDebugLevel)) \
{ \
RT_PRINTK fmt; \
}
#define RT_ASSERT(expr,fmt) \
if(!(expr)) { \
printk( "Assertion failed! %s at ......\n", #expr); \
printk( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \
}
#define dbg_enter() { printk("==> %s\n", __FUNCTION__); }
#define dbg_exit() { printk("<== %s\n", __FUNCTION__); }
#define dbg_trace(str) { printk("%s:%s\n", __FUNCTION__, str); }
#else
#define ODM_RT_TRACE(pDM_Odm,comp, level, fmt)
#define RT_TRACE_F(comp, level, fmt)
#define RT_ASSERT(expr, fmt)
#define dbg_enter()
#define dbg_exit()
#define dbg_trace(str)
#endif
#if DBG
#define DbgPrint printk
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen) \
{ \
char *szTitle = _TitleString; \
pu1Byte pbtHexData = _HexData; \
u4Byte u4bHexDataLen = _HexDataLen; \
u4Byte __i; \
DbgPrint("%s", szTitle); \
for (__i=0;__i<u4bHexDataLen;__i++) \
{ \
if ((__i & 15) == 0) \
{ \
DbgPrint("\n"); \
} \
DbgPrint("%02X%s", pbtHexData[__i], ( ((__i&3)==3) ? " " : " ") ); \
} \
DbgPrint("\n"); \
}
// RT_PRINT_XXX macros: implemented for debugging purpose.
// Added by Annie, 2005-11-21.
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \
if (((__i + 1) % 16) == 0) DbgPrint("\n"); \
} \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i, __j; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint("\n"); \
for( __i=0; __i<(int)_AddNum; __i++ ) \
{ \
for( __j=0; __j<6; __j++ ) \
DbgPrint("%02X%s", ptr[__i*6+__j], (__j==5)?"":"-"); \
DbgPrint("\n"); \
} \
}
// Added by Annie, 2005-11-22.
#define MAX_STR_LEN 64
#define PRINTABLE(_ch) (_ch>=' ' &&_ch<='~' ) // I want to see ASCII 33 to 126 only. Otherwise, I print '?'. Annie, 2005-11-22.
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len) \
if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \
{ \
int __i; \
u1Byte buffer[MAX_STR_LEN]; \
int length = (_Len<MAX_STR_LEN)? _Len : (MAX_STR_LEN-1) ; \
PlatformZeroMemory( buffer, MAX_STR_LEN ); \
PlatformMoveMemory( buffer, (pu1Byte)_Ptr, length ); \
for( __i=0; __i<MAX_STR_LEN; __i++ ) \
{ \
if( !PRINTABLE(buffer[__i]) ) buffer[__i] = '?'; \
} \
buffer[length] = '\0'; \
DbgPrint("Rtl819x: "); \
DbgPrint(_TitleString); \
DbgPrint(": %d, <%s>\n", _Len, buffer); \
}
#else // of #if DBG
#define DbgPrint(...)
#define PRINT_DATA(_TitleString, _HexData, _HexDataLen)
#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen)
#define RT_PRINT_ADDR(_Comp, _Level, _TitleString, _Ptr)
#define RT_PRINT_ADDRS(_Comp, _Level, _TitleString, _Ptr, _AddNum)
#define RT_PRINT_STR(_Comp, _Level, _TitleString, _Ptr, _Len)
#endif // of #if DBG
#endif // #if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define DEBUG_PRINT 1
// Please add new OS's print API by yourself
//#if (RT_PLATFORM==PLATFORM_WINDOWS)
#if (DEBUG_PRINT == 1) && DBG
#define RT_DISP(dbgtype, dbgflag, printstr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
DbgPrint printstr;\
}\
}
#define RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_Ptr; \
DbgPrint printstr; \
DbgPrint(" "); \
for( __i=0; __i<6; __i++ ) \
DbgPrint("%02X%s", ptr[__i], (__i==5)?"":"-"); \
DbgPrint("\n"); \
}\
}
#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)\
{\
if (DBGP_Type[dbgtype] & dbgflag)\
{\
int __i; \
pu1Byte ptr = (pu1Byte)_HexData; \
DbgPrint(_TitleString); \
for( __i=0; __i<(int)_HexDataLen; __i++ ) \
{ \
DbgPrint("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" ");\
if (((__i + 1) % 16) == 0) DbgPrint("\n");\
} \
DbgPrint("\n"); \
}\
}
#define FunctionIn(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("==========> %s\n", __FUNCTION__))
#define FunctionOut(_comp) ODM_RT_TRACE(pDM_Odm,(_comp), DBG_LOUD, ("<========== %s\n", __FUNCTION__))
#else
#define RT_DISP(dbgtype, dbgflag, printstr)
#define RT_DISP_ADDR(dbgtype, dbgflag, printstr, _Ptr)
#define RT_DISP_DATA(dbgtype, dbgflag, _TitleString, _HexData, _HexDataLen)
#define FunctionIn(_comp)
#define FunctionOut(_comp)
#endif
/*------------------------Export Marco Definition---------------------------*/
/*------------------------Export global variable----------------------------*/
extern u4Byte DBGP_Type[DBGP_TYPE_MAX];
extern DBGP_HEAD_T DBGP_Head;
/*------------------------Export global variable----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
extern void DBGP_Flag_Init(void);
extern void DBG_PrintAllFlag(void);
extern void DBG_PrintAllComp(void);
extern void DBG_PrintFlagEvent(u1Byte DbgFlag);
extern void DBG_DumpMem(const u1Byte DbgComp,
const u1Byte DbgLevel,
pu1Byte pMem,
u2Byte Len);
/*--------------------------Exported Function prototype---------------------*/
extern u4Byte GlobalDebugLevel;
extern u8Byte GlobalDebugComponents;
#endif
#endif // __ODM_DBG_H__

413
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_interface.h Normal file
View file

@ -0,0 +1,413 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_INTERFACE_H__
#define __ODM_INTERFACE_H__
//
// =========== Constant/Structure/Enum/... Define
//
//
// =========== Macro Define
//
#define _reg_all(_name) ODM_##_name
#define _reg_ic(_name, _ic) ODM_##_name##_ic
#define _bit_all(_name) BIT_##_name
#define _bit_ic(_name, _ic) BIT_##_name##_ic
// _cat: implemented by Token-Pasting Operator.
#if 0
#define _cat(_name, _ic_type, _func) \
( \
_func##_all(_name) \
)
#endif
/*===================================
#define ODM_REG_DIG_11N 0xC50
#define ODM_REG_DIG_11AC 0xDDD
ODM_REG(DIG,_pDM_Odm)
=====================================*/
#define _reg_11N(_name) ODM_REG_##_name##_11N
#define _reg_11AC(_name) ODM_REG_##_name##_11AC
#define _bit_11N(_name) ODM_BIT_##_name##_11N
#define _bit_11AC(_name) ODM_BIT_##_name##_11AC
#ifdef __ECOS
#define _rtk_cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
_func##_11AC(_name) \
)
#else
#define _cat(_name, _ic_type, _func) \
( \
((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \
_func##_11AC(_name) \
)
#endif
/*
// only sample code
//#define _cat(_name, _ic_type, _func) \
// ( \
// ((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C): \
// ((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D): \
// ((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S): \
// ((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A): \
// ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \
// _func##_ic(_name, _8195) \
// )
*/
// _name: name of register or bit.
// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)"
// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType.
#ifdef __ECOS
#define ODM_REG(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _bit)
#else
#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg)
#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)
#endif
typedef enum _ODM_H2C_CMD
{
/*ODM_H2C_RSSI_REPORT = 0,
ODM_H2C_PSD_RESULT=1,
ODM_H2C_PathDiv = 2,
ODM_H2C_WIFI_CALIBRATION = 3,
ODM_H2C_IQ_CALIBRATION = 4,
ODM_H2C_RA_PARA_ADJUST=5,
ODM_MAX_H2CCMD*/
PHYDM_H2C_TXBF = 0x41,
ODM_H2C_RSSI_REPORT = 0x42,
ODM_H2C_IQ_CALIBRATION = 0x45,
ODM_H2C_RA_PARA_ADJUST = 0x47,
PHYDM_H2C_DYNAMIC_TX_PATH = 0x48,
PHYDM_H2C_FW_TRACE_EN = 0x49,
ODM_H2C_WIFI_CALIBRATION = 0x6d,
PHYDM_H2C_MU = 0x4a,
ODM_MAX_H2CCMD
}ODM_H2C_CMD;
//
// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem.
// Suggest HW team to use thread instead of workitem. Windows also support the feature.
//
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
typedef void *PRT_WORK_ITEM ;
typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE;
typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext);
#if 0
typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE;
typedef struct _RT_WORK_ITEM
{
RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object.
PVOID Adapter; // Pointer to Adapter object.
PVOID pContext; // Parameter to passed to CallBackFunc().
RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem.
u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled.
PVOID pPlatformExt; // Pointer to platform-dependent extension.
BOOLEAN bFree;
char szID[36]; // An identity string of this workitem.
}RT_WORK_ITEM, *PRT_WORK_ITEM;
#endif
#endif
//
// =========== Extern Variable ??? It should be forbidden.
//
//
// =========== EXtern Function Prototype
//
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u2Byte
ODM_Read2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
u4Byte
ODM_Read4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
);
VOID
ODM_Write1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u1Byte Data
);
VOID
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
);
VOID
ODM_Write4Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte Data
);
VOID
ODM_SetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetMACReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetBBReg(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
VOID
ODM_SetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask,
IN u4Byte Data
);
u4Byte
ODM_GetRFReg(
IN PDM_ODM_T pDM_Odm,
IN ODM_RF_RADIO_PATH_E eRFPath,
IN u4Byte RegAddr,
IN u4Byte BitMask
);
//
// Memory Relative Function.
//
VOID
ODM_AllocateMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID *pPtr,
IN u4Byte length
);
VOID
ODM_FreeMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pPtr,
IN u4Byte length
);
VOID
ODM_MoveMemory(
IN PDM_ODM_T pDM_Odm,
OUT PVOID pDest,
IN PVOID pSrc,
IN u4Byte Length
);
s4Byte ODM_CompareMemory(
IN PDM_ODM_T pDM_Odm,
IN PVOID pBuf1,
IN PVOID pBuf2,
IN u4Byte length
);
void ODM_Memory_Set
(IN PDM_ODM_T pDM_Odm,
IN PVOID pbuf,
IN s1Byte value,
IN u4Byte length);
//
// ODM MISC-spin lock relative API.
//
#if( DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL|ODM_CE))
VOID
ODM_AcquireSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
VOID
ODM_ReleaseSpinLock(
IN PDM_ODM_T pDM_Odm,
IN RT_SPINLOCK_TYPE type
);
#endif
//
// ODM MISC-workitem relative API.
//
VOID
ODM_InitializeWorkItem(
IN PDM_ODM_T pDM_Odm,
IN PRT_WORK_ITEM pRtWorkItem,
IN RT_WORKITEM_CALL_BACK RtWorkItemCallback,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_StartWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_StopWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_FreeWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_ScheduleWorkItem(
IN PRT_WORK_ITEM pRtWorkItem
);
VOID
ODM_IsWorkItemScheduled(
IN PRT_WORK_ITEM pRtWorkItem
);
//
// ODM Timer relative API.
//
VOID
ODM_StallExecution(
IN u4Byte usDelay
);
VOID
ODM_delay_ms(IN u4Byte ms);
VOID
ODM_delay_us(IN u4Byte us);
VOID
ODM_sleep_ms(IN u4Byte ms);
VOID
ODM_sleep_us(IN u4Byte us);
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE|ODM_AP|ODM_ADSL))
VOID
ODM_SetTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN u4Byte msDelay
);
VOID
ODM_InitializeTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer,
IN RT_TIMER_CALL_BACK CallBackFunc,
IN PVOID pContext,
IN const char* szID
);
VOID
ODM_CancelTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
VOID
ODM_ReleaseTimer(
IN PDM_ODM_T pDM_Odm,
IN PRT_TIMER pTimer
);
#endif
//
// ODM FW relative API.
//
VOID
ODM_FillH2CCmd(
IN PDM_ODM_T pDM_Odm,
IN u1Byte ElementID,
IN u4Byte CmdLen,
IN pu1Byte pCmdBuffer
);
u8Byte
ODM_GetCurrentTime(
IN PDM_ODM_T pDM_Odm
);
u8Byte
ODM_GetProgressingTime(
IN PDM_ODM_T pDM_Odm,
IN u8Byte Start_Time
);
#endif // __ODM_INTERFACE_H__

349
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_precomp.h Normal file
View file

@ -0,0 +1,349 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_PRECOMP_H__
#define __ODM_PRECOMP_H__
#include "phydm_types.h"
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting.
#else
#define TEST_FALG___ 1
#endif
//2 Config Flags and Structs - defined by each ODM Type
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "../8192cd_cfg.h"
#include "../odm_inc.h"
#include "../8192cd.h"
#include "../8192cd_util.h"
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#ifdef AP_BUILD_WORKAROUND
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
// Flags
#include "../8192cd_cfg.h" // OUTSRC needs ADSL config flags.
#include "../odm_inc.h" // OUTSRC needs some extra flags.
// Data Structure
#include "../common_types.h" // OUTSRC and rtl8192cd both needs basic type such as UINT8 and BIT0.
#include "../8192cd.h" // OUTSRC needs basic ADSL struct definition.
#include "../8192cd_util.h" // OUTSRC needs basic I/O function.
#ifdef _BIG_ENDIAN_
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#else
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
#ifdef ADSL_AP_BUILD_WORKAROUND
// NESTED_INC: Functions defined outside should not be included!! Marked by Annie, 2011-10-14.
#include "../8192cd_headers.h"
#include "../8192cd_debug.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE)
#define BEAMFORMING_SUPPORT 0
#elif (DM_ODM_SUPPORT_TYPE ==ODM_IOT)
#define BEAMFORMING_SUPPORT 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#include "mp_precomp.h"
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#endif
//2 Hardware Parameter Files
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/Hal8192CEFWImg_AP.h"
#include "rtl8192c/Hal8192CEPHYImg_AP.h"
#include "rtl8192c/Hal8192CEMACImg_AP.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/Hal8192CEFWImg_ADSL.h"
#include "rtl8192c/Hal8192CEPHYImg_ADSL.h"
#include "rtl8192c/Hal8192CEMACImg_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#if(RTL8192CE_SUPPORT ==1)
#include "rtl8192c/Hal8192CEFWImg_CE.h"
#include "rtl8192c/Hal8192CEPHYImg_CE.h"
#include "rtl8192c/Hal8192CEMACImg_CE.h"
#endif
#if(RTL8192CU_SUPPORT ==1)
#include "rtl8192c/Hal8192CUFWImg_CE.h"
#include "rtl8192c/Hal8192CUPHYImg_CE.h"
#include "rtl8192c/Hal8192CUMACImg_CE.h"
#endif
#if(RTL8192DE_SUPPORT ==1)
#include "rtl8192d/Hal8192DEFWImg_CE.h"
#include "rtl8192d/Hal8192DEPHYImg_CE.h"
#include "rtl8192d/Hal8192DEMACImg_CE.h"
#endif
#if(RTL8192DU_SUPPORT ==1)
#include "rtl8192d/Hal8192DUFWImg_CE.h"
#include "rtl8192d/Hal8192DUPHYImg_CE.h"
#include "rtl8192d/Hal8192DUMACImg_CE.h"
#endif
#if(RTL8723AS_SUPPORT==1)
#include "rtl8723a/Hal8723SHWImg_CE.h"
#endif
#if(RTL8723AU_SUPPORT==1)
#include "rtl8723a/Hal8723UHWImg_CE.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#endif
//2 OutSrc Header Files
#if (RTL8188E_SUPPORT==1)
// Old ODM
#include "rtl8188e\odm.h"
#include "rtl8188e\odm_HWConfig.h"
#include "rtl8188e\odm_debug.h"
#include "rtl8188e\odm_RegDefine11AC.h"
#include "rtl8188e\odm_RegDefine11N.h"
#include "rtl8188e\odm_interface.h"
#include "rtl8188e\odm_reg.h"
#include "rtl8188e\Hal8188EAdaptivity.h"
#else
// new ODM
#include "phydm.h"
#include "phydm_HWConfig.h"
#include "phydm_debug.h"
#include "phydm_RegDefine11AC.h"
#include "phydm_RegDefine11N.h"
#include "phydm_AntDiv.h"
#include "phydm_EdcaTurboCheck.h"
#include "phydm_DIG.h"
#include "PhyDM_Adaptivity.h"
#include "phydm_PathDiv.h"
#include "phydm_RaInfo.h"
#include "phydm_DynamicBBPowerSaving.h"
#include "phydm_DynamicTxPower.h"
#include "phydm_CfoTracking.h"
#include "phydm_NoiseMonitor.h"
#include "phydm_interface.h"
#include "phydm_reg.h"
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#if (RTL8192C_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_AP.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
#include "rtl8192c/HalDMOutSrc8192C_ADSL.h"
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
//#include "hal_com.h"
#include "HalPhyRf.h"
#if (RTL8192C_SUPPORT==1)
#ifdef CONFIG_INTEL_PROXIM
#include "../proxim/intel_proxim.h"
#endif
#include "rtl8192c/HalDMOutSrc8192C_CE.h"
#include <rtl8192c_hal.h>
#endif
#if (RTL8192D_SUPPORT==1)
#include "rtl8192d/HalDMOutSrc8192D_CE.h"
#include "rtl8192d_hal.h"
#endif
#if (RTL8723A_SUPPORT==1)
#include "rtl8192c/HalDMOutSrc8192C_CE.h" //for IQK,LCK,Power-tracking
#include "../rtl8723a/rtl8723a_hal.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/HalPhyRf_8188e.h"//for IQK,LCK,Power-tracking
#include "rtl8188e/Hal8188ERateAdaptive.h"//for RA,Power training
#include "../rtl8188e/rtl8188e_hal.h"
#endif
#if (RTL8192E_SUPPORT==1)
#include "rtl8192e/HalPhyRf_8192e.h"//for IQK,LCK,Power-tracking
#include "rtl8192e_hal.h"
#endif
#if (RTL8812A_SUPPORT==1)
#include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a_hal.h"
#endif
#if (RTL8821A_SUPPORT==1)
#include "rtl8821a/HalPhyRf_8821A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a/HalPhyRf_8812A.h"//for IQK,LCK,Power-tracking
#include "rtl8812a_hal.h"
#endif
#if (RTL8723B_SUPPORT==1)
#include "rtl8723b/HalPhyRf_8723B.h"//for IQK,LCK,Power-tracking
#include "rtl8723b_hal.h"
#endif
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#include "HalPhyRf.h"
#if (RTL8195A_SUPPORT==1)
#include "rtl8195a/HalPhyRf_8195A.h"//for IQK,LCK,Power-tracking
#include "rtl8195a_hal.h"
#endif
#if (RTL8711B_SUPPORT==1)
#include "rtl8711b/HalPhyRf_8711b.h"//for IQK,LCK,Power-tracking
#include "rtl8711b_hal.h"
#endif
#endif
#if (RTL8192C_SUPPORT==1)
#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
#include "rtl8192c/Hal8192CHWImg_MAC.h"
#include "rtl8192c/Hal8192CHWImg_RF.h"
#include "rtl8192c/Hal8192CHWImg_BB.h"
#include "rtl8192c/Hal8192CHWImg_FW.h"
#endif
#include "rtl8192c/phydm_RTL8192C.h"
#endif
#if (RTL8192D_SUPPORT==1)
#include "rtl8192d/phydm_RTL8192D.h"
#endif
#if (RTL8723A_SUPPORT==1)
#include "rtl8723a/HalHWImg8723A_MAC.h"
#include "rtl8723a/HalHWImg8723A_RF.h"
#include "rtl8723a/HalHWImg8723A_BB.h"
#include "rtl8723a/HalHWImg8723A_FW.h"
#include "rtl8723a/phydm_RegConfig8723A.h"
#endif
#if (RTL8188E_SUPPORT==1)
#include "rtl8188e/HalHWImg8188E_MAC.h"
#include "rtl8188e/HalHWImg8188E_RF.h"
#include "rtl8188e/HalHWImg8188E_BB.h"
#include "rtl8188e/HalHWImg8188E_FW.h"
#include "rtl8188e/Hal8188EReg.h"
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
#include "rtl8188e/HalPhyRf_8188e.h"
#endif
#if (TEST_CHIP_SUPPORT == 1)
#include "rtl8188e/HalHWImg8188E_TestChip_MAC.h"
#include "rtl8188e/HalHWImg8188E_TestChip_RF.h"
#include "rtl8188e/HalHWImg8188E_TestChip_BB.h"
#endif
#include "rtl8188e/odm_RegConfig8188E.h"
#include "rtl8188e/odm_RTL8188E.h"
#endif
#if (RTL8192E_SUPPORT==1)
#include "rtl8192e/HalHWImg8192E_MAC.h"
#include "rtl8192e/HalHWImg8192E_RF.h"
#include "rtl8192e/HalHWImg8192E_BB.h"
#include "rtl8192e/HalHWImg8192E_FW.h"
#include "rtl8192e/Hal8192EReg.h"
#include "rtl8192e/phydm_RegConfig8192E.h"
#include "rtl8192e/phydm_RTL8192E.h"
#endif
#if (RTL8723B_SUPPORT==1)
#include "rtl8723b/HalHWImg8723B_MAC.h"
#include "rtl8723b/HalHWImg8723B_RF.h"
#include "rtl8723b/HalHWImg8723B_BB.h"
#include "rtl8723b/HalHWImg8723B_FW.h"
#include "rtl8723b/HalHWImg8723B_MP.h"
#include "rtl8723b/Hal8723BReg.h"
#include "rtl8723b/phydm_RTL8723B.h"
#include "rtl8723b/phydm_RegConfig8723B.h"
#endif
#if (RTL8812A_SUPPORT==1)
#include "rtl8812a/HalHWImg8812A_MAC.h"
#include "rtl8812a/HalHWImg8812A_RF.h"
#include "rtl8812a/HalHWImg8812A_BB.h"
#include "rtl8812a/HalHWImg8812A_FW.h"
#include "rtl8812a/phydm_RegConfig8812A.h"
#include "rtl8812a/phydm_RTL8812A.h"
#endif
#if (RTL8821A_SUPPORT==1)
#include "rtl8821a/HalHWImg8821A_MAC.h"
#include "rtl8821a/HalHWImg8821A_RF.h"
#include "rtl8821a/HalHWImg8821A_BB.h"
#include "rtl8821a/HalHWImg8821A_FW.h"
#include "rtl8821a/phydm_RegConfig8821A.h"
#include "rtl8821a/phydm_RTL8821A.h"
#endif
#if (RTL8195A_SUPPORT==1)
#include "rtl8195a/halhwimg8195a_mac.h"
#include "rtl8195a/halhwimg8195a_rf.h"
#include "rtl8195a/halhwimg8195a_bb.h"
#include "rtl8195a/Hal8195AReg.h"
#include "rtl8195a/phydm_RTL8195A.h"
#include "rtl8195a/phydm_RegConfig8195A.h"
#include "rtl8195a/ROM_RTL8195A_PHYDM.h"
#include "rtl8195a/Hal8195ARateAdaptive.h"
#endif
#if (RTL8711B_SUPPORT==1)
#include "rtl8711b/HalHWImg8711B_MAC.h"
#include "rtl8711b/HalHWImg8711B_RF.h"
#include "rtl8711b/HalHWImg8711B_BB.h"
#include "rtl8711b/HalHWImg8711B_FW.h"
#include "rtl8711b/HalHWImg8711B_MP.h"
#include "rtl8711b/Hal8711BReg.h"
#include "rtl8711b/phydm_RTL8711B.h"
#include "rtl8711b/phydm_RegConfig8711B.h"
#include "rtl8711b/ROM_RTL8711B_PHYDM.h"
#include "rtl8711b/Hal8711BRateAdaptive.h"
#endif
#endif // __ODM_PRECOMP_H__

208
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_reg.h Normal file
View file

@ -0,0 +1,208 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//============================================================
// File Name: odm_reg.h
//
// Description:
//
// This file is for general register definition.
//
//
//============================================================
#ifndef __HAL_ODM_REG_H__
#define __HAL_ODM_REG_H__
//
// Register Definition
//
//MAC REG
#define ODM_BB_RESET 0x002
#define ODM_DUMMY 0x4fe
#define RF_T_METER_OLD 0x24
#define RF_T_METER_NEW 0x42
#define ODM_EDCA_VO_PARAM 0x500
#define ODM_EDCA_VI_PARAM 0x504
#define ODM_EDCA_BE_PARAM 0x508
#define ODM_EDCA_BK_PARAM 0x50C
#define ODM_TXPAUSE 0x522
//BB REG
#define ODM_FPGA_PHY0_PAGE8 0x800
#define ODM_PSD_SETTING 0x808
#define ODM_AFE_SETTING 0x818
#define ODM_TXAGC_B_6_18 0x830
#define ODM_TXAGC_B_24_54 0x834
#define ODM_TXAGC_B_MCS32_5 0x838
#define ODM_TXAGC_B_MCS0_MCS3 0x83c
#define ODM_TXAGC_B_MCS4_MCS7 0x848
#define ODM_TXAGC_B_MCS8_MCS11 0x84c
#define ODM_ANALOG_REGISTER 0x85c
#define ODM_RF_INTERFACE_OUTPUT 0x860
#define ODM_TXAGC_B_MCS12_MCS15 0x868
#define ODM_TXAGC_B_11_A_2_11 0x86c
#define ODM_AD_DA_LSB_MASK 0x874
#define ODM_ENABLE_3_WIRE 0x88c
#define ODM_PSD_REPORT 0x8b4
#define ODM_R_ANT_SELECT 0x90c
#define ODM_CCK_ANT_SELECT 0xa07
#define ODM_CCK_PD_THRESH 0xa0a
#define ODM_CCK_RF_REG1 0xa11
#define ODM_CCK_MATCH_FILTER 0xa20
#define ODM_CCK_RAKE_MAC 0xa2e
#define ODM_CCK_CNT_RESET 0xa2d
#define ODM_CCK_TX_DIVERSITY 0xa2f
#define ODM_CCK_FA_CNT_MSB 0xa5b
#define ODM_CCK_FA_CNT_LSB 0xa5c
#define ODM_CCK_NEW_FUNCTION 0xa75
#define ODM_OFDM_PHY0_PAGE_C 0xc00
#define ODM_OFDM_RX_ANT 0xc04
#define ODM_R_A_RXIQI 0xc14
#define ODM_R_A_AGC_CORE1 0xc50
#define ODM_R_A_AGC_CORE2 0xc54
#define ODM_R_B_AGC_CORE1 0xc58
#define ODM_R_AGC_PAR 0xc70
#define ODM_R_HTSTF_AGC_PAR 0xc7c
#define ODM_TX_PWR_TRAINING_A 0xc90
#define ODM_TX_PWR_TRAINING_B 0xc98
#define ODM_OFDM_FA_CNT1 0xcf0
#define ODM_OFDM_PHY0_PAGE_D 0xd00
#define ODM_OFDM_FA_CNT2 0xda0
#define ODM_OFDM_FA_CNT3 0xda4
#define ODM_OFDM_FA_CNT4 0xda8
#define ODM_TXAGC_A_6_18 0xe00
#define ODM_TXAGC_A_24_54 0xe04
#define ODM_TXAGC_A_1_MCS32 0xe08
#define ODM_TXAGC_A_MCS0_MCS3 0xe10
#define ODM_TXAGC_A_MCS4_MCS7 0xe14
#define ODM_TXAGC_A_MCS8_MCS11 0xe18
#define ODM_TXAGC_A_MCS12_MCS15 0xe1c
//RF REG
#define ODM_GAIN_SETTING 0x00
#define ODM_CHANNEL 0x18
#define ODM_RF_T_METER 0x24
#define ODM_RF_T_METER_92D 0x42
#define ODM_RF_T_METER_88E 0x42
#define ODM_RF_T_METER_92E 0x42
#define ODM_RF_T_METER_8812 0x42
//Ant Detect Reg
#define ODM_DPDT 0x300
//PSD Init
#define ODM_PSDREG 0x808
//92D Path Div
#define PATHDIV_REG 0xB30
#define PATHDIV_TRI 0xBA0
//
// Bitmap Definition
//
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP))
// TX AGC
#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
#if defined(CONFIG_WLAN_HAL_8814AE)
#define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8
#define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc
#define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0
#define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4
#define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8
#endif
#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
#if defined(CONFIG_WLAN_HAL_8814AE)
#define rTxAGC_B_MCS19_MCS16_JAguar 0xed8
#define rTxAGC_B_MCS23_MCS20_JAguar 0xedc
#define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0
#define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4
#define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8
#define rTxAGC_C_CCK11_CCK1_JAguar 0x1820
#define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824
#define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828
#define rTxAGC_C_MCS3_MCS0_JAguar 0x182c
#define rTxAGC_C_MCS7_MCS4_JAguar 0x1830
#define rTxAGC_C_MCS11_MCS8_JAguar 0x1834
#define rTxAGC_C_MCS15_MCS12_JAguar 0x1838
#define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c
#define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840
#define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844
#define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848
#define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c
#define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8
#define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc
#define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0
#define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4
#define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8
#define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20
#define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24
#define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28
#define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c
#define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30
#define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34
#define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38
#define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c
#define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40
#define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44
#define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48
#define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c
#define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8
#define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc
#define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0
#define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4
#define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8
#endif
#define bTxAGC_byte0_Jaguar 0xff
#define bTxAGC_byte1_Jaguar 0xff00
#define bTxAGC_byte2_Jaguar 0xff0000
#define bTxAGC_byte3_Jaguar 0xff000000
#endif
#define BIT_FA_RESET BIT0
#endif

442
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/phydm_types.h Normal file
View file

@ -0,0 +1,442 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_TYPES_H__
#define __ODM_TYPES_H__
#define ODM_RATEMCS15_SG 0x1c
#define ODM_RATEMCS32 0x20
// CCK Rates, TxHT = 0
#define ODM_RATE1M 0x00
#define ODM_RATE2M 0x01
#define ODM_RATE5_5M 0x02
#define ODM_RATE11M 0x03
// OFDM Rates, TxHT = 0
#define ODM_RATE6M 0x04
#define ODM_RATE9M 0x05
#define ODM_RATE12M 0x06
#define ODM_RATE18M 0x07
#define ODM_RATE24M 0x08
#define ODM_RATE36M 0x09
#define ODM_RATE48M 0x0A
#define ODM_RATE54M 0x0B
// MCS Rates, TxHT = 1
#define ODM_RATEMCS0 0x0C
#define ODM_RATEMCS1 0x0D
#define ODM_RATEMCS2 0x0E
#define ODM_RATEMCS3 0x0F
#define ODM_RATEMCS4 0x10
#define ODM_RATEMCS5 0x11
#define ODM_RATEMCS6 0x12
#define ODM_RATEMCS7 0x13
#define ODM_RATEMCS8 0x14
#define ODM_RATEMCS9 0x15
#define ODM_RATEMCS10 0x16
#define ODM_RATEMCS11 0x17
#define ODM_RATEMCS12 0x18
#define ODM_RATEMCS13 0x19
#define ODM_RATEMCS14 0x1A
#define ODM_RATEMCS15 0x1B
#define ODM_RATEMCS16 0x1C
#define ODM_RATEMCS17 0x1D
#define ODM_RATEMCS18 0x1E
#define ODM_RATEMCS19 0x1F
#define ODM_RATEMCS20 0x20
#define ODM_RATEMCS21 0x21
#define ODM_RATEMCS22 0x22
#define ODM_RATEMCS23 0x23
#define ODM_RATEMCS24 0x24
#define ODM_RATEMCS25 0x25
#define ODM_RATEMCS26 0x26
#define ODM_RATEMCS27 0x27
#define ODM_RATEMCS28 0x28
#define ODM_RATEMCS29 0x29
#define ODM_RATEMCS30 0x2A
#define ODM_RATEMCS31 0x2B
#define ODM_RATEVHTSS1MCS0 0x2C
#define ODM_RATEVHTSS1MCS1 0x2D
#define ODM_RATEVHTSS1MCS2 0x2E
#define ODM_RATEVHTSS1MCS3 0x2F
#define ODM_RATEVHTSS1MCS4 0x30
#define ODM_RATEVHTSS1MCS5 0x31
#define ODM_RATEVHTSS1MCS6 0x32
#define ODM_RATEVHTSS1MCS7 0x33
#define ODM_RATEVHTSS1MCS8 0x34
#define ODM_RATEVHTSS1MCS9 0x35
#define ODM_RATEVHTSS2MCS0 0x36
#define ODM_RATEVHTSS2MCS1 0x37
#define ODM_RATEVHTSS2MCS2 0x38
#define ODM_RATEVHTSS2MCS3 0x39
#define ODM_RATEVHTSS2MCS4 0x3A
#define ODM_RATEVHTSS2MCS5 0x3B
#define ODM_RATEVHTSS2MCS6 0x3C
#define ODM_RATEVHTSS2MCS7 0x3D
#define ODM_RATEVHTSS2MCS8 0x3E
#define ODM_RATEVHTSS2MCS9 0x3F
#define ODM_RATEVHTSS3MCS0 0x40
#define ODM_RATEVHTSS3MCS1 0x41
#define ODM_RATEVHTSS3MCS2 0x42
#define ODM_RATEVHTSS3MCS3 0x43
#define ODM_RATEVHTSS3MCS4 0x44
#define ODM_RATEVHTSS3MCS5 0x45
#define ODM_RATEVHTSS3MCS6 0x46
#define ODM_RATEVHTSS3MCS7 0x47
#define ODM_RATEVHTSS3MCS8 0x48
#define ODM_RATEVHTSS3MCS9 0x49
#define ODM_RATEVHTSS4MCS0 0x4A
#define ODM_RATEVHTSS4MCS1 0x4B
#define ODM_RATEVHTSS4MCS2 0x4C
#define ODM_RATEVHTSS4MCS3 0x4D
#define ODM_RATEVHTSS4MCS4 0x4E
#define ODM_RATEVHTSS4MCS5 0x4F
#define ODM_RATEVHTSS4MCS6 0x50
#define ODM_RATEVHTSS4MCS7 0x51
#define ODM_RATEVHTSS4MCS8 0x52
#define ODM_RATEVHTSS4MCS9 0x53
//
// Define Different SW team support
//
#define ODM_AP 0x01 //BIT0
#define ODM_ADSL 0x02 //BIT1
#define ODM_CE 0x04 //BIT2
#define ODM_WIN 0x08 //BIT3
#define ODM_IOT 0x10 //BIT4
#define DM_ODM_SUPPORT_TYPE ODM_IOT
// Deifne HW endian support
#define ODM_ENDIAN_BIG 0
#define ODM_ENDIAN_LITTLE 1
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc)))
#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_IOT))
#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv)))
#endif
#if (DM_ODM_SUPPORT_TYPE != ODM_WIN)
#define RT_PCI_INTERFACE 1
#define RT_USB_INTERFACE 2
#define RT_SDIO_INTERFACE 3
#define RT_LXBUS_INTERFACE 4
#endif
typedef enum _HAL_STATUS{
HAL_STATUS_SUCCESS,
HAL_STATUS_FAILURE,
/*RT_STATUS_PENDING,
RT_STATUS_RESOURCE,
RT_STATUS_INVALID_CONTEXT,
RT_STATUS_INVALID_PARAMETER,
RT_STATUS_NOT_SUPPORT,
RT_STATUS_OS_API_FAILED,*/
}HAL_STATUS,*PHAL_STATUS;
#if( (DM_ODM_SUPPORT_TYPE == ODM_AP) ||(DM_ODM_SUPPORT_TYPE == ODM_ADSL) || (DM_ODM_SUPPORT_TYPE == ODM_CE))
#define VISTA_USB_RX_REVISE 0
//
// Declare for ODM spin lock defintion temporarily fro compile pass.
//
typedef enum _RT_SPINLOCK_TYPE{
RT_TX_SPINLOCK = 1,
RT_RX_SPINLOCK = 2,
RT_RM_SPINLOCK = 3,
RT_CAM_SPINLOCK = 4,
RT_SCAN_SPINLOCK = 5,
RT_LOG_SPINLOCK = 7,
RT_BW_SPINLOCK = 8,
RT_CHNLOP_SPINLOCK = 9,
RT_RF_OPERATE_SPINLOCK = 10,
RT_INITIAL_SPINLOCK = 11,
RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30.
#if VISTA_USB_RX_REVISE
RT_USBRX_CONTEXT_SPINLOCK = 13,
RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR
#endif
//Shall we define Ndis 6.2 SpinLock Here ?
RT_PORT_SPINLOCK=16,
RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09.
RT_BTData_SPINLOCK=25,
RT_WAPI_OPTION_SPINLOCK=26,
RT_WAPI_RX_SPINLOCK=27,
// add for 92D CCK control issue
RT_CCK_PAGEA_SPINLOCK = 28,
RT_BUFFER_SPINLOCK = 29,
RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
RT_GEN_TEMP_BUF_SPINLOCK = 31,
RT_AWB_SPINLOCK = 32,
RT_FW_PS_SPINLOCK = 33,
RT_HW_TIMER_SPIN_LOCK = 34,
RT_MPT_WI_SPINLOCK = 35,
RT_P2P_SPIN_LOCK = 36, // Protect P2P context
RT_DBG_SPIN_LOCK = 37,
RT_IQK_SPINLOCK = 38,
RT_PENDED_OID_SPINLOCK = 39,
RT_CHNLLIST_SPINLOCK = 40,
RT_INDIC_SPINLOCK = 41, //protect indication
}RT_SPINLOCK_TYPE;
#endif
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
#define STA_INFO_T RT_WLAN_STA
#define PSTA_INFO_T PRT_WLAN_STA
// typedef unsigned long u4Byte,*pu4Byte;
#define CONFIG_HW_ANTENNA_DIVERSITY
#define CONFIG_SW_ANTENNA_DIVERSITY
#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
#define ADSL_AP_BUILD_WORKAROUND
#define AP_BUILD_WORKAROUND
//
#ifdef CONFIG_ANT_SWITCH
#define CONFIG_HW_ANTENNA_DIVERSITY
#if ( defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_NOT_SUPPORT_ANTDIV
#elif( !defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_2G_SUPPORT_ANTDIV
#elif( defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_5G_SUPPORT_ANTDIV
#elif( !defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY) )
#define CONFIG_2G5G_SUPPORT_ANTDIV
#endif
#endif
#ifdef AP_BUILD_WORKAROUND
#include "../typedef.h"
#else
typedef void VOID,*PVOID;
typedef unsigned char BOOLEAN,*PBOOLEAN;
typedef unsigned char u1Byte,*pu1Byte;
typedef unsigned short u2Byte,*pu2Byte;
typedef unsigned int u4Byte,*pu4Byte;
typedef unsigned long long u8Byte,*pu8Byte;
typedef char s1Byte,*ps1Byte;
typedef short s2Byte,*ps2Byte;
typedef long s4Byte,*ps4Byte;
typedef long long s8Byte,*ps8Byte;
#endif
typedef struct rtl8192cd_priv *prtl8192cd_priv;
typedef struct stat_info STA_INFO_T,*PSTA_INFO_T;
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#define _TRUE 1
#define _FALSE 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_ADSL)
// To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07.
#define ADSL_AP_BUILD_WORKAROUND
#define ADSL_BUILD_WORKAROUND
//
typedef unsigned char BOOLEAN,*PBOOLEAN;
typedef unsigned char u1Byte,*pu1Byte;
typedef unsigned short u2Byte,*pu2Byte;
typedef unsigned int u4Byte,*pu4Byte;
typedef unsigned long long u8Byte,*pu8Byte;
typedef char s1Byte,*ps1Byte;
typedef short s2Byte,*ps2Byte;
typedef long s4Byte,*ps4Byte;
typedef long long s8Byte,*ps8Byte;
typedef struct rtl8192cd_priv *prtl8192cd_priv;
typedef struct stat_info STA_INFO_T,*PSTA_INFO_T;
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#define _TRUE 1
#define _FALSE 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
#include <drv_types.h>
#if 0
typedef u8 u1Byte, *pu1Byte;
typedef u16 u2Byte,*pu2Byte;
typedef u32 u4Byte,*pu4Byte;
typedef u64 u8Byte,*pu8Byte;
typedef s8 s1Byte,*ps1Byte;
typedef s16 s2Byte,*ps2Byte;
typedef s32 s4Byte,*ps4Byte;
typedef s64 s8Byte,*ps8Byte;
#else
#define u1Byte u8
#define pu1Byte u8*
#define u2Byte u16
#define pu2Byte u16*
#define u4Byte u32
#define pu4Byte u32*
#define u8Byte u64
#define pu8Byte u64*
#define s1Byte s8
#define ps1Byte s8*
#define s2Byte s16
#define ps2Byte s16*
#define s4Byte s32
#define ps4Byte s32*
#define s8Byte s64
#define ps8Byte s64*
#endif
#ifdef CONFIG_USB_HCI
#define DEV_BUS_TYPE RT_USB_INTERFACE
#elif defined(CONFIG_PCI_HCI)
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#elif defined(CONFIG_SDIO_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#elif defined(CONFIG_GSPI_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#elif defined(CONFIG_LX_HCI)
#define DEV_BUS_TYPE RT_PCI_INTERFACE
#endif
#if defined(CONFIG_LITTLE_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#elif defined (CONFIG_BIG_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#endif
typedef struct timer_list RT_TIMER, *PRT_TIMER;
typedef void * RT_TIMER_CALL_BACK;
#define STA_INFO_T struct sta_info
#define PSTA_INFO_T struct sta_info *
#ifndef TRUE
#define TRUE _TRUE
#endif
#ifndef FALSE
#define FALSE _FALSE
#endif
#define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value)
#define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value)
#define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value)
//define useless flag to avoid compile warning
#define USE_WORKITEM 0
#define FOR_BRAZIL_PRETEST 0
#define FPGA_TWO_MAC_VERIFICATION 0
#define RTL8881A_SUPPORT 0
#elif (DM_ODM_SUPPORT_TYPE == ODM_IOT)
#include <drv_types.h>
#define RA_MASK_PHYDMLIZE_CE 1
typedef unsigned char u1Byte,*pu1Byte;
typedef unsigned short u2Byte,*pu2Byte;
typedef unsigned int u4Byte,*pu4Byte;
typedef unsigned long long u8Byte,*pu8Byte;
typedef signed char s1Byte,*ps1Byte; /* GCC ROM char = unsigned char */
typedef signed short s2Byte,*ps2Byte;
typedef signed long s4Byte,*ps4Byte;
typedef long long s8Byte,*ps8Byte;
typedef struct sta_info STA_INFO_T,*PSTA_INFO_T;
#if defined(CONFIG_GSPI_HCI)
#define DEV_BUS_TYPE RT_SDIO_INTERFACE
#elif defined(CONFIG_LX_HCI)
#define DEV_BUS_TYPE RT_LXBUS_INTERFACE
#endif
// Array_MP_8195A_TXPWR_LMT[]
typedef enum _ODM_PW_LMT_REGULATION_TYPE{
PW_LMT_REGU_NULL = 0,
PW_LMT_REGU_FCC = 1,
PW_LMT_REGU_ETSI = 2,
PW_LMT_REGU_MKK = 3,
PW_LMT_REGU_WW13 = 4
}ODM_PW_LMT_REGULATION_TYPE;
typedef enum _ODM_PW_LMT_BAND_TYPE{
PW_LMT_BAND_NULL = 0,
PW_LMT_BAND_2_4G = 1,
PW_LMT_BAND_5G = 2
}ODM_PW_LMT_BAND_TYPE;
typedef enum _ODM_PW_LMT_BANDWIDTH_TYPE{
PW_LMT_BW_NULL = 0,
PW_LMT_BW_20M = 1,
PW_LMT_BW_40M = 2,
PW_LMT_BW_80M = 3
}ODM_PW_LMT_BANDWIDTH_TYPE;
typedef enum _ODM_PW_LMT_RATESECTION_TYPE{
PW_LMT_RS_NULL = 0,
PW_LMT_RS_CCK = 1,
PW_LMT_RS_OFDM = 2,
PW_LMT_RS_HT = 3,
PW_LMT_RS_VHT = 4
}ODM_PW_LMT_RATESECTION_TYPE;
typedef enum _ODM_PW_LMT_RFPATH_TYPE{
PW_LMT_PH_NULL = 0,
PW_LMT_PH_1T = 1,
PW_LMT_PH_2T = 2,
PW_LMT_PH_3T = 3,
PW_LMT_PH_4T = 4
}ODM_PW_LMT_RFPATH_TYPE;
#if defined(CONFIG_LITTLE_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
#elif defined (CONFIG_BIG_ENDIAN)
#define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
#endif
#endif
#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0)
#define COND_ELSE 2
#define COND_ENDIF 3
#endif // __ODM_TYPES_H__

59
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rom_odm_interface.h Normal file
View file

@ -0,0 +1,59 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ROM_ODM_INTERFACE_H__
#define __ROM_ODM_INTERFACE_H__
#include "hal_api.h"
//
// =========== Macro Define
//
#define ODM_Read1Byte(pDM_Odm, RegAddr) HAL_READ8(WIFI_REG_BASE, RegAddr)
#define ODM_Read2Byte(pDM_Odm, RegAddr) HAL_READ16(WIFI_REG_BASE, RegAddr)
#define ODM_Read4Byte(pDM_Odm, RegAddr) HAL_READ32(WIFI_REG_BASE, RegAddr)
#define ODM_Write1Byte(pDM_Odm, RegAddr, Data) HAL_WRITE8(WIFI_REG_BASE, RegAddr, Data)
#define ODM_Write2Byte(pDM_Odm, RegAddr, Data) HAL_WRITE16(WIFI_REG_BASE, addr, value)
#define ODM_Write4Byte(pDM_Odm, RegAddr, Data) HAL_WRITE32(WIFI_REG_BASE, addr, value)
#if (RTL8195A_SUPPORT == 1)
#define ODM_GetMACReg(pDM_Odm,RegAddr, BitMask) PHY_QueryBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask))
#define ODM_SetMACReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data))
#define ODM_GetBBReg(pDM_Odm, RegAddr, BitMask) PHY_QueryBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask))
#define ODM_SetBBReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8195A((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data))
#endif
#if (RTL8711B_SUPPORT ==1)
#define ODM_GetMACReg(pDM_Odm,RegAddr, BitMask) PHY_QueryBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask))
#define ODM_SetMACReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data))
#define ODM_GetBBReg(pDM_Odm, RegAddr, BitMask) PHY_QueryBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask))
#define ODM_SetBBReg(pDM_Odm, RegAddr, BitMask, Data) PHY_SetBBReg_8711B((pDM_Odm->Adapter), (RegAddr), (BitMask), (Data))
#endif
//
// =========== Extern Variable
//
//
// =========== EXtern Function Prototype
//
#endif // __ROM_ODM_INTERFACE_H__

289
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/Hal8195ARateAdaptive.h Normal file
View file

@ -0,0 +1,289 @@
/*
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __HALCOM_RATE_ADAPTIVE_RAM_H__
#define __HALCOM_RATE_ADAPTIVE_RAM_H__
#if RATE_ADAPTIVE_SUPPORT
/*--------------------------Define -------------------------------------------*/
#define FIRST_MACID 0 // This is the connection of STA to AP
// Rate index mapping
#define RATE_CCK_1M ODM_RATE1M
#define RATE_CCK_2M ODM_RATE2M
#define RATE_CCK_5M ODM_RATE5_5M
#define RATE_CCK_11M ODM_RATE11M
#define RATE_OFDM_6M ODM_RATE6M
#define RATE_OFDM_9M ODM_RATE9M
#define RATE_OFDM_12M ODM_RATE12M
#define RATE_OFDM_18M ODM_RATE18M
#define RATE_OFDM_24M ODM_RATE24M
#define RATE_OFDM_36M ODM_RATE36M
#define RATE_OFDM_48M ODM_RATE48M
#define RATE_OFDM_54M ODM_RATE54M
#define RATE_HT_MCS0 ODM_RATEMCS0
#define RATE_HT_MCS1 ODM_RATEMCS1
#define RATE_HT_MCS2 ODM_RATEMCS2
#define RATE_HT_MCS3 ODM_RATEMCS3
#define RATE_HT_MCS4 ODM_RATEMCS4
#define RATE_HT_MCS5 ODM_RATEMCS5
#define RATE_HT_MCS6 ODM_RATEMCS6
#define RATE_HT_MCS7 ODM_RATEMCS7
#define RATE_HT_MCS8 ODM_RATEMCS8
#define RATE_HT_MCS9 ODM_RATEMCS9
#define RATE_HT_MCS10 ODM_RATEMCS10
#define RATE_HT_MCS11 ODM_RATEMCS11
#define RATE_HT_MCS12 ODM_RATEMCS12
#define RATE_HT_MCS13 ODM_RATEMCS13
#define RATE_HT_MCS14 ODM_RATEMCS14
#define RATE_HT_MCS15 ODM_RATEMCS15
#define MACID_NUM 128
// TX report format
#define TXRPT_SIZE 16
//offset 0
#define TXRPT_DATARATE (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6)
#define TXRPT_SGI BIT7
//offset 1
#define TXRPT_PWRSTS (BIT0|BIT1|BIT2)
#define TXRPT_TRYNESSCNT (BIT3|BIT4|BIT5|BIT6)
#define TXRPT_TRYRATE BIT7
//offset 2
#define TXRPT_TRYRESULT BIT6
#define TXRPT_TRYFINISH BIT7
//offset 3
#define TXRPT_PAUSERPT BIT6
#define TXRPT_RESETRPT BIT7
//offset 4
//offset 5
#define TXRPT_BW (BIT0|BIT1)
#define TXRPT_PKTDROP BIT2
#define RATE_UP 1
#define RATE_DOWN 2
#define RSSI_TH1 45
#define RSSI_TH2 25
#define PERENTRY 27
#define RETRYSIZE 5
#define RATESIZE 20
#define RAMASK_SIZE 8
#define SS_PT_TH_High 66
#define SS_PT_TH_low 57
#define SS_PT_off 48
#define SS_RA_INIT_RATE_RSSI 30
#define STEP_DROP 1
#define CONFIG_SGI 0
#define TRY_WAITING 10
// RA mask
#define Mask_length_REG 8
#define Rate_id_NUM 9 // 6 rate id from reg
#define ARFB_table_NUM 7
#define TRY_NESS_CNT_IDX_SIZE 16
/*------------------------------Define Enum-----------------------------------*/
typedef enum _RTL8195_RATEID_IDX_ {
MODE_BGN_40M_2SS = 0,
MODE_BGN_40M_1SS = 1,
MODE_BGN_20M_2SS_BN = 2,
MODE_BGN_20M_1SS_BN = 3,
MODE_GN_N2SS = 4,
MODE_GN_N1SS = 5,
MODE_BG = 6,
MODE_G = 7,
MODE_B = 8
} RTL8195_RATEID_IDX, *PRTL8195_RATEID_IDX;
typedef enum _VHT_HT_SWITCH_ {
TYPE_HT = 0,
TYPE_VHT = 1,
TYPE_MIX1 = 2,
TYPE_MIX2 = 3
} VHT_SEL_SWITCH, *PVHT_SEL_SWITCH;
/*--------------------------Define MACRO--------------------------------------*/
#define TRYING_DISABLE 0
#define TRYING_ENABLE 1
//RA MASK: INIT_RATE_MASK
//if VHT_HT_SWITCH = 1, it means VHT.
//Bit[51:12] : VHT 1SS ~ VHT 4SS
//if VHT_HT_SWITCH = 0, it means HT.
//Bit[43:12] : HT 1SS ~ HT4SS
//offset6
//#define VHT_HT_SWITCH BIT4
// H2C CMD
//offset0
#define H2CID13_MACID 0x7F
//offset1
#define H2CID13_RATEID 0x1F
#define H2CID13_SGI BIT7
//offset2
#define H2CID13_BW (BIT0|BIT1)
#define H2CID13_enldpc BIT2
#define H2CID13_NOUPDATE BIT3
#define H2CID13_VHT_EN (BIT5|BIT4)
#define H2CID13_DISPT BIT6
#define H2CID13_DISRA BIT7
//H2C AP_Req_Tx_Rpt
#define H2CID43_RTY_OK_TOTAL BIT0
#define H2CID43_RTY_CNT_MACID BIT1
//RAInfo
#define MASK_RA_ULDL_STATE BIT0
#define MASK_RA_STBC_STATE BIT1
#define MASK_RA_LDPC_CAP_STATE BIT2
#define MASK_RA_SHORTCUT_STATE BIT3
#define MASK_RA_SHORTCUT_FLAG BIT4
#define MASK_RA_INIT_RATE_RSSI_STATE BIT5
#define MASK_RA_BF_STATE BIT6
#define MASK_RA_DELAY_RATE BIT7
#define RA_ULDL_STATE_SHT 0
#define RA_STBC_STATE_SHT 1
#define RA_LDPC_CAP_STATE_SHT 2
#define RA_SHORTCUT_STATE_SHT 3
#define RA_SHORTCUT_FLAG_SHT 4
#define RA_INIT_RATE_RSSI_SHT 5
#define RA_BF_STATE_SHT 6
#define RA_DELAY_RATE_SHT 7
/*------------------------Export global variable------------------------------*/
//2 Rate Adaptive
//HW Statistic
//extern MEMTYPE_XDATA u16 TOTAL[MACID_NUM];
//extern MEMTYPE_XDATA u1Byte DROP[MACID_NUM];
//extern MEMTYPE_XDATA u16 RTY[MACID_NUM][5];
//extern MEMTYPE_XDATA STAINFO_RA stainfo_ra[MACID_NUM];
//extern MEMTYPE_XDATA u16 Nsc[MACID_NUM];
//extern MEMTYPE_XDATA u1Byte RSSI[MACID_NUM]; // add by Gary
//extern MEMTYPE_XDATA u1Byte BUPDATE[MACID_NUM];
/*------------------------------Function declaration--------------------------*/
VOID
InitBBNHM(
void
);
VOID
BBNHM(
void
);
VOID
ODM_InitRAInfo(
IN PDM_ODM_T pDM_Odm
);
VOID
H2CHDL_Set_MACID_Config(
IN PDM_ODM_T pDM_Odm,
IN u1Byte *pbuf
);
VOID
H2CHDL_SetRssiSingle(
u1Byte *pbuf
);
VOID
H2CHDL_APReqTxrpt(
u1Byte *pbuf
);
VOID
H2CHDL_InitRateCollect(
u1Byte *pbuf
);
VOID
TryDone(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo
);
VOID
RateDownTrying(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo
);
VOID
RateDecisionRAM8195A(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo
);
VOID
GetRATRfromREG(
IN u16 reg_addr,
IN u1Byte macid
);
VOID
PHY_DM_RA_SetRSSI_8195A(
IN PDM_ODM_T pDM_Odm,
IN u1Byte MacID,
IN u1Byte Rssi
);
#if 0
extern void
Rate_trying_decision(
IN u1Byte macid,
IN u1Byte rate,
IN u1Byte datarc,
IN u1Byte aggnum
);
#endif
//debug
VOID
ArfrRefresh(
IN PDM_ODM_T pDM_Odm,
IN PODM_RA_INFO_T pRaInfo
);
#endif //#if CONFIG_RATE_ADAPTIVE
#endif //#ifndef __HALCOM_RATE_ADAPTIVE_RAM_H__

1371
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/Hal8195AReg.h Normal file
View file

File diff suppressed because it is too large Load diff

127
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/HalPhyRf_8195A.h Normal file
View file

@ -0,0 +1,127 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HAL_PHY_RF_8195A_H__
#define __HAL_PHY_RF_8195A_H__
/*--------------------------Define Parameters-------------------------------*/
#define IQK_DELAY_TIME_8195A 10 //ms
#define IQK_DEFERRED_TIME_8195A 4
#define index_mapping_NUM_8195A 15
#define AVG_THERMAL_NUM_8195A 4
#define RF_T_METER_8195A 0x42 //
void ConfigureTxpowerTrack_8195A(
PTXPWRTRACK_CFG pConfig
);
void DoIQK_8195A(
PDM_ODM_T pDM_Odm,
u1Byte DeltaThermalIndex,
u1Byte ThermalValue,
u1Byte Threshold
);
VOID
ODM_TxPwrTrackSetPwr_8195A(
PDM_ODM_T pDM_Odm,
PWRTRACK_METHOD Method,
u1Byte RFPath,
u1Byte ChannelMappedIndex
);
VOID
ODM_TxXtalTrackSetXtal_8195A(
PDM_ODM_T pDM_Odm
);
//1 7. IQK
void
PHY_IQCalibrate_8195A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER Adapter,
#endif
IN BOOLEAN bReCovery,
IN BOOLEAN bRestore);
//
// LC calibrate
//
void
PHY_LCCalibrate_8195A(
IN PDM_ODM_T pDM_Odm
);
VOID
_PHY_SaveADDARegisters_8195A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN pu4Byte ADDABackup,
IN u4Byte RegisterNum
);
VOID
_PHY_PathADDAOn_8195A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte ADDAReg,
IN BOOLEAN isPathAOn,
IN BOOLEAN is2T
);
VOID
_PHY_MACSettingCalibration_8195A(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm,
#else
IN PADAPTER pAdapter,
#endif
IN pu4Byte MACReg,
IN pu4Byte MACBackup
);
VOID
_PHY_PathAStandBy(
#if (DM_ODM_SUPPORT_TYPE & ODM_AP)
IN PDM_ODM_T pDM_Odm
#else
IN PADAPTER pAdapter
#endif
);
#endif // #ifndef __HAL_PHY_RF_8188E_H__

128
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/ROM_RTL8195A_PHYDM.h Normal file
View file

@ -0,0 +1,128 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ROM_RTL8195A_PHYDM_H__
#define __ROM_RTL8195A_PHYDM_H__
typedef struct _FALSE_ALARM_STATISTICS{
u4Byte Cnt_Parity_Fail;
u4Byte Cnt_Rate_Illegal;
u4Byte Cnt_Crc8_fail;
u4Byte Cnt_Mcs_fail;
u4Byte Cnt_Ofdm_fail;
u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A
u4Byte Cnt_Cck_fail;
u4Byte Cnt_all;
u4Byte Cnt_Fast_Fsync;
u4Byte Cnt_SB_Search_fail;
u4Byte Cnt_OFDM_CCA;
u4Byte Cnt_CCK_CCA;
u4Byte Cnt_CCA_all;
u4Byte Cnt_BW_USC; //Gary
u4Byte Cnt_BW_LSC; //Gary
}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;
typedef struct _CFO_TRACKING_
{
BOOLEAN bATCStatus;
BOOLEAN largeCFOHit;
BOOLEAN bAdjust;
u1Byte CrystalCap;
u1Byte DefXCap;
int CFO_tail[2];
int CFO_ave_pre;
u4Byte packetCount;
u4Byte packetCount_pre;
BOOLEAN bForceXtalCap;
BOOLEAN bReset;
u1Byte CFO_TH_XTAL_HIGH;
u1Byte CFO_TH_XTAL_LOW;
u1Byte CFO_TH_ATC;
}CFO_TRACKING, *PCFO_TRACKING;
typedef struct _ROM_INFO{
u1Byte EEPROMVersion;
u1Byte CrystalCap;
u8Byte DebugComponents;
u4Byte DebugLevel;
}ROM_INFO, *PROM_INFO;
extern FALSE_ALARM_STATISTICS FalseAlmCnt;
extern CFO_TRACKING DM_CfoTrack;
extern ROM_INFO ROMInfo;
u1Byte
ROM_odm_QueryRxPwrPercentage(
IN s1Byte AntPower
);
u1Byte
ROM_odm_EVMdbToPercentage(
IN s1Byte Value
);
s4Byte
ROM_odm_SignalScaleMapping_8195A(
IN u1Byte SupportInterface,
IN s4Byte CurrSig
);
VOID
ROM_odm_FalseAlarmCounterStatistics(
IN PVOID pDM_VOID
);
VOID
ROM_odm_SetEDCCAThreshold(
IN PVOID pDM_VOID,
IN s1Byte H2L,
IN s1Byte L2H
);
VOID
ROM_odm_SetTRxMux(
IN PVOID pDM_VOID,
IN ODM_Trx_MUX_Type txMode,
IN ODM_Trx_MUX_Type rxMode
);
VOID
ROM_odm_SetCrystalCap(
IN PVOID pDM_VOID,
IN u1Byte CrystalCap
);
u1Byte
ROM_odm_GetDefaultCrytaltalCap(
IN PVOID pDM_VOID
);
VOID
ROM_ODM_CfoTrackingReset(
IN PVOID pDM_VOID
);
VOID
ROM_odm_CfoTrackingFlow(
IN PVOID pDM_VOID
);
#endif

59
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_bb.h Normal file
View file

@ -0,0 +1,59 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.23*/
#if (RTL8195A_SUPPORT == 1)
#ifndef __INC_MP_BB_HW_IMG_8195A_H
#define __INC_MP_BB_HW_IMG_8195A_H
/******************************************************************************
* AGC_TAB.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8195A_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8195A_AGC_TAB(void);
/******************************************************************************
* PHY_REG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8195A_PHY_REG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8195A_PHY_REG(void);
/******************************************************************************
* PHY_REG_PG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8195A_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8195A_PHY_REG_PG(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

39
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_mac.h Normal file
View file

@ -0,0 +1,39 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.23*/
#if (RTL8195A_SUPPORT == 1)
#ifndef __INC_MP_MAC_HW_IMG_8195A_H
#define __INC_MP_MAC_HW_IMG_8195A_H
/******************************************************************************
* MAC_REG.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8195A_MAC_REG(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8195A_MAC_REG(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

104
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/halhwimg8195a_rf.h Normal file
View file

@ -0,0 +1,104 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
/*Image2HeaderVersion: 2.23*/
#if (RTL8195A_SUPPORT == 1)
#ifndef __INC_MP_RF_HW_IMG_8195A_H
#define __INC_MP_RF_HW_IMG_8195A_H
/******************************************************************************
* RadioA.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8195A_RadioA(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8195A_RadioA(void);
/******************************************************************************
* RADIO_DIFF.TXT
******************************************************************************/
extern u4Byte Array_MP_8195A_RADIO_DIFF_LB[50];
extern u4Byte Array_MP_8195A_RADIO_DIFF_MB[50];
extern u4Byte Array_MP_8195A_RADIO_DIFF_HB[50];
void
ODM_ReadAndConfig_MP_8195A_RADIO_DIFF(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Array[],
IN u4Byte ArrayLen
);
u4Byte ODM_GetVersion_MP_8195A_RADIO_DIFF(void);
/******************************************************************************
* TxPowerTrack_QFN48.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8195A_TxPowerTrack_QFN48(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8195A_TxPowerTrack_QFN48(void);
/******************************************************************************
* TxPowerTrack_QFN56.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8195A_TxPowerTrack_QFN56(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8195A_TxPowerTrack_QFN56(void);
/******************************************************************************
* TxPowerTrack_TFBGA96.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8195A_TxPowerTrack_TFBGA96(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8195A_TxPowerTrack_TFBGA96(void);
/******************************************************************************
* TXPWR_LMT.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8195A_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8195A_TXPWR_LMT(void);
/******************************************************************************
* TxXtalTrack.TXT
******************************************************************************/
void
ODM_ReadAndConfig_MP_8195A_TxXtalTrack(/* TC: Test Chip, MP: MP Chip*/
IN PDM_ODM_T pDM_Odm
);
u4Byte ODM_GetVersion_MP_8195A_TxXtalTrack(void);
#endif
#endif /* end of HWIMG_SUPPORT*/

69
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/phydm_RTL8195A.h Normal file
View file

@ -0,0 +1,69 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ODM_RTL8723B_H__
#define __ODM_RTL8723B_H__
#define DM_DIG_MIN_NIC_8723 0x1C
#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
VOID
ODM_AntennaDiversityInit_8723B( IN PDM_ODM_T pDM_Odm);
VOID
ODM_AntselStatistics_8723B(
IN PDM_ODM_T pDM_Odm,
IN u1Byte antsel_tr_mux,
IN u4Byte MacId,
IN u4Byte RxPWDBAll);
VOID
ODM_AntennaDiversity_8723B( IN PDM_ODM_T pDM_Odm);
VOID
ODM_UpdateRxIdleAnt_8723B(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant);
VOID
ODM_SetTxAntByTxInfo_8723B(
IN PDM_ODM_T pDM_Odm,
IN pu1Byte pDesc,
IN u1Byte macId
);
#endif
VOID
odm_DIG_8723(IN PDM_ODM_T pDM_Odm);
s1Byte
odm_CCKRSSI_8723B(
IN u1Byte LNA_idx,
IN u1Byte VGA_idx
);
s1Byte
odm_RSSIOFDM_8723B(
IN s1Byte rx_pwr_new
);
#endif

89
USDK/component/common/drivers/wlan/realtek/src/hal/OUTSRC/rtl8195a/phydm_RegConfig8195A.h Normal file
View file

@ -0,0 +1,89 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_ODM_REGCONFIG_H_8195A
#define __INC_ODM_REGCONFIG_H_8195A
#if (RTL8195A_SUPPORT == 1)
void
odm_ConfigRFReg_8195A(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data,
IN ODM_RF_RADIO_PATH_E RF_PATH,
IN u4Byte RegAddr
);
void
odm_ConfigRF_RadioA_8195A(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Data
);
void
odm_ConfigMAC_8195A(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u1Byte Data
);
void
odm_ConfigBB_AGC_8195A(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_REG_PG_8195A(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Band,
IN u4Byte RfPath,
IN u4Byte TxNum,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_PHY_8195A(
IN PDM_ODM_T pDM_Odm,
IN u4Byte Addr,
IN u4Byte Bitmask,
IN u4Byte Data
);
void
odm_ConfigBB_TXPWR_LMT_8195A(
IN PDM_ODM_T pDM_Odm,
IN u1Byte Regulation,
IN u1Byte Band,
IN u1Byte Bandwidth,
IN u1Byte RateSection,
IN u1Byte RfPath,
IN u1Byte Channel,
IN u1Byte PowerLimit
);
#endif
#endif // end of SUPPORT

498
USDK/component/common/drivers/wlan/realtek/src/hal/hal_data.h Normal file
View file

@ -0,0 +1,498 @@
/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#ifndef __HAL_DATA_H__
#define __HAL_DATA_H__
#include "hal_com.h"
#ifdef CONFIG_RTL8188F
#include "OUTSRC/rtl8188f/phydm_precomp.h"
#else
#include "OUTSRC/phydm_precomp.h"
#endif
#ifdef CONFIG_RTL8723A
#include "rtl8723a/rtl8723a_hal.h"
#endif
#ifdef CONFIG_RTL8188E
#include "rtl8188e/rtl8188e_hal.h"
#endif
#ifdef CONFIG_RTL8195A
#include "rtl8195a_hal.h"
#endif
#if (CONFIG_RTL8711B ==1)
#include "rtl8711b_hal.h"
#endif
#ifdef CONFIG_RTL8188F
#include "rtl8188f/rtl8188f_hal.h"
#endif
//
// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
//
typedef enum _RT_MULTI_FUNC{
RT_MULTI_FUNC_NONE = 0x00,
RT_MULTI_FUNC_WIFI = 0x01,
RT_MULTI_FUNC_BT = 0x02,
RT_MULTI_FUNC_GPS = 0x04,
}RT_MULTI_FUNC,*PRT_MULTI_FUNC;
//
// <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08.
//
typedef enum _RT_POLARITY_CTL {
RT_POLARITY_LOW_ACT = 0,
RT_POLARITY_HIGH_ACT = 1,
} RT_POLARITY_CTL, *PRT_POLARITY_CTL;
// For RTL8723 regulator mode. by tynli. 2011.01.14.
typedef enum _RT_REGULATOR_MODE {
RT_SWITCHING_REGULATOR = 0,
RT_LDO_REGULATOR = 1,
} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE;
#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number
#define CHANNEL_MAX_NUMBER_2G 14
#define CHANNEL_MAX_NUMBER_5G 54 // Please refer to "phy_GetChnlGroup8812A" and "Hal_ReadTxPowerInfo8812A"
#define CHANNEL_MAX_NUMBER_5G_80M 7
// Tx Power Limit Table Size
#define MAX_REGULATION_NUM 3 // FCC, ETSI, MKK
#define MAX_2_4G_BANDWITH_NUM 2 // 20M, 40M
#if defined(NOT_SUPPORT_RF_MULTIPATH) && defined(NOT_SUPPORT_VHT)
#define MAX_RATE_SECTION_NUM 3 // CCk, OFDM, HT
#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 3 // CCK:1,OFDM:1, HT:1(MCS0_MCS7)
#else
#define MAX_RATE_SECTION_NUM 10
#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 // CCK:1,OFDM:1, HT:4, VHT:4
#endif
#define MAX_5G_BANDWITH_NUM 4
#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 // OFDM:1, HT:4, VHT:4
#define HCI_SUS_ENTER 0
#define HCI_SUS_LEAVING 1
#define HCI_SUS_LEAVE 2
#define HCI_SUS_ENTERING 3
#define HCI_SUS_ERR 4
struct dm_priv
{
u8 DM_Type;
u8 DMFlag;
u8 InitDMFlag;
u32 InitODMFlag;
//* Upper and Lower Signal threshold for Rate Adaptive*/
int UndecoratedSmoothedPWDB;
int UndecoratedSmoothedCCK;
int EntryMinUndecoratedSmoothedPWDB;
int EntryMaxUndecoratedSmoothedPWDB;
int MinUndecoratedPWDBForDM;
int LastMinUndecoratedPWDBForDM;
//for High Power
u8 bDynamicTxPowerEnable;
u8 LastDTPLvl;
u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06
//for tx power tracking
u8 bTXPowerTracking;
u8 TXPowercount;
u8 bTXPowerTrackingInit;
u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default
u8 PowerIndex_backup[6];
s32 OFDM_Pkt_Cnt;
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
u8 INIDATA_RATE[32];
};
#ifdef CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
#define MCUCMDQUEUEDEPTH 15
#define MCUCMDLENGTH 2
#define MACIDNUM 128
typedef struct _cmd_queue_{
u32 FwCmdContent[MCUCMDLENGTH];
}CMD_QUEUE;
#endif
#ifdef CONFIG_RF_GAIN_OFFSET
#ifdef CONFIG_RTL8188F
struct kfree_data_t {
u8 flag;
s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX];
s8 thermal;
};
#define KFREE_FLAG_ON BIT0
#define KFREE_FLAG_THERMAL_K_ON BIT1
#endif
#endif
typedef struct hal_com_data
{
HAL_VERSION VersionID;
// RT_MULTI_FUNC MultiFunc; // For multi-function consideration.
// RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control.
RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO
u16 CustomerID;
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B) ||defined (CONFIG_RTL8188F)
u16 ForcedDataRate;// Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M.
#endif
u16 FirmwareVersion;
u16 FirmwareVersionRev;
u16 FirmwareSubVersion;
u16 FirmwareSignature;
// u8 PGMaxGroup;
//current WIFI_PHY values
u32 ReceiveConfig;
// WIRELESS_MODE CurrentWirelessMode;
CHANNEL_WIDTH CurrentChannelBW;
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)||defined (CONFIG_RTL8188F)
BAND_TYPE CurrentBandType; //0:2.4G, 1:5G
#endif
u8 CurrentChannel;
u8 nCur40MhzPrimeSC;// Control channel sub-carrier
u8 CurrentCenterFrequencyIndex1;
#if !defined(NOT_SUPPORT_80M)
u8 nCur80MhzPrimeSC; //used for primary 40MHz of 80MHz mode
#endif
u16 BasicRateSet;
u8 hci_sus_state;
//rf_ctrl
u8 rf_chip;
u8 rf_type;
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)||defined (CONFIG_RTL8188F)
u8 PackageType;
u8 ChipID;
#endif
u8 NumTotalRFPath;
u8 BoardType;
//
// EEPROM setting.
//
// u16 EEPROMVID;
// u16 EEPROMPID;
// u16 EEPROMSVID;
// u16 EEPROMSDID;
u8 EEPROMCustomerID;
// u8 EEPROMSubCustomerID;
u8 EEPROMVersion;
u8 EEPROMRegulatory;
#ifdef CONFIG_RF_GAIN_OFFSET
#ifdef CONFIG_RTL8188F
struct kfree_data_t kfree_data;
#endif
#endif
// u8 bTXPowerDataReadFromEEPORM;
u8 EEPROMThermalMeter;
// u8 bAPKThermalMeterIgnore;
// BOOLEAN EepromOrEfuse;
//u8 EfuseMap[2][HWSET_MAX_SIZE_512]; //92C:256bytes, 88E:512bytes, we use union set (512bytes)
//u8 EfuseUsedPercentage;
#ifdef HAL_EFUSE_MEMORY
EFUSE_HAL EfuseHal;
#endif
//u8 bIQKInitialized;
u8 Regulation2_4G;
#if !defined(NOT_SUPPORT_5G)
u8 Regulation5G;
#endif
#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)||defined (CONFIG_RTL8188F)
s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND]
[TX_PWR_BY_RATE_NUM_RF]
[TX_PWR_BY_RATE_NUM_RF]
[TX_PWR_BY_RATE_NUM_RATE];
#endif
//---------------------------------------------------------------------------------//
#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)||defined (CONFIG_RTL8188F)
u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
//If only one tx, only BW20 and OFDM are used.
s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
#if !defined(NOT_SUPPORT_RF_MULTIPATH)
s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
#endif
//2 Power Limit Table
// Power Limit Table for 2.4G
s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM]
[MAX_2_4G_BANDWITH_NUM]
[MAX_RATE_SECTION_NUM]
[CHANNEL_MAX_NUMBER_2G]
[MAX_RF_PATH];
#if !defined(NOT_SUPPORT_5G)
// Power Limit Table for 5G
s8 TxPwrLimit_5G[MAX_REGULATION_NUM]
[MAX_5G_BANDWITH_NUM]
[MAX_RATE_SECTION_NUM]
[CHANNEL_MAX_NUMBER_5G]
[MAX_RF_PATH];
#endif
// Store the original power by rate value of the base of each rate section of rf path A & B
u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF]
[TX_PWR_BY_RATE_NUM_RF]
[MAX_BASE_NUM_IN_PHY_REG_PG_2_4G];
#if !defined(NOT_SUPPORT_5G)
u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF]
[TX_PWR_BY_RATE_NUM_RF]
[MAX_BASE_NUM_IN_PHY_REG_PG_5G];
#endif
#else
u8 TxPwrLevelCck[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrHt20Diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
#endif
// For power group
// u8 PwrGroupHT20[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
// u8 PwrGroupHT40[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
// u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff
// The current Tx Power Level
u8 CurrentCckTxPwrIdx;
u8 CurrentOfdm24GTxPwrIdx;
u8 CurrentBW2024GTxPwrIdx;
u8 CurrentBW4024GTxPwrIdx;
u8 CrystalCap;
//u32 AntennaTxPath; // Antenna path Tx
//u32 AntennaRxPath; // Antenna path Rx
//u8 BluetoothCoexist;
// u8 ExternalPA;
#if defined(CONFIG_RTL8188F)
/* PHY DM & DM Section */
u8 INIDATA_RATE[32/*MACID_NUM_SW_LIMIT*/];
/* Upper and Lower Signal threshold for Rate Adaptive*/
int EntryMinUndecoratedSmoothedPWDB;
int EntryMaxUndecoratedSmoothedPWDB;
int MinUndecoratedPWDBForDM;
#endif
//u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16.
//u32 LedControlNum;
//u32 LedControlMode;
//u8 b1x1RecvCombine; // for 1T1R receive combining
//u8 bCurrentTurboEDCA;
#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)||defined (CONFIG_RTL8188F)
BOOLEAN bSwChnl;
BOOLEAN bSetChnlBW;
BOOLEAN bChnlBWInitialized;
#endif
// BOOLEAN bNeedIQK;
u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo.
#if defined(NOT_SUPPORT_RF_MULTIPATH)
BB_REGISTER_DEFINITION_T PHYRegDef[1]; //Radio A
u32 RfRegChnlVal[1];
#else
BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
u32 RfRegChnlVal[2];
#endif
//RDG enable
// BOOLEAN bRDGEnable;
#if (defined(CONFIG_RTL8711B) || defined(CONFIG_RTL8188F))
//for host message to fw
u8 LastHMEBoxNum;
#endif
u8 fw_ractrl;
// u8 RegTxPause;
// Beacon function related global variable.
// u32 RegBcnCtrlVal;
u8 RegFwHwTxQCtrl;
u8 RegReg542;
// u8 RegCR_1;
u16 RegRRSR;
struct dm_priv dmpriv;
DM_ODM_T odmpriv;
//_lock odm_stainfo_lock;
#ifdef DBG_CONFIG_ERROR_DETECT
struct sreset_priv srestpriv;
#endif
#ifdef CONFIG_BT_COEXIST
struct btcoexist_priv bt_coexist;
#endif
//#ifdef CONFIG_ANTENNA_DIVERSITY
u8 CurAntenna;
u8 AntDivCfg;
u8 TRxAntDivType;
//#endif
// u8 bDumpRxPkt;//for debug
// u8 bDumpTxPkt;//for debug
// u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.
// 2010/08/09 MH Add CU power down mode.
// BOOLEAN pwrdown;
// Add for dual MAC 0--Mac0 1--Mac1
// u32 interfaceIndex;
u8 OutEpQueueSel;
u8 OutEpNumber;
// 2010/12/10 MH Add for USB aggreation mode dynamic shceme.
// BOOLEAN UsbRxHighSpeedMode;
// 2010/11/22 MH Add for slim combo debug mode selective.
// This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock.
//BOOLEAN SlimComboDbg;
u16 EfuseUsedBytes;
#ifdef CONFIG_P2P
struct P2P_PS_Offload_t p2p_ps_offload;
#endif
u8 AMPDUDensity;
// Auto FSM to Turn On, include clock, isolation, power control for MAC only
u8 bMacPwrCtrlOn;
#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
//
// For SDIO Interface HAL related
//
//
// SDIO ISR Related
//
// u32 IntrMask[1];
// u32 IntrMaskToSet[1];
// LOG_INTERRUPT InterruptLog;
// u32 sdio_himr;
// u32 sdio_hisr;
//
// SDIO Tx FIFO related.
//
// HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg
// u8 SdioTxFIFOFreePage[TX_FREE_PG_QUEUE];
// _lock SdioTxFIFOFreePageLock;
// _thread_hdl_ SdioXmitThread;
// _sema SdioXmitSema;
// _sema SdioXmitTerminateSema;
//
// SDIO Rx FIFO related.
//
// u8 SdioRxFIFOCnt;
// u16 SdioRxFIFOSize;
#endif //CONFIG_SDIO_HCI
#ifdef CONFIG_USB_HCI
u32 UsbBulkOutSize;
// Interrupt relatd register information.
u32 IntArray[3];//HISR0,HISR1,HSISR
u32 IntrMask[3];
//u8 C2hArray[16];
#ifdef CONFIG_USB_TX_AGGREGATION
u8 UsbTxAggMode;
u8 UsbTxAggDescNum;
#endif
#ifdef CONFIG_USB_RX_AGGREGATION
u16 HwRxPageSize; // Hardware setting
u32 MaxUsbRxAggBlock;
USB_RX_AGG_MODE UsbRxAggMode;
u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed
u8 UsbRxAggBlockTimeout;
u8 UsbRxAggPageCount; // 8192C DMA page count
u8 UsbRxAggPageTimeout;
#endif
#endif //CONFIG_USB_HCI
#if defined (CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
// u32 TransmitConfig;
u32 IntArray[3];
u32 IntrMask[3];
// u8 bDefaultAntenna;
// u8 bIQKInitialized;
// u8 bInterruptMigration;
// u8 bDisableTxInt;
#ifdef CONFIG_SUPPORT_HW_WPS_PBC
u8 bGpioHwWpsPbc;
#endif
u16 RxExpectTag;
#ifdef CONFIG_DEBUG_DYNAMIC
struct hal_debug debug_info;
#endif
#endif //CONFIG_PCI_HCI || CONFIG_LX_HCI
#ifdef CONFIG_TX_EARLY_MODE
u8 bEarlyModeEnable;
#endif
#ifdef CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
struct task_struct littlewifipriv;
//CMD_QUEUE FwCmdQueue[MCUCMDQUEUEDEPTH];
//fw section
u32 WifiMcuCmdBitMap;
u8 bConnected[MACIDNUM/8];
BOOLEAN PMUTaskRAEn;
u8 BcnIgnoreEdccaEn;
#ifdef CONFIG_POWER_SAVING
struct task_struct enter32kpriv;
#ifdef TDMA_POWER_SAVING
struct task_struct TDMApriv;
#endif //#ifdef TDMA_POWER_SAVING
PS_PARM PSParmpriv;
u8 ScanEn;
#endif //#ifdef CONFIG_POWER_SAVING
#endif
} HAL_DATA_COMMON, *PHAL_DATA_COMMON;
typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE;
#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData))
#endif //__HAL_DATA_H__

1125
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8192CPhyReg.h Normal file
View file

File diff suppressed because it is too large Load diff

186
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APhyCfg.h Normal file
View file

@ -0,0 +1,186 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8195APHYCFG_H__
#define __INC_HAL8195APHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
#define LOOP_LIMIT 5
#define MAX_STALL_TIME 50 //us
#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
#define MAX_TXPWR_IDX_NMODE_92S 63
#define Reset_Cnt_Limit 3
#if defined (CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
#define MAX_AGGR_NUM 0x0B
#else
#define MAX_AGGR_NUM 0x07
#endif // CONFIG_PCI_HCI
/*--------------------------Define Parameters End-------------------------------*/
/*------------------------------Define structure----------------------------*/
/* BB/RF related */
typedef struct _R_ANTENNA_SELECT_OFDM{
u32 r_tx_antenna:4;
u32 r_ant_l:4;
u32 r_ant_non_ht:4;
u32 r_ant_ht1:4;
u32 r_ant_ht2:4;
u32 r_ant_ht_s1:4;
u32 r_ant_non_ht_s1:4;
u32 OFDM_TXSC:2;
u32 Reserved:2;
}R_ANTENNA_SELECT_OFDM;
typedef struct _R_ANTENNA_SELECT_CCK{
u8 r_cckrx_enable_2:2;
u8 r_cckrx_enable:2;
u8 r_ccktx_enable:4;
}R_ANTENNA_SELECT_CCK;
/*------------------------------Define structure End----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
u32
PHY_QueryBBReg_8195A(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetBBReg_8195A(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
u32
PHY_QueryRFReg_8195A(
IN PADAPTER Adapter,
IN u32 eRFPath,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetRFReg_8195A(
IN PADAPTER Adapter,
IN u32 eRFPath,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
u32 PHY_QueryBBReg_8195A_Safe(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
);
VOID PHY_SetBBReg_8195A_Safe(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) PHY_QueryBBReg_8195A_Safe((Adapter), (RegAddr), (BitMask))
#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) PHY_SetBBReg_8195A_Safe((Adapter), (RegAddr), (BitMask), (Data))
#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) PHY_QueryRFReg_8195A((Adapter), (eRFPath), (RegAddr), (BitMask))
#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) PHY_SetRFReg_8195A((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
#define PHY_SetMacReg PHY_SetBBReg
#define PHY_QueryMacReg PHY_QueryBBReg
/* MAC/BB/RF HAL config */
int PHY_BBConfig8195A(PADAPTER Adapter );
int PHY_RFConfig8195A(PADAPTER Adapter );
s32 PHY_MACConfig8195A(PADAPTER padapter);
#ifdef CONFIG_SUDO_PHY_SETTING
int PHY_SudoPhyConfig8195A(PADAPTER Adapter);
#endif
int
PHY_ConfigRFWithParaFile_8195A(
IN PADAPTER Adapter,
IN u8* pFileName,
RF_PATH eRFPath
);
int
PHY_ConfigRFWithHeaderFile_8723B(
IN PADAPTER Adapter,
RF_PATH eRFPath
);
u8
PHY_GetTxPowerIndex_8195A(
IN PADAPTER pAdapter,
IN u8 RFPath,
IN u8 Rate,
IN CHANNEL_WIDTH BandWidth,
IN u8 Channel
);
VOID
PHY_SetTxPowerLevel8195A(
IN PADAPTER Adapter,
IN u8 channel
);
VOID
PHY_SetBWMode8195A(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth, // 20M or 40M
IN unsigned char Offset // Upper, Lower, or Don't care
);
VOID
PHY_SwChnl8195A( // Call after initialization
IN PADAPTER Adapter,
IN u8 channel
);
VOID
PHY_SetSwChnlBWMode8195A(
IN PADAPTER Adapter,
IN u8 channel,
IN CHANNEL_WIDTH Bandwidth,
IN u8 Offset40,
IN u8 Offset80
);
VOID PHY_SetRFPathSwitch_8723B(
IN PADAPTER pAdapter,
IN BOOLEAN bMain
);
/*--------------------------Exported Function prototype End---------------------*/
#endif

272
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APhyReg.h Normal file
View file

@ -0,0 +1,272 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __INC_HAL8195APHYREG_H__
#define __INC_HAL8195APHYREG_H__
//
// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
// Page1(0x100)
//
#define rPMAC_Reset 0x100
//
// Page8(0x800)
//
#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
#define rFPGA0_TxInfo 0x804 // Status report??
#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
#define rFPGA0_XA_HSSIParameter2 0x824
#define rFPGA0_XB_HSSIParameter1 0x828
#define rFPGA0_XB_HSSIParameter2 0x82c
#define rTxAGC_B_Rate18_06 0x830
#define rTxAGC_B_Rate54_24 0x834
#define rTxAGC_B_CCK1_55_Mcs32 0x838
#define rTxAGC_B_Mcs03_Mcs00 0x83c
#define rFPGA0_XA_LSSIParameter 0x840
#define rFPGA0_XB_LSSIParameter 0x844
#define rTxAGC_B_Mcs07_Mcs04 0x848
#define rTxAGC_B_Mcs11_Mcs08 0x84c
#define rFPGA0_XCD_SwitchControl 0x85c
#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
#define rFPGA0_XB_RFInterfaceOE 0x864
#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
#define rTxAGC_B_Mcs15_Mcs12 0x868
#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
#define rFPGA0_XCD_RFInterfaceSW 0x874
#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback
#define rFPGA0_XB_LSSIReadBack 0x8a4
#define rFPGA0_XC_LSSIReadBack 0x8a8
#define rFPGA0_XD_LSSIReadBack 0x8ac
#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback
#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback
//
// Page9(0x900)
//
#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
#define rFPGA1_TxInfo 0x90c // Useless now // Status report??
#define rS0S1_PathSwitch 0x948
#define rRXDFIR_Filter 0x954
//
// PageA(0xA00)
//
// Set Control channel to upper or lower. These settings are required only for 40MHz
#define rCCK0_System 0xa00
#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
//
// PageB(0xB00)
//
#define rPdp_AntA 0xb00
#define rPdp_AntA_4 0xb04
#define rPdp_AntA_8 0xb08
#define rPdp_AntA_C 0xb0c
#define rPdp_AntA_10 0xb10
#define rPdp_AntA_14 0xb14
#define rPdp_AntA_18 0xb18
#define rPdp_AntA_1C 0xb1c
#define rPdp_AntA_20 0xb20
#define rPdp_AntA_24 0xb24
#define rConfig_Pmpd_AntA 0xb28
#define rConfig_ram64x16 0xb2c
#define rBndA 0xb30
#define rHssiPar 0xb34
#define rConfig_AntA 0xb68
#define rConfig_AntB 0xb6c
#define rPdp_AntB 0xb70
#define rPdp_AntB_4 0xb74
#define rPdp_AntB_8 0xb78
#define rPdp_AntB_C 0xb7c
#define rPdp_AntB_10 0xb80
#define rPdp_AntB_14 0xb84
#define rPdp_AntB_18 0xb88
#define rPdp_AntB_1C 0xb8c
#define rPdp_AntB_20 0xb90
#define rPdp_AntB_24 0xb94
#define rConfig_Pmpd_AntB 0xb98
#define rBndB 0xba0
#define rAPK 0xbd8
#define rPm_Rx0_AntA 0xbdc
#define rPm_Rx1_AntA 0xbe0
#define rPm_Rx2_AntA 0xbe4
#define rPm_Rx3_AntA 0xbe8
#define rPm_Rx0_AntB 0xbec
#define rPm_Rx1_AntB 0xbf0
#define rPm_Rx2_AntB 0xbf4
#define rPm_Rx3_AntB 0xbf8
//
// PageC(0xC00)
//
#define rOFDM0_TRxPathEnable 0xc04
#define rOFDM0_TRMuxPar 0xc08
#define rOFDM0_XARxAFE 0xc10 // RxIQ DC offset, Rx digital filter, DC notch filter
#define rOFDM0_XARxIQImbalance 0xc14 // RxIQ imblance matrix
#define rOFDM0_XBRxIQImbalance 0xc1c
#define rOFDM0_RxDetector1 0xc30 // PD,BW & SBD // DM tune init gain
#define rOFDM0_ECCAThreshold 0xc4c // energy CCA
#define rOFDM0_XAAGCCore1 0xc50 // DIG
#define rOFDM0_XBAGCCore1 0xc58
#define rOFDM0_AGCRSSITable 0xc78
#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
#define rOFDM0_XBTxIQImbalance 0xc88
#define rOFDM0_XCTxAFE 0xc94
#define rOFDM0_XDTxAFE 0xc9c
#define rOFDM0_RxIQExtAnta 0xca0
#define rOFDM0_TxPseudoNoiseWgt 0xce4 // Double ADC
//
// PageD(0xD00)
//
#define rOFDM1_LSTF 0xd00
#define rOFDM1_TRxPathEnable 0xd04
//
// PageE(0xE00)
//
#define rTxAGC_A_Rate18_06 0xe00
#define rTxAGC_A_Rate54_24 0xe04
#define rTxAGC_A_CCK1_Mcs32 0xe08
#define rTxAGC_A_Mcs03_Mcs00 0xe10
#define rTxAGC_A_Mcs07_Mcs04 0xe14
#define rTxAGC_A_Mcs11_Mcs08 0xe18
#define rTxAGC_A_Mcs15_Mcs12 0xe1c
#define rFPGA0_IQK 0xe28
#define rTx_IQK_Tone_A 0xe30
#define rRx_IQK_Tone_A 0xe34
#define rTx_IQK_PI_A 0xe38
#define rRx_IQK_PI_A 0xe3c
#define rTx_IQK 0xe40
#define rRx_IQK 0xe44
#define rIQK_AGC_Pts 0xe48
#define rIQK_AGC_Rsp 0xe4c
#define rTx_IQK_Tone_B 0xe50
#define rRx_IQK_Tone_B 0xe54
#define rTx_IQK_PI_B 0xe58
#define rRx_IQK_PI_B 0xe5c
#define rIQK_AGC_Cont 0xe60
#define rBlue_Tooth 0xe6c
#define rRx_Wait_CCA 0xe70 // Rx ADC clock
#define rTx_CCK_RFON 0xe74
#define rTx_CCK_BBON 0xe78
#define rTx_OFDM_RFON 0xe7c
#define rTx_OFDM_BBON 0xe80
#define rTx_To_Rx 0xe84
#define rTx_To_Tx 0xe88
#define rRx_CCK 0xe8c
#define rTx_Power_Before_IQK_A 0xe94
#define rTx_Power_After_IQK_A 0xe9c
#define rRx_Power_Before_IQK_A_2 0xea4
#define rRx_Power_After_IQK_A_2 0xeac
#define rTx_Power_Before_IQK_B 0xeb4
#define rTx_Power_After_IQK_B 0xebc
#define rRx_Power_Before_IQK_B 0xec0
#define rRx_Power_Before_IQK_B_2 0xec4
#define rRx_Power_After_IQK_B 0xec8
#define rRx_Power_After_IQK_B_2 0xecc
#define rRx_OFDM 0xed0
#define rRx_Wait_RIFS 0xed4
#define rRx_TO_Rx 0xed8
#define rStandby 0xedc
#define rSleep 0xee0
#define rPMPD_ANAEN 0xeec
//for PutRegsetting & GetRegSetting BitMask
#define bMaskH3Bytes 0xffffff00
//
// RL6052 Register definition
//
#define RF_AC 0x00 //
#define RF_TXM_IDAC 0x08 //
#define RF_CHNLBW 0x18 // RF channel and BW switch
#define RF_RCK_OS 0x30 // RF TX PA control
#define RF_TXPA_G1 0x31 // RF TX PA control
#define RF_TXPA_G2 0x32 // RF TX PA control
#define RF_WE_LUT 0xEF
//
//Bit Mask
//
// 1. Page1(0x100)
#define bBBResetB 0x100 // Useless now?
// 2. Page8(0x800)
#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
#define bCCKEn 0x1000000
#define bOFDMEn 0x2000000
#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
#define bXCTxAGC 0xf000
#define bXDTxAGC 0xf0000
#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
#define b3WireAddressLength 0x400
#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
#define bLSSIReadAddress 0x7f800000 // T65 RF
#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
#define bLSSIReadBackData 0xfffff // T65 RF
// 3. Page9(0x900)
// 4. PageA(0xA00)
#define bCCKBBMode 0x3
#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
#define bCCKScramble 0x8
#define bCCKTxRate 0x3000
// 5. PageC(0xC00)
// 6. PageE(0xE00)
#define bOFDMContinueTx 0x10000000
#define bOFDMSingleCarrier 0x20000000
#define bOFDMSingleTone 0x40000000
//
// Other Definition
//
//for PutRegsetting & GetRegSetting BitMask
#define bMaskByte0 0xff
#define bMaskByte1 0xff00
#define bMaskByte2 0xff0000
#define bMaskByte3 0xff000000
#define bMaskHWord 0xffff0000
#define bMaskLWord 0x0000ffff
#define bMaskDWord 0xffffffff
#define bMask12Bits 0xfff
#define bMaskH4Bits 0xf0000000
#define bEnable 0x1
#define bDisable 0x0
#endif

397
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/Hal8195APwrSeq.h Normal file
View file

@ -0,0 +1,397 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef REALTEK_POWER_SEQUENCE_8195A
#define REALTEK_POWER_SEQUENCE_8195A
#include "HalPwrSeqCmd.h"
/*
Check document WM-20130111-JackieLau-RTL8723B_Power_Architecture v02.vsd
There are 6 HW Power States:
0: POFF--Power Off
1: PDN--Power Down
2: CARDEMU--Card Emulation
3: ACT--Active Mode
4: LPS--Low Power State
5: SUS--Suspend
The transision from different states are defined below
TRANS_CARDEMU_TO_ACT
TRANS_ACT_TO_CARDEMU
TRANS_CARDEMU_TO_SUS
TRANS_SUS_TO_CARDEMU
TRANS_CARDEMU_TO_PDN
TRANS_ACT_TO_LPS
TRANS_LPS_TO_ACT
TRANS_END
*/
#define RTL8195A_TRANS_CARDEMU_TO_ACT_STEPS 4
#define RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS 4
#define RTL8195A_TRANS_CARDEMU_TO_SUS_STEPS 7
#define RTL8195A_TRANS_SUS_TO_CARDEMU_STEPS 15
#define RTL8195A_TRANS_CARDEMU_TO_PDN_STEPS 15
#define RTL8195A_TRANS_PDN_TO_CARDEMU_STEPS 15
#define RTL8195A_TRANS_ACT_TO_LPS_STEPS 15
#define RTL8195A_TRANS_LPS_TO_ACT_STEPS 15
#define RTL8195A_TRANS_ACT_TO_SWLPS_STEPS 22
#define RTL8195A_TRANS_SWLPS_TO_ACT_STEPS 15
#define RTL8195A_TRANS_END_STEPS 1
//1TODO:chris
#if 1
#define RTL8195A_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
{0x0004, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},\
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/
#define RTL8195A_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1|BIT2), 0},/*0x04[24:26] = 0 turn off RF*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT0|BIT1), 0},/*0x04[16:17] = 0 BB reset*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x20[1] = 1 turn off MAC by HW state machine*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x20[1] = 0 polling until return 0 to disable*/ \
#define RTL8195A_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8195A_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8195A_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
#define RTL8195A_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
#define RTL8195A_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8195A_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8195A_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
#define RTL8195A_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8195A_TRANS_ACT_TO_SWLPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/ \
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/ \
{0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */ \
{0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */ \
{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\
{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/ \
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */
#define RTL8195A_TRANS_SWLPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\
{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#else
#define RTL8723B_TRANS_CARDEMU_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS},/*Delay 1ms*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, 0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]=1*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/* Enable WL control XTAL setting*/ \
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Enable HSISR GPIO[C:0] interrupt*/\
{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
{0x0068, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3, BIT3},/*For GPIO9 internal pull high setting by test chip*/\
{0x0069, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, BIT6},/*For GPIO9 internal pull high setting*/
#define RTL8723B_TRANS_ACT_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from register 0x65[2] */\
{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Enable rising edge triggering interrupt*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
{0x0010, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6, 0},/* Enable BT control XTAL setting*/ \
{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/ \
{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/ \
#define RTL8723B_TRANS_CARDEMU_TO_SUS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723B_TRANS_SUS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8723B_TRANS_CARDEMU_TO_CARDDIS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1}, /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
#define RTL8723B_TRANS_CARDDIS_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/\
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*0x23[4] = 1b'0 12H LDO enter normal mode*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*PCIe DMA start*/
#define RTL8723B_TRANS_CARDEMU_TO_PDN \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x20}, /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
#define RTL8723B_TRANS_PDN_TO_CARDEMU \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
#define RTL8723B_TRANS_ACT_TO_LPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*PCIe DMA stop*/ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x03},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/
#define RTL8723B_TRANS_LPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#define RTL8723B_TRANS_ACT_TO_SWLPS \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0194, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*enable 32 K source*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*CCK and OFDM are enable*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*disable security engine*/ \
{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x40},/*When driver enter Sus/ Disable, enable LOP for BT*/ \
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT5, BIT5},/*reset dual TSF*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*Reset MCUFWDL register*/ \
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 1},/*Reset CPU IO Wrapper*/ \
{0x0287, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*polling RXFF packet number = 0 */ \
{0x0286, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/*polling RXDMA idle */ \
{0x013D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Clear FW RPWM interrupt */\
{0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Set FW RPWM interrupt source*/\
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, BIT4},/*switch TSF to 32K*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/*polling TSF stable*/\
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*Set FW LPS*/ \
{0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/*polling FW LPS ready */
#define RTL8723B_TRANS_SWLPS_TO_ACT \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT4, 0},/*switch TSF to 32K*/\
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
{0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\
{0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \
{0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \
{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
#endif
#define RTL8195A_TRANS_END \
/* format */ \
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, //
extern WLAN_PWR_CFG rtl8195A_power_on_flow[RTL8195A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8195A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8195A_radio_off_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8195A_card_disable_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8195A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8195A_card_enable_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8195A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8195A_suspend_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8195A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8195A_resume_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8195A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8195A_hwpdn_flow[RTL8195A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8195A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8195A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8195A_enter_lps_flow[RTL8195A_TRANS_ACT_TO_LPS_STEPS+RTL8195A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8195A_leave_lps_flow[RTL8195A_TRANS_LPS_TO_ACT_STEPS+RTL8195A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8195A_enter_swlps_flow[RTL8195A_TRANS_ACT_TO_SWLPS_STEPS+RTL8195A_TRANS_END_STEPS];
extern WLAN_PWR_CFG rtl8195A_leave_swlps_flow[RTL8195A_TRANS_SWLPS_TO_ACT_STEPS+RTL8195A_TRANS_END_STEPS];
#endif

56
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rom_Hal8195APhyCfg.h Normal file
View file

@ -0,0 +1,56 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __ROM_HAL8195APHYCFG_H__
#define __ROM_HAL8195APHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
/*--------------------------Define Parameters End-------------------------------*/
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure End----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
u32
phy_CalculateBitShift(
u32 BitMask
);
u32
PHY_QueryBBReg_8195A(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask
);
VOID
PHY_SetBBReg_8195A(
IN PADAPTER Adapter,
IN u32 RegAddr,
IN u32 BitMask,
IN u32 Data
);
/*--------------------------Exported Function prototype End---------------------*/
#endif

337
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_cmd.h Normal file
View file

@ -0,0 +1,337 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8195A_CMD_H__
#define __RTL8195A_CMD_H__
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- H2C CMD DEFINITION ------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
enum h2c_cmd_8195A{
//Common Class: 000
H2C_8195A_RSVD_PAGE = 0x00,
H2C_8195A_MEDIA_STATUS_RPT = 0x01,
H2C_8195A_SCAN_ENABLE = 0x02,
H2C_8195A_KEEP_ALIVE = 0x03,
H2C_8195A_DISCON_DECISION = 0x04,
H2C_8195A_PSD_OFFLOAD = 0x05,
H2C_8195A_AP_OFFLOAD = 0x08,
H2C_8195A_BCN_RSVDPAGE = 0x09,
H2C_8195A_PROBERSP_RSVDPAGE = 0x0A,
H2C_8195A_FCS_RSVDPAGE = 0x10,
H2C_8195A_FCS_INFO = 0x11,
//PoweSave Class: 001
H2C_8195A_SET_PWR_MODE = 0x20,
H2C_8195A_PS_TUNING_PARA = 0x21,
H2C_8195A_PS_TUNING_PARA2 = 0x22,
H2C_8195A_P2P_LPS_PARAM = 0x23,
H2C_8195A_P2P_PS_OFFLOAD = 0x24,
H2C_8195A_PS_SCAN_ENABLE = 0x25,
H2C_8195A_SAP_PS_ = 0x26,
H2C_8195A_INACTIVE_PS_ = 0x27, //Inactive_PS
H2C_8195A_FWLPS_IN_IPS_ = 0x28,
//Dynamic Mechanism Class: 010
H2C_8195A_MACID_CFG = 0x40,
H2C_8195A_TXBF = 0x41,
H2C_8195A_RSSI_SETTING = 0x42,
H2C_8195A_AP_REQ_TXRPT = 0x43,
H2C_8195A_INIT_RATE_COLLECT = 0x44,
//BT Class: 011
H2C_8195A_B_TYPE_TDMA = 0x60,
H2C_8195A_BT_INFO = 0x61,
H2C_8195A_FORCE_BT_TXPWR = 0x62,
H2C_8195A_BT_IGNORE_WLANACT = 0x63,
H2C_8195A_DAC_SWING_VALUE = 0x64,
H2C_8195A_ANT_SEL_RSV = 0x65,
H2C_8195A_WL_OPMODE = 0x66,
H2C_8195A_BT_MP_OPER = 0x67,
H2C_8195A_BT_CONTROL = 0x68,
H2C_8195A_BT_WIFI_CTRL = 0x69,
H2C_8195A_BT_FW_PATCH = 0x6A,
//WOWLAN Class: 100
H2C_8195A_WOWLAN = 0x80,
H2C_8195A_REMOTE_WAKE_CTRL = 0x81,
H2C_8195A_AOAC_GLOBAL_INFO = 0x82,
H2C_8195A_AOAC_RSVD_PAGE = 0x83,
H2C_8195A_AOAC_RSVD_PAGE2 = 0x84,
H2C_8195A_D0_SCAN_OFFLOAD_INFO = 0x85,
H2C_8195A_D0_SCAN_OFFLOAD_CTRL = 0x86,
H2C_8195A_CHNL_SWITCH_OFFLOAD = 0x87,
H2C_8195A_RESET_TSF = 0xC0,
H2C_8195A_BCN_IGNORE_EDCCA = 0xC2,
H2C_8195A_MAXID,
};
#define H2C_8195A_RSVDPAGE_LOC_LEN 5
#define H2C_8195A_MEDIA_STATUS_RPT_LEN 3
#define H2C_8195A_KEEP_ALIVE_CTRL_LEN 2
#define H2C_8195A_DISCON_DECISION_LEN 3
//#define H2C_8195A_AP_OFFLOAD_LEN 3
#define H2C_8195A_PWRMODE_LEN 11
#define H2C_8195A_PSTUNEPARAM_LEN 4
#define H2C_8195A_MACID_CFG_LEN 7
#define H2C_8195A_BTMP_OPER_LEN 4
#define H2C_8195A_WOWLAN_LEN 3
#define H2C_8195A_REMOTE_WAKE_CTRL_LEN 1
#define H2C_8195A_AOAC_GLOBAL_INFO_LEN 2
#define H2C_8195A_AOAC_RSVDPAGE_LOC_LEN 7
//#define H2C_8723B_SCAN_OFFLOAD_CTRL_LEN 4
#define H2C_8195A_BT_FW_PATCH_LEN 6
#define H2C_8195A_RSSI_SETTING_LEN 4
#define H2C_8195A_AP_REQ_TXRPT_LEN 2
#define H2C_8195A_FORCE_BT_TXPWR_LEN 3
#define H2C_8195A_BCN_IGNORE_EDCCA_LEN 1
#ifdef CONFIG_WOWLAN
#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 )
#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5])
#define cpIpAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3])
//
// ARP packet
//
// LLC Header
#define GET_ARP_PKT_LLC_TYPE(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6)
//ARP element
#define GET_ARP_PKT_OPERATION(__pHeader) ReadEF2Byte( ((u8*)(__pHeader)) + 6)
#define GET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+8)
#define GET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr((u8*)(_val), ((u8*)(__pHeader))+14)
#define GET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr((u8*)(_val), ((u8*)(__pHeader))+18)
#define GET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr((u8*)(_val), ((u8*)(__pHeader))+24)
#define SET_ARP_PKT_HW(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 0, __Value)
#define SET_ARP_PKT_PROTOCOL(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 2, __Value)
#define SET_ARP_PKT_HW_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 4, __Value)
#define SET_ARP_PKT_PROTOCOL_ADDR_LEN(__pHeader, __Value) WriteEF1Byte( ((u8*)(__pHeader)) + 5, __Value)
#define SET_ARP_PKT_OPERATION(__pHeader, __Value) WriteEF2Byte( ((u8*)(__pHeader)) + 6, __Value)
#define SET_ARP_PKT_SENDER_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+8, (u8*)(_val))
#define SET_ARP_PKT_SENDER_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+14, (u8*)(_val))
#define SET_ARP_PKT_TARGET_MAC_ADDR(__pHeader, _val) cpMacAddr(((u8*)(__pHeader))+18, (u8*)(_val))
#define SET_ARP_PKT_TARGET_IP_ADDR(__pHeader, _val) cpIpAddr(((u8*)(__pHeader))+24, (u8*)(_val))
#define FW_WOWLAN_FUN_EN BIT(0)
#define FW_WOWLAN_PATTERN_MATCH BIT(1)
#define FW_WOWLAN_MAGIC_PKT BIT(2)
#define FW_WOWLAN_UNICAST BIT(3)
#define FW_WOWLAN_ALL_PKT_DROP BIT(4)
#define FW_WOWLAN_GPIO_ACTIVE BIT(5)
#define FW_WOWLAN_REKEY_WAKEUP BIT(6)
#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7)
#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0)
#define FW_FW_PARSE_MAGIC_PKT BIT(1)
#define FW_REMOTE_WAKE_CTRL_EN BIT(0)
#define FW_REALWOWLAN_EN BIT(5)
#endif //CONFIG_WOWLAN
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- H2C CMD CONTENT --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
//_RSVDPAGE_LOC_CMD_0x00
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
//_MEDIA_STATUS_RPT_PARM_CMD_0x01
#define SET_8723B_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
//_KEEP_ALIVE_CMD_0x03
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8723B_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
//_DISCONNECT_DECISION_CMD_0x04
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
// _PWR_MOD_CMD_0x20
#define SET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_TDMA_SLOT_LEN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+7, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_TDMA_PERIOD_LEN_1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+8, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_TDMA_PERIOD_LEN_2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+9, 0, 8, __Value)
#define SET_8723B_H2CCMD_PWRMODE_PARM_TDMA_PERIOD_LEN_3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+10, 0, 8, __Value)
#define GET_8723B_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8)
// _PS_TUNE_PARAM_CMD_0x21
#define SET_8723B_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value)
#define SET_8723B_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value)
#define SET_8723B_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
//_MACID_CFG_CMD_0x40
#define SET_8723B_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value)
#define SET_8723B_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value)
//_RSSI_SETTING_CMD_0x42
#define SET_8723B_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value)
#define SET_8723B_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
// _AP_REQ_TXRPT_CMD_0x43
#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
// _FORCE_BT_TXPWR_CMD_0x62
#define SET_8723B_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE_8BIT(__pH2CCmd, 0, 8, __Value)
// _FORCE_BT_MP_OPER_CMD_0x67
#define SET_8723B_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value)
#define SET_8723B_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value)
#define SET_8723B_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value)
// _BT_FW_PATCH_0x6A
#define SET_8723B_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value)
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8723B_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
// _WoWLAN PARAM_CMD_0x80
#define SET_8723B_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value)
#define SET_8723B_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value)
#define SET_8723B_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
// _REMOTE_WAKEUP_CMD_0x81
#define SET_8723B_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value)
#define SET_8723B_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value)
// AOAC_GLOBAL_INFO_0x82
#define SET_8723B_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
// AOAC_RSVDPAGE_LOC_0x83
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_REQ(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value)
#define SET_8723B_H2CCMD_AOAC_RSVDPAGE_LOC_NETWORK_LIST(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+6, 0, 8, __Value)
//---------------------------------------------------------------------------------------------------------//
//------------------------------------------- Structure --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
typedef struct _RSVDPAGE_LOC {
u8 LocProbeRsp;
u8 LocPsPoll;
u8 LocNullData;
u8 LocQosNull;
u8 LocBTQosNull;
#ifdef CONFIG_WOWLAN
u8 LocRemoteCtrlInfo;
u8 LocArpRsp;
u8 LocNbrAdv;
u8 LocGTKRsp;
u8 LocGTKInfo;
u8 LocProbeReq;
u8 LocNetList;
#endif //CONFIG_WOWLAN
} RSVDPAGE_LOC_8195A, *PRSVDPAGE_LOC_8195A;
//---------------------------------------------------------------------------------------------------------//
//---------------------------------- Function Statement --------------------------------------------------//
//---------------------------------------------------------------------------------------------------------//
// host message to firmware cmd
void rtl8195a_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode);
void rtl8195a_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus);
#ifdef CONFIG_BT_COEXIST
void rtl8195a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(PADAPTER padapter);
#endif
void rtl8195a_set_rssi_cmd(PADAPTER padapter, u8 *param);
void rtl8195a_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8* arg, u8 rssi_level);
void rtl8195a_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack);
//s32 rtl8723b_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable);
void rtl8195a_set_FwPsTuneParam_cmd(PADAPTER padapter);
void rtl8195a_set_FwMacIdConfig_cmd(_adapter* padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask);
void rtl8195a_set_FwMediaStatusRpt_cmd(PADAPTER padapter, u8 mstatus, u8 macid);
void rtl8195a_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param);
void rtl8195a_download_rsvd_page(PADAPTER padapter, u8 mstatus);
#ifdef CONFIG_P2P
void rtl8195a_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state);
#endif //CONFIG_P2P
void CheckFwRsvdPageContent(PADAPTER padapter);
#ifdef CONFIG_WOWLAN
void rtl8195a_set_wowlan_cmd(_adapter* padapter, u8 enable);
void SetFwRelatedForWoWLAN8195a(_adapter* padapter, u8 bHostIsGoingtoSleep);
#endif//CONFIG_WOWLAN
void rtl8195a_set_FwPwrModeInIPS_cmd(PADAPTER padapter);
#ifdef CONFIG_TSF_RESET_OFFLOAD
u8 rtl8195a_reset_tsf(_adapter *padapter, u8 reset_port);
#endif // CONFIG_TSF_RESET_OFFLOAD
s32 FillH2CCmd8195A(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer);
#define FillH2CCmd FillH2CCmd8195A
#endif

81
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_dm.h Normal file
View file

@ -0,0 +1,81 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8195A_DM_H__
#define __RTL8195A_DM_H__
enum{
UP_LINK,
DOWN_LINK,
};
enum{
LLT,
TXRPT,
RXBUFF,
TXBUFF,
};
//============================================================
// Description:
//
// This file is for 8723B dynamic mechanism only
//
//
//============================================================
//0x8000: TXRPT:2K
//max macid : 128
//TXRPT SIZE 16 bytes
//0x8800: Rate Mask:1K
//Ramask size 8bytes
#define DYNAMIC_FUNC_BT BIT(0)
#define REPORT_OFFSET 0x8100
#define RAMASK_OFFSET 0x8900
#define LLT_H_ADDR 0x650
#define TXREPORT_H_ADDR 0x660
#define RXBUFF_H_ADDR 0x670
#define TXBUFF_H_ADDR 0x680
//============================================================
// structure and define
//============================================================
//============================================================
// function prototype
//============================================================
void rtl8195a_init_dm_priv(PADAPTER padapter);
void rtl8195a_deinit_dm_priv(PADAPTER padapter);
void rtl8195a_InitHalDm(PADAPTER padapter);
void rtl8195a_HalDmWatchDog(PADAPTER padapter);
void rtl8195a_HalDmWatchDog_in_LPS(PADAPTER padapter);
void rtl8195a_hal_dm_in_lps(PADAPTER padapter);
u8 ReadTxrpt8(IN PADAPTER padapter, IN u8 Macid, IN u8 Offset);
VOID WriteTxrpt8(IN PADAPTER padapter, IN u8 Macid, IN u8 Offset, IN u8 Val);
BOOLEAN GetMediaStatusCommon(IN PADAPTER pAdapter, IN u8 macid);
VOID GetTxrptStatistic(IN PDM_ODM_T pDM_Odm, IN PODM_RA_INFO_T pRaInfo,IN u8 Reset_var);
#endif

35
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_led.h Normal file
View file

@ -0,0 +1,35 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8195A_LED_H__
#define __RTL8195A_LED_H__
#include <drv_conf.h>
#include <osdep_service.h>
#include <drv_types.h>
//================================================================================
// Interface to manipulate LED objects.
//================================================================================
void rtl8195a_InitSwLeds(PADAPTER padapter);
void rtl8195a_DeInitSwLeds(PADAPTER padapter);
#endif

130
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_pmu_cmd.h Normal file
View file

@ -0,0 +1,130 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8195A_PMU_CMD_H__
#define __RTL8195A_PMU_CMD_H__
typedef enum _RT_MEDIA_STATUS{
RT_MEDIA_DISCONNECT = 0,
RT_MEDIA_CONNECT = 1
}RT_MEDIA_STATUS;
typedef enum _H2C_CMD_ {
//1 Class1: Common
H2CID_RSVDPAGE = 0x00,
H2CID_JOININFO = 0x01,
H2CID_SCAN = 0x02,
H2CID_KEEP_ALIVE = 0x03,
H2CID_DISCONNECT_DECISION = 0x04,
H2CID_PSD_OFFLOAD = 0x05,
rsvd2 = 0x06,
rsvd3 = 0x07,
H2CID_AP_OFFLOAD = 0x08,
H2CID_BCN_RsvdPage = 0x09,
H2CID_Probersp_RsvdPage = 0x0A,
H2CID_AP_OFFLOAD_STAINFO = 0x0B,
H2CID_FAST_CS_RSVDPAGE = 0x10,
H2CID_FAST_CHANNEL_SWITCH = 0x11,
H2CID_BB_GAIN_REPORT = 0x12,
H2CID_GPIO_CTRL = 0x13,
H2CID_HW_INFO = 0x14,
//1 Class2: Power Save
H2CID_SETPWRMODE = 0x20,
H2CID_PSTURNINGPARM = 0x21,
H2CID_PSTURNINGPARM2 = 0x22,
H2CID_PSLPSPARM = 0x23,
H2CID_P2PPS_OFFLOAD = 0x24,
H2CID_PS_SCAN = 0x25,
H2CID_SAPPS = 0x26,
H2CID_INACTIVE_PS = 0x27,
H2CID_NOLINK_PS = 0x28,
//1 Class3: Dynamic Mechaism
H2CID_MACID_CFG = 0x40,
H2CID_TxBF = 0x41,
H2CID_RSSI_SETTING = 0x42,
H2CID_AP_REQ_TXRPT = 0x43,
H2CID_INIT_RATE_COLLECT = 0x44,
H2CID_IQK_OFFLOAD = 0x45,
//1 Class4: BT Coex
H2CID_B_TYPE_TDMA = 0x60,
H2CID_BT_INFO = 0x61,
H2CID_FORCE_BT_TXPWR = 0x62,
H2CID_BT_IGNORE_WLANACT = 0x63,
H2CID_DAC_SWING_VALUE = 0x64,
H2CID_ANT_SEL_REVERSE = 0x65,
H2CID_WL_OPMODE = 0x66,
H2CID_BT_MP_OPERATION = 0x67,
H2CID_BT_CONTROL = 0x68,
H2CID_BT_WIFICTRL = 0x69,
H2CID_BT_PATCH_DOWNLOAD = 0x6A,
H2CID_BT_SCO_eSCO_OPERATION = 0x6B,
H2CID_BT_Page_Scan_Interval = 0x6C,
H2CID_WL_Calibraion = 0x6D,
H2CID_GNT_BT_CTRL = 0x6E,
H2CID_BT_ONLY_TEST = 0x6F,
//1 Class5: WOWLAN
H2CID_WoWLAN = 0x80,
H2CID_RemoteWakeCtrl = 0x81,
H2CID_AOAC_Global_info = 0x82,
H2CID_AOAC_Rsvdpage1 = 0x83,
H2CID_AOAC_Rsvdpage2 = 0x84,
H2CID_D0_Scan_offload_info = 0x85,
H2CID_D0_Scan_offload_ctrl = 0x86,
H2CID_Switch_channel = 0x87,
H2CID_AOAC_Rsvdpage3 = 0x88,
H2CID_GPIO_WF_Customize = 0x89,
H2CID_P2P_RsvdPage = 0x8A,
H2CID_P2P_Offload = 0x8B,
//1 Class6: LTECOEX
H2CID_LTECOEX_EN = 0xA0,
H2CID_WLAN_High_Priority = 0xA1,
//1 Class7: Patch
H2CID_TSF_RESET = 0xC0,
H2CID_BB_NHM = 0xC1,
H2CID_BCN_IGNORE_EDCCA = 0xC2,
//1 Class8: Testing
H2CID_H2C2HLB = 0xE0
} H2C_CMD, *PH2C_CMD;
typedef struct _H2CParam_JoinInfo_ {
BOOLEAN bConnected:1;
BOOLEAN bMacid_ind:1;
u8 rsvd:6;
u8 macid;
u8 macid_end;
}H2CParam_JoinInfo, *PH2CParam_JoinInfo;
typedef struct _H2CParam_RsvdPage_ {
RSVDPAGE_LOC_8195A RsvdPageLoc;
u8 *ReservedPagePacket;
u32 TotalPacketLen;
} H2CParam_RsvdPage, *PH2CParam_RsvdPage;
u32 H2CCmdCommon(PADAPTER padapter, u8 ElementID, u8 *pCmdBuffer);
#endif //__RTL8195A_PMU_CMD_H__

491
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_pmu_task.h Normal file
View file

@ -0,0 +1,491 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8195A_PMU_TASK_H__
#define __RTL8195A_PMU_TASK_H__
#ifdef CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
//BitMAPDefine
#define RATEADAPTIVE BIT0
#define H2CEVENT BIT1
#define C2HEVENT BIT2
#define RATRYDONE BIT3
#define REMOTEWAKEEVENT BIT4
#define APOFFLOADEVENT BIT5
#define MAILBOXEVENT BIT6
#define SWTIMEREVENT BIT7
#define BBNHMEVENT BIT8
#define DBGPKTEVENT BIT9
#define SIDEBANDWoWLAN BIT10
#if 0
#ifdef CONFIG_POWER_SAVING
#define BCNEARLY BIT11
#define MTIBCNIVLEAR BIT12
#define BCNRX BIT13
#define RXBMD1 BIT14
#define RXBMD0 BIT15
#define RXUMD1 BIT16
#define RXUMD0 BIT17
#define TXPKTIN BIT18
#define GTIMER6TO BIT19
#define GTIMER7TO BIT20
#endif //#ifdef CONFIG_POWER_SAVING
#endif
//BT mailbox
#define SETDATA BIT2
#define SETACK BIT1
#define GETDATA BIT0
/*--------------------------Define -------------------------------------------*/
#ifdef CONFIG_POWER_SAVING
#define MACID_CLIENT 0
#endif //#ifdef CONFIG_POWER_SAVING
/*------------------------------Define Enum-----------------------------------*/
#ifdef CONFIG_POWER_SAVING
//REGDUMP_FW_ERR0
typedef enum _FW_ERR0_STATUS_
{
FES0_H2C_CMDID = BIT0,
FES0_H2C_PTR = BIT1,
FES0_BB_RW = BIT2,
FES0_TXPKT_TXPAUSE = BIT3,
FES0_TSF_STABLE = BIT4,
FES0_TXSM_STABLE = BIT5,
FES0_RPWM_STABLE = BIT6,
FES0_C2H_TIMEOUT_ERR = BIT7,
}FW_ERR0_STATUS, *PFW_ERR0_STATUS;
//TxPauseReasonCode
typedef enum _TRPC_ {
TPRC_ISSUENULLDATA_1 = 0x26,
TPRC_ISSUENULLDATA_2 = 0x27,
TPRC_PSS2TS3 = 0x2B,
TPRC_PSS0TS1 = 0x2C,
TPRC_PSS2TS4 = 0x2D,
TPRC_PSS2TS5 = 0x2E,
TPRC_PSS0TS6 = 0x2F,
} TRPC, *PTRPC;
typedef enum _PS_MODE_SETTING_SELECTION_
{
MODE_SETTING_ACTIVE = 0,
MODE_SETTING_LEGACY = 1,
MODE_SETTING_WMMPS = 2,
#ifdef TDMA_POWER_SAVING
MODE_SETTING_TDMA = 3
#endif //#ifdef TDMA_POWER_SAVING
}PS_MODE_SETTING_SELECTION, *PPS_MODE_SETTING_SELECTION;
typedef enum _RxListenBeaconMode_
{
RLBM_MIN = 0,
RLBM_MAX = 1,
RLBM_SELF_DEFINED = 2
}RxListenBeaconMode, *PRxListenBeaconMode;
typedef enum _SMART_PS_MODE_FOR_LEGACY_
{
SMART_PS_MODE_LEGACY_PWR1 = 0, // TRX all use PS_POLL
SMART_PS_MODE_TX_PWR0 = 1, // TX: pwr bit = 0, RX: PS_POLL
SMART_PS_MODE_TRX_PWR0 = 2 // TX: pwr bit = 0, RX: NULL(0)
}SMART_PS_MODE_FOR_LEGACY, *PSMART_PS_MODE_FOR_LEGACY;
#endif //#ifdef CONFIG_POWER_SAVING
/*--------------------------Define MACRO--------------------------------------*/
#define HAL_WL_READ32(addr) \
HAL_READ32(WIFI_REG_BASE, addr)
#define HAL_WL_WRITE32(addr, value) \
HAL_WRITE32(WIFI_REG_BASE, addr, value)
#define HAL_WL_READ16(addr) \
HAL_READ16(WIFI_REG_BASE, addr)
#define HAL_WL_WRITE16(addr, value) \
HAL_WRITE16(WIFI_REG_BASE, addr, value)
#define HAL_WL_READ8(addr) \
HAL_READ8(WIFI_REG_BASE, addr)
#define HAL_WL_WRITE8(addr, value) \
HAL_WRITE8(WIFI_REG_BASE, addr, value)
#ifdef CONFIG_POWER_SAVING
#define mtou(x) ((x)<<10) //ms->us
#define WAIT_TSF_STABLE_BREAK_CNT 5000
#define WAIT_TSF_STABLE_CNT 50
#define WAIT_TSF_STABLE_ONCE_TIME 20
#define TSFIS32K 1
#define TSFIS40M 0
#define GET_TSF_STATE() (((HAL_WL_READ16(0xF0) & BIT8) && (HAL_WL_READ16(0xF0) & BIT9)) ? TSFIS32K : TSFIS40M)
#define REG_ARFR5_8723B 0x04A4
#define WAIT_TXSM_STABLE_CNT 1000
#define WAIT_TXSM_STABLE_ONCE_TIME 50
#define MODE_TIMER 1
#define MODE_COUNTER 0
#define GTIMER6 6
#define GTIMER7 7
#define TIMER_BCNTO GTIMER6 //6
#define TIMER_DTIM GTIMER6 //6
#define TIMER_CHECKSTATE GTIMER6 //6
#define TIMER_PSTRX GTIMER7 //7
#ifdef TDMA_POWER_SAVING
#define TIMER_TDMA GTIMER7 //7
#endif //#ifdef TDMA_POWER_SAVING
#define RTY_LMT_NULLDATA 8
#define RTY_LMT_PSPOLL 24
#define RTY_LMT_MORE_NULLDATA 24
/*
PS_RX_INFO[7:0]: Power Save RX Information Register
initial value: 0x00
REG III.220 (Offset 0x 0692h) PS_RX_INFO Register Definition
*/
#define RXDATAIN0 BIT0 //PSTX
#define RXDATAIN1 BIT1 //PSRX
#define RXDATAIN2 BIT2
#define RXMGTIN0 BIT3
#define RXCTRLIN0 BIT4
//CPWM Definition
#define CLK_DOWN_RDY BIT4
//Power Save Tuning Parameter
//#if IS_CATEGORY_WOWLAN(CONFIG_CATEGORY_SEL)
//#define DEFAULT_BCN_TO_LIMIT 5 // 1
//#define DEFAULT_BCN_TO_PERIOD 8 //5
//#else
#define DEFAULT_BCN_TO_LIMIT 2 // 1
#define DEFAULT_BCN_TO_PERIOD 4 //5
//#endif
#define DEFAULT_BCN_TO_TIMES_LIMIT 2 // 20140806
#define DEFAULT_DTIM_TIMEOUT 15 // 7 // 7 ms
#define DEFAULT_PS_TIMEOUT 15 // 20 // 20 ms
#define DEFAULT_PS_DTIM_PERIOD 7
#define DEFAULT_PS_DRV_EARLY 2
#define DEFAULT_ENTER32K_TIMER 1000 //us
//#define PS_DRV_BCN_SHIFT_MAX DEFAULT_PS_DRV_EARLY-1
#define NULL_DATA0_ALLOW 1
#define NULL_DATA0_DENY 0
#define PS_RF_OFF_8723B 0
#define PS_GO_ON BIT0
#define PS_TX_NULL BIT1
#define PS_RF_ON BIT2
#define PS_REGISTER_ACTIVE BIT3
//#define PS_ACK BIT6
//#define PS_TOGGLE BIT7
#define PS_STATE_MASK (0x0F)
//#define PS_STATE(x) (PS_STATE_MASK & (x))
#define PS_IS_TX_NULL(x) ((x) & PS_TX_NULL )
//#define PS_IS_ACK(x) ((x) & PS_ACK )
#define PS_IS_CLK_ON(x) ((x) & (PS_RF_OFF_8723B |PS_ALL_ON ))
#define PS_IS_RF_OFF(x) ((x)|PS_RF_OFF_8723B)
//#define PS_IS_RF_ON(x) ((x) & (PS_RF_ON))
//#define PS_IS_ACTIVE(x) ((x) & (PS_REGISTER_ACTIVE))
#define PS_STATUS_S0 (PS_REGISTER_ACTIVE | PS_RF_ON) //(1,1,0) all on = register active + rf on
#define PS_STATUS_S1 (PS_REGISTER_ACTIVE | PS_RF_ON | PS_TX_NULL) //(1,1,1) all on + tx null(1)
#define PS_STATUS_S2 (PS_RF_ON) //(0,1,0) register sleep + rf on
#define PS_STATUS_S3 (PS_RF_ON | PS_TX_NULL) //(0,1,1) register sleep + rf on + tx null(0)
#define PS_STATUS_S4 0 //(0,0,0) all OFF
#define PS_STATUS_S5 (PS_TX_NULL ) //(0,0,1) SCAN = register sleep + rf on + scan enable
#define PS_STATUS_S6 (PS_REGISTER_ACTIVE) //(1,0,0) NoA off = register active + rf off
/* DATA FIN Condition Flags */
#define STA_DATA_OPEN BIT0 // indicate that FW open due to TIM = 1 condition. (PS-POLL as trigger frame)
#define BC_DATA_OPEN BIT1 // indicate that FW open due to DTIM = 1 condition. (BC & MC)
#define QOS_DATA_OPEN BIT2 // indicate that FW open due to UAPSD trigger condition. (QNULL)
#define ALL_80211_DATA_OPEN (STA_DATA_OPEN | BC_DATA_OPEN | QOS_DATA_OPEN)
#define IS_80211_DATA_OPEN(x) ((x) & ALL_80211_DATA_OPEN)
#define C2H_DATA_OPEN BIT3 // indicate that FW open due to C2H event
#define IS_C2H_DATA_OPEN(x) ((x) & C2H_DATA_OPEN)
#define BCN_DATA_OPEN BIT4
#define APP_DATA_OPEN BIT5
#define SET_DATA_OPEN(x, type) ((x) |= (type))
#define CLR_DATA_OPEN(x, type) ((x) &= (~type))
#define IS_DATA_OPEN(x, type) ((x) & (type))
//pwr state
#define PS_TYPE_32KPERMISSION 0
#define PS_TYPE_CURRENT_PS_STATE 1
#define PS_TYPE_LASTRPWM 2
#define CCXRPT_START_ADDR 0x0000
#define SW_DEFINE_NULL0 0x123
#define SW_DEFINE_NULL1 0x321
#define SW_DEFINE_OFFSET 6
#define RETRY_OVER BIT7
#define CCXRPT_OFFSET(x) (x << 3)
#define WLAN_ENTERCRITICAL() __disable_irq()
#define WLAN_EXITCRITICAL() __enable_irq()
#endif //#ifdef CONFIG_POWER_SAVING
/*------------------------------Define Struct---------------------------------*/
#ifdef CONFIG_POWER_SAVING
typedef struct _PS_PARM_ {
u8 Enter32KHzPermission;
u8 bAllQueueUAPSD;
u8 ps_dtim_flag; // indicate dtim of current beacon.
u8 pstrx_rxcnt_period;
u8 NoConnect32k;
u8 ack_last_rpwm;
u8 TxNull0;
u8 TxNull1;
u8 TxNull0ok;
u8 TxNull1ok;
u8 RfOffLicenseForBCNRx; //filen: After we received ps_bcn_cnt beacons, we can sleep(rf off).
u8 BCNAggEn;
u8 IsGoingTo32K;
u8 bMaxTrackingBcnMode;
u8 BcnTraceDone;
/*
filen: to indicate whether it is smart power saving or not
0: Legacy PS
1: Smart PS(RX use ps_poll)
2: Smart PS (RX use null_data(0))
*/
u8 smart_ps:4; //enum SMART_PS_MODE
u8 RLBM:4; // RX BCN MODE (min, max, active, ...)
u8 AwakeInterval;
u8 ps_mode; // ps type (avtive, legacy, wmmps)
u8 ClkRequestEnable;
u8 last_rpwm;
u8 current_ps_state;
u8 ps_data_open;
u8 ps_bcn_pass_time; // fw will only report one beacon information to driver after ps_bcn_pass_time ms. Unit: 100ms
u8 ps_dtim_period;
u8 ps_dtim_cnt;
u8 ps_bcn_to; // beacon timeout (ms).
u8 bcn_to_cnt; // indicate the total number of contnuous BCN_TO we have received.
u8 bcn_to_times_cnt; //20140806
u8 min_rate_in_rrsr;
// u8 lps_control;
u16 ps_drv_early_itv;
// u32 RFECtrl;
u32 null1_ok_cnt;
#ifdef TDMA_POWER_SAVING
u8 SlotPeriod;
u8 FirstOnPeriod;
u8 SecondOnPeriod;
u8 ThirdOnPeriod;
u8 CurrentSlot;
BOOLEAN TDMAOnPeriod;
#endif // #ifdef TDMA_POWER_SAVING
#if 0
u8 BcnAheadShift;
u8 BcnEarlyShift;
u8 BcnEarlyShiftMax;
u8 DefaultBcnEarly;
u8 RxBcnCount;
u8 TBTTCount;
u8 CurrentEarly;
u8 CurrentTimeOut;
u8 ReachBcnLimitCount;
u8 BcnDelayInAheadGroupOfAP;
u8 BcnDelayInRearGroupOfAP;
u8 BcnDelay[BCN_CALCULATION_MAX];
u8 XtalDelay;
u16 TSFOnTBTT; //unit in TU
u32 TSFOnRxBcn;
u32 TSFOnBcnEarly;
#endif
#if 0
#if CONFIG_BCNEARLY_ADJUST
u8 BcnEalyIndex;
u8 BcnEarlyAdjustPosition;
u8 BcnAdjustTogo;
u8 RxBcnArray[BCN_ADJUST_COUNT];
#endif
#endif
}PS_PARM, *PPS_PARM;
typedef struct _LEGACY_PS_PPARM_ {
u8 ps_mode:7;
u8 ClkRequestEnable:1;
u8 RLBM:4; //RX Listen BCN Mode
u8 smart_ps:4;
u8 AwakeInterval; //Unit: beacon interval, this field is only valid in PS Self-Defined mode
u8 bAllQueueUAPSD:1; // 1: all queue are uapsd 0: not all queue are uapsd
u8 bMaxTrackingBcnMode:1;
u8 rsvd:6;
//#if CONFIG_FAST_CPWM
u8 PwrState;
//#else
// u8 permission32k:1;
// u8 rsvd1:7;
//#endif
u8 LowPwrRxBCN :1;
u8 AntAutoSwitch :1;
u8 PSAllowBTHighPri:1;
u8 ProtectBCN :1;
u8 SilencePeriod :1;
u8 FastBTConnect :1;
u8 TwoAntennaEn :1;
u8 rsvd2 :1;
u8 AdoptUserSetting:1;
u8 DrvBcnEarlyShift :3;
u8 DrvBcnTimeOut :4;
#ifdef TDMA_POWER_SAVING
u8 SlotPeriod;
u8 FirstOnPeriod;
u8 SecondOnPeriod;
u8 ThirdOnPeriod;
#endif //#ifdef TDMA_POWER_SAVING
}LEGACY_PS_PARM, *PLEGACY_PS_PARM;
//H2C Index: 0x20
typedef struct _H2CParam_SetPwrMode_parm_ {
LEGACY_PS_PARM PwrModeParm;
}H2CParam_PwrMode, *PH2CParam_PwrMode;
#endif //#ifdef CONFIG_POWER_SAVING
/*------------------------------Function declaration--------------------------*/
#ifdef CONFIG_POWER_SAVING
#if 0
extern void ClockDown(PADAPTER padapter);
extern void ClockUp(PADAPTER padapter);
extern void PrintBcnFunction(void);
extern void DisDbgMsg(void);
extern void EnDbgMsg(void);
extern void UpChGain(void);
extern void StartCount(PADAPTER padapter);
extern void StopCount(PADAPTER padapter);
extern void IssueNullDataTest(PADAPTER padapter);
extern void ShowPowerState(PADAPTER padapter);
#endif
#ifdef TDMA_POWER_SAVING
extern void TDMAChangeStateTask(PADAPTER padapter);
#endif //#ifdef TDMA_POWER_SAVING
extern void EnterPS(PADAPTER padapter);
extern void GTimer6Handle(VOID *Data);
extern void GTimer7Handle(VOID *Data);
extern void InitGTimer1ms(PADAPTER padapter, u8 IRQDis, u8 TimerID, u32 Period);
extern void DeInitGTimer1ms(PADAPTER padapter, u8 TimerID);
extern void ChangeTransmiteRate(u16 offset, u8 rate);
extern void PowerBitSetting(BOOLEAN bPowerBit, u16 offset);
extern void ChkandChangePS(PPS_PARM pPSParm, BOOLEAN bPowerBit);
extern u16 IssueRsvdPagePacketSetting(u8 PageNum, BOOLEAN bHwSEQEn, u8 RtyLmt);
extern void InitRsvdPgPkt(void);
extern BOOLEAN IssueNullData(PPS_PARM pPSParm, BOOLEAN bPowerBit, u8 RtyLmt);
extern void IssuePSPoll(void);
extern BOOLEAN WaitTxStateMachineOk(void);
extern void WriteTxPause(u8 value, u8 rcode);
extern void PsCloseRF(void);
extern void PsOpenRF(void);
extern void SetPwrStateReg(PPS_PARM pPSParm, u8 PwrStateType, u8 value);
extern BOOLEAN ChkTxQueueIsEmpty(void);
extern void InitPS(PADAPTER padapter);
extern void ResetPSParm(PADAPTER padapter);
extern void Legacy_PS_Setting(PADAPTER padapter);
extern void PSModeSetting(PADAPTER padapter, u8 on);
extern void ConfigListenBeaconPeriod(PPS_PARM pPSParm, u8 RLBM, u8 AwakeInterval);
extern void PSSetMode(PADAPTER padapter, PLEGACY_PS_PARM pparm);
extern BOOLEAN PS_S2_Condition_Match(PPS_PARM pPSParm);
extern BOOLEAN PS_S4_Condition_Match(PADAPTER padapter);
extern BOOLEAN PS_32K_Condition_Match(void);
extern void PS_S2ToS3ToS0State(PADAPTER padapter, u8 nulldata0Allow);
extern void PS_S2ToS0State(PPS_PARM pPSParm);
extern void PS_S3ToS2orS0State(PPS_PARM pPSParm);
extern void PS_S0ToS1ToS2State(PADAPTER padapter);
extern void PS_S1ToS0orS2State(PPS_PARM pPSParm);
extern void PS_S2ToS4State(PADAPTER padapter);
extern void PS_S2ToS5State(PPS_PARM pPSParm);
extern void PS_S4ToS2State(PPS_PARM pPSParm, u8 ReleaseTxPause);
extern void PS_S5ToS2State(PPS_PARM pPSParm);
extern void PS_S0ToS6State(PADAPTER padapter);
extern void PS_S6ToS0State(PPS_PARM pPSParm);
extern void CheckTSFIsStable(u8 ReqState);
extern void WaitHWStateReady(void);
extern void SysClkDown(PPS_PARM pPSParm);
extern void SysClkUp(PPS_PARM pPSParm);
extern void SleepTo32K(PPS_PARM pPSParm);
extern void Change_PS_State(PADAPTER padapter, u8 request_ps_state, u8 nulldata0Allow);
extern void ChangePSStateByRPWM(PADAPTER padapter);
extern void SetSmartPSTimer(PADAPTER padapter);
extern void SmartPS2InitTimerAndToGetRxPkt(PADAPTER padapter);
extern void PS_OnBeacon(PADAPTER padapter);
extern void PSBcnEarlyProcess(PADAPTER padapter);
extern void PSMtiBcnEarlyProcess(PADAPTER padapter);
extern void PSRxBcnProcess(PADAPTER padapter);
extern void TxPktInPSOn(PADAPTER padapter);
extern void PsBcnToProcess(PADAPTER padapter);
extern BOOL RPWMProcess(PADAPTER padapter, BOOLEAN benter32k);
extern void ISR_MtiBcnEarly(PADAPTER padapter);
extern void ISR_BcnEarly(PADAPTER padapter);
extern void ISR_RxBcn(PADAPTER padapter);
extern void ISR_RxBCMD1(PADAPTER padapter);
extern void ISR_RxBCMD0(PADAPTER padapter);
extern void ISR_RxUCMD1(PADAPTER padapter);
extern void ISR_RxUCMD0(PADAPTER padapter);
extern void ISR_TxPktIn(PADAPTER padapter);
extern void ISR_TXCCX(PADAPTER padapter);
extern void H2CHDL_SetPwrMode(PADAPTER padapter, u8* pCmdBuffer);
extern void CheckInReqStateTask(PADAPTER padapter);
extern void HalSetRPWM(PADAPTER padapter, BOOLEAN benter32k);
extern u32 HalGetNullTxRpt(PADAPTER padapter);
//extern thread_return HalEnter32KThreadRtl8195a(thread_context context);
#endif //#ifdef CONFIG_POWER_SAVING
extern void ISR_TBTT(PADAPTER padapter);
extern void H2CHDL_BcnIgnoreEDCCA(PADAPTER padapter, u8* pCmdBuffer);
void PMUTask(PADAPTER padapter);
void PMUInitial(PADAPTER padapter);
#endif //CONFIG_LITTLE_WIFI_MCU_FUNCTION_THREAD
#endif //__RTL8195A_PMU_TASK_H__

232
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_recv.h Normal file
View file

@ -0,0 +1,232 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8195A_RECV_H__
#define __RTL8195A_RECV_H__
#ifdef CONFIG_WLAN_HAL_TEST
#define MAX_RECVBUF_SZ 1200//(RX_DMA_SIZE_8195A - RX_DMA_RESERVED_SIZE_8195A)
#else
#if (SKB_PRE_ALLOCATE_RX==1)
#define MAX_RECVBUF_SZ MAX_SKB_BUF_SIZE //1650 //(RX_DMA_SIZE_8195A - RX_DMA_RESERVED_SIZE_8195A)
#else
#define MAX_RECVBUF_SZ (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
RXDESC_SIZE +\
(MAX_RX_PKT_LIMIT * 512) +\
SKB_RESERVED_FOR_SAFETY) // 0+32+24+512*4+0 = 2104
#endif
#endif
//DWORD 0
#define SET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value)
#define SET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 30, 1, __Value)
#define SET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 31, 1, __Value)
#define GET_RX_STATUS_DESC_PKT_LEN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14)
#define GET_RX_STATUS_DESC_CRC32_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1)
#define GET_RX_STATUS_DESC_ICV_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1)
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 4)
#define GET_RX_STATUS_DESC_SECURITY_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 20, 3)
#define GET_RX_STATUS_DESC_QOS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1)
#define GET_RX_STATUS_DESC_SHIFT_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 24, 2)
#define GET_RX_STATUS_DESC_PHY_STATUS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 26, 1)
#define GET_RX_STATUS_DESC_SWDEC_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 27, 1)
#define GET_RX_STATUS_DESC_LAST_SEG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 1)
#define GET_RX_STATUS_DESC_FIRST_SEG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 29, 1)
#define GET_RX_STATUS_DESC_EOR_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 30, 1)
#define GET_RX_STATUS_DESC_OWN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1)
//DWORD 1
#define GET_RX_STATUS_DESC_MACID_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
#define GET_RX_STATUS_DESC_TID_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
#define GET_RX_STATUS_DESC_AMSDU_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
#define GET_RX_STATUS_DESC_RXID_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 14, 1)
#define GET_RX_STATUS_DESC_PAGGR_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 15, 1)
#define GET_RX_STATUS_DESC_A1_FIT_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 16, 4)
#define GET_RX_STATUS_DESC_CHKERR_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 20, 1)
#define GET_RX_STATUS_DESC_IPVER_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
#define GET_RX_STATUS_DESC_IS_TCPUDP__8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
#define GET_RX_STATUS_DESC_CHK_VLD_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
#define GET_RX_STATUS_DESC_PAM_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 24, 1)
#define GET_RX_STATUS_DESC_PWR_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 25, 1)
#define GET_RX_STATUS_DESC_MORE_DATA_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 26, 1)
#define GET_RX_STATUS_DESC_MORE_FRAG_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 27, 1)
#define GET_RX_STATUS_DESC_TYPE_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 28, 2)
#define GET_RX_STATUS_DESC_MC_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 30, 1)
#define GET_RX_STATUS_DESC_BC_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 31, 1)
//DWORD 2
#define GET_RX_STATUS_DESC_SEQ_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 0, 12)
#define GET_RX_STATUS_DESC_FRAG_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 12, 4)
#define GET_RX_STATUS_DESC_RX_IS_QOS_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 16, 1)
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 18, 6)
#define GET_RX_STATUS_DESC_RPT_SEL_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 28, 1)
//DWORD 3
#define GET_RX_STATUS_DESC_RX_RATE_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 0, 7)
#define GET_RX_STATUS_DESC_HTC_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 10, 1)
#define GET_RX_STATUS_DESC_EOSP_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 11, 1)
#define GET_RX_STATUS_DESC_BSSID_FIT_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 12, 2)
#ifdef CONFIG_USB_RX_AGGREGATION
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 16, 8)
#endif
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 29, 1)
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 30, 1)
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 31, 1)
//DWORD 6
#define GET_RX_STATUS_DESC_SPLCP_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 0, 1)
#define GET_RX_STATUS_DESC_LDPC_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 1, 1)
#define GET_RX_STATUS_DESC_STBC_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 2, 1)
#define GET_RX_STATUS_DESC_BW_8812(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 4, 2)
//DWORD 5
#define GET_RX_STATUS_DESC_TSFL_8812(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8812(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
#define SET_RX_STATUS_DESC_BUFF_ADDR_8812(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
typedef struct rxreport_8723b
{
//DWORD 0
u32 pktlen:14;
u32 crc32:1;
u32 icverr:1;
u32 drvinfosize:4;
u32 security:3;
u32 qos:1;
u32 shift:2;
u32 physt:1;
u32 swdec:1;
u32 rsvd0028:2;
u32 eor:1;
u32 rsvd0031:1;
//DWORD 1
u32 macid:7;
u32 rsvd0407:1;
u32 tid:4;
u32 macid_vld:1;
u32 amsdu:1;
u32 rxid_match:1;
u32 paggr:1;
u32 a1fit:4;
u32 chkerr:1; //20
u32 rx_ipv:1;
u32 rx_is_tcp_udp:1;
u32 chk_vld:1; //23
u32 pam:1;
u32 pwr:1;
u32 md:1;
u32 mf:1;
u32 type:2;
u32 mc:1;
u32 bc:1;
//DWORD 2
u32 seq:12;
u32 frag:4;
u32 rx_is_qos:1;
u32 rsvd0817:1;
u32 wlanhd_iv_len:6;
u32 hwrsvd0824:4;
u32 c2h_ind:1;
u32 rsvd0829:2;
u32 fcs_ok:1;
//DWORD 3
u32 rx_rate:7;
u32 rsvd1207:3;
u32 htc:1;
u32 esop:1;
u32 bssid_fit:2;
u32 rsvd1214:2;
u32 dma_agg_num:8;
u32 rsvd1224:5;
u32 patternmatch:1;
u32 unicastwake:1;
u32 magicwake:1;
//DWORD 4
u32 splcp:1; //Ofdm sgi or cck_splcp
u32 ldpc:1;
u32 stbc:1;
u32 not_sounding:1;
u32 bw:2;
u32 rsvd1606:26;
//DWORD 5
u32 tsfl;
} RXREPORT, *PRXREPORT;
typedef struct phystatus_8723b
{
u32 rxgain_a:7;
u32 trsw_a:1;
u32 rxgain_b:7;
u32 trsw_b:1;
u32 chcorr_l:16;
u32 sigqualcck:8;
u32 cfo_a:8;
u32 cfo_b:8;
u32 chcorr_h:8;
u32 noisepwrdb_h:8;
u32 cfo_tail_a:8;
u32 cfo_tail_b:8;
u32 rsvd0824:8;
u32 rsvd1200:8;
u32 rxevm_a:8;
u32 rxevm_b:8;
u32 rxsnr_a:8;
u32 rxsnr_b:8;
u32 noisepwrdb_l:8;
u32 rsvd1616:8;
u32 postsnr_a:8;
u32 postsnr_b:8;
u32 csi_a:8;
u32 csi_b:8;
u32 targetcsi_a:8;
u32 targetcsi_b:8;
u32 sigevm:8;
u32 maxexpwr:8;
u32 exintflag:1;
u32 sgien:1;
u32 rxsc:2;
u32 idlelong:1;
u32 anttrainen:1;
u32 antselb:1;
u32 antsel:1;
} PHYSTATUS, *PPHYSTATUS;
s32 rtl8195a_init_recv_priv(PADAPTER padapter);
void rtl8195a_free_recv_priv(PADAPTER padapter);
void rtl8195a_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc);
void rtl8195a_query_rx_phy_status(union recv_frame *precvframe, u8 *pphy_status);
#endif

32
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_rf.h Normal file
View file

@ -0,0 +1,32 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8195A_RF_H__
#define __RTL8195A_RF_H__
int PHY_RF6052_Config8195A( IN PADAPTER Adapter );
VOID
PHY_RF6052SetBandwidth8195A(
IN PADAPTER Adapter,
IN CHANNEL_WIDTH Bandwidth);
#endif

345
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_spec.h Normal file
View file

@ -0,0 +1,345 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*******************************************************************************/
#ifndef __RTL8195A_SPEC_H__
#define __RTL8195A_SPEC_H__
#include <drv_conf.h>
#define HAL_NAV_UPPER_UNIT_8723B 128 // micro-second
//-----------------------------------------------------
//
// 0x0000h ~ 0x00FFh System Configuration
//
//-----------------------------------------------------
#define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038
#define REG_PAD_CTRL1_8723B 0x0064
#define REG_AFE_CTRL_4_8723B 0x0078
#define REG_HMEBOX_DBG_0_8723B 0x0088
#define REG_HMEBOX_DBG_1_8723B 0x008A
#define REG_HMEBOX_DBG_2_8723B 0x008C
#define REG_HMEBOX_DBG_3_8723B 0x008E
//-----------------------------------------------------
//
// 0x0100h ~ 0x01FFh MACTOP General Configuration
//
//-----------------------------------------------------
#define REG_C2HEVT_CMD_ID_8723B 0x01A0
#define REG_C2HEVT_CMD_LEN_8723B 0x01AE
#ifdef CONFIG_WOWLAN
#define REG_WOWLAN_WAKE_REASON 0x01C7
#endif
#define REG_HMEBOX_EXT0_8723B 0x01F0
#define REG_HMEBOX_EXT1_8723B 0x01F4
#define REG_HMEBOX_EXT2_8723B 0x01F8
#define REG_HMEBOX_EXT3_8723B 0x01FC
//-----------------------------------------------------
//
// 0x0200h ~ 0x027Fh TXDMA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0280h ~ 0x02FFh RXDMA Configuration
//
//-----------------------------------------------------
#define REG_RXDMA_MODE_CTRL_8723B 0x0290
//-----------------------------------------------------
//
// 0x0300h ~ 0x03FFh PCIe
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
#define REG_TXPKTBUF_BCNQ_BDNY_8195A 0x0424
#define REG_TXPKTBUF_MGQ_BDNY_8195A 0x0425
#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8195A 0x045D
#ifdef CONFIG_WOWLAN
#define REG_TXPKTBUF_IV_LOW 0x0484
#define REG_TXPKTBUF_IV_HIGH 0x0488
#endif
//-----------------------------------------------------
//
// 0x0500h ~ 0x05FFh EDCA Configuration
//
//-----------------------------------------------------
#define REG_SECONDARY_CCA_CTRL_8723B 0x0577
//-----------------------------------------------------
//
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
//============================================================
// SDIO Bus Specification
//============================================================
//-----------------------------------------------------
// SDIO CMD Address Mapping
//-----------------------------------------------------
//-----------------------------------------------------
// I/O bus domain (Host)
//-----------------------------------------------------
//-----------------------------------------------------
// SDIO register
//-----------------------------------------------------
#define SDIO_REG_HCPWM1_8723B 0x025 // HCI Current Power Mode 1
//============================================================================
// 8723 Regsiter Bit and Content definition
//============================================================================
//2 HSISR
// interrupt mask which needs to clear
#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
HSISR_SPS_OCP_INT |\
HSISR_RON_INT |\
HSISR_PDNINT |\
HSISR_GPIO9_INT)
//-----------------------------------------------------
//
// 0x0100h ~ 0x01FFh MACTOP General Configuration
//
//-----------------------------------------------------
#define RXDMA_AGG_MODE_EN BIT(1)
//-----------------------------------------------------
//
// 0x0200h ~ 0x027Fh TXDMA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0280h ~ 0x02FFh RXDMA Configuration
//
//-----------------------------------------------------
#ifdef CONFIG_WOWLAN
#define RXPKT_RELEASE_POLL BIT(16)
#define RXDMA_IDLE BIT(17)
#define RW_RELEASE_EN BIT(18)
#endif
//-----------------------------------------------------
//
// 0x0400h ~ 0x047Fh Protocol Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0500h ~ 0x05FFh EDCA Configuration
//
//-----------------------------------------------------
//-----------------------------------------------------
//
// 0x0600h ~ 0x07FFh WMAC Configuration
//
//-----------------------------------------------------
#endif
//====================================================
// EEPROM/Efuse PG Offset for 8195A
//====================================================
// 0x10 ~ 0x63 = TX power area.
#define EEPROM_TX_PWR_INX_8195A 0x20
#define EEPROM_ChannelPlan_8195A 0xC8
#define EEPROM_XTAL_8195A 0xC9
#define EEPROM_THERMAL_METER_8195A 0xCA
#define EEPROM_IQK_LCK_8195A 0xCB
#define EEPROM_2G_5G_PA_TYPE_8195A 0xCC
#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8195A 0xCD
#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8195A 0xCE
#define EEPROM_RF_BOARD_OPTION_8195A 0x131
#define EEPROM_FEATURE_OPTION_8195A 0x132
#define EEPROM_RF_BT_SETTING_8195A 0x133
#define EEPROM_VERSION_8195A 0x134
#define EEPROM_CustomID_8195A 0x135
#define EEPROM_TX_BBSWING_2G_8195A 0x136
#define EEPROM_TX_PWR_CAL_RATE_8195A 0x138
#define EEPROM_RF_ANTENNA_OPT_8195A 0x139
#define EEPROM_RFE_OPTION_8195A 0x13A
//RTL8723BU
#define EEPROM_MAC_ADDR_8723BU 0x107
#define EEPROM_VID_8723BU 0x100
#define EEPROM_PID_8723BU 0x102
#define EEPROM_PA_TYPE_8723BU 0xBC
#define EEPROM_LNA_TYPE_2G_8723BU 0xBD
//RTL8723BS
#define EEPROM_MAC_ADDR_8723BS 0x11A
#define EEPROM_MAC_ADDR_8195A 0x11A
#define EEPROM_Voltage_ADDR_8723B 0x8
#define EEPROM_TX_KFREE_8195A 0xEE
#define EEPROM_PACKAGE_TYPE_8195A 0xF8
//====================================================
// EEPROM/Efuse Value Type
//====================================================
#define EETYPE_TX_PWR 0x0
//====================================================
// EEPROM/Efuse Default Value
//====================================================
#define EEPROM_CID_DEFAULT 0x0
#define EEPROM_CID_DEFAULT_EXT 0xFF // Reserved for Realtek
#define EEPROM_CID_TOSHIBA 0x4
#define EEPROM_CID_CCX 0x10
#define EEPROM_CID_QMI 0x0D
#define EEPROM_CID_WHQL 0xFE
#define EEPROM_CHANNEL_PLAN_FCC 0x0
#define EEPROM_CHANNEL_PLAN_IC 0x1
#define EEPROM_CHANNEL_PLAN_ETSI 0x2
#define EEPROM_CHANNEL_PLAN_SPAIN 0x3
#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
#define EEPROM_CHANNEL_PLAN_MKK 0x5
#define EEPROM_CHANNEL_PLAN_MKK1 0x6
#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
#define EEPROM_CHANNEL_PLAN_TELEC 0x8
#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
#define EEPROM_CHANNEL_PLAN_NCC_TAIWAN 0xB
#define EEPROM_CHANNEL_PLAN_CHIAN 0XC
#define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO 0XD
#define EEPROM_CHANNEL_PLAN_KOREA 0xE
#define EEPROM_CHANNEL_PLAN_TURKEY 0xF
#define EEPROM_CHANNEL_PLAN_JAPAN 0x10
#define EEPROM_CHANNEL_PLAN_FCC_NO_DFS 0x11
#define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS 0x12
#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G 0x13
#define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS 0x14
#define EEPROM_USB_OPTIONAL1 0xE
#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
#define RTL_EEPROM_ID 0x8129
#define EEPROM_Default_TSSI 0x0
#define EEPROM_Default_BoardType 0x02
#define EEPROM_Default_ThermalMeter 0x12
#define EEPROM_Default_ThermalMeter_92SU 0x7
#define EEPROM_Default_ThermalMeter_88E 0x18
#define EEPROM_Default_ThermalMeter_8812 0x18
#define EEPROM_Default_ThermalMeter_8192E 0x1A
#define EEPROM_Default_ThermalMeter_8723B 0x18
#define EEPROM_Default_ThermalMeter_8195A 0x1A
#define EEPROM_Default_CrystalCap 0x0
#define EEPROM_Default_CrystalCap_8723B 0x20
#define EEPROM_Default_CrystalCap_8195A 0x20
#define EEPROM_Default_CrystalFreq 0x0
#define EEPROM_Default_TxPowerLevel_92C 0x22
#define EEPROM_Default_TxPowerLevel_2G 0x2C
#define EEPROM_Default_TxPowerLevel_5G 0x22
#define EEPROM_Default_TxPowerLevel 0x22
#define EEPROM_Default_HT40_2SDiff 0x0
#define EEPROM_Default_HT20_Diff 2
#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
#define EEPROM_Default_LegacyHTTxPowerDiff_92C 0x3
#define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4
#define EEPROM_Default_HT40_PwrMaxOffset 0
#define EEPROM_Default_HT20_PwrMaxOffset 0
#define EEPROM_Default_PID 0x1234
#define EEPROM_Default_VID 0x5678
#define EEPROM_Default_CustomerID 0xAB
#define EEPROM_Default_CustomerID_8188E 0x00
#define EEPROM_Default_SubCustomerID 0xCD
#define EEPROM_Default_Version 0
#define EEPROM_Default_externalPA_C9 0x00
#define EEPROM_Default_externalPA_CC 0xFF
#define EEPROM_Default_internalPA_SP3T_C9 0xAA
#define EEPROM_Default_internalPA_SP3T_CC 0xAF
#define EEPROM_Default_internalPA_SPDT_C9 0xAA
#ifdef CONFIG_PCI_HCI
#define EEPROM_Default_internalPA_SPDT_CC 0xA0
#else
#define EEPROM_Default_internalPA_SPDT_CC 0xFA
#endif
#define EEPROM_Default_PAType 0
#define EEPROM_Default_LNAType 0
//New EFUSE deafult value
#define EEPROM_DEFAULT_24G_CCK_INDEX 0x20
#define EEPROM_DEFAULT_24G_40M_INDEX 0x20
#define EEPROM_DEFAULT_24G_HT20_DIFF 0X00
#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X02
#define EEPROM_DEFAULT_5G_INDEX 0X2A
#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00
#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04
#define EEPROM_DEFAULT_DIFF 0XFE
#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F
#define EEPROM_DEFAULT_BOARD_OPTION 0x01 // Enable power by rate and power limit
#define EEPROM_DEFAULT_RFE_OPTION 0x04
#define EEPROM_DEFAULT_FEATURE_OPTION 0x00
#define EEPROM_DEFAULT_BT_OPTION 0x10
#define EEPROM_DEFAULT_TX_CALIBRATE_RATE 0x00
#ifdef CONFIG_USB_HCI
//should be renamed and moved to another file
typedef enum _BOARD_TYPE_8192CUSB{
BOARD_USB_DONGLE = 0, // USB dongle
BOARD_USB_High_PA = 1, // USB dongle with high power PA
BOARD_MINICARD = 2, // Minicard
BOARD_USB_SOLO = 3, // USB solo-Slim module
BOARD_USB_COMBO = 4, // USB Combo-Slim module
} BOARD_TYPE_8723BUSB, *PBOARD_TYPE_8723BUSB;
#endif
#if defined (CONFIG_PCI_HCI) || defined(CONFIG_LX_HCI)
#define RT_BCN_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER)
#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
#endif

30
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_sreset.h Normal file
View file

@ -0,0 +1,30 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _RTL8195A_SRESET_H_
#define _RTL8195A_SRESET_H_
#include <rtw_sreset.h>
#ifdef DBG_CONFIG_ERROR_DETECT
extern void rtl8723b_sreset_xmit_status_check(_adapter *padapter);
extern void rtl8723b_sreset_linked_status_check(_adapter *padapter);
#endif
#endif

473
USDK/component/common/drivers/wlan/realtek/src/hal/rtl8195a/rtl8195a_xmit.h Normal file
View file

@ -0,0 +1,473 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __RTL8195A_XMIT_H__
#define __RTL8195A_XMIT_H__
//
// Queue Select Value in TxDesc
//
#define QSLT_BK 0x2//0x01
#define QSLT_BE 0x0
#define QSLT_VI 0x5//0x4
#define QSLT_VO 0x7//0x6
#define QSLT_BEACON 0x10
#define QSLT_HIGH 0x11
#define QSLT_MGNT 0x12
#define QSLT_CMD 0x13
#define MAX_TID (15)
//OFFSET 0
#define OFFSET_SZ 0
#define OFFSET_SHT 16
#define BMC BIT(24)
#define LSG BIT(26)
#define FSG BIT(27)
#define OWN BIT(31)
//OFFSET 4
#define PKT_OFFSET_SZ 0
#define BK BIT(6)
#define QSEL_SHT 8
#define Rate_ID_SHT 16
#define NAVUSEHDR BIT(20)
#define PKT_OFFSET_SHT 26
#define HWPC BIT(31)
//OFFSET 8
#define AGG_EN BIT(29)
//OFFSET 12
#define SEQ_SHT 16
//OFFSET 16
#define QoS BIT(6)
#define HW_SEQ_EN BIT(7)
#define USERATE BIT(8)
#define DISDATAFB BIT(10)
#define DATA_SHORT BIT(24)
#define DATA_BW BIT(25)
//OFFSET 20
#define SGI BIT(6)
//
//defined for TX DESC Operation
//
typedef struct txdesc_8723b
{
// Offset 0
u32 pktlen:16;
u32 offset:8;
u32 bmc:1;
u32 htc:1;
u32 rsvd0026:1;
u32 rsvd0027:1;
u32 linip:1;
u32 noacm:1;
u32 gf:1;
u32 rsvd0031:1;
// Offset 4
u32 macid:7;
u32 rsvd0407:1;
u32 qsel:5;
u32 rdg_nav_ext:1;
u32 lsig_txop_en:1;
u32 pifs:1;
u32 rate_id:5;
u32 en_desc_id:1;
u32 sectype:2;
u32 pkt_offset:5; // unit: 8 bytes
u32 moredata:1;
u32 txop_ps_cap:1;
u32 txop_ps_mode:1;
// Offset 8
u32 p_aid:9;
u32 rsvd0809:1;
u32 cca_rts:2;
u32 agg_en:1;
u32 rdg_en:1;
u32 null_0:1;
u32 null_1:1;
u32 bk:1;
u32 morefrag:1;
u32 raw:1;
u32 spe_rpt:1;
u32 ampdu_density:3;
u32 bt_null:1;
u32 g_id:6;
u32 rsvd0830:2;
// Offset 12
u32 wheader_len:4;
u32 chk_en:1;
u32 early_rate:1;
u32 hw_ssn_sel:2;
u32 userate:1;
u32 disrtsfb:1;
u32 disdatafb:1;
u32 cts2self:1;
u32 rtsen:1;
u32 hw_rts_en:1;
u32 port_id:1;
u32 navusehdr:1;
u32 use_max_len:1;
u32 max_agg_num:5;
u32 ndpa:2;
u32 ampdu_max_time:8;
// Offset 16
u32 datarate:7;
u32 try_rate:1;
u32 data_ratefb_lmt:5;
u32 rts_ratefb_lmt:4;
u32 rty_lmt_en:1;
u32 data_rt_lmt:6;
u32 rtsrate:5;
u32 pcts_en:1;
u32 pcts_mask_idx:2;
// Offset 20
u32 data_sc:4;
u32 data_short:1;
u32 data_bw:2;
u32 data_ldpc:1;
u32 data_stbc:2;
u32 vcs_stbc:2;
u32 rts_short:1;
u32 rts_sc:4;
u32 rsvd2016:7;
u32 tx_ant:4;
u32 txpwr_offset:3;
u32 rsvd2031:1;
// Offset 24
u32 sw_define:12;
u32 mbssid:4;
u32 antsel_A:3;
u32 antsel_B:3;
u32 antsel_C:3;
u32 antsel_D:3;
u32 rsvd2428:4;
// Offset 28
u32 checksum:16;
u32 rsvd2816:8;
u32 usb_txagg_num:8;
// Offset 32
u32 rts_rc:6;
u32 bar_rty_th:2;
u32 data_rc:6;
u32 rsvd3214:1;
u32 en_hwseq:1;
u32 nextneadpage:8;
u32 tailpage:8;
// Offset 36
u32 padding_len:11;
u32 txbf_path:1;
u32 seq:12;
u32 final_data_rate:8;
}TXDESC_8723B, *PTXDESC_8723B;
#ifndef __INC_HAL8723BDESC_H
#define __INC_HAL8723BDESC_H
#define RX_STATUS_DESC_SIZE_8723B 24
#define RX_DRV_INFO_SIZE_UNIT_8723B 8
//DWORD 0
#define SET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value)
#define SET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 30, 1, __Value)
#define SET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 31, 1, __Value)
#define GET_RX_STATUS_DESC_PKT_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14)
#define GET_RX_STATUS_DESC_CRC32_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1)
#define GET_RX_STATUS_DESC_ICV_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1)
#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 4)
#define GET_RX_STATUS_DESC_SECURITY_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 20, 3)
#define GET_RX_STATUS_DESC_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1)
#define GET_RX_STATUS_DESC_SHIFT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 24, 2)
#define GET_RX_STATUS_DESC_PHY_STATUS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 26, 1)
#define GET_RX_STATUS_DESC_SWDEC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 27, 1)
#define GET_RX_STATUS_DESC_LAST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 1)
#define GET_RX_STATUS_DESC_FIRST_SEG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 29, 1)
#define GET_RX_STATUS_DESC_EOR_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 30, 1)
#define GET_RX_STATUS_DESC_OWN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1)
//DWORD 1
#define GET_RX_STATUS_DESC_MACID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7)
#define GET_RX_STATUS_DESC_TID_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4)
#define GET_RX_STATUS_DESC_AMSDU_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1)
#define GET_RX_STATUS_DESC_RXID_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 14, 1)
#define GET_RX_STATUS_DESC_PAGGR_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 15, 1)
#define GET_RX_STATUS_DESC_A1_FIT_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 16, 4)
#define GET_RX_STATUS_DESC_CHKERR_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 20, 1)
#define GET_RX_STATUS_DESC_IPVER_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1)
#define GET_RX_STATUS_DESC_IS_TCPUDP__8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1)
#define GET_RX_STATUS_DESC_CHK_VLD_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1)
#define GET_RX_STATUS_DESC_PAM_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 24, 1)
#define GET_RX_STATUS_DESC_PWR_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 25, 1)
#define GET_RX_STATUS_DESC_MORE_DATA_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 26, 1)
#define GET_RX_STATUS_DESC_MORE_FRAG_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 27, 1)
#define GET_RX_STATUS_DESC_TYPE_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 28, 2)
#define GET_RX_STATUS_DESC_MC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 30, 1)
#define GET_RX_STATUS_DESC_BC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 31, 1)
//DWORD 2
#define GET_RX_STATUS_DESC_SEQ_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 0, 12)
#define GET_RX_STATUS_DESC_FRAG_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 12, 4)
#define GET_RX_STATUS_DESC_RX_IS_QOS_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 16, 1)
#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 18, 6)
#define GET_RX_STATUS_DESC_RPT_SEL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 28, 1)
//DWORD 3
#define GET_RX_STATUS_DESC_RX_RATE_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 0, 7)
#define GET_RX_STATUS_DESC_HTC_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 10, 1)
#define GET_RX_STATUS_DESC_EOSP_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 11, 1)
#define GET_RX_STATUS_DESC_BSSID_FIT_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 12, 2)
#ifdef CONFIG_USB_RX_AGGREGATION
#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 16, 8)
#endif
#define GET_RX_STATUS_DESC_PATTERN_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 29, 1)
#define GET_RX_STATUS_DESC_UNICAST_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 30, 1)
#define GET_RX_STATUS_DESC_MAGIC_MATCH_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 31, 1)
//DWORD 6
#define GET_RX_STATUS_DESC_SPLCP_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 0, 1)
#define GET_RX_STATUS_DESC_LDPC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 1, 1)
#define GET_RX_STATUS_DESC_STBC_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 2, 1)
#define GET_RX_STATUS_DESC_BW_8723B(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 4, 2)
//DWORD 5
#define GET_RX_STATUS_DESC_TSFL_8723B(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32)
#define GET_RX_STATUS_DESC_BUFF_ADDR64_8723B(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32)
#define SET_RX_STATUS_DESC_BUFF_ADDR_8723B(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value)
// Dword 0
#define GET_TX_DESC_OWN_8723B(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
#define SET_TX_DESC_PKT_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
#define SET_TX_DESC_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
#define SET_TX_DESC_BMC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
#define SET_TX_DESC_HTC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
#define SET_TX_DESC_LAST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
#define SET_TX_DESC_FIRST_SEG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
#define SET_TX_DESC_LINIP_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
#define SET_TX_DESC_NO_ACM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
#define SET_TX_DESC_GF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
#define SET_TX_DESC_OWN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
// Dword 1
#define SET_TX_DESC_MACID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
#define SET_TX_DESC_QUEUE_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
#define SET_TX_DESC_RDG_NAV_EXT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
#define SET_TX_DESC_LSIG_TXOP_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
#define SET_TX_DESC_PIFS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
#define SET_TX_DESC_RATE_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
#define SET_TX_DESC_EN_DESC_ID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
#define SET_TX_DESC_SEC_TYPE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
#define SET_TX_DESC_PKT_OFFSET_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
// Dword 2
#define SET_TX_DESC_PAID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value)
#define SET_TX_DESC_CCA_RTS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
#define SET_TX_DESC_AGG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
#define SET_TX_DESC_RDG_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
#define SET_TX_DESC_AGG_BREAK_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
#define SET_TX_DESC_MORE_FRAG_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
#define SET_TX_DESC_RAW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
#define SET_TX_DESC_SPE_RPT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
#define SET_TX_DESC_AMPDU_DENSITY_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
#define SET_TX_DESC_BT_INT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
#define SET_TX_DESC_GID_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
// Dword 3
#define SET_TX_DESC_WHEADER_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
#define SET_TX_DESC_CHK_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
#define SET_TX_DESC_EARLY_MODE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
#define SET_TX_DESC_HWSEQ_SEL_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
#define SET_TX_DESC_USE_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
#define SET_TX_DESC_DISABLE_RTS_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
#define SET_TX_DESC_DISABLE_FB_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
#define SET_TX_DESC_CTS2SELF_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
#define SET_TX_DESC_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
#define SET_TX_DESC_HW_RTS_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
#define SET_TX_DESC_NAV_USE_HDR_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
#define SET_TX_DESC_USE_MAX_LEN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
#define SET_TX_DESC_MAX_AGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
#define SET_TX_DESC_NDPA_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
#define SET_TX_DESC_AMPDU_MAX_TIME_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
// Dword 4
#define SET_TX_DESC_TX_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
#define SET_TX_DESC_DATA_RETRY_LIMIT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
#define SET_TX_DESC_RTS_RATE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
// Dword 5
#define SET_TX_DESC_DATA_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
#define SET_TX_DESC_DATA_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
#define SET_TX_DESC_DATA_BW_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
#define SET_TX_DESC_DATA_LDPC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
#define SET_TX_DESC_DATA_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
#define SET_TX_DESC_CTROL_STBC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
#define SET_TX_DESC_RTS_SHORT_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
#define SET_TX_DESC_RTS_SC_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
// Dword 6
#define SET_TX_DESC_SW_DEFINE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
#define SET_TX_DESC_ANTSEL_A_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
#define SET_TX_DESC_ANTSEL_B_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
#define SET_TX_DESC_ANTSEL_C_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
#define SET_TX_DESC_ANTSEL_D_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
// Dword 7
#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)
#define SET_TX_DESC_TX_BUFFER_SIZE_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#else
#define SET_TX_DESC_TX_DESC_CHECKSUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
#endif
#define SET_TX_DESC_USB_TXAGG_NUM_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
#if(DEV_BUS_TYPE == RT_SDIO_INTERFACE)
#define SET_TX_DESC_SDIO_TXSEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
#endif
// Dword 8
#define SET_TX_DESC_HWSEQ_EN_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
// Dword 9
#define SET_TX_DESC_SEQ_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
// Dword 10
#define SET_TX_DESC_TX_BUFFER_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
// Dword 11
#define SET_TX_DESC_NEXT_DESC_ADDRESS_8723B(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
#define SET_EARLYMODE_PKTNUM_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
#define SET_EARLYMODE_LEN0_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
#define SET_EARLYMODE_LEN1_1_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
#define SET_EARLYMODE_LEN1_2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
#define SET_EARLYMODE_LEN2_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value)
#define SET_EARLYMODE_LEN3_8723B(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
#endif
//-----------------------------------------------------------
//
// Rate
//
//-----------------------------------------------------------
// CCK Rates, TxHT = 0
#define DESC8723B_RATE1M 0x00
#define DESC8723B_RATE2M 0x01
#define DESC8723B_RATE5_5M 0x02
#define DESC8723B_RATE11M 0x03
// OFDM Rates, TxHT = 0
#define DESC8723B_RATE6M 0x04
#define DESC8723B_RATE9M 0x05
#define DESC8723B_RATE12M 0x06
#define DESC8723B_RATE18M 0x07
#define DESC8723B_RATE24M 0x08
#define DESC8723B_RATE36M 0x09
#define DESC8723B_RATE48M 0x0a
#define DESC8723B_RATE54M 0x0b
// MCS Rates, TxHT = 1
#define DESC8723B_RATEMCS0 0x0c
#define DESC8723B_RATEMCS1 0x0d
#define DESC8723B_RATEMCS2 0x0e
#define DESC8723B_RATEMCS3 0x0f
#define DESC8723B_RATEMCS4 0x10
#define DESC8723B_RATEMCS5 0x11
#define DESC8723B_RATEMCS6 0x12
#define DESC8723B_RATEMCS7 0x13
#define DESC8723B_RATEMCS8 0x14
#define DESC8723B_RATEMCS9 0x15
#define DESC8723B_RATEMCS10 0x16
#define DESC8723B_RATEMCS11 0x17
#define DESC8723B_RATEMCS12 0x18
#define DESC8723B_RATEMCS13 0x19
#define DESC8723B_RATEMCS14 0x1a
#define DESC8723B_RATEMCS15 0x1b
#define DESC8723B_RATEVHTSS1MCS0 0x2c
#define DESC8723B_RATEVHTSS1MCS1 0x2d
#define DESC8723B_RATEVHTSS1MCS2 0x2e
#define DESC8723B_RATEVHTSS1MCS3 0x2f
#define DESC8723B_RATEVHTSS1MCS4 0x30
#define DESC8723B_RATEVHTSS1MCS5 0x31
#define DESC8723B_RATEVHTSS1MCS6 0x32
#define DESC8723B_RATEVHTSS1MCS7 0x33
#define DESC8723B_RATEVHTSS1MCS8 0x34
#define DESC8723B_RATEVHTSS1MCS9 0x35
#define DESC8723B_RATEVHTSS2MCS0 0x36
#define DESC8723B_RATEVHTSS2MCS1 0x37
#define DESC8723B_RATEVHTSS2MCS2 0x38
#define DESC8723B_RATEVHTSS2MCS3 0x39
#define DESC8723B_RATEVHTSS2MCS4 0x3a
#define DESC8723B_RATEVHTSS2MCS5 0x3b
#define DESC8723B_RATEVHTSS2MCS6 0x3c
#define DESC8723B_RATEVHTSS2MCS7 0x3d
#define DESC8723B_RATEVHTSS2MCS8 0x3e
#define DESC8723B_RATEVHTSS2MCS9 0x3f
#define RX_HAL_IS_CCK_RATE_8723B(pDesc)\
(GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE1M ||\
GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE2M ||\
GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE5_5M ||\
GET_RX_STATUS_DESC_RX_RATE_8723B(pDesc) == DESC8723B_RATE11M)
void rtl8195a_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem);
void rtl8195a_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame);
s32 rtl8195ab_init_xmit_priv(PADAPTER padapter);
void rtl8195ab_free_xmit_priv(PADAPTER padapter);
s32 rtl8195ab_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe);
s32 rtl8195ab_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe);
s32 rtl8195ab_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
void rtl8195ab_xmitframe_resume(_adapter *padapter);
u32 GetDmaTxbdIdx(u32 ff_hwaddr);
struct xmit_buf * rtl8195a_dequeue_xmitbuf(struct rtw_tx_ring *ring);
BOOLEAN FreeXimtBuf(struct xmit_buf *pxmitbuf);
u8 check_tx_desc_resource(_adapter *padapter, int prio);
#endif

493
USDK/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_intf.c Normal file
View file

@ -0,0 +1,493 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _GSPI_INTF_C_
#include <drv_types.h>
#ifdef CONFIG_GSPI_HCI
struct dvobj_priv *gspi_dvobj_init(void)
{
// int status = _FAIL;
struct dvobj_priv *dvobj = NULL;
PGSPI_DATA pgspi_data;
_func_enter_;
dvobj = (struct dvobj_priv*)rtw_zmalloc(sizeof(*dvobj));
if (NULL == dvobj) {
goto exit;
}
pgspi_data = &dvobj->intf_data;
rtw_mutex_init(&pgspi_data->spi_mutex);
//pgspi_data->block_transfer_len = 512; //512 blocks r/w is not required for GSPI interface
//pgspi_data->tx_block_mode = 0;
//pgspi_data->rx_block_mode = 0;
// status = _SUCCESS;
#if 0
free_dvobj:
if (status != _SUCCESS && dvobj) {
rtw_mfree((u8*)dvobj, sizeof(*dvobj));
dvobj = NULL;
}
#endif
exit:
_func_exit_;
return dvobj;
}
void gspi_dvobj_deinit(struct dvobj_priv *dvobj)
{
//TODO
// struct dvobj_priv *dvobj = spi_get_drvdata(spi);
_func_enter_;
//TODO
// spi_set_drvdata(spi, NULL);
if (dvobj) {
//TODO
// gspi_deinit(dvobj);
rtw_mutex_free(&dvobj->intf_data.spi_mutex);
rtw_mfree((u8*)dvobj, sizeof(*dvobj));
}
_func_exit_;
}
s32 gspi_dvobj_xmit_mgnt(_adapter * padapter, struct xmit_frame *pmgntframe)
{
s32 ret = _SUCCESS;
struct pkt_attrib *pattrib;
struct xmit_buf *pxmitbuf;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
u8 *pframe = NULL;
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("+rtw_xmit_mgnt()\n"));
pattrib = &pmgntframe->attrib;
pxmitbuf = pmgntframe->pxmitbuf;
pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
rtw_hal_update_txdesc(padapter, pmgntframe, pmgntframe->buf_addr);
pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz;
//pxmitbuf->pg_num = (pxmitbuf->len + 127)/128; // 128 is tx page size
//pxmitbuf->ptail = pmgntframe->buf_addr + pxmitbuf->len;
pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pmgntframe);
rtw_count_tx_stats(padapter, pmgntframe, pattrib->last_txcmdsz);
//RT_TRACE(_module_rtl871x_xmit_c_, _drv_always_, ("+rtw_xmit_mgnt(): type=%d\n", GetFrameSubType(pframe)));
if(GetFrameSubType(pframe)==WIFI_BEACON) //dump beacon directly
{
//When using dedicated xmit frame for issue bcn on ap mode
//free xmit frame for bcn reserved page on station mode - Alex Fang
#if USE_DEDICATED_BCN_TX
if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) {
rtw_free_xmitframe(pxmitpriv, pmgntframe);
pxmitbuf->priv_data = NULL;
}
rtw_write_port(padapter, ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr), pxmitbuf->len, pxmitbuf->pbuf);
if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
#else
rtw_free_xmitframe(pxmitpriv, pmgntframe);
pxmitbuf->priv_data = NULL;
rtw_xmit_xmitbuf(padapter, pxmitbuf);
#endif
}
else
{
rtw_free_xmitframe(pxmitpriv, pmgntframe);
pxmitbuf->priv_data = NULL;
rtw_xmit_xmitbuf(padapter, pxmitbuf);
}
if (ret != _SUCCESS)
rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("-rtw_xmit_mgnt\n"));
return ret;
}
//#include <skbuff.h>
s32 gspi_dvobj_xmit_data(_adapter *padapter, struct xmit_frame *pxmitframe)
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
_irqL irql;
s32 err;
#ifdef CONFIG_80211N_HT
if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
(pxmitframe->attrib.ether_type != 0x0806) &&
(pxmitframe->attrib.ether_type != 0x888e) &&
(pxmitframe->attrib.dhcp_pkt != 1))
{
if (padapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE)
rtw_issue_addbareq_cmd(padapter, pxmitframe);
}
#endif
#if USE_SKB_AS_XMITBUF
rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
#endif
rtw_enter_critical_bh(&pxmitpriv->lock, &irql);
#if 1 //FIX_XMITFRAME_FAULT, move from rtw_xmit().
#ifdef CONFIG_AP_MODE
if(xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE)
{
rtw_exit_critical_bh(&pxmitpriv->lock, &irql);
return 1;
}
#endif
#endif
err = rtw_xmitframe_enqueue(padapter, pxmitframe);
rtw_exit_critical_bh(&pxmitpriv->lock, &irql);
if (err != _SUCCESS) {
RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmit_data(): enqueue xmitframe fail\n"));
rtw_free_xmitframe(pxmitpriv, pxmitframe);
// Trick, make the statistics correct
pxmitpriv->tx_pkts--;
pxmitpriv->tx_drop++;
return _TRUE;
}
rtw_count_tx_stats(padapter, pxmitframe, pxmitframe->attrib.last_txcmdsz);
#ifdef CONFIG_CONCURRENT_MODE
if (padapter->adapter_type > PRIMARY_ADAPTER){
padapter = padapter->pbuddy_adapter;
}
#endif
rtw_wakeup_task(&padapter->xmitThread);
return _FALSE;
}
const struct host_ctrl_intf_ops hci_ops = {
gspi_dvobj_init,
gspi_dvobj_deinit,
NULL,
NULL
};
//TODO
#if 0
unsigned int oob_irq;
static irqreturn_t spi_interrupt_thread(int irq, void *data)
{
struct dvobj_priv *dvobj;
PGSPI_DATA pgspi_data;
dvobj = (struct dvobj_priv*)data;
pgspi_data = &dvobj->intf_data;
//spi_int_hdl(padapter);
if (pgspi_data->priv_wq)
queue_delayed_work(pgspi_data->priv_wq, &pgspi_data->irq_work, 0);
return IRQ_HANDLED;
}
static u8 gspi_alloc_irq(struct dvobj_priv *dvobj)
{
PGSPI_DATA pgspi_data;
struct spi_device *spi;
int err;
pgspi_data = &dvobj->intf_data;
spi = pgspi_data->func;
err = request_irq(oob_irq, spi_interrupt_thread,
IRQF_TRIGGER_FALLING,//IRQF_TRIGGER_HIGH;//|IRQF_ONESHOT,
DRV_NAME, dvobj);
//err = request_threaded_irq(oob_irq, NULL, spi_interrupt_thread,
// IRQF_TRIGGER_FALLING,
// DRV_NAME, dvobj);
if (err < 0) {
DBG_871X("Oops: can't allocate irq %d err:%d\n", oob_irq, err);
goto exit;
}
enable_irq_wake(oob_irq);
disable_irq(oob_irq);
exit:
return err?_FAIL:_SUCCESS;
}
#endif //#if 0
//TODO
#if 0
static void spi_irq_work(void *data)
{
struct delayed_work *dwork;
PGSPI_DATA pgspi;
struct dvobj_priv *dvobj;
dwork = container_of(data, struct delayed_work, work);
pgspi = container_of(dwork, GSPI_DATA, irq_work);
dvobj = spi_get_drvdata(pgspi->func);
if (!dvobj->if1) {
DBG_871X("%s if1 == NULL !!\n", __FUNCTION__);
return;
}
spi_int_hdl(dvobj->if1);
}
#endif //#if 0
//TODO
#if 0
static int rtw_gspi_suspend(struct spi_device *spi, pm_message_t mesg)
{
struct dvobj_priv *dvobj = spi_get_drvdata(spi);
PADAPTER padapter = (_adapter *)dvobj->if1;
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct net_device *pnetdev = padapter->pnetdev;
int ret = 0;
u32 start_time = rtw_get_current_time();
_func_enter_;
DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid);
pwrpriv->bInSuspend = _TRUE;
while (pwrpriv->bips_processing == _TRUE)
rtw_msleep_os(1);
if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved))
{
DBG_871X("%s bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n", __FUNCTION__
,padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved);
goto exit;
}
rtw_cancel_all_timer(padapter);
LeaveAllPowerSaveMode(padapter);
//padapter->net_closed = _TRUE;
//s1.
if(pnetdev)
{
netif_carrier_off(pnetdev);
rtw_netif_stop_queue(pnetdev);
}
#ifdef CONFIG_WOWLAN
padapter->pwrctrlpriv.bSupportWakeOnWlan=_TRUE;
#else
//s2.
//s2-1. issue rtw_disassoc_cmd to fw
disconnect_hdl(padapter, NULL);
//rtw_disassoc_cmd(padapter);
#endif
#ifdef CONFIG_LAYER2_ROAMING_RESUME
if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED) )
{
DBG_871X("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__,
pmlmepriv->cur_network.network.Ssid.Ssid,
MAC_ARG(pmlmepriv->cur_network.network.MacAddress),
pmlmepriv->cur_network.network.Ssid.SsidLength,
pmlmepriv->assoc_ssid.SsidLength);
pmlmepriv->to_roaming = 1;
}
#endif
//s2-2. indicate disconnect to os
rtw_indicate_disconnect(padapter);
//s2-3.
rtw_free_assoc_resources(padapter, 1);
//s2-4.
rtw_free_network_queue(padapter, _TRUE);
rtw_led_control(padapter, LED_CTL_POWER_OFF);
rtw_dev_unload(padapter);
if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY))
rtw_indicate_scan_done(padapter, 1);
if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING))
rtw_indicate_disconnect(padapter);
// interface deinit
gspi_deinit(dvobj);
RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("%s: deinit GSPI complete!\n", __FUNCTION__));
rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_OFF);
rtw_mdelay_os(1);
exit:
DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__
, ret, rtw_get_passing_time_ms(start_time));
_func_exit_;
return ret;
}
extern int pm_netdev_open(struct net_device *pnetdev,u8 bnormal);
int rtw_resume_process(_adapter *padapter)
{
struct net_device *pnetdev;
struct pwrctrl_priv *pwrpriv;
u8 is_pwrlock_hold_by_caller;
u8 is_directly_called_by_auto_resume;
int ret = 0;
u32 start_time = rtw_get_current_time();
_func_enter_;
DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid);
rtw_wifi_gpio_wlan_ctrl(WLAN_PWDN_ON);
rtw_mdelay_os(1);
rtw_set_chip_endian(adapter);
if (padapter) {
pnetdev = padapter->pnetdev;
pwrpriv = &padapter->pwrctrlpriv;
} else {
ret = -1;
goto exit;
}
// interface init
if (gspi_init(adapter_to_dvobj(padapter)) != _SUCCESS)
{
ret = -1;
RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: initialize SDIO Failed!!\n", __FUNCTION__));
goto exit;
}
rtw_hal_disable_interrupt(padapter);
if (gspi_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)
{
ret = -1;
RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: gspi_alloc_irq Failed!!\n", __FUNCTION__));
goto exit;
}
rtw_reset_drv_sw(padapter);
pwrpriv->bkeepfwalive = _FALSE;
DBG_871X("bkeepfwalive(%x)\n",pwrpriv->bkeepfwalive);
if(pm_netdev_open(pnetdev,_TRUE) != 0) {
ret = -1;
goto exit;
}
netif_device_attach(pnetdev);
netif_carrier_on(pnetdev);
if( padapter->pid[1]!=0) {
DBG_871X("pid[1]:%d\n",padapter->pid[1]);
rtw_signal_process(padapter->pid[1], SIGUSR2);
}
#ifdef CONFIG_LAYER2_ROAMING_RESUME
rtw_roaming(padapter, NULL);
#endif
#ifdef CONFIG_RESUME_IN_WORKQUEUE
rtw_unlock_suspend();
#endif //CONFIG_RESUME_IN_WORKQUEUE
pwrpriv->bInSuspend = _FALSE;
exit:
DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__
, ret, rtw_get_passing_time_ms(start_time));
_func_exit_;
return ret;
}
static int rtw_gspi_resume(struct spi_device *spi)
{
struct dvobj_priv *dvobj = spi_get_drvdata(spi);
PADAPTER padapter = (_adapter *)dvobj->if1;
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
int ret = 0;
DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid);
if(pwrpriv->bInternalAutoSuspend ){
ret = rtw_resume_process(padapter);
} else {
#ifdef CONFIG_RESUME_IN_WORKQUEUE
rtw_resume_in_workqueue(pwrpriv);
#elif defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
if(rtw_is_earlysuspend_registered(pwrpriv)) {
//jeff: bypass resume here, do in late_resume
pwrpriv->do_late_resume = _TRUE;
} else {
ret = rtw_resume_process(padapter);
}
#else // Normal resume process
ret = rtw_resume_process(padapter);
#endif //CONFIG_RESUME_IN_WORKQUEUE
}
DBG_871X("<======== %s return %d\n", __FUNCTION__, ret);
return ret;
}
static struct spi_driver rtw_spi_drv = {
.probe = rtw_drv_probe,
.remove = rtw_dev_remove,
.suspend = rtw_gspi_suspend,
.resume = rtw_gspi_resume,
.driver = {
.name = "wlan_spi",
.bus = &spi_bus_type,
.owner = THIS_MODULE,
}
};
#endif //#if 0
#endif

566
USDK/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_io.c Normal file
View file

@ -0,0 +1,566 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*******************************************************************************/
#define _GSPI_IO_C_
#include <drv_types.h>
#ifdef CONFIG_GSPI_HCI
u8 spi_read8(struct dvobj_priv *pdvobj, u32 addr, s32 *err);
u16 spi_read16(struct dvobj_priv *pdvobj, u32 addr, s32 *err);
u32 spi_read32(struct dvobj_priv *pdvobj, u32 addr, s32 *err);
s32 spi_write8(struct dvobj_priv *pdvobj, u32 addr, u8 buf, s32 *err);
s32 spi_write16(struct dvobj_priv *pdvobj, u32 addr, u16 buf, s32 *err);
s32 spi_write32(struct dvobj_priv *pdvobj, u32 addr, u32 buf, s32 *err);
static u32 rtw_spi_transfer(
struct dvobj_priv *pdvobj,
bool pool,
u8* buf,
u32 buf_len)
{
_mutex *spi_mutex;
u32 ret_value = _SUCCESS;
spi_mutex = &(pdvobj->intf_data.spi_mutex);
rtw_enter_critical_mutex(spi_mutex, NULL);
if(!WLAN_BSP_Transfer(buf, buf_len))
ret_value = _FAIL;
rtw_exit_critical_mutex(spi_mutex, NULL);
return ret_value;
}
static int addr_convert(u32 addr)
{
u32 domain_id = 0 ;
u32 temp_addr = addr&0xffff0000;
if (temp_addr == 0 ) {
domain_id = WLAN_IOREG_DOMAIN;
return domain_id;
}
switch (temp_addr) {
case WLAN_LOCAL_OFFSET:
domain_id = SPI_LOCAL_DOMAIN;
break;
case WLAN_IOREG_OFFSET:
domain_id = WLAN_IOREG_DOMAIN;
break;
case FW_FIFO_OFFSET:
domain_id = FW_FIFO_DOMAIN;
break;
case TX_HIQ_OFFSET:
domain_id = TX_HIQ_DOMAIN;
break;
case TX_MIQ_OFFSET:
domain_id = TX_MIQ_DOMAIN;
break;
case TX_LOQ_OFFSET:
domain_id = TX_LOQ_DOMAIN;
break;
case RX_RXOFF_OFFSET:
domain_id = RX_RXFIFO_DOMAIN;
break;
default:
break;
}
return domain_id;
}
/*
* Description:
* Translate sdio fifo address to Domain ID in each WLAN FIFO
*/
static u32 hwaddr2txfifo(u32 addr)
{
u32 fifo_domain_id;
switch (addr)
{
case WLAN_TX_HIQ_DEVICE_ID:
fifo_domain_id = TX_HIQ_DOMAIN;
break;
case WLAN_TX_MIQ_DEVICE_ID:
fifo_domain_id = TX_MIQ_DOMAIN;
break;
case WLAN_TX_LOQ_DEVICE_ID:
fifo_domain_id = TX_LOQ_DOMAIN;
break;
default:
fifo_domain_id = TX_LOQ_DOMAIN;
break;
}
return fifo_domain_id;
}
static u32 buf_endian_reverse(u32 src)
{
return (((src&0x000000ff)<<24)|((src&0x0000ff00)<<8)|
((src&0x00ff0000)>>8)|((src&0xff000000)>>24));
}
//
// Description:
// Query SDIO Local register to query current the number of Free TxPacketBuffer page.
//
// Assumption:
// 1. Running at PASSIVE_LEVEL
// 2. RT_TX_SPINLOCK is NOT acquired.
//
// Created by Roger, 2011.01.28.
//
#ifdef CONFIG_RTL8188F
u8 spi_query_status_info(struct dvobj_priv *pdvobj)
{
pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX] = spi_read8(pdvobj, LOCAL_REG_FREE_TXPG, NULL);
pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX] =spi_read8(pdvobj, LOCAL_REG_FREE_TXPG+2, NULL);
pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX] = spi_read8(pdvobj, LOCAL_REG_FREE_TXPG+4, NULL);
pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] = spi_read8(pdvobj, LOCAL_REG_FREE_TXPG+6, NULL);
RT_TRACE(_module_hci_ops_c_, _drv_notice_,
("%s: Free page for HIQ(%x),MIDQ(%x),LOWQ(%x),PUBQ(%x)\n",
__FUNCTION__,
pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]));
//_exit_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql);
return _TRUE;
}
#else
u8 spi_query_status_info(struct dvobj_priv *pdvobj)
{
u32 NumOfFreePage;
NumOfFreePage = spi_read32(pdvobj, LOCAL_REG_FREE_TXPG, NULL);
// _enter_critical_bh(&pdvobj->SdioTxFIFOFreePageLock, &irql);
rtw_memcpy(pdvobj->SdioTxFIFOFreePage, &NumOfFreePage, 4);
RT_TRACE(_module_hci_ops_c_, _drv_notice_,
("%s: Free page for HIQ(%x),MIDQ(%x),LOWQ(%x),PUBQ(%x)\n",
__FUNCTION__,
pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]));
// _exit_critical_bh(&pdvobj->SdioTxFIFOFreePageLock, &irql);
return _TRUE;
}
#endif
static void spi_get_status_info(struct dvobj_priv *pdvobj, unsigned char *status)
{
#ifdef CONFIG_MEMORY_ACCESS_ALIGNED
u32 local_status[2];
u8 *pstatus = (u8*)(&local_status[0]);
memcpy(pstatus, status, GSPI_STATUS_LEN);
#else
u8 *pstatus = status;
#endif
#ifdef CONFIG_RTL8188F
pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] = GET_STATUS_PUB_PAGE_NUM(pstatus)*2;
#else
pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] = GET_STATUS_PUB_PAGE_NUM(pstatus);
#endif
pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX] = GET_STATUS_HI_PAGE_NUM(pstatus);
pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX] = GET_STATUS_MID_PAGE_NUM(pstatus);
pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX] = GET_STATUS_LOW_PAGE_NUM(pstatus);
RT_TRACE(_module_hci_ops_c_, _drv_dump_,
("%s: Free page for HIQ(%x),MIDQ(%x),LOWQ(%x),PUBQ(%x)\n",
__FUNCTION__,
pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]));
}
static int spi_read_write_reg(struct dvobj_priv *pdvobj, int write_flag, u32 addr, char * buf, int len, u32 eddien)
{
int fun = 1, domain_id = 0x0; //LOCAL
unsigned int cmd = 0 ;
int byte_en = 0 ;//,i = 0 ;
int ret = 1;
unsigned char status[8] = {0};
unsigned int data_tmp = 0;
u32 force_bigendian = eddien;
u32 spi_buf[4] = {0};
bool polled = TRUE;
if (len!=1 && len!=2 && len != 4) {
return -1;
}
domain_id = addr_convert(addr);
addr &= 0x7fff;
len &= 0xff;
if (write_flag) //write register
{
int remainder = addr % 4;
u32 val32 = *(u32 *)buf;
switch(len) {
case 1:
byte_en = (0x1 << remainder);
data_tmp = (val32& 0xff)<< (remainder*8);
break;
case 2:
byte_en = (0x3 << remainder);
data_tmp = (val32 & 0xffff)<< (remainder*8);
break;
case 4:
byte_en = 0xf;
data_tmp = val32 & 0xffffffff;
break;
default:
byte_en = 0xf;
data_tmp = val32 & 0xffffffff;
break;
}
}
else //read register
{
switch(len) {
case 1:
byte_en = 0x1;
break;
case 2:
byte_en = 0x3;
break;
case 4:
byte_en = 0xf;
break;
default:
byte_en = 0xf;
break;
}
if(domain_id == SPI_LOCAL_DOMAIN)
byte_en = 0;
}
//addr = 0xF0 4byte: 0x2800f00f
REG_LEN_FORMAT(&cmd, byte_en);
REG_ADDR_FORMAT(&cmd, (addr&0xfffffffc));
REG_DOMAIN_ID_FORMAT(&cmd, domain_id);
REG_FUN_FORMAT(&cmd, fun);
REG_RW_FORMAT(&cmd, write_flag);
if (force_bigendian) {
cmd = buf_endian_reverse(cmd);
}
if (!write_flag && (domain_id!= RX_RXFIFO_DOMAIN)) {
u32 read_data = 0;
rtw_memset(spi_buf, 0x00, sizeof(spi_buf));
spi_buf[0] = cmd;
spi_buf[1] = 0;
spi_buf[2] = 0;
spi_buf[3] = 0;
rtw_spi_transfer(pdvobj, polled, (u8*)spi_buf, sizeof(spi_buf));
rtw_memcpy(status, (u8 *) &spi_buf[1], sizeof(status));
read_data = EF4Byte(spi_buf[3]);
//add for 8810
#ifdef CONFIG_BIG_ENDIAN
if (!force_bigendian)
read_data = buf_endian_reverse(read_data);
#else
if (force_bigendian)
read_data = buf_endian_reverse(read_data);
#endif
*(u32*)buf = read_data;
} else if (write_flag ) {
#ifdef CONFIG_BIG_ENDIAN
if (!force_bigendian)
data_tmp = buf_endian_reverse(data_tmp);
#else
if (force_bigendian)
data_tmp = buf_endian_reverse(data_tmp);
#endif
spi_buf[0] = cmd;
spi_buf[1] = data_tmp;
spi_buf[2] = 0;
spi_buf[3] = 0;
rtw_spi_transfer(pdvobj, polled, (u8*)spi_buf, sizeof(spi_buf));
rtw_memcpy(status, (u8 *) &spi_buf[2], sizeof(status));
}
spi_get_status_info(pdvobj, (unsigned char*)status);
return ret;
}
static int spi_io_priv(struct dvobj_priv *pdvobj)
{
//struct dvobj_priv *pdvobj = &Adapter->dvobjpriv;
return _SUCCESS;
}
static int spi_write8_endian(struct dvobj_priv *pdvobj, u32 addr, u32 buf, u32 big)
{
return spi_read_write_reg(pdvobj,1,addr,(char *)&buf,1, big);
}
u8 spi_read8(struct dvobj_priv *pdvobj, u32 addr, s32 *err)
{
u32 ret = 0;
int val32 = 0 , remainder = 0 ;
s32 _err = 0;
_err = spi_read_write_reg(pdvobj,0,addr&0xFFFFFFFC,(char *)&ret,4,0);
remainder = addr % 4;
val32 = ret;
val32 = (val32& (0xff<< (remainder<<3)))>>(remainder<<3);
if (err)
*err = _err;
return (u8)val32;
}
u16 spi_read16(struct dvobj_priv *pdvobj, u32 addr, s32 *err)
{
u32 ret = 0;
int val32 = 0 , remainder = 0 ;
s32 _err = 0;
_err = spi_read_write_reg(pdvobj,0,addr&0xFFFFFFFC,(char *)&ret,4,0);
remainder = addr % 4;
val32 = ret;
val32 = (val32& (0xffff<< (remainder<<3)))>>(remainder<<3);
if (err)
*err = _err;
return (u16)val32;
}
u32 spi_read32(struct dvobj_priv *pdvobj, u32 addr, s32 *err)
{
u32 ret = 0;
s32 _err = 0;
_err = spi_read_write_reg(pdvobj,0,addr&0xFFFFFFFC,(char *)&ret,4,0);
if (err)
*err = _err;
return ret;
}
s32 spi_write8(struct dvobj_priv *pdvobj, u32 addr, u8 buf, s32 *err)
{
int ret = 0;
ret = spi_read_write_reg(pdvobj,1,addr,(char *)&buf,1,0);
if (err)
*err = ret;
return ret;
}
s32 spi_write16(struct dvobj_priv *pdvobj, u32 addr, u16 buf, s32 *err)
{
int ret = 0;
ret = spi_read_write_reg(pdvobj,1,addr,(char *)&buf,2,0);
if (err)
*err = ret;
return ret;
}
s32 spi_write32(struct dvobj_priv *pdvobj, u32 addr, u32 buf, s32 *err)
{
int ret = 0;
ret = spi_read_write_reg(pdvobj, 1,addr,(char *)&buf,4,0);
if (err)
*err = ret;
return ret;
}
static int spi_read_rx_fifo(struct dvobj_priv *pdvobj, u32 addr, u8 *buf, u32 len, struct fifo_more_data *pmore_data)
{
int fun = 1, domain_id = RX_RXFIFO_DOMAIN;
unsigned int cmd = 0;
unsigned char *status = buf + len;
u8 *spi_buf = (u8 *) (buf - GSPI_CMD_LEN);
int spi_buf_len = 0;
bool polled = TRUE;
bool use_alloc = FALSE;
u32 max_skb_len = 0;
#ifndef CONFIG_DONT_CARE_TP
max_skb_len = MAX_SKB_BUF_SIZE;
#else
max_skb_len = MAX_RX_SKB_BUF_SIZE;
#endif
if(((GSPI_CMD_LEN + len + GSPI_STATUS_LEN) > max_skb_len) || (!buf)) {
#if !defined(CONFIG_MP_INCLUDED) || !defined(CONFIG_MP_IWPRIV_SUPPORT) // Cloud 2013/09/06
DBG_871X("data len=%d, MAX_SKB_BUF_SIZE(%d) is not enough, change to dynamic alloc\n", len, max_skb_len);
#endif
use_alloc = TRUE;
spi_buf_len = GSPI_CMD_LEN + len + GSPI_STATUS_LEN;
spi_buf = rtw_malloc(spi_buf_len);
if(spi_buf == NULL) {
DBG_871X("Failed to alloc %d bytes\n", len);
return _FAIL;
}
else {
buf = spi_buf + GSPI_CMD_LEN;
status = spi_buf + GSPI_CMD_LEN + len;
}
}
FIFO_LEN_FORMAT(&cmd, len); //TX Agg len
FIFO_DOMAIN_ID_FORMAT(&cmd, domain_id);
FIFO_FUN_FORMAT(&cmd, fun);
FIFO_RW_FORMAT(&cmd, 0); //read
rtw_memset(status, 0x00, GSPI_STATUS_LEN);
rtw_memset(buf, 0x0, len);
#ifdef CONFIG_MEMORY_ACCESS_ALIGNED
memcpy(spi_buf, (u8 *)&cmd, sizeof(int));
#else
*((u32 *) spi_buf) = cmd;
#endif
rtw_spi_transfer(pdvobj, polled, (u8 *) spi_buf, GSPI_CMD_LEN + len + GSPI_STATUS_LEN);
spi_get_status_info(pdvobj, status);
pmore_data->more_data = GET_STATUS_HISR_LOW8BIT(status) & BIT(0);
pmore_data->len = GET_STATUS_RX_LENGTH(status);
if(use_alloc) {
//Drop the data
rtw_mfree(spi_buf, spi_buf_len);
return _FAIL;
}
return _SUCCESS;
}
static int spi_write_tx_fifo(struct dvobj_priv *pdvobj, u32 addr, u8 *buf, u32 len)
{
int fun = 1; //TX_HIQ_FIFO
unsigned int cmd = 0;
unsigned char *status = buf + len;
u8 *spi_buf = (u8 *) (buf - GSPI_CMD_LEN);
u32 page_num = 0;
u32 wait_num = 100;
bool polled = TRUE;
u32 fifo = 0;
_func_enter_;
fifo = hwaddr2txfifo(addr);
spi_query_status_info(pdvobj);
if (fifo == TX_HIQ_DOMAIN)
page_num = pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX];
else if (fifo == TX_LOQ_DOMAIN)
page_num = pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX];
else
page_num = pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX];
while (page_num + pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] < 15) {
DBG_871X("Oops: spi_write_tx_fifo(): page_num is %d, padapter->pub_page is %d, wait_num is %d",
page_num, pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX], wait_num);
rtw_msleep_os(1);
//rtw_udelay_os(20);
spi_read32(pdvobj, 0x608, NULL);
if (fifo == TX_HIQ_DOMAIN)
page_num = pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX];
else if (fifo == TX_LOQ_DOMAIN)
page_num = pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX];
else
page_num = pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX];
if (wait_num <= 2) {
DBG_871X("%s(): wait_num is <= 2 drop", __FUNCTION__);
return _FAIL;
}
wait_num --;
}
FIFO_LEN_FORMAT(&cmd, len); //TX Agg len
FIFO_DOMAIN_ID_FORMAT(&cmd, fifo);
FIFO_FUN_FORMAT(&cmd, fun);
FIFO_RW_FORMAT(&cmd, (unsigned int) 1); //write
//DBG_871X("%s(): len = %d\n", __FUNCTION__, len);
//RT_PRINT_DATA(_module_hal_xmit_c_, _drv_always_, "Tx:\n", buf, GSPI_CMD_LEN + len);
rtw_memset(status, 0x00, GSPI_STATUS_LEN);
#ifdef CONFIG_MEMORY_ACCESS_ALIGNED
memcpy(spi_buf, (u8 *)&cmd, sizeof(int));
#else
*((u32 *) spi_buf) = cmd;
#endif
rtw_spi_transfer(pdvobj, polled, (u8 *) spi_buf, GSPI_CMD_LEN + len + GSPI_STATUS_LEN);
spi_get_status_info(pdvobj, status);
_func_exit_;
return _SUCCESS;
}
void spi_set_intf_ops(struct _io_ops *pops)
{
pops->init_io_priv = &spi_io_priv;
pops->write8_endian = &spi_write8_endian;
pops->_read8 = &spi_read8;
pops->_read16 = &spi_read16;
pops->_read32 = &spi_read32;
pops->_write8 = &spi_write8;
pops->_write16 = &spi_write16;
pops->_write32 = &spi_write32;
pops->read_rx_fifo = &spi_read_rx_fifo;
pops->write_tx_fifo = &spi_write_tx_fifo;
}
#endif

236
USDK/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_isr.c Normal file
View file

@ -0,0 +1,236 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
******************************************************************************/
#define _GSPI_ISR_C_
#include <drv_types.h>
#ifdef CONFIG_GSPI_HCI
extern struct recv_buf* rtw_recv_rxfifo(_adapter * padapter, u32 size, struct fifo_more_data* more_data);
u8 spi_read8(struct dvobj_priv *pdvobj, u32 addr, s32 *err);
u16 spi_read16(struct dvobj_priv *pdvobj, u32 addr, s32 *err);
u32 spi_read32(struct dvobj_priv *pdvobj, u32 addr, s32 *err);
s32 spi_write8(struct dvobj_priv *pdvobj, u32 addr, u8 buf, s32 *err);
s32 spi_write16(struct dvobj_priv *pdvobj, u32 addr, u16 buf, s32 *err);
s32 spi_write32(struct dvobj_priv *pdvobj, u32 addr, u32 buf, s32 *err);
void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr)
{
struct dvobj_priv *pdvobj = padapter->dvobj;
#ifdef CONFIG_LPS_LCLK
if (sdio_hisr & HCI_HISR_CPWM1)
{
struct reportpwrstate_parm report;
report.state = spi_read8(pdvobj, LOCAL_REG_HCPWM1, NULL);
if(report.state == 0xEA)
report.state = PS_STATE_S0;
else
report.state = PS_STATE_S2;
cpwm_int_hdl(padapter, &report);
}
#endif
if (sdio_hisr & HCI_HISR_TXERR)
{
u32 status;
status = rtw_read32(padapter, REG_TXDMA_STATUS);
rtw_write32(padapter, REG_TXDMA_STATUS, status);
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, status));
}
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
if (sdio_hisr & HCI_HISR_BCNERLY_INT)
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
if (sdio_hisr & (HCI_HISR_TXBCNOK|HCI_HISR_TXBCNERR))
#endif
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
#if 0 //for debug
if (sdio_hisr & SDIO_HISR_BCNERLY_INT)
DBG_8192C("%s: SDIO_HISR_BCNERLY_INT\n", __func__);
if (sdio_hisr & SDIO_HISR_TXBCNOK)
DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__);
if (sdio_hisr & SDIO_HISR_TXBCNERR) {
u1Byte v422, v550, v419;
v422 = rtw_read8(padapter, 0x422);
v419 = rtw_read8(padapter, 0x419);
v550 = rtw_read8(padapter, 0x550);
DBG_8192C("%s: SDIO_HISR_TXBCNERR 422=%02x, 419=%02x, 550=%02x\n", __func__, v422, v419, v550);
}
#endif
if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
{
//send_beacon(padapter);
if(pmlmepriv->update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter);
}
}
#if 0//def CONFIG_CONCURRENT_MODE
if(check_buddy_fwstate(padapter, WIFI_AP_STATE))
{
//send_beacon(padapter);
if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter->pbuddy_adapter);
}
}
#endif
}
#endif //CONFIG_INTERRUPT_BASED_TXBCN
if (sdio_hisr & HCI_HISR_C2HCMD)
{
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: C2H Command\n", __func__));
//TODO
// rtw_c2h_wk_cmd(padapter);
}
if (sdio_hisr & HCI_HISR_RX_REQUEST)// || sdio_hisr & SPI_HISR_RXFOVW)
{
struct recv_buf *precvbuf;
struct fifo_more_data more_data = {0};
//RT_TRACE(_module_hci_ops_c_,_drv_info_, ("%s: RX Request, size=%d\n", __func__, pdvobj->SdioRxFIFOSize));
sdio_hisr ^= HCI_HISR_RX_REQUEST;
do {
more_data.more_data = 0;
more_data.len = 0;
if (pdvobj->SdioRxFIFOSize == 0)
{
u16 val = 0;
s32 ret;
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s, %d, read RXFIFOsize again size=%d\n", __FUNCTION__, __LINE__, pdvobj->SdioRxFIFOSize));
val = spi_read16(pdvobj, LOCAL_REG_RX0_REQ_LEN_1_BYTE, &ret);
if (!ret) {
pdvobj->SdioRxFIFOSize = val;
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: RX_REQUEST, read RXFIFOsize again size=%d\n", __func__, pdvobj->SdioRxFIFOSize));
} else {
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: RX_REQUEST, read RXFIFOsize ERROR!!\n", __func__));
}
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s, %d, read RXFIFOsize again size=%d\n", __FUNCTION__, __LINE__, pdvobj->SdioRxFIFOSize));
}
if (pdvobj->SdioRxFIFOSize != 0)
{
#ifdef RTL8723A_SDIO_LOOPBACK
sd_recv_loopback(padapter, pdvobj->SdioRxFIFOSize);
#else
if (sdio_hisr & HCI_HISR_RXFOVW)
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s RXFOVW RX\n", __func__));
precvbuf = rtw_recv_rxfifo(padapter, pdvobj->SdioRxFIFOSize, &more_data);
if (precvbuf)
rtw_rxhandler(padapter, precvbuf);
if (more_data.more_data) {
pdvobj->SdioRxFIFOSize = more_data.len;
} else {
pdvobj->SdioRxFIFOSize = 0;
}
#endif
//If Rx_request ISR is set, execute receive tasklet (sdio_hisr & SPI_HISR_RX_REQUEST)
#if defined(CONFIG_ISR_THREAD_MODE_INTERRUPT) && defined(CONFIG_RECV_TASKLET_THREAD)
rtw_wakeup_task(&padapter->recvtasklet_thread);
#endif
}
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
{
//Prevent BCN update not realtime in ap mode - Alex Fang
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
if((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) && (pmlmepriv->update_bcn == _TRUE))
break;
}
#endif
} while (more_data.more_data);
#ifdef PLATFORM_LINUX
#ifdef CONFIG_GSPI_HCI
tasklet_schedule(&padapter->recvpriv.recv_tasklet);
#endif
#endif
}
}
void spi_int_hdl(PADAPTER padapter)
{
struct dvobj_priv *pdvobj = padapter->dvobj;
u32 sdio_hisr = 0;
s32 ret;
if ((padapter->bDriverStopped == _TRUE) ||
(padapter->bSurpriseRemoved == _TRUE))
return;
sdio_hisr = spi_read32(pdvobj, LOCAL_REG_HISR, &ret);
if (!ret) {
RT_TRACE(_module_hci_ops_c_, _drv_err_, ("%s: read SDIO_REG_HISR FAIL!!\n", __func__));
return;
}
pdvobj->SdioRxFIFOSize = spi_read16(pdvobj, LOCAL_REG_RX0_REQ_LEN_1_BYTE, &ret);
if (!ret) {
RT_TRACE(_module_hci_ops_c_, _drv_err_, ("%s: read SPI_REG_RX0_REQ_LEN FAIL!!\n", __func__));
return;
}
if (sdio_hisr & pdvobj->sdio_himr)
{
u32 v32;
sdio_hisr &= pdvobj->sdio_himr;
// clear HISR
v32 = sdio_hisr & MASK_SPI_HISR_CLEAR;
if (v32) {
spi_write32(pdvobj, LOCAL_REG_HISR, v32, &ret);
}
spi_int_dpc(padapter, sdio_hisr);
} else {
RT_TRACE(_module_hci_ops_c_, _drv_err_,
("%s: HISR(0x%08x) and HIMR(0x%08x) not match!\n",
__FUNCTION__, sdio_hisr, pdvobj->sdio_himr));
if(sdio_hisr)
spi_write32(pdvobj, LOCAL_REG_HISR, sdio_hisr, &ret);
}
}
#endif

257
USDK/component/common/drivers/wlan/realtek/src/hci/gspi/gspi_spec.h Normal file
View file

@ -0,0 +1,257 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*******************************************************************************/
#ifndef __GSPI_SPEC_H__
#define __GSPI_SPEC_H__
#define SPI_LOCAL_DOMAIN 0x0
#define WLAN_IOREG_DOMAIN 0x8
#define FW_FIFO_DOMAIN 0x4
#define TX_HIQ_DOMAIN 0xc
#define TX_MIQ_DOMAIN 0xd
#define TX_LOQ_DOMAIN 0xe
#define RX_RXFIFO_DOMAIN 0x1f
//IO Bus domain address mapping
#define DEFUALT_OFFSET 0x0
#define LOCAL_OFFSET 0x10250000
#define SPI_LOCAL_OFFSET 0x10250000
#define WLAN_IOREG_OFFSET 0x10260000
#define FW_FIFO_OFFSET 0x10270000
#define TX_HIQ_OFFSET 0x10310000
#define TX_MIQ_OFFSET 0x1032000
#define TX_LOQ_OFFSET 0x10330000
#define RX_RXOFF_OFFSET 0x10340000
#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13]
#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13]
#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13]
#define WLAN_TX_EXQ_DEVICE_ID 3 // 0b[16], 011b[15:13]
#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13]
#define WLAN_IOREG_DEVICE_ID 8 // 1b[16]
//SPI Tx Free Page Index
#define HI_QUEUE_IDX 0
#define MID_QUEUE_IDX 1
#define LOW_QUEUE_IDX 2
#define PUBLIC_QUEUE_IDX 3
#define MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ
#define MAX_RX_QUEUE 1
//SPI Local registers
#ifdef CONFIG_RTL8188F
#define SPI_REG_TX_CTRL 0x0000 // SPI Tx Control
#define SPI_REG_STATUS_RECOVERY 0x0004
#define SPI_REG_INT_TIMEOUT 0x0006
#define SPI_REG_HIMR 0x0014 // SPI Host Interrupt Mask
#define SPI_REG_HISR 0x0018 // SPI Host Interrupt Service Routine
#define SPI_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length
#define SPI_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page
#define SPI_REG_HTSFR_INFO 0x0030 // HTSF Informaion
#define SPI_REG_HCPWM1 0x0038 // HCI Current Power Mode 1
#define SPI_REG_HCPWM2 0x003A // HCI Current Power Mode 2
#define SPI_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 need check for 8188f???
#define SPI_REG_HPS_CLKR 0x0084 // HCI Power Save Clock
#define SPI_REG_HSUS_CTRL 0x0086 // SPI HCI Suspend Control
#else
#define SPI_REG_TX_CTRL 0x0000 // SPI Tx Control
#define SPI_REG_STATUS_RECOVERY 0x0004
#define SPI_REG_INT_TIMEOUT 0x0006
#define SPI_REG_HIMR 0x0014 // SPI Host Interrupt Mask
#define SPI_REG_HISR 0x0018 // SPI Host Interrupt Service Routine
#define SPI_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length
#define SPI_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page
#define SPI_REG_HCPWM1 0x0024 // HCI Current Power Mode 1
#define SPI_REG_HCPWM2 0x0026 // HCI Current Power Mode 2
#define SPI_REG_HTSFR_INFO 0x0030 // HTSF Informaion
#define SPI_REG_HRPWM1 0x0080 // HCI Request Power Mode 1
#define SPI_REG_HRPWM2 0x0082 // HCI Request Power Mode 2
#define SPI_REG_HPS_CLKR 0x0084 // HCI Power Save Clock
#define SPI_REG_HSUS_CTRL 0x0086 // SPI HCI Suspend Control
#define SPI_REG_HIMR_ON 0x0090 //SPI Host Extension Interrupt Mask Always
#define SPI_REG_HISR_ON 0x0091 //SPI Host Extension Interrupt Status Always
#define SPI_REG_CFG 0x00F0 //SPI Configuration Register
#endif
#define LOCAL_REG_TX_CTRL (SPI_REG_TX_CTRL |SPI_LOCAL_OFFSET)
#define LOCAL_REG_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY |SPI_LOCAL_OFFSET)
#define LOCAL_REG_INT_TIMEOUT (SPI_REG_INT_TIMEOUT |SPI_LOCAL_OFFSET)
#define LOCAL_REG_HIMR (SPI_REG_HIMR |SPI_LOCAL_OFFSET)
#define LOCAL_REG_HISR (SPI_REG_HISR |SPI_LOCAL_OFFSET)
#define LOCAL_REG_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN |SPI_LOCAL_OFFSET)
#define LOCAL_REG_FREE_TXPG (SPI_REG_FREE_TXPG |SPI_LOCAL_OFFSET)
#define LOCAL_REG_HRPWM1 (SPI_REG_HRPWM1 |SPI_LOCAL_OFFSET)
#define LOCAL_REG_HCPWM1 (SPI_REG_HCPWM1 |SPI_LOCAL_OFFSET)
#define LOCAL_REG_SUSPEND_NORMAL (SPI_REG_HSUS_CTRL|SPI_LOCAL_OFFSET)
#define HCI_HIMR_DISABLED 0
//SPI HIMR MASK diff with SDIO
#ifdef CONFIG_RTL8188F
#define HCI_HISR_RX_REQUEST BIT(0)
#define HCI_HISR_AVAL BIT(1)
#define HCI_HISR_TXERR BIT(2)
#define HCI_HISR_RXERR BIT(3)
#define HCI_HISR_TXFOVW BIT(4)
#define HCI_HISR_RXFOVW BIT(5)
#define HCI_HISR_TXBCNOK BIT(6)
#define HCI_HISR_TXBCNERR BIT(7)
#define HCI_HISR_BCNERLY_INT BIT(16)
#define HCI_HISR_C2HCMD BIT(17)
#define HCI_HISR_CPWM1 BIT(18)
#define HCI_HISR_CPWM2 BIT(19)
#define HCI_HISR_HSISR_IND BIT(20)
#define HCI_HISR_GTINT3_IND BIT(21)
#define HCI_HISR_GTINT4_IND BIT(22)
#define HCI_HISR_PSTIMEOUT BIT(23)
#define HCI_HISR_OCPINT BIT(24)
#define HCI_HISR_ATIMEND BIT(25)
#define HCI_HISR_ATIMEND_E BIT(26)
#define HCI_HISR_CTWEND BIT(27)
#define HCI_HISR_TSF_BIT32_TOGGLE BIT(29)
#define HCI_HISR_PSTIMEOUT_E BIT(30)
//SPI HIMR MASK diff with SDIO
#define HCI_HIMR_RX_REQUEST BIT(0)
#define HCI_HIMR_AVAL BIT(1)
#define HCI_HIMR_TXERR BIT(2)
#define HCI_HIMR_RXERR BIT(3)
#define HCI_HIMR_TXFOVW BIT(4)
#define HCI_HIMR_RXFOVW BIT(5)
#define HCI_HIMR_TXBCNOK BIT(6)
#define HCI_HIMR_TXBCNERR BIT(7)
#define HCI_HIMR_BCNERLY_INT BIT(16)
#define HCI_HIMR_C2HCMD BIT(17)
#define HCI_HIMR_CPWM1 BIT(18)
#define HCI_HIMR_CPWM2 BIT(19)
#define HCI_HIMR_HSISR_IND BIT(20)
#define HCI_HIMR_GTINT3_IND BIT(21)
#define HCI_HIMR_GTINT4_IND BIT(22)
#define HCI_HIMR_PSTIMEOUT BIT(23)
#define HCI_HIMR_OCPINT BIT(24)
#define HCI_HIMR_ATIMEND BIT(25)
#define HCI_HIMR_ATIMEND_E BIT(26)
#define HCI_HIMR_CTWEND BIT(27)
#define HCI_HIMR_TSF_BIT32_TOGGLE BIT(29)
#define HCI_HIMR_PSTIMEOUT_E BIT(30)
#else
#define HCI_HISR_RX_REQUEST BIT(0)
#define HCI_HISR_AVAL BIT(1)
#define HCI_HISR_TXERR BIT(2)
#define HCI_HISR_RXERR BIT(3)
#define HCI_HISR_TXFOVW BIT(4)
#define HCI_HISR_RXFOVW BIT(5)
#define HCI_HISR_TXBCNOK BIT(6)
#define HCI_HISR_TXBCNERR BIT(7)
#define HCI_HISR_BCNERLY_INT BIT(16)
#define HCI_HISR_ATIMEND BIT(17)
#define HCI_HISR_ATIMEND_E BIT(18)
#define HCI_HISR_CTWEND BIT(19)
#define HCI_HISR_C2HCMD BIT(20)
#define HCI_HISR_CPWM1 BIT(21)
#define HCI_HISR_CPWM2 BIT(22)
#define HCI_HISR_HSISR_IND BIT(23)
#define HCI_HISR_GTINT3_IND BIT(24)
#define HCI_HISR_GTINT4_IND BIT(25)
#define HCI_HISR_PSTIMEOUT BIT(26)
#define HCI_HISR_OCPINT BIT(27)
#define HCI_HISR_TSF_BIT32_TOGGLE BIT(29)
//SPI HIMR MASK diff with SDIO
#define HCI_HIMR_RX_REQUEST BIT(0)
#define HCI_HIMR_AVAL BIT(1)
#define HCI_HIMR_TXERR BIT(2)
#define HCI_HIMR_RXERR BIT(3)
#define HCI_HIMR_TXFOVW BIT(4)
#define HCI_HIMR_RXFOVW BIT(5)
#define HCI_HIMR_TXBCNOK BIT(6)
#define HCI_HIMR_TXBCNERR BIT(7)
#define HCI_HIMR_BCNERLY_INT BIT(16)
#define HCI_HIMR_ATIMEND BIT(17)
#define HCI_HIMR_ATIMEND_E BIT(18)
#define HCI_HIMR_CTWEND BIT(19)
#define HCI_HIMR_C2HCMD BIT(20)
#define HCI_HIMR_CPWM1 BIT(21)
#define HCI_HIMR_CPWM2 BIT(22)
#define HCI_HIMR_HSISR_IND BIT(23)
#define HCI_HIMR_GTINT3_IND BIT(24)
#define HCI_HIMR_GTINT4_IND BIT(25)
#define HCI_HIMR_PSTIMEOUT BIT(26)
#define HCI_HIMR_OCPINT BIT(27)
#define HCI_HIMR_TSF_BIT32_TOGGLE BIT(29)
#endif
#define MASK_SPI_HISR_CLEAR (HCI_HIMR_TXERR |\
HCI_HIMR_RXERR |\
HCI_HIMR_TXFOVW |\
HCI_HIMR_RXFOVW |\
HCI_HIMR_TXBCNOK |\
HCI_HIMR_TXBCNERR |\
HCI_HIMR_C2HCMD |\
HCI_HIMR_CPWM1 |\
HCI_HIMR_CPWM2 |\
HCI_HIMR_HSISR_IND |\
HCI_HIMR_GTINT3_IND |\
HCI_HIMR_GTINT4_IND |\
HCI_HIMR_PSTIMEOUT |\
HCI_HIMR_OCPINT)
#define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)//(x<<(unsigned int)24)
#define REG_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
#define REG_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
#define REG_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
#define REG_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
#define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)//(x<<(unsigned int)24)
//#define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
#define FIFO_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
#define FIFO_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
#define FIFO_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
//get status dword0
#define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8)
#define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6)
#define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6)
#define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6)
#define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6)
//get status dword1
#define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8)
#define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8)
#define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1)
#define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1)
#define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16)
#define RXDESC_SIZE 24
#define TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page
#define TX_FIFO_PAGE_SZ 128
struct spi_more_data {
unsigned long more_data;
unsigned long len;
};
extern BUS_DRV_OPS_T bus_driver_ops;
extern u8 spi_query_status_info(struct dvobj_priv *pdvobj);
extern void spi_set_intf_ops(struct _io_ops *pops);
#endif //__GSPI_SPEC_H__

68
USDK/component/common/drivers/wlan/realtek/src/hci/hci_intfs.h Normal file
View file

@ -0,0 +1,68 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _HCI_INTFS_H_
#define _HCI_INTFS_H_
#include <autoconf.h>
struct host_ctrl_intf_ops
{
struct dvobj_priv * (*dvobj_init)(void);
void (*dvobj_deinit)(struct dvobj_priv *dvobj);
void (*dvobj_request_irq)(struct dvobj_priv *dvobj);
void (*dvobj_free_irq)(struct dvobj_priv *dvobj);
};
extern struct dvobj_priv *hci_dvobj_init(void);
extern void hci_dvobj_deinit(struct dvobj_priv *dvobj);
extern void hci_dvobj_request_irq(struct dvobj_priv *dvobj);
extern void hci_dvobj_free_irq(struct dvobj_priv *dvobj);
#if defined(CONFIG_GSPI_HCI)
#define hci_bus_intf_type RTW_GSPI
#define hci_set_intf_ops spi_set_intf_ops
#define hci_intf_start rtw_hal_enable_interrupt
#define hci_intf_stop rtw_hal_disable_interrupt
extern s32 gspi_dvobj_xmit_mgnt(_adapter * padapter, struct xmit_frame *pmgntframe);
extern s32 gspi_dvobj_xmit_data(_adapter *padapter, struct xmit_frame *pxmitframe);
#endif
#if defined(CONFIG_SDIO_HCI)
#define hci_bus_intf_type RTW_SDIO
#define hci_set_intf_ops sdio_set_intf_ops
#define hci_intf_start rtw_hal_enable_interrupt
#define hci_intf_stop rtw_hal_disable_interrupt
extern s32 sdio_dvobj_xmit_mgnt(_adapter * padapter, struct xmit_frame *pmgntframe);
extern s32 sdio_dvobj_xmit_data(_adapter *padapter, struct xmit_frame *pxmitframe);
#endif
#if defined(CONFIG_LX_HCI)
#define hci_bus_intf_type RTW_LXBUS
#define hci_set_intf_ops lxbus_set_intf_ops
#define hci_intf_start rtw_hal_enable_interrupt
#define hci_intf_stop hci_lxbus_intf_stop
void hci_lxbus_intf_stop(_adapter *padapter);
u32 lextra_bus_dma_Interrupt (void* data);
#endif
#endif //_HCI_INTFS_H_

433
USDK/component/common/drivers/wlan/realtek/src/hci/hci_spec.h Normal file
View file

@ -0,0 +1,433 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __HCI_SPEC_H__
#define __HCI_SPEC_H__
#if defined(CONFIG_GSPI_HCI)
#include "gspi/gspi_spec.h"
// SPI Header Files
#ifdef PLATFORM_LINUX
#include <linux/spi/spi.h>
#endif
#define GSPI_CMD_LEN 4
#define HAL_INTERFACE_CMD_LEN GSPI_CMD_LEN
#define GSPI_STATUS_LEN 8
#define HAL_INTERFACE_CMD_STATUS_LEN GSPI_STATUS_LEN
#define HAL_INTERFACE_OVERHEAD (HAL_INTERFACE_CMD_LEN+HAL_INTERFACE_OVERHEAD)
//reserve tx headroom in case of softap forwarding unicase packet
#define RX_RESERV_HEADROOM (SKB_WLAN_TX_EXTRA_LEN>RX_DRIVER_INFO+RXDESC_SIZE)?(SKB_WLAN_TX_EXTRA_LEN-RX_DRIVER_INFO-RXDESC_SIZE):0
typedef struct gspi_data
{
//u8 func_number;
//u8 tx_block_mode;
//u8 rx_block_mode;
u16 block_transfer_len; //u32 block_transfer_len;
#ifdef PLATFORM_LINUX
struct spi_device *func;
struct workqueue_struct *priv_wq;
struct delayed_work irq_work;
#endif
#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
_mutex spi_mutex;
#endif
} GSPI_DATA, *PGSPI_DATA;
#define INTF_DATA GSPI_DATA
//extern void spi_set_intf_ops(struct _io_ops *pops);
extern void spi_int_hdl(PADAPTER padapter);
#define rtw_hci_interrupt_handler(__adapter) spi_int_hdl(__adapter)
#elif defined(CONFIG_SDIO_HCI)
#include "sdio/sdio_spec.h"
#define GSPI_CMD_LEN 0
#define HAL_INTERFACE_CMD_LEN GSPI_CMD_LEN
#define GSPI_STATUS_LEN 8
#define HAL_INTERFACE_CMD_STATUS_LEN GSPI_STATUS_LEN
#define HAL_INTERFACE_OVERHEAD (HAL_INTERFACE_CMD_LEN+HAL_INTERFACE_OVERHEAD)
#define RX_RESERV_HEADROOM (SKB_WLAN_TX_EXTRA_LEN>RX_DRIVER_INFO+RXDESC_SIZE)?(SKB_WLAN_TX_EXTRA_LEN-RX_DRIVER_INFO-RXDESC_SIZE):0
typedef struct gspi_data
{
//u8 func_number;
//u8 tx_block_mode;
//u8 rx_block_mode;
u16 block_transfer_len; //u32 block_transfer_len;
#ifdef PLATFORM_LINUX
struct spi_device *func;
struct workqueue_struct *priv_wq;
struct delayed_work irq_work;
#endif
struct sdio_func *func;
#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
_mutex spi_mutex;
#endif
} GSPI_DATA, *PGSPI_DATA;
#define INTF_DATA GSPI_DATA
//extern void spi_set_intf_ops(struct _io_ops *pops);
extern void spi_int_hdl(PADAPTER padapter);
#define rtw_hci_interrupt_handler(__adapter) spi_int_hdl(__adapter)
#elif defined(CONFIG_USB_HCI)
#include <usb_ops.h>
#include <usb_osintf.h>
#elif defined(CONFIG_PCI_HCI)
#include <pci_osintf.h>
#ifdef PLATFORM_LINUX
#include <linux/pci.h>
#endif
#define INTF_CMD_LEN 0
#define INTEL_VENDOR_ID 0x8086
#define SIS_VENDOR_ID 0x1039
#define ATI_VENDOR_ID 0x1002
#define ATI_DEVICE_ID 0x7914
#define AMD_VENDOR_ID 0x1022
#define PCI_MAX_BRIDGE_NUMBER 255
#define PCI_MAX_DEVICES 32
#define PCI_MAX_FUNCTION 8
#define PCI_CONF_ADDRESS 0x0CF8 // PCI Configuration Space Address
#define PCI_CONF_DATA 0x0CFC // PCI Configuration Space Data
#define PCI_CLASS_BRIDGE_DEV 0x06
#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10
#define U1DONTCARE 0xFF
#define U2DONTCARE 0xFFFF
#define U4DONTCARE 0xFFFFFFFF
#define PCI_VENDER_ID_REALTEK 0x10ec
#define HAL_HW_PCI_8180_DEVICE_ID 0x8180
#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 //8185 or 8185b
#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 //8185b
#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 //8185b
#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 //8190
#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 //8723E
#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 //8192 PCI-E
#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 //8192 SE
#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 //8192 SE
#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 //8191 SE Crab
#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 //8191 SE RE
#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 //8191 SE Unicron
#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 //8190 PCI for Ceraga
#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 //8190 Cardbus for Ceraga
#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 //8192e PCIE for Ceraga
#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 //8192e Express Card for Ceraga
#define HAL_HW_PCI_700F_DEVICE_ID 0x700F
#define HAL_HW_PCI_701F_DEVICE_ID 0x701F
#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304
#define HAL_HW_PCI_8192CET_DEVICE_ID 0x8191 //8192ce
#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178 //8192ce
#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177 //8192ce
#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176 //8192ce
#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191 //8192ce
#define HAL_HW_PCI_8192DE_DEVICE_ID 0x8193 //8192de
#define HAL_HW_PCI_002B_DEVICE_ID 0x002B //8192de, provided by HW SD
#define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179
#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers
#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00
#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 //8192 support 16 pages of IO registers
#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01
#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 //8192 support 16 pages of IO registers
#define HAL_HW_PCI_REVISION_ID_8192SE 0x10
#define HAL_HW_PCI_REVISION_ID_8192CE 0x1
#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 //8192 support 16 pages of IO registers
#define HAL_HW_PCI_REVISION_ID_8192DE 0x0
#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 //8192 support 16 pages of IO registers
enum pci_bridge_vendor {
PCI_BRIDGE_VENDOR_INTEL = 0x0,//0b'0000,0001
PCI_BRIDGE_VENDOR_ATI, //= 0x02,//0b'0000,0010
PCI_BRIDGE_VENDOR_AMD, //= 0x04,//0b'0000,0100
PCI_BRIDGE_VENDOR_SIS ,//= 0x08,//0b'0000,1000
PCI_BRIDGE_VENDOR_UNKNOWN, //= 0x40,//0b'0100,0000
PCI_BRIDGE_VENDOR_MAX ,//= 0x80
} ;
// copy this data structor defination from MSDN SDK
typedef struct _PCI_COMMON_CONFIG {
u16 VendorID;
u16 DeviceID;
u16 Command;
u16 Status;
u8 RevisionID;
u8 ProgIf;
u8 SubClass;
u8 BaseClass;
u8 CacheLineSize;
u8 LatencyTimer;
u8 HeaderType;
u8 BIST;
union {
struct _PCI_HEADER_TYPE_0 {
u32 BaseAddresses[6];
u32 CIS;
u16 SubVendorID;
u16 SubSystemID;
u32 ROMBaseAddress;
u8 CapabilitiesPtr;
u8 Reserved1[3];
u32 Reserved2;
u8 InterruptLine;
u8 InterruptPin;
u8 MinimumGrant;
u8 MaximumLatency;
} type0;
#if 0
struct _PCI_HEADER_TYPE_1 {
u32 BaseAddresses[PCI_TYPE1_ADDRESSES];
u8 PrimaryBusNumber;
u8 SecondaryBusNumber;
u8 SubordinateBusNumber;
u8 SecondaryLatencyTimer;
u8 IOBase;
u8 IOLimit;
u16 SecondaryStatus;
u16 MemoryBase;
u16 MemoryLimit;
u16 PrefetchableMemoryBase;
u16 PrefetchableMemoryLimit;
u32 PrefetchableMemoryBaseUpper32;
u32 PrefetchableMemoryLimitUpper32;
u16 IOBaseUpper;
u16 IOLimitUpper;
u32 Reserved2;
u32 ExpansionROMBase;
u8 InterruptLine;
u8 InterruptPin;
u16 BridgeControl;
} type1;
struct _PCI_HEADER_TYPE_2 {
u32 BaseAddress;
u8 CapabilitiesPtr;
u8 Reserved2;
u16 SecondaryStatus;
u8 PrimaryBusNumber;
u8 CardbusBusNumber;
u8 SubordinateBusNumber;
u8 CardbusLatencyTimer;
u32 MemoryBase0;
u32 MemoryLimit0;
u32 MemoryBase1;
u32 MemoryLimit1;
u16 IOBase0_LO;
u16 IOBase0_HI;
u16 IOLimit0_LO;
u16 IOLimit0_HI;
u16 IOBase1_LO;
u16 IOBase1_HI;
u16 IOLimit1_LO;
u16 IOLimit1_HI;
u8 InterruptLine;
u8 InterruptPin;
u16 BridgeControl;
u16 SubVendorID;
u16 SubSystemID;
u32 LegacyBaseAddress;
u8 Reserved3[56];
u32 SystemControl;
u8 MultiMediaControl;
u8 GeneralStatus;
u8 Reserved4[2];
u8 GPIO0Control;
u8 GPIO1Control;
u8 GPIO2Control;
u8 GPIO3Control;
u32 IRQMuxRouting;
u8 RetryStatus;
u8 CardControl;
u8 DeviceControl;
u8 Diagnostic;
} type2;
#endif
} u;
u8 DeviceSpecific[108];
} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;
typedef struct _RT_PCI_CAPABILITIES_HEADER {
u8 CapabilityID;
u8 Next;
} RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER;
struct pci_priv{
BOOLEAN pci_clk_req;
u8 pciehdr_offset;
// PCIeCap is only differece between B-cut and C-cut.
// Configuration Space offset 72[7:4]
// 0: A/B cut
// 1: C cut and later.
u8 pcie_cap;
u8 linkctrl_reg;
u8 busnumber;
u8 devnumber;
u8 funcnumber;
u8 pcibridge_busnum;
u8 pcibridge_devnum;
u8 pcibridge_funcnum;
u8 pcibridge_vendor;
u16 pcibridge_vendorid;
u16 pcibridge_deviceid;
u8 pcibridge_pciehdr_offset;
u8 pcibridge_linkctrlreg;
u8 amd_l1_patch;
};
typedef struct _RT_ISR_CONTENT
{
union{
u32 IntArray[2];
u32 IntReg4Byte;
u16 IntReg2Byte;
};
}RT_ISR_CONTENT, *PRT_ISR_CONTENT;
//#define RegAddr(addr) (addr + 0xB2000000UL)
//some platform macros will def here
static inline void NdisRawWritePortUlong(u32 port, u32 val)
{
outl(val, port);
//writel(val, (u8 *)RegAddr(port));
}
static inline void NdisRawWritePortUchar(u32 port, u8 val)
{
outb(val, port);
//writeb(val, (u8 *)RegAddr(port));
}
static inline void NdisRawReadPortUchar(u32 port, u8 *pval)
{
*pval = inb(port);
//*pval = readb((u8 *)RegAddr(port));
}
static inline void NdisRawReadPortUshort(u32 port, u16 *pval)
{
*pval = inw(port);
//*pval = readw((u8 *)RegAddr(port));
}
static inline void NdisRawReadPortUlong(u32 port, u32 *pval)
{
*pval = inl(port);
//*pval = readl((u8 *)RegAddr(port));
}
#elif defined(CONFIG_LX_HCI)
#define GSPI_CMD_LEN 0
#define GSPI_STATUS_LEN 0
#include "lxbus/lxbus_spec.h"
#endif // interface define
#if 0 //TODO
struct intf_priv {
u8 *intf_dev;
u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64
u32 max_xmitsz; //USB2.0: unlimited, SDIO:512
u32 max_recvsz; //USB2.0: unlimited, SDIO:512
volatile u8 *io_rwmem;
volatile u8 *allocated_io_rwmem;
u32 io_wsz; //unit: 4bytes
u32 io_rsz;//unit: 4bytes
u8 intf_status;
void (*_bus_io)(u8 *priv);
/*
Under Sync. IRP (SDIO/USB)
A protection mechanism is necessary for the io_rwmem(read/write protocol)
Under Async. IRP (SDIO/USB)
The protection mechanism is through the pending queue.
*/
_mutex ioctl_mutex;
#ifdef PLATFORM_LINUX
#ifdef CONFIG_USB_HCI
// when in USB, IO is through interrupt in/out endpoints
struct usb_device *udev;
PURB piorw_urb;
u8 io_irp_cnt;
u8 bio_irp_pending;
_sema io_retevt;
_timer io_timer;
u8 bio_irp_timeout;
u8 bio_timer_cancel;
#endif
#endif
#ifdef PLATFORM_OS_XP
#ifdef CONFIG_SDIO_HCI
// below is for io_rwmem...
PMDL pmdl;
PSDBUS_REQUEST_PACKET sdrp;
PSDBUS_REQUEST_PACKET recv_sdrp;
PSDBUS_REQUEST_PACKET xmit_sdrp;
PIRP piorw_irp;
#endif
#ifdef CONFIG_USB_HCI
PURB piorw_urb;
PIRP piorw_irp;
u8 io_irp_cnt;
u8 bio_irp_pending;
_sema io_retevt;
#endif
#endif
};
#endif
#endif //__HCI_SPEC_H__

55
USDK/component/common/drivers/wlan/realtek/src/hci/lxbus/lxbus_spec.h Normal file
View file

@ -0,0 +1,55 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __LXBUS_SPEC_H__
#define __LXBUS_SPEC_H__
#include <lxbus_ops.h>
//#include <lxbus_hal.h>
#define HAL_INTERFACE_CMD_LEN 0
#define HAL_INTERFACE_CMD_STATUS_LEN 0
#define HAL_INTERFACE_OVERHEAD (HAL_INTERFACE_CMD_LEN+HAL_INTERFACE_CMD_STATUS_LEN)
/*
* The following data structure is used for 8195a debug, and should not
* declared this parameter in release version to save sram usage
* It is used for debugging tx/rx and r/w pointer
*/
struct hal_debug
{
unsigned int int_count;
unsigned int crc_err;
u16 last_write_be;
u16 last_write_mgt;
u16 last_closed_be;
u16 last_closed_mgt;
};
// The following section should be removed?
#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13]
#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13]
#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13]
#define SDIO_MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ
#endif //__LXBUS_SPEC_H__

818
USDK/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_drvio.c Normal file
View file

@ -0,0 +1,818 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*******************************************************************************/
#define _GSPI_IO_C_
#include <drv_types.h>
#ifdef CONFIG_SDIO_HCI
#include "wifi_io.h" //from sdio_host driver
//#include <FreeRTOS.h>
//#include <task.h>
//#define SDIO_CMD52_IO
//SDIO host local register space mapping.
#define SDIO_LOCAL_MSK 0x0FFF
#define WLAN_IOREG_MSK 0x7FFF
#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0]
#define WLAN_RX0FF_MSK 0x0003
#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID
#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13]
#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13]
#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13]
#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13]
#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13]
#define WLAN_IOREG_DEVICE_ID 8 // 1b[16]
//
// Description:
// Query SDIO Local register to query current the number of Free TxPacketBuffer page.
//
// Assumption:
// 1. Running at PASSIVE_LEVEL
// 2. RT_TX_SPINLOCK is NOT acquired.
//
// Created by Roger, 2011.01.28.
//
#ifdef CONFIG_RTL8188F
u8 spi_query_status_info(struct dvobj_priv *pdvobj)
{
ADAPTER *padapter = pdvobj->if1;
pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX] = rtw_read8(padapter, LOCAL_REG_FREE_TXPG);
pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX] = rtw_read8(padapter, LOCAL_REG_FREE_TXPG+2);
pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX] = rtw_read8(padapter, LOCAL_REG_FREE_TXPG+4);
pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] = rtw_read8(padapter, LOCAL_REG_FREE_TXPG+6);
RT_TRACE(_module_hci_ops_c_, _drv_notice_,
("%s: Free page for HIQ(%x),MIDQ(%x),LOWQ(%x),PUBQ(%x)\n",
__FUNCTION__,
pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]));
//_exit_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql);
return _TRUE;
}
#else
u8 spi_query_status_info(struct dvobj_priv *pdvobj)
{
u32 NumOfFreePage;
ADAPTER *padapter = pdvobj->if1;
NumOfFreePage = rtw_read32(padapter, LOCAL_REG_FREE_TXPG);
// _enter_critical_bh(&pdvobj->SdioTxFIFOFreePageLock, &irql);
rtw_memcpy(pdvobj->SdioTxFIFOFreePage, &NumOfFreePage, 4);
RT_TRACE(_module_hci_ops_c_, _drv_notice_,
("%s: Free page for HIQ(%x),MIDQ(%x),LOWQ(%x),PUBQ(%x)\n",
__FUNCTION__,
pdvobj->SdioTxFIFOFreePage[HI_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[MID_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[LOW_QUEUE_IDX],
pdvobj->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]));
// _exit_critical_bh(&pdvobj->SdioTxFIFOFreePageLock, &irql);
return _TRUE;
}
#endif
static unsigned char get_deviceid(unsigned int addr)
{
unsigned char devideId;
unsigned short pseudoId;
pseudoId = (unsigned short)(addr >> 16);
switch (pseudoId)
{
case 0x1025:
devideId = SDIO_LOCAL_DEVICE_ID;
break;
case 0x1026:
devideId = WLAN_IOREG_DEVICE_ID;
break;
// case 0x1027:
// devideId = SDIO_FIRMWARE_FIFO;
// break;
case 0x1031:
devideId = WLAN_TX_HIQ_DEVICE_ID;
break;
case 0x1032:
devideId = WLAN_TX_MIQ_DEVICE_ID;
break;
case 0x1033:
devideId = WLAN_TX_LOQ_DEVICE_ID;
break;
case 0x1034:
devideId = WLAN_RX0FF_DEVICE_ID;
break;
default:
// devideId = (u8)((addr >> 13) & 0xF);
devideId = WLAN_IOREG_DEVICE_ID;
break;
}
return devideId;
}
static unsigned int _cvrt2ftaddr(const unsigned int addr, unsigned char *pdeviceId, unsigned short *poffset)
{
unsigned char deviceId;
unsigned short offset;
unsigned int ftaddr;
deviceId = get_deviceid(addr);
offset = 0;
switch (deviceId)
{
case SDIO_LOCAL_DEVICE_ID:
offset = addr & SDIO_LOCAL_MSK;
break;
case WLAN_TX_HIQ_DEVICE_ID:
case WLAN_TX_MIQ_DEVICE_ID:
case WLAN_TX_LOQ_DEVICE_ID:
offset = addr & WLAN_FIFO_MSK;
break;
case WLAN_RX0FF_DEVICE_ID:
offset = addr & WLAN_RX0FF_MSK;
break;
case WLAN_IOREG_DEVICE_ID:
default:
deviceId = WLAN_IOREG_DEVICE_ID;
offset = addr & WLAN_IOREG_MSK;
break;
}
ftaddr = (deviceId << 13) | offset;
if (pdeviceId) *pdeviceId = deviceId;
if (poffset) *poffset = offset;
return ftaddr;
}
unsigned char sdio_read8(ADAPTER *Adapter, unsigned int addr, int *err)
{
struct dvobj_priv *psdiodev;
unsigned int ftaddr;
unsigned char val;
_func_enter_;
psdiodev = adapter_to_dvobj(Adapter);
ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func);
val = rtw_sdio_bus_ops.readb(psdiodev->intf_data.func, ftaddr, err);
rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func);
if(err && *err)
DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
_func_exit_;
return val;
}
unsigned short sdio_read16(ADAPTER *Adapter, unsigned int addr, int *err)
{
struct dvobj_priv *psdiodev;
unsigned int ftaddr;
unsigned short val;
_func_enter_;
psdiodev = adapter_to_dvobj(Adapter);
if (addr & 1)
DBG_871X( "sdio_read16 addr is wrong addr:0x%08x\n", addr);
ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func);
val = rtw_sdio_bus_ops.readw(psdiodev->intf_data.func, ftaddr, err);
rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func);
if(err && *err)
DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
_func_exit_;
return val;
}
unsigned int sdio_read32(ADAPTER *Adapter, unsigned int addr, int *err)
{
struct dvobj_priv *psdiodev;
unsigned int ftaddr;
unsigned int val;
_func_enter_;
psdiodev = adapter_to_dvobj(Adapter);
if (addr & 3)
DBG_871X( "sdio_read32 addr is wrong addr:0x%08x\n", addr);
ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func);
val = rtw_sdio_bus_ops.readl(psdiodev->intf_data.func, ftaddr, err);
rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func);
if(err && *err)
DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
_func_exit_;
return val;
}
unsigned int sdio_write8(ADAPTER *Adapter, unsigned int addr, unsigned int buf, int*err)
{
struct dvobj_priv *psdiodev;
unsigned int ftaddr;
unsigned int val = 0;
_func_enter_;
psdiodev = adapter_to_dvobj(Adapter);
ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func);
rtw_sdio_bus_ops.writeb(psdiodev->intf_data.func, buf&0xFF,ftaddr, err);
rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func);
if(err && *err)
DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
_func_exit_;
return val;
}
unsigned int sdio_write16(ADAPTER *Adapter, unsigned int addr,unsigned int buf, int *err)
{
struct dvobj_priv *psdiodev;
unsigned int ftaddr;
unsigned int val = 0;
_func_enter_;
psdiodev = adapter_to_dvobj(Adapter);
if (addr & 1)
DBG_871X( "sdio_write16 addr is wrong addr:0x%08x\n", addr);
ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func);
rtw_sdio_bus_ops.writew(psdiodev->intf_data.func, buf&0xFFFF,ftaddr, err);
rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func);
if(err && *err)
DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
_func_exit_;
return val;
}
unsigned int sdio_write32(ADAPTER *Adapter, unsigned int addr, unsigned int buf, int *err)
{
struct dvobj_priv *psdiodev;
unsigned int ftaddr;
unsigned int val = 0;
_func_enter_;
psdiodev = adapter_to_dvobj(Adapter);
if (addr & 3)
DBG_871X( "sdio_write32 addr is wrong addr:0x%08x\n", addr);
ftaddr = _cvrt2ftaddr(addr, NULL, NULL);
rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func);
rtw_sdio_bus_ops.writel(psdiodev->intf_data.func, buf&0xFFFFFFFF,ftaddr, err);
rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func);
if(err && *err)
DBG_871X( "%s: FAIL!(%d) addr=0x%05x\n", __func__, *err, addr);
_func_exit_;
return val;
}
unsigned int _fifoqueue2ftaddr(unsigned int fifo, unsigned int addr)
{
unsigned int cmdaddr = TX_HIQ_DOMAIN;
switch(fifo) {
case TX_LOQ_DOMAIN:
cmdaddr = ((WLAN_TX_LOQ_DEVICE_ID << 13) | (addr & WLAN_FIFO_MSK));
break;
case TX_HIQ_DOMAIN:
cmdaddr = ((WLAN_TX_HIQ_DEVICE_ID << 13) | (addr & WLAN_FIFO_MSK));
break;
case TX_MIQ_DOMAIN:
cmdaddr = ((WLAN_TX_MIQ_DEVICE_ID << 13) | (addr & WLAN_FIFO_MSK));
break;
case RX_RXFIFO_DOMAIN:
cmdaddr = ((WLAN_RX0FF_DEVICE_ID << 13) | (addr & WLAN_RX0FF_MSK));
break;
default:
cmdaddr = ((WLAN_TX_MIQ_DEVICE_ID << 13) | (addr & WLAN_FIFO_MSK));
break;
}
return cmdaddr;
}
void sdio_write_tx_fifo(ADAPTER *Adapter, unsigned char *buf, int reallen, unsigned int fifo)
{
struct dvobj_priv *psdiodev;
unsigned int ftaddr;
unsigned char *mem = buf;
int free_mem = 0;
int status;
unsigned int cnt = (unsigned int)reallen;
unsigned int page_num = 0;
unsigned int wait_num = 100;
unsigned int use_page = 0;
_func_enter_;
use_page = (cnt + TX_FIFO_PAGE_SZ - 1) / TX_FIFO_PAGE_SZ;
if (cnt > 512)
cnt = _RND(cnt, 512);
else
cnt = _RND(cnt, 4);
if (((u32)buf) % 4) {
mem = rtw_zmalloc(cnt);
while(!mem) {
DBG_871X("rtw_zmalloc fail, cannot write tx fifo now\n");
rtw_yield_os();
mem = rtw_zmalloc(cnt);
}
free_mem = 1;
//DBG_871X("sdio_write_tx_fifo tem_buf:%p ", mem);
rtw_memcpy(mem, buf, reallen);
} else {
mem = buf;
}
if (((u32)mem) % 4) {
DBG_871X("sdio_write_tx_fifo: Oops mem %p not 4 byte Alignment this will cause DMA wrong \n", mem);
}
psdiodev = adapter_to_dvobj(Adapter);
if (fifo == TX_HIQ_DOMAIN)
page_num = psdiodev->SdioTxFIFOFreePage[HI_QUEUE_IDX];
else if (fifo == TX_LOQ_DOMAIN)
page_num = psdiodev->SdioTxFIFOFreePage[LOW_QUEUE_IDX];
else
page_num = psdiodev->SdioTxFIFOFreePage[MID_QUEUE_IDX];
if (page_num + psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] < use_page) {
spi_query_status_info(Adapter->dvobj);
}
while (page_num + psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] < use_page) {
DBG_871X("Oops: spi_write_tx_fifo(): page_num is %d, padapter->pub_page is %d, wait_num is %d",
page_num, psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX], wait_num);
rtw_msleep_os(1);
//rtw_udelay_os(20);
spi_query_status_info(Adapter->dvobj);
if (fifo == TX_HIQ_DOMAIN)
page_num = psdiodev->SdioTxFIFOFreePage[HI_QUEUE_IDX];
else if (fifo == TX_LOQ_DOMAIN)
page_num = psdiodev->SdioTxFIFOFreePage[LOW_QUEUE_IDX];
else
page_num = psdiodev->SdioTxFIFOFreePage[MID_QUEUE_IDX];
if (wait_num <= 2) {
DBG_871X("%s(): wait_num is <= 2 drop", __FUNCTION__);
return;
}
wait_num --;
}
if (fifo == TX_HIQ_DOMAIN) {
if (use_page <= page_num) {
psdiodev->SdioTxFIFOFreePage[HI_QUEUE_IDX] -= page_num;
} else {
psdiodev->SdioTxFIFOFreePage[HI_QUEUE_IDX] = 0;
psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= use_page - psdiodev->SdioTxFIFOFreePage[HI_QUEUE_IDX];
}
} else if (fifo == TX_LOQ_DOMAIN) {
if (use_page <= page_num) {
psdiodev->SdioTxFIFOFreePage[LOW_QUEUE_IDX] -= page_num;
} else {
psdiodev->SdioTxFIFOFreePage[LOW_QUEUE_IDX] = 0;
psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= use_page - psdiodev->SdioTxFIFOFreePage[LOW_QUEUE_IDX];
}
} else {
if (use_page <= page_num) {
psdiodev->SdioTxFIFOFreePage[MID_QUEUE_IDX] -= page_num;
} else {
psdiodev->SdioTxFIFOFreePage[MID_QUEUE_IDX] = 0;
psdiodev->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= use_page - psdiodev->SdioTxFIFOFreePage[MID_QUEUE_IDX];
}
}
//must reallen here or tx will wrong when RND(512)
ftaddr = _fifoqueue2ftaddr(fifo, reallen >> 2);
rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func);
status = rtw_sdio_bus_ops.memcpy_toio(psdiodev->intf_data.func, ftaddr, mem, cnt);
rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func);
if (free_mem) {
rtw_mfree(mem, cnt);
}
if (status) {
DBG_871X("sdio_write_tx_fifo:status:%x ftaddr:%x Length:%d fifo:%x ", status, ftaddr, cnt, fifo);
}
_func_exit_;
return;
}
void sdio_read_rx_fifo(ADAPTER *Adapter, unsigned char *buf, int reallen)
{
struct dvobj_priv *psdiodev;
unsigned int ftaddr;
unsigned char *mem = buf;
int free_mem = 0;
int status;
unsigned int cnt = (unsigned int)reallen;
static unsigned int sdio_rxfifo_cnt = 0;
unsigned int fifo = RX_RXFIFO_DOMAIN;
_func_enter_;
if (cnt > 512)
cnt = _RND(cnt, 512);
else
cnt = _RND(cnt, 4);
mem = rtw_zmalloc(cnt);
if (mem) {
free_mem = 1;
//DBG_871X("sdio_read_rx_fifo tem_buf:%p ", mem);
} else {
//DBG_871X("sdio_read_rx_fifo tem_buf:Oops %p ", mem);
mem = buf;
}
if (mem == NULL) {
DBG_871X("sdio_read_rx_fifo: Oops mem is NULL \n");
return;
}
if (((u32)mem) % 4) {
DBG_871X("sdio_read_rx_fifo: Oops mem %p not 4 byte Alignment this will cause DMA wrong \n", mem);
}
psdiodev = adapter_to_dvobj(Adapter);
ftaddr = _fifoqueue2ftaddr(fifo, sdio_rxfifo_cnt++);
rtw_sdio_bus_ops.claim_host(psdiodev->intf_data.func);
status = rtw_sdio_bus_ops.memcpy_fromio(psdiodev->intf_data.func, mem, ftaddr, cnt);
rtw_sdio_bus_ops.release_host(psdiodev->intf_data.func);
if (free_mem) {
if (buf)
rtw_memcpy(buf, mem, reallen);
rtw_mfree(mem, cnt);
}
if (status) {
//error
DBG_871X("rtw_sdio_read_rx_fifo error 0x%x\n"
"***** Addr = %x *****\n"
"***** Length = %d *****\n", status, ftaddr, cnt);
}
_func_exit_;
return;
}
void sdio_cmd52_read(ADAPTER *Adapter, u32 addr, u32 cnt, u8 *pdata, int *err)
{
int i = 0;
for (i = 0; i < cnt; i++) {
pdata[i] = sdio_read8(Adapter, addr + i, err);
if (err && *err)
break;
}
}
void sdio_cmd52_write(ADAPTER *Adapter, u32 addr, u32 cnt, u8 *pdata, int *err)
{
int i = 0;
for (i = 0; i < cnt; i++) {
sdio_write8(Adapter, addr + i, pdata[i], err);
if (err && *err)
break;
}
}
u8 _sdio_read8(struct dvobj_priv *pdvobj, u32 addr, s32 *err)
{
u8 val;
ADAPTER *Adapter = pdvobj->if1;
_func_enter_;
val = sdio_read8(Adapter, addr, err);
_func_exit_;
return val;
}
u16 _sdio_read16(struct dvobj_priv *pdvobj, u32 addr, s32 *err)
{
u8 bMacPwrCtrlOn = _FALSE;
u16 val;
u8 cmd52_io = 0;
ADAPTER *Adapter = pdvobj->if1;
_func_enter_;
/* we should use CMD 52 before bMacPwrCtrlOn */
rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
cmd52_io = !bMacPwrCtrlOn;
#ifdef SDIO_CMD52_IO
cmd52_io = 1;
#endif
if (cmd52_io) {
sdio_cmd52_read(Adapter, addr, 2, (u8*)&val, err);
val = le16_to_cpu(val);
return val;
}
val = sdio_read16(Adapter, addr, err);
_func_exit_;
return val;
}
u32 _sdio_read32(struct dvobj_priv *pdvobj, u32 addr, s32 *err)
{
u8 bMacPwrCtrlOn = _FALSE;
u32 val;
u8 cmd52_io = 0;
ADAPTER *Adapter = pdvobj->if1;
_func_enter_;
/* we should use CMD 52 before bMacPwrCtrlOn */
rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
cmd52_io = !bMacPwrCtrlOn;
#ifdef SDIO_CMD52_IO
cmd52_io = 1;
#endif
if (cmd52_io) {
sdio_cmd52_read(Adapter, addr, 4, (u8*)&val, err);
val = le32_to_cpu(val);
return val;
}
val = sdio_read32(Adapter, addr, err);
_func_exit_;
return val;
}
s32 _sdio_write8(struct dvobj_priv *pdvobj, u32 addr, u8 val, s32 *err)
{
ADAPTER *Adapter = pdvobj->if1;
_func_enter_;
sdio_write8(Adapter, addr, (u32)val, err);
_func_exit_;
return _SUCCESS;
}
s32 _sdio_write16(struct dvobj_priv *pdvobj, u32 addr, u16 val, s32 *err)
{
u8 bMacPwrCtrlOn = _FALSE;
u8 cmd52_io = 0;
ADAPTER *Adapter = pdvobj->if1;
_func_enter_;
/* we should use CMD 52 before bMacPwrCtrlOn */
rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
cmd52_io = !bMacPwrCtrlOn;
#ifdef SDIO_CMD52_IO
cmd52_io = 1;
#endif
if (cmd52_io) {
val = cpu_to_le16(val);
sdio_cmd52_write(Adapter, addr, 2, (u8*)&val, err);
return _SUCCESS;
}
sdio_write16(Adapter, addr, (u32)val, err);
_func_exit_;
return _SUCCESS;
}
s32 _sdio_write32(struct dvobj_priv *pdvobj, u32 addr, u32 val, s32 *err)
{
u8 bMacPwrCtrlOn = _FALSE;
u8 cmd52_io = 0;
ADAPTER *Adapter = pdvobj->if1;
_func_enter_;
/* we should use CMD 52 before bMacPwrCtrlOn */
rtw_hal_get_hwreg(Adapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
cmd52_io = !bMacPwrCtrlOn;
#ifdef SDIO_CMD52_IO
cmd52_io = 1;
#endif
if (cmd52_io) {
val = cpu_to_le32(val);
sdio_cmd52_write(Adapter, addr, 4, (u8*)&val, err);
return _SUCCESS;
}
sdio_write32(Adapter, addr, val, err);
_func_exit_;
return _SUCCESS;
}
/*
* Description:
* Read from RX FIFO
* Round read size to block size,
* and make sure data transfer will be done in one command.
*
* Parameters:
* pintfhdl a pointer of intf_hdl
* addr port ID
* cnt size to read
* rmem address to put data
*
* Return:
* _SUCCESS(1) Success
* _FAIL(0) Fail
*/
static int _sdio_read_rx_fifo(struct dvobj_priv *pdvobj, u32 addr, u8 *mem, u32 cnt, struct fifo_more_data *pmore_data)
{
ADAPTER *Adapter = pdvobj->if1;
//struct spi_more_data more_data = {0};
//DBG_8192C("%s \n", __func__);
rtw_memset(pmore_data, 0, sizeof(struct fifo_more_data));
sdio_read_rx_fifo(Adapter, mem, cnt);
return _SUCCESS;
}
/*
* Description:
* Translate sdio fifo address to Domain ID in each WLAN FIFO
*/
static u32 hwaddr2txfifo(u32 addr)
{
u32 fifo_domain_id;
switch (addr)
{
case WLAN_TX_HIQ_DEVICE_ID:
fifo_domain_id = TX_HIQ_DOMAIN;
break;
case WLAN_TX_MIQ_DEVICE_ID:
fifo_domain_id = TX_MIQ_DOMAIN;
break;
case WLAN_TX_LOQ_DEVICE_ID:
fifo_domain_id = TX_LOQ_DOMAIN;
break;
default:
fifo_domain_id = TX_LOQ_DOMAIN;
break;
}
return fifo_domain_id;
}
static int _sdio_write_tx_fifo(struct dvobj_priv *pdvobj, u32 addr, u8 *mem, u32 cnt)
{
u8 remain_len = 0;
u32 w_sz = cnt;
ADAPTER *Adapter = pdvobj->if1;
remain_len = w_sz%4;
if (remain_len != 0)
w_sz += 4 -remain_len;
#if 0//ndef LZM_TEST
if (1) {
int i = 0;
for(i = 0; i < w_sz; i += 4) {
DBG_871X("_sdio_write_port[%d]: 0x%08x ", i, *(u32*)(mem + i));
}
}
#endif
#if 0
{
static u32 write_test = 0;
u32 now_time = 0;
write_test++;
if(write_test==1000) {
now_time = xTaskGetTickCount() * portTICK_RATE_MS;
DBG_8192C("%s fifo:%d cnt:%d w_sz:%d mem:%p, now time:%d\n", __func__, addr, cnt, w_sz, mem, now_time);
write_test = 0;
}
}
#endif
sdio_write_tx_fifo(Adapter, mem, w_sz, hwaddr2txfifo(addr));
return _SUCCESS;
}
static int sdio_io_priv(struct dvobj_priv *pdvobj)
{
ADAPTER *Adapter = pdvobj->if1;
//struct dvobj_priv *pdvobj = &Adapter->dvobjpriv;
return _SUCCESS;
}
void sdio_set_intf_ops(struct _io_ops *pops)
{
pops->init_io_priv = &sdio_io_priv;
pops->write8_endian = NULL;
pops->_read8 = &_sdio_read8;
pops->_read16 = &_sdio_read16;
pops->_read32 = &_sdio_read32;
pops->_write8 = &_sdio_write8;
pops->_write16 = &_sdio_write16;
pops->_write32 = &_sdio_write32;
pops->read_rx_fifo = &_sdio_read_rx_fifo;
pops->write_tx_fifo = &_sdio_write_tx_fifo;
}
#endif

264
USDK/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_intf.c Normal file
View file

@ -0,0 +1,264 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#define _GSPI_INTF_C_
#include <drv_types.h>
#ifdef CONFIG_SDIO_HCI
#include "wifi_io.h" //from sdio_driver
#ifndef CONFIG_SDIO_HCI
#error "CONFIG_SDIO_HCI should be on!\n"
#endif
struct dvobj_priv *gspi_dvobj_init(void)
{
// int status = _FAIL;
struct dvobj_priv *dvobj = NULL;
PGSPI_DATA pgspi_data;
_func_enter_;
dvobj = (struct dvobj_priv*)rtw_zmalloc(sizeof(*dvobj));
if (NULL == dvobj) {
goto exit;
}
pgspi_data = &dvobj->intf_data;
rtw_mutex_init(&pgspi_data->spi_mutex);
//pgspi_data->block_transfer_len = 512; //512 blocks r/w is not required for GSPI interface
//pgspi_data->tx_block_mode = 0;
//pgspi_data->rx_block_mode = 0;
// status = _SUCCESS;
if(wifi_sdio_func) {
DBG_871X("[gspi_dvobj_init] get wifi_func:%p\n", wifi_sdio_func);
dvobj->intf_data.func = wifi_sdio_func;
} else {
DBG_871X("[gspi_dvobj_init] Oops: get wifi sdio function fail");
}
exit:
_func_exit_;
return dvobj;
}
void gspi_dvobj_deinit(struct dvobj_priv *dvobj)
{
//TODO
// struct dvobj_priv *dvobj = spi_get_drvdata(spi);
_func_enter_;
//TODO
// spi_set_drvdata(spi, NULL);
if (dvobj) {
//TODO
// gspi_deinit(dvobj);
rtw_mutex_free(&dvobj->intf_data.spi_mutex);
rtw_mfree((u8*)dvobj, sizeof(*dvobj));
}
_func_exit_;
}
void sdio_dvobj_interrupt_entry(struct sdio_func *func)
{
//DBG_871X("[sdio_wifi_interrupt_entry] func :%p\n", func);
//sdio irq have claim host, we should release it
//and claim it after SDIO IO, or SDIO IO will deadlock
rtw_sdio_bus_ops.release_host(func);
rtw_hci_interrupt_handler(func->drv_priv);
rtw_sdio_bus_ops.claim_host(func);
}
void sdio_dvobj_request_irq(struct dvobj_priv *dvobj)
{
_func_enter_;
if(dvobj->intf_data.func) {
dvobj->intf_data.func->drv_priv = (void*)dvobj->if1;
rtw_sdio_bus_ops.claim_host(dvobj->intf_data.func);
rtw_sdio_bus_ops.claim_irq(dvobj->intf_data.func, sdio_dvobj_interrupt_entry);
rtw_sdio_bus_ops.release_host(dvobj->intf_data.func);
}
_func_exit_;
}
void sdio_dvobj_free_irq(struct dvobj_priv *dvobj)
{
_func_enter_;
if(dvobj->intf_data.func) {
dvobj->intf_data.func->drv_priv = (void*)dvobj->if1;
rtw_sdio_bus_ops.claim_host(dvobj->intf_data.func);
rtw_sdio_bus_ops.release_irq(dvobj->intf_data.func);
rtw_sdio_bus_ops.release_host(dvobj->intf_data.func);
}
_func_exit_;
}
static inline u32 ffaddr2deviceId(struct dvobj_priv *pdvobj, u32 addr)
{
return pdvobj->Queue2Pipe[addr];
}
static s32 rtw_xmit_xmitbuf(_adapter * padapter, struct xmit_buf *pxmitbuf)
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
u32 deviceId;
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("@@@rtw_xmit_xmitbuf(): pxmitbuf->len=%d\n", pxmitbuf->len));
//translate queue index to Device Id
deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr);
rtw_write_port(padapter, deviceId, pxmitbuf->len, (u8*)pxmitbuf->pbuf);
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
return _SUCCESS;
}
s32 sdio_dvobj_xmit_mgnt(_adapter * padapter, struct xmit_frame *pmgntframe)
{
s32 ret = _SUCCESS;
struct pkt_attrib *pattrib;
struct xmit_buf *pxmitbuf;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct mlme_priv *pmlmepriv = &(padapter->mlmepriv);
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
u8 *pframe = NULL;
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("+rtw_xmit_mgnt()\n"));
pattrib = &pmgntframe->attrib;
pxmitbuf = pmgntframe->pxmitbuf;
pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET;
//rtw_hal_update_txdesc(padapter, pmgntframe, pmgntframe->buf_addr);
pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz;
//pxmitbuf->pg_num = (pxmitbuf->len + 127)/128; // 128 is tx page size
//pxmitbuf->ptail = pmgntframe->buf_addr + pxmitbuf->len;
pxmitbuf->ff_hwaddr = rtw_get_ff_hwaddr(pmgntframe);
rtw_count_tx_stats(padapter, pmgntframe, pattrib->last_txcmdsz);
//RT_TRACE(_module_rtl871x_xmit_c_, _drv_always_, ("+rtw_xmit_mgnt(): type=%d\n", GetFrameSubType(pframe)));
if(GetFrameSubType(pframe)==WIFI_BEACON) //dump beacon directly
{
//When using dedicated xmit frame for issue bcn on ap mode
//free xmit frame for bcn reserved page on station mode - Alex Fang
#if USE_DEDICATED_BCN_TX
if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) {
rtw_free_xmitframe(pxmitpriv, pmgntframe);
pxmitbuf->priv_data = NULL;
}
rtw_write_port(padapter, ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr), pxmitbuf->len, pxmitbuf->pbuf);
if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE)
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
#else
rtw_free_xmitframe(pxmitpriv, pmgntframe);
pxmitbuf->priv_data = NULL;
rtw_xmit_xmitbuf(padapter, pxmitbuf);
#endif
}
else
{
rtw_free_xmitframe(pxmitpriv, pmgntframe);
pxmitbuf->priv_data = NULL;
rtw_xmit_xmitbuf(padapter, pxmitbuf);
}
if (ret != _SUCCESS)
rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("-rtw_xmit_mgnt\n"));
return ret;
}
s32 sdio_dvobj_xmit_data(_adapter *padapter, struct xmit_frame *pxmitframe)
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
_irqL irql;
s32 err;
#ifdef CONFIG_80211N_HT
if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
(pxmitframe->attrib.ether_type != 0x0806) &&
(pxmitframe->attrib.ether_type != 0x888e) &&
(pxmitframe->attrib.dhcp_pkt != 1))
{
if (padapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE)
rtw_issue_addbareq_cmd(padapter, pxmitframe);
}
#endif
#if USE_SKB_AS_XMITBUF
rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe);
#endif
rtw_enter_critical_bh(&pxmitpriv->lock, &irql);
#if 1 //FIX_XMITFRAME_FAULT, move from rtw_xmit().
#ifdef CONFIG_AP_MODE
if(xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE)
{
rtw_exit_critical_bh(&pxmitpriv->lock, &irql);
return 1;
}
#endif
#endif
err = rtw_xmitframe_enqueue(padapter, pxmitframe);
rtw_exit_critical_bh(&pxmitpriv->lock, &irql);
if (err != _SUCCESS) {
RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmit_data(): enqueue xmitframe fail\n"));
rtw_free_xmitframe(pxmitpriv, pxmitframe);
// Trick, make the statistics correct
pxmitpriv->tx_pkts--;
pxmitpriv->tx_drop++;
return _TRUE;
}
#ifdef CONFIG_CONCURRENT_MODE
if (padapter->adapter_type > PRIMARY_ADAPTER){
padapter = padapter->pbuddy_adapter;
}
#endif
rtw_wakeup_task(&padapter->xmitThread);
return _FALSE;
}
const struct host_ctrl_intf_ops hci_ops = {
gspi_dvobj_init,
gspi_dvobj_deinit,
sdio_dvobj_request_irq,
sdio_dvobj_free_irq
};
#endif

223
USDK/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_isr.c Normal file
View file

@ -0,0 +1,223 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*******************************************************************************/
#define _GSPI_ISR_C_
#include <drv_types.h>
#ifdef CONFIG_SDIO_HCI
extern struct recv_buf* rtw_recv_rxfifo(_adapter * padapter, u32 size, struct fifo_more_data* more_data);
void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr)
{
struct dvobj_priv *pdvobj = padapter->dvobj;
#ifdef CONFIG_LPS_LCLK
if (sdio_hisr & HCI_HISR_CPWM1)
{
struct reportpwrstate_parm report;
report.state = rtw_read8(padapter, LOCAL_REG_HCPWM1);
cpwm_int_hdl(padapter, &report);
}
#endif
if (sdio_hisr & HCI_HISR_TXERR)
{
u32 status;
status = rtw_read32(padapter, REG_TXDMA_STATUS);
rtw_write32(padapter, REG_TXDMA_STATUS, status);
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, status));
}
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT
if (sdio_hisr & HCI_HISR_BCNERLY_INT)
#endif
#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR
if (sdio_hisr & (HCI_HISR_TXBCNOK|HCI_HISR_TXBCNERR))
#endif
{
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
#if 0 //for debug
if (sdio_hisr & SDIO_HISR_BCNERLY_INT)
DBG_8192C("%s: SDIO_HISR_BCNERLY_INT\n", __func__);
if (sdio_hisr & SDIO_HISR_TXBCNOK)
DBG_8192C("%s: SDIO_HISR_TXBCNOK\n", __func__);
if (sdio_hisr & SDIO_HISR_TXBCNERR) {
u1Byte v422, v550, v419;
v422 = rtw_read8(padapter, 0x422);
v419 = rtw_read8(padapter, 0x419);
v550 = rtw_read8(padapter, 0x550);
DBG_8192C("%s: SDIO_HISR_TXBCNERR 422=%02x, 419=%02x, 550=%02x\n", __func__, v422, v419, v550);
}
#endif
if(check_fwstate(pmlmepriv, WIFI_AP_STATE))
{
//send_beacon(padapter);
if(pmlmepriv->update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter);
}
}
#ifdef CONFIG_CONCURRENT_MODE
if(check_buddy_fwstate(padapter, WIFI_AP_STATE))
{
//send_beacon(padapter);
if(padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE)
{
//tx_beacon_hdl(padapter, NULL);
set_tx_beacon_cmd(padapter->pbuddy_adapter);
}
}
#endif
}
#endif //CONFIG_INTERRUPT_BASED_TXBCN
if (sdio_hisr & HCI_HISR_C2HCMD)
{
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: C2H Command\n", __func__));
//TODO
// rtw_c2h_wk_cmd(padapter);
}
if (sdio_hisr & HCI_HISR_RX_REQUEST)// || sdio_hisr & SPI_HISR_RXFOVW)
{
struct recv_buf *precvbuf;
struct fifo_more_data more_data = {0};
//RT_TRACE(_module_hci_ops_c_,_drv_info_, ("%s: RX Request, size=%d\n", __func__, pdvobj->SdioRxFIFOSize));
sdio_hisr ^= HCI_HISR_RX_REQUEST;
do {
more_data.more_data = 0;
more_data.len = 0;
if (pdvobj->SdioRxFIFOSize == 0)
{
u16 val = 0;
//s32 ret; //LZM_TODO
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s, %d, read RXFIFOsize again size=%d\n", __FUNCTION__, __LINE__, pdvobj->SdioRxFIFOSize));
val = rtw_read16(padapter, LOCAL_REG_RX0_REQ_LEN_1_BYTE);
//if (!ret) {
pdvobj->SdioRxFIFOSize = val;
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: RX_REQUEST, read RXFIFOsize again size=%d\n", __func__, pdvobj->SdioRxFIFOSize));
//} else {
// RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s: RX_REQUEST, read RXFIFOsize ERROR!!\n", __func__));
//}
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s, %d, read RXFIFOsize again size=%d\n", __FUNCTION__, __LINE__, pdvobj->SdioRxFIFOSize));
}
if (pdvobj->SdioRxFIFOSize != 0)
{
#ifdef RTL8723A_SDIO_LOOPBACK
sd_recv_loopback(padapter, pdvobj->SdioRxFIFOSize);
#else
if (sdio_hisr & HCI_HISR_RXFOVW)
RT_TRACE(_module_hci_ops_c_, _drv_info_, ("%s RXFOVW RX\n", __func__));
precvbuf = rtw_recv_rxfifo(padapter, pdvobj->SdioRxFIFOSize, &more_data);
if (precvbuf)
rtw_rxhandler(padapter, precvbuf);
if (more_data.more_data) {
pdvobj->SdioRxFIFOSize = more_data.len;
} else {
pdvobj->SdioRxFIFOSize = 0;
}
#endif
//If Rx_request ISR is set, execute receive tasklet (sdio_hisr & SPI_HISR_RX_REQUEST)
#if defined(CONFIG_ISR_THREAD_MODE_INTERRUPT) && defined(CONFIG_RECV_TASKLET_THREAD)
rtw_wakeup_task(&padapter->recvtasklet_thread);
#endif
}
#ifdef CONFIG_INTERRUPT_BASED_TXBCN
{
//Prevent BCN update not realtime in ap mode - Alex Fang
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
if((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) && (pmlmepriv->update_bcn == _TRUE))
break;
}
#endif
} while (more_data.more_data || pdvobj->SdioRxFIFOSize);
#ifdef PLATFORM_LINUX
#ifdef CONFIG_GSPI_HCI
tasklet_schedule(&padapter->recvpriv.recv_tasklet);
#endif
#endif
}
}
void spi_int_hdl(PADAPTER padapter)
{
struct dvobj_priv *pdvobj = padapter->dvobj;
u32 sdio_hisr = 0;
//s32 ret;
if ((padapter->bDriverStopped == _TRUE) ||
(padapter->bSurpriseRemoved == _TRUE))
return;
sdio_hisr = rtw_read32(padapter, LOCAL_REG_HISR);//, &ret);
//if (!ret) {
// RT_TRACE(_module_hci_ops_c_, _drv_err_, ("%s: read SDIO_REG_HISR FAIL!!\n", __func__));
// return;
//}
pdvobj->SdioRxFIFOSize = rtw_read16(padapter, LOCAL_REG_RX0_REQ_LEN_1_BYTE);//, &ret);
//if (!ret) {
// RT_TRACE(_module_hci_ops_c_, _drv_err_, ("%s: read SPI_REG_RX0_REQ_LEN FAIL!!\n", __func__));
// return;
//}
if (sdio_hisr & pdvobj->sdio_himr)
{
u32 v32;
sdio_hisr &= pdvobj->sdio_himr;
// clear HISR
v32 = sdio_hisr & MASK_SPI_HISR_CLEAR;
if (v32) {
rtw_write32(padapter, LOCAL_REG_HISR, v32);//, &ret);
}
spi_int_dpc(padapter, sdio_hisr);
} else {
//RT_TRACE(_module_hci_ops_c_, _drv_err_,
// ("%s: HISR(0x%08x) and HIMR(0x%08x) not match!\n",
// __FUNCTION__, sdio_hisr, pdvobj->sdio_himr));
}
}
#endif

193
USDK/component/common/drivers/wlan/realtek/src/hci/sdio/sdio_spec.h Normal file
View file

@ -0,0 +1,193 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*******************************************************************************/
#ifndef __GSDIO_SPEC_H__
#define __GSDIO_SPEC_H__
#define SPI_LOCAL_DOMAIN 0x0
#define WLAN_IOREG_DOMAIN 0x8
#define FW_FIFO_DOMAIN 0x4
#define TX_HIQ_DOMAIN 0xc
#define TX_MIQ_DOMAIN 0xd
#define TX_LOQ_DOMAIN 0xe
#define RX_RXFIFO_DOMAIN 0x1f
//IO Bus domain address mapping
#define DEFUALT_OFFSET 0x0
#define SPI_LOCAL_OFFSET 0x10250000
#define WLAN_IOREG_OFFSET 0x10260000
#define FW_FIFO_OFFSET 0x10270000
#define TX_HIQ_OFFSET 0x10310000
#define TX_MIQ_OFFSET 0x1032000
#define TX_LOQ_OFFSET 0x10330000
#define RX_RXOFF_OFFSET 0x10340000
#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13]
#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13]
#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13]
#define WLAN_TX_EXQ_DEVICE_ID 3 // 0b[16], 011b[15:13]
#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13]
#define WLAN_IOREG_DEVICE_ID 8 // 1b[16]
//SPI Tx Free Page Index
#define HI_QUEUE_IDX 0
#define MID_QUEUE_IDX 1
#define LOW_QUEUE_IDX 2
#define PUBLIC_QUEUE_IDX 3
#define MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ
#define MAX_RX_QUEUE 1
//SPI Local registers
#define SPI_REG_TX_CTRL (SPI_LOCAL_OFFSET | 0x0000) // SPI Tx Control
#define SPI_REG_STATUS_RECOVERY (SPI_LOCAL_OFFSET | 0x0004)
#define SPI_REG_INT_TIMEOUT (SPI_LOCAL_OFFSET | 0x0006)
#define SPI_REG_HIMR (SPI_LOCAL_OFFSET | 0x0014) // SPI Host Interrupt Mask
#define SPI_REG_HISR (SPI_LOCAL_OFFSET | 0x0018) // SPI Host Interrupt Service Routine
#define SPI_REG_RX0_REQ_LEN (SPI_LOCAL_OFFSET | 0x001C) // RXDMA Request Length
#define SPI_REG_FREE_TXPG (SPI_LOCAL_OFFSET | 0x0020) // Free Tx Buffer Page
#define SPI_REG_HCPWM1 (SPI_LOCAL_OFFSET | 0x0024) // HCI Current Power Mode 1
#define SPI_REG_HCPWM2 (SPI_LOCAL_OFFSET | 0x0026) // HCI Current Power Mode 2
#define SPI_REG_HTSFR_INFO (SPI_LOCAL_OFFSET | 0x0030) // HTSF Informaion
#define SPI_REG_HRPWM1 (SPI_LOCAL_OFFSET | 0x0080) // HCI Request Power Mode 1
#define SPI_REG_HRPWM2 (SPI_LOCAL_OFFSET | 0x0082) // HCI Request Power Mode 2
#define SPI_REG_HPS_CLKR (SPI_LOCAL_OFFSET | 0x0084) // HCI Power Save Clock
#define SPI_REG_HSUS_CTRL (SPI_LOCAL_OFFSET | 0x0086) // SPI HCI Suspend Control
#define SPI_REG_HIMR_ON (SPI_LOCAL_OFFSET | 0x0090) //SPI Host Extension Interrupt Mask Always
#define SPI_REG_HISR_ON (SPI_LOCAL_OFFSET | 0x0091) //SPI Host Extension Interrupt Status Always
#define SPI_REG_CFG (SPI_LOCAL_OFFSET | 0x00F0) //SPI Configuration Register
#define LOCAL_REG_TX_CTRL (SPI_REG_TX_CTRL |SPI_LOCAL_OFFSET)
#define LOCAL_REG_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY |SPI_LOCAL_OFFSET)
#define LOCAL_REG_INT_TIMEOUT (SPI_REG_INT_TIMEOUT |SPI_LOCAL_OFFSET)
#define LOCAL_REG_HIMR (SPI_REG_HIMR |SPI_LOCAL_OFFSET)
#define LOCAL_REG_HISR (SPI_REG_HISR |SPI_LOCAL_OFFSET)
#define LOCAL_REG_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN |SPI_LOCAL_OFFSET)
#define LOCAL_REG_FREE_TXPG (SPI_REG_FREE_TXPG |SPI_LOCAL_OFFSET)
#define LOCAL_REG_HRPWM1 (SPI_REG_HRPWM1 |SPI_LOCAL_OFFSET)
#define LOCAL_REG_HCPWM1 (SPI_REG_HCPWM1 |SPI_LOCAL_OFFSET)
#define HCI_HIMR_DISABLED 0
//SPI HIMR MASK diff with SDIO
#define HCI_HISR_RX_REQUEST BIT(0)
#define HCI_HISR_AVAL BIT(1)
#define HCI_HISR_TXERR BIT(2)
#define HCI_HISR_RXERR BIT(3)
#define HCI_HISR_TXFOVW BIT(4)
#define HCI_HISR_RXFOVW BIT(5)
#define HCI_HISR_TXBCNOK BIT(6)
#define HCI_HISR_TXBCNERR BIT(7)
#define HCI_HISR_BCNERLY_INT BIT(16)
#define HCI_HISR_C2HCMD BIT(17)
#define HCI_HISR_CPWM1 BIT(18)
#define HCI_HISR_CPWM2 BIT(19)
#define HCI_HISR_HSISR_IND BIT(20)
#define HCI_HISR_GTINT3_IND BIT(21)
#define HCI_HISR_GTINT4_IND BIT(22)
#define HCI_HISR_PSTIMEOUT BIT(23)
#define HCI_HISR_OCPINT BIT(24)
#define HCI_HISR_ATIMEND BIT(25)
#define HCI_HISR_ATIMEND_E BIT(26)
#define HCI_HISR_CTWEND BIT(27)
//SPI HIMR MASK diff with SDIO
#define HCI_HIMR_RX_REQUEST BIT(0)
#define HCI_HIMR_AVAL BIT(1)
#define HCI_HIMR_TXERR BIT(2)
#define HCI_HIMR_RXERR BIT(3)
#define HCI_HIMR_TXFOVW BIT(4)
#define HCI_HIMR_RXFOVW BIT(5)
#define HCI_HIMR_TXBCNOK BIT(6)
#define HCI_HIMR_TXBCNERR BIT(7)
#define HCI_HIMR_BCNERLY_INT BIT(16)
#define HCI_HIMR_ATIMEND BIT(17)
#define HCI_HIMR_ATIMEND_E BIT(18)
#define HCI_HIMR_CTWEND BIT(19)
#define HCI_HIMR_C2HCMD BIT(20)
#define HCI_HIMR_CPWM1 BIT(21)
#define HCI_HIMR_CPWM2 BIT(22)
#define HCI_HIMR_HSISR_IND BIT(23)
#define HCI_HIMR_GTINT3_IND BIT(24)
#define HCI_HIMR_GTINT4_IND BIT(25)
#define HCI_HIMR_PSTIMEOUT BIT(26)
#define HCI_HIMR_OCPINT BIT(27)
#define HCI_HIMR_TSF_BIT32_TOGGLE BIT(29)
#define MASK_SPI_HISR_CLEAR (HCI_HIMR_TXERR |\
HCI_HIMR_RXERR |\
HCI_HIMR_TXFOVW |\
HCI_HIMR_RXFOVW |\
HCI_HIMR_TXBCNOK |\
HCI_HIMR_TXBCNERR |\
HCI_HIMR_C2HCMD |\
HCI_HIMR_CPWM1 |\
HCI_HIMR_CPWM2 |\
HCI_HIMR_HSISR_IND |\
HCI_HIMR_GTINT3_IND |\
HCI_HIMR_GTINT4_IND |\
HCI_HIMR_PSTIMEOUT |\
HCI_HIMR_OCPINT)
#define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)//(x<<(unsigned int)24)
#define REG_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
#define REG_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
#define REG_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
#define REG_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
#define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)//(x<<(unsigned int)24)
//#define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16)
#define FIFO_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0)
#define FIFO_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5)
#define FIFO_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7)
//get status dword0
#define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8)
#define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6)
#define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6)
#define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6)
#define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6)
//get status dword1
#define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8)
#define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8)
#define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1)
#define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1)
#define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16)
#define RXDESC_SIZE 24
#define TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page
#define TX_FIFO_PAGE_SZ 128
struct spi_more_data {
unsigned long more_data;
unsigned long len;
};
extern BUS_DRV_OPS_T bus_driver_ops;
extern u8 spi_query_status_info(struct dvobj_priv *pdvobj);
extern void sdio_set_intf_ops(struct _io_ops *pops);
#endif //__GSPI_SPEC_H__

161
USDK/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_intfs.h Normal file
View file

@ -0,0 +1,161 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __FREERTOS_INTFS_H_
#define __FREERTOS_INTFS_H_
//TODO
#if 0
struct intf_priv {
u8 *intf_dev;
u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64
u32 max_xmitsz; //USB2.0: unlimited, SDIO:512
u32 max_recvsz; //USB2.0: unlimited, SDIO:512
volatile u8 *io_rwmem;
volatile u8 *allocated_io_rwmem;
u32 io_wsz; //unit: 4bytes
u32 io_rsz;//unit: 4bytes
u8 intf_status;
void (*_bus_io)(u8 *priv);
/*
Under Sync. IRP (SDIO/USB)
A protection mechanism is necessary for the io_rwmem(read/write protocol)
Under Async. IRP (SDIO/USB)
The protection mechanism is through the pending queue.
*/
_mutex ioctl_mutex;
#ifdef PLATFORM_LINUX
#ifdef CONFIG_USB_HCI
// when in USB, IO is through interrupt in/out endpoints
struct usb_device *udev;
PURB piorw_urb;
u8 io_irp_cnt;
u8 bio_irp_pending;
_sema io_retevt;
_timer io_timer;
u8 bio_irp_timeout;
u8 bio_timer_cancel;
#endif
#endif
#ifdef PLATFORM_OS_XP
#ifdef CONFIG_SDIO_HCI
// below is for io_rwmem...
PMDL pmdl;
PSDBUS_REQUEST_PACKET sdrp;
PSDBUS_REQUEST_PACKET recv_sdrp;
PSDBUS_REQUEST_PACKET xmit_sdrp;
PIRP piorw_irp;
#endif
#ifdef CONFIG_USB_HCI
PURB piorw_urb;
PIRP piorw_irp;
u8 io_irp_cnt;
u8 bio_irp_pending;
_sema io_retevt;
#endif
#endif
};
#ifdef CONFIG_R871X_TEST
int rtw_start_pseudo_adhoc(_adapter *padapter);
int rtw_stop_pseudo_adhoc(_adapter *padapter);
#endif
#endif //#if 0
typedef struct _driver_priv {
int drv_registered;
_mutex hw_init_mutex;
#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT)
//global variable
_mutex h2c_fwcmd_mutex;
_mutex setch_mutex;
_mutex setbw_mutex;
#endif
} drv_priv, *pdrv_priv;
struct net_device *rtw_init_netdev(_adapter *padapter);
void rtw_os_indicate_disconnect( _adapter *adapter );
#ifdef CONFIG_PROC_DEBUG
void rtw_proc_init_one(struct net_device *dev);
void rtw_proc_remove_one(struct net_device *dev);
#else
//static void should be declared in .c file
//proc is not supported in freertos
//static void rtw_proc_init_one(struct net_device *dev){}
//static void rtw_proc_remove_one(struct net_device *dev){}
#define rtw_proc_init_one(dev)
#define rtw_proc_remove_one(dev)
#endif
extern int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen);
extern void rtw_os_indicate_connect(_adapter *adapter);
extern void indicate_wx_custom_event(_adapter *padapter, char *msg);
extern int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);
extern void netdev_lwip_post_sleep_processing(void);
extern void wireless_send_event(struct net_device *dev, unsigned int cmd, union iwreq_data *wrqu, char *extra);
#ifdef CONFIG_CONCURRENT_MODE
struct _io_ops;
_adapter *rtw_drv_if2_init(_adapter *primary_padapter, char *name, void (*set_intf_ops)(struct _io_ops *pops));
void rtw_drv_if2_free(_adapter *pbuddy_padapter);
#endif
#if defined(CONFIG_ISR_THREAD_MODE_POLLING) || defined(CONFIG_ISR_THREAD_MODE_INTERRUPT)
extern thread_return rtw_interrupt_thread(thread_context context);
#endif
#ifdef CONFIG_RECV_TASKLET_THREAD
extern thread_return rtw_recv_tasklet(thread_context context);
#endif
#ifdef CONFIG_XMIT_TASKLET_THREAD
extern thread_return rtw_xmit_tasklet(thread_context context);
#endif
extern struct net_device *rtw_drv_probe(struct net_device* parent_dev, u32 mode); //Wlan driver init entry
extern void rtw_drv_entry(void);
extern void rtw_drv_halt(void);
extern int rtw_dev_remove(struct net_device *pnetdev);
extern int rtw_ioctl(struct net_device *dev, struct iwreq *rq, int cmd);
#if defined(CONFIG_LX_HCI)
u32 lextra_bus_dma_Interrupt (void* data);
#endif
#endif //__FREERTOS_INTFS_H_

55
USDK/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_recv.h Normal file
View file

@ -0,0 +1,55 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __FREERTOS_RECV_H_
#define __FREERTOS_RECV_H_
extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
extern void _rtw_free_recv_priv (struct recv_priv *precvpriv);
extern s32 rtw_recv_entry(union recv_frame *precv_frame);
extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame);
extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt);
extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame);
#if BAD_MIC_COUNTERMEASURE
extern void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup);
#endif
int rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter);
void rtw_free_recv_priv (struct recv_priv *precvpriv);
int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter);
int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe);
void rtw_os_recv_resource_free(struct recv_priv *precvpriv);
int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf);
int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf);
void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf);
void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl);
void rltk_netif_rx(struct sk_buff *skb);
#endif //__FREERTOS_RECV_H_

72
USDK/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_skbuff.h Normal file
View file

@ -0,0 +1,72 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef _FREERTOS_SKBUFF_H_
#define _FREERTOS_SKBUFF_H_
#if (RTL8195A_SUPPORT == 1)
// For Lextra(PCI-E like interface), RX buffer along with its skb is required to be
// pre-allocation and set into rx buffer descriptor ring during initialization.
#if (SKB_PRE_ALLOCATE_RX==1)
#define MAX_SKB_BUF_NUM (8 + 4) //tx+rx (8 + RX_Q_DESC_NUM) Reduce rx skb number due to memory limitation
#define MAX_LOCAL_SKB_NUM (10 + 18) //tx+rx
#else
#if WIFI_LOGO_CERTIFICATION
#define MAX_SKB_BUF_NUM 10 //tx+rx, ping 10k test
#elif defined(CONFIG_INIC_EN)&&(CONFIG_INIC_EN==1) //For iNIC throughput request
#define MAX_SKB_BUF_NUM 59
#else
#define MAX_SKB_BUF_NUM 8 //tx+rx
#endif
#define MAX_LOCAL_SKB_NUM (MAX_SKB_BUF_NUM + 2) //tx+rx, +2: AP mode broadcast
#endif
#elif (RTL8711B_SUPPORT == 1)
#if (SKB_PRE_ALLOCATE_RX==1)
#define MAX_SKB_BUF_NUM (8 + 4) //tx+rx (8 + RX_Q_DESC_NUM) Reduce rx skb number due to memory limitation
#define MAX_LOCAL_SKB_NUM (10 + 18) //tx+rx
#else
#if WIFI_LOGO_CERTIFICATION
#define MAX_SKB_BUF_NUM 10 //tx+rx, ping 10k test
#elif defined(CONFIG_INIC_EN)&&(CONFIG_INIC_EN==1) //For iNIC throughput request
#define MAX_SKB_BUF_NUM 59
#else
#define MAX_SKB_BUF_NUM 8 //tx+rx
#endif
#define MAX_LOCAL_SKB_NUM (MAX_SKB_BUF_NUM + 2) //tx+rx, +2: AP mode broadcast
#endif
#else
#ifndef CONFIG_DONT_CARE_TP
#ifndef CONFIG_HIGH_TP
#define MAX_LOCAL_SKB_NUM 10
#define MAX_SKB_BUF_NUM 7
#else
#define MAX_LOCAL_SKB_NUM 100
#define MAX_SKB_BUF_NUM 100
#endif
#else
#define MAX_LOCAL_SKB_NUM 10
#define MAX_TX_SKB_BUF_NUM 6
#define MAX_RX_SKB_BUF_NUM 1
#endif
#endif
extern int max_local_skb_num;
extern int max_skb_buf_num;
#endif

62
USDK/component/common/drivers/wlan/realtek/src/osdep/freertos/freertos_xmit.h Normal file
View file

@ -0,0 +1,62 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __FREERTOS_XMIT_H_
#define __FREERTOS_XMIT_H_
struct pkt_file {
_pkt *pkt;
SIZE_T pkt_len; //the remainder length of the open_file
_buffer *cur_buffer;
u8 *buf_start;
u8 *cur_addr;
SIZE_T buf_len;
};
//Decrease xmit frame due to memory limitation - Alex Fang
#if USE_XMIT_EXTBUFF
#define NR_XMITFRAME 16 //NR_XMITBUFF + NR_XMIT_EXTBUFF
#else
#ifndef CONFIG_HIGH_TP
//#define NR_XMITFRAME 8
#define NR_XMITFRAME 6 //Decrease recv frame due to memory limitation - YangJue
#else
#define NR_XMITFRAME 100
#endif
#endif
extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev);
extern void rtw_os_xmit_schedule(_adapter *padapter);
extern int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 alloc_sz);
extern void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 free_sz);
extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib);
extern uint rtw_remainder_len(struct pkt_file *pfile);
extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile);
extern uint _rtw_pktfile_read (struct pkt_file *pfile, u8 *rmem, uint rlen);
extern sint rtw_endofpktfile (struct pkt_file *pfile);
extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt);
extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe);
#endif //__FREERTOS_XMIT_H_

460
USDK/component/common/drivers/wlan/realtek/src/osdep/freertos/wrapper.h Normal file
View file

@ -0,0 +1,460 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************
* Wrapper provide a linux-like interface
************************************************************************/
#ifndef __WRAPPER_H__
#define __WRAPPER_H__
//----- ------------------------------------------------------------------
// Include Files
//----- ------------------------------------------------------------------
#include <stdio.h>
#include <string.h>
#include "wireless.h"
#include <skbuff.h>
#ifdef PLATFORM_FREERTOS
#include "freertos_service.h"
#elif defined(PLATFORM_CMSIS_RTOS)
#include "rtx_service.h"
#endif
#ifndef __LIST_H
#warning "DLIST_NOT_DEFINE!!!!!!"
//----- ------------------------------------------------------------------
// Linled List
//----- ------------------------------------------------------------------
/*
* Simple doubly linked list implementation.
*
* Some of the internal functions ("__xxx") are useful when
* manipulating whole lists rather than single entries, as
* sometimes we already know the next/prev entries and we can
* generate better code by using them directly rather than
* using the generic single-entry routines.
*/
// struct list_head {
// struct list_head *next, *prev;
// };
#define LIST_HEAD_INIT(name) { &(name), &(name) }
#define INIT_LIST_HEAD(ptr) do { \
(ptr)->next = (ptr); (ptr)->prev = (ptr); \
} while (0)
/*
* Insert a new entry between two known consecutive entries.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline void __list_add(struct list_head * new,
struct list_head * prev,
struct list_head * next)
{
next->prev = new;
new->next = next;
new->prev = prev;
prev->next = new;
}
/*
* Delete a list entry by making the prev/next entries
* point to each other.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline void __list_del(struct list_head * prev,
struct list_head * next)
{
next->prev = prev;
prev->next = next;
}
/**
* list_del - deletes entry from list.
* @entry: the element to delete from the list.
* Note: list_empty on entry does not return true after this, the entry is in an undefined state.
*/
static __inline void list_del(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
}
/**
* list_del_init - deletes entry from list and reinitialize it.
* @entry: the element to delete from the list.
*/
static __inline void list_del_init(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
INIT_LIST_HEAD(entry);
}
/**
* list_empty - tests whether a list is empty
* @head: the list to test.
*/
static __inline int list_empty(struct list_head *head)
{
return head->next == head;
}
/**
* list_splice - join two lists
* @list: the new list to add.
* @head: the place to add it in the first list.
*/
static __inline void list_splice(struct list_head *list, struct list_head *head)
{
struct list_head *first = list->next;
if (first != list) {
struct list_head *last = list->prev;
struct list_head *at = head->next;
first->prev = head;
head->next = first;
last->next = at;
at->prev = last;
}
}
void list_add(struct list_head *new, struct list_head *head);
void list_add_tail(struct list_head *new, struct list_head *head);
#endif
extern void save_and_cli(void);
extern void restore_flags(void);
//----- ------------------------------------------------------------------
// SKB Operation
//----- ------------------------------------------------------------------
#define SMP_CACHE_BYTES 4
#define SKB_DATA_ALIGN(X) (((X) + (SMP_CACHE_BYTES - 1)) & ~(SMP_CACHE_BYTES - 1))
// Consideration for SKB size
// Tx: [INTF_CMD][TX_DESC][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][INTF_STATUS]
// Since SKB is used to accept ethernet packet from upper layer, SKB length of WLAN_MAX_ETHFRM_LEN
// (= 1514) is enough. But since SKB is also used to get spi receive packet, overall buffer space
// should be taken into consideration.
// RX: [INTF_CMD][RX_DESC][Drv_Info][WLAN_HDR][QoS][IV][SNAP][Data][MIC][ICV][CRC][INTF_STATUS]
//
// 32: Driver_Info that carry phy related information for each packets. Required only for receive case.
// WLAN_MAX_ETHFRM_LEN : May not be required because WLAN_HEADER +SNAP can totally
// cover ethernet header. Keep in only for safety.
//
// **Notes** SDIO requires 512 blocks r/w, so 512*4 = 2048 is required.
// 2003/12/26. The value is reduced from 2048 to 1658 for GSPI
// 2014/02/05. The value is 1650 for 8195A LX_BUS
#define SKB_RESERVED_FOR_SAFETY 0
#define SKB_WLAN_TX_EXTRA_LEN (TXDESC_SIZE + WLAN_HDR_A4_QOS_LEN + WLAN_MAX_IV_LEN + WLAN_SNAP_HEADER - WLAN_ETHHDR_LEN)
#define RX_DRIVER_INFO 32
#if (defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI)
#define HAL_INTERFACE_OVERHEAD_SKB_DATA 12 //HAL_INTERFACE_CMD (4) + HAL_INTERFACE_STATUS (8)
#elif defined(CONFIG_LX_HCI)
#define HAL_INTERFACE_OVERHEAD_SKB_DATA 0
#endif
#if defined CONFIG_GSPI_HCI || defined CONFIG_SDIO_HCI || defined(CONFIG_LX_HCI)
#if defined(CONFIG_RTL8195A) || defined(CONFIG_RTL8711B)
#if defined(CONFIG_MP_INCLUDED)
#ifdef CONFIG_DONT_CARE_TP
#define MAX_RX_PKT_LIMIT ((WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN + 511) / 512) // 4, for lxbus
#else
#define MAX_RX_PKT_LIMIT ((WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN + 511) / 512) // 4, for lxbus
#endif
#define MAX_RX_PKT_SIZE MAX_RX_PKT_LIMIT*512 // MAX_SKB_BUF_SIZE = 0+32+40+512*4+0 = 2120
#else
#ifdef CONFIG_DONT_CARE_TP
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN
#else
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN // MAX_RX_PKT_SIZE = 64+1514 = 1578
#endif
#define MAX_RX_PKT_LIMIT ((MAX_RX_PKT_SIZE + 511) / 512) // ((1578 + 512) / 512) = 4
#endif
#else
#ifdef CONFIG_DONT_CARE_TP
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_RX_ETHFRM_LEN
#else
#define MAX_RX_PKT_SIZE WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_ETHFRM_LEN
#endif
#endif
#ifdef CONFIG_DONT_CARE_TP
#define MAX_TX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
WLAN_MAX_PROTOCOL_OVERHEAD + WLAN_MAX_TX_ETHFRM_LEN +\
SKB_RESERVED_FOR_SAFETY)
#define MAX_RX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
MAX_RX_PKT_SIZE +\
SKB_RESERVED_FOR_SAFETY)
#else
#define MAX_SKB_BUF_SIZE (HAL_INTERFACE_OVERHEAD_SKB_DATA+RX_DRIVER_INFO+\
((TXDESC_SIZE>RXDESC_SIZE)? TXDESC_SIZE:RXDESC_SIZE) +\
MAX_RX_PKT_SIZE +\
SKB_RESERVED_FOR_SAFETY) // 0+32+40+1578+0 = 1650
#endif
#else
#define MAX_SKB_BUF_SIZE 2048
#endif
#if 0
struct sk_buff_head {
struct list_head *next, *prev;
u32 qlen;
};
struct sk_buff {
/* These two members must be first. */
struct sk_buff *next; /* Next buffer in list */
struct sk_buff *prev; /* Previous buffer in list */
struct sk_buff_head *list; /* List we are on */
unsigned char *head; /* Head of buffer */
unsigned char *data; /* Data head pointer */
unsigned char *tail; /* Tail pointer */
unsigned char *end; /* End pointer */
struct net_device *dev; /* Device we arrived on/are leaving by */
unsigned int len; /* Length of actual data */
};
/**
* skb_put - add data to a buffer
* @skb: buffer to use
* @len: amount of data to add
*
* This function extends the used data area of the buffer. If this would
* exceed the total buffer size the kernel will panic. A pointer to the
* first byte of the extra data is returned.
*/
static __inline__ unsigned char *skb_put(struct sk_buff *skb, unsigned int len)
{
unsigned char *tmp=skb->tail;
skb->tail+=len;
skb->len+=len;
if(skb->tail>skb->end) {
ASSERT(0);
}
return tmp;
}
static __inline__ unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len)
{
skb->len-=len;
skb->data = (unsigned char *)(((unsigned int)skb->data) + len);
return skb->data;
}
/**
* skb_reserve - adjust headroom
* @skb: buffer to alter
* @len: bytes to move
*
* Increase the headroom of an empty &sk_buff by reducing the tail
* room. This is only allowed for an empty buffer.
*/
static __inline__ void skb_reserve(struct sk_buff *skb, unsigned int len)
{
skb->data+=len;
skb->tail+=len;
}
static __inline__ void skb_queue_head_init(struct sk_buff_head *list)
{
list->prev = (struct list_head *)list;
list->next = (struct list_head *)list;
list->qlen = 0;
}
/**
* __skb_queue_tail - queue a buffer at the list tail
* @list: list to use
* @newsk: buffer to queue
*
* Queue a buffer at the end of a list. This function takes no locks
* and you must therefore hold required locks before calling it.
*
* A buffer cannot be placed on two lists at the same time.
*/
static __inline__ void __skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk)
{
struct sk_buff *prev, *next;
newsk->list = list;
list->qlen++;
next = (struct sk_buff *)list;
prev = next->prev;
newsk->next = next;
newsk->prev = prev;
next->prev = newsk;
prev->next = newsk;
}
/**
* skb_queue_tail - queue a buffer at the list tail
* @list: list to use
* @newsk: buffer to queue
*
* Queue a buffer at the tail of the list. This function takes the
* list lock and can be used safely with other locking &sk_buff functions
* safely.
*
* A buffer cannot be placed on two lists at the same time.
*/
static __inline__ void skb_queue_tail(struct sk_buff_head *list, struct sk_buff *newsk)
{
save_and_cli();
__skb_queue_tail(list, newsk);
restore_flags();
}
static __inline__ void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len)
{
skb->head = buf;
skb->data = buf;
skb->tail = buf;
skb->end = buf + len;
}
static __inline__ unsigned char *skb_tail_pointer(const struct sk_buff *skb)
{
return skb->tail;
}
static __inline__ void skb_reset_tail_pointer(struct sk_buff *skb)
{
skb->tail = skb->data;
}
static __inline__ void skb_set_tail_pointer(struct sk_buff *skb, const int offset)
{
skb->tail = skb->data + offset;
}
static __inline__ unsigned char *skb_end_pointer(const struct sk_buff *skb)
{
return skb->end;
}
#endif
/*
* External functions
*/
struct net_device;
extern void kfree_skb_chk_key(struct sk_buff *skb, struct net_device *root_dev);
#ifdef CONFIG_TRACE_SKB
extern void show_skb(void);
extern int _set_skb_list_flag(struct sk_buff *skb, unsigned int queueflag);
extern void dump_skb_list(void);
#define set_skb_list_flag(skb, queueflag) \
(\
_set_skb_list_flag((skb), queueflag), \
(skb) ? (skb)->funcname[(skb)->list_idx] = __FUNCTION__:NULL \
)
extern int _clear_skb_list_flag(struct sk_buff *skb, unsigned int queueflag);
#define clear_skb_list_flag(skb, queueflag) \
(\
_clear_skb_list_flag((skb), queueflag), \
(skb) ? (skb)->funcname[(skb)->list_idx] = __FUNCTION__ : NULL \
)
#define dev_kfree_skb_any(trx, holder, skb) \
do{\
clear_skb_list_flag(skb, SKBLIST_##trx##holder##_MASK);\
set_skb_list_flag(skb, SKBLIST_POOL);\
kfree_skb_chk_key(skb, skb->dev);\
}while (0)
#else
#define dev_kfree_skb_any(skb) kfree_skb_chk_key(skb, skb->dev)
#endif
extern struct sk_buff *dev_alloc_skb(unsigned int length, unsigned int reserve_len);
extern struct sk_buff *skb_clone(struct sk_buff *skb, int gfp_mask);
extern struct sk_buff *skb_copy(const struct sk_buff *skb, int gfp_mask, unsigned int reserve_len);
extern unsigned char *skb_pull(struct sk_buff *skb, unsigned int len);
//----- ------------------------------------------------------------------
// Device structure
//----- ------------------------------------------------------------------
struct net_device_stats {
unsigned long rx_packets; /* total packets received */
unsigned long tx_packets; /* total packets transmitted */
unsigned long rx_dropped; /* no space in linux buffers */
unsigned long tx_dropped; /* no space available in linux */
unsigned long rx_bytes; /* total bytes received */
unsigned long tx_bytes; /* total bytes transmitted */
unsigned long rx_overflow; /* rx fifo overflow count */
};
struct net_device {
char name[16];
void *priv; /* pointer to private data */
unsigned char dev_addr[6]; /* set during bootup */
int (*init)(void);
int (*open)(struct net_device *dev);
int (*stop)(struct net_device *dev);
int (*hard_start_xmit)(struct sk_buff *skb, struct net_device *dev);
int (*do_ioctl)(struct net_device *dev, struct iwreq *ifr, int cmd);
struct net_device_stats* (*get_stats)(struct net_device *dev);
};
typedef struct {
struct net_device *dev; /* Binding wlan driver netdev */
void *skb; /* pending Rx packet */
unsigned int tx_busy;
unsigned int rx_busy;
unsigned char enable;
unsigned char mac[6];
} Rltk_wlan_t;
#define netdev_priv(dev) dev->priv
extern struct net_device *alloc_etherdev(int sizeof_priv);
void free_netdev(struct net_device *dev);
int dev_alloc_name(struct net_device *net_dev, const char *ifname);
//----- ------------------------------------------------------------------
// Timer Operation
//----- ------------------------------------------------------------------
void init_timer(struct timer_list *timer);
void mod_timer(struct timer_list *timer, u32 delay_time_ms);
void cancel_timer_ex(struct timer_list * timer);
void del_timer_sync(struct timer_list * timer);
void init_timer_wrapper(void);
void deinit_timer_wrapper(void);
void rtw_init_timer(_timer *ptimer, void *adapter, TIMER_FUN pfunc,void* cntx, const char *name);
void rtw_set_timer(_timer *ptimer,u32 delay_time);
u8 rtw_cancel_timer(_timer *ptimer);
void rtw_del_timer(_timer *ptimer);
#endif //__WRAPPER_H__

278
USDK/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.c Normal file
View file

@ -0,0 +1,278 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
//#define _LWIP_INTF_C_
#include <autoconf.h>
#include <lwip_intf.h>
#include <lwip/netif.h>
#if !DEVICE_EMAC
#include <lwip_netconf.h>
#include <ethernetif.h>
#endif
#include <osdep_service.h>
#include <wifi/wifi_util.h>
//----- ------------------------------------------------------------------
// External Reference
//----- ------------------------------------------------------------------
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
extern struct netif *xnetif[];
#else
extern struct netif xnetif[]; //LWIP netif
#endif
#endif
/**
* rltk_wlan_set_netif_info - set netif hw address and register dev pointer to netif device
* @idx_wlan: netif index
* 0 for STA only or SoftAP only or STA in STA+SoftAP concurrent mode,
* 1 for SoftAP in STA+SoftAP concurrent mode
* @dev: register netdev pointer to LWIP. Reserved.
* @dev_addr: set netif hw address
*
* Return Value: None
*/
void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr)
{
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
rtw_memcpy(xnetif[idx_wlan]->hwaddr, dev_addr, 6);
#else
rtw_memcpy(xnetif[idx_wlan].hwaddr, dev_addr, 6);
xnetif[idx_wlan].state = dev;
#endif
#endif
}
/**
* rltk_wlan_send - send IP packets to WLAN. Called by low_level_output().
* @idx: netif index
* @sg_list: data buffer list
* @sg_len: size of each data buffer
* @total_len: total data len
*
* Return Value: None
*/
int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len)
{
#if (CONFIG_LWIP_LAYER == 1)
struct eth_drv_sg *last_sg;
struct sk_buff *skb = NULL;
int ret = 0;
if(idx == -1){
DBG_ERR("netif is DOWN");
return -1;
}
DBG_TRACE("%s is called", __FUNCTION__);
save_and_cli();
if(rltk_wlan_check_isup(idx))
rltk_wlan_tx_inc(idx);
else {
DBG_ERR("netif is DOWN");
restore_flags();
return -1;
}
restore_flags();
skb = rltk_wlan_alloc_skb(total_len);
if (skb == NULL) {
//DBG_ERR("rltk_wlan_alloc_skb() for data len=%d failed!", total_len);
ret = -1;
goto exit;
}
for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
rtw_memcpy(skb->tail, (void *)(sg_list->buf), sg_list->len);
skb_put(skb, sg_list->len);
}
rltk_wlan_send_skb(idx, skb);
exit:
save_and_cli();
rltk_wlan_tx_dec(idx);
restore_flags();
return ret;
#endif
}
/**
* rltk_wlan_recv - indicate packets to LWIP. Called by ethernetif_recv().
* @idx: netif index
* @sg_list: data buffer list
* @sg_len: size of each data buffer
*
* Return Value: None
*/
void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len)
{
#if (CONFIG_LWIP_LAYER == 1)
struct eth_drv_sg *last_sg;
struct sk_buff *skb;
DBG_TRACE("%s is called", __FUNCTION__);
if (!rltk_wlan_check_isup(idx))
return;
if(idx == -1){
DBG_ERR("skb is NULL");
return;
}
skb = rltk_wlan_get_recv_skb(idx);
DBG_ASSERT(skb, "No pending rx skb");
for (last_sg = &sg_list[sg_len]; sg_list < last_sg; ++sg_list) {
if (sg_list->buf != 0) {
rtw_memcpy((void *)(sg_list->buf), skb->data, sg_list->len);
skb_pull(skb, sg_list->len);
}
}
#endif
}
int netif_is_valid_IP(int idx, unsigned char *ip_dest)
{
#if CONFIG_LWIP_LAYER == 1
#if DEVICE_EMAC
struct netif *pnetif = xnetif[idx];
#else
struct netif *pnetif = &xnetif[idx];
#endif
ip_addr_t addr = { 0 };
#ifdef CONFIG_MEMORY_ACCESS_ALIGNED
unsigned int temp;
memcpy(&temp, ip_dest, sizeof(unsigned int));
u32_t *ip_dest_addr = &temp;
#else
u32_t *ip_dest_addr = (u32_t*)ip_dest;
#endif
addr.addr = *ip_dest_addr;
if(pnetif->ip_addr.addr == 0)
return 1;
if(ip_addr_ismulticast(&addr) || ip_addr_isbroadcast(&addr,pnetif)){
return 1;
}
//if(ip_addr_netcmp(&(pnetif->ip_addr), &addr, &(pnetif->netmask))) //addr&netmask
// return 1;
if(ip_addr_cmp(&(pnetif->ip_addr),&addr))
return 1;
DBG_TRACE("invalid IP: %d.%d.%d.%d ",ip_dest[0],ip_dest[1],ip_dest[2],ip_dest[3]);
#endif
#ifdef CONFIG_DONT_CARE_TP
if(pnetif->flags & NETIF_FLAG_IPSWITCH)
return 1;
else
#endif
return 0;
}
int netif_get_idx(struct netif *pnetif)
{
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
if (pnetif == xnetif[0])
return 0;
#else
int idx = pnetif - xnetif;
switch(idx) {
case 0:
return 0;
case 1:
return 1;
default:
return -1;
}
#endif
#else
return -1;
#endif
}
unsigned char *netif_get_hwaddr(int idx_wlan)
{
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
return xnetif[idx_wlan]->hwaddr;
#else
return xnetif[idx_wlan].hwaddr;
#endif
#else
return NULL;
#endif
}
void netif_rx(int idx, unsigned int len)
{
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
wlan_emac_recv(xnetif[idx], len);
#else
ethernetif_recv(&xnetif[idx], len);
#endif
#endif
#if (CONFIG_INIC_EN == 1)
inic_netif_rx(idx, len);
#endif
}
void netif_post_sleep_processing(void)
{
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
#else
lwip_POST_SLEEP_PROCESSING(); //For FreeRTOS tickless to enable Lwip ARP timer when leaving IPS - Alex Fang
#endif
#endif
}
void netif_pre_sleep_processing(void)
{
#if (CONFIG_LWIP_LAYER == 1)
#if DEVICE_EMAC
#else
lwip_PRE_SLEEP_PROCESSING();
#endif
#endif
}
#ifdef CONFIG_WOWLAN
unsigned char *rltk_wlan_get_ip(int idx){
#if (CONFIG_LWIP_LAYER == 1)
return LwIP_GetIP(&xnetif[idx]);
#else
return NULL;
#endif
}
#endif

84
USDK/component/common/drivers/wlan/realtek/src/osdep/lwip_intf.h Normal file
View file

@ -0,0 +1,84 @@
/* mbed Microcontroller Library
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __LWIP_INTF_H__
#define __LWIP_INTF_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <wireless.h>
#include <skbuff.h>
struct netif;
//----- ------------------------------------------------------------------
// Ethernet Buffer
//----- ------------------------------------------------------------------
#if DEVICE_EMAC
struct eth_drv_sg {
unsigned int buf;
unsigned int len;
};
#define MAX_ETH_DRV_SG 32
#define MAX_ETH_MSG 1540
extern void wlan_emac_recv(struct netif *netif, int len);
#else
#include "ethernetif.h" // moved to ethernetif.h by jimmy 12/2/2015
#endif
//----- ------------------------------------------------------------------
// Wlan Interface Provided
//----- ------------------------------------------------------------------
unsigned char rltk_wlan_check_isup(int idx);
void rltk_wlan_tx_inc(int idx);
void rltk_wlan_tx_dec(int idx);
struct sk_buff * rltk_wlan_get_recv_skb(int idx);
struct sk_buff * rltk_wlan_alloc_skb(unsigned int total_len);
void rltk_wlan_set_netif_info(int idx_wlan, void * dev, unsigned char * dev_addr);
void rltk_wlan_send_skb(int idx, struct sk_buff *skb); //struct sk_buff as defined above comment line
int rltk_wlan_send(int idx, struct eth_drv_sg *sg_list, int sg_len, int total_len);
void rltk_wlan_recv(int idx, struct eth_drv_sg *sg_list, int sg_len);
unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: interface is down
//----- ------------------------------------------------------------------
// Network Interface provided
//----- ------------------------------------------------------------------
int netif_is_valid_IP(int idx,unsigned char * ip_dest);
int netif_get_idx(struct netif *pnetif);
unsigned char *netif_get_hwaddr(int idx_wlan);
void netif_rx(int idx, unsigned int len);
void netif_post_sleep_processing(void);
void netif_pre_sleep_processing(void);
#if (CONFIG_LWIP_LAYER == 1)
#if !DEVICE_EMAC
extern void ethernetif_recv(struct netif *netif, int total_len);
#endif
extern void lwip_PRE_SLEEP_PROCESSING(void);
extern void lwip_POST_SLEEP_PROCESSING(void);
#endif //CONFIG_LWIP_LAYER == 1
#ifdef CONFIG_WOWLAN
extern unsigned char *rltk_wlan_get_ip(int idx);
#endif
#ifdef __cplusplus
}
#endif
#endif //#ifndef __LWIP_INTF_H__

113
USDK/component/common/drivers/wlan/realtek/src/osdep/netdev.h Normal file
View file

@ -0,0 +1,113 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __NETDEV_H_
#define __NETDEV_H_
/* Define compilor specific symbol */
//
// inline function
//
#if defined ( __ICCARM__ )
#define __inline__ inline
#define __inline inline
#define __inline_definition //In dialect C99, inline means that a function's definition is provided
//only for inlining, and that there is another definition
//(without inline) somewhere else in the program.
//That means that this program is incomplete, because if
//add isn't inlined (for example, when compiling without optimization),
//then main will have an unresolved reference to that other definition.
// Do not inline function is the function body is defined .c file and this
// function will be called somewhere else, otherwise there is compile error
#elif defined ( __CC_ARM )
#define __inline__ __inline //__linine__ is not supported in keil compilor, use __inline instead
#define inline __inline
#define __inline_definition // for dialect C99
#elif defined ( __GNUC__ )
#define __inline__ inline
#define __inline inline
#define __inline_definition inline
#endif
#include <stdio.h>
#include <drv_conf.h>
#if defined( PLATFORM_FREERTOS)
#include "freertos_service.h"
#elif defined( PLATFORM_ECOS)
#include "ecos/ecos_service.h"
#elif defined(PLATFORM_CMSIS_RTOS)
#include "rtx_service.h"
#endif
// rtl8195a uses receive_tasklet for wps
// 8189em uses interrupt_thread for wps
#if defined(CONFIG_WPS)
#define RECV_STACK_FOR_WPS 448//512//384 //Change to 512 for WPS (IAR STM32) stack overflow
#else
#define RECV_STACK_FOR_WPS 0
#endif
#ifdef CONFIG_DONT_CARE_TP
#define XMIT_STACKSIZE 192 //256
#define CMD_STACKSIZE 384 //512
#else
#define XMIT_STACKSIZE 256
#define CMD_STACKSIZE 512 //1024
#endif //CONFIG_DONT_CARE_TP
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
#define RECV_STACKSIZE 256
#else //CONFIG_PLATFORM_8195A
#ifdef CONFIG_INCLUDE_WPA_PSK
#if PSK_SUPPORT_TKIP
#define RECV_STACKSIZE (512 + 256 + 128 + RECV_STACK_FOR_WPS)
#else
#define RECV_STACKSIZE (512 + 256 + RECV_STACK_FOR_WPS )
#endif
#else
#define RECV_STACKSIZE (512 + 256 + RECV_STACK_FOR_WPS) //Can be reduced
#endif
#endif //CONFIG_PLATFORM_8195A
#define XMIT_TASKLET_STACKSIZE 256
#define RECV_TASKLET_STACKSIZE (1024 + RECV_STACK_FOR_WPS)
#define SDIOXMIT_STACKSIZE 256
struct rtw_netdev_priv_indicator {
void *priv;
u32 sizeof_priv;
};
#define rtw_netdev_priv(netdev) ( ((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv )
#define ADPT_FMT "%s"
#define ADPT_ARG(adapter) adapter->pnetdev->name
#define FUNC_NDEV_FMT "%s"
#define FUNC_NDEV_ARG(ndev) __func__
#define FUNC_ADPT_FMT "%s(%s)"
#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name
#include "wifi_constants.h"
#include "wifi_structures.h"
int rtw_if_wifi_thread(char *name);
#endif //#ifndef __OSDEP_SERVICE_H_

116
USDK/component/common/drivers/wlan/realtek/src/osdep/osdep_intf.h Normal file
View file

@ -0,0 +1,116 @@
/******************************************************************************
*
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __OSDEP_INTF_H_
#define __OSDEP_INTF_H_
typedef struct net_device * _nic_hdl;
struct iw_request_info {
u16 cmd; /* Wireless Extension command */
u16 flags; /* More to come ;-) */
};
typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info,
union iwreq_data *wrqu, char *extra);
struct pkt_buff {
_list list;
u32 len;
unsigned char *data;
};
#if defined(PLATFORM_FREERTOS) || defined (PLATFORM_CMSIS_RTOS)
#include "freertos/wrapper.h"
#include "freertos/freertos_intfs.h"
#include "freertos/freertos_xmit.h"
#include "freertos/freertos_recv.h"
#elif defined(PLATFORM_ECOS)
#include "ecos/ecos_xmit.h"
#include "ecos/ecos_recv.h"
#include "ecos/ecos_mlme.h"
#include "ecos/ecos_intfs.h"
#ifdef CONFIG_PROC_DEBUG //need move to ecos/ecos_intfs.h
void rtw_proc_init_one(struct net_device *dev);
void rtw_proc_remove_one(struct net_device *dev);
#else
static void rtw_proc_init_one(struct net_device *dev){}
static void rtw_proc_remove_one(struct net_device *dev){}
#endif //CONFIG_PROC_DEBUG
#elif defined(PLATFORM_LINUX)
int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname);
struct net_device *rtw_init_netdev(_adapter *padapter);
#ifdef CONFIG_PROC_DEBUG
void rtw_proc_init_one(struct net_device *dev);
void rtw_proc_remove_one(struct net_device *dev);
#else
static void rtw_proc_init_one(struct net_device *dev){}
static void rtw_proc_remove_one(struct net_device *dev){}
#endif //CONFIG_PROC_DEBUG
#endif
#ifdef CONFIG_CONCURRENT_MODE
struct _io_ops;
_adapter *rtw_drv_if2_init(_adapter *primary_padapter, char *name, void (*set_intf_ops)(struct _io_ops *pops));
void rtw_drv_if2_free(_adapter *pbuddy_padapter);
#endif
struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv);
struct net_device * rtw_alloc_etherdev(int sizeof_priv);
void rtw_free_netdev(struct net_device * netdev);
int rtw_netif_queue_stopped(struct net_device *pnetdev);
void rtw_netif_wake_queue(struct net_device *pnetdev);
void rtw_netif_start_queue(struct net_device *pnetdev);
void rtw_netif_stop_queue(struct net_device *pnetdev);
struct pkt_buff *rtw_alloc_pktbuf(unsigned int size);
void rtw_free_pktbuf(struct pkt_buff *skb);
#if 0
int RTW_STATUS_CODE(int error_code);
//flags used for rtw_update_mem_stat()
enum {
MEM_STAT_VIR_ALLOC_SUCCESS,
MEM_STAT_VIR_ALLOC_FAIL,
MEM_STAT_VIR_FREE,
MEM_STAT_PHY_ALLOC_SUCCESS,
MEM_STAT_PHY_ALLOC_FAIL,
MEM_STAT_PHY_FREE,
MEM_STAT_TX, //used to distinguish TX/RX, asigned from caller
MEM_STAT_TX_ALLOC_SUCCESS,
MEM_STAT_TX_ALLOC_FAIL,
MEM_STAT_TX_FREE,
MEM_STAT_RX, //used to distinguish TX/RX, asigned from caller
MEM_STAT_RX_ALLOC_SUCCESS,
MEM_STAT_RX_ALLOC_FAIL,
MEM_STAT_RX_FREE
};
#endif
#endif //_OSDEP_INTF_H_

72
USDK/component/common/drivers/wlan/realtek/src/osdep/skbuff.h Normal file
View file

@ -0,0 +1,72 @@
/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#ifndef __SKBUFF_H__
#define __SKBUFF_H__
struct sk_buff_head {
struct list_head *next, *prev;
unsigned int qlen;
};
#ifdef CONFIG_TRACE_SKB
#define TRACE_SKB_DEPTH 8
#endif
struct sk_buff {
/* These two members must be first. */
struct sk_buff *next; /* Next buffer in list */
struct sk_buff *prev; /* Previous buffer in list */
struct sk_buff_head *list; /* List we are on */
unsigned char *head; /* Head of buffer */
unsigned char *data; /* Data head pointer */
unsigned char *tail; /* Tail pointer */
unsigned char *end; /* End pointer */
void *dev; /* Device we arrived on/are leaving by */
unsigned int len; /* Length of actual data */
#ifdef CONFIG_TRACE_SKB
unsigned int liston[TRACE_SKB_DEPTH]; /* Trace the Lists we went through */
const char *funcname[TRACE_SKB_DEPTH];
unsigned int list_idx; /* Trace the List we are on */
#endif
//#ifdef CONFIG_DONT_CARE_TP
int dyalloc_flag;
//#endif
};
unsigned char *skb_put(struct sk_buff *skb, unsigned int len);
unsigned char *skb_pull(struct sk_buff *skb, unsigned int len);
void skb_reserve(struct sk_buff *skb, unsigned int len);
void skb_assign_buf(struct sk_buff *skb, unsigned char *buf, unsigned int len);
unsigned char *skb_tail_pointer(const struct sk_buff *skb);
void skb_set_tail_pointer(struct sk_buff *skb, const int offset);
unsigned char *skb_end_pointer(const struct sk_buff *skb);
void init_skb_pool(void);
void init_skb_data_pool(void);
#ifndef CONFIG_DONT_CARE_TP
struct sk_buff *dev_alloc_skb(unsigned int length, unsigned int reserve_len);
#else
struct sk_buff *dev_alloc_tx_skb(unsigned int length, unsigned int reserve_len);
struct sk_buff *dev_alloc_rx_skb(unsigned int length, unsigned int reserve_len);
#define dev_alloc_skb dev_alloc_tx_skb
#endif
void kfree_skb(struct sk_buff *skb);
#endif //__SKBUFF_H__

1209
USDK/component/common/drivers/wlan/realtek/src/osdep/wireless.h Normal file
View file

File diff suppressed because it is too large Load diff

81
USDK/component/common/drivers/wlan/realtek/src/osdep/wlan_intf.h Normal file
View file

@ -0,0 +1,81 @@
/******************************************************************************
* Copyright (c) 2013-2016 Realtek Semiconductor Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
******************************************************************************/
#ifndef __WLAN_INTF_H__
#define __WLAN_INTF_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <autoconf.h>
#include <wireless.h>
#include "wifi_constants.h"
#ifndef WLAN0_IDX
#define WLAN0_IDX 0
#endif
#ifndef WLAN1_IDX
#define WLAN1_IDX 1
#endif
#ifndef WLAN_UNDEF
#define WLAN_UNDEF -1
#endif
/***********************************************************/
/*
struct sk_buff {
// These two members must be first.
struct sk_buff *next; // Next buffer in list
struct sk_buff *prev; // Previous buffer in list
struct sk_buff_head *list; // List we are on
unsigned char *head; // Head of buffer
unsigned char *data; // Data head pointer
unsigned char *tail; // Tail pointer
unsigned char *end; //End pointer
struct net_device *dev; //Device we arrived on/are leaving by
unsigned int len; // Length of actual data
};
*/
/************************************************************/
//----- ------------------------------------------------------------------
// Wlan Interface opened for upper layer
//----- ------------------------------------------------------------------
int rltk_wlan_init(int idx_wlan, rtw_mode_t mode); //return 0: success. -1:fail
void rltk_wlan_deinit(void);
void rltk_wlan_deinit_fastly(void);
int rltk_wlan_start(int idx_wlan);
void rltk_wlan_statistic(unsigned char idx);
unsigned char rltk_wlan_running(unsigned char idx); // interface is up. 0: interface is down
int rltk_wlan_control(unsigned long cmd, void *data);
int rltk_wlan_handshake_done(void);
int rltk_wlan_rf_on(void);
int rltk_wlan_rf_off(void);
int rltk_wlan_check_bus(void);
int rltk_wlan_wireless_mode(unsigned char mode);
int rltk_wlan_set_wps_phase(unsigned char is_trigger_wps);
int rtw_ps_enable(int enable);
int rltk_wlan_is_connected_to_ap(void);
#ifdef __cplusplus
}
#endif
#endif //#ifndef __WLAN_INTF_H__

14
USDK/component/common/drivers/wlan/realtek/src/wifi_skbuf.c Normal file
View file

@ -0,0 +1,14 @@
#include <section_config.h>
#include <freertos/wrapper.h>
#undef MAX_SKB_BUF_NUM
#define MAX_SKB_BUF_NUM 16
// DO NOT modify this structure
struct skb_data {
struct list_head list;
unsigned char buf[MAX_SKB_BUF_SIZE];
atomic_t ref;
};
SRAM_BD_DATA_SECTION
struct skb_data skb_data_pool[MAX_SKB_BUF_NUM];