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pvvx 2017-07-04 13:51:35 +03:00
parent ddaaf1af2d
commit 2947b7a296
6 changed files with 31 additions and 28 deletions
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46
USDK/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c
View file

@ -432,7 +432,8 @@ CLKCal(
} }
else { else {
//anack //anack
RRTemp = (((2133/Rtemp) >> x) - 1); //pvvx: eror RTL8710AF? RRTemp = (((2133/Rtemp) >> x) - 1);
RRTemp = (2133/Rtemp) - 1;
} }
if ( x == 5 ) if ( x == 5 )
DiagPrintf("Using ana to cal is not allowed!\n"); DiagPrintf("Using ana to cal is not allowed!\n");
@ -516,7 +517,7 @@ SleepClkGatted(
//3 1.5 Enable low power mode //3 1.5 Enable low power mode
// 1.5.1 0x4000_0118[2] = 1 => for sleep mode // 1.5.1 0x4000_0118[2] = 1 => for sleep mode
Rtemp = 0x00000004;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004; Rtemp = BIT_SYSON_PM_CMD_SLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//3 1.6 Wait CHIP enter low power mode //3 1.6 Wait CHIP enter low power mode
@ -580,7 +581,7 @@ VOID SleepPwrGatted(
//3 1.5 Enable low power mode //3 1.5 Enable low power mode
// 1.5.1 0x4000_0118[2] = 1 => for sleep mode // 1.5.1 0x4000_0118[2] = 1 => for sleep mode
Rtemp = 0x00000004;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004; Rtemp = BIT_SYSON_PM_CMD_SLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000004;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//3 1.6 Wait CHIP enter low power mode //3 1.6 Wait CHIP enter low power mode
@ -648,7 +649,7 @@ DStandby(
//3 1.5 Enable low power mode //3 1.5 Enable low power mode
// [0x4000_0118[1] = 1 => for deep standby mode] // [0x4000_0118[1] = 1 => for deep standby mode]
Rtemp = 0x00000002; Rtemp = BIT_SYSON_PM_CMD_DSTBY;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//3 1.6 Wait CHIP enter low power mode //3 1.6 Wait CHIP enter low power mode
@ -733,7 +734,7 @@ DSleep(
//3 2.2.3 //3 2.2.3
//2.3 Enable low power mode: 0x4000_0118[0] = 1'b1; //2.3 Enable low power mode: 0x4000_0118[0] = 1'b1;
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001; Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//2.4 Wait CHIP enter deep sleep mode //2.4 Wait CHIP enter deep sleep mode
@ -1446,7 +1447,8 @@ SleepCG(
Rtemp = 0x74003B00; //0x74003900; Rtemp = 0x74003B00; //0x74003900;
} }
else { else {
Rtemp = 0x74000900; Rtemp = 0x74000900; // BIT_SYSON_PMOPT_NORM_XTAL_EN | BIT_SYSON_PMOPT_NORM_SYSPLL_EN | BIT_SYSON_PMOPT_NORM_SYSCLK_SEL | BIT_SYSON_PMOPT_NORM_EN_PWM
// | BIT_SYSON_PMOPT_SLP_LPLDO_SEL | BIT_SYSON_PMOPT_SLP_EN_SOC
} }
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp);
@ -1465,49 +1467,49 @@ SleepCG(
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_ANA_TIM_CTRL, Rtemp);
//Enable wake event //Enable wake event
WakeEvent |= BIT0; WakeEvent |= BIT0; // BIT_SYSON_WEVT_SYSTIM_MSK
} }
if (Option & SLP_GTIMER) { if (Option & SLP_GTIMER) {
//Enable wake event //Enable wake event
WakeEvent |= BIT1; WakeEvent |= BIT1; // BIT_SYSON_WEVT_GTIM_MSK
} }
if (Option & SLP_GPIO) { if (Option & SLP_GPIO) {
//Enable wake event //Enable wake event
WakeEvent |= BIT4; WakeEvent |= BIT4; // BIT_SYSON_WEVT_GPIO_MSK
} }
if (Option & SLP_WL) { if (Option & SLP_WL) {
//Enable wake event //Enable wake event
WakeEvent |= BIT8; WakeEvent |= BIT8; // BIT_SYSON_WEVT_WLAN_MSK
} }
if (Option & SLP_NFC) { if (Option & SLP_NFC) {
//Enable wake event //Enable wake event
WakeEvent |= BIT28; WakeEvent |= BIT28; // BIT_SYSON_WEVT_A33_MSK
} }
if (Option & SLP_SDIO) { if (Option & SLP_SDIO) {
//Enable wake event //Enable wake event
WakeEvent |= BIT14; WakeEvent |= BIT14; // BIT_SYSON_WEVT_SDIO_MSK
} }
if (Option & SLP_USB) { if (Option & SLP_USB) {
//Enable wake event //Enable wake event
//WakeEvent |= BIT16; //WakeEvent |= BIT16; // BIT_SYSON_WEVT_USB_MSK
} }
if (Option & SLP_TIMER33) { if (Option & SLP_TIMER33) {
//Enable wake event //Enable wake event
WakeEvent |= BIT28; WakeEvent |= BIT28; // BIT_SYSON_WEVT_A33_MSK
} }
/* /*
while(1) { while(1) {
@ -1533,7 +1535,7 @@ SleepCG(
if (SDREn) SDRSleep(); if (SDREn) SDRSleep();
#endif #endif
Rtemp = 0x00000004; Rtemp = BIT_SYSON_PM_CMD_SLP;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//3 Wait CHIP enter low power mode //3 Wait CHIP enter low power mode
@ -1565,7 +1567,7 @@ SleepPG(
//3 2 Configure power state option: //3 2 Configure power state option:
// 2.1 power mode option: // 2.1 power mode option:
Rtemp = 0x74000100; Rtemp = 0x74000100; // BIT_SYSON_PMOPT_SLP_LPLDO_SEL
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, Rtemp);
// 2.2 sleep power mode option1 // 2.2 sleep power mode option1
@ -1648,7 +1650,7 @@ SleepPG(
LDO25M_CTRL(OFF); LDO25M_CTRL(OFF);
#endif #endif
Rtemp = 0x00000004; Rtemp = BIT_SYSON_PM_CMD_SLP;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//3 Wait CHIP enter low power mode //3 Wait CHIP enter low power mode
@ -1776,7 +1778,7 @@ DeepStandby(
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & 0xBFFFFFFF); Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & 0xBFFFFFFF);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp);
Rtemp = 0x00000002; Rtemp = BIT_SYSON_PM_CMD_DSTBY;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//3 Wait CHIP enter low power mode //3 Wait CHIP enter low power mode
@ -1885,7 +1887,7 @@ DeepSleep(
Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & 0xBFFFFFFF); Rtemp = (HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN) & 0xBFFFFFFF);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_FUNC_EN, Rtemp);
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001; Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//2.4 Wait CHIP enter deep sleep mode //2.4 Wait CHIP enter deep sleep mode
@ -1916,7 +1918,7 @@ DSleep_GPIO(
//2.2.2 //2.2.2
//2.3 Enable low power mode: 0x4000_0118[0] = 1'b1; //2.3 Enable low power mode: 0x4000_0118[0] = 1'b1;
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001; Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//2.4 Wait CHIP enter deep sleep mode //2.4 Wait CHIP enter deep sleep mode
@ -1989,7 +1991,7 @@ DSleep_Timer(
//3 2.3 //3 2.3
//2.3 Enable low power mode: 0x4000_0118[0] = 1'b1; //2.3 Enable low power mode: 0x4000_0118[0] = 1'b1;
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001; Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//2.4 Wait CHIP enter deep sleep mode //2.4 Wait CHIP enter deep sleep mode
@ -3253,7 +3255,7 @@ SOCPSTestApp(
//3 2.2.3 //3 2.2.3
//2.3 Enable low power mode: 0x4000_0118[0] = 1'b1; //2.3 Enable low power mode: 0x4000_0118[0] = 1'b1;
Rtemp = 0x00000001;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001; Rtemp = BIT_SYSON_PM_CMD_DSLP;//HAL_READ32(SYSTEM_CTRL_BASE, REG_SYSON_PWRMGT_CTRL) | 0x00000001;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp); HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, Rtemp);
//2.4 Wait CHIP enter deep sleep mode //2.4 Wait CHIP enter deep sleep mode

BIN
USDK/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/lib_sdcard_v2.a Normal file
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Binary file not shown.

1
USDK/sdkset.mk
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@ -240,6 +240,7 @@ SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/flash_eep.c
endif endif
#peripheral - hal #peripheral - hal
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/bitband_io.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_32k.c SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_32k.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_adc.c SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_adc.c
SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_gdma.c SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_gdma.c

8
project.mk
View file

@ -1,12 +1,12 @@
#============================================= #=============================================
# SDK CONFIG # SDK CONFIG
#============================================= #=============================================
WEB_INA219_DRV = 1 #WEB_INA219_DRV = 1
#WEB_ADC_DRV = 1 #WEB_ADC_DRV = 1
WEB_SDCARD = 1 #WEB_SDCARD = 1
#USE_AT = 1 #USE_AT = 1
USE_FATFS = 1 #USE_FATFS = 1
USE_SDIOH = 1 #USE_SDIOH = 1
#USE_POLARSSL = 1 #USE_POLARSSL = 1
#USE_P2P_WPS = 1 #USE_P2P_WPS = 1
#USE_GCC_LIB = 1 #USE_GCC_LIB = 1

2
project/inc/platform_autoconf.h
View file

@ -31,7 +31,7 @@
#define RTL8195A 1 #define RTL8195A 1
/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz, /* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */ 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
#define CONFIG_CPU_CLK 0 #define CONFIG_CPU_CLK 1
//166.6MHZ - RUN/IDLE/SLP ~63/21/6.4 mA //166.6MHZ - RUN/IDLE/SLP ~63/21/6.4 mA
//83.3MHZ - RUN/IDLE/SLP ~55/15/6.4 mA //83.3MHZ - RUN/IDLE/SLP ~55/15/6.4 mA
//41.6MHZ - RUN/IDLE ~51/11 mA //41.6MHZ - RUN/IDLE ~51/11 mA

2
project/src/console/atcmd_user.c
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@ -290,7 +290,7 @@ LOCAL void fATDS(int argc, char *argv[])
{ {
uint32 sleep_ms = 10000; uint32 sleep_ms = 10000;
if(argc > 1) sleep_ms = atoi(argv[1]); if(argc > 1) sleep_ms = atoi(argv[1]);
#if 0 #if 0 // WakeUp PB_1
if(argc > 2) { if(argc > 2) {
printf("%u ms waiting low level on PB_1 before launching Deep-Sleep...\n", sleep_ms); printf("%u ms waiting low level on PB_1 before launching Deep-Sleep...\n", sleep_ms);
// turn off log uart // turn off log uart