mirror of
https://github.com/pvvx/RTL00_WEB.git
synced 2024-11-22 05:54:19 +00:00
update
This commit is contained in:
pvvx
parent
de758bfdb3
commit
1e44ff6a55
13 changed files with 543 additions and 41 deletions
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@ -1,5 +1,5 @@
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/*
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* BootLoader Ver 0.3 (18/10/2017)
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* BootLoader Ver 0.3 (19/10/2017)
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* Created on: 12/02/2017
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* Author: pvvx
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*/
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@ -38,11 +38,11 @@
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typedef struct _seg_header {
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uint32 size;
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uint32 ldaddr;
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uint32 sign[2];
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} IMGSEGHEAD, *PIMGSEGHEAD;
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typedef struct _img2_header {
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IMGSEGHEAD seg;
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uint32 sign[2];
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void (*startfunc)(void);
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uint8 rtkwin[7];
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uint8 ver[13];
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@ -530,10 +530,10 @@ LOCAL uint32 BOOT_RAM_TEXT_SECTION get_seg_id(uint32 addr, int32 size) {
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LOCAL uint32 BOOT_RAM_TEXT_SECTION load_img2_head(uint32 faddr, PIMG2HEAD hdr) {
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flashcpy(faddr, hdr, sizeof(IMG2HEAD));
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uint32 ret = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
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if (hdr->sign[1] == IMG_SIGN2_RUN) {
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if (hdr->sign[0] == IMG_SIGN1_RUN) {
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if (hdr->seg.sign[1] == IMG_SIGN2_RUN) {
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if (hdr->seg.sign[0] == IMG_SIGN1_RUN) {
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ret |= 1 << 9; // есть сигнатура RUN
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} else if (hdr->sign[0] == IMG_SIGN1_SWP) {
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} else if (hdr->seg.sign[0] == IMG_SIGN1_SWP) {
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ret |= 1 << 8; // есть сигнатура SWP
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};
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}
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@ -1,5 +1,5 @@
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/*
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* StartUp USDK v0.2 (18/10/2017)
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* StartUp USDK v0.2 (19/10/2017)
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* Created on: 02/03/2017
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* Author: pvvx
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*/
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@ -50,7 +50,7 @@ extern const unsigned char cus_sig[32]; // images name
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IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 =
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{ InfraStart + 1 };
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#ifdef CONFIG_SDR_EN
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#ifdef FIX_SDR_CALIBRATION // for speed :)
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#include "rtl8195a/rtl8195a_sdr.h"
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LOCAL void sdr_init(void) {
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@ -106,6 +106,7 @@ LOCAL void sdr_init(void) {
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DBG_8195A(" ok\n");
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}
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#endif // FIX_SDR_CALIBRATION
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#endif // CONFIG_SDR_EN
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/*
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//----- HalNMIHandler_Patch
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void HalNMIHandler_Patch(void) {
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@ -177,6 +177,7 @@ SECTIONS
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LONG(0)
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UartLogRamCmdTable = .;
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KEEP(*(SORT(.mon.tab*)))
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KEEP(*(SORT(.sdram.mon.tab*)))
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UartLogRamCmdTable_end = .;
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LONG(0)
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} > BD_RAM
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@ -0,0 +1,265 @@
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ENTRY(Reset_Handler)
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ENTRY(main)
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INCLUDE "export-rom_v04.txt"
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MEMORY
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{
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ROM (rx) : ORIGIN = 0x000000, LENGTH = 1M /* end 0x00100000 */
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ROM_USED_RAM (rwx): ORIGIN = 0x10000000, LENGTH = 0x2400 /* end 0x10002400 */
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BOOT_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
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ROM_HEAP (rwx) : ORIGIN = 0x10002400, LENGTH = 3K /* end 0x10003000 */
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RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12K /* end 0x10006000 */
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BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 424K /* end 0x10070000 */
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TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
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TCM_TAB (rwx) : ORIGIN = 0x1FFFFD00, LENGTH = 768 /* end 0x20000000 */
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SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M /* end 0x30200000 */
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}
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EXTERN(RAM_IMG2_VALID_PATTEN)
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EXTERN(InfraStart)
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SECTIONS
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{
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/* 0x00000000: ROM */
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.rom :
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{
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__rom_image_start__ = .;
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KEEP(*(.rom));
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__rom_image_end__ = .;
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} > ROM
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/* 0x10000000: SRAM */
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.rom_ram : /* use in rom */
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{
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__ram_image_start__ = .;
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KEEP(*(.ram_dedecated_vector_table)) /* 0x10000000: NewVectorTable */
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KEEP(*(.ram_user_define_irq_table)) /* 0x10000100: UserIrqFunTable */
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KEEP(*(.ram_user_define_data_table)) /* 0x10000200: UserIrqDataTable */
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__rom_bss_start__ = .;
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KEEP(*(.hal.ram.bss)) /* 0x10000300: CfgSysDebugWarn .. _pHAL_Gpio_Adapter */
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KEEP(*(.timer2_7_vector_table.data)) /* 0x10000358: Timer2To7VectorTable */
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KEEP(*(.infra.ram.bss)) /* 0x10000370: first .. z4 */
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KEEP(*(.mon.ram.bss)) /* 0x10000384: pUartLogCtl .. ArgvArray */
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KEEP(*(.wlan_ram_map)) /* 0x100006d4: rom_wlan_ram_map, FalseAlmCnt, ROMInfo, DM_CfoTrack */
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KEEP(*(.ram.rom.wlanmap)) /* align(8) */
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KEEP(*(.libc.ram.bss)) /* 0x10000760: rom_libgloss_ram_map __rtl_malloc_av_ __rtl_errno */
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__rom_bss_end__ = .;
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} > ROM_USED_RAM
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/* 0x10000bc8: bootloader */
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.ram_image1.text . : /* use in rom & boot */
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{
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/* __ram_start_table_start__ = .; */
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__ram_image1_text_start__ = .;
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KEEP(*(.boot.start.ram.data*))
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/* __image1_validate_code__ = .; */
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KEEP(*(.image1.validate.rodata))
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KEEP(*(.infra.ram.data*))
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KEEP(*(.timer.ram.data*))
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KEEP(*(.cutb.ram.data*))
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KEEP(*(.cutc.ram.data*))
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KEEP(*(.libc.reent))
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KEEP(*(.rom.unc.data))
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KEEP(*(.sdr.rand2.data))
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PROVIDE (__ram_image_end__ = .); /* 0x100020c0: end */
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/* boot & images data */
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KEEP(*(.hal.ram.data))
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KEEP(*(.hal.flash.data))
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KEEP(*(.boot.rodata*))
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KEEP(*(.boot.text*))
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KEEP(*(.boot.data*))
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__image1_bss_start__ = .;
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KEEP(*(.boot.bss*))
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__image1_bss_end__ = .;
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__ram_image1_text_end__ = .;
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} > BOOT_RAM
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.romheap :
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{
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__rom_heap_start__ = .;
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end = __rom_heap_start__;
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. = ALIGN(0x1000);
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__rom_heap_end__ = .;
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} > ROM_HEAP
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.ram_heap1 :
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{
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__ram_heap1_start__ = .;
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/* *(.heap1*) */
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} > RAM_HEAP1
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.tcm :
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{
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__ram_tcm_start__ = .;
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__tcm_heap_start__ = .;
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*(.tcm.heap)
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} > TCM
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.soc_ps_monitor :
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{
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__tcm_heap_end__ = .;
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} > TCM_TAB
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.image2.start.table :
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{
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__ram_heap1_end__ = .;
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__ram_image2_text_start__ = .;
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__image2_entry_func__ = .;
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.image2.start.table1$$Base = .;
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KEEP(*(SORT(.image2.ram.data*)))
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__image2_validate_code__ = .;
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KEEP(*(.image2.validate.rodata*))
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KEEP(*(.custom.validate.rodata*))
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} > BD_RAM
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.sdr_text :
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{
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__sdram_data_start__ = .;
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INCLUDE "sdram_obj.txt"
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*(.sdram.text*)
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} > SDRAM_RAM
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.sdr_rodata :
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{
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*(.sdram.rodata*)
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} > SDRAM_RAM
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.sdr_data :
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{
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*(.sdram.data*)
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__sdram_data_end__ = .;
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} > SDRAM_RAM
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.sdr_bss :
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{
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__sdram_bss_start__ = .;
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*(.uvc.ram.bss)
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*(.sdram.bss*)
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INCLUDE "sdram_bss.txt"
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__sdram_bss_end__ = .;
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. = ALIGN(8);
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__sdram_heap_start__ = .;
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} > SDRAM_RAM
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.ram_image2.text :
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{
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*(.infra.ram.start*)
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. = ALIGN(4);
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KEEP(*(.init))
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/* init data */
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. = ALIGN(4);
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PROVIDE (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE (__init_array_end = .);
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. = ALIGN(4);
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KEEP(*(.fini))
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. = ALIGN(4);
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PROVIDE (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE (__fini_array_end = .);
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*(.mon.ram.text*)
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*(.hal.flash.text*)
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*(.hal.sdrc.text*)
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*(.hal.gpio.text*)
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*(.fwu.text*)
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*(.otg.rom.text*)
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*(.text*)
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/* *(.sdram.text*) */
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*(.p2p.text*)
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*(.wps.text*)
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*(.websocket.text*)
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} > BD_RAM
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.ram_image2.rodata :
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{
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*(.rodata*)
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*(.fwu.rodata*)
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/* *(.sdram.rodata*) */
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*(.p2p.rodata*)
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*(.wps.rodata*)
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*(.websocket.rodata*)
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. = ALIGN(4);
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xHeapRegions = .;
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LONG(__ram_heap1_start__)
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LONG(__ram_heap1_end__ - __ram_heap1_start__)
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LONG(__ram_heap2_start__)
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LONG(__ram_heap2_end__ - __ram_heap2_start__)
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LONG(__sdram_heap_start__)
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LONG(__sdram_heap_end__ - __sdram_heap_start__)
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LONG(0)
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LONG(0)
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UartLogRamCmdTable = .;
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KEEP(*(SORT(.mon.tab*)))
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KEEP(*(SORT(.sdram.mon.tab*)))
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UartLogRamCmdTable_end = .;
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LONG(0)
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} > BD_RAM
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PROVIDE(UartLogRamCmdTableSize = UartLogRamCmdTable_end - UartLogRamCmdTable);
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.ram.data :
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{
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__data_start__ = .;
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*(.data*)
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*(.p2p.data*)
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*(.wps.data*)
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*(.websocket.data*)
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/* *(.sdram.data*) */
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__data_end__ = .;
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__ram_image2_text_end__ = .;
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} > BD_RAM
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.ram.bss :
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{
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__bss_start__ = .;
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.ram.bss$$Base = .;
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*(.hal.flash.data*)
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*(.hal.sdrc.data*)
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*(.hal.gpio.data*)
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*(.fwu.data*)
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*(.bdsram.data*)
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*(.bfsram.data*)
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*(COMMON)
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*(.bss*)
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/* *(.sdram.bss*) */
|
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*(.p2p.bss*)
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*(.wps.bss*)
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*(.websocket.bss*)
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*(.ssl_ram_map*)
|
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__bss_end__ = .;
|
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.ram.bss$$Limit = .;
|
||||
|
||||
} > BD_RAM
|
||||
|
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.ram_heap2 :
|
||||
{
|
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. = ALIGN(8);
|
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__ram_heap2_start__ = .;
|
||||
*(.heap*) /* ucHeap */
|
||||
} > BD_RAM
|
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__ram_heap2_end__ = 0x10070000;
|
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|
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__sdram_heap_end__ = 0x30200000;
|
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|
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.boot.head :
|
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{
|
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KEEP(*(.loader.head*))
|
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}
|
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ASSERT(__ram_image_end__ == 0x100020c0, "Error rom-bios-boot code & data!")
|
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}
|
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|
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@ -0,0 +1,42 @@
|
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/**** from lib_mdns.a ****/
|
||||
*DNSCommon.o(.bss*)
|
||||
*dnssd_clientlib.o(.bss*)
|
||||
*dnssd_clientshim.o(.bss*)
|
||||
*mDNS.o(.bss*)
|
||||
*mDNSMain.o(.bss*)
|
||||
*mDNSPosix.o(.bss*)
|
||||
*mDNSPosixOverwrite.o(.bss*)
|
||||
*posix.o(.bss*)
|
||||
|
||||
/**** from lib_uvc.a ****/
|
||||
*v4l2-dev.o(.bss*)
|
||||
*v4l2-device.o(.bss*)
|
||||
*v4l2-fh.o(.bss*)
|
||||
*v4l2_driver.o(.bss*)
|
||||
*v4l2_intf.o(.bss*)
|
||||
*videobuf2-core.o(.bss*)
|
||||
*uvc_ctrl.o(.bss*)
|
||||
*uvc_driver.o(.bss*)
|
||||
*uvc_intf.o(.bss*)
|
||||
*uvc_queue.o(.bss*)
|
||||
*uvc_v4l2.o(.bss*)
|
||||
*uvc_video.o(.bss*)
|
||||
|
||||
/**** from lib_usb_otg_linux.a ***
|
||||
*dwc_common_os.o(.bss*)
|
||||
*dwc_otg_hcd_os.o(.bss*) */
|
||||
|
||||
/**** from lib_usb_drv.a ****/
|
||||
*usb.o(.bss*)
|
||||
|
||||
/**** from lib_usb_otg.a ****/
|
||||
*dwc_os.o(.bss*)
|
||||
*dwc_otg_cil.o(.bss*)
|
||||
*dwc_otg_cil_intr.o(.bss*)
|
||||
*dwc_otg_common.o(.bss*)
|
||||
*dwc_otg_dbg.o(.bss*)
|
||||
*dwc_otg_driver.o(.bss*)
|
||||
*dwc_otg_hcd.o(.bss*)
|
||||
*dwc_otg_hcd_ddma.o(.bss*)
|
||||
*dwc_otg_hcd_intr.o(.bss*)
|
||||
*dwc_otg_hcd_queue.o(.bss*)
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
|
||||
/**** from lib_mdns.a ****/
|
||||
*DNSCommon.o(.text*)
|
||||
*dnssd_clientlib.o(.text*)
|
||||
*dnssd_clientshim.o(.text*)
|
||||
*mDNS.o(.text*)
|
||||
*mDNSMain.o(.text*)
|
||||
*mDNSPosix.o(.text*)
|
||||
*mDNSPosixOverwrite.o(.text*)
|
||||
*posix.o(.text*)
|
||||
|
||||
*DNSCommon.o(.rodata*)
|
||||
*dnssd_clientlib.o(.rodata*)
|
||||
*dnssd_clientshim.o(.rodata*)
|
||||
*mDNS.o(.rodata*)
|
||||
*mDNSMain.o(.rodata*)
|
||||
*mDNSPosix.o(.rodata*)
|
||||
*mDNSPosixOverwrite.o(.rodata*)
|
||||
*posix.o(.rodata*)
|
||||
|
||||
*DNSCommon.o(.data*)
|
||||
*dnssd_clientlib.o(.data*)
|
||||
*dnssd_clientshim.o(.data*)
|
||||
*mDNS.o(.data*)
|
||||
*mDNSMain.o(.data*)
|
||||
*mDNSPosix.o(.data*)
|
||||
*mDNSPosixOverwrite.o(.data*)
|
||||
*posix.o(.data*)
|
||||
|
||||
/**** from lib_uvc.a ****/
|
||||
*v4l2-dev.o(.text*)
|
||||
*v4l2-device.o(.text*)
|
||||
*v4l2-fh.o(.text*)
|
||||
*v4l2_driver.o(.text*)
|
||||
*v4l2_intf.o(.text*)
|
||||
*videobuf2-core.o(.text*)
|
||||
*uvc_ctrl.o(.text*)
|
||||
*uvc_driver.o(.text*)
|
||||
*uvc_intf.o(.text*)
|
||||
*uvc_queue.o(.text*)
|
||||
*uvc_v4l2.o(.text*)
|
||||
*uvc_video.o(.text*)
|
||||
|
||||
*v4l2-dev.o(.rodata*)
|
||||
*v4l2-device.o(.rodata*)
|
||||
*v4l2-fh.o(.rodata*)
|
||||
*v4l2_driver.o(.rodata*)
|
||||
*v4l2_intf.o(.rodata*)
|
||||
*videobuf2-core.o(.rodata*)
|
||||
*uvc_ctrl.o(.rodata*)
|
||||
*uvc_driver.o(.rodata*)
|
||||
*uvc_intf.o(.rodata*)
|
||||
*uvc_queue.o(.rodata*)
|
||||
*uvc_v4l2.o(.rodata*)
|
||||
*uvc_video.o(.rodata*)
|
||||
|
||||
*v4l2-dev.o(.data*)
|
||||
*v4l2-device.o(.data*)
|
||||
*v4l2-fh.o(.data*)
|
||||
*v4l2_driver.o(.data*)
|
||||
*v4l2_intf.o(.data*)
|
||||
*videobuf2-core.o(.data*)
|
||||
*uvc_ctrl.o(.data*)
|
||||
*uvc_driver.o(.data*)
|
||||
*uvc_intf.o(.data*)
|
||||
*uvc_queue.o(.data*)
|
||||
*uvc_v4l2.o(.data*)
|
||||
*uvc_video.o(.data*)
|
||||
|
||||
|
||||
/**** from lib_usb_otg_linux.a ***
|
||||
*dwc_common_os.o(.text*)
|
||||
*dwc_otg_hcd_os.o(.text*) */
|
||||
*dwc_common_os.o(.rodata*)
|
||||
*dwc_otg_hcd_os.o(.rodata*)
|
||||
*dwc_common_os.o(.data*)
|
||||
*dwc_otg_hcd_os.o(.data*)
|
||||
|
||||
|
||||
/**** from lib_usb_drv.a ****/
|
||||
*usb.o(.text*)
|
||||
*usb.o(.rodata*)
|
||||
*usb.o(.data*)
|
||||
|
||||
/**** from lib_usb_otg.a ***
|
||||
*dwc_os.o(.text*)
|
||||
*dwc_otg_cil.o(.text*)
|
||||
*dwc_otg_cil_intr.o(.text*)
|
||||
*dwc_otg_common.o(.text*)
|
||||
*dwc_otg_dbg.o(.text*)
|
||||
*dwc_otg_driver.o(.text*)
|
||||
*dwc_otg_hcd.o(.text*)
|
||||
*dwc_otg_hcd_ddma.o(.text*)
|
||||
*dwc_otg_hcd_intr.o(.text*)
|
||||
*dwc_otg_hcd_queue.o(.text*) */
|
||||
|
||||
*dwc_os.o(.rodata*)
|
||||
*dwc_otg_cil.o(.rodata*)
|
||||
*dwc_otg_cil_intr.o(.rodata*)
|
||||
*dwc_otg_common.o(.rodata*)
|
||||
*dwc_otg_dbg.o(.rodata*)
|
||||
*dwc_otg_driver.o(.rodata*)
|
||||
*dwc_otg_hcd.o(.rodata*)
|
||||
*dwc_otg_hcd_ddma.o(.rodata*)
|
||||
*dwc_otg_hcd_intr.o(.rodata*)
|
||||
*dwc_otg_hcd_queue.o(.rodata*)
|
||||
|
||||
*dwc_os.o(.data*)
|
||||
*dwc_otg_cil.o(.data*)
|
||||
*dwc_otg_cil_intr.o(.data*)
|
||||
*dwc_otg_common.o(.data*)
|
||||
*dwc_otg_dbg.o(.data*)
|
||||
*dwc_otg_driver.o(.data*)
|
||||
*dwc_otg_hcd.o(.data*)
|
||||
*dwc_otg_hcd_ddma.o(.data*)
|
||||
*dwc_otg_hcd_intr.o(.data*)
|
||||
*dwc_otg_hcd_queue.o(.data*)
|
||||
|
|
@ -38,37 +38,38 @@ set mem inaccessible-by-default off
|
|||
# Setup GDB FOR FASTER DOWNLOADS
|
||||
set remote memory-write-packet-size 8192
|
||||
set remote memory-write-packet-size fixed
|
||||
set $SPI_FLASH_BASE = 0x98000000
|
||||
end
|
||||
#############
|
||||
# Boot_Flash
|
||||
define SetBootFlash
|
||||
printf "SetBoot = Flash:\n"
|
||||
monitor long 0x40000210 = 0x211157
|
||||
monitor long 0x40000210 = 0x00011113
|
||||
end
|
||||
# Boot RAM start_addr0() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
|
||||
define SetBootCall0
|
||||
printf "SetBoot = Call0:\n"
|
||||
monitor long 0x40000210 = 0x80111157
|
||||
monitor long 0x40000210 = 0x80011113
|
||||
end
|
||||
# Boot RAM start_addr1() Run if ( v40000210 & 0x20000000 )
|
||||
define SetBootCall1
|
||||
printf "SetBoot = Call1:\n"
|
||||
monitor long 0x40000210 = 0x20111157
|
||||
monitor long 0x40000210 = 0x20011113
|
||||
end
|
||||
# Boot RAM start_addr2() Run if ( v40000210 & 0x10000000 )
|
||||
define SetBootCall2
|
||||
printf "SetBoot = Call2:\n"
|
||||
monitor long 0x40000210 = 0x10111157
|
||||
monitor long 0x40000210 = 0x10011113
|
||||
end
|
||||
# Boot RAM start_addr3() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
|
||||
define SetBootCall3
|
||||
printf "SetBoot = Call3:\n"
|
||||
monitor long 0x40000210 = 0x8111157
|
||||
monitor long 0x40000210 = 0x8011113
|
||||
end
|
||||
# Boot RAM start_addr4() Init console, Run if ( v40000210 & 0x4000000 )
|
||||
define SetBootCall4
|
||||
printf "SetBoot = Call4:\n"
|
||||
monitor long 0x40000210 = 0x4111157
|
||||
monitor long 0x40000210 = 0x4011113
|
||||
end
|
||||
# CPU CLK 166 MHz?
|
||||
define SetClk166MHz
|
||||
|
|
@ -89,8 +90,7 @@ monitor long 0x40000304 = 0x1FC00002
|
|||
monitor long 0x40000250 = 0x400
|
||||
monitor long 0x40000340 = 0x0
|
||||
monitor long 0x40000230 = 0xdcc4
|
||||
monitor long 0x40000210 = 0x11117
|
||||
monitor long 0x40000210 = 0x11157
|
||||
monitor long 0x40000210 = 0x11113
|
||||
monitor long 0x400002c0 = 0x110011
|
||||
monitor long 0x40000320 = 0xffffffff
|
||||
end
|
||||
|
|
@ -125,7 +125,6 @@ monitor long 0x40006018 = 0
|
|||
monitor long 0x4000601C = 0
|
||||
#disable DMA
|
||||
monitor long 0x4000604C = 0
|
||||
set $SPI_FLASH_BASE = 0x98000000
|
||||
end
|
||||
###################
|
||||
# SetFirwareSize #
|
||||
|
|
@ -154,7 +153,26 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
|
|||
printf "Image2Size = %d\n", $Image2Size
|
||||
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
|
||||
set $FirmwareSize = $Image2Addr + $Image2Size
|
||||
printf "FirmwareSize = %d\n", $FirmwareSize
|
||||
set $Image3Addr = $FirmwareSize
|
||||
set $parms1 = $rambuffer - $FirmwareSize
|
||||
set $parms3 = $Image3Addr + 0x08
|
||||
restore $arg0 binary $parms1 $Image3Addr $parms3
|
||||
set $Image3Size = {int}($rambuffer)
|
||||
set $Image3LoadAddr = {int}($rambuffer+0x4)
|
||||
if $Image3Size != 0xFFFFFFFF && $Image3Size != 0
|
||||
set $Image3Size = $Image3Size + 16
|
||||
printf "Image3Size = %d\n", $Image3Size
|
||||
printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
|
||||
set $FirmwareSize = $Image3Addr + $Image3Size
|
||||
printf "FirmwareSize = %d\n", $FirmwareSize
|
||||
else
|
||||
set $Image3Size = 0
|
||||
if $Image3LoadAddr == 0x30000000
|
||||
set $FirmwareSize = $FirmwareSize + 8
|
||||
end
|
||||
printf "Image3 - None\n"
|
||||
printf "FirmwareSize = %d\n", $FirmwareSize
|
||||
end
|
||||
else
|
||||
set $Image2Size = 0
|
||||
printf "Image2 - None\n"
|
||||
|
|
@ -164,7 +182,9 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
|
|||
else
|
||||
set $Image1Size = 0
|
||||
set $Image2Size = 0
|
||||
set $Image3Size = 0
|
||||
set $Image2Addr = 0
|
||||
set $Image3Addr = 0
|
||||
set $FirmwareSize = 0
|
||||
printf "Image not format Firmware!\n"
|
||||
end
|
||||
|
|
@ -173,6 +193,10 @@ end
|
|||
# Flash Images Info #
|
||||
#####################
|
||||
define FlashImagesInfo
|
||||
set $Image2Size = 0
|
||||
set $Image3Size = 0
|
||||
set $Image2Addr = 0
|
||||
set $Image3Addr = 0
|
||||
printf "Flash Info:\n"
|
||||
set $Image1Size = {int}($SPI_FLASH_BASE + 0x10) + 32
|
||||
set $Image1LoadAddr = {int}($SPI_FLASH_BASE + 0x14)
|
||||
|
|
@ -181,16 +205,26 @@ printf "Image1 - None\n"
|
|||
else
|
||||
set $Image2FlashAddr = {short}($SPI_FLASH_BASE + 0x18) * 1024
|
||||
if $Image2FlashAddr == 0
|
||||
$Image2FlashAddr = $Image1Size
|
||||
set $Image2FlashAddr = $Image1Size
|
||||
end
|
||||
set $Image2Size = {int}($Image2FlashAddr + $SPI_FLASH_BASE)
|
||||
set $Image2LoadAddr = {int}($Image2FlashAddr + $SPI_FLASH_BASE + 0x4)
|
||||
printf "Image1Size = %d\n", $Image1Size
|
||||
printf "Image1LoadAddr = 0x%08x\n", $Image1LoadAddr
|
||||
printf "Image2FlashAddr = 0x%08x\n", $Image2FlashAddr
|
||||
if $Image2Size != 0xFFFFFFFF
|
||||
if $Image2Size != 0xFFFFFFFF && $Image2Size != 0
|
||||
printf "Image2Size = %d\n", $Image2Size
|
||||
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
|
||||
set $Image3FlashAddr = $Image2FlashAddr + $Image2Size + 0x10
|
||||
set $Image3Size = {int}($Image3FlashAddr + $SPI_FLASH_BASE)
|
||||
set $Image3LoadAddr = {int}($Image3FlashAddr + $SPI_FLASH_BASE + 0x4)
|
||||
if $Image3Size != 0xFFFFFFFF && $Image3Size !=0
|
||||
printf "Image3FlashAddr = 0x%08x\n", $Image3FlashAddr
|
||||
printf "Image3Size = %d\n", $Image3Size
|
||||
printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
|
||||
else
|
||||
printf "Image3 - None\n"
|
||||
end
|
||||
else
|
||||
printf "Image2 - None\n"
|
||||
end
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@ set $rtl8710_flasher_auto_erase = 1
|
|||
set $rtl8710_flasher_auto_verify = 1
|
||||
set $rtl8710_flasher_firmware_ptr = 0x10001000
|
||||
set $rtl8710_flasher_buffer = 0x10008000
|
||||
#262144
|
||||
set $rtl8710_flasher_buffer_size = 421888
|
||||
set $rtl8710_flasher_sector_size = 4096
|
||||
set $rtl8710_flasher_auto_erase_sector = 0xFFFFFFFF
|
||||
|
|
@ -37,11 +36,10 @@ if $rtl8710_flasher_capacity == 0
|
|||
monitor go
|
||||
FlasherWait
|
||||
set $id = {int}($rtl8710_flasher_buffer + 0x0C)
|
||||
set $rtl8710_flasher_capacity = 1 << (($id >> 16) & 0x0ff)
|
||||
if ($id == 0x1420c2)
|
||||
set $rtl8710_flasher_capacity = 1 << (($id >> 16) & 0x0ff)
|
||||
printf "Flash ID = 0x%08x : MX25L8006E (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10
|
||||
else
|
||||
set $rtl8710_flasher_capacity = {int}(1024*1024)
|
||||
printf "Flash ID = 0x%08x : (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10
|
||||
end
|
||||
printf "RTL8710 flasher initialized\n"
|
||||
|
|
@ -108,9 +106,9 @@ while $offset < $size
|
|||
end
|
||||
set $flash_offset = $arg1 + $offset
|
||||
printf "write offset 0x%08x\n", $flash_offset
|
||||
set $parms1 = $rtl8710_flasher_buffer + 0x20 - $offset - $arg1
|
||||
set $parms2 = $offset + $arg1
|
||||
set $parms3 = $offset + $len + $arg1
|
||||
set $parms1 = $rtl8710_flasher_buffer + 0x20 - $flash_offset
|
||||
set $parms2 = $flash_offset
|
||||
set $parms3 = $flash_offset + $len
|
||||
restore $arg0 binary $parms1 $parms2 $parms3
|
||||
if $rtl8710_flasher_auto_erase != 0
|
||||
set $count_i = $flash_offset
|
||||
|
|
@ -154,7 +152,12 @@ if $Image1Size != 0
|
|||
#FlasherWrite $wr_flile 0 $Image1Size
|
||||
call2
|
||||
if $Image2Size != 0 && $Image2Addr >= $Image1Size
|
||||
printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
|
||||
if $Image3Size != 0 && $Image3Addr > $Image2Size
|
||||
set $Image2Size = $Image2Size + $Image3Size
|
||||
printf "Write Image2&3 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
|
||||
else
|
||||
printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
|
||||
end
|
||||
#FlasherWrite $wr_flile $Image2Addr $Image2Size
|
||||
call3
|
||||
end
|
||||
|
|
|
|||
|
|
@ -55,6 +55,7 @@ endif
|
|||
PATHLIBS = sdk/component/soc/realtek/8195a/misc/bsp/lib/common/gcc
|
||||
|
||||
ifdef USE_SDRAM
|
||||
CFLAGS += -DUSE_SDRAM=1
|
||||
LDFILE ?= rlx8195A-symbol-v04-img3.ld
|
||||
else
|
||||
LDFILE ?= rlx8195A-symbol-v04-img2.ld
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ set mem inaccessible-by-default off
|
|||
# Setup GDB FOR FASTER DOWNLOADS
|
||||
set remote memory-write-packet-size 8192
|
||||
set remote memory-write-packet-size fixed
|
||||
set $SPI_FLASH_BASE = 0x98000000
|
||||
end
|
||||
#############
|
||||
# Boot_Flash
|
||||
|
|
@ -124,7 +125,6 @@ monitor long 0x40006018 = 0
|
|||
monitor long 0x4000601C = 0
|
||||
#disable DMA
|
||||
monitor long 0x4000604C = 0
|
||||
set $SPI_FLASH_BASE = 0x98000000
|
||||
end
|
||||
###################
|
||||
# SetFirwareSize #
|
||||
|
|
@ -153,7 +153,26 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
|
|||
printf "Image2Size = %d\n", $Image2Size
|
||||
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
|
||||
set $FirmwareSize = $Image2Addr + $Image2Size
|
||||
printf "FirmwareSize = %d\n", $FirmwareSize
|
||||
set $Image3Addr = $FirmwareSize
|
||||
set $parms1 = $rambuffer - $FirmwareSize
|
||||
set $parms3 = $Image3Addr + 0x08
|
||||
restore $arg0 binary $parms1 $Image3Addr $parms3
|
||||
set $Image3Size = {int}($rambuffer)
|
||||
set $Image3LoadAddr = {int}($rambuffer+0x4)
|
||||
if $Image3Size != 0xFFFFFFFF && $Image3Size != 0
|
||||
set $Image3Size = $Image3Size + 16
|
||||
printf "Image3Size = %d\n", $Image3Size
|
||||
printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
|
||||
set $FirmwareSize = $Image3Addr + $Image3Size
|
||||
printf "FirmwareSize = %d\n", $FirmwareSize
|
||||
else
|
||||
set $Image3Size = 0
|
||||
if $Image3LoadAddr == 0x30000000
|
||||
set $FirmwareSize = $FirmwareSize + 8
|
||||
end
|
||||
printf "Image3 - None\n"
|
||||
printf "FirmwareSize = %d\n", $FirmwareSize
|
||||
end
|
||||
else
|
||||
set $Image2Size = 0
|
||||
printf "Image2 - None\n"
|
||||
|
|
@ -163,7 +182,9 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
|
|||
else
|
||||
set $Image1Size = 0
|
||||
set $Image2Size = 0
|
||||
set $Image3Size = 0
|
||||
set $Image2Addr = 0
|
||||
set $Image3Addr = 0
|
||||
set $FirmwareSize = 0
|
||||
printf "Image not format Firmware!\n"
|
||||
end
|
||||
|
|
@ -172,6 +193,10 @@ end
|
|||
# Flash Images Info #
|
||||
#####################
|
||||
define FlashImagesInfo
|
||||
set $Image2Size = 0
|
||||
set $Image3Size = 0
|
||||
set $Image2Addr = 0
|
||||
set $Image3Addr = 0
|
||||
printf "Flash Info:\n"
|
||||
set $Image1Size = {int}($SPI_FLASH_BASE + 0x10) + 32
|
||||
set $Image1LoadAddr = {int}($SPI_FLASH_BASE + 0x14)
|
||||
|
|
@ -180,16 +205,26 @@ printf "Image1 - None\n"
|
|||
else
|
||||
set $Image2FlashAddr = {short}($SPI_FLASH_BASE + 0x18) * 1024
|
||||
if $Image2FlashAddr == 0
|
||||
$Image2FlashAddr = $Image1Size
|
||||
set $Image2FlashAddr = $Image1Size
|
||||
end
|
||||
set $Image2Size = {int}($Image2FlashAddr + $SPI_FLASH_BASE)
|
||||
set $Image2LoadAddr = {int}($Image2FlashAddr + $SPI_FLASH_BASE + 0x4)
|
||||
printf "Image1Size = %d\n", $Image1Size
|
||||
printf "Image1LoadAddr = 0x%08x\n", $Image1LoadAddr
|
||||
printf "Image2FlashAddr = 0x%08x\n", $Image2FlashAddr
|
||||
if $Image2Size != 0xFFFFFFFF
|
||||
if $Image2Size != 0xFFFFFFFF && $Image2Size != 0
|
||||
printf "Image2Size = %d\n", $Image2Size
|
||||
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
|
||||
set $Image3FlashAddr = $Image2FlashAddr + $Image2Size + 0x10
|
||||
set $Image3Size = {int}($Image3FlashAddr + $SPI_FLASH_BASE)
|
||||
set $Image3LoadAddr = {int}($Image3FlashAddr + $SPI_FLASH_BASE + 0x4)
|
||||
if $Image3Size != 0xFFFFFFFF && $Image3Size !=0
|
||||
printf "Image3FlashAddr = 0x%08x\n", $Image3FlashAddr
|
||||
printf "Image3Size = %d\n", $Image3Size
|
||||
printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
|
||||
else
|
||||
printf "Image3 - None\n"
|
||||
end
|
||||
else
|
||||
printf "Image2 - None\n"
|
||||
end
|
||||
|
|
|
|||
|
|
@ -152,7 +152,12 @@ if $Image1Size != 0
|
|||
#FlasherWrite $wr_flile 0 $Image1Size
|
||||
call2
|
||||
if $Image2Size != 0 && $Image2Addr >= $Image1Size
|
||||
printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
|
||||
if $Image3Size != 0 && $Image3Addr > $Image2Size
|
||||
set $Image2Size = $Image2Size + $Image3Size
|
||||
printf "Write Image2&3 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
|
||||
else
|
||||
printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
|
||||
end
|
||||
#FlasherWrite $wr_flile $Image2Addr $Image2Size
|
||||
call3
|
||||
end
|
||||
|
|
|
|||
12
project.mk
12
project.mk
|
|
@ -1,6 +1,7 @@
|
|||
#=============================================
|
||||
# SDK CONFIG
|
||||
#=============================================
|
||||
#USE_SDRAM = 1
|
||||
WEB_INA219_DRV = 1
|
||||
#WEB_MLX90614_DRV = 1
|
||||
#WEB_ADC_DRV = 1
|
||||
|
|
@ -43,9 +44,9 @@ CFLAGS += -DLOGUART_STACK_SIZE=1024
|
|||
ADD_SRC_C += project/src/user/main.c
|
||||
ADD_SRC_C += project/src/user/user_start.c
|
||||
# components
|
||||
ADD_SRC_C += project/src/console/atcmd_user.c
|
||||
ADD_SRC_C += project/src/console/wifi_console.c
|
||||
ADD_SRC_C += project/src/console/wlan_tst.c
|
||||
DRAM_C += project/src/console/atcmd_user.c
|
||||
DRAM_C += project/src/console/wifi_console.c
|
||||
#DRAM_C += project/src/console/wlan_tst.c
|
||||
#ADD_SRC_C += project/src/console/pwm_tst.c
|
||||
|
||||
ifdef USE_SDCARD
|
||||
|
|
@ -76,8 +77,7 @@ ADD_SRC_C += project/src/adc_ws/adc_ws.c
|
|||
CFLAGS += -DWEB_ADC_DRV=1
|
||||
endif
|
||||
|
||||
|
||||
#Web-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
#Web
|
||||
INCLUDES += project/inc/web
|
||||
ADD_SRC_C += project/src/tcpsrv/tcp_srv_conn.c
|
||||
ADD_SRC_C += project/src/webfs/webfs.c
|
||||
|
|
@ -88,5 +88,3 @@ ADD_SRC_C += project/src/web/websock.c
|
|||
ADD_SRC_C += project/src/web/web_int_callbacks.c
|
||||
ADD_SRC_C += project/src/web/web_int_vars.c
|
||||
ADD_SRC_C += project/src/web/web_auth.c
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@
|
|||
#define CONFIG_EFUSE_NORMAL 1
|
||||
#undef CONFIG_EFUSE_TEST
|
||||
#define CONFIG_EFUSE_MODULE 1
|
||||
#ifdef RTL8711AM
|
||||
#if defined(RTL8711AM) || defined(USE_SDRAM)
|
||||
#define CONFIG_SDR_EN 1
|
||||
#endif
|
||||
#define CONFIG_SDR_NORMAL 1
|
||||
|
|
|
|||
Loading…
Reference in a new issue