update

USDK/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c

@@ -1,5 +1,5 @@
 /* 
- *  BootLoader Ver 0.3 (18/10/2017)
+ *  BootLoader Ver 0.3 (19/10/2017)
  *  Created on: 12/02/2017
  *      Author: pvvx
  */
@@ -38,11 +38,11 @@
 typedef struct _seg_header {
 	uint32 size;
 	uint32 ldaddr;
+	uint32 sign[2];
 } IMGSEGHEAD, *PIMGSEGHEAD;
 
 typedef struct _img2_header {
 	IMGSEGHEAD seg;
-	uint32 sign[2];
 	void (*startfunc)(void);
 	uint8 rtkwin[7];
 	uint8 ver[13];
@@ -530,10 +530,10 @@ LOCAL uint32 BOOT_RAM_TEXT_SECTION get_seg_id(uint32 addr, int32 size) {
 LOCAL uint32 BOOT_RAM_TEXT_SECTION load_img2_head(uint32 faddr, PIMG2HEAD hdr) {
 	flashcpy(faddr, hdr, sizeof(IMG2HEAD));
 	uint32 ret = get_seg_id(hdr->seg.ldaddr, hdr->seg.size);
-	if (hdr->sign[1] == IMG_SIGN2_RUN) {
+	if (hdr->seg.sign[1] == IMG_SIGN2_RUN) {
-		if (hdr->sign[0] == IMG_SIGN1_RUN) {
+		if (hdr->seg.sign[0] == IMG_SIGN1_RUN) {
 			ret |= 1 << 9;	// есть сигнатура RUN
-		} else if (hdr->sign[0] == IMG_SIGN1_SWP) {
+		} else if (hdr->seg.sign[0] == IMG_SIGN1_SWP) {
 			ret |= 1 << 8;  // есть сигнатура SWP
 		};
 	}

USDK/component/soc/realtek/8195a/fwlib/ram_lib/startup.c

@@ -1,5 +1,5 @@
 /* 
- *  StartUp USDK v0.2 (18/10/2017)
+ *  StartUp USDK v0.2 (19/10/2017)
  *  Created on: 02/03/2017
  *      Author: pvvx
  */
@@ -50,7 +50,7 @@ extern const unsigned char cus_sig[32]; // images name
 
 IMAGE2_START_RAM_FUN_SECTION RAM_START_FUNCTION gImage2EntryFun0 =
 	{ InfraStart + 1 };
-
+#ifdef CONFIG_SDR_EN
 #ifdef FIX_SDR_CALIBRATION // for speed :)
 #include "rtl8195a/rtl8195a_sdr.h"
 LOCAL void sdr_init(void) {
@@ -106,6 +106,7 @@ LOCAL void sdr_init(void) {
 	DBG_8195A(" ok\n");
 }
 #endif // FIX_SDR_CALIBRATION
+#endif // CONFIG_SDR_EN
 /*
 //----- HalNMIHandler_Patch
 void HalNMIHandler_Patch(void) {

USDK/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld

@@ -177,6 +177,7 @@ SECTIONS
 		LONG(0)
 		UartLogRamCmdTable = .;
 		KEEP(*(SORT(.mon.tab*)))
+		KEEP(*(SORT(.sdram.mon.tab*)))
 		UartLogRamCmdTable_end = .;
 		LONG(0)
 	} > BD_RAM

USDK/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img3.ld

@@ -0,0 +1,265 @@
+
+ENTRY(Reset_Handler)
+ENTRY(main)
+
+INCLUDE "export-rom_v04.txt"
+
+MEMORY
+{
+  ROM (rx)  		: ORIGIN = 0x000000,   LENGTH = 1M	    /* end 0x00100000 */
+  ROM_USED_RAM (rwx): ORIGIN = 0x10000000, LENGTH = 0x2400	/* end 0x10002400 */
+  BOOT_RAM (rwx)	: ORIGIN = 0x10000bc8, LENGTH = 21560	/* end 0x10006000 */
+  ROM_HEAP (rwx)	: ORIGIN = 0x10002400, LENGTH = 3K		/* end 0x10003000 */
+  RAM_HEAP1 (rwx)	: ORIGIN = 0x10003000, LENGTH = 12K		/* end 0x10006000 */
+  BD_RAM (rwx)		: ORIGIN = 0x10006000, LENGTH = 424K	/* end 0x10070000 */
+  TCM (rwx)			: ORIGIN = 0x1FFF0000, LENGTH = 64K		/* end 0x20000000 */
+  TCM_TAB (rwx)		: ORIGIN = 0x1FFFFD00, LENGTH = 768		/* end 0x20000000 */
+  SDRAM_RAM (rwx)	: ORIGIN = 0x30000000, LENGTH = 2M	 	/* end 0x30200000 */
+}
+
+EXTERN(RAM_IMG2_VALID_PATTEN)
+EXTERN(InfraStart)
+
+SECTIONS
+{
+	/* 0x00000000: ROM */
+
+	.rom :
+	{
+		__rom_image_start__ = .;
+		KEEP(*(.rom));
+		__rom_image_end__ = .;
+	} > ROM
+
+	/* 0x10000000: SRAM */
+	
+	.rom_ram : /* use in rom */
+	{
+		__ram_image_start__ = .;
+		KEEP(*(.ram_dedecated_vector_table)) 	/* 0x10000000: NewVectorTable */
+		KEEP(*(.ram_user_define_irq_table)) 	/* 0x10000100: UserIrqFunTable */
+		KEEP(*(.ram_user_define_data_table)) 	/* 0x10000200: UserIrqDataTable */
+		__rom_bss_start__ = .;
+		KEEP(*(.hal.ram.bss)) 					/* 0x10000300: CfgSysDebugWarn .. _pHAL_Gpio_Adapter */
+		KEEP(*(.timer2_7_vector_table.data))	/* 0x10000358: Timer2To7VectorTable */
+		KEEP(*(.infra.ram.bss)) 				/* 0x10000370: first .. z4 */
+		KEEP(*(.mon.ram.bss))					/* 0x10000384: pUartLogCtl .. ArgvArray */
+		KEEP(*(.wlan_ram_map)) 					/* 0x100006d4: rom_wlan_ram_map, FalseAlmCnt, ROMInfo, DM_CfoTrack */
+		KEEP(*(.ram.rom.wlanmap))				/* align(8) */
+		KEEP(*(.libc.ram.bss)) 					/* 0x10000760: rom_libgloss_ram_map __rtl_malloc_av_ __rtl_errno */
+		__rom_bss_end__ = .;
+	} > ROM_USED_RAM
+
+	/* 0x10000bc8: bootloader */
+
+	.ram_image1.text . : /* use in rom & boot */
+	{
+		/* __ram_start_table_start__ = .; */
+		__ram_image1_text_start__ = .;
+		KEEP(*(.boot.start.ram.data*)) 
+		/* __image1_validate_code__	= .; */
+		KEEP(*(.image1.validate.rodata))
+	
+	    KEEP(*(.infra.ram.data*))
+	    KEEP(*(.timer.ram.data*))
+	    KEEP(*(.cutb.ram.data*)) 
+	    KEEP(*(.cutc.ram.data*)) 
+		KEEP(*(.libc.reent)) 
+		KEEP(*(.rom.unc.data)) 
+		KEEP(*(.sdr.rand2.data))
+
+	    PROVIDE (__ram_image_end__ = .);		/* 0x100020c0: end */
+
+		/* boot & images data */
+
+	    KEEP(*(.hal.ram.data))
+		KEEP(*(.hal.flash.data))
+		KEEP(*(.boot.rodata*))
+		KEEP(*(.boot.text*))
+		KEEP(*(.boot.data*))
+	    __image1_bss_start__ = .;
+		KEEP(*(.boot.bss*))
+	    __image1_bss_end__ = .;
+		__ram_image1_text_end__ = .;
+
+	} > BOOT_RAM
+
+	.romheap :
+	{
+		__rom_heap_start__ = .; 
+		end = __rom_heap_start__;
+	  	. = ALIGN(0x1000);
+		__rom_heap_end__ = .; 
+	} > ROM_HEAP
+
+	.ram_heap1 : 
+	{
+  		__ram_heap1_start__ = .;
+		/*   *(.heap1*) */
+	} > RAM_HEAP1
+
+	.tcm :
+	{
+	  	__ram_tcm_start__ = .;
+  		__tcm_heap_start__ = .;
+	    *(.tcm.heap)
+	} > TCM
+
+	.soc_ps_monitor :
+	{ 
+  		__tcm_heap_end__ = .;
+	} > TCM_TAB
+
+	.image2.start.table :
+	{
+		__ram_heap1_end__ = .;
+		__ram_image2_text_start__ = .;
+		__image2_entry_func__ = .;
+		.image2.start.table1$$Base = .;
+		KEEP(*(SORT(.image2.ram.data*)))
+		__image2_validate_code__ = .;
+		KEEP(*(.image2.validate.rodata*))
+		KEEP(*(.custom.validate.rodata*))
+	} > BD_RAM
+
+	.sdr_text :
+	{
+		__sdram_data_start__ = .;
+	INCLUDE "sdram_obj.txt"
+		*(.sdram.text*) 
+	} > SDRAM_RAM
+
+	.sdr_rodata :
+	{
+		*(.sdram.rodata*) 
+	} > SDRAM_RAM
+
+	.sdr_data : 
+	{
+		*(.sdram.data*) 
+		__sdram_data_end__ = .;
+	} > SDRAM_RAM
+
+	.sdr_bss :
+	{
+		__sdram_bss_start__ = .;
+		*(.uvc.ram.bss)
+		*(.sdram.bss*)
+	INCLUDE "sdram_bss.txt"
+		__sdram_bss_end__ = .;
+		. = ALIGN(8);
+		__sdram_heap_start__ = .;
+	} > SDRAM_RAM
+	
+	.ram_image2.text :
+	{
+		*(.infra.ram.start*)
+		. = ALIGN(4);
+		KEEP(*(.init))
+
+		/* init data */
+		. = ALIGN(4);
+		PROVIDE (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE (__init_array_end = .);
+
+		. = ALIGN(4);
+		KEEP(*(.fini))
+
+		. = ALIGN(4);
+		PROVIDE (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE (__fini_array_end = .);
+
+		*(.mon.ram.text*)
+		*(.hal.flash.text*)	 
+		*(.hal.sdrc.text*)
+		*(.hal.gpio.text*)
+		*(.fwu.text*)
+		*(.otg.rom.text*)
+		*(.text*)
+/*		*(.sdram.text*) */
+		*(.p2p.text*)
+		*(.wps.text*)
+		*(.websocket.text*)
+	} > BD_RAM
+
+	.ram_image2.rodata :
+	{
+	*(.rodata*)
+		*(.fwu.rodata*)
+/*		*(.sdram.rodata*) */
+		*(.p2p.rodata*)
+		*(.wps.rodata*)
+		*(.websocket.rodata*)
+		. = ALIGN(4);
+		xHeapRegions = .;
+		LONG(__ram_heap1_start__)
+		LONG(__ram_heap1_end__ - __ram_heap1_start__)
+		LONG(__ram_heap2_start__)
+		LONG(__ram_heap2_end__ - __ram_heap2_start__)
+		LONG(__sdram_heap_start__)
+		LONG(__sdram_heap_end__ - __sdram_heap_start__)
+		LONG(0)
+		LONG(0)
+		UartLogRamCmdTable = .;
+		KEEP(*(SORT(.mon.tab*)))
+		KEEP(*(SORT(.sdram.mon.tab*)))
+		UartLogRamCmdTable_end = .;
+		LONG(0)
+	} > BD_RAM
+	
+	PROVIDE(UartLogRamCmdTableSize = UartLogRamCmdTable_end - UartLogRamCmdTable);
+
+	.ram.data : 
+	{
+		__data_start__ = .;
+		*(.data*)
+		*(.p2p.data*)
+		*(.wps.data*)
+		*(.websocket.data*)
+/*		*(.sdram.data*) */
+		__data_end__ = .;
+		__ram_image2_text_end__ = .;
+	} > BD_RAM
+	
+	.ram.bss :
+	{
+		__bss_start__ = .;
+		.ram.bss$$Base = .;
+		*(.hal.flash.data*)
+		*(.hal.sdrc.data*)
+		*(.hal.gpio.data*)
+		*(.fwu.data*)
+		*(.bdsram.data*)
+		*(.bfsram.data*)
+		*(COMMON)
+		*(.bss*)
+/*		*(.sdram.bss*) */
+		*(.p2p.bss*)
+		*(.wps.bss*)
+		*(.websocket.bss*)
+		*(.ssl_ram_map*)
+		__bss_end__ = .;
+		.ram.bss$$Limit = .;
+		
+	} > BD_RAM
+
+	.ram_heap2 : 
+	{
+		. = ALIGN(8);
+		__ram_heap2_start__ = .;
+		*(.heap*) /* ucHeap */
+	} > BD_RAM
+	__ram_heap2_end__ = 0x10070000;
+	
+	__sdram_heap_end__ = 0x30200000;
+
+	.boot.head :
+	{
+		KEEP(*(.loader.head*))
+	}
+	ASSERT(__ram_image_end__ == 0x100020c0, "Error rom-bios-boot code & data!")
+}

USDK/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/sdram_bss.txt

@@ -0,0 +1,42 @@
+/**** from lib_mdns.a ****/
+*DNSCommon.o(.bss*)
+*dnssd_clientlib.o(.bss*)
+*dnssd_clientshim.o(.bss*)
+*mDNS.o(.bss*)
+*mDNSMain.o(.bss*)
+*mDNSPosix.o(.bss*)
+*mDNSPosixOverwrite.o(.bss*)
+*posix.o(.bss*) 
+
+/**** from lib_uvc.a ****/
+*v4l2-dev.o(.bss*)
+*v4l2-device.o(.bss*)
+*v4l2-fh.o(.bss*)
+*v4l2_driver.o(.bss*)
+*v4l2_intf.o(.bss*)
+*videobuf2-core.o(.bss*)
+*uvc_ctrl.o(.bss*)
+*uvc_driver.o(.bss*)
+*uvc_intf.o(.bss*)
+*uvc_queue.o(.bss*)
+*uvc_v4l2.o(.bss*)
+*uvc_video.o(.bss*)
+
+/**** from lib_usb_otg_linux.a ***
+*dwc_common_os.o(.bss*)
+*dwc_otg_hcd_os.o(.bss*) */
+
+/**** from lib_usb_drv.a ****/
+*usb.o(.bss*) 
+
+/**** from lib_usb_otg.a ****/
+*dwc_os.o(.bss*)
+*dwc_otg_cil.o(.bss*)
+*dwc_otg_cil_intr.o(.bss*)
+*dwc_otg_common.o(.bss*)
+*dwc_otg_dbg.o(.bss*)
+*dwc_otg_driver.o(.bss*)
+*dwc_otg_hcd.o(.bss*)
+*dwc_otg_hcd_ddma.o(.bss*)
+*dwc_otg_hcd_intr.o(.bss*)
+*dwc_otg_hcd_queue.o(.bss*) 

USDK/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/sdram_obj.txt

@@ -0,0 +1,117 @@
+
+/**** from lib_mdns.a ****/
+*DNSCommon.o(.text*)
+*dnssd_clientlib.o(.text*)
+*dnssd_clientshim.o(.text*)
+*mDNS.o(.text*)
+*mDNSMain.o(.text*)
+*mDNSPosix.o(.text*)
+*mDNSPosixOverwrite.o(.text*)
+*posix.o(.text*)
+
+*DNSCommon.o(.rodata*)
+*dnssd_clientlib.o(.rodata*)
+*dnssd_clientshim.o(.rodata*)
+*mDNS.o(.rodata*)
+*mDNSMain.o(.rodata*)
+*mDNSPosix.o(.rodata*)
+*mDNSPosixOverwrite.o(.rodata*)
+*posix.o(.rodata*)
+
+*DNSCommon.o(.data*)
+*dnssd_clientlib.o(.data*)
+*dnssd_clientshim.o(.data*)
+*mDNS.o(.data*)
+*mDNSMain.o(.data*)
+*mDNSPosix.o(.data*)
+*mDNSPosixOverwrite.o(.data*)
+*posix.o(.data*)
+
+/**** from lib_uvc.a ****/
+*v4l2-dev.o(.text*)
+*v4l2-device.o(.text*)
+*v4l2-fh.o(.text*)
+*v4l2_driver.o(.text*)
+*v4l2_intf.o(.text*)
+*videobuf2-core.o(.text*)
+*uvc_ctrl.o(.text*)
+*uvc_driver.o(.text*)
+*uvc_intf.o(.text*)
+*uvc_queue.o(.text*)
+*uvc_v4l2.o(.text*)
+*uvc_video.o(.text*) 
+
+*v4l2-dev.o(.rodata*)
+*v4l2-device.o(.rodata*)
+*v4l2-fh.o(.rodata*)
+*v4l2_driver.o(.rodata*)
+*v4l2_intf.o(.rodata*)
+*videobuf2-core.o(.rodata*)
+*uvc_ctrl.o(.rodata*)
+*uvc_driver.o(.rodata*)
+*uvc_intf.o(.rodata*)
+*uvc_queue.o(.rodata*)
+*uvc_v4l2.o(.rodata*)
+*uvc_video.o(.rodata*) 
+
+*v4l2-dev.o(.data*)
+*v4l2-device.o(.data*)
+*v4l2-fh.o(.data*)
+*v4l2_driver.o(.data*)
+*v4l2_intf.o(.data*)
+*videobuf2-core.o(.data*)
+*uvc_ctrl.o(.data*)
+*uvc_driver.o(.data*)
+*uvc_intf.o(.data*)
+*uvc_queue.o(.data*)
+*uvc_v4l2.o(.data*)
+*uvc_video.o(.data*) 
+
+
+/**** from lib_usb_otg_linux.a ***
+*dwc_common_os.o(.text*)
+*dwc_otg_hcd_os.o(.text*) */
+*dwc_common_os.o(.rodata*)
+*dwc_otg_hcd_os.o(.rodata*) 
+*dwc_common_os.o(.data*)
+*dwc_otg_hcd_os.o(.data*) 
+
+
+/**** from lib_usb_drv.a ****/
+*usb.o(.text*) 
+*usb.o(.rodata*) 
+*usb.o(.data*) 
+
+/**** from lib_usb_otg.a ***
+*dwc_os.o(.text*)
+*dwc_otg_cil.o(.text*)
+*dwc_otg_cil_intr.o(.text*)
+*dwc_otg_common.o(.text*)
+*dwc_otg_dbg.o(.text*)
+*dwc_otg_driver.o(.text*)
+*dwc_otg_hcd.o(.text*)
+*dwc_otg_hcd_ddma.o(.text*)
+*dwc_otg_hcd_intr.o(.text*)
+*dwc_otg_hcd_queue.o(.text*) */
+
+*dwc_os.o(.rodata*)
+*dwc_otg_cil.o(.rodata*)
+*dwc_otg_cil_intr.o(.rodata*)
+*dwc_otg_common.o(.rodata*)
+*dwc_otg_dbg.o(.rodata*)
+*dwc_otg_driver.o(.rodata*)
+*dwc_otg_hcd.o(.rodata*)
+*dwc_otg_hcd_ddma.o(.rodata*)
+*dwc_otg_hcd_intr.o(.rodata*)
+*dwc_otg_hcd_queue.o(.rodata*)
+
+*dwc_os.o(.data*)
+*dwc_otg_cil.o(.data*)
+*dwc_otg_cil_intr.o(.data*)
+*dwc_otg_common.o(.data*)
+*dwc_otg_dbg.o(.data*)
+*dwc_otg_driver.o(.data*)
+*dwc_otg_hcd.o(.data*)
+*dwc_otg_hcd_ddma.o(.data*)
+*dwc_otg_hcd_intr.o(.data*)
+*dwc_otg_hcd_queue.o(.data*)

USDK/flasher/gdb_flasher.jlink

@@ -38,37 +38,38 @@ set mem inaccessible-by-default off
 # Setup GDB FOR FASTER DOWNLOADS
 set remote memory-write-packet-size 8192
 set remote memory-write-packet-size fixed
+set $SPI_FLASH_BASE = 0x98000000
 end
 #############
 # Boot_Flash
 define SetBootFlash
 printf "SetBoot = Flash:\n"
-monitor long 0x40000210 = 0x211157
+monitor long 0x40000210 = 0x00011113
 end
 # Boot RAM start_addr0() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 ) 
 define SetBootCall0
 printf "SetBoot = Call0:\n"
-monitor long 0x40000210 = 0x80111157
+monitor long 0x40000210 = 0x80011113
 end
 # Boot RAM start_addr1() Run if ( v40000210 & 0x20000000 ) 
 define SetBootCall1
 printf "SetBoot = Call1:\n"
-monitor long 0x40000210 = 0x20111157
+monitor long 0x40000210 = 0x20011113
 end
 # Boot RAM start_addr2() Run if ( v40000210 & 0x10000000 )
 define SetBootCall2
 printf "SetBoot = Call2:\n"
-monitor long 0x40000210 = 0x10111157
+monitor long 0x40000210 = 0x10011113
 end
 # Boot RAM start_addr3() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
 define SetBootCall3
 printf "SetBoot = Call3:\n"
-monitor long 0x40000210 = 0x8111157
+monitor long 0x40000210 = 0x8011113
 end
 # Boot RAM start_addr4() Init console, Run if ( v40000210 & 0x4000000 )
 define SetBootCall4
 printf "SetBoot = Call4:\n"
-monitor long 0x40000210 = 0x4111157
+monitor long 0x40000210 = 0x4011113
 end
 # CPU CLK 166 MHz?
 define SetClk166MHz
@@ -89,8 +90,7 @@ monitor long 0x40000304 = 0x1FC00002
 monitor long 0x40000250 = 0x400
 monitor long 0x40000340 = 0x0
 monitor long 0x40000230 = 0xdcc4
-monitor long 0x40000210 = 0x11117
+monitor long 0x40000210 = 0x11113
-monitor long 0x40000210 = 0x11157
 monitor long 0x400002c0 = 0x110011
 monitor long 0x40000320 = 0xffffffff
 end
@@ -125,7 +125,6 @@ monitor long 0x40006018 = 0
 monitor long 0x4000601C = 0
 #disable DMA
 monitor long 0x4000604C = 0
-set $SPI_FLASH_BASE = 0x98000000
 end
 ###################
 # SetFirwareSize #
@@ -154,7 +153,26 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
   printf "Image2Size = %d\n", $Image2Size
   printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
   set $FirmwareSize = $Image2Addr + $Image2Size
+  set $Image3Addr = $FirmwareSize 
+  set $parms1 = $rambuffer - $FirmwareSize
+  set $parms3 = $Image3Addr + 0x08
+  restore $arg0 binary $parms1 $Image3Addr $parms3
+  set $Image3Size = {int}($rambuffer)
+  set $Image3LoadAddr = {int}($rambuffer+0x4)
+  if $Image3Size != 0xFFFFFFFF && $Image3Size != 0
+   set $Image3Size = $Image3Size + 16
+   printf "Image3Size = %d\n", $Image3Size
+   printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
+   set $FirmwareSize = $Image3Addr + $Image3Size
    printf "FirmwareSize = %d\n", $FirmwareSize
+  else
+   set $Image3Size = 0
+   if $Image3LoadAddr == 0x30000000
+    set $FirmwareSize = $FirmwareSize + 8
+   end
+   printf "Image3 - None\n"
+   printf "FirmwareSize = %d\n", $FirmwareSize
+  end
  else
   set $Image2Size = 0
   printf "Image2 - None\n"
@@ -164,7 +182,9 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
 else
  set $Image1Size = 0
  set $Image2Size = 0
+ set $Image3Size = 0
  set $Image2Addr = 0
+ set $Image3Addr = 0
  set $FirmwareSize = 0
  printf "Image not format Firmware!\n"
 end 
@@ -173,6 +193,10 @@ end
 # Flash Images Info #
 #####################
 define FlashImagesInfo
+set $Image2Size = 0
+set $Image3Size = 0
+set $Image2Addr = 0
+set $Image3Addr = 0
 printf "Flash Info:\n"
 set $Image1Size = {int}($SPI_FLASH_BASE + 0x10) + 32
 set $Image1LoadAddr = {int}($SPI_FLASH_BASE + 0x14)
@@ -181,16 +205,26 @@ printf "Image1 - None\n"
 else
 set $Image2FlashAddr = {short}($SPI_FLASH_BASE + 0x18) * 1024
 if $Image2FlashAddr == 0 
-$Image2FlashAddr = $Image1Size 
+set $Image2FlashAddr = $Image1Size 
 end 
 set $Image2Size = {int}($Image2FlashAddr + $SPI_FLASH_BASE)
 set $Image2LoadAddr = {int}($Image2FlashAddr + $SPI_FLASH_BASE + 0x4)
 printf "Image1Size = %d\n", $Image1Size
 printf "Image1LoadAddr = 0x%08x\n", $Image1LoadAddr
 printf "Image2FlashAddr = 0x%08x\n", $Image2FlashAddr
-if $Image2Size != 0xFFFFFFFF
+if $Image2Size != 0xFFFFFFFF && $Image2Size != 0
 printf "Image2Size = %d\n", $Image2Size
 printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
+set $Image3FlashAddr = $Image2FlashAddr + $Image2Size + 0x10
+set $Image3Size = {int}($Image3FlashAddr + $SPI_FLASH_BASE)
+set $Image3LoadAddr = {int}($Image3FlashAddr + $SPI_FLASH_BASE + 0x4)
+if $Image3Size != 0xFFFFFFFF && $Image3Size !=0
+printf "Image3FlashAddr = 0x%08x\n", $Image3FlashAddr
+printf "Image3Size = %d\n", $Image3Size
+printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
+else
+printf "Image3 - None\n"
+end
 else
 printf "Image2 - None\n"
 end

USDK/flasher/gdb_wrflash.jlink

@@ -7,7 +7,6 @@ set $rtl8710_flasher_auto_erase = 1
 set $rtl8710_flasher_auto_verify = 1
 set $rtl8710_flasher_firmware_ptr = 0x10001000
 set $rtl8710_flasher_buffer = 0x10008000
-#262144
 set $rtl8710_flasher_buffer_size = 421888
 set $rtl8710_flasher_sector_size = 4096
 set $rtl8710_flasher_auto_erase_sector = 0xFFFFFFFF
@@ -37,11 +36,10 @@ if $rtl8710_flasher_capacity == 0
  monitor go
  FlasherWait
  set $id = {int}($rtl8710_flasher_buffer + 0x0C)
- if ($id == 0x1420c2) 
  set $rtl8710_flasher_capacity = 1 << (($id >> 16) & 0x0ff)
+ if ($id == 0x1420c2) 
   printf "Flash ID = 0x%08x : MX25L8006E (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10
  else 
-  set $rtl8710_flasher_capacity = {int}(1024*1024)
   printf "Flash ID = 0x%08x : (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10
  end
  printf "RTL8710 flasher initialized\n"
@@ -108,9 +106,9 @@ while $offset < $size
  end
  set $flash_offset = $arg1 + $offset
  printf "write offset 0x%08x\n", $flash_offset
- set $parms1 = $rtl8710_flasher_buffer + 0x20 - $offset - $arg1
+ set $parms1 = $rtl8710_flasher_buffer + 0x20 - $flash_offset
- set $parms2 = $offset + $arg1
+ set $parms2 = $flash_offset
- set $parms3 = $offset + $len + $arg1
+ set $parms3 = $flash_offset + $len
  restore $arg0 binary $parms1 $parms2 $parms3
  if $rtl8710_flasher_auto_erase != 0
   set $count_i = $flash_offset
@@ -154,7 +152,12 @@ if $Image1Size != 0
  #FlasherWrite $wr_flile 0 $Image1Size
  call2
  if $Image2Size != 0 && $Image2Addr >= $Image1Size
+  if $Image3Size != 0 && $Image3Addr > $Image2Size
+   set $Image2Size = $Image2Size + $Image3Size
+   printf "Write Image2&3 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
+  else
    printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
+  end
   #FlasherWrite $wr_flile $Image2Addr $Image2Size
   call3
  end

USDK/sdkset.mk

@@ -55,6 +55,7 @@ endif
 PATHLIBS = sdk/component/soc/realtek/8195a/misc/bsp/lib/common/gcc
 
 ifdef USE_SDRAM
+CFLAGS += -DUSE_SDRAM=1
 LDFILE ?= rlx8195A-symbol-v04-img3.ld
 else
 LDFILE ?= rlx8195A-symbol-v04-img2.ld

flasher/gdb_flasher.jlink

@@ -38,6 +38,7 @@ set mem inaccessible-by-default off
 # Setup GDB FOR FASTER DOWNLOADS
 set remote memory-write-packet-size 8192
 set remote memory-write-packet-size fixed
+set $SPI_FLASH_BASE = 0x98000000
 end
 #############
 # Boot_Flash
@@ -124,7 +125,6 @@ monitor long 0x40006018 = 0
 monitor long 0x4000601C = 0
 #disable DMA
 monitor long 0x4000604C = 0
-set $SPI_FLASH_BASE = 0x98000000
 end
 ###################
 # SetFirwareSize #
@@ -153,7 +153,26 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
   printf "Image2Size = %d\n", $Image2Size
   printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
   set $FirmwareSize = $Image2Addr + $Image2Size
+  set $Image3Addr = $FirmwareSize 
+  set $parms1 = $rambuffer - $FirmwareSize
+  set $parms3 = $Image3Addr + 0x08
+  restore $arg0 binary $parms1 $Image3Addr $parms3
+  set $Image3Size = {int}($rambuffer)
+  set $Image3LoadAddr = {int}($rambuffer+0x4)
+  if $Image3Size != 0xFFFFFFFF && $Image3Size != 0
+   set $Image3Size = $Image3Size + 16
+   printf "Image3Size = %d\n", $Image3Size
+   printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
+   set $FirmwareSize = $Image3Addr + $Image3Size
    printf "FirmwareSize = %d\n", $FirmwareSize
+  else
+   set $Image3Size = 0
+   if $Image3LoadAddr == 0x30000000
+    set $FirmwareSize = $FirmwareSize + 8
+   end
+   printf "Image3 - None\n"
+   printf "FirmwareSize = %d\n", $FirmwareSize
+  end
  else
   set $Image2Size = 0
   printf "Image2 - None\n"
@@ -163,7 +182,9 @@ if $Image1Size != 0 && $Image1Size < 0x1000000
 else
  set $Image1Size = 0
  set $Image2Size = 0
+ set $Image3Size = 0
  set $Image2Addr = 0
+ set $Image3Addr = 0
  set $FirmwareSize = 0
  printf "Image not format Firmware!\n"
 end 
@@ -172,6 +193,10 @@ end
 # Flash Images Info #
 #####################
 define FlashImagesInfo
+set $Image2Size = 0
+set $Image3Size = 0
+set $Image2Addr = 0
+set $Image3Addr = 0
 printf "Flash Info:\n"
 set $Image1Size = {int}($SPI_FLASH_BASE + 0x10) + 32
 set $Image1LoadAddr = {int}($SPI_FLASH_BASE + 0x14)
@@ -180,16 +205,26 @@ printf "Image1 - None\n"
 else
 set $Image2FlashAddr = {short}($SPI_FLASH_BASE + 0x18) * 1024
 if $Image2FlashAddr == 0 
-$Image2FlashAddr = $Image1Size 
+set $Image2FlashAddr = $Image1Size 
 end 
 set $Image2Size = {int}($Image2FlashAddr + $SPI_FLASH_BASE)
 set $Image2LoadAddr = {int}($Image2FlashAddr + $SPI_FLASH_BASE + 0x4)
 printf "Image1Size = %d\n", $Image1Size
 printf "Image1LoadAddr = 0x%08x\n", $Image1LoadAddr
 printf "Image2FlashAddr = 0x%08x\n", $Image2FlashAddr
-if $Image2Size != 0xFFFFFFFF
+if $Image2Size != 0xFFFFFFFF && $Image2Size != 0
 printf "Image2Size = %d\n", $Image2Size
 printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
+set $Image3FlashAddr = $Image2FlashAddr + $Image2Size + 0x10
+set $Image3Size = {int}($Image3FlashAddr + $SPI_FLASH_BASE)
+set $Image3LoadAddr = {int}($Image3FlashAddr + $SPI_FLASH_BASE + 0x4)
+if $Image3Size != 0xFFFFFFFF && $Image3Size !=0
+printf "Image3FlashAddr = 0x%08x\n", $Image3FlashAddr
+printf "Image3Size = %d\n", $Image3Size
+printf "Image3LoadAddr = 0x%08x\n", $Image3LoadAddr
+else
+printf "Image3 - None\n"
+end
 else
 printf "Image2 - None\n"
 end

flasher/gdb_wrflash.jlink

@@ -152,7 +152,12 @@ if $Image1Size != 0
  #FlasherWrite $wr_flile 0 $Image1Size
  call2
  if $Image2Size != 0 && $Image2Addr >= $Image1Size
+  if $Image3Size != 0 && $Image3Addr > $Image2Size
+   set $Image2Size = $Image2Size + $Image3Size
+   printf "Write Image2&3 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
+  else
    printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
+  end
   #FlasherWrite $wr_flile $Image2Addr $Image2Size
   call3
  end

project.mk

@@ -1,6 +1,7 @@
 #=============================================
 # SDK CONFIG
 #=============================================
+#USE_SDRAM = 1
 WEB_INA219_DRV = 1
 #WEB_MLX90614_DRV = 1
 #WEB_ADC_DRV = 1
@@ -43,9 +44,9 @@ CFLAGS += -DLOGUART_STACK_SIZE=1024
 ADD_SRC_C += project/src/user/main.c
 ADD_SRC_C += project/src/user/user_start.c
 # components
-ADD_SRC_C += project/src/console/atcmd_user.c
+DRAM_C += project/src/console/atcmd_user.c
-ADD_SRC_C += project/src/console/wifi_console.c
+DRAM_C += project/src/console/wifi_console.c
-ADD_SRC_C += project/src/console/wlan_tst.c
+#DRAM_C += project/src/console/wlan_tst.c
 #ADD_SRC_C += project/src/console/pwm_tst.c
 
 ifdef USE_SDCARD
@@ -76,8 +77,7 @@ ADD_SRC_C += project/src/adc_ws/adc_ws.c
 CFLAGS += -DWEB_ADC_DRV=1
 endif
 
-
+#Web
-#Web-<2D><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
 INCLUDES += project/inc/web
 ADD_SRC_C += project/src/tcpsrv/tcp_srv_conn.c
 ADD_SRC_C += project/src/webfs/webfs.c
@@ -88,5 +88,3 @@ ADD_SRC_C += project/src/web/websock.c
 ADD_SRC_C += project/src/web/web_int_callbacks.c
 ADD_SRC_C += project/src/web/web_int_vars.c
 ADD_SRC_C += project/src/web/web_auth.c
-
-

project/inc/platform_autoconf.h

@@ -145,7 +145,7 @@
 #define CONFIG_EFUSE_NORMAL 1
 #undef  CONFIG_EFUSE_TEST
 #define CONFIG_EFUSE_MODULE 1
-#ifdef RTL8711AM
+#if defined(RTL8711AM) || defined(USE_SDRAM)
 #define CONFIG_SDR_EN 1
 #endif
 #define CONFIG_SDR_NORMAL 1