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pvvx 2017-12-12 23:34:32 +03:00
parent b3dc0dda87
commit 0830a1244a
29 changed files with 240 additions and 152 deletions
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1
USDK/component/soc/realtek/8195a/fwlib/hal_misc.h
View file

@ -29,6 +29,7 @@ enum _HAL_RESET_REASON{
typedef u32 HAL_RESET_REASON;
#ifdef CONFIG_TIMER_MODULE
/* Min Step 31 us ! */
extern _LONG_CALL_ unsigned int HalDelayUs(unsigned int us);
#endif

2
USDK/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
View file

@ -291,7 +291,7 @@ LOCAL uint8 INFRA_START_SECTION _Get_ChipId() {
LOCAL void INFRA_START_SECTION sdr_preinit(void) {
HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0,
((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03)
((HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xfffff) | BIT_SYS_REGU_LDO25M_ADJ(0x03))); // ROM: BIT_SYS_REGU_LDO25M_ADJ(0x0e)? HAL RAM BIT_SYS_REGU_LDO25M_ADJ(0x03) L25EOUTVOLTAGE ?
LDO25M_CTRL(ON);
SRAM_MUX_CFG(0x2);
SDR_CLK_SEL(SDR_CLOCK_SEL_VALUE); // REG_PESOC_CLK_SEL

5
USDK/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
View file

@ -203,12 +203,12 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
HalReInitPlatformTimer(); // HalInitPlatformTimerV02(); HalTimerOpInit_Patch((VOID*) (&HalTimerOp));
SystemCoreClockUpdate();
En32KCalibration();
//---- Spic
// _memset(SpicInitParaAllClk, 0, sizeof(SpicInitParaAllClk));
*(uint32 *)(&SpicInitParaAllClk[0][0].BaudRate) = 0x01310202; // patch
*(uint32 *)(&SpicInitParaAllClk[1][0].BaudRate) = 0x11311301; // patch
// *(uint32 *)(&SpicInitParaAllClk[2][0].BaudRate) = 0x21311301; // patch
#ifdef CONFIG_SDR_EN
SPI_FLASH_PIN_FCTRL(ON);
/*
// uint8 SpicBaudRate = CPU_CLK_TYPE_NO - 1 - ((HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) >> 4) & 7);
@ -224,7 +224,6 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
};
*/
// SpicFlashInitRtl8195A(SpicDualBitMode); // SpicReadIDRtl8195A(); SpicDualBitMode
#ifdef CONFIG_SDR_EN
//---- SDRAM
uint8 ChipId = HalGetChipId();
if (ChipId >= CHIP_ID_8195AM) {
@ -253,9 +252,9 @@ extern HAL_GPIO_ADAPTER gBoot_Gpio_Adapter;
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT(21)); // Flag SDRAM Init or None
#else
HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~BIT(21))); // Flag SDRAM Not Init
#endif // CONFIG_SDR_EN
//----- Close Flash
SPI_FLASH_PIN_FCTRL(OFF);
#endif // CONFIG_SDR_EN
InitSoCPM();
VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler,

3
USDK/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
View file

@ -712,7 +712,8 @@ VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate)
}
ClockDivider &= 0xFFFE; // bit 0 always is 0
}
DBG_SSI_INFO("spi_frequency: Set SCLK Freq=%d\r\n", (ssi_clk/ClockDivider));
// DBG_SSI_INFO("spi_frequency: Set SCLK Freq=%d\r\n", (ssi_clk/ClockDivider));
DiagPrintf("spi_frequency: Set SCLK Freq=%d\r\n", (ssi_clk/ClockDivider));
pHalSsiAdapter->ClockDivider = ClockDivider;
SsiEn = HAL_SSI_READ32(spi_idx, REG_DW_SSI_SSIENR); // Backup SSI_EN register

2
USDK/component/soc/realtek/8195a/fwlib/src/hal_32k.c
View file

@ -67,7 +67,7 @@ En32KCalibration(
DiagPrintf("Check lock: %d\n", Ttemp);
DiagPrintf("0x278: %x\n", Rtemp);
#endif
if (Ttemp > 100000) { /*Delay 100ms*/
if (Ttemp > 100000/63) { /*Delay 100ms*/
DiagPrintf("32K Calibration Fail!\n", Ttemp);
break;
}

BIN
USDK/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/lib_wlan.a
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