2017-06-21 00:00:20 +00:00
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/*
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* Simple ADC DRV (adc_drv.h)
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*
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* Created on: 19 июн. 2017 г.
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* Author: pvvx
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*/
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#ifndef _DRIVER_ADC_DRV_H_
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#define _DRIVER_ADC_DRV_H_
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#include "rtl8195a.h"
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#include "rtl8195a_adc.h"
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void ADCIrqInit(IRQ_FUN IrqFunc, u32 IrqData, u32 intr_enable); // intr_enable = bits: REG_ADC_INTR_EN - BIT_ADC_FIFO_RD_ERROR_EN | BIT_ADC_FIFO_RD_REQ_EN | BIT_ADC_FIFO_FULL_EN ...
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void ADCIrqDeInit(void);
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2018-03-04 11:05:52 +00:00
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void ADCInit(unsigned char mode, unsigned char xclk, unsigned char dcmf);
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2017-06-21 00:00:20 +00:00
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void ADCDeInit(void);
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void ADCEnable(void); // ADC Start
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void ADCDisable(void); // ADC Stop
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2018-03-04 11:05:52 +00:00
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#define ADC_DECIMATION_1 1
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#define ADC_DECIMATION_2 2
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#define ADC_DECIMATION_4 3
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#define ADC_DECIMATION_8 4
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#define ADC_SAMPLE_CLK_x1 0
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#define ADC_SAMPLE_CLK_x2 1
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#define ADC_SAMPLE_CLK_x4 2
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#define ADC_SAMPLE_CLK_x8 3
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#define ADC_DECIMATION_FILTER ADC_DECIMATION_1
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#define ADC_SAMPLE_XCLK ADC_SAMPLE_CLK_x8
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#define ADC_SMPS = 975*(1<<ADC_SAMPLE_XCLK)/(1<<ADC_DECIMATION_FILTER)
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// 975*(1<<2)/(1<<1) = 1950 sps
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// Add ADC_ANAPAR_AD0
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#define BIT_SHIFT_ADC_SAMPLE_CLK 14
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#define BIT_MASK_ADC_SAMPLE_CLK 0x3
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#define BIT_CTRL_ADC_SAMPLE_CLKL(x) (((x) & BIT_MASK_ADC_SAMPLE_CLK) << BIT_SHIFT_ADC_SAMPLE_CLK)
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// Add ADC_ANAPAR_AD1
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#define BIT_SHIFT_DOWN_SAMPLE_RATE 18
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#define BIT_MASK_DOWN_SAMPLE_RATE 0x7
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#define BIT_CTRL_DOWN_SAMPLE_RATE(x) (((x) & BIT_MASK_DOWN_SAMPLE_RATE) << BIT_SHIFT_DOWN_SAMPLE_RATE)
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#define BIT_ADC_DECIMATION_FILTER_ORDER ((u32)0x00000001 << 12) /*!< decimation filter order, 0: order3, 1: order4 */
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#define BIT_ADC_EXT_VREF_EN ((u32)0x00000001 << 2)
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#define BIT_ADC_FEEDBK_CAPACITY_VAL ((u32)0x00000001 << 1)
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#define BIT_ADC_DIGITAL_RST_BAR ((u32)0x00000001 << 0)
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2017-06-21 00:00:20 +00:00
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#endif /* _DRIVER_ADC_DRV_H_ */
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