mirror of
https://github.com/pvvx/RTL00_HelloWorld.git
synced 2024-12-01 10:40:28 +00:00
738 lines
24 KiB
Text
738 lines
24 KiB
Text
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SECTIONS
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{
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__vectors_table = 0x0;
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Reset_Handler = 0x101;
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NMI_Handler = 0x109;
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HardFault_Handler = 0x10d;
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MemManage_Handler = 0x121;
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BusFault_Handler = 0x125;
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UsageFault_Handler = 0x129;
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HalLogUartInit = 0x201;
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HalSerialPutcRtl8195a = 0x2d9;
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HalSerialGetcRtl8195a = 0x309;
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HalSerialGetIsrEnRegRtl8195a = 0x329;
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HalSerialSetIrqEnRegRtl8195a = 0x335;
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HalCpuClkConfig = 0x341;
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HalGetCpuClk = 0x355;
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HalRomInfo = 0x39d;
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HalGetRomInfo = 0x3b5;
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HalResetVsr = 0x3c5;
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HalDelayUs = 0x899;
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HalNMIHandler = 0x8e1;
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HalHardFaultHandler = 0x911;
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HalMemManageHandler = 0xc09;
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HalBusFaultHandler = 0xc39;
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HalUsageFaultHandler = 0xc69;
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HalUart0PinCtrlRtl8195A = 0xcfd;
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HalUart1PinCtrlRtl8195A = 0xdc9;
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HalUart2PinCtrlRtl8195A = 0xe9d;
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HalSPI0PinCtrlRtl8195A = 0xf75;
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HalSPI1PinCtrlRtl8195A = 0x1015;
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HalSPI2PinCtrlRtl8195A = 0x10e5;
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HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
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HalI2C0PinCtrlRtl8195A = 0x1275;
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HalI2C1PinCtrlRtl8195A = 0x1381;
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HalI2C2PinCtrlRtl8195A = 0x1459;
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HalI2C3PinCtrlRtl8195A = 0x1529;
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HalI2S0PinCtrlRtl8195A = 0x1639;
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HalI2S1PinCtrlRtl8195A = 0x176d;
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HalPCM0PinCtrlRtl8195A = 0x1845;
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HalPCM1PinCtrlRtl8195A = 0x1949;
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HalSDIODPinCtrlRtl8195A = 0x1a1d;
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HalSDIOHPinCtrlRtl8195A = 0x1a6d;
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HalMIIPinCtrlRtl8195A = 0x1ab9;
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HalWLLEDPinCtrlRtl8195A = 0x1b51;
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HalWLANT0PinCtrlRtl8195A = 0x1c0d;
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HalWLANT1PinCtrlRtl8195A = 0x1c61;
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HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
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HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
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HalNFCPinCtrlRtl8195A = 0x1d59;
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HalPWM0PinCtrlRtl8195A = 0x1da9;
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HalPWM1PinCtrlRtl8195A = 0x1ead;
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HalPWM2PinCtrlRtl8195A = 0x1fb5;
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HalPWM3PinCtrlRtl8195A = 0x20b1;
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HalETE0PinCtrlRtl8195A = 0x21b9;
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HalETE1PinCtrlRtl8195A = 0x22c1;
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HalETE2PinCtrlRtl8195A = 0x23c9;
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HalETE3PinCtrlRtl8195A = 0x24d1;
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HalEGTIMPinCtrlRtl8195A = 0x25d9;
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HalSPIFlashPinCtrlRtl8195A = 0x2679;
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HalSDRPinCtrlRtl8195A = 0x2725;
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HalJTAGPinCtrlRtl8195A = 0x280d;
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HalTRACEPinCtrlRtl8195A = 0x2861;
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HalLOGUartPinCtrlRtl8195A = 0x28b9;
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HalLOGUartIRPinCtrlRtl8195A = 0x291d;
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HalSICPinCtrlRtl8195A = 0x2981;
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HalEEPROMPinCtrlRtl8195A = 0x29d9;
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HalDEBUGPinCtrlRtl8195A = 0x2a31;
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HalPinCtrlRtl8195A = 0x2b39;
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SpicRxCmdRtl8195A = 0x2e5d;
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SpicWaitBusyDoneRtl8195A = 0x2ea5;
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SpicGetFlashStatusRtl8195A = 0x2eb5;
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SpicWaitWipDoneRtl8195A = 0x2f55;
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SpicTxCmdRtl8195A = 0x2f6d;
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SpicSetFlashStatusRtl8195A = 0x2fc1;
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SpicCmpDataForCalibrationRtl8195A = 0x3049;
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SpicLoadInitParaFromClockRtl8195A = 0x3081;
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SpicInitRtl8195A = 0x30e5;
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SpicEraseFlashRtl8195A = 0x31bd;
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SpiFlashApp = 0x3279;
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HalPeripheralIntrHandle = 0x33b5;
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HalSysOnIntrHandle = 0x3439;
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HalWdgIntrHandle = 0x3485;
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HalTimer0IntrHandle = 0x34d5;
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HalTimer1IntrHandle = 0x3525;
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HalI2C3IntrHandle = 0x3575;
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HalTimer2To7IntrHandle = 0x35c5;
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HalSpi0IntrHandle = 0x3615;
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HalGpioIntrHandle = 0x3665;
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HalUart0IntrHandle = 0x36b5;
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HalSpiFlashIntrHandle = 0x3705;
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HalUsbOtgIntrHandle = 0x3755;
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HalSdioHostIntrHandle = 0x37a5;
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HalI2s0OrPcm0IntrHandle = 0x37f5;
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HalI2s1OrPcm1IntrHandle = 0x3845;
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HalWlDmaIntrHandle = 0x3895;
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HalWlProtocolIntrHandle = 0x38e5;
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HalCryptoIntrHandle = 0x3935;
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HalGmacIntrHandle = 0x3985;
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HalGdma0Ch0IntrHandle = 0x39d5;
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HalGdma0Ch1IntrHandle = 0x3a25;
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HalGdma0Ch2IntrHandle = 0x3a75;
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HalGdma0Ch3IntrHandle = 0x3ac5;
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HalGdma0Ch4IntrHandle = 0x3b15;
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HalGdma0Ch5IntrHandle = 0x3b65;
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HalGdma1Ch0IntrHandle = 0x3bb5;
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HalGdma1Ch1IntrHandle = 0x3c05;
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HalGdma1Ch2IntrHandle = 0x3c55;
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HalGdma1Ch3IntrHandle = 0x3ca5;
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HalGdma1Ch4IntrHandle = 0x3cf5;
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HalGdma1Ch5IntrHandle = 0x3d45;
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HalSdioDeviceIntrHandle = 0x3d95;
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VectorTableInitRtl8195A = 0x3de5;
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VectorTableInitForOSRtl8195A = 0x4019;
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VectorIrqRegisterRtl8195A = 0x4029;
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VectorIrqUnRegisterRtl8195A = 0x4091;
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VectorIrqEnRtl8195A = 0x40f1;
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VectorIrqDisRtl8195A = 0x418d;
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_UartRxDmaIrqHandle = 0x422d;
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HalRuartPutCRtl8195a = 0x4281;
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HalRuartGetCRtl8195a = 0x429d;
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HalRuartRTSCtrlRtl8195a = 0x42bd;
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HalRuartGetDebugValueRtl8195a = 0x42e1;
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HalRuartGetIMRRtl8195a = 0x43e1;
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HalRuartSetIMRRtl8195a = 0x442d;
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_UartIrqHandle = 0x4465;
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HalRuartDmaInitRtl8195a = 0x4681;
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HalRuartIntDisableRtl8195a = 0x4845;
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HalRuartDeInitRtl8195a = 0x4855;
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HalRuartIntEnableRtl8195a = 0x4985;
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_UartTxDmaIrqHandle = 0x4995;
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HalRuartRegIrqRtl8195a = 0x49d1;
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HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
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HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
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HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
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RuartLock = 0x4cc9;
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RuartUnLock = 0x4ced;
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HalRuartIntSendRtl8195a = 0x4d09;
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HalRuartDmaSendRtl8195a = 0x4e35;
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HalRuartStopSendRtl8195a = 0x4f89;
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HalRuartIntRecvRtl8195a = 0x504d;
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HalRuartDmaRecvRtl8195a = 0x51ad;
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HalRuartStopRecvRtl8195a = 0x52cd;
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RuartIsTimeout = 0x5385;
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HalRuartSendRtl8195a = 0x53b1;
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HalRuartRecvRtl8195a = 0x5599;
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RuartResetRxFifoRtl8195a = 0x5751;
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HalRuartResetRxFifoRtl8195a = 0x5775;
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HalRuartInitRtl8195a = 0x5829;
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HalGdmaOnOffRtl8195a = 0x5df1;
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HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
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HalGdmaChEnRtl8195a = 0x5e51;
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HalGdmaChDisRtl8195a = 0x5e6d;
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HalGdamChInitRtl8195a = 0x5e91;
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HalGdmaChSetingRtl8195a = 0x5ebd;
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HalGdmaChIsrCleanRtl8195a = 0x6419;
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HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
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HalGdmaChCleanAutoDstRtl8195a = 0x6501;
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HalEFUSEPowerSwitch8195AROM = 0x6561;
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HALEFUSEOneByteReadROM = 0x65f9;
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HALEFUSEOneByteWriteROM = 0x6699;
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rtl_memcmpb_v1_00 = 0x681d;
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rtl_random_v1_00 = 0x6861;
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rtl_align_to_be32_v1_00 = 0x6881;
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rtl_memsetw_v1_00 = 0x6899;
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rtl_memsetb_v1_00 = 0x68ad;
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rtl_memcpyw_v1_00 = 0x68bd;
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rtl_memcpyb_v1_00 = 0x68dd;
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rtl_memDump_v1_00 = 0x68f5;
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rtl_AES_set_encrypt_key = 0x6901;
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rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
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rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
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rtl_cryptoEngine_init_v1_00 = 0x6ea9;
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rtl_cryptoEngine_exit_v1_00 = 0x7055;
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rtl_cryptoEngine_reset_v1_00 = 0x70b1;
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rtl_cryptoEngine_v1_00 = 0x70ed;
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rtl_crypto_cipher_init_v1_00 = 0x7c69;
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rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
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rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
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HalSsiPinmuxEnableRtl8195a = 0x7cd5;
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HalSsiEnableRtl8195a = 0x7e45;
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HalSsiDisableRtl8195a = 0x7ef9;
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HalSsiLoadSettingRtl8195a = 0x7fad;
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HalSsiSetInterruptMaskRtl8195a = 0x8521;
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HalSsiGetInterruptMaskRtl8195a = 0x85c9;
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HalSsiSetSclkPolarityRtl8195a = 0x863d;
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HalSsiSetSclkPhaseRtl8195a = 0x8715;
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HalSsiWriteRtl8195a = 0x87e9;
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HalSsiSetDeviceRoleRtl8195a = 0x8861;
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HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
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HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
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HalSsiReadRtl8195a = 0x89b9;
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HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
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HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
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HalSsiGetStatusRtl8195a = 0x8b1d;
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HalSsiWriteableRtl8195a = 0x8b91;
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HalSsiReadableRtl8195a = 0x8c09;
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HalSsiBusyRtl8195a = 0x8c81;
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HalSsiReadInterruptRtl8195a = 0x8cf9;
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HalSsiWriteInterruptRtl8195a = 0x8efd;
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HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
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HalSsiGetInterruptStatusRtl8195a = 0x90d9;
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HalSsiInterruptEnableRtl8195a = 0x914d;
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HalSsiInterruptDisableRtl8195a = 0x9299;
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HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
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HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
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HalSsiInitRtl8195a = 0x94d1;
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_SsiReadInterrupt = 0x9ba5;
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_SsiWriteInterrupt = 0x9db1;
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_SsiIrqHandle = 0x9eb1;
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HalI2CWrite32 = 0xa061;
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HalI2CRead32 = 0xa09d;
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HalI2CDeInit8195a = 0xa0dd;
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HalI2CSendRtl8195a = 0xa1f1;
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HalI2CReceiveRtl8195a = 0xa25d;
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HalI2CEnableRtl8195a = 0xa271;
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HalI2CIntrCtrl8195a = 0xa389;
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HalI2CReadRegRtl8195a = 0xa3a1;
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HalI2CWriteRegRtl8195a = 0xa3b1;
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HalI2CSetCLKRtl8195a = 0xa3c5;
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HalI2CMassSendRtl8195a = 0xa6e9;
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HalI2CClrIntrRtl8195a = 0xa749;
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HalI2CClrAllIntrRtl8195a = 0xa761;
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HalI2CInit8195a = 0xa775;
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HalI2CDMACtrl8195a = 0xaa31;
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RtkI2CIoCtrl = 0xaa61;
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RtkI2CPowerCtrl = 0xaa65;
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HalI2COpInit = 0xaa69;
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I2CIsTimeout = 0xac65;
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I2CTXGDMAISRHandle = 0xb435;
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I2CRXGDMAISRHandle = 0xb4c1;
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RtkI2CIrqInit = 0xb54d;
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RtkI2CIrqDeInit = 0xb611;
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RtkI2CPinMuxInit = 0xb675;
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RtkI2CPinMuxDeInit = 0xb7c9;
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RtkI2CDMAInit = 0xb955;
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RtkI2CInit = 0xbc95;
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RtkI2CDMADeInit = 0xbdad;
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RtkI2CDeInit = 0xbe4d;
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RtkI2CSendUserAddr = 0xbee5;
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RtkI2CSend = 0xc07d;
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RtkI2CLoadDefault = 0xce51;
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RtkSalI2COpInit = 0xcf21;
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HalI2SWrite32 = 0xcf65;
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HalI2SRead32 = 0xcf85;
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HalI2SDeInitRtl8195a = 0xcfa9;
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HalI2STxRtl8195a = 0xcfc9;
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HalI2SRxRtl8195a = 0xd011;
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HalI2SEnableRtl8195a = 0xd05d;
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HalI2SIntrCtrlRtl8195a = 0xd0b1;
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HalI2SReadRegRtl8195a = 0xd0d1;
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HalI2SClrIntrRtl8195a = 0xd0dd;
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HalI2SClrAllIntrRtl8195a = 0xd0fd;
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HalI2SInitRtl8195a = 0xd11d;
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GPIO_GetIPPinName_8195a = 0xd2e5;
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GPIO_GetChipPinName_8195a = 0xd331;
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GPIO_PullCtrl_8195a = 0xd39d;
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GPIO_FuncOn_8195a = 0xd421;
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GPIO_FuncOff_8195a = 0xd481;
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GPIO_Int_Mask_8195a = 0xd4e9;
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GPIO_Int_SetType_8195a = 0xd511;
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HAL_GPIO_IrqHandler_8195a = 0xd5fd;
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HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
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HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
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HAL_GPIO_IntCtrl_8195a = 0xd6cd;
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HAL_GPIO_Init_8195a = 0xd805;
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HAL_GPIO_DeInit_8195a = 0xdac1;
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HAL_GPIO_ReadPin_8195a = 0xdbd1;
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HAL_GPIO_WritePin_8195a = 0xdc91;
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HAL_GPIO_RegIrq_8195a = 0xddad;
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HAL_GPIO_UnRegIrq_8195a = 0xddf5;
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HAL_GPIO_UserRegIrq_8195a = 0xde15;
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HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
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HAL_GPIO_MaskIrq_8195a = 0xdfc1;
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HAL_GPIO_UnMaskIrq_8195a = 0xe061;
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HAL_GPIO_IntDebounce_8195a = 0xe101;
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HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
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HAL_GPIO_PullCtrl_8195a = 0xe1c9;
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DumpForOneBytes = 0xe259;
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CmdRomHelp = 0xe419;
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CmdWriteWord = 0xe491;
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CmdDumpHelfWord = 0xe505;
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CmdDumpWord = 0xe5f1;
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CmdDumpByte = 0xe6f5;
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CmdSpiFlashTool = 0xe751;
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GetRomCmdNum = 0xe7a9;
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CmdWriteByte = 0xe7ad;
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Isspace = 0xe7ed;
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Strtoul = 0xe801;
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ArrayInitialize = 0xe8b1;
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GetArgc = 0xe8c9;
|
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GetArgv = 0xe8f9;
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UartLogCmdExecute = 0xe95d;
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UartLogShowBackSpace = 0xe9fd;
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UartLogRecallOldCmd = 0xea39;
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UartLogHistoryCmd = 0xea71;
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UartLogCmdChk = 0xeadd;
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UartLogIrqHandle = 0xebf5;
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RtlConsolInit = 0xecc5;
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RtlConsolTaskRom = 0xed49;
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RtlExitConsol = 0xed79;
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RtlConsolRom = 0xedcd;
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HalTimerOpInit = 0xee0d;
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HalTimerIrq2To7Handle = 0xee59;
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HalGetTimerIdRtl8195a = 0xef09;
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HalTimerInitRtl8195a = 0xef3d;
|
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HalTimerDisRtl8195a = 0xf069;
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HalTimerEnRtl8195a = 0xf089;
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HalTimerReadCountRtl8195a = 0xf0a9;
|
||
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HalTimerIrqClearRtl8195a = 0xf0bd;
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|
HalTimerDumpRegRtl8195a = 0xf0d1;
|
||
|
VSprintf = 0xf129;
|
||
|
DiagPrintf = 0xf39d;
|
||
|
DiagSPrintf = 0xf3b9;
|
||
|
DiagSnPrintf = 0xf3d1;
|
||
|
prvDiagPrintf = 0xf3ed;
|
||
|
prvDiagSPrintf = 0xf40d;
|
||
|
_memcmp = 0xf429;
|
||
|
_memcpy = 0xf465;
|
||
|
_memset = 0xf511;
|
||
|
Rand = 0xf585;
|
||
|
_strncpy = 0xf60d;
|
||
|
_strcpy = 0xf629;
|
||
|
prvStrCpy = 0xf639;
|
||
|
_strlen = 0xf651;
|
||
|
_strnlen = 0xf669;
|
||
|
prvStrLen = 0xf699;
|
||
|
_strcmp = 0xf6b1;
|
||
|
_strncmp = 0xf6d1;
|
||
|
prvStrCmp = 0xf719;
|
||
|
StrUpr = 0xf749;
|
||
|
prvAtoi = 0xf769;
|
||
|
prvStrStr = 0xf7bd;
|
||
|
_strsep = 0xf7d5;
|
||
|
skip_spaces = 0xf815;
|
||
|
skip_atoi = 0xf831;
|
||
|
_parse_integer_fixup_radix = 0xf869;
|
||
|
_parse_integer = 0xf8bd;
|
||
|
simple_strtoull = 0xf915;
|
||
|
simple_strtoll = 0xf945;
|
||
|
simple_strtoul = 0xf965;
|
||
|
simple_strtol = 0xf96d;
|
||
|
_vsscanf = 0xf985;
|
||
|
_sscanf = 0xff71;
|
||
|
div_u64 = 0xff91;
|
||
|
div_s64 = 0xff99;
|
||
|
div_u64_rem = 0xffa1;
|
||
|
div_s64_rem = 0xffb1;
|
||
|
_strpbrk = 0xffc1;
|
||
|
_strchr = 0xffed;
|
||
|
aes_set_key = 0x10005;
|
||
|
aes_encrypt = 0x103d1;
|
||
|
aes_decrypt = 0x114a5;
|
||
|
AES_WRAP = 0x125c9;
|
||
|
AES_UnWRAP = 0x12701;
|
||
|
crc32_get = 0x12861;
|
||
|
arc4_byte = 0x12895;
|
||
|
rt_arc4_init = 0x128bd;
|
||
|
rt_arc4_crypt = 0x12901;
|
||
|
rt_md5_init = 0x131c1;
|
||
|
rt_md5_append = 0x131f5;
|
||
|
rt_md5_final = 0x1327d;
|
||
|
rt_md5_hmac = 0x132d5;
|
||
|
rtw_get_bit_value_from_ieee_value = 0x13449;
|
||
|
rtw_is_cckrates_included = 0x13475;
|
||
|
rtw_is_cckratesonly_included = 0x134b5;
|
||
|
rtw_check_network_type = 0x134dd;
|
||
|
rtw_set_fixed_ie = 0x1350d;
|
||
|
rtw_set_ie = 0x1352d;
|
||
|
rtw_get_ie = 0x1355d;
|
||
|
rtw_set_supported_rate = 0x13591;
|
||
|
rtw_get_rateset_len = 0x13611;
|
||
|
rtw_get_wpa_ie = 0x1362d;
|
||
|
rtw_get_wpa2_ie = 0x136c9;
|
||
|
rtw_get_wpa_cipher_suite = 0x13701;
|
||
|
rtw_get_wpa2_cipher_suite = 0x13769;
|
||
|
rtw_parse_wpa_ie = 0x137d1;
|
||
|
rtw_parse_wpa2_ie = 0x138ad;
|
||
|
rtw_get_sec_ie = 0x13965;
|
||
|
rtw_get_wps_ie = 0x13a15;
|
||
|
rtw_get_wps_attr = 0x13a99;
|
||
|
rtw_get_wps_attr_content = 0x13b49;
|
||
|
rtw_ieee802_11_parse_elems = 0x13b91;
|
||
|
str_2char2num = 0x13d9d;
|
||
|
key_2char2num = 0x13db9;
|
||
|
convert_ip_addr = 0x13dd1;
|
||
|
rom_psk_PasswordHash = 0x13e9d;
|
||
|
rom_psk_CalcGTK = 0x13ed5;
|
||
|
rom_psk_CalcPTK = 0x13f69;
|
||
|
wep_80211_encrypt = 0x14295;
|
||
|
wep_80211_decrypt = 0x142f5;
|
||
|
tkip_micappendbyte = 0x14389;
|
||
|
rtw_secmicsetkey = 0x143d9;
|
||
|
rtw_secmicappend = 0x14419;
|
||
|
rtw_secgetmic = 0x14435;
|
||
|
rtw_seccalctkipmic = 0x1449d;
|
||
|
tkip_phase1 = 0x145a5;
|
||
|
tkip_phase2 = 0x14725;
|
||
|
tkip_80211_encrypt = 0x14941;
|
||
|
tkip_80211_decrypt = 0x149d5;
|
||
|
aes1_encrypt = 0x14a8d;
|
||
|
aesccmp_construct_mic_iv = 0x14c65;
|
||
|
aesccmp_construct_mic_header1 = 0x14ccd;
|
||
|
aesccmp_construct_mic_header2 = 0x14d21;
|
||
|
aesccmp_construct_ctr_preload = 0x14db5;
|
||
|
aes_80211_encrypt = 0x14e29;
|
||
|
aes_80211_decrypt = 0x151ad;
|
||
|
_sha1_process_message_block = 0x155b9;
|
||
|
_sha1_pad_message = 0x15749;
|
||
|
rt_sha1_init = 0x157e5;
|
||
|
rt_sha1_update = 0x15831;
|
||
|
rt_sha1_finish = 0x158a9;
|
||
|
rt_hmac_sha1 = 0x15909;
|
||
|
rom_aes_128_cbc_encrypt = 0x15a65;
|
||
|
rom_aes_128_cbc_decrypt = 0x15ae1;
|
||
|
rom_rijndaelKeySetupEnc = 0x15b5d;
|
||
|
rom_aes_decrypt_init = 0x15c39;
|
||
|
rom_aes_internal_decrypt = 0x15d15;
|
||
|
rom_aes_decrypt_deinit = 0x16071;
|
||
|
rom_aes_encrypt_init = 0x16085;
|
||
|
rom_aes_internal_encrypt = 0x1609d;
|
||
|
rom_aes_encrypt_deinit = 0x16451;
|
||
|
bignum_init = 0x17b35;
|
||
|
bignum_deinit = 0x17b61;
|
||
|
bignum_get_unsigned_bin_len = 0x17b81;
|
||
|
bignum_get_unsigned_bin = 0x17b85;
|
||
|
bignum_set_unsigned_bin = 0x17c21;
|
||
|
bignum_cmp = 0x17cd1;
|
||
|
bignum_cmp_d = 0x17cd5;
|
||
|
bignum_add = 0x17cfd;
|
||
|
bignum_sub = 0x17d0d;
|
||
|
bignum_mul = 0x17d1d;
|
||
|
bignum_exptmod = 0x17d2d;
|
||
|
WPS_realloc = 0x17d51;
|
||
|
os_zalloc = 0x17d99;
|
||
|
rom_hmac_sha256_vector = 0x17dc1;
|
||
|
rom_hmac_sha256 = 0x17ebd;
|
||
|
rom_sha256_vector = 0x18009;
|
||
|
phy_CalculateBitShift = 0x18221;
|
||
|
PHY_SetBBReg_8195A = 0x18239;
|
||
|
PHY_QueryBBReg_8195A = 0x18279;
|
||
|
ROM_odm_QueryRxPwrPercentage = 0x1829d;
|
||
|
ROM_odm_EVMdbToPercentage = 0x182bd;
|
||
|
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
|
||
|
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
|
||
|
ROM_odm_SetEDCCAThreshold = 0x18721;
|
||
|
ROM_odm_SetTRxMux = 0x18749;
|
||
|
ROM_odm_SetCrystalCap = 0x18771;
|
||
|
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
|
||
|
ROM_ODM_CfoTrackingReset = 0x187e9;
|
||
|
ROM_odm_CfoTrackingFlow = 0x18811;
|
||
|
curve25519_donna = 0x1965d;
|
||
|
aes_test_alignment_detection = 0x1a391;
|
||
|
aes_mode_reset = 0x1a3ed;
|
||
|
aes_ecb_encrypt = 0x1a3f9;
|
||
|
aes_ecb_decrypt = 0x1a431;
|
||
|
aes_cbc_encrypt = 0x1a469;
|
||
|
aes_cbc_decrypt = 0x1a579;
|
||
|
aes_cfb_encrypt = 0x1a701;
|
||
|
aes_cfb_decrypt = 0x1a9e5;
|
||
|
aes_ofb_crypt = 0x1acc9;
|
||
|
aes_ctr_crypt = 0x1af7d;
|
||
|
aes_encrypt_key128 = 0x1b289;
|
||
|
aes_encrypt_key192 = 0x1b2a5;
|
||
|
aes_encrypt_key256 = 0x1b2c1;
|
||
|
aes_encrypt_key = 0x1b2e1;
|
||
|
aes_decrypt_key128 = 0x1b351;
|
||
|
aes_decrypt_key192 = 0x1b36d;
|
||
|
aes_decrypt_key256 = 0x1b389;
|
||
|
aes_decrypt_key = 0x1b3a9;
|
||
|
aes_init = 0x1b419;
|
||
|
CRYPTO_chacha_20 = 0x1b41d;
|
||
|
CRYPTO_poly1305_init = 0x1bc25;
|
||
|
CRYPTO_poly1305_update = 0x1bd09;
|
||
|
CRYPTO_poly1305_finish = 0x1bd8d;
|
||
|
rom_sha512_starts = 0x1ceb5;
|
||
|
rom_sha512_update = 0x1d009;
|
||
|
rom_sha512_finish = 0x1d011;
|
||
|
rom_sha512 = 0x1d261;
|
||
|
rom_sha512_hmac_starts = 0x1d299;
|
||
|
rom_sha512_hmac_update = 0x1d35d;
|
||
|
rom_sha512_hmac_finish = 0x1d365;
|
||
|
rom_sha512_hmac_reset = 0x1d3b5;
|
||
|
rom_sha512_hmac = 0x1d3d1;
|
||
|
rom_sha512_hkdf = 0x1d40d;
|
||
|
rom_ed25519_gen_keypair = 0x1d501;
|
||
|
rom_ed25519_gen_signature = 0x1d505;
|
||
|
rom_ed25519_verify_signature = 0x1d51d;
|
||
|
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
|
||
|
rom_ed25519_crypto_sign_detached = 0x1d579;
|
||
|
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
|
||
|
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
|
||
|
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
|
||
|
rom_ed25519_ge_p3_tobytes = 0x207d5;
|
||
|
rom_ed25519_ge_scalarmult_base = 0x20821;
|
||
|
rom_ed25519_ge_tobytes = 0x209e1;
|
||
|
rom_ed25519_sc_muladd = 0x20a2d;
|
||
|
rom_ed25519_sc_reduce = 0x2603d;
|
||
|
rtl_memchr_v1_00 = 0x28a4d;
|
||
|
rtl_memcmp_v1_00 = 0x28ae1;
|
||
|
rtl_memcpy_v1_00 = 0x28b49;
|
||
|
__aeabi_memcpy = 0x28b49;
|
||
|
__aeabi_memcpy4 = 0x28b49;
|
||
|
rtl_memmove_v1_00 = 0x28bed;
|
||
|
rtl_memset_v1_00 = 0x28cb5;
|
||
|
__aeabi_memset = 0x28cb5;
|
||
|
rtl_strcat_v1_00 = 0x28d49;
|
||
|
rtl_strchr_v1_00 = 0x28d91;
|
||
|
rtl_strcmp_v1_00 = 0x28e55;
|
||
|
rtl_strcpy_v1_00 = 0x28ec9;
|
||
|
rtl_strlen_v1_00 = 0x28f15;
|
||
|
rtl_strncat_v1_00 = 0x28f69;
|
||
|
rtl_strncmp_v1_00 = 0x28fc5;
|
||
|
rtl_strncpy_v1_00 = 0x2907d;
|
||
|
rtl_strstr_v1_00 = 0x293cd;
|
||
|
rtl_strsep_v1_00 = 0x2960d;
|
||
|
rtl_strtok_v1_00 = 0x29619;
|
||
|
rtl__strtok_r_v1_00 = 0x2962d;
|
||
|
rtl_strtok_r_v1_00 = 0x29691;
|
||
|
rtl_close_v1_00 = 0x29699;
|
||
|
rtl_fstat_v1_00 = 0x296ad;
|
||
|
rtl_isatty_v1_00 = 0x296c1;
|
||
|
rtl_lseek_v1_00 = 0x296d5;
|
||
|
rtl_open_v1_00 = 0x296e9;
|
||
|
rtl_read_v1_00 = 0x296fd;
|
||
|
rtl_write_v1_00 = 0x29711;
|
||
|
rtl_sbrk_v1_00 = 0x29725;
|
||
|
rtl_ltoa_v1_00 = 0x297bd;
|
||
|
rtl_ultoa_v1_00 = 0x29855;
|
||
|
rtl_dtoi_v1_00 = 0x298c5;
|
||
|
rtl_dtoi64_v1_00 = 0x29945;
|
||
|
rtl_dtoui_v1_00 = 0x299dd;
|
||
|
rtl_ftol_v1_00 = 0x299e5;
|
||
|
rtl_itof_v1_00 = 0x29a51;
|
||
|
rtl_itod_v1_00 = 0x29ae9;
|
||
|
rtl_i64tod_v1_00 = 0x29b79;
|
||
|
rtl_uitod_v1_00 = 0x29c55;
|
||
|
rtl_ftod_v1_00 = 0x29d2d;
|
||
|
rtl_dtof_v1_00 = 0x29de9;
|
||
|
rtl_uitof_v1_00 = 0x29e89;
|
||
|
rtl_fadd_v1_00 = 0x29f65;
|
||
|
rtl_fsub_v1_00 = 0x2a261;
|
||
|
rtl_fmul_v1_00 = 0x2a559;
|
||
|
rtl_fdiv_v1_00 = 0x2a695;
|
||
|
rtl_dadd_v1_00 = 0x2a825;
|
||
|
rtl_dsub_v1_00 = 0x2aed9;
|
||
|
rtl_dmul_v1_00 = 0x2b555;
|
||
|
rtl_ddiv_v1_00 = 0x2b8ad;
|
||
|
rtl_dcmpeq_v1_00 = 0x2be4d;
|
||
|
rtl_dcmplt_v1_00 = 0x2bebd;
|
||
|
rtl_dcmpgt_v1_00 = 0x2bf51;
|
||
|
rtl_dcmple_v1_00 = 0x2c049;
|
||
|
rtl_fcmplt_v1_00 = 0x2c139;
|
||
|
rtl_fcmpgt_v1_00 = 0x2c195;
|
||
|
rtl_cos_f32_v1_00 = 0x2c229;
|
||
|
rtl_sin_f32_v1_00 = 0x2c435;
|
||
|
rtl_fabs_v1_00 = 0x2c639;
|
||
|
rtl_fabsf_v1_00 = 0x2c641;
|
||
|
rtl_dtoa_r_v1_00 = 0x2c77d;
|
||
|
__rom_mallocr_init_v1_00 = 0x2d7d1;
|
||
|
rtl_free_r_v1_00 = 0x2d841;
|
||
|
rtl_malloc_r_v1_00 = 0x2da31;
|
||
|
rtl_realloc_r_v1_00 = 0x2df55;
|
||
|
rtl_memalign_r_v1_00 = 0x2e331;
|
||
|
rtl_valloc_r_v1_00 = 0x2e421;
|
||
|
rtl_pvalloc_r_v1_00 = 0x2e42d;
|
||
|
rtl_calloc_r_v1_00 = 0x2e441;
|
||
|
rtl_cfree_r_v1_00 = 0x2e4a9;
|
||
|
rtl_Balloc_v1_00 = 0x2e515;
|
||
|
rtl_Bfree_v1_00 = 0x2e571;
|
||
|
rtl_i2b_v1_00 = 0x2e585;
|
||
|
rtl_multadd_v1_00 = 0x2e599;
|
||
|
rtl_mult_v1_00 = 0x2e629;
|
||
|
rtl_pow5mult_v1_00 = 0x2e769;
|
||
|
rtl_hi0bits_v1_00 = 0x2e809;
|
||
|
rtl_d2b_v1_00 = 0x2e845;
|
||
|
rtl_lshift_v1_00 = 0x2e901;
|
||
|
rtl_cmp_v1_00 = 0x2e9bd;
|
||
|
rtl_diff_v1_00 = 0x2ea01;
|
||
|
rtl_sread_v1_00 = 0x2eae9;
|
||
|
rtl_seofread_v1_00 = 0x2eb39;
|
||
|
rtl_swrite_v1_00 = 0x2eb3d;
|
||
|
rtl_sseek_v1_00 = 0x2ebc1;
|
||
|
rtl_sclose_v1_00 = 0x2ec11;
|
||
|
rtl_sbrk_r_v1_00 = 0x2ec41;
|
||
|
rtl_fflush_r_v1_00 = 0x2ef8d;
|
||
|
rtl_vfprintf_r_v1_00 = 0x2f661;
|
||
|
rtl_fpclassifyd = 0x30c15;
|
||
|
CpkClkTbl = 0x30c68;
|
||
|
ROM_IMG1_VALID_PATTEN = 0x30c80;
|
||
|
SpicCalibrationPattern = 0x30c88;
|
||
|
SpicInitCPUCLK = 0x30c98;
|
||
|
BAUDRATE = 0x30ca8;
|
||
|
OVSR = 0x30d1c;
|
||
|
DIV = 0x30d90;
|
||
|
OVSR_ADJ = 0x30e04;
|
||
|
__AES_rcon = 0x30e78;
|
||
|
__AES_Te4 = 0x30ea0;
|
||
|
I2CDmaChNo = 0x312a0;
|
||
|
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
|
||
|
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
|
||
|
_GPIO_SWPORT_DDR_TBL = 0x31594;
|
||
|
_GPIO_EXT_PORT_TBL = 0x31598;
|
||
|
_GPIO_SWPORT_DR_TBL = 0x3159c;
|
||
|
UartLogRomCmdTable = 0x316a0;
|
||
|
_HalRuartOp = 0x31700;
|
||
|
_HalGdmaOp = 0x31760;
|
||
|
RTW_WPA_OUI_TYPE = 0x3540c;
|
||
|
WPA_CIPHER_SUITE_NONE = 0x35410;
|
||
|
WPA_CIPHER_SUITE_WEP40 = 0x35414;
|
||
|
WPA_CIPHER_SUITE_TKIP = 0x35418;
|
||
|
WPA_CIPHER_SUITE_CCMP = 0x3541c;
|
||
|
WPA_CIPHER_SUITE_WEP104 = 0x35420;
|
||
|
RSN_CIPHER_SUITE_NONE = 0x35424;
|
||
|
RSN_CIPHER_SUITE_WEP40 = 0x35428;
|
||
|
RSN_CIPHER_SUITE_TKIP = 0x3542c;
|
||
|
RSN_CIPHER_SUITE_CCMP = 0x35430;
|
||
|
RSN_CIPHER_SUITE_WEP104 = 0x35434;
|
||
|
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
|
||
|
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
|
||
|
RSN_VERSION_BSD = 0x3544c;
|
||
|
rom_wps_Te0 = 0x35988;
|
||
|
rom_wps_rcons = 0x35d88;
|
||
|
rom_wps_Td4s = 0x35d94;
|
||
|
rom_wps_Td0 = 0x35e94;
|
||
|
__rom_b_cut_end__ = 0x4467c;
|
||
|
__rom_c_cut_text_start__ = 0x4467c;
|
||
|
HalInitPlatformLogUartV02 = 0x4467d;
|
||
|
HalReInitPlatformLogUartV02 = 0x4471d;
|
||
|
HalInitPlatformTimerV02 = 0x44755;
|
||
|
HalShowBuildInfoV02 = 0x447cd;
|
||
|
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
|
||
|
HalSpiInitV02 = 0x4488d;
|
||
|
HalBootFlowV02 = 0x44a29;
|
||
|
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
|
||
|
HalResetVsrV02 = 0x44b41;
|
||
|
HalI2CSendRtl8195aV02 = 0x44ce1;
|
||
|
HalI2CSetCLKRtl8195aV02 = 0x44d59;
|
||
|
RtkI2CSendV02 = 0x4508d;
|
||
|
RtkI2CReceiveV02 = 0x459a1;
|
||
|
HalI2COpInitV02 = 0x461ed;
|
||
|
I2CISRHandleV02 = 0x463e9;
|
||
|
RtkSalI2COpInitV02 = 0x46be1;
|
||
|
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
|
||
|
SpiFlashAppV02 = 0x46c85;
|
||
|
SpicInitRtl8195AV02 = 0x46dc5;
|
||
|
SpicEraseFlashRtl8195AV02 = 0x46ea1;
|
||
|
HalTimerIrq2To7HandleV02 = 0x46f5d;
|
||
|
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
|
||
|
HalTimerInitRtl8195aV02 = 0x4706d;
|
||
|
HalTimerReadCountRtl8195aV02 = 0x471b5;
|
||
|
HalTimerReLoadRtl8195aV02 = 0x471d1;
|
||
|
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
|
||
|
HalTimerDeInitRtl8195aV02 = 0x472c1;
|
||
|
HalTimerOpInitV02 = 0x472f9;
|
||
|
GPIO_LockV02 = 0x47345;
|
||
|
GPIO_UnLockV02 = 0x47379;
|
||
|
GPIO_Int_Clear_8195aV02 = 0x473a5;
|
||
|
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
|
||
|
FindElementIndexV02 = 0x47541;
|
||
|
HalRuartInitRtl8195aV02 = 0x4756d;
|
||
|
DramInit_rom = 0x47619;
|
||
|
ChangeRandSeed_rom = 0x47979;
|
||
|
Sdr_Rand2_rom = 0x47985;
|
||
|
MemTest_rom = 0x479dd;
|
||
|
SdrCalibration_rom = 0x47a45;
|
||
|
SdrControllerInit_rom = 0x47d99;
|
||
|
SDIO_EnterCritical = 0x47e39;
|
||
|
SDIO_ExitCritical = 0x47e85;
|
||
|
SDIO_IRQ_Handler_Rom = 0x47ec5;
|
||
|
SDIO_Interrupt_Init_Rom = 0x47f31;
|
||
|
SDIO_Device_Init_Rom = 0x47f81;
|
||
|
SDIO_Interrupt_DeInit_Rom = 0x48215;
|
||
|
SDIO_Device_DeInit_Rom = 0x48255;
|
||
|
SDIO_Enable_Interrupt_Rom = 0x48281;
|
||
|
SDIO_Disable_Interrupt_Rom = 0x482a1;
|
||
|
SDIO_Clear_ISR_Rom = 0x482c1;
|
||
|
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
|
||
|
SDIO_Free_Rx_Pkt_Rom = 0x48331;
|
||
|
SDIO_Recycle_Rx_BD_Rom = 0x48355;
|
||
|
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
|
||
|
SDIO_RxTask_Rom = 0x4851d;
|
||
|
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
|
||
|
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
|
||
|
SDIO_Process_RPWM_Rom = 0x485b5;
|
||
|
SDIO_Reset_Cmd_Rom = 0x485e9;
|
||
|
SDIO_Rx_Data_Transaction_Rom = 0x48611;
|
||
|
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
|
||
|
SDIO_Register_Tx_Callback_Rom = 0x488f5;
|
||
|
SDIO_ReadMem_Rom = 0x488fd;
|
||
|
SDIO_WriteMem_Rom = 0x489a9;
|
||
|
SDIO_SetMem_Rom = 0x48a69;
|
||
|
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
|
||
|
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
|
||
|
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
|
||
|
SDIO_TxTask_Rom = 0x48e9d;
|
||
|
SDIO_TaskUp_Rom = 0x48eed;
|
||
|
SDIO_Boot_Up = 0x48f55;
|
||
|
__rom_c_cut_text_end__ = 0x49070;
|
||
|
__rom_c_cut_rodata_start__ = 0x49070;
|
||
|
BAUDRATE_v02 = 0x49070;
|
||
|
OVSR_v02 = 0x490fc;
|
||
|
DIV_v02 = 0x49188;
|
||
|
OVSR_ADJ_v02 = 0x49214;
|
||
|
SdrDramInfo_rom = 0x492a0;
|
||
|
SdrDramTiming_rom = 0x492b4;
|
||
|
SdrDramModeReg_rom = 0x492e8;
|
||
|
SdrDramDev_rom = 0x49304;
|
||
|
__rom_c_cut_rodata_end__ = 0x49314;
|
||
|
NewVectorTable = 0x10000000;
|
||
|
UserIrqFunTable = 0x10000100;
|
||
|
UserIrqDataTable = 0x10000200;
|
||
|
__rom_bss_start__ = 0x10000300;
|
||
|
CfgSysDebugWarn = 0x10000300;
|
||
|
CfgSysDebugInfo = 0x10000304;
|
||
|
CfgSysDebugErr = 0x10000308;
|
||
|
ConfigDebugWarn = 0x1000030c;
|
||
|
ConfigDebugInfo = 0x10000310;
|
||
|
ConfigDebugErr = 0x10000314;
|
||
|
HalTimerOp = 0x10000318;
|
||
|
GPIOState = 0x10000334;
|
||
|
gTimerRecord = 0x1000034c;
|
||
|
SSI_DBG_CONFIG = 0x10000350;
|
||
|
_pHAL_Gpio_Adapter = 0x10000354;
|
||
|
Timer2To7VectorTable = 0x10000358;
|
||
|
pUartLogCtl = 0x10000384;
|
||
|
UartLogBuf = 0x10000388;
|
||
|
UartLogCtl = 0x10000408;
|
||
|
UartLogHistoryBuf = 0x10000430;
|
||
|
ArgvArray = 0x100006ac;
|
||
|
rom_wlan_ram_map = 0x100006d4;
|
||
|
FalseAlmCnt = 0x100006e0;
|
||
|
ROMInfo = 0x10000720;
|
||
|
DM_CfoTrack = 0x10000738;
|
||
|
rom_libgloss_ram_map = 0x10000760;
|
||
|
rtl_errno = 0x10000bc4;
|
||
|
_rtl_impure_ptr = 0x10001c60;
|
||
|
}
|