2017-02-19 19:48:36 +00:00
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/*
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2017-02-26 00:16:40 +00:00
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*
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2017-02-19 19:48:36 +00:00
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*/
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#define AUTOCONF_INCLUDED
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#define RTL8710AF
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//#define RTL8711AM
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/*
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* Target Platform Selection
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*/
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#define CONFIG_WITHOUT_MONITOR 1
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#undef CONFIG_RTL8195A
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#define CONFIG_RTL8195A 1
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#undef CONFIG_FPGA
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#undef CONFIG_RTL_SIM
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#undef CONFIG_POST_SIM
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/*
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* < Mass Production Option
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*/
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#undef CONFIG_MP
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#undef CONFIG_CP
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#undef CONFIG_FT
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#define RTL8195A 1
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2017-02-26 00:16:40 +00:00
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/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
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6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
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#define CONFIG_CPU_CLK 0
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//166.6MHZ - RUN/IDLE/SLP ~63/21/6.4 mA
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//83.3MHZ - RUN/IDLE/SLP ~55/15/6.4 mA
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//41.6MHZ - RUN/IDLE ~51/11 mA
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//20.8MHZ - RUN/IDLE ~49/9.5 mA
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//4MHZ - IDLE ~8 mA
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2017-02-19 19:48:36 +00:00
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#undef CONFIG_FPGA_CLK
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#define CONFIG_SDR_CLK 1
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#define CONFIG_SDR_100MHZ 1
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#undef CONFIG_SDR_50MHZ
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#undef CONFIG_SDR_25MHZ
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#undef CONFIG_SDR_12_5MHZ
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#define SDR_CLOCK_SEL_VALUE (0)
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#define CONFIG_BOOT_PROCEDURE 1
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#define CONFIG_IMAGE_PAGE_LOAD 1
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#undef CONFIG_IMAGE_AUTO_LOAD
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#undef CONFIG_IMAGE_PAGE_LOAD
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//#define CONFIG_IMAGE_AUTO_LOAD 1
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//#define CONFIG_BOOT_TO_UPGRADE_IMG2 1
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#undef CONFIG_PERI_UPDATE_IMG
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#define CONFIG_BOOT_FROM_JTAG 1
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#undef CONFIG_ALIGNMENT_EXCEPTION_ENABLE
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#define CONFIG_KERNEL 1
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#define PLATFORM_FREERTOS 1
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#undef PLATFORM_UCOSII
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#undef PLATFORM_ECOS
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#undef CONFIG_TASK_SCHEDUL_DIS
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#define TASK_SCHEDULER_DISABLED (0)
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#define CONFIG_NORMALL_MODE 1
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#undef CONFIG_MEMORY_VERIFY_MODE
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#define CONFIG_TIMER_EN 1
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#define CONFIG_TIMER_NORMAL 1
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#undef CONFIG_TIMER_TEST
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#define CONFIG_TIMER_MODULE 1
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#define CONFIG_WDG 1
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#undef CONFIG_WDG_NON
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#define CONFIG_WDG_NORMAL 1
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#define CONFIG_GDMA_EN 1
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#define CONFIG_GDMA_NORMAL 1
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#undef CONFIG_GDMA_TEST
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#define CONFIG_GDMA_MODULE 1
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#define CONFIG_WIFI_EN 1
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#define CONFIG_WIFI_NORMAL 1
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#undef CONFIG_WIFI_TEST
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#define CONFIG_WIFI_MODULE 1
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#define CONFIG_GPIO_EN 1
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#define CONFIG_GPIO_NORMAL 1
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#undef CONFIG_GPIO_TEST
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#define CONFIG_GPIO_MODULE 1
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#if defined(CONFIG_INIC) || (CONFIG_SDIOD)
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#define CONFIG_SDIO_DEVICE_EN 1
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#define CONFIG_SDIO_DEVICE_NORMAL 1
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#undef CONFIG_SDIO_DEVICE_TEST
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#define CONFIG_SDIO_DEVICE_MODULE 1
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#else
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#undef CONFIG_SDIO_DEVICE_EN
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#endif
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#define CONFIG_SDIO_HOST_EN 1
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//#define CONFIG_USB_EN 1
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#undef CONFIG_USB_NORMAL
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#define CONFIG_USB_TEST 1
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#define CONFIG_USB_MODULE 1
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#define CONFIG_USB_VERIFY 1
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#undef CONFIG_USB_ROM_LIB
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//#define CONFIG_USB_DBGINFO_EN 1
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#if defined(CONFIG_INIC) || (CONFIG_USBD)
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#define DWC_DEVICE_ONLY 1
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#else
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#define DWC_HOST_ONLY 1
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#define CONFIG_USB_HOST_ONLY 1
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#endif
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#define CONFIG_SPI_COM_EN 1
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#define CONFIG_SPI_COM_NORMAL 1
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#undef CONFIG_SPI_COM_TEST
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#define CONFIG_SPI_COM_MODULE 1
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#define CONFIG_UART_EN 1
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#define CONFIG_UART_NORMAL 1
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#undef CONFIG_UART_TEST
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#define CONFIG_UART_MODULE 1
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#define CONFIG_I2C_EN 1
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#define CONFIG_I2C_NORMAL 1
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#undef CONFIG_I2C_TEST
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#define CONFIG_I2C_MODULE 1
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#undef CONFIG_DEBUG_LOG_I2C_HAL
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#undef CONFIG_PCM_EN
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#define CONFIG_I2S_EN 1
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#define CONFIG_I2S_NORMAL 1
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#undef CONFIG_I2S_TEST
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#define CONFIG_I2S_MODULE 1
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#undef CONFIG_DEBUG_LOG_I2S_HAL
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#define CONFIG_NFC_EN 1
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#define CONFIG_NFC_NORMAL 1
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#undef CONFIG_NFC_TEST
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#define CONFIG_NFC_MODULE 1
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#define CONFIG_SOC_PS_EN 1
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#define CONFIG_SOC_PS_NORMAL 1
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#undef CONFIG_SOC_PS_TEST
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#define CONFIG_SOC_PS_MODULE 1 // hal_soc_ps_monitor.c
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//#define CONFIG_SOC_PS_VERIFY 1 // hal_soc_ps_monitor.c
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#define CONFIG_CRYPTO_EN 1
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#define CONFIG_CRYPTO_NORMAL 1
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#undef CONFIG_CRYPTO_TEST
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#define CONFIG_CRYPTO_MODULE 1
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2017-02-26 00:16:40 +00:00
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#define CONFIG_CRYPTO_STARTUP 0
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2017-02-19 19:48:36 +00:00
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#define CONFIG_MII_EN 1
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#define CONFIG_PWM_EN 1
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#define CONFIG_PWM_NORMAL 1
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#undef CONFIG_PWM_TEST
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#define CONFIG_PWM_MODULE 1
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#define CONFIG_EFUSE_EN 1 // common/mbed/targets/hal/rtl8195a/efuse_api.c
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#define CONFIG_EFUSE_NORMAL 1
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#undef CONFIG_EFUSE_TEST
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#define CONFIG_EFUSE_MODULE 1
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#ifdef RTL8711AM
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#define CONFIG_SDR_EN 1
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#endif
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#define CONFIG_SDR_NORMAL 1
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#undef CONFIG_SDR_TEST
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#define CONFIG_SDR_MODULE 1
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#define CONFIG_SPIC_EN 1
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#define CONFIG_SPIC_NORMAL 1
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#undef CONFIG_SPIC_TEST
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#define CONFIG_SPIC_MODULE 1
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#define CONFIG_ADC_EN 1
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//#define CONFIG_DAC_EN 1
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#define CONFIG_NOR_FLASH 1
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#undef CONFIG_SPI_FLASH
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#undef CONFIG_NAND_FLASH
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#undef CONFIG_NONE_FLASH
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#undef CONFIG_BTBX_EN
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// add pvvx
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#define CONFIG_LOG_UART_EN 1
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/*
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* < Engineer Mode Config
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*/
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#undef CONFIG_JTAG
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#undef CONFIG_COMPILE_FLASH_DOWNLOAD_CODE
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#undef CONIFG_COMPILE_EXTERNAL_SRAM_CALIBRATE
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#undef CONFIG_CMSIS_MATH_LIB_EN
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/*
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* < Application Config
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*/
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#define CONFIG_NETWORK 1
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#define CONFIG_RTLIB_EN 1
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#define CONFIG_RTLIB_NORMAL 1
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#undef CONFIG_RTLIB_TEST
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#define CONFIG_RTLIB_MODULE 1
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/*
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* < System Debug Message Config
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*/
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#define CONFIG_UART_LOG_HISTORY 1
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#undef CONFIG_CONSOLE_NORMALL_MODE
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#define CONFIG_CONSOLE_VERIFY_MODE 1
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/* CONFIG_DEBUG_LOG:
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=0 Off all diag/debug msg,
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=1 Only errors,
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=2 errors + warning, (default)
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=3 errors + warning + info,
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=4 errors + warning + info + debug,
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=5 full */
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2017-02-20 03:29:38 +00:00
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#define CONFIG_DEBUG_LOG 2
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2017-02-19 19:48:36 +00:00
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#if CONFIG_DEBUG_LOG > 0
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//#define CONFIG_DEBUG_ERR_MSG 1
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#define CONFIG_DEBUG_LOG_ADC_HAL 1
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#define CONFIG_DEBUG_LOG_I2S_HAL 1
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//#undef CONFIG_DEBUG_WARN_MSG
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//#undef CONFIG_DEBUG_INFO_MSG
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#endif // CONFIG_DEBUG_LOG
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/*
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* < SDK Option Config
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*/
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#undef CONFIG_MBED_ENABLED
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#undef CONFIG_APP_DEMO
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/*
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* < Select Chip Version
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*/
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#undef CONFIG_CHIP_A_CUT
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#define CONFIG_CHIP_B_CUT 1
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#undef CONFIG_CHIP_C_CUT
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#undef CONFIG_CHIP_E_CUT
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/*
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* < Select toolchain
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*/
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#undef CONFIG_TOOLCHAIN_ASDK
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#undef CONFIG_TOOLCHAIN_ARM_GCC
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/*
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* < Build Option
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*/
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#define CONFIG_LINK_ROM_LIB 1
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#undef CONFIG_LINK_ROM_SYMB
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#undef CONFIG_NORMAL_BUILD
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#undef CONFIG_RELEASE_BUILD
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#undef CONFIG_RELEASE_BUILD_LIBRARIES
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#undef CONFIG_LIB_BUILD_RAM
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#define CONFIG_RELEASE_BUILD_RAM_ALL 1
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#undef CONFIG_IMAGE_ALL
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#define CONFIG_IMAGE_SEPARATE 1
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2017-02-26 00:16:40 +00:00
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#if CONFIG_CPU_CLK < 6
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#define CPU_CLOCK_SEL_DIV5_3 0
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#define CPU_CLOCK_SEL_VALUE CONFIG_CPU_CLK
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2017-02-19 19:48:36 +00:00
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#else
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2017-02-26 00:16:40 +00:00
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#define CPU_CLOCK_SEL_DIV5_3 1
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#define CPU_CLOCK_SEL_VALUE (CONFIG_CPU_CLK-6)
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2017-02-19 19:48:36 +00:00
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#endif
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2017-02-26 00:16:40 +00:00
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#if CPU__CLK_DIV5_3
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#define PLATFORM_CLOCK (200000000ul>>CPU_CLOCK_SEL_VALUE)
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#else
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#define PLATFORM_CLOCK (((200000000ul*5ul)/3ul)>>CPU_CLOCK_SEL_VALUE)
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#endif
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