mirror of
https://github.com/pvvx/RTL00MP3.git
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112 lines
6.1 KiB
C
112 lines
6.1 KiB
C
/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "wait_api.h"
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#include "us_ticker_api.h"
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#include "platform_autoconf.h"
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#define WAIT_US_USE_CYCCNT
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#ifdef WAIT_US_USE_CYCCNT
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//#include "core_cm3.h"
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#ifdef __cplusplus
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#define __I volatile /*!< Defines 'read only' permissions */
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#else
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#define __I volatile const /*!< Defines 'read only' permissions */
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#endif
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#define __O volatile /*!< Defines 'write only' permissions */
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#define __IO volatile /*!< Defines 'read / write' permissions */
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typedef struct
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{
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__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
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__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
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__IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
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__IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
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} CoreDebug_Type;
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#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
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#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
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/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
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*/
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typedef struct
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{
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__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
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__IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
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__IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
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__IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
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__IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
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__IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
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__IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
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__I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
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__IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
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__IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
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__IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
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uint32_t RESERVED0[1];
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__IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
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__IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
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__IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
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uint32_t RESERVED1[1];
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__IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
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__IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
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__IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
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uint32_t RESERVED2[1];
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__IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
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__IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
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__IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
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} DWT_Type;
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#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
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#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
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#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
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#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
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#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
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#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
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#endif
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void wait(float s) { // До 1073741 секунд? 298 часов
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// wait_us((int)(s * 1000000.0f));
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vTaskDelay((int)(s * 1000.0f));
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}
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void wait_ms(int ms) { // До 1073741 секунд? 298 часов
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if(ms > 0) vTaskDelay(ms);
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// wait_us(ms * 1000);
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}
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void wait_us(int us) { // До 2.147483648 секунды!
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uint32_t start;
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#ifdef WAIT_US_USE_CYCCNT
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if(us < 1) return;
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if (us < 255) { // G-timer resolution is ~31 us (1/32K), use DWT->CYCCNT...
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if(!(DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk)) { // уже включен?
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CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; // открыть доступ
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DWT->CYCCNT = 0; // обнулить и запустить
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DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; // запустить счет
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}
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start = DWT->CYCCNT + us * ( PLATFORM_CLOCK / 1000000 );
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while ( ( ( int32_t )DWT->CYCCNT - start) < 0 );
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}
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else
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#endif
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{
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start = us_ticker_read(); // G-timer resolution is ~31 us (1/32K), and is a countdown timer
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while ((us_ticker_read() - start) < (uint32_t)us);
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}
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}
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