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pvvx 2017-04-22 16:44:33 +03:00
parent cf7a2d9683
commit f7b901aa27
76 changed files with 3753 additions and 3990 deletions
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3
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_diag.h
View file

@ -51,6 +51,9 @@
#define UART_STOP_1BIT 0x0
#define UART_STOP_2BIT 0x4
#ifndef DEFAULT_BAUDRATE
#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
#endif
#define HAL_UART_READ32(addr) HAL_READ32(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE32(addr, value) HAL_WRITE32(LOG_UART_REG_BASE, addr, value)

2
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/hal_misc_v0.c
View file

@ -336,7 +336,7 @@ PatchHalInitPlatformLogUart(
UartIrqHandle.Priority = 0;
//4 Inital Log uart
UartAdapter.BaudRate = UART_BAUD_RATE_38400;
UartAdapter.BaudRate = DEFAULT_BAUDRATE;
UartAdapter.DataLength = UART_DATA_LEN_8BIT;
UartAdapter.FIFOControl = 0xC1;
UartAdapter.IntEnReg = 0x00;

5
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/rtl_boot.c
View file

@ -13,8 +13,9 @@
//-------------------------------------------------------------------------
// Data declarations
#define DEFAULT_BAUDRATE UART_BAUD_RATE_38400
#ifndef DEFAULT_BAUDRATE
#define DEFAULT_BAUDRATE 38400
#endif
/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */

1
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h
View file

@ -616,6 +616,7 @@
#define BIT_MASK_XTAL_DRV_RF_LATCH 0xffffffffL
#define BIT_XTAL_DRV_RF_LATCH(x) (((x) & BIT_MASK_XTAL_DRV_RF_LATCH) << BIT_SHIFT_XTAL_DRV_RF_LATCH)
// BIT25 - To release DAC delta sigma clock gating
//2 REG_RSVD

74
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pwm.c
View file

@ -3,8 +3,8 @@
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
* --------------------------
* bug fixing: pvvx
*/
@ -15,9 +15,10 @@
#include "rtl8195a_pwm.h"
#include "hal_pwm.h"
extern HAL_PWM_ADAPTER PWMPin[];
//extern HAL_PWM_ADAPTER PWMPin[];
extern HAL_TIMER_OP HalTimerOp;
//extern HAL_TIMER_OP HalTimerOp;
extern u32 gTimerRecord;
/**
* @brief Configure a G-Timer to generate a tick with certain time.
@ -33,33 +34,30 @@ Pwm_SetTimerTick_8195a(
u32 tick_time
)
{
TIMER_ADAPTER TimerAdapter;
if (tick_time <= MIN_GTIMER_TIMEOUT) {
tick_time = MIN_GTIMER_TIMEOUT;
}
else {
tick_time = (((tick_time-1)/TIMER_TICK_US)+1) * TIMER_TICK_US;
}
// Initial a G-Timer for the PWM pin
if (pPwmAdapt->tick_time != tick_time) {
TimerAdapter.IrqDis = 1; // Disable Irq
TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) NULL;
TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
TimerAdapter.IrqHandle.Priority = 10;
TimerAdapter.IrqHandle.Data = (u32)NULL;
TimerAdapter.TimerId = pPwmAdapt->gtimer_id;
TimerAdapter.TimerIrqPriority = 0;
TimerAdapter.TimerLoadValueUs = tick_time-1;
TimerAdapter.TimerMode = 1; // auto-reload with user defined value
HalTimerOp.HalTimerInit((VOID*) &TimerAdapter);
pPwmAdapt->tick_time = tick_time;
DBG_PWM_INFO("%s: Timer_Id=%d Count=%d\n", __FUNCTION__, pPwmAdapt->gtimer_id, tick_time);
// if timer is running ?
if(gTimerRecord & (1 << pPwmAdapt->gtimer_id)) {
HalTimerReLoadRtl8195a_Patch(pPwmAdapt->gtimer_id, tick_time);
} else {
TIMER_ADAPTER TimerAdapter;
TimerAdapter.IrqDis = 1; // Disable Irq
TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) NULL;
TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
TimerAdapter.IrqHandle.Priority = 10;
TimerAdapter.IrqHandle.Data = (u32)NULL;
TimerAdapter.TimerId = pPwmAdapt->gtimer_id;
TimerAdapter.TimerIrqPriority = 0;
TimerAdapter.TimerLoadValueUs = tick_time-1;
TimerAdapter.TimerMode = 1; // auto-reload with user defined value
HalTimerInitRtl8195a_Patch((VOID*) &TimerAdapter);
}
}
}
@ -95,7 +93,7 @@ HAL_Pwm_SetDuty_8195a(
period = MIN_GTIMER_TIMEOUT*2;
}
else {
tick_time = period / 0x3fc; // a duty cycle be devided into 1020 ticks
tick_time = period / 1020; // 0x3fc; // a duty cycle be devided into 1020 ticks
if (tick_time < MIN_GTIMER_TIMEOUT) {
tick_time = MIN_GTIMER_TIMEOUT;
}
@ -103,36 +101,24 @@ HAL_Pwm_SetDuty_8195a(
Pwm_SetTimerTick_8195a(pPwmAdapt, tick_time);
tick_time = pPwmAdapt->tick_time;
#if 0
// Check if current tick time needs adjustment
if ((pPwmAdapt->tick_time << 12) <= period) {
// need a longger tick time
}
else if ((pPwmAdapt->tick_time >> 2) >= period) {
// need a shorter tick time
}
#endif
period_tick = period/tick_time;
if (period_tick == 0) {
period_tick = 1;
}
if (pulse_width >= period) {
// pulse_width = period-1;
pulse_width = period;
}
pulsewidth_tick = pulse_width/tick_time;
if (pulsewidth_tick == 0) {
// pulsewidth_tick = 1;
}
timer_id = pPwmAdapt->gtimer_id;
pPwmAdapt->period = period_tick & 0x3ff;
pPwmAdapt->pulsewidth = pulsewidth_tick & 0x3ff;
pPwmAdapt->period = period_tick & BIT_MASK_PERI_PWM0_PERIOD;
pPwmAdapt->pulsewidth = pulsewidth_tick & BIT_MASK_PERI_PWM0_DUTY;
RegAddr = REG_PERI_PWM0_CTRL + (pwm_id*4);
RegValue = BIT31 | (timer_id<<24) | (pulsewidth_tick<<12) | period_tick;
RegValue = BIT_PERI_PWM0_EN | BIT_PERI_PWM0_GT_SEL(timer_id) | BIT_PERI_PWM0_DUTY(pulsewidth_tick) | BIT_PERI_PWM0_PERIOD(period_tick);
HAL_WRITE32(PERI_ON_BASE, RegAddr, RegValue);
}
@ -157,10 +143,10 @@ HAL_Pwm_Init_8195a(
pwm_id = pPwmAdapt->pwm_id;
pin_sel = pPwmAdapt->sel;
// Initial a G-Timer for the PWM pin
Pwm_SetTimerTick_8195a(pPwmAdapt, MIN_GTIMER_TIMEOUT);
//p/ Pwm_SetTimerTick_8195a(pPwmAdapt, MIN_GTIMER_TIMEOUT);
// Set default duty ration
HAL_Pwm_SetDuty_8195a(pPwmAdapt, 20000, 10000);
//p/ HAL_Pwm_SetDuty_8195a(pPwmAdapt, 20000, 10000);
// Configure the Pin Mux
PinCtrl((PWM0+pwm_id), pin_sel, 1);
@ -187,7 +173,7 @@ HAL_Pwm_Enable_8195a(
// Configure the Pin Mux
if (!pPwmAdapt->enable) {
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 1);
HalTimerOp.HalTimerEn(pPwmAdapt->gtimer_id);
HalTimerEnRtl8195a_Patch(pPwmAdapt->gtimer_id);
pPwmAdapt->enable = 1;
}
}
@ -211,7 +197,7 @@ HAL_Pwm_Disable_8195a(
// Configure the Pin Mux
if (pPwmAdapt->enable) {
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 0);
HalTimerOp.HalTimerDis(pPwmAdapt->gtimer_id);
HalTimerDisRtl8195a(pPwmAdapt->gtimer_id);
pPwmAdapt->enable = 0;
}
}

4
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c
View file

@ -142,8 +142,6 @@ HalRuartResetTRxFifoRtl8195a(
return HAL_OK;
}
extern u64 div_u64(u64 dividend, u32 divisor);
HAL_Status
HalRuartGenBaudRateRtl8195a(
IN RUART_SPEED_SETTING *pBaudSetting
@ -154,7 +152,7 @@ HalRuartGenBaudRateRtl8195a(
u32 min_err=0xffffffff;
u32 uart_ovsr;
u32 uart_ovsr_mod;
u32 min_uart_ovsr =0; // ovsr with mini err
u32 min_uart_ovsr; // ovsr with mini err
u32 min_uart_ovsr_mod;
u64 uart_clock;
u32 divisor_temp;

48
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_adc.c
View file

@ -650,7 +650,7 @@ RtkADCPinMuxInit(
ADCLocalTemp |= BIT25;
/* To release DAC delta sigma clock gating */
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_SYSPLL_CTRL2,ADCLocalTemp);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL2, ADCLocalTemp);
/* Turn on DAC active clock */
ACTCK_ADC_CCTRL(ON);
@ -1267,12 +1267,14 @@ RtkADCReceive(
pHALADCGdmaAdpt->MuliBlockCunt = 0;
pHALADCGdmaOp->HalGdmaChSeting(pHALADCGdmaAdpt);
pHALADCGdmaOp->HalGdmaChEn(pHALADCGdmaAdpt);
pSalADCHND->DevSts = ADC_STS_RX_ING;
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat |= BIT_ADC_PWR_AUTO;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
pHALADCGdmaOp->HalGdmaChEn(pHALADCGdmaAdpt);
pSalADCHND->DevSts = ADC_STS_RX_ING;
return _EXIT_SUCCESS;
}
return _EXIT_FAILURE;
@ -1288,9 +1290,6 @@ RtkADCReceiveBuf(
PSAL_ADC_HND pSalADCHND = (PSAL_ADC_HND) Data;
PSAL_ADC_HND_PRIV pSalADCHNDPriv = NULL;
PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt = NULL;
PHAL_ADC_OP pHalADCOP = NULL;
//PIRQ_HANDLE pIrqHandleADCGdma = NULL;
@ -1299,13 +1298,8 @@ RtkADCReceiveBuf(
/* To Get the SAL_I2C_MNGT_ADPT Pointer */
pSalADCHNDPriv = CONTAINER_OF(pSalADCHND, SAL_ADC_HND_PRIV, SalADCHndPriv);
pSalADCMngtAdpt = CONTAINER_OF(pSalADCHNDPriv->ppSalADCHnd, SAL_ADC_MNGT_ADPT, pSalHndPriv);
pHalADCOP = pSalADCMngtAdpt->pHalOp;
pHalADCOP = pSalADCMngtAdpt->pHalOp;
/* Clear ADC Status */
//HAL_ADC_READ32(REG_ADC_INTR_STS);
@ -1315,11 +1309,12 @@ RtkADCReceiveBuf(
//DBG_8195A(">>INTR:%x\n",AdcTempDat);
ADCFullStsFlag = 0;
HalDelayUs(2000);
/// HalDelayUs(2000); ?
HalDelayUs(20);
DBG_ADC_INFO("RtkADCReceiveBuf, Check to enable ADC manully or not\n");
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER);
if (unlikely((AdcTempDat & 0x00000008) == 0)) {
if (unlikely((AdcTempDat & BIT_ADC_ISO_MANUAL) == 0)) {
;
}
else {
@ -1329,23 +1324,22 @@ RtkADCReceiveBuf(
//AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER);
}
pSalADCHND->pInitDat->ADCIntrMSK = (BIT_ADC_FIFO_FULL_EN);
pHalADCOP->HalADCIntrCtrl(pSalADCHND->pInitDat);
pSalADCHND->DevSts = ADC_STS_IDLE;
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
if ((AdcTempDat & 0x00000001) == 0){
if ((AdcTempDat & BIT_ADC_EN_MANUAL) == 0){
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
DBG_ADC_INFO("RtkADCReceiveBuf, Before set, Reg AD1:%x\n", AdcTempDat);
AdcTempDat |= (0x01);
AdcTempDat |= BIT_ADC_EN_MANUAL;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
DBG_ADC_INFO("RtkADCReceiveBuf, After set, Reg AD1:%x\n", AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("RtkADCReceiveBuf, Before set, Reg AD0:%x\n", AdcTempDat);
AdcTempDat |= (0x01);
AdcTempDat |= BIT_ADC_EN_MANUAL;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("RtkADCReceiveBuf, After set, Reg AD0:%x\n", AdcTempDat);
@ -1359,14 +1353,14 @@ RtkADCReceiveBuf(
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("RtkADCReceiveBuf, End of ADC, Before set, AD0:%x\n", AdcTempDat);
AdcTempDat &= (~0x01);
AdcTempDat &= (~BIT_ADC_EN_MANUAL);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("RtkADCReceiveBuf, End of ADC, After set, AD0:%x\n", AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
DBG_ADC_INFO("RtkADCReceiveBuf, End of ADC, Before set, AD1:%x\n", AdcTempDat);
AdcTempDat &= (~0x01);
AdcTempDat &= (~BIT_ADC_EN_MANUAL);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
DBG_ADC_INFO("RtkADCReceiveBuf, End of ADC, After set, AD1:%x\n", AdcTempDat);
@ -1410,7 +1404,7 @@ RtkADCRxManualRotate(
DBG_ADC_INFO("RtkADCRxManualRotate, Check to enable ADC manully or not\n");
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER);
if (unlikely((AdcTempDat & 0x00000008) == 0)) {
if (unlikely((AdcTempDat & BIT_ADC_ISO_MANUAL) == 0)) {
;
}
else {
@ -1426,7 +1420,7 @@ RtkADCRxManualRotate(
pSalADCHND->DevSts = ADC_STS_IDLE;
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
if ((AdcTempDat & 0x00000001) == 0){
if ((AdcTempDat & BIT_ADC_EN_MANUAL) == 0){
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
DBG_ADC_INFO("RtkADCRxManualRotate, Before set, Reg AD1:%x\n", AdcTempDat);
/* Clear for manual rotrate first*/
@ -1435,7 +1429,7 @@ RtkADCRxManualRotate(
AdcTempDat |= (BIT0);
/* Enable manual mode, this is to turn cali. off */
AdcTempDat &= ~(BIT11);
// AdcTempDat &= ~(BIT11);
AdcTempDat |= (BIT11);
/* Set rotation to default state
@ -1476,7 +1470,7 @@ RtkADCRxManualRotate(
/* Read Content */
for (tempcnt=0; tempcnt<16; tempcnt++){
ADCDatBuf[0] = (u32)HAL_ADC_READ32(REG_ADC_FIFO_READ);
ADCDatBuf[0] = (u32)HAL_ADC_READ32(REG_ADC_FIFO_READ);
}
/* Close ADC */
@ -1507,7 +1501,7 @@ RtkADCRxManualRotate(
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("RtkADCRxManualRotate, Before set, Reg AD0:%x\n", AdcTempDat);
AdcTempDat |= (0x01);
AdcTempDat |= BIT_ADC_EN_MANUAL;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("RtkADCRxManualRotate, After set, Reg AD0:%x\n", AdcTempDat);
@ -1537,14 +1531,14 @@ RtkADCRxManualRotate(
/* Close ADC */
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("RtkADCRxManualRotate, End of ADC, Before set, AD0:%x\n", AdcTempDat);
AdcTempDat &= (~0x01);
AdcTempDat &= (~BIT_ADC_EN_MANUAL);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("RtkADCRxManualRotate, End of ADC, After set, AD0:%x\n", AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
DBG_ADC_INFO("RtkADCRxManualRotate, End of ADC, Before set, AD1:%x\n", AdcTempDat);
AdcTempDat &= (~0x01);
AdcTempDat &= (~BIT0);
/* Disable manual mode */
AdcTempDat &= (~BIT11);

6
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_log_uart.c
View file

@ -161,7 +161,7 @@ void HalLogUartIrqHandle(VOID * Data) {
void HalLogUartSetBaudRate(HAL_LOG_UART_ADAPTER *pUartAdapter) {
u32 clk4 = HalGetCpuClk() >> 2; // PLATFORM_CLOCK/2; // (unsigned int) HalGetCpuClk() >> 2; // div 4
if (pUartAdapter->BaudRate == 0)
pUartAdapter->BaudRate = UART_BAUD_RATE_38400;
pUartAdapter->BaudRate = DEFAULT_BAUDRATE;
u32 br16 = pUartAdapter->BaudRate << 4; // * 16
if ((br16 != 0) && (br16 <= clk4)) {
unsigned int dll = clk4 / br16;
@ -200,7 +200,7 @@ u32 HalLogUartInitSetting(HAL_LOG_UART_ADAPTER *pUartAdapter) {
// HalPinCtrlRtl8195A(LOG_UART, 0, 1); ????
u32 clk4 = HalGetCpuClk() >> 2; // PLATFORM_CLOCK/2; // (unsigned int) HalGetCpuClk() >> 2; // div 4
if (pUartAdapter->BaudRate == 0)
pUartAdapter->BaudRate = UART_BAUD_RATE_38400;
pUartAdapter->BaudRate = DEFAULT_BAUDRATE;
u32 br16 = pUartAdapter->BaudRate << 4; // * 16
HAL_UART_WRITE32(UART_INTERRUPT_EN_REG_OFF, 0); // 40003004 = 0;
if (br16 <= clk4) {
@ -418,7 +418,7 @@ void HalInitLogUart(void) {
HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL,
HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_LOG_UART_EN); // 40000230 |= 0x1000u;
HalPinCtrlRtl8195A(LOG_UART, 0, 1);
UartAdapter.BaudRate = UART_BAUD_RATE_38400;
UartAdapter.BaudRate = DEFAULT_BAUDRATE;
UartAdapter.DataLength = UART_DATA_LEN_8BIT;
UartAdapter.FIFOControl = FCR_RX_TRIG_MASK | FCR_FIFO_EN; // 0xC1;
UartAdapter.IntEnReg = IER_ERBFI | IER_ELSI; // 5

4
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pwm.c
View file

@ -3,8 +3,8 @@
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
* --------------------------
* bug fixing: pvvx
*/

21
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c
View file

@ -46,7 +46,6 @@ PatchHalLogUartInit(
u32 Divisor;
u32 Dlh;
u32 Dll;
u32 SysClock;
/*
Interrupt enable Register
@ -71,21 +70,11 @@ PatchHalLogUartInit(
// set up buad rate division
#ifdef CONFIG_FPGA
SysClock = SYSTEM_CLK;
Divisor = (SysClock / (16 * (UartAdapter.BaudRate)));
Divisor = (SYSTEM_CLK / (16 * (UartAdapter.BaudRate)));
#else
{
u32 SampleRate, Remaind;
SysClock = HalGetCpuClk() >> 2;
SampleRate = (16 * (UartAdapter.BaudRate));
Divisor= SysClock/SampleRate;
Remaind = ((SysClock*10)/SampleRate) - (Divisor*10);
if (Remaind > 4) Divisor++;
Divisor = HalGetCpuClk()/(32 * UartAdapter.BaudRate);
Divisor = (Divisor & 1) + (Divisor >> 1);
}
#endif
@ -98,7 +87,7 @@ PatchHalLogUartInit(
HAL_UART_WRITE32(UART_DLL_OFF, Dll);
HAL_UART_WRITE32(UART_DLH_OFF, Dlh);
// clear DLAB bit
HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 0);
// HAL_UART_WRITE32(UART_LINE_CTL_REG_OFF, 0); // есть далее
// set data format
SetData = UartAdapter.Parity | UartAdapter.Stop | UartAdapter.DataLength;
@ -160,7 +149,7 @@ PSHalInitPlatformLogUart(
UartIrqHandle.Priority = 0;
//4 Inital Log uart
UartAdapter.BaudRate = UART_BAUD_RATE_38400;
UartAdapter.BaudRate = DEFAULT_BAUDRATE;
UartAdapter.DataLength = UART_DATA_LEN_8BIT;
UartAdapter.FIFOControl = 0xC1;
UartAdapter.IntEnReg = 0x00;

4
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_ssi.c
View file

@ -547,13 +547,13 @@ HalSsiInit(VOID *Data)
DBG_SSI_ERR("Invalid SPI Index.\n");
break;
}
/*
ret = FunctionChk(Function, (u32)PinmuxSelect);
if(ret == _FALSE){
DBG_SSI_ERR("Invalid Pinmux Setting.\n");
return HAL_ERR_PARA;
}
*/
#ifdef CONFIG_SOC_PS_MODULE
REG_POWER_STATE SsiPwrState;
#endif