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delete '!!!'

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pvvx 2017-02-28 10:40:07 +03:00
parent de57c04fb4
commit ed4c83a935
44 changed files with 206 additions and 187 deletions
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40
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_32k.c
View file

@ -19,9 +19,9 @@ En32KCalibration(
{
u32 Rtemp;
u32 Ttemp = 0;
//DiagPrintf("32K clock source calibration\n");
#if CONFIG_DEBUG_LOG > 5
DiagPrintf("32K clock source calibration\n");
#endif
//set parameter
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL0, 0);
//offset 1 = 0x1500
@ -57,16 +57,20 @@ En32KCalibration(
Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_OSC32K_REG_CTRL1);
if ((Rtemp & 0x3000) != 0x0){
//DiagPrintf("32.768 Calibration Success\n", Ttemp);
#if CONFIG_DEBUG_LOG > 5
DiagPrintf("32.768 Calibration Success\n", Ttemp);
#endif
break;
}
else {
Ttemp++;
HalDelayUs(30);
//DiagPrintf("Check lock: %d\n", Ttemp);
//DiagPrintf("0x278: %x\n", Rtemp);
#if CONFIG_DEBUG_LOG > 5
DiagPrintf("Check lock: %d\n", Ttemp);
DiagPrintf("0x278: %x\n", Rtemp);
#endif
if (Ttemp > 100000) { /*Delay 100ms*/
DiagPrintf("32K Calibration Fail!!\n", Ttemp);
DiagPrintf("32K Calibration Fail!\n", Ttemp);
break;
}
}
@ -78,6 +82,10 @@ WDG_ADAPTER WDGAdapter;
extern HAL_TIMER_OP HalTimerOp;
#ifdef CONFIG_WDG_NORMAL
/*
* pvvx: if WDT RESET_MODE:
* HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & 0x1FFFFF);
*/
VOID
WDGInitial(
IN u32 Period
@ -93,8 +101,9 @@ WDGInitial(
u32 PeriodTemp = 0;
u32 *Reg = (u32*)&(WDGAdapter.Ctrl);
DBG_8195A(" Period = 0x%08x\n", Period);
#if CONFIG_DEBUG_LOG > 1
DBG_8195A("WdgPeriod = %d ms\n", Period);
#endif
for (CountId = 0; CountId < 12; CountId++) {
CountTemp = ((0x00000001 << (CountId+1))-1);
DivFactor = (u16)((PeriodProcess)/(CountTemp*3));
@ -111,18 +120,20 @@ WDGInitial(
}
}
DBG_8195A("WdgScalar = 0x%08x\n", DivFacProcess);
DBG_8195A("WdgCunLimit = 0x%08x\n", CountProcess);
#if CONFIG_DEBUG_LOG > 4
DBG_8195A("WdgScalar = %p\n", DivFacProcess);
DBG_8195A("WdgCunLimit = %p\n", CountProcess);
#endif
WDGAdapter.Ctrl.WdgScalar = DivFacProcess;
WDGAdapter.Ctrl.WdgEnByte = 0;
WDGAdapter.Ctrl.WdgClear = 1;
WDGAdapter.Ctrl.WdgCunLimit = CountProcess;
WDGAdapter.Ctrl.WdgMode = RESET_MODE;
WDGAdapter.Ctrl.WdgToISR = 0;
#if CONFIG_DEBUG_LOG > 4
DBG_8195A("WdgCtrl = %p\n", (u32)(*Reg));
#endif
HAL_WRITE32(VENDOR_REG_BASE, 0, (*Reg));
}
VOID
@ -160,6 +171,7 @@ WDGIrqInitial(
InterruptRegister(&(WDGAdapter.IrqHandle));
InterruptEn(&(WDGAdapter.IrqHandle));
WDGAdapter.Ctrl.WdgToISR = 1; // clear ISR first
WDGAdapter.Ctrl.WdgMode = INT_MODE;
HAL_WRITE32(VENDOR_REG_BASE, 0, ((*Temp)));

6
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_i2c.c
View file

@ -358,7 +358,7 @@ I2CISRHandle_Patch(
if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) &
BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(1)) {
I2CStsTmp = pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_TX_ABRT_SOURCE);
DBG_I2C_ERR("!!!I2C%d INTR_TX_ABRT!!!\n",I2CIrqIdx);
DBG_I2C_ERR("!I2C%d INTR_TX_ABRT!\n",I2CIrqIdx);
DBG_I2C_ERR("I2C%d IC_TX_ABRT_SOURCE[%2x]: %x\n", I2CIrqIdx, REG_DW_I2C_IC_TX_ABRT_SOURCE, I2CStsTmp);
DBG_I2C_ERR("Dev Sts:%x\n",pSalI2CHND->DevSts);
DBG_I2C_ERR("rx len:%x\n",pSalI2CHND->pRXBuf->DataLen);
@ -579,7 +579,7 @@ I2CISRHandle_Patch(
if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) &
BIT_CTRL_IC_INTR_STAT_R_TX_OVER(1)) {
DBG_I2C_ERR("!!!I2C%d INTR_TX_OVER!!!\n",I2CIrqIdx);
DBG_I2C_ERR("!I2C%d INTR_TX_OVER!\n",I2CIrqIdx);
/* Clear I2C interrupt */
pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_TX_OVER;
@ -778,7 +778,7 @@ I2CISRHandle_Patch(
if (pHalI2COP->HalI2CReadReg(pHalI2CInitDat,REG_DW_I2C_IC_INTR_STAT) &
BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(1)) {
DBG_I2C_ERR("!!!I2C%d INTR_RX_UNDER!!!\n",I2CIrqIdx);
DBG_I2C_ERR("!I2C%d INTR_RX_UNDER!\n",I2CIrqIdx);
pHalI2CInitDat->I2CIntrClr = REG_DW_I2C_IC_CLR_RX_UNDER;
pHalI2COP->HalI2CClrIntr(pHalI2CInitDat);

2
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
View file

@ -310,7 +310,7 @@ SdrTestApp(
//1 "SdrControllerInit" is located in Image1, so we shouldn't call it in Image2
if (!SdrControllerInit()) {
DBG_8195A("SDR Calibartion Fail!!!!\n");
DBG_8195A("SDR Calibartion Fail!\n");
}
break;
case 2:

6
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c
View file

@ -8,6 +8,7 @@
*/
#include "rtl8195a.h"
#include "hal_soc_ps_monitor.h"
#include "rtl_consol.h"
#include "PinNames.h"
#include "gpio_api.h"
@ -135,6 +136,8 @@ PatchHalLogUartInit(
return 0;
}
//_LONG_CALL_ extern VOID UartLogIrqHandle(VOID * Data); // in ROM
extern void UartLogIrqHandleRam(void * data);
VOID
PSHalInitPlatformLogUart(
VOID
@ -443,7 +446,7 @@ CLKCal(
RRTemp = (((2133/Rtemp) >> x) - 1);
}
if ( x == 5 )
DiagPrintf("Using ana to cal is not allowed!!\n");
DiagPrintf("Using ana to cal is not allowed!\n");
return RRTemp;
}
@ -1902,7 +1905,6 @@ DeepSleep(
}
}
VOID
DSleep_GPIO(
VOID

4
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c
View file

@ -369,7 +369,7 @@ SpicFlashInitRtl8195A(
#endif
break;
default:
DBG_8195A("No Support SPI Mode!!!!!!!!\n");
DBG_8195A("No Support SPI Mode!\n");
break;
}
@ -1455,7 +1455,7 @@ SpicNVMCalStore(u8 BitMode, u8 CpuClk)
}
else {
// There is a parameter on the flash memory already
DBG_SPIF_ERR("SpicNVMCalStore: The flash memory(@0x%x = 0x%x) is not able to be write, Erase it first!!\r\n",
DBG_SPIF_ERR("SpicNVMCalStore: The flash memory(@0x%x = 0x%x) is not able to be write, Erase it first!\r\n",
(FLASH_SPIC_PARA_BASE+flash_offset), spci_para);
}
}