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This commit is contained in:
pvvx 2017-02-26 03:15:02 +03:00
parent 5615d7ab9c
commit e851661fa4
71 changed files with 2326 additions and 11244 deletions
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62
project/inc/platform_autoconf.h
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@ -1,8 +1,10 @@
/*
* Automatically generated by make menuconfig: don't edit
*
*/
#define AUTOCONF_INCLUDED
#define RTL8710AF
//#define RTL8711AM
/*
* Target Platform Selection
*/
@ -13,7 +15,6 @@
#undef CONFIG_FPGA
#undef CONFIG_RTL_SIM
#undef CONFIG_POST_SIM
/*
* < Mass Production Option
*/
@ -21,13 +22,15 @@
#undef CONFIG_CP
#undef CONFIG_FT
#define RTL8195A 1
#define CONFIG_CPU_CLK 1
#define CONFIG_CPU_166_6MHZ 1 // RUN/IDLE/SLP ~63/21/6.4 mA
//#define CONFIG_CPU_83_3MHZ 1 // RUN/IDLE/SLP ~55/15/6.4 mA
//#define CONFIG_CPU_41_6MHZ 1 // RUN/IDLE ~51/11 mA
//#define CONFIG_CPU_20_8MHZ 1 // RUN/IDLE ~49/9.5 mA
//#define CONFIG_CPU_10_4MHZ 1
//#define CONFIG_CPU_4MHZ 1 // IDLE ~8 mA
/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
#define CONFIG_CPU_CLK 0
//166.6MHZ - RUN/IDLE/SLP ~63/21/6.4 mA
//83.3MHZ - RUN/IDLE/SLP ~55/15/6.4 mA
//41.6MHZ - RUN/IDLE ~51/11 mA
//20.8MHZ - RUN/IDLE ~49/9.5 mA
//4MHZ - IDLE ~8 mA
#undef CONFIG_FPGA_CLK
#define CONFIG_SDR_CLK 1
#define CONFIG_SDR_100MHZ 1
#undef CONFIG_SDR_50MHZ
@ -78,7 +81,7 @@
#else
#undef CONFIG_SDIO_DEVICE_EN
#endif
//#define CONFIG_SDIO_HOST_EN 1
#define CONFIG_SDIO_HOST_EN 1
//#define CONFIG_USB_EN 1
#undef CONFIG_USB_NORMAL
#define CONFIG_USB_TEST 1
@ -124,6 +127,7 @@
#define CONFIG_CRYPTO_NORMAL 1
#undef CONFIG_CRYPTO_TEST
#define CONFIG_CRYPTO_MODULE 1
#define CONFIG_CRYPTO_STARTUP 0
#define CONFIG_MII_EN 1
#define CONFIG_PWM_EN 1
#define CONFIG_PWM_NORMAL 1
@ -133,7 +137,9 @@
#define CONFIG_EFUSE_NORMAL 1
#undef CONFIG_EFUSE_TEST
#define CONFIG_EFUSE_MODULE 1
//#define CONFIG_SDR_EN 1
#ifdef RTL8711AM
#define CONFIG_SDR_EN 1
#endif
#define CONFIG_SDR_NORMAL 1
#undef CONFIG_SDR_TEST
#define CONFIG_SDR_MODULE 1
@ -191,7 +197,6 @@
//#undef CONFIG_DEBUG_WARN_MSG
//#undef CONFIG_DEBUG_INFO_MSG
#endif // CONFIG_DEBUG_LOG
/*
* < SDK Option Config
*/
@ -225,26 +230,17 @@
#undef CONFIG_IMAGE_ALL
#define CONFIG_IMAGE_SEPARATE 1
#if defined(CONFIG_CPU_166_6MHZ)
#define CPU_CLOCK_SEL_VALUE 0
#define PLATFORM_CLOCK (166666666) // (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
#elif defined(CONFIG_CPU_83_3MHZ)
#define CPU_CLOCK_SEL_VALUE 1
#define PLATFORM_CLOCK (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
#elif defined(CONFIG_CPU_41_6MHZ)
#define CPU_CLOCK_SEL_VALUE 2
#define PLATFORM_CLOCK (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
#elif defined(CONFIG_CPU_20_8MHZ)
#define CPU_CLOCK_SEL_VALUE 3
#define PLATFORM_CLOCK (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
#elif defined(CONFIG_CPU_10_4MHZ)
#define CPU_CLOCK_SEL_VALUE 4
#define PLATFORM_CLOCK (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
#elif defined(CONFIG_CPU_4MHZ)
#define CPU_CLOCK_SEL_VALUE 5
#define PLATFORM_CLOCK (4000000)
#if CONFIG_CPU_CLK < 6
#define CPU_CLOCK_SEL_DIV5_3 0
#define CPU_CLOCK_SEL_VALUE CONFIG_CPU_CLK
#else
#define CONFIG_CPU_166_6MHZ 1
#define CPU_CLOCK_SEL_VALUE (0)
#define PLATFORM_CLOCK (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
#define CPU_CLOCK_SEL_DIV5_3 1
#define CPU_CLOCK_SEL_VALUE (CONFIG_CPU_CLK-6)
#endif
#if CPU__CLK_DIV5_3
#define PLATFORM_CLOCK (200000000ul>>CPU_CLOCK_SEL_VALUE)
#else
#define PLATFORM_CLOCK (((200000000ul*5ul)/3ul)>>CPU_CLOCK_SEL_VALUE)
#endif