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https://github.com/pvvx/RTL00MP3.git
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Update
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pvvx
parent
5615d7ab9c
commit
e851661fa4
71 changed files with 2326 additions and 11244 deletions
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@ -1,8 +1,10 @@
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/*
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* Automatically generated by make menuconfig: don't edit
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*
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*/
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#define AUTOCONF_INCLUDED
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#define RTL8710AF
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//#define RTL8711AM
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/*
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* Target Platform Selection
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*/
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@ -13,7 +15,6 @@
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#undef CONFIG_FPGA
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#undef CONFIG_RTL_SIM
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#undef CONFIG_POST_SIM
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/*
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* < Mass Production Option
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*/
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@ -21,13 +22,15 @@
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#undef CONFIG_CP
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#undef CONFIG_FT
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#define RTL8195A 1
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#define CONFIG_CPU_CLK 1
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#define CONFIG_CPU_166_6MHZ 1 // RUN/IDLE/SLP ~63/21/6.4 mA
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//#define CONFIG_CPU_83_3MHZ 1 // RUN/IDLE/SLP ~55/15/6.4 mA
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//#define CONFIG_CPU_41_6MHZ 1 // RUN/IDLE ~51/11 mA
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//#define CONFIG_CPU_20_8MHZ 1 // RUN/IDLE ~49/9.5 mA
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//#define CONFIG_CPU_10_4MHZ 1
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//#define CONFIG_CPU_4MHZ 1 // IDLE ~8 mA
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/* 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000? Hz,
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6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000? Hz */
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#define CONFIG_CPU_CLK 0
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//166.6MHZ - RUN/IDLE/SLP ~63/21/6.4 mA
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//83.3MHZ - RUN/IDLE/SLP ~55/15/6.4 mA
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//41.6MHZ - RUN/IDLE ~51/11 mA
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//20.8MHZ - RUN/IDLE ~49/9.5 mA
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//4MHZ - IDLE ~8 mA
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#undef CONFIG_FPGA_CLK
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#define CONFIG_SDR_CLK 1
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#define CONFIG_SDR_100MHZ 1
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#undef CONFIG_SDR_50MHZ
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@ -78,7 +81,7 @@
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#else
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#undef CONFIG_SDIO_DEVICE_EN
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#endif
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//#define CONFIG_SDIO_HOST_EN 1
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#define CONFIG_SDIO_HOST_EN 1
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//#define CONFIG_USB_EN 1
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#undef CONFIG_USB_NORMAL
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#define CONFIG_USB_TEST 1
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@ -124,6 +127,7 @@
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#define CONFIG_CRYPTO_NORMAL 1
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#undef CONFIG_CRYPTO_TEST
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#define CONFIG_CRYPTO_MODULE 1
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#define CONFIG_CRYPTO_STARTUP 0
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#define CONFIG_MII_EN 1
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#define CONFIG_PWM_EN 1
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#define CONFIG_PWM_NORMAL 1
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@ -133,7 +137,9 @@
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#define CONFIG_EFUSE_NORMAL 1
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#undef CONFIG_EFUSE_TEST
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#define CONFIG_EFUSE_MODULE 1
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//#define CONFIG_SDR_EN 1
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#ifdef RTL8711AM
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#define CONFIG_SDR_EN 1
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#endif
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#define CONFIG_SDR_NORMAL 1
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#undef CONFIG_SDR_TEST
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#define CONFIG_SDR_MODULE 1
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@ -191,7 +197,6 @@
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//#undef CONFIG_DEBUG_WARN_MSG
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//#undef CONFIG_DEBUG_INFO_MSG
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#endif // CONFIG_DEBUG_LOG
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/*
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* < SDK Option Config
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*/
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@ -225,26 +230,17 @@
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#undef CONFIG_IMAGE_ALL
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#define CONFIG_IMAGE_SEPARATE 1
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#if defined(CONFIG_CPU_166_6MHZ)
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#define CPU_CLOCK_SEL_VALUE 0
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#define PLATFORM_CLOCK (166666666) // (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
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#elif defined(CONFIG_CPU_83_3MHZ)
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#define CPU_CLOCK_SEL_VALUE 1
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#define PLATFORM_CLOCK (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
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#elif defined(CONFIG_CPU_41_6MHZ)
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#define CPU_CLOCK_SEL_VALUE 2
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#define PLATFORM_CLOCK (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
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#elif defined(CONFIG_CPU_20_8MHZ)
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#define CPU_CLOCK_SEL_VALUE 3
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#define PLATFORM_CLOCK (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
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#elif defined(CONFIG_CPU_10_4MHZ)
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#define CPU_CLOCK_SEL_VALUE 4
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#define PLATFORM_CLOCK (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
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#elif defined(CONFIG_CPU_4MHZ)
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#define CPU_CLOCK_SEL_VALUE 5
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#define PLATFORM_CLOCK (4000000)
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#if CONFIG_CPU_CLK < 6
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#define CPU_CLOCK_SEL_DIV5_3 0
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#define CPU_CLOCK_SEL_VALUE CONFIG_CPU_CLK
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#else
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#define CONFIG_CPU_166_6MHZ 1
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#define CPU_CLOCK_SEL_VALUE (0)
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#define PLATFORM_CLOCK (((200000000*5)/3)>>(CPU_CLOCK_SEL_VALUE + 1))
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#define CPU_CLOCK_SEL_DIV5_3 1
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#define CPU_CLOCK_SEL_VALUE (CONFIG_CPU_CLK-6)
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#endif
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#if CPU__CLK_DIV5_3
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#define PLATFORM_CLOCK (200000000ul>>CPU_CLOCK_SEL_VALUE)
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#else
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#define PLATFORM_CLOCK (((200000000ul*5ul)/3ul)>>CPU_CLOCK_SEL_VALUE)
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#endif
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@ -121,7 +121,7 @@ static enum mad_flow input(struct mad_stream *stream) {
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// We both silence the output as well as wait a while by pushing silent samples into the i2s system.
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// This waits for about 200mS
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#if DEBUG_MAIN_LEVEL > 1
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DBG_8195A("FIFO: Buffer Underrun\n");
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// DBG_8195A("FIFO: Buffer Underrun\n");
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#endif
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for (n = 0; n < 441*2; n++) sampToOut(0);
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} else {
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@ -491,33 +491,39 @@ void connect_start(void) {
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*/
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void main(void) {
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#if DEBUG_MAIN_LEVEL > 2
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#if DEBUG_MAIN_LEVEL > 3
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ConfigDebugErr = -1;
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ConfigDebugInfo = -1;
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ConfigDebugInfo = -1; //~_DBG_SPI_FLASH_;
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ConfigDebugWarn = -1;
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CfgSysDebugErr = -1;
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CfgSysDebugInfo = -1;
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CfgSysDebugWarn = -1;
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#endif
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/*
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if ( rtl_cryptoEngine_init() != 0 ) DBG_8195A("crypto engine init failed\r\n");
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*/
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#if defined(CONFIG_CPU_CLK)
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#if 1 // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
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HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) & (~(1<<17)));
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HalCpuClkConfig(CPU_CLOCK_SEL_VALUE); // 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
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#else // 0 - 200000000 Hz, 1 - 10000000 Hz, 2 - 50000000 Hz, 3 - 25000000 Hz, 4 - 12500000 Hz, 5 - 4000000 Hz
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HalCpuClkConfig(1);
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HAL_SYS_CTRL_WRITE32(REG_SYS_SYSPLL_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_SYSPLL_CTRL1) | (1<<17));
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if(HalGetCpuClk() != PLATFORM_CLOCK) {
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#if CPU_CLOCK_SEL_DIV5_3
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// 6 - 200000000 Hz, 7 - 10000000 Hz, 8 - 50000000 Hz, 9 - 25000000 Hz, 10 - 12500000 Hz, 11 - 4000000 Hz
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HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
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*((int *)0x40000074) |= (1<<17); // REG_SYS_SYSPLL_CTRL1 |= BIT_SYS_SYSPLL_DIV5_3
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#else
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// 0 - 166666666 Hz, 1 - 83333333 Hz, 2 - 41666666 Hz, 3 - 20833333 Hz, 4 - 10416666 Hz, 5 - 4000000 Hz
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*((int *)0x40000074) &= ~(1<<17); // REG_SYS_SYSPLL_CTRL1 &= ~BIT_SYS_SYSPLL_DIV5_3
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HalCpuClkConfig(CPU_CLOCK_SEL_VALUE);
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#endif
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HAL_LOG_UART_ADAPTER pUartAdapter;
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pUartAdapter.BaudRate = RUART_BAUD_RATE_38400;
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pUartAdapter.BaudRate = UART_BAUD_RATE_38400;
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HalLogUartSetBaudRate(&pUartAdapter);
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SystemCoreClockUpdate();
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En32KCalibration();
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}
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#if defined(CONFIG_CRYPTO_STARTUP) && (CONFIG_CRYPTO_STARTUP)
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if ( rtl_cryptoEngine_init() != 0 ) {
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DBG_8195A("crypto engine init failed\r\n");
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}
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#endif
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#if DEBUG_MAIN_LEVEL > 1
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DBG_INFO_MSG_ON(_DBG_TCM_HEAP_); // On Debug TCM MEM
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#endif
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#if DEBUG_MAIN_LEVEL > 0
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vPortFree(pvPortMalloc(4)); // Init RAM heap
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vPortFree(pvPortMalloc(4)); // Init RAM heap
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fATST(NULL); // RAM/TCM/Heaps info
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#endif
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/* pre-processor of application example */
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