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update

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This commit is contained in:
pvvx 2017-02-18 07:46:36 +03:00
parent 4d4f8c1b29
commit e423a86f64
12 changed files with 38 additions and 22 deletions
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2
RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt
View file

@ -764,7 +764,7 @@ SECTIONS
gRamPatchFun2 = 0x10000bd8; /* HalResetVsrV02(), HalResetVsr() */
__image1_validate_code__ = 0x10000bdc; /* 8 bytes HalResetVsrV02(), HalResetVsr() */
RAM_IMG1_VALID_PATTEN = 0x10000bdc;
_RandSeed = 0x10000be4; /* ChangeRandSeed_rom().. Sdr_Rand2_rom() */
rand_x = 0x10000be4; /* ChangeRandSeed_rom().. Sdr_Rand2_rom() */
AvaWds = 0x10000be8; /* SdrCalibration_rom() */
SdrDramInfo = 0x10001be8; /* SdrCalibration_rom() */
SdrDramTiming = 0x10001bfc; /* SdrCalibration_rom() */

27
RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v04-img2.ld
View file

@ -9,11 +9,11 @@ MEMORY
{
ROM_USED_RAM (rwx): ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
ROM_HEAP (rwx) : ORIGIN = 0x10002400, LENGTH = 3K /* end 0x10003000 */
RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12k /* end 0x10006000 */
RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12K /* end 0x10006000 */
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 424K /* end 0x10070000 */
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
TCM_TAB (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 0 /*2M end 0x30200000 */
TCM_TAB (rwx) : ORIGIN = 0x1FFFFD00, LENGTH = 768 /* end 0x20000000 */
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M /* end 0x30200000 */
}
EXTERN(RAM_IMG2_VALID_PATTEN)
@ -21,6 +21,7 @@ EXTERN(main)
EXTERN(InfraStart)
EXTERN(gImage2EntryFun0)
SECTIONS
{
__rom_bss_start__ = 0x10000300;
@ -51,7 +52,8 @@ SECTIONS
{
__ram_tcm_start__ = .;
*mem.o (.bss*)
*memp.o (.bss*)
*memp.o (.bss*)
__tcm_heap_start__ = .;
*(.tcm.heap)
}
.dummy
@ -78,6 +80,11 @@ SECTIONS
}
} > TCM
.soc_ps_monitor :
{
__tcm_heap_end__ = .;
} > TCM_TAB
.image2.start.table :
{
__ram_heap1_end__ = .;
@ -116,11 +123,11 @@ SECTIONS
. = ALIGN(4);
xHeapRegions = .;
LONG(__ram_heap1_start__)
LONG(ORIGIN(RAM_HEAP1) + LENGTH(RAM_HEAP1) - __ram_heap1_start__)
LONG(__ram_heap1_end__ - __ram_heap1_start__)
LONG(__ram_heap2_start__)
LONG(ORIGIN(BD_RAM) + LENGTH(BD_RAM) - __ram_heap2_start__)
LONG(__ram_heap2_end__ - __ram_heap2_start__)
LONG(__sdram_heap_start__)
LONG(ORIGIN(SDRAM_RAM) + LENGTH(SDRAM_RAM) - __sdram_heap_start__)
LONG(__sdram_heap_end__ - __sdram_heap_start__)
LONG(0)
LONG(0)
} > BD_RAM
@ -148,20 +155,23 @@ SECTIONS
*(.bss*)
*(COMMON)
*(.bdsram.data*)
*(.bfsram.data*)
*(.sdram.bss*)
*(.p2p.bss*)
*(.wps.bss*)
*(.websocket.bss*)
__bss_end__ = .;
.ram.bss$$Limit = .;
} > BD_RAM
.ram_heap2 :
{
. = ALIGN(8);
__ram_heap2_start__ = .;
KEEP(*(.bfsram.data*)) /* ucHeap */
KEEP(*(.heap*)) /* ucHeap */
} > BD_RAM
__ram_heap2_end__ = 0x10070000;
.sdr_text :
{
@ -184,6 +194,7 @@ SECTIONS
. = ALIGN(8);
__sdram_heap_start__ = .;
} > SDRAM_RAM
__sdram_heap_end__ = 0x30200000;
.boot.head :
{

7
RTL00_SDKV35a/component/soc/realtek/common/bsp/section_config.h
View file

@ -210,7 +210,7 @@
#define SDIO_ROM_BSS_SECTION \
SECTION(".sdio.rom.bss")
#define SDIO_ROM_TEXT_SECTION \
SECTION(".sdio.rom.text")
SECTION(".sdio.rom.text")
//3 SRAM Config Section
#define SRAM_BD_DATA_SECTION \
@ -219,6 +219,9 @@
#define SRAM_BF_DATA_SECTION \
SECTION(".bfsram.data")
#define SRAM_HEAP_SECTION \
SECTION(".sram.heap")
#define START_RAM_FUN_SECTION \
SECTION(".start.ram.data")
@ -277,7 +280,7 @@
#define IMAGE2_START_RAM_FUN_SECTION \
SECTION(".image2.ram.data")
SECTION(".image2.ram.data")
#define SDRAM_DATA_SECTION \
SECTION(".sdram.data")