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boot v0.1

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pvvx 2017-03-16 05:01:44 +03:00
parent d8c84cd5fe
commit d9bd706408
24 changed files with 2734 additions and 2568 deletions
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6
RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt
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@ -305,8 +305,8 @@ SECTIONS
HalTimerIrq2To7Handle = 0xee59;
HalGetTimerIdRtl8195a = 0xef09;
HalTimerInitRtl8195a = 0xef3d;
HalTimerDisRtl8195a = 0xf069;
HalTimerEnRtl8195a = 0xf089;
HalTimerDisRtl8195a = 0xf069; /* error! */
HalTimerEnRtl8195a = 0xf089; /* error! */
HalTimerReadCountRtl8195a = 0xf0a9;
HalTimerIrqClearRtl8195a = 0xf0bd;
HalTimerDumpRegRtl8195a = 0xf0d1;
@ -624,7 +624,7 @@ SECTIONS
rom_wps_rcons = 0x35d88;
rom_wps_Td4s = 0x35d94;
rom_wps_Td0 = 0x35e94;
str_rom_57ch3Dch0A = 0x3ed05;
str_rom_57ch3Dch0A = 0x3ed05; /* "========================================================\n" */
str_rom_0123456789ABCDEF = 0x3ec24; /* "0123456789ABCDEF" */
str_rom_hex_addr = 0x442D6; /* "[Addr] .0 .1 .2 .3 .4 .5 .6 .7 .8 .9 .A .B .C .D .E .F\r\n" */
str_rom_0123456789abcdef = 0x44660; /* "0123456789abcdef" */

2
RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/include/rtl_bios_data.h
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@ -208,7 +208,7 @@ extern DRAM_MODE_REG_INFO SdrDramModeReg; // 10001c30
0 } /* Mode2Cwl */
extern DRAM_INFO SdrDramDev; // 10001c4c
#define DRAM_INFO_INIT() { DRAM_INFO_TYPE, DRAM_INFO_COL_ADDR_WTH,DRAM_INFO_BANK_SZ, DRAM_INFO_DQ_WTH }
//extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // SpicInitParaAllClk[3][6] !
extern SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // 100021ec [144=0x90]
/* ROM + "C" standard library */
extern struct _reent * _rtl_impure_ptr; // 10001c60 = { &impure_reent };