first commit

This commit is contained in:
pvvx 2016-11-09 03:56:41 +03:00
parent 2ee525362e
commit d108756e9b
792 changed files with 336059 additions and 0 deletions

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@ -0,0 +1,738 @@
SECTIONS
{
__vectors_table = 0x0;
Reset_Handler = 0x101;
NMI_Handler = 0x109;
HardFault_Handler = 0x10d;
MemManage_Handler = 0x121;
BusFault_Handler = 0x125;
UsageFault_Handler = 0x129;
HalLogUartInit = 0x201;
HalSerialPutcRtl8195a = 0x2d9;
HalSerialGetcRtl8195a = 0x309;
HalSerialGetIsrEnRegRtl8195a = 0x329;
HalSerialSetIrqEnRegRtl8195a = 0x335;
HalCpuClkConfig = 0x341;
HalGetCpuClk = 0x355;
HalRomInfo = 0x39d;
HalGetRomInfo = 0x3b5;
HalResetVsr = 0x3c5;
HalDelayUs = 0x899;
HalNMIHandler = 0x8e1;
HalHardFaultHandler = 0x911;
HalMemManageHandler = 0xc09;
HalBusFaultHandler = 0xc39;
HalUsageFaultHandler = 0xc69;
HalUart0PinCtrlRtl8195A = 0xcfd;
HalUart1PinCtrlRtl8195A = 0xdc9;
HalUart2PinCtrlRtl8195A = 0xe9d;
HalSPI0PinCtrlRtl8195A = 0xf75;
HalSPI1PinCtrlRtl8195A = 0x1015;
HalSPI2PinCtrlRtl8195A = 0x10e5;
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
HalI2C0PinCtrlRtl8195A = 0x1275;
HalI2C1PinCtrlRtl8195A = 0x1381;
HalI2C2PinCtrlRtl8195A = 0x1459;
HalI2C3PinCtrlRtl8195A = 0x1529;
HalI2S0PinCtrlRtl8195A = 0x1639;
HalI2S1PinCtrlRtl8195A = 0x176d;
HalPCM0PinCtrlRtl8195A = 0x1845;
HalPCM1PinCtrlRtl8195A = 0x1949;
HalSDIODPinCtrlRtl8195A = 0x1a1d;
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
HalMIIPinCtrlRtl8195A = 0x1ab9;
HalWLLEDPinCtrlRtl8195A = 0x1b51;
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
HalWLANT1PinCtrlRtl8195A = 0x1c61;
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
HalNFCPinCtrlRtl8195A = 0x1d59;
HalPWM0PinCtrlRtl8195A = 0x1da9;
HalPWM1PinCtrlRtl8195A = 0x1ead;
HalPWM2PinCtrlRtl8195A = 0x1fb5;
HalPWM3PinCtrlRtl8195A = 0x20b1;
HalETE0PinCtrlRtl8195A = 0x21b9;
HalETE1PinCtrlRtl8195A = 0x22c1;
HalETE2PinCtrlRtl8195A = 0x23c9;
HalETE3PinCtrlRtl8195A = 0x24d1;
HalEGTIMPinCtrlRtl8195A = 0x25d9;
HalSPIFlashPinCtrlRtl8195A = 0x2679;
HalSDRPinCtrlRtl8195A = 0x2725;
HalJTAGPinCtrlRtl8195A = 0x280d;
HalTRACEPinCtrlRtl8195A = 0x2861;
HalLOGUartPinCtrlRtl8195A = 0x28b9;
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
HalSICPinCtrlRtl8195A = 0x2981;
HalEEPROMPinCtrlRtl8195A = 0x29d9;
HalDEBUGPinCtrlRtl8195A = 0x2a31;
HalPinCtrlRtl8195A = 0x2b39;
SpicRxCmdRtl8195A = 0x2e5d;
SpicWaitBusyDoneRtl8195A = 0x2ea5;
SpicGetFlashStatusRtl8195A = 0x2eb5;
SpicWaitWipDoneRtl8195A = 0x2f55;
SpicTxCmdRtl8195A = 0x2f6d;
SpicSetFlashStatusRtl8195A = 0x2fc1;
SpicCmpDataForCalibrationRtl8195A = 0x3049;
SpicLoadInitParaFromClockRtl8195A = 0x3081;
SpicInitRtl8195A = 0x30e5;
SpicEraseFlashRtl8195A = 0x31bd;
SpiFlashApp = 0x3279;
HalPeripheralIntrHandle = 0x33b5;
HalSysOnIntrHandle = 0x3439;
HalWdgIntrHandle = 0x3485;
HalTimer0IntrHandle = 0x34d5;
HalTimer1IntrHandle = 0x3525;
HalI2C3IntrHandle = 0x3575;
HalTimer2To7IntrHandle = 0x35c5;
HalSpi0IntrHandle = 0x3615;
HalGpioIntrHandle = 0x3665;
HalUart0IntrHandle = 0x36b5;
HalSpiFlashIntrHandle = 0x3705;
HalUsbOtgIntrHandle = 0x3755;
HalSdioHostIntrHandle = 0x37a5;
HalI2s0OrPcm0IntrHandle = 0x37f5;
HalI2s1OrPcm1IntrHandle = 0x3845;
HalWlDmaIntrHandle = 0x3895;
HalWlProtocolIntrHandle = 0x38e5;
HalCryptoIntrHandle = 0x3935;
HalGmacIntrHandle = 0x3985;
HalGdma0Ch0IntrHandle = 0x39d5;
HalGdma0Ch1IntrHandle = 0x3a25;
HalGdma0Ch2IntrHandle = 0x3a75;
HalGdma0Ch3IntrHandle = 0x3ac5;
HalGdma0Ch4IntrHandle = 0x3b15;
HalGdma0Ch5IntrHandle = 0x3b65;
HalGdma1Ch0IntrHandle = 0x3bb5;
HalGdma1Ch1IntrHandle = 0x3c05;
HalGdma1Ch2IntrHandle = 0x3c55;
HalGdma1Ch3IntrHandle = 0x3ca5;
HalGdma1Ch4IntrHandle = 0x3cf5;
HalGdma1Ch5IntrHandle = 0x3d45;
HalSdioDeviceIntrHandle = 0x3d95;
VectorTableInitRtl8195A = 0x3de5;
VectorTableInitForOSRtl8195A = 0x4019;
VectorIrqRegisterRtl8195A = 0x4029;
VectorIrqUnRegisterRtl8195A = 0x4091;
VectorIrqEnRtl8195A = 0x40f1;
VectorIrqDisRtl8195A = 0x418d;
_UartRxDmaIrqHandle = 0x422d;
HalRuartPutCRtl8195a = 0x4281;
HalRuartGetCRtl8195a = 0x429d;
HalRuartRTSCtrlRtl8195a = 0x42bd;
HalRuartGetDebugValueRtl8195a = 0x42e1;
HalRuartGetIMRRtl8195a = 0x43e1;
HalRuartSetIMRRtl8195a = 0x442d;
_UartIrqHandle = 0x4465;
HalRuartDmaInitRtl8195a = 0x4681;
HalRuartIntDisableRtl8195a = 0x4845;
HalRuartDeInitRtl8195a = 0x4855;
HalRuartIntEnableRtl8195a = 0x4985;
_UartTxDmaIrqHandle = 0x4995;
HalRuartRegIrqRtl8195a = 0x49d1;
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
RuartLock = 0x4cc9;
RuartUnLock = 0x4ced;
HalRuartIntSendRtl8195a = 0x4d09;
HalRuartDmaSendRtl8195a = 0x4e35;
HalRuartStopSendRtl8195a = 0x4f89;
HalRuartIntRecvRtl8195a = 0x504d;
HalRuartDmaRecvRtl8195a = 0x51ad;
HalRuartStopRecvRtl8195a = 0x52cd;
RuartIsTimeout = 0x5385;
HalRuartSendRtl8195a = 0x53b1;
HalRuartRecvRtl8195a = 0x5599;
RuartResetRxFifoRtl8195a = 0x5751;
HalRuartResetRxFifoRtl8195a = 0x5775;
HalRuartInitRtl8195a = 0x5829;
HalGdmaOnOffRtl8195a = 0x5df1;
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
HalGdmaChEnRtl8195a = 0x5e51;
HalGdmaChDisRtl8195a = 0x5e6d;
HalGdamChInitRtl8195a = 0x5e91;
HalGdmaChSetingRtl8195a = 0x5ebd;
HalGdmaChBlockSetingRtl8195a = 0x000060dd;
HalGdmaChIsrCleanRtl8195a = 0x6419;
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
HalEFUSEPowerSwitch8195AROM = 0x6561;
HALEFUSEOneByteReadROM = 0x65f9;
HALEFUSEOneByteWriteROM = 0x6699;
__rtl_memcmpb_v1_00 = 0x681d;
__rtl_random_v1_00 = 0x6861;
__rtl_align_to_be32_v1_00 = 0x6881;
__rtl_memsetw_v1_00 = 0x6899;
__rtl_memsetb_v1_00 = 0x68ad;
__rtl_memcpyw_v1_00 = 0x68bd;
__rtl_memcpyb_v1_00 = 0x68dd;
__rtl_memDump_v1_00 = 0x68f5;
__rtl_AES_set_encrypt_key = 0x6901;
__rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
__rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
__rtl_cryptoEngine_init_v1_00 = 0x6ea9;
__rtl_cryptoEngine_exit_v1_00 = 0x7055;
__rtl_cryptoEngine_reset_v1_00 = 0x70b1;
__rtl_cryptoEngine_v1_00 = 0x70ed;
__rtl_crypto_cipher_init_v1_00 = 0x7c69;
__rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
__rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
HalSsiEnableRtl8195a = 0x7e45;
HalSsiDisableRtl8195a = 0x7ef9;
HalSsiLoadSettingRtl8195a = 0x7fad;
HalSsiSetInterruptMaskRtl8195a = 0x8521;
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
HalSsiSetSclkPolarityRtl8195a = 0x863d;
HalSsiSetSclkPhaseRtl8195a = 0x8715;
HalSsiWriteRtl8195a = 0x87e9;
HalSsiSetDeviceRoleRtl8195a = 0x8861;
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
HalSsiReadRtl8195a = 0x89b9;
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
HalSsiGetStatusRtl8195a = 0x8b1d;
HalSsiWriteableRtl8195a = 0x8b91;
HalSsiReadableRtl8195a = 0x8c09;
HalSsiBusyRtl8195a = 0x8c81;
HalSsiReadInterruptRtl8195a = 0x8cf9;
HalSsiWriteInterruptRtl8195a = 0x8efd;
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
HalSsiInterruptEnableRtl8195a = 0x914d;
HalSsiInterruptDisableRtl8195a = 0x9299;
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
HalSsiInitRtl8195a = 0x94d1;
_SsiReadInterrupt = 0x9ba5;
_SsiWriteInterrupt = 0x9db1;
_SsiIrqHandle = 0x9eb1;
HalI2CWrite32 = 0xa061;
HalI2CRead32 = 0xa09d;
HalI2CDeInit8195a = 0xa0dd;
HalI2CSendRtl8195a = 0xa1f1;
HalI2CReceiveRtl8195a = 0xa25d;
HalI2CEnableRtl8195a = 0xa271;
HalI2CIntrCtrl8195a = 0xa389;
HalI2CReadRegRtl8195a = 0xa3a1;
HalI2CWriteRegRtl8195a = 0xa3b1;
HalI2CSetCLKRtl8195a = 0xa3c5;
HalI2CMassSendRtl8195a = 0xa6e9;
HalI2CClrIntrRtl8195a = 0xa749;
HalI2CClrAllIntrRtl8195a = 0xa761;
HalI2CInit8195a = 0xa775;
HalI2CDMACtrl8195a = 0xaa31;
RtkI2CIoCtrl = 0xaa61;
RtkI2CPowerCtrl = 0xaa65;
HalI2COpInit = 0xaa69;
I2CIsTimeout = 0xac65;
I2CTXGDMAISRHandle = 0xb435;
I2CRXGDMAISRHandle = 0xb4c1;
RtkI2CIrqInit = 0xb54d;
RtkI2CIrqDeInit = 0xb611;
RtkI2CPinMuxInit = 0xb675;
RtkI2CPinMuxDeInit = 0xb7c9;
RtkI2CDMAInit = 0xb955;
RtkI2CInit = 0xbc95;
RtkI2CDMADeInit = 0xbdad;
RtkI2CDeInit = 0xbe4d;
RtkI2CSendUserAddr = 0xbee5;
RtkI2CSend = 0xc07d;
RtkI2CLoadDefault = 0xce51;
RtkSalI2COpInit = 0xcf21;
HalI2SWrite32 = 0xcf65;
HalI2SRead32 = 0xcf85;
HalI2SDeInitRtl8195a = 0xcfa9;
HalI2STxRtl8195a = 0xcfc9;
HalI2SRxRtl8195a = 0xd011;
HalI2SEnableRtl8195a = 0xd05d;
HalI2SIntrCtrlRtl8195a = 0xd0b1;
HalI2SReadRegRtl8195a = 0xd0d1;
HalI2SClrIntrRtl8195a = 0xd0dd;
HalI2SClrAllIntrRtl8195a = 0xd0fd;
HalI2SInitRtl8195a = 0xd11d;
GPIO_GetIPPinName_8195a = 0xd2e5;
GPIO_GetChipPinName_8195a = 0xd331;
GPIO_PullCtrl_8195a = 0xd39d;
GPIO_FuncOn_8195a = 0xd421;
GPIO_FuncOff_8195a = 0xd481;
GPIO_Int_Mask_8195a = 0xd4e9;
GPIO_Int_SetType_8195a = 0xd511;
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
HAL_GPIO_Init_8195a = 0xd805;
HAL_GPIO_DeInit_8195a = 0xdac1;
HAL_GPIO_ReadPin_8195a = 0xdbd1;
HAL_GPIO_WritePin_8195a = 0xdc91;
HAL_GPIO_RegIrq_8195a = 0xddad;
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
HAL_GPIO_UserRegIrq_8195a = 0xde15;
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
HAL_GPIO_IntDebounce_8195a = 0xe101;
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
DumpForOneBytes = 0xe259;
CmdRomHelp = 0xe419;
CmdWriteWord = 0xe491;
CmdDumpHelfWord = 0xe505;
CmdDumpWord = 0xe5f1;
CmdDumpByte = 0xe6f5;
CmdSpiFlashTool = 0xe751;
GetRomCmdNum = 0xe7a9;
CmdWriteByte = 0xe7ad;
Isspace = 0xe7ed;
Strtoul = 0xe801;
ArrayInitialize = 0xe8b1;
GetArgc = 0xe8c9;
GetArgv = 0xe8f9;
UartLogCmdExecute = 0xe95d;
UartLogShowBackSpace = 0xe9fd;
UartLogRecallOldCmd = 0xea39;
UartLogHistoryCmd = 0xea71;
UartLogCmdChk = 0xeadd;
UartLogIrqHandle = 0xebf5;
RtlConsolInit = 0xecc5;
RtlConsolTaskRom = 0xed49;
RtlExitConsol = 0xed79;
RtlConsolRom = 0xedcd;
HalTimerOpInit = 0xee0d;
HalTimerIrq2To7Handle = 0xee59;
HalGetTimerIdRtl8195a = 0xef09;
HalTimerInitRtl8195a = 0xef3d;
HalTimerDisRtl8195a = 0xf069;
HalTimerEnRtl8195a = 0xf089;
HalTimerReadCountRtl8195a = 0xf0a9;
HalTimerIrqClearRtl8195a = 0xf0bd;
HalTimerDumpRegRtl8195a = 0xf0d1;
VSprintf = 0xf129;
DiagPrintf = 0xf39d;
DiagSPrintf = 0xf3b9;
DiagSnPrintf = 0xf3d1;
prvDiagPrintf = 0xf3ed;
prvDiagSPrintf = 0xf40d;
_memcmp = 0xf429;
_memcpy = 0xf465;
_memset = 0xf511;
Rand = 0xf585;
_strncpy = 0xf60d;
_strcpy = 0xf629;
prvStrCpy = 0xf639;
_strlen = 0xf651;
_strnlen = 0xf669;
prvStrLen = 0xf699;
_strcmp = 0xf6b1;
_strncmp = 0xf6d1;
prvStrCmp = 0xf719;
StrUpr = 0xf749;
prvAtoi = 0xf769;
prvStrStr = 0xf7bd;
_strsep = 0xf7d5;
skip_spaces = 0xf815;
skip_atoi = 0xf831;
_parse_integer_fixup_radix = 0xf869;
_parse_integer = 0xf8bd;
simple_strtoull = 0xf915;
simple_strtoll = 0xf945;
simple_strtoul = 0xf965;
simple_strtol = 0xf96d;
_vsscanf = 0xf985;
_sscanf = 0xff71;
div_u64 = 0xff91;
div_s64 = 0xff99;
div_u64_rem = 0xffa1;
div_s64_rem = 0xffb1;
_strpbrk = 0xffc1;
_strchr = 0xffed;
aes_set_key = 0x10005;
aes_encrypt = 0x103d1;
aes_decrypt = 0x114a5;
AES_WRAP = 0x125c9;
AES_UnWRAP = 0x12701;
crc32_get = 0x12861;
arc4_byte = 0x12895;
rt_arc4_init = 0x128bd;
rt_arc4_crypt = 0x12901;
rt_md5_init = 0x131c1;
rt_md5_append = 0x131f5;
rt_md5_final = 0x1327d;
rt_md5_hmac = 0x132d5;
rtw_get_bit_value_from_ieee_value = 0x13449;
rtw_is_cckrates_included = 0x13475;
rtw_is_cckratesonly_included = 0x134b5;
rtw_check_network_type = 0x134dd;
rtw_set_fixed_ie = 0x1350d;
rtw_set_ie = 0x1352d;
rtw_get_ie = 0x1355d;
rtw_set_supported_rate = 0x13591;
rtw_get_rateset_len = 0x13611;
rtw_get_wpa_ie = 0x1362d;
rtw_get_wpa2_ie = 0x136c9;
rtw_get_wpa_cipher_suite = 0x13701;
rtw_get_wpa2_cipher_suite = 0x13769;
rtw_parse_wpa_ie = 0x137d1;
rtw_parse_wpa2_ie = 0x138ad;
rtw_get_sec_ie = 0x13965;
rtw_get_wps_ie = 0x13a15;
rtw_get_wps_attr = 0x13a99;
rtw_get_wps_attr_content = 0x13b49;
rtw_ieee802_11_parse_elems = 0x13b91;
str_2char2num = 0x13d9d;
key_2char2num = 0x13db9;
convert_ip_addr = 0x13dd1;
rom_psk_PasswordHash = 0x13e9d;
rom_psk_CalcGTK = 0x13ed5;
rom_psk_CalcPTK = 0x13f69;
wep_80211_encrypt = 0x14295;
wep_80211_decrypt = 0x142f5;
tkip_micappendbyte = 0x14389;
rtw_secmicsetkey = 0x143d9;
rtw_secmicappend = 0x14419;
rtw_secgetmic = 0x14435;
rtw_seccalctkipmic = 0x1449d;
tkip_phase1 = 0x145a5;
tkip_phase2 = 0x14725;
tkip_80211_encrypt = 0x14941;
tkip_80211_decrypt = 0x149d5;
aes1_encrypt = 0x14a8d;
aesccmp_construct_mic_iv = 0x14c65;
aesccmp_construct_mic_header1 = 0x14ccd;
aesccmp_construct_mic_header2 = 0x14d21;
aesccmp_construct_ctr_preload = 0x14db5;
aes_80211_encrypt = 0x14e29;
aes_80211_decrypt = 0x151ad;
_sha1_process_message_block = 0x155b9;
_sha1_pad_message = 0x15749;
rt_sha1_init = 0x157e5;
rt_sha1_update = 0x15831;
rt_sha1_finish = 0x158a9;
rt_hmac_sha1 = 0x15909;
rom_aes_128_cbc_encrypt = 0x15a65;
rom_aes_128_cbc_decrypt = 0x15ae1;
rom_rijndaelKeySetupEnc = 0x15b5d;
rom_aes_decrypt_init = 0x15c39;
rom_aes_internal_decrypt = 0x15d15;
rom_aes_decrypt_deinit = 0x16071;
rom_aes_encrypt_init = 0x16085;
rom_aes_internal_encrypt = 0x1609d;
rom_aes_encrypt_deinit = 0x16451;
bignum_init = 0x17b35;
bignum_deinit = 0x17b61;
bignum_get_unsigned_bin_len = 0x17b81;
bignum_get_unsigned_bin = 0x17b85;
bignum_set_unsigned_bin = 0x17c21;
bignum_cmp = 0x17cd1;
bignum_cmp_d = 0x17cd5;
bignum_add = 0x17cfd;
bignum_sub = 0x17d0d;
bignum_mul = 0x17d1d;
bignum_exptmod = 0x17d2d;
WPS_realloc = 0x17d51;
os_zalloc = 0x17d99;
rom_hmac_sha256_vector = 0x17dc1;
rom_hmac_sha256 = 0x17ebd;
rom_sha256_vector = 0x18009;
phy_CalculateBitShift = 0x18221;
PHY_SetBBReg_8195A = 0x18239;
PHY_QueryBBReg_8195A = 0x18279;
ROM_odm_QueryRxPwrPercentage = 0x1829d;
ROM_odm_EVMdbToPercentage = 0x182bd;
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
ROM_odm_SetEDCCAThreshold = 0x18721;
ROM_odm_SetTRxMux = 0x18749;
ROM_odm_SetCrystalCap = 0x18771;
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
ROM_ODM_CfoTrackingReset = 0x187e9;
ROM_odm_CfoTrackingFlow = 0x18811;
curve25519_donna = 0x1965d;
aes_test_alignment_detection = 0x1a391;
aes_mode_reset = 0x1a3ed;
aes_ecb_encrypt = 0x1a3f9;
aes_ecb_decrypt = 0x1a431;
aes_cbc_encrypt = 0x1a469;
aes_cbc_decrypt = 0x1a579;
aes_cfb_encrypt = 0x1a701;
aes_cfb_decrypt = 0x1a9e5;
aes_ofb_crypt = 0x1acc9;
aes_ctr_crypt = 0x1af7d;
aes_encrypt_key128 = 0x1b289;
aes_encrypt_key192 = 0x1b2a5;
aes_encrypt_key256 = 0x1b2c1;
aes_encrypt_key = 0x1b2e1;
aes_decrypt_key128 = 0x1b351;
aes_decrypt_key192 = 0x1b36d;
aes_decrypt_key256 = 0x1b389;
aes_decrypt_key = 0x1b3a9;
aes_init = 0x1b419;
CRYPTO_chacha_20 = 0x1b41d;
CRYPTO_poly1305_init = 0x1bc25;
CRYPTO_poly1305_update = 0x1bd09;
CRYPTO_poly1305_finish = 0x1bd8d;
rom_sha512_starts = 0x1ceb5;
rom_sha512_update = 0x1d009;
rom_sha512_finish = 0x1d011;
rom_sha512 = 0x1d261;
rom_sha512_hmac_starts = 0x1d299;
rom_sha512_hmac_update = 0x1d35d;
rom_sha512_hmac_finish = 0x1d365;
rom_sha512_hmac_reset = 0x1d3b5;
rom_sha512_hmac = 0x1d3d1;
rom_sha512_hkdf = 0x1d40d;
rom_ed25519_gen_keypair = 0x1d501;
rom_ed25519_gen_signature = 0x1d505;
rom_ed25519_verify_signature = 0x1d51d;
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
rom_ed25519_crypto_sign_detached = 0x1d579;
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
rom_ed25519_ge_p3_tobytes = 0x207d5;
rom_ed25519_ge_scalarmult_base = 0x20821;
rom_ed25519_ge_tobytes = 0x209e1;
rom_ed25519_sc_muladd = 0x20a2d;
rom_ed25519_sc_reduce = 0x2603d;
__rtl_memchr_v1_00 = 0x28a4d;
__rtl_memcmp_v1_00 = 0x28ae1;
__rtl_memcpy_v1_00 = 0x28b49;
__aeabi_memcpy = 0x28b49;
__aeabi_memcpy4 = 0x28b49;
__rtl_memmove_v1_00 = 0x28bed;
__rtl_memset_v1_00 = 0x28cb5;
__aeabi_memset = 0x28cb5;
__rtl_strcat_v1_00 = 0x28d49;
__rtl_strchr_v1_00 = 0x28d91;
__rtl_strcmp_v1_00 = 0x28e55;
__rtl_strcpy_v1_00 = 0x28ec9;
__rtl_strlen_v1_00 = 0x28f15;
__rtl_strncat_v1_00 = 0x28f69;
__rtl_strncmp_v1_00 = 0x28fc5;
__rtl_strncpy_v1_00 = 0x2907d;
__rtl_strstr_v1_00 = 0x293cd;
__rtl_strsep_v1_00 = 0x2960d;
__rtl_strtok_v1_00 = 0x29619;
__rtl__strtok_r_v1_00 = 0x2962d;
__rtl_strtok_r_v1_00 = 0x29691;
__rtl_close_v1_00 = 0x29699;
__rtl_fstat_v1_00 = 0x296ad;
__rtl_isatty_v1_00 = 0x296c1;
__rtl_lseek_v1_00 = 0x296d5;
__rtl_open_v1_00 = 0x296e9;
__rtl_read_v1_00 = 0x296fd;
__rtl_write_v1_00 = 0x29711;
__rtl_sbrk_v1_00 = 0x29725;
__rtl_ltoa_v1_00 = 0x297bd;
__rtl_ultoa_v1_00 = 0x29855;
__rtl_dtoi_v1_00 = 0x298c5;
__rtl_dtoi64_v1_00 = 0x29945;
__rtl_dtoui_v1_00 = 0x299dd;
__rtl_ftol_v1_00 = 0x299e5;
__rtl_itof_v1_00 = 0x29a51;
__rtl_itod_v1_00 = 0x29ae9;
__rtl_i64tod_v1_00 = 0x29b79;
__rtl_uitod_v1_00 = 0x29c55;
__rtl_ftod_v1_00 = 0x29d2d;
__rtl_dtof_v1_00 = 0x29de9;
__rtl_uitof_v1_00 = 0x29e89;
__rtl_fadd_v1_00 = 0x29f65;
__rtl_fsub_v1_00 = 0x2a261;
__rtl_fmul_v1_00 = 0x2a559;
__rtl_fdiv_v1_00 = 0x2a695;
__rtl_dadd_v1_00 = 0x2a825;
__rtl_dsub_v1_00 = 0x2aed9;
__rtl_dmul_v1_00 = 0x2b555;
__rtl_ddiv_v1_00 = 0x2b8ad;
__rtl_dcmpeq_v1_00 = 0x2be4d;
__rtl_dcmplt_v1_00 = 0x2bebd;
__rtl_dcmpgt_v1_00 = 0x2bf51;
__rtl_dcmple_v1_00 = 0x2c049;
__rtl_fcmplt_v1_00 = 0x2c139;
__rtl_fcmpgt_v1_00 = 0x2c195;
__rtl_cos_f32_v1_00 = 0x2c229;
__rtl_sin_f32_v1_00 = 0x2c435;
__rtl_fabs_v1_00 = 0x2c639;
__rtl_fabsf_v1_00 = 0x2c641;
__rtl_dtoa_r_v1_00 = 0x2c77d;
__rom_mallocr_init_v1_00 = 0x2d7d1;
__rtl_free_r_v1_00 = 0x2d841;
__rtl_malloc_r_v1_00 = 0x2da31;
__rtl_realloc_r_v1_00 = 0x2df55;
__rtl_memalign_r_v1_00 = 0x2e331;
__rtl_valloc_r_v1_00 = 0x2e421;
__rtl_pvalloc_r_v1_00 = 0x2e42d;
__rtl_calloc_r_v1_00 = 0x2e441;
__rtl_cfree_r_v1_00 = 0x2e4a9;
__rtl_Balloc_v1_00 = 0x2e515;
__rtl_Bfree_v1_00 = 0x2e571;
__rtl_i2b_v1_00 = 0x2e585;
__rtl_multadd_v1_00 = 0x2e599;
__rtl_mult_v1_00 = 0x2e629;
__rtl_pow5mult_v1_00 = 0x2e769;
__rtl_hi0bits_v1_00 = 0x2e809;
__rtl_d2b_v1_00 = 0x2e845;
__rtl_lshift_v1_00 = 0x2e901;
__rtl_cmp_v1_00 = 0x2e9bd;
__rtl_diff_v1_00 = 0x2ea01;
__rtl_sread_v1_00 = 0x2eae9;
__rtl_seofread_v1_00 = 0x2eb39;
__rtl_swrite_v1_00 = 0x2eb3d;
__rtl_sseek_v1_00 = 0x2ebc1;
__rtl_sclose_v1_00 = 0x2ec11;
__rtl_sbrk_r_v1_00 = 0x2ec41;
__rtl_fflush_r_v1_00 = 0x2ef8d;
__rtl_vfprintf_r_v1_00 = 0x2f661;
__rtl_fpclassifyd = 0x30c15;
CpkClkTbl = 0x30c68;
ROM_IMG1_VALID_PATTEN = 0x30c80;
SpicCalibrationPattern = 0x30c88;
SpicInitCPUCLK = 0x30c98;
BAUDRATE = 0x30ca8;
OVSR = 0x30d1c;
DIV = 0x30d90;
OVSR_ADJ = 0x30e04;
__AES_rcon = 0x30e78;
__AES_Te4 = 0x30ea0;
I2CDmaChNo = 0x312a0;
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
_GPIO_SWPORT_DDR_TBL = 0x31594;
_GPIO_EXT_PORT_TBL = 0x31598;
_GPIO_SWPORT_DR_TBL = 0x3159c;
UartLogRomCmdTable = 0x316a0;
_HalRuartOp = 0x31700;
_HalGdmaOp = 0x31760;
RTW_WPA_OUI_TYPE = 0x3540c;
WPA_CIPHER_SUITE_NONE = 0x35410;
WPA_CIPHER_SUITE_WEP40 = 0x35414;
WPA_CIPHER_SUITE_TKIP = 0x35418;
WPA_CIPHER_SUITE_CCMP = 0x3541c;
WPA_CIPHER_SUITE_WEP104 = 0x35420;
RSN_CIPHER_SUITE_NONE = 0x35424;
RSN_CIPHER_SUITE_WEP40 = 0x35428;
RSN_CIPHER_SUITE_TKIP = 0x3542c;
RSN_CIPHER_SUITE_CCMP = 0x35430;
RSN_CIPHER_SUITE_WEP104 = 0x35434;
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
RSN_VERSION_BSD = 0x3544c;
rom_wps_Te0 = 0x35988;
rom_wps_rcons = 0x35d88;
rom_wps_Td4s = 0x35d94;
rom_wps_Td0 = 0x35e94;
__rom_b_cut_end__ = 0x4467c;
__rom_c_cut_text_start__ = 0x4467c;
HalInitPlatformLogUartV02 = 0x4467d;
HalReInitPlatformLogUartV02 = 0x4471d;
HalInitPlatformTimerV02 = 0x44755;
HalShowBuildInfoV02 = 0x447cd;
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
HalSpiInitV02 = 0x4488d;
HalBootFlowV02 = 0x44a29;
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
HalResetVsrV02 = 0x44b41;
HalI2CSendRtl8195aV02 = 0x44ce1;
HalI2CSetCLKRtl8195aV02 = 0x44d59;
RtkI2CSendV02 = 0x4508d;
RtkI2CReceiveV02 = 0x459a1;
HalI2COpInitV02 = 0x461ed;
I2CISRHandleV02 = 0x463e9;
RtkSalI2COpInitV02 = 0x46be1;
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
SpiFlashAppV02 = 0x46c85;
SpicInitRtl8195AV02 = 0x46dc5;
SpicEraseFlashRtl8195AV02 = 0x46ea1;
HalTimerIrq2To7HandleV02 = 0x46f5d;
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
HalTimerInitRtl8195aV02 = 0x4706d;
HalTimerReadCountRtl8195aV02 = 0x471b5;
HalTimerReLoadRtl8195aV02 = 0x471d1;
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
HalTimerDeInitRtl8195aV02 = 0x472c1;
HalTimerOpInitV02 = 0x472f9;
GPIO_LockV02 = 0x47345;
GPIO_UnLockV02 = 0x47379;
GPIO_Int_Clear_8195aV02 = 0x473a5;
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
FindElementIndexV02 = 0x47541;
HalRuartInitRtl8195aV02 = 0x4756d;
DramInit_rom = 0x47619;
ChangeRandSeed_rom = 0x47979;
Sdr_Rand2_rom = 0x47985;
MemTest_rom = 0x479dd;
SdrCalibration_rom = 0x47a45;
SdrControllerInit_rom = 0x47d99;
SDIO_EnterCritical = 0x47e39;
SDIO_ExitCritical = 0x47e85;
SDIO_IRQ_Handler_Rom = 0x47ec5;
SDIO_Interrupt_Init_Rom = 0x47f31;
SDIO_Device_Init_Rom = 0x47f81;
SDIO_Interrupt_DeInit_Rom = 0x48215;
SDIO_Device_DeInit_Rom = 0x48255;
SDIO_Enable_Interrupt_Rom = 0x48281;
SDIO_Disable_Interrupt_Rom = 0x482a1;
SDIO_Clear_ISR_Rom = 0x482c1;
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
SDIO_Free_Rx_Pkt_Rom = 0x48331;
SDIO_Recycle_Rx_BD_Rom = 0x48355;
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
SDIO_RxTask_Rom = 0x4851d;
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
SDIO_Process_RPWM_Rom = 0x485b5;
SDIO_Reset_Cmd_Rom = 0x485e9;
SDIO_Rx_Data_Transaction_Rom = 0x48611;
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
SDIO_Register_Tx_Callback_Rom = 0x488f5;
SDIO_ReadMem_Rom = 0x488fd;
SDIO_WriteMem_Rom = 0x489a9;
SDIO_SetMem_Rom = 0x48a69;
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
SDIO_TxTask_Rom = 0x48e9d;
SDIO_TaskUp_Rom = 0x48eed;
SDIO_Boot_Up = 0x48f55;
__rom_c_cut_text_end__ = 0x49070;
__rom_c_cut_rodata_start__ = 0x49070;
BAUDRATE_v02 = 0x49070;
OVSR_v02 = 0x490fc;
DIV_v02 = 0x49188;
OVSR_ADJ_v02 = 0x49214;
SdrDramInfo_rom = 0x492a0;
SdrDramTiming_rom = 0x492b4;
SdrDramModeReg_rom = 0x492e8;
SdrDramDev_rom = 0x49304;
__rom_c_cut_rodata_end__ = 0x49314;
NewVectorTable = 0x10000000;
UserIrqFunTable = 0x10000100;
UserIrqDataTable = 0x10000200;
__rom_bss_start__ = 0x10000300;
CfgSysDebugWarn = 0x10000300;
CfgSysDebugInfo = 0x10000304;
CfgSysDebugErr = 0x10000308;
ConfigDebugWarn = 0x1000030c;
ConfigDebugInfo = 0x10000310;
ConfigDebugErr = 0x10000314;
HalTimerOp = 0x10000318;
GPIOState = 0x10000334;
gTimerRecord = 0x1000034c;
SSI_DBG_CONFIG = 0x10000350;
_pHAL_Gpio_Adapter = 0x10000354;
Timer2To7VectorTable = 0x10000358;
pUartLogCtl = 0x10000384;
UartLogBuf = 0x10000388;
UartLogCtl = 0x10000408;
UartLogHistoryBuf = 0x10000430;
ArgvArray = 0x100006ac;
rom_wlan_ram_map = 0x100006d4;
FalseAlmCnt = 0x100006e0;
ROMInfo = 0x10000720;
DM_CfoTrack = 0x10000738;
rom_libgloss_ram_map = 0x10000760;
__rtl_errno = 0x10000bc4;
_rtl_impure_ptr = 0x10001c60;
}

View file

@ -0,0 +1,743 @@
SECTIONS
{
__vectors_table = 0x0;
Reset_Handler = 0x101;
NMI_Handler = 0x109;
HardFault_Handler = 0x10d;
MemManage_Handler = 0x121;
BusFault_Handler = 0x125;
UsageFault_Handler = 0x129;
HalLogUartInit = 0x201;
HalSerialPutcRtl8195a = 0x2d9;
HalSerialGetcRtl8195a = 0x309;
HalSerialGetIsrEnRegRtl8195a = 0x329;
HalSerialSetIrqEnRegRtl8195a = 0x335;
HalCpuClkConfig = 0x341;
HalGetCpuClk = 0x355;
HalRomInfo = 0x39d;
HalGetRomInfo = 0x3b5;
HalResetVsr = 0x3c5;
HalDelayUs = 0x899;
HalNMIHandler = 0x8e1;
HalHardFaultHandler = 0x911;
HalMemManageHandler = 0xc09;
HalBusFaultHandler = 0xc39;
HalUsageFaultHandler = 0xc69;
HalUart0PinCtrlRtl8195A = 0xcfd;
HalUart1PinCtrlRtl8195A = 0xdc9;
HalUart2PinCtrlRtl8195A = 0xe9d;
HalSPI0PinCtrlRtl8195A = 0xf75;
HalSPI1PinCtrlRtl8195A = 0x1015;
HalSPI2PinCtrlRtl8195A = 0x10e5;
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
HalI2C0PinCtrlRtl8195A = 0x1275;
HalI2C1PinCtrlRtl8195A = 0x1381;
HalI2C2PinCtrlRtl8195A = 0x1459;
HalI2C3PinCtrlRtl8195A = 0x1529;
HalI2S0PinCtrlRtl8195A = 0x1639;
HalI2S1PinCtrlRtl8195A = 0x176d;
HalPCM0PinCtrlRtl8195A = 0x1845;
HalPCM1PinCtrlRtl8195A = 0x1949;
HalSDIODPinCtrlRtl8195A = 0x1a1d;
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
HalMIIPinCtrlRtl8195A = 0x1ab9;
HalWLLEDPinCtrlRtl8195A = 0x1b51;
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
HalWLANT1PinCtrlRtl8195A = 0x1c61;
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
HalNFCPinCtrlRtl8195A = 0x1d59;
HalPWM0PinCtrlRtl8195A = 0x1da9;
HalPWM1PinCtrlRtl8195A = 0x1ead;
HalPWM2PinCtrlRtl8195A = 0x1fb5;
HalPWM3PinCtrlRtl8195A = 0x20b1;
HalETE0PinCtrlRtl8195A = 0x21b9;
HalETE1PinCtrlRtl8195A = 0x22c1;
HalETE2PinCtrlRtl8195A = 0x23c9;
HalETE3PinCtrlRtl8195A = 0x24d1;
HalEGTIMPinCtrlRtl8195A = 0x25d9;
HalSPIFlashPinCtrlRtl8195A = 0x2679;
HalSDRPinCtrlRtl8195A = 0x2725;
HalJTAGPinCtrlRtl8195A = 0x280d;
HalTRACEPinCtrlRtl8195A = 0x2861;
HalLOGUartPinCtrlRtl8195A = 0x28b9;
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
HalSICPinCtrlRtl8195A = 0x2981;
HalEEPROMPinCtrlRtl8195A = 0x29d9;
HalDEBUGPinCtrlRtl8195A = 0x2a31;
HalPinCtrlRtl8195A = 0x2b39;
SpicRxCmdRtl8195A = 0x2e5d;
SpicWaitBusyDoneRtl8195A = 0x2ea5;
SpicGetFlashStatusRtl8195A = 0x2eb5;
SpicWaitWipDoneRtl8195A = 0x2f55;
SpicTxCmdRtl8195A = 0x2f6d;
SpicSetFlashStatusRtl8195A = 0x2fc1;
SpicCmpDataForCalibrationRtl8195A = 0x3049;
SpicLoadInitParaFromClockRtl8195A = 0x3081;
SpicInitRtl8195A = 0x30e5;
SpicEraseFlashRtl8195A = 0x31bd;
SpiFlashApp = 0x3279;
HalPeripheralIntrHandle = 0x33b5;
HalSysOnIntrHandle = 0x3439;
HalWdgIntrHandle = 0x3485;
HalTimer0IntrHandle = 0x34d5;
HalTimer1IntrHandle = 0x3525;
HalI2C3IntrHandle = 0x3575;
HalTimer2To7IntrHandle = 0x35c5;
HalSpi0IntrHandle = 0x3615;
HalGpioIntrHandle = 0x3665;
HalUart0IntrHandle = 0x36b5;
HalSpiFlashIntrHandle = 0x3705;
HalUsbOtgIntrHandle = 0x3755;
HalSdioHostIntrHandle = 0x37a5;
HalI2s0OrPcm0IntrHandle = 0x37f5;
HalI2s1OrPcm1IntrHandle = 0x3845;
HalWlDmaIntrHandle = 0x3895;
HalWlProtocolIntrHandle = 0x38e5;
HalCryptoIntrHandle = 0x3935;
HalGmacIntrHandle = 0x3985;
HalGdma0Ch0IntrHandle = 0x39d5;
HalGdma0Ch1IntrHandle = 0x3a25;
HalGdma0Ch2IntrHandle = 0x3a75;
HalGdma0Ch3IntrHandle = 0x3ac5;
HalGdma0Ch4IntrHandle = 0x3b15;
HalGdma0Ch5IntrHandle = 0x3b65;
HalGdma1Ch0IntrHandle = 0x3bb5;
HalGdma1Ch1IntrHandle = 0x3c05;
HalGdma1Ch2IntrHandle = 0x3c55;
HalGdma1Ch3IntrHandle = 0x3ca5;
HalGdma1Ch4IntrHandle = 0x3cf5;
HalGdma1Ch5IntrHandle = 0x3d45;
HalSdioDeviceIntrHandle = 0x3d95;
VectorTableInitRtl8195A = 0x3de5;
VectorTableInitForOSRtl8195A = 0x4019;
VectorIrqRegisterRtl8195A = 0x4029;
VectorIrqUnRegisterRtl8195A = 0x4091;
VectorIrqEnRtl8195A = 0x40f1;
VectorIrqDisRtl8195A = 0x418d;
_UartRxDmaIrqHandle = 0x422d;
HalRuartPutCRtl8195a = 0x4281;
HalRuartGetCRtl8195a = 0x429d;
HalRuartRTSCtrlRtl8195a = 0x42bd;
HalRuartGetDebugValueRtl8195a = 0x42e1;
HalRuartGetIMRRtl8195a = 0x43e1;
HalRuartSetIMRRtl8195a = 0x442d;
_UartIrqHandle = 0x4465;
HalRuartDmaInitRtl8195a = 0x4681;
HalRuartIntDisableRtl8195a = 0x4845;
HalRuartDeInitRtl8195a = 0x4855;
HalRuartIntEnableRtl8195a = 0x4985;
_UartTxDmaIrqHandle = 0x4995;
HalRuartRegIrqRtl8195a = 0x49d1;
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
RuartLock = 0x4cc9;
RuartUnLock = 0x4ced;
HalRuartIntSendRtl8195a = 0x4d09;
HalRuartDmaSendRtl8195a = 0x4e35;
HalRuartStopSendRtl8195a = 0x4f89;
HalRuartIntRecvRtl8195a = 0x504d;
HalRuartDmaRecvRtl8195a = 0x51ad;
HalRuartStopRecvRtl8195a = 0x52cd;
RuartIsTimeout = 0x5385;
HalRuartSendRtl8195a = 0x53b1;
HalRuartRecvRtl8195a = 0x5599;
RuartResetRxFifoRtl8195a = 0x5751;
HalRuartResetRxFifoRtl8195a = 0x5775;
HalRuartInitRtl8195a = 0x5829;
HalGdmaOnOffRtl8195a = 0x5df1;
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
HalGdmaChEnRtl8195a = 0x5e51;
HalGdmaChDisRtl8195a = 0x5e6d;
HalGdamChInitRtl8195a = 0x5e91;
HalGdmaChSetingRtl8195a = 0x5ebd;
HalGdmaChBlockSetingRtl8195a = 0x000060dd;
HalGdmaChIsrCleanRtl8195a = 0x6419;
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
HalEFUSEPowerSwitch8195AROM = 0x6561;
HALEFUSEOneByteReadROM = 0x65f9;
HALEFUSEOneByteWriteROM = 0x6699;
__rtl_memcmpb_v1_00 = 0x681d;
__rtl_random_v1_00 = 0x6861;
__rtl_align_to_be32_v1_00 = 0x6881;
__rtl_memsetw_v1_00 = 0x6899;
__rtl_memsetb_v1_00 = 0x68ad;
__rtl_memcpyw_v1_00 = 0x68bd;
__rtl_memcpyb_v1_00 = 0x68dd;
__rtl_memDump_v1_00 = 0x68f5;
__rtl_AES_set_encrypt_key = 0x6901;
__rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
__rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
__rtl_cryptoEngine_init_v1_00 = 0x6ea9;
__rtl_cryptoEngine_exit_v1_00 = 0x7055;
__rtl_cryptoEngine_reset_v1_00 = 0x70b1;
__rtl_cryptoEngine_v1_00 = 0x70ed;
__rtl_crypto_cipher_init_v1_00 = 0x7c69;
__rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
__rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
HalSsiEnableRtl8195a = 0x7e45;
HalSsiDisableRtl8195a = 0x7ef9;
HalSsiLoadSettingRtl8195a = 0x7fad;
HalSsiSetInterruptMaskRtl8195a = 0x8521;
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
HalSsiSetSclkPolarityRtl8195a = 0x863d;
HalSsiSetSclkPhaseRtl8195a = 0x8715;
HalSsiWriteRtl8195a = 0x87e9;
HalSsiSetDeviceRoleRtl8195a = 0x8861;
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
HalSsiReadRtl8195a = 0x89b9;
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
HalSsiGetStatusRtl8195a = 0x8b1d;
HalSsiWriteableRtl8195a = 0x8b91;
HalSsiReadableRtl8195a = 0x8c09;
HalSsiBusyRtl8195a = 0x8c81;
HalSsiReadInterruptRtl8195a = 0x8cf9;
HalSsiWriteInterruptRtl8195a = 0x8efd;
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
HalSsiInterruptEnableRtl8195a = 0x914d;
HalSsiInterruptDisableRtl8195a = 0x9299;
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
HalSsiInitRtl8195a = 0x94d1;
_SsiReadInterrupt = 0x9ba5;
_SsiWriteInterrupt = 0x9db1;
_SsiIrqHandle = 0x9eb1;
HalI2CWrite32 = 0xa061;
HalI2CRead32 = 0xa09d;
HalI2CDeInit8195a = 0xa0dd;
HalI2CSendRtl8195a = 0xa1f1;
HalI2CReceiveRtl8195a = 0xa25d;
HalI2CEnableRtl8195a = 0xa271;
HalI2CIntrCtrl8195a = 0xa389;
HalI2CReadRegRtl8195a = 0xa3a1;
HalI2CWriteRegRtl8195a = 0xa3b1;
HalI2CSetCLKRtl8195a = 0xa3c5;
HalI2CMassSendRtl8195a = 0xa6e9;
HalI2CClrIntrRtl8195a = 0xa749;
HalI2CClrAllIntrRtl8195a = 0xa761;
HalI2CInit8195a = 0xa775;
HalI2CDMACtrl8195a = 0xaa31;
RtkI2CIoCtrl = 0xaa61;
RtkI2CPowerCtrl = 0xaa65;
HalI2COpInit = 0xaa69;
I2CIsTimeout = 0xac65;
I2CTXGDMAISRHandle = 0xb435;
I2CRXGDMAISRHandle = 0xb4c1;
RtkI2CIrqInit = 0xb54d;
RtkI2CIrqDeInit = 0xb611;
RtkI2CPinMuxInit = 0xb675;
RtkI2CPinMuxDeInit = 0xb7c9;
RtkI2CDMAInit = 0xb955;
RtkI2CInit = 0xbc95;
RtkI2CDMADeInit = 0xbdad;
RtkI2CDeInit = 0xbe4d;
RtkI2CSendUserAddr = 0xbee5;
RtkI2CSend = 0xc07d;
RtkI2CLoadDefault = 0xce51;
RtkSalI2COpInit = 0xcf21;
HalI2SWrite32 = 0xcf65;
HalI2SRead32 = 0xcf85;
HalI2SDeInitRtl8195a = 0xcfa9;
HalI2STxRtl8195a = 0xcfc9;
HalI2SRxRtl8195a = 0xd011;
HalI2SEnableRtl8195a = 0xd05d;
HalI2SIntrCtrlRtl8195a = 0xd0b1;
HalI2SReadRegRtl8195a = 0xd0d1;
HalI2SClrIntrRtl8195a = 0xd0dd;
HalI2SClrAllIntrRtl8195a = 0xd0fd;
HalI2SInitRtl8195a = 0xd11d;
GPIO_GetIPPinName_8195a = 0xd2e5;
GPIO_GetChipPinName_8195a = 0xd331;
GPIO_PullCtrl_8195a = 0xd39d;
GPIO_FuncOn_8195a = 0xd421;
GPIO_FuncOff_8195a = 0xd481;
GPIO_Int_Mask_8195a = 0xd4e9;
GPIO_Int_SetType_8195a = 0xd511;
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
HAL_GPIO_Init_8195a = 0xd805;
HAL_GPIO_DeInit_8195a = 0xdac1;
HAL_GPIO_ReadPin_8195a = 0xdbd1;
HAL_GPIO_WritePin_8195a = 0xdc91;
HAL_GPIO_RegIrq_8195a = 0xddad;
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
HAL_GPIO_UserRegIrq_8195a = 0xde15;
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
HAL_GPIO_IntDebounce_8195a = 0xe101;
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
DumpForOneBytes = 0xe259;
CmdRomHelp = 0xe419;
CmdWriteWord = 0xe491;
CmdDumpHelfWord = 0xe505;
CmdDumpWord = 0xe5f1;
CmdDumpByte = 0xe6f5;
CmdSpiFlashTool = 0xe751;
GetRomCmdNum = 0xe7a9;
CmdWriteByte = 0xe7ad;
Isspace = 0xe7ed;
Strtoul = 0xe801;
ArrayInitialize = 0xe8b1;
GetArgc = 0xe8c9;
GetArgv = 0xe8f9;
UartLogCmdExecute = 0xe95d;
UartLogShowBackSpace = 0xe9fd;
UartLogRecallOldCmd = 0xea39;
UartLogHistoryCmd = 0xea71;
UartLogCmdChk = 0xeadd;
UartLogIrqHandle = 0xebf5;
RtlConsolInit = 0xecc5;
RtlConsolTaskRom = 0xed49;
RtlExitConsol = 0xed79;
RtlConsolRom = 0xedcd;
HalTimerOpInit = 0xee0d;
HalTimerIrq2To7Handle = 0xee59;
HalGetTimerIdRtl8195a = 0xef09;
HalTimerInitRtl8195a = 0xef3d;
HalTimerDisRtl8195a = 0xf069;
HalTimerEnRtl8195a = 0xf089;
HalTimerReadCountRtl8195a = 0xf0a9;
HalTimerIrqClearRtl8195a = 0xf0bd;
HalTimerDumpRegRtl8195a = 0xf0d1;
VSprintf = 0xf129;
DiagPrintf = 0xf39d;
DiagSPrintf = 0xf3b9;
DiagSnPrintf = 0xf3d1;
prvDiagPrintf = 0xf3ed;
prvDiagSPrintf = 0xf40d;
_memcmp = 0xf429;
_memcpy = 0xf465;
_memset = 0xf511;
Rand = 0xf585;
_strncpy = 0xf60d;
_strcpy = 0xf629;
prvStrCpy = 0xf639;
_strlen = 0xf651;
_strnlen = 0xf669;
prvStrLen = 0xf699;
_strcmp = 0xf6b1;
_strncmp = 0xf6d1;
prvStrCmp = 0xf719;
StrUpr = 0xf749;
prvAtoi = 0xf769;
prvStrStr = 0xf7bd;
_strsep = 0xf7d5;
skip_spaces = 0xf815;
skip_atoi = 0xf831;
_parse_integer_fixup_radix = 0xf869;
_parse_integer = 0xf8bd;
simple_strtoull = 0xf915;
simple_strtoll = 0xf945;
simple_strtoul = 0xf965;
simple_strtol = 0xf96d;
_vsscanf = 0xf985;
_sscanf = 0xff71;
div_u64 = 0xff91;
div_s64 = 0xff99;
div_u64_rem = 0xffa1;
div_s64_rem = 0xffb1;
_strpbrk = 0xffc1;
_strchr = 0xffed;
aes_set_key = 0x10005;
aes_encrypt = 0x103d1;
aes_decrypt = 0x114a5;
AES_WRAP = 0x125c9;
AES_UnWRAP = 0x12701;
crc32_get = 0x12861;
arc4_byte = 0x12895;
rt_arc4_init = 0x128bd;
rt_arc4_crypt = 0x12901;
rt_md5_init = 0x131c1;
rt_md5_append = 0x131f5;
rt_md5_final = 0x1327d;
rt_md5_hmac = 0x132d5;
rtw_get_bit_value_from_ieee_value = 0x13449;
rtw_is_cckrates_included = 0x13475;
rtw_is_cckratesonly_included = 0x134b5;
rtw_check_network_type = 0x134dd;
rtw_set_fixed_ie = 0x1350d;
rtw_set_ie = 0x1352d;
rtw_get_ie = 0x1355d;
rtw_set_supported_rate = 0x13591;
rtw_get_rateset_len = 0x13611;
rtw_get_wpa_ie = 0x1362d;
rtw_get_wpa2_ie = 0x136c9;
rtw_get_wpa_cipher_suite = 0x13701;
rtw_get_wpa2_cipher_suite = 0x13769;
rtw_parse_wpa_ie = 0x137d1;
rtw_parse_wpa2_ie = 0x138ad;
rtw_get_sec_ie = 0x13965;
rtw_get_wps_ie = 0x13a15;
rtw_get_wps_attr = 0x13a99;
rtw_get_wps_attr_content = 0x13b49;
rtw_ieee802_11_parse_elems = 0x13b91;
str_2char2num = 0x13d9d;
key_2char2num = 0x13db9;
convert_ip_addr = 0x13dd1;
rom_psk_PasswordHash = 0x13e9d;
rom_psk_CalcGTK = 0x13ed5;
rom_psk_CalcPTK = 0x13f69;
wep_80211_encrypt = 0x14295;
wep_80211_decrypt = 0x142f5;
tkip_micappendbyte = 0x14389;
rtw_secmicsetkey = 0x143d9;
rtw_secmicappend = 0x14419;
rtw_secgetmic = 0x14435;
rtw_seccalctkipmic = 0x1449d;
tkip_phase1 = 0x145a5;
tkip_phase2 = 0x14725;
tkip_80211_encrypt = 0x14941;
tkip_80211_decrypt = 0x149d5;
aes1_encrypt = 0x14a8d;
aesccmp_construct_mic_iv = 0x14c65;
aesccmp_construct_mic_header1 = 0x14ccd;
aesccmp_construct_mic_header2 = 0x14d21;
aesccmp_construct_ctr_preload = 0x14db5;
aes_80211_encrypt = 0x14e29;
aes_80211_decrypt = 0x151ad;
_sha1_process_message_block = 0x155b9;
_sha1_pad_message = 0x15749;
rt_sha1_init = 0x157e5;
rt_sha1_update = 0x15831;
rt_sha1_finish = 0x158a9;
rt_hmac_sha1 = 0x15909;
rom_aes_128_cbc_encrypt = 0x15a65;
rom_aes_128_cbc_decrypt = 0x15ae1;
rom_rijndaelKeySetupEnc = 0x15b5d;
rom_aes_decrypt_init = 0x15c39;
rom_aes_internal_decrypt = 0x15d15;
rom_aes_decrypt_deinit = 0x16071;
rom_aes_encrypt_init = 0x16085;
rom_aes_internal_encrypt = 0x1609d;
rom_aes_encrypt_deinit = 0x16451;
bignum_init = 0x17b35;
bignum_deinit = 0x17b61;
bignum_get_unsigned_bin_len = 0x17b81;
bignum_get_unsigned_bin = 0x17b85;
bignum_set_unsigned_bin = 0x17c21;
bignum_cmp = 0x17cd1;
bignum_cmp_d = 0x17cd5;
bignum_add = 0x17cfd;
bignum_sub = 0x17d0d;
bignum_mul = 0x17d1d;
bignum_exptmod = 0x17d2d;
WPS_realloc = 0x17d51;
os_zalloc = 0x17d99;
rom_hmac_sha256_vector = 0x17dc1;
rom_hmac_sha256 = 0x17ebd;
rom_sha256_vector = 0x18009;
phy_CalculateBitShift = 0x18221;
PHY_SetBBReg_8195A = 0x18239;
PHY_QueryBBReg_8195A = 0x18279;
ROM_odm_QueryRxPwrPercentage = 0x1829d;
ROM_odm_EVMdbToPercentage = 0x182bd;
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
ROM_odm_SetEDCCAThreshold = 0x18721;
ROM_odm_SetTRxMux = 0x18749;
ROM_odm_SetCrystalCap = 0x18771;
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
ROM_ODM_CfoTrackingReset = 0x187e9;
ROM_odm_CfoTrackingFlow = 0x18811;
curve25519_donna = 0x1965d;
aes_test_alignment_detection = 0x1a391;
aes_mode_reset = 0x1a3ed;
aes_ecb_encrypt = 0x1a3f9;
aes_ecb_decrypt = 0x1a431;
aes_cbc_encrypt = 0x1a469;
aes_cbc_decrypt = 0x1a579;
aes_cfb_encrypt = 0x1a701;
aes_cfb_decrypt = 0x1a9e5;
aes_ofb_crypt = 0x1acc9;
aes_ctr_crypt = 0x1af7d;
aes_encrypt_key128 = 0x1b289;
aes_encrypt_key192 = 0x1b2a5;
aes_encrypt_key256 = 0x1b2c1;
aes_encrypt_key = 0x1b2e1;
aes_decrypt_key128 = 0x1b351;
aes_decrypt_key192 = 0x1b36d;
aes_decrypt_key256 = 0x1b389;
aes_decrypt_key = 0x1b3a9;
aes_init = 0x1b419;
CRYPTO_chacha_20 = 0x1b41d;
CRYPTO_poly1305_init = 0x1bc25;
CRYPTO_poly1305_update = 0x1bd09;
CRYPTO_poly1305_finish = 0x1bd8d;
rom_sha512_starts = 0x1ceb5;
rom_sha512_update = 0x1d009;
rom_sha512_finish = 0x1d011;
rom_sha512 = 0x1d261;
rom_sha512_hmac_starts = 0x1d299;
rom_sha512_hmac_update = 0x1d35d;
rom_sha512_hmac_finish = 0x1d365;
rom_sha512_hmac_reset = 0x1d3b5;
rom_sha512_hmac = 0x1d3d1;
rom_sha512_hkdf = 0x1d40d;
rom_ed25519_gen_keypair = 0x1d501;
rom_ed25519_gen_signature = 0x1d505;
rom_ed25519_verify_signature = 0x1d51d;
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
rom_ed25519_crypto_sign_detached = 0x1d579;
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
rom_ed25519_ge_p3_tobytes = 0x207d5;
rom_ed25519_ge_scalarmult_base = 0x20821;
rom_ed25519_ge_tobytes = 0x209e1;
rom_ed25519_sc_muladd = 0x20a2d;
rom_ed25519_sc_reduce = 0x2603d;
__rtl_memchr_v1_00 = 0x28a4d;
__rtl_memcmp_v1_00 = 0x28ae1;
__rtl_memcpy_v1_00 = 0x28b49;
__aeabi_memcpy = 0x28b49;
__aeabi_memcpy4 = 0x28b49;
__rtl_memmove_v1_00 = 0x28bed;
__rtl_memset_v1_00 = 0x28cb5;
__aeabi_memset = 0x28cb5;
__rtl_strcat_v1_00 = 0x28d49;
__rtl_strchr_v1_00 = 0x28d91;
__rtl_strcmp_v1_00 = 0x28e55;
__rtl_strcpy_v1_00 = 0x28ec9;
__rtl_strlen_v1_00 = 0x28f15;
__rtl_strncat_v1_00 = 0x28f69;
__rtl_strncmp_v1_00 = 0x28fc5;
__rtl_strncpy_v1_00 = 0x2907d;
__rtl_strstr_v1_00 = 0x293cd;
__rtl_strsep_v1_00 = 0x2960d;
__rtl_strtok_v1_00 = 0x29619;
__rtl__strtok_r_v1_00 = 0x2962d;
__rtl_strtok_r_v1_00 = 0x29691;
__rtl_close_v1_00 = 0x29699;
__rtl_fstat_v1_00 = 0x296ad;
__rtl_isatty_v1_00 = 0x296c1;
__rtl_lseek_v1_00 = 0x296d5;
__rtl_open_v1_00 = 0x296e9;
__rtl_read_v1_00 = 0x296fd;
__rtl_write_v1_00 = 0x29711;
__rtl_sbrk_v1_00 = 0x29725;
__rtl_ltoa_v1_00 = 0x297bd;
__rtl_ultoa_v1_00 = 0x29855;
__rtl_dtoi_v1_00 = 0x298c5;
__rtl_dtoi64_v1_00 = 0x29945;
__rtl_dtoui_v1_00 = 0x299dd;
__rtl_ftol_v1_00 = 0x299e5;
__rtl_itof_v1_00 = 0x29a51;
__rtl_itod_v1_00 = 0x29ae9;
__rtl_i64tod_v1_00 = 0x29b79;
__rtl_uitod_v1_00 = 0x29c55;
__rtl_ftod_v1_00 = 0x29d2d;
__rtl_dtof_v1_00 = 0x29de9;
__rtl_uitof_v1_00 = 0x29e89;
__rtl_fadd_v1_00 = 0x29f65;
__rtl_fsub_v1_00 = 0x2a261;
__rtl_fmul_v1_00 = 0x2a559;
__rtl_fdiv_v1_00 = 0x2a695;
__rtl_dadd_v1_00 = 0x2a825;
__rtl_dsub_v1_00 = 0x2aed9;
__rtl_dmul_v1_00 = 0x2b555;
__rtl_ddiv_v1_00 = 0x2b8ad;
__rtl_dcmpeq_v1_00 = 0x2be4d;
__rtl_dcmplt_v1_00 = 0x2bebd;
__rtl_dcmpgt_v1_00 = 0x2bf51;
__rtl_dcmple_v1_00 = 0x2c049;
__rtl_fcmplt_v1_00 = 0x2c139;
__rtl_fcmpgt_v1_00 = 0x2c195;
__rtl_cos_f32_v1_00 = 0x2c229;
__rtl_sin_f32_v1_00 = 0x2c435;
__rtl_fabs_v1_00 = 0x2c639;
__rtl_fabsf_v1_00 = 0x2c641;
__rtl_dtoa_r_v1_00 = 0x2c77d;
__rom_mallocr_init_v1_00 = 0x2d7d1;
__rtl_free_r_v1_00 = 0x2d841;
__rtl_malloc_r_v1_00 = 0x2da31;
__rtl_realloc_r_v1_00 = 0x2df55;
__rtl_memalign_r_v1_00 = 0x2e331;
__rtl_valloc_r_v1_00 = 0x2e421;
__rtl_pvalloc_r_v1_00 = 0x2e42d;
__rtl_calloc_r_v1_00 = 0x2e441;
__rtl_cfree_r_v1_00 = 0x2e4a9;
__rtl_Balloc_v1_00 = 0x2e515;
__rtl_Bfree_v1_00 = 0x2e571;
__rtl_i2b_v1_00 = 0x2e585;
__rtl_multadd_v1_00 = 0x2e599;
__rtl_mult_v1_00 = 0x2e629;
__rtl_pow5mult_v1_00 = 0x2e769;
__rtl_hi0bits_v1_00 = 0x2e809;
__rtl_d2b_v1_00 = 0x2e845;
__rtl_lshift_v1_00 = 0x2e901;
__rtl_cmp_v1_00 = 0x2e9bd;
__rtl_diff_v1_00 = 0x2ea01;
__rtl_sread_v1_00 = 0x2eae9;
__rtl_seofread_v1_00 = 0x2eb39;
__rtl_swrite_v1_00 = 0x2eb3d;
__rtl_sseek_v1_00 = 0x2ebc1;
__rtl_sclose_v1_00 = 0x2ec11;
__rtl_sbrk_r_v1_00 = 0x2ec41;
__rtl_fflush_r_v1_00 = 0x2ef8d;
__rtl_vfprintf_r_v1_00 = 0x2f661;
__rtl_fpclassifyd = 0x30c15;
CpkClkTbl = 0x30c68;
ROM_IMG1_VALID_PATTEN = 0x30c80;
SpicCalibrationPattern = 0x30c88;
SpicInitCPUCLK = 0x30c98;
BAUDRATE = 0x30ca8;
OVSR = 0x30d1c;
DIV = 0x30d90;
OVSR_ADJ = 0x30e04;
__AES_rcon = 0x30e78;
__AES_Te4 = 0x30ea0;
I2CDmaChNo = 0x312a0;
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
_GPIO_SWPORT_DDR_TBL = 0x31594;
_GPIO_EXT_PORT_TBL = 0x31598;
_GPIO_SWPORT_DR_TBL = 0x3159c;
UartLogRomCmdTable = 0x316a0;
_HalRuartOp = 0x31700;
_HalGdmaOp = 0x31760;
RTW_WPA_OUI_TYPE = 0x3540c;
WPA_CIPHER_SUITE_NONE = 0x35410;
WPA_CIPHER_SUITE_WEP40 = 0x35414;
WPA_CIPHER_SUITE_TKIP = 0x35418;
WPA_CIPHER_SUITE_CCMP = 0x3541c;
WPA_CIPHER_SUITE_WEP104 = 0x35420;
RSN_CIPHER_SUITE_NONE = 0x35424;
RSN_CIPHER_SUITE_WEP40 = 0x35428;
RSN_CIPHER_SUITE_TKIP = 0x3542c;
RSN_CIPHER_SUITE_CCMP = 0x35430;
RSN_CIPHER_SUITE_WEP104 = 0x35434;
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
RSN_VERSION_BSD = 0x3544c;
rom_wps_Te0 = 0x35988;
rom_wps_rcons = 0x35d88;
rom_wps_Td4s = 0x35d94;
rom_wps_Td0 = 0x35e94;
__rom_b_cut_end__ = 0x4467c;
__rom_c_cut_text_start__ = 0x4467c;
HalInitPlatformLogUartV02 = 0x4467d;
HalReInitPlatformLogUartV02 = 0x4471d;
HalInitPlatformTimerV02 = 0x44755;
HalShowBuildInfoV02 = 0x447cd;
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
HalSpiInitV02 = 0x4488d;
HalBootFlowV02 = 0x44a29;
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
HalResetVsrV02 = 0x44b41;
HalI2CSendRtl8195aV02 = 0x44ce1;
HalI2CSetCLKRtl8195aV02 = 0x44d59;
RtkI2CSendV02 = 0x4508d;
RtkI2CReceiveV02 = 0x459a1;
HalI2COpInitV02 = 0x461ed;
I2CISRHandleV02 = 0x463e9;
RtkSalI2COpInitV02 = 0x46be1;
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
SpiFlashAppV02 = 0x46c85;
SpicInitRtl8195AV02 = 0x46dc5;
SpicEraseFlashRtl8195AV02 = 0x46ea1;
HalTimerIrq2To7HandleV02 = 0x46f5d;
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
HalTimerInitRtl8195aV02 = 0x4706d;
HalTimerReadCountRtl8195aV02 = 0x471b5;
HalTimerReLoadRtl8195aV02 = 0x471d1;
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
HalTimerDeInitRtl8195aV02 = 0x472c1;
HalTimerOpInitV02 = 0x472f9;
GPIO_LockV02 = 0x47345;
GPIO_UnLockV02 = 0x47379;
GPIO_Int_Clear_8195aV02 = 0x473a5;
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
FindElementIndexV02 = 0x47541;
HalRuartInitRtl8195aV02 = 0x4756d;
DramInit_rom = 0x47619;
ChangeRandSeed_rom = 0x47979;
Sdr_Rand2_rom = 0x47985;
MemTest_rom = 0x479dd;
SdrCalibration_rom = 0x47a45;
SdrControllerInit_rom = 0x47d99;
SDIO_EnterCritical = 0x47e39;
SDIO_ExitCritical = 0x47e85;
SDIO_IRQ_Handler_Rom = 0x47ec5;
SDIO_Interrupt_Init_Rom = 0x47f31;
SDIO_Device_Init_Rom = 0x47f81;
SDIO_Interrupt_DeInit_Rom = 0x48215;
SDIO_Device_DeInit_Rom = 0x48255;
SDIO_Enable_Interrupt_Rom = 0x48281;
SDIO_Disable_Interrupt_Rom = 0x482a1;
SDIO_Clear_ISR_Rom = 0x482c1;
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
SDIO_Free_Rx_Pkt_Rom = 0x48331;
SDIO_Recycle_Rx_BD_Rom = 0x48355;
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
SDIO_RxTask_Rom = 0x4851d;
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
SDIO_Process_RPWM_Rom = 0x485b5;
SDIO_Reset_Cmd_Rom = 0x485e9;
SDIO_Rx_Data_Transaction_Rom = 0x48611;
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
SDIO_Register_Tx_Callback_Rom = 0x488f5;
SDIO_ReadMem_Rom = 0x488fd;
SDIO_WriteMem_Rom = 0x489a9;
SDIO_SetMem_Rom = 0x48a69;
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
SDIO_TxTask_Rom = 0x48e9d;
SDIO_TaskUp_Rom = 0x48eed;
SDIO_Boot_Up = 0x48f55;
__rom_c_cut_text_end__ = 0x49070;
__rom_c_cut_rodata_start__ = 0x49070;
BAUDRATE_v02 = 0x49070;
OVSR_v02 = 0x490fc;
DIV_v02 = 0x49188;
OVSR_ADJ_v02 = 0x49214;
SdrDramInfo_rom = 0x492a0;
SdrDramTiming_rom = 0x492b4;
SdrDramModeReg_rom = 0x492e8;
SdrDramDev_rom = 0x49304;
__rom_c_cut_rodata_end__ = 0x49314;
NewVectorTable = 0x10000000;
UserIrqFunTable = 0x10000100;
UserIrqDataTable = 0x10000200;
__rom_bss_start__ = 0x10000300;
CfgSysDebugWarn = 0x10000300;
CfgSysDebugInfo = 0x10000304;
CfgSysDebugErr = 0x10000308;
ConfigDebugWarn = 0x1000030c;
ConfigDebugInfo = 0x10000310;
ConfigDebugErr = 0x10000314;
HalTimerOp = 0x10000318;
GPIOState = 0x10000334;
gTimerRecord = 0x1000034c;
SSI_DBG_CONFIG = 0x10000350;
_pHAL_Gpio_Adapter = 0x10000354;
Timer2To7VectorTable = 0x10000358;
_rand_first = 0x10000370;
_rand_z1 = 0x10000374;
_rand_z2 = 0x10000378;
_rand_z3 = 0x1000037C;
_rand_z4 = 0x10000380;
pUartLogCtl = 0x10000384;
UartLogBuf = 0x10000388;
UartLogCtl = 0x10000408;
UartLogHistoryBuf = 0x10000430;
ArgvArray = 0x100006ac;
rom_wlan_ram_map = 0x100006d4;
FalseAlmCnt = 0x100006e0;
ROMInfo = 0x10000720;
DM_CfoTrack = 0x10000738;
rom_libgloss_ram_map = 0x10000760;
__rtl_errno = 0x10000bc4;
_rtl_impure_ptr = 0x10001c60;
}

View file

@ -0,0 +1,18 @@
set libname=lib_platform
del %libname%_new.a
md %libname%.lib
cd %libname%.lib
PATH=D:\MCU\GNU_Tools_ARM_Embedded\5.2_2015q4\bin;%PATH%
arm-none-eabi-ar.exe x ..\%libname%.a
del hal_efuse.o
del hal_common.o
del freertos_pmu_8195a.o
del hal_soc_ps_monitor.o
del app_start.o
del hal_log_uart.o
del hal_pinmux.o
del hal_misc.o
del startup.o
arm-none-eabi-ar.exe ru ..\%libname%_new.a *.o
cd ..
rd /q /s %libname%.lib

View file

@ -0,0 +1,8 @@
for %%a in (*.a) do (
md %%a.o
cd %%a.o
arm-none-eabi-ar x ..\%%a
for %%o in (*.o) do arm-none-eabi-objdump -S %%o > %%o.asm
cd ..
)

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@ -0,0 +1,243 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_v02.txt"
MEMORY
{
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 65536
ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560
//RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 16128
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 434176
RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 7936
//BD_RAM (rwx) : ORIGIN = 0x10004000, LENGTH = 442368
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
}
SECTIONS
{
__rom_bss_start__ = 0x10000300;
__rom_bss_end__ = 0x10000bc8;
/*
.ram.start.table :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.start.ram.data*)))
__ram_start_table_end__ = .;
} > ROM_USED_RAM
*/
/* Add . to assign the start address of the section, *
* to prevent the change of the start address by ld doing section alignment */
/* these 4 sections is used by ROM global variable */
/* Don't move them and never add RAM code variable to these sections */
/*---------------------------
.ram_image1.text . :
{
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.infra.ram.data*))
KEEP(*(.timer.ram.data*))
KEEP(*(.cutb.ram.data*))
KEEP(*(.cutc.ram.data*))
KEEP(*(.hal.ram.data*))
__image1_bss_start__ = .;
__image1_bss_end__ = .;
__ram_image1_data_end__ = .;
*(.hal.ram.text*)
*(.infra.ram.text*)
__ram_image1_text_end__ = .;
} > ROM_USED_RAM
*/
/*
.tcm :
{
__tcm_start__ = .;
*(.tcm.heap)
*mem.o (.bss)
*memp.o (.bss)
__tcm_end__ = .;
} > TCM
----------------------------*/
.bootloader :
{
KEEP(*(.loader.data*))
} > ROM_USED_RAM
OVERLAY 0x1FFF0000:
{
.valid
{
*mem.o (.bss*)
*memp.o (.bss*)
*(.tcm.heap)
}
.dummy
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.start.ram.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.infra.ram.data*))
KEEP(*(.timer.ram.data*))
KEEP(*(.cutb.ram.data*))
KEEP(*(.cutc.ram.data*))
KEEP(*(.hal.ram.data*))
__image1_bss_start__ = .;
.ram_image1.bss$$Base = .;
__image1_bss_end__ = .;
.ram_image1.bss$$Limit = .;
__ram_image1_data_end__ = .;
*(.hal.ram.text*)
*(.infra.ram.text*)
}
} > TCM
.image2.start.table :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
.image2.start.table1$$Base = .;
KEEP(*(SORT(.image2.ram.data*)))
__image2_validate_code__ = .;
KEEP(*(.image2.validate.rodata*))
KEEP(*(.custom.validate.rodata*))
} > BD_RAM
.ram_image2.text :
{
KEEP(*(.infra.ram.start*))
*(.mon.ram.text*)
*(.hal.flash.text*)
*(.hal.sdrc.text*)
*(.hal.gpio.text*)
*(.fwu.text*)
*(.text*)
} > BD_RAM
.ram_image2.rodata :
{
*(.rodata*)
*(.fwu.rodata*)
} > BD_RAM
.ram.data :
{
__data_start__ = .;
*(.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
} > BD_RAM
.ram.bss :
{
__bss_start__ = .;
.ram.bss$$Base = .;
*(.hal.flash.data*)
*(.hal.sdrc.data*)
*(.hal.gpio.data*)
*(.fwu.data*)
*(.bss*)
*(COMMON)
*(.bdsram.data*)
__bss_end__ = .;
.ram.bss$$Limit = .;
} > BD_RAM
.bf_data :
{
__buffer_data_start__ = .;
*(.bfsram.data*)
__buffer_data_end__ = .;
} > BD_RAM
.bf_data2 :
{
__buffer_data_start2__ = .;
__buffer_data_end2__ = .;
} > RECY_RAM
.sdr_text :
{
__sdram_data_start__ = .;
*(.sdram.text*)
*(.p2p.text*)
*(.wps.text*)
*(.websocket.text*)
} > SDRAM_RAM
.sdr_rodata :
{
*(.sdram.rodata*)
*(.p2p.rodata*)
*(.wps.rodata*)
*(.websocket.rodata*)
} > SDRAM_RAM
.sdr_data :
{
*(.sdram.data*)
*(.p2p.data*)
*(.wps.data*)
*(.websocket.data*)
__sdram_data_end__ = .;
} > SDRAM_RAM
.sdr_bss :
{
__sdram_bss_start__ = .;
*(.sdram.bss*)
*(.p2p.bss*)
*(.wps.bss*)
*(.websocket.bss*)
__sdram_bss_end__ = .;
} > SDRAM_RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > BD_RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > BD_RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
.boot.head :
{
KEEP(*(.loader.head*))
}
}

View file

@ -0,0 +1,248 @@
ENTRY(Reset_Handler)
INCLUDE "export-rom_v03.txt"
MEMORY
{
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 65536
ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560
//RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 16128
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 434176
RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 7936
//BD_RAM (rwx) : ORIGIN = 0x10004000, LENGTH = 442368
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
}
EXTERN(RAM_IMG2_VALID_PATTEN)
EXTERN(InfraStart)
EXTERN(gImage2EntryFun0)
/*EXTERN(VectorTableOverrideRtl8195A)
EXTERN(SYSPlatformInit)*/
SECTIONS
{
__rom_bss_start__ = 0x10000300;
__rom_bss_end__ = 0x10000bc8;
/*
.ram.start.table :
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.start.ram.data*)))
__ram_start_table_end__ = .;
} > ROM_USED_RAM
*/
/* Add . to assign the start address of the section, *
* to prevent the change of the start address by ld doing section alignment */
/* these 4 sections is used by ROM global variable */
/* Don't move them and never add RAM code variable to these sections */
/*---------------------------
.ram_image1.text . :
{
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.infra.ram.data*))
KEEP(*(.timer.ram.data*))
KEEP(*(.cutb.ram.data*))
KEEP(*(.cutc.ram.data*))
KEEP(*(.hal.ram.data*))
__image1_bss_start__ = .;
__image1_bss_end__ = .;
__ram_image1_data_end__ = .;
*(.hal.ram.text*)
*(.infra.ram.text*)
__ram_image1_text_end__ = .;
} > ROM_USED_RAM
*/
/*
.tcm :
{
__tcm_start__ = .;
*(.tcm.heap)
*mem.o (.bss)
*memp.o (.bss)
__tcm_end__ = .;
} > TCM
----------------------------*/
.bootloader :
{
KEEP(*(.loader.data*))
} > ROM_USED_RAM
OVERLAY 0x1FFF0000:
{
.valid
{
*mem.o (.bss*)
*memp.o (.bss*)
*(.tcm.heap)
}
.dummy
{
__ram_image1_text_start__ = .;
__ram_start_table_start__ = .;
KEEP(*(SORT(.start.ram.data*)))
__ram_start_table_end__ = .;
__image1_validate_code__ = .;
KEEP(*(.image1.validate.rodata*))
KEEP(*(.infra.ram.data*))
KEEP(*(.timer.ram.data*))
KEEP(*(.cutb.ram.data*))
KEEP(*(.cutc.ram.data*))
KEEP(*(.hal.ram.data*))
__image1_bss_start__ = .;
.ram_image1.bss$$Base = .;
__image1_bss_end__ = .;
.ram_image1.bss$$Limit = .;
__ram_image1_data_end__ = .;
*(.hal.ram.text*)
*(.infra.ram.text*)
}
} > TCM
.image2.start.table :
{
__ram_image2_text_start__ = .;
__image2_entry_func__ = .;
.image2.start.table1$$Base = .;
*(SORT(.image2.ram.data*))
__image2_validate_code__ = .;
*(.image2.validate.rodata*)
*(.custom.validate.rodata*)
} > BD_RAM
.ram_image2.text :
{
*(.infra.ram.start*)
*(.mon.ram.text*)
*(.hal.flash.text*)
*(.hal.sdrc.text*)
*(.hal.gpio.text*)
*(.fwu.text*)
*(.text*)
*(.sdram.text*)
*(.p2p.text*)
*(.wps.text*)
*(.websocket.text*)
} > BD_RAM
.ram_image2.rodata :
{
*(.rodata*)
*(.fwu.rodata*)
*(.sdram.rodata*)
*(.p2p.rodata*)
*(.wps.rodata*)
*(.websocket.rodata*)
} > BD_RAM
.ram.data :
{
__data_start__ = .;
*(.data*)
*(.sdram.data*)
*(.p2p.data*)
*(.wps.data*)
*(.websocket.data*)
__data_end__ = .;
__ram_image2_text_end__ = .;
} > BD_RAM
.ram.bss :
{
__bss_start__ = .;
.ram.bss$$Base = .;
*(.hal.flash.data*)
*(.hal.sdrc.data*)
*(.hal.gpio.data*)
*(.fwu.data*)
*(.bss*)
*(COMMON)
*(.bdsram.data*)
*(.sdram.bss*)
*(.p2p.bss*)
*(.wps.bss*)
*(.websocket.bss*)
__bss_end__ = .;
.ram.bss$$Limit = .;
} > BD_RAM
.bf_data :
{
__buffer_data_start__ = .;
*(.bfsram.data*)
__buffer_data_end__ = .;
} > BD_RAM
.bf_data2 :
{
__buffer_data_start2__ = .;
__buffer_data_end2__ = .;
} > RECY_RAM
.sdr_text :
{
__sdram_data_start__ = .;
} > SDRAM_RAM
.sdr_rodata :
{
} > SDRAM_RAM
.sdr_data :
{
__sdram_data_end__ = .;
} > SDRAM_RAM
.sdr_bss :
{
__sdram_bss_start__ = .;
__sdram_bss_end__ = .;
} > SDRAM_RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > BD_RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > BD_RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(BD_RAM) + LENGTH(BD_RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
.boot.head :
{
KEEP(*(.loader.head*))
}
}

View file

@ -0,0 +1,46 @@
#include <stdio.h>
#include "hal_api.h"
#if !defined (__ICCARM__)
extern u8 RAM_IMG1_VALID_PATTEN[];
void *tmp = RAM_IMG1_VALID_PATTEN;
#endif
#if defined ( __ICCARM__ )
size_t __write(int Handle, const unsigned char * Buf, size_t Bufsize)
{
int nChars = 0;
/* Check for stdout and stderr
(only necessary if file descriptors are enabled.) */
if (Handle != 1 && Handle != 2)
{
return -1;
}
for (/*Empty */; Bufsize > 0; --Bufsize)
{
DiagPutChar(*Buf++);
++nChars;
}
return nChars;
}
size_t __read(int Handle, unsigned char * Buf, size_t Bufsize)
{
int nChars = 0;
/* Check for stdin
(only necessary if FILE descriptors are enabled) */
if (Handle != 0)
{
return -1;
}
for (/*Empty*/; Bufsize > 0; --Bufsize)
{
int c = DiagGetChar(_FALSE);
if (c < 0)
break;
*(Buf++) = c;
++nChars;
}
return nChars;
}
#endif

View file

@ -0,0 +1,366 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
//#include <stdarg.h>
#include "rtl_consol.h"
#include "osdep_api.h"
#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
#include "freertos_pmu.h"
#endif
#include "tcm_heap.h"
MON_RAM_BSS_SECTION
volatile UART_LOG_CTL UartLogCtl;
MON_RAM_BSS_SECTION
volatile UART_LOG_CTL *pUartLogCtl;
MON_RAM_BSS_SECTION
u8 *ArgvArray[MAX_ARGV];
MON_RAM_BSS_SECTION
UART_LOG_BUF UartLogBuf;
#ifdef CONFIG_UART_LOG_HISTORY
MON_RAM_BSS_SECTION
u8 UartLogHistoryBuf[UART_LOG_HISTORY_LEN][UART_LOG_CMD_BUFLEN];
#endif
_LONG_CALL_
extern u8
UartLogCmdChk(
IN u8 RevData,
IN UART_LOG_CTL *prvUartLogCtl,
IN u8 EchoFlag
);
_LONG_CALL_
extern VOID
ArrayInitialize(
IN u8 *pArrayToInit,
IN u8 ArrayLen,
IN u8 InitValue
);
_LONG_CALL_
extern VOID
UartLogHistoryCmd(
IN u8 RevData,
IN UART_LOG_CTL *prvUartLogCtl,
IN u8 EchoFlag
);
_LONG_CALL_
extern VOID
UartLogCmdExecute(
IN PUART_LOG_CTL pUartLogCtlExe
);
//=================================================
/* Minimum and maximum values a `signed long int' can hold.
(Same as `int'). */
#ifndef __LONG_MAX__
#if defined (__alpha__) || (defined (__sparc__) && defined(__arch64__)) || defined (__sparcv9) || defined (__s390x__)
#define __LONG_MAX__ 9223372036854775807L
#else
#define __LONG_MAX__ 2147483647L
#endif /* __alpha__ || sparc64 */
#endif
#undef LONG_MIN
#define LONG_MIN (-LONG_MAX-1)
#undef LONG_MAX
#define LONG_MAX __LONG_MAX__
/* Maximum value an `unsigned long int' can hold. (Minimum is 0). */
#undef ULONG_MAX
#define ULONG_MAX (LONG_MAX * 2UL + 1)
#ifndef __LONG_LONG_MAX__
#define __LONG_LONG_MAX__ 9223372036854775807LL
#endif
//======================================================
//<Function>: UartLogIrqHandleRam
//<Usage >: To deal with Uart-Log RX IRQ
//<Argus >: VOID
//<Return >: VOID
//<Notes >: NA
//======================================================
MON_RAM_TEXT_SECTION
VOID
UartLogIrqHandleRam
(
VOID * Data
)
{
u8 UartReceiveData = 0;
//For Test
BOOL PullMode = _FALSE;
u32 IrqEn = DiagGetIsrEnReg();
DiagSetIsrEnReg(0);
UartReceiveData = DiagGetChar(PullMode);
if (UartReceiveData == 0) {
goto exit;
}
//KB_ESC chk is for cmd history, it's a special case here.
if (UartReceiveData == KB_ASCII_ESC) {
//4 Esc detection is only valid in the first stage of boot sequence (few seconds)
if (pUartLogCtl->ExecuteEsc != _TRUE)
{
pUartLogCtl->ExecuteEsc = _TRUE;
(*pUartLogCtl).EscSTS = 0;
}
else
{
//4 the input commands are valid only when the task is ready to execute commands
if ((pUartLogCtl->BootRdy == 1)
#ifdef CONFIG_KERNEL
||(pUartLogCtl->TaskRdy == 1)
#endif
)
{
if ((*pUartLogCtl).EscSTS==0)
{
(*pUartLogCtl).EscSTS = 1;
}
}
else
{
(*pUartLogCtl).EscSTS = 0;
}
}
}
else if ((*pUartLogCtl).EscSTS==1){
if (UartReceiveData != KB_ASCII_LBRKT){
(*pUartLogCtl).EscSTS = 0;
}
else{
(*pUartLogCtl).EscSTS = 2;
}
}
else{
if ((*pUartLogCtl).EscSTS==2){
(*pUartLogCtl).EscSTS = 0;
#ifdef CONFIG_UART_LOG_HISTORY
if ((UartReceiveData=='A')|| UartReceiveData=='B'){
UartLogHistoryCmd(UartReceiveData,(UART_LOG_CTL *)pUartLogCtl,1);
}
#endif
}
else{
if (UartLogCmdChk(UartReceiveData,(UART_LOG_CTL *)pUartLogCtl,1)==2)
{
//4 check UartLog buffer to prevent from incorrect access
if (pUartLogCtl->pTmpLogBuf != NULL)
{
pUartLogCtl->ExecuteCmd = _TRUE;
#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
if (pUartLogCtl->TaskRdy)
RtlUpSemaFromISR((_Sema *)&pUartLogCtl->Sema);
#endif
}
else
{
ArrayInitialize((u8 *)pUartLogCtl->pTmpLogBuf->UARTLogBuf, UART_LOG_CMD_BUFLEN, '\0');
}
}
}
}
exit:
DiagSetIsrEnReg(IrqEn);
}
MON_RAM_TEXT_SECTION
VOID
RtlConsolInitRam(
IN u32 Boot,
IN u32 TBLSz,
IN VOID *pTBL
)
{
UartLogBuf.BufCount = 0;
ArrayInitialize(&UartLogBuf.UARTLogBuf[0],UART_LOG_CMD_BUFLEN,'\0');
pUartLogCtl = &UartLogCtl;
pUartLogCtl->NewIdx = 0;
pUartLogCtl->SeeIdx = 0;
pUartLogCtl->RevdNo = 0;
pUartLogCtl->EscSTS = 0;
pUartLogCtl->BootRdy = 0;
pUartLogCtl->pTmpLogBuf = &UartLogBuf;
#ifdef CONFIG_UART_LOG_HISTORY
pUartLogCtl->CRSTS = 0;
pUartLogCtl->pHistoryBuf = &UartLogHistoryBuf[0];
#endif
pUartLogCtl->pfINPUT = (VOID*)&DiagPrintf;
pUartLogCtl->pCmdTbl = (PCOMMAND_TABLE) pTBL;
pUartLogCtl->CmdTblSz = TBLSz;
#ifdef CONFIG_KERNEL
pUartLogCtl->TaskRdy = 0;
#endif
//executing boot sequence
if (Boot == ROM_STAGE)
{
pUartLogCtl->ExecuteCmd = _FALSE;
pUartLogCtl->ExecuteEsc = _FALSE;
}
else
{
pUartLogCtl->ExecuteCmd = _FALSE;
pUartLogCtl->ExecuteEsc= _TRUE; //don't check Esc anymore
#if defined(CONFIG_KERNEL)
/* Create a Semaphone */
RtlInitSema((_Sema*)&(pUartLogCtl->Sema), 0);
pUartLogCtl->TaskRdy = 0;
#ifdef PLATFORM_FREERTOS
#define LOGUART_STACK_SIZE 200 //USE_MIN_STACK_SIZE modify from 512 to 128
#if CONFIG_USE_TCM_HEAP
{
int ret = 0;
void *stack_addr = tcm_heap_malloc(LOGUART_STACK_SIZE*sizeof(int));
//void *stack_addr = rtw_malloc(stack_size*sizeof(int));
if(stack_addr == NULL){
DiagPrintf("Out of TCM heap in \"LOGUART_TASK\" ");
}
ret = xTaskGenericCreate(
RtlConsolTaskRam,
(const char *)"log_uart",
LOGUART_STACK_SIZE,
NULL,
tskIDLE_PRIORITY + 5 + PRIORITIE_OFFSET, // +5
NULL,
stack_addr,
NULL);
if (pdTRUE != ret)
{
DiagPrintf("Create Log UART Task Err!!\n");
}
}
#else
if (pdTRUE != xTaskCreate( RtlConsolTaskRam, (const signed char * const)"log_uart", LOGUART_STACK_SIZE, NULL, tskIDLE_PRIORITY + 5 + PRIORITIE_OFFSET, NULL))
{
DiagPrintf("Create Log UART Task Err!!\n");
}
#endif
#endif
#endif
}
CONSOLE_8195A();
}
#if SUPPORT_LOG_SERVICE
extern char log_buf[LOG_SERVICE_BUFLEN];
extern xSemaphoreHandle log_rx_interrupt_sema;
#endif
//======================================================
void console_cmd_exec(PUART_LOG_CTL pUartLogCtlExe)
{
u8 CmdCnt = 0;
u8 argc = 0;
u8 **argv;
//u32 CmdNum;
PUART_LOG_BUF pUartLogBuf = pUartLogCtlExe->pTmpLogBuf;
#if SUPPORT_LOG_SERVICE
strncpy(log_buf, (const u8*)&(*pUartLogBuf).UARTLogBuf[0], LOG_SERVICE_BUFLEN-1);
#endif
argc = GetArgc((const u8*)&((*pUartLogBuf).UARTLogBuf[0]));
argv = GetArgv((const u8*)&((*pUartLogBuf).UARTLogBuf[0]));
if(argc > 0){
#if SUPPORT_LOG_SERVICE
// if(log_handler(argv[0]) == NULL)
// legency_interactive_handler(argc, argv);
RtlUpSema((_Sema *)&log_rx_interrupt_sema);
#endif
ArrayInitialize(argv[0], sizeof(argv[0]) ,0);
}else{
#if defined(configUSE_WAKELOCK_PMU) && (configUSE_WAKELOCK_PMU == 1)
acquire_wakelock(WAKELOCK_LOGUART);
#endif
CONSOLE_8195A(); // for null command
}
(*pUartLogBuf).BufCount = 0;
ArrayInitialize(&(*pUartLogBuf).UARTLogBuf[0], UART_LOG_CMD_BUFLEN, '\0');
}
//======================================================
// overload original RtlConsolTaskRam
MON_RAM_TEXT_SECTION
VOID
RtlConsolTaskRam(
VOID *Data
)
{
#if SUPPORT_LOG_SERVICE
log_service_init();
#endif
//4 Set this for UartLog check cmd history
#ifdef CONFIG_KERNEL
pUartLogCtl->TaskRdy = 1;
#endif
#ifndef CONFIG_KERNEL
pUartLogCtl->BootRdy = 1;
#endif
do{
#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
RtlDownSema((_Sema *)&pUartLogCtl->Sema);
#endif
if (pUartLogCtl->ExecuteCmd) {
// Add command handler here
console_cmd_exec((PUART_LOG_CTL)pUartLogCtl);
//UartLogCmdExecute((PUART_LOG_CTL)pUartLogCtl);
pUartLogCtl->ExecuteCmd = _FALSE;
}
}while(1);
}
extern void * UartLogRomCmdTable;
//======================================================
void console_init(void)
{
IRQ_HANDLE UartIrqHandle;
//4 Register Log Uart Callback function
UartIrqHandle.Data = 0;//(u32)&UartAdapter;
UartIrqHandle.IrqNum = UART_LOG_IRQ;
UartIrqHandle.IrqFun = (IRQ_FUN) UartLogIrqHandleRam;
UartIrqHandle.Priority = 0; // ??
//4 Register Isr handle
InterruptUnRegister(&UartIrqHandle);
InterruptRegister(&UartIrqHandle);
#if !TASK_SCHEDULER_DISABLED
// RtlConsolInitRam((u32)ROM_STAGE,(u32)0,(VOID*)NULL);
RtlConsolInitRam((u32)RAM_STAGE,(u32)6,(VOID*)UartLogRomCmdTable); // ); NULL);
#else
RtlConsolInitRam((u32)RAM_STAGE,(u32)6,(VOID*)UartLogRomCmdTable); // ); NULL);
// RtlConsolInitRam((u32)ROM_STAGE,(u32)0,(VOID*)NULL);
#endif
}

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _RTK_CONSOL_H_
#define _RTK_CONSOL_H_
/*
* Include user defined options first. Anything not defined in these files
* will be set to standard values. Override anything you dont like!
*/
#if defined(CONFIG_PLATFORM_8195A) || defined(CONFIG_PLATFORM_8711B)
#include "platform_opts.h"
#endif
#include "osdep_api.h"
#include "hal_diag.h"
#define CONSOLE_PREFIX "#"
//Log UART
//UART_LOG_CMD_BUFLEN: only 126 bytes could be used for keeping input
// cmd, the last byte is for string end ('\0').
#define UART_LOG_CMD_BUFLEN 127
#define MAX_ARGV 10
typedef u32 (*ECHOFUNC)(IN u8*,...); //UART LOG echo-function type.
typedef struct _UART_LOG_BUF_ {
u8 BufCount; //record the input cmd char number.
u8 UARTLogBuf[UART_LOG_CMD_BUFLEN]; //record the input command.
} UART_LOG_BUF, *PUART_LOG_BUF;
typedef struct _UART_LOG_CTL_ {
u8 NewIdx; //+0x00
u8 SeeIdx; //+0x01
u8 RevdNo; //+0x02
u8 EscSTS; //+0x03
u8 ExecuteCmd; //+0x04
u8 ExecuteEsc; //+0x05
u8 BootRdy; //+0x06
u8 Resvd; //+0x07
PUART_LOG_BUF pTmpLogBuf;
VOID *pfINPUT;
PCOMMAND_TABLE pCmdTbl;
u32 CmdTblSz;
#ifdef CONFIG_UART_LOG_HISTORY
u32 CRSTS;
#endif
#ifdef CONFIG_UART_LOG_HISTORY
u8 (*pHistoryBuf)[UART_LOG_CMD_BUFLEN];
#endif
#ifdef CONFIG_KERNEL
u32 TaskRdy;
_Sema Sema;
#else
// Since ROM code will reference this typedef, so keep the typedef same size
u32 TaskRdy;
void *Sema;
#endif
} UART_LOG_CTL, *PUART_LOG_CTL;
#define KB_ASCII_NUL 0x00
#define KB_ASCII_BS 0x08
#define KB_ASCII_TAB 0x09
#define KB_ASCII_LF 0x0A
#define KB_ASCII_CR 0x0D
#define KB_ASCII_ESC 0x1B
#define KB_ASCII_SP 0x20
#define KB_ASCII_BS_7F 0x7F
#define KB_ASCII_LBRKT 0x5B //[
#define KB_SPACENO_TAB 1
#ifdef CONFIG_UART_LOG_HISTORY
#define UART_LOG_HISTORY_LEN 5
#endif
#if CONFIG_DEBUG_LOG > 0
#define _ConsolePrint DiagPrintf
#else
#define _ConsolePrint
#endif
#ifndef CONSOLE_PREFIX
#define CONSOLE_PREFIX "<RTL8195A>"
#endif
#define CONSOLE_8195A(...) do {\
_ConsolePrint("\r"CONSOLE_PREFIX __VA_ARGS__);\
}while(0)
_LONG_CALL_ VOID
RtlConsolInit(
IN u32 Boot,
IN u32 TBLSz,
IN VOID *pTBL
);
#if defined(CONFIG_KERNEL)
_LONG_CALL_ VOID
RtlConsolTaskRam(
VOID *Data
);
#endif
_LONG_CALL_ VOID
RtlConsolTaskRom(
VOID *Data
);
_LONG_CALL_ u32
Strtoul(
IN const u8 *nptr,
IN u8 **endptr,
IN u32 base
);
void console_init(void);
extern _LONG_CALL_ROM_ int GetArgc(const u8 *string);
extern _LONG_CALL_ROM_ u8** GetArgv(const u8 *string);
#endif //_RTK_CONSOL_H_

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/*
* rtl_lib.h
*
* Definitions for RTL library functions
*/
#ifndef _RTL_LIB_ROM_H_
#define _RTL_LIB_ROM_H_
#include <basic_types.h>
#include <diag.h>
#include <reent.h>
#include "../libc/rom/string/rom_libc_string.h"
#include "../libgloss/rtl8195a/rom/rom_libgloss_retarget.h"
#ifndef _PTR
#define _PTR void *
#endif
#ifndef _AND
#define _AND ,
#endif
#ifndef _NOARGS
#define _NOARGS void
#endif
#ifndef _CONST
#define _CONST const
#endif
#ifndef _VOLATILE
#define _VOLATILE volatile
#endif
#ifndef _SIGNED
#define _SIGNED signed
#endif
#ifndef _DOTS
#define _DOTS , ...
#endif
#ifndef _VOID
#define _VOID void
#endif
//
// RTL library functions in ROM
//
#define __rtl_memset __rtl_memset_v1_00
#define __rtl_memchr __rtl_memchr_v1_00
#define __rtl_memmove __rtl_memmove_v1_00
#define __rtl_strcmp __rtl_strcmp_v1_00
#define __rtl_memcpy __rtl_memcpy_v1_00
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
extern _LONG_CALL_ void * __rtl_memchr_v1_00(const void * src_void , int c , size_t length);
extern _LONG_CALL_ void * __rtl_memmove_v1_00( void * dst_void , const void * src_void , size_t length);
extern _LONG_CALL_ int __rtl_strcmp_v1_00(const char *s1 , const char *s2);
extern _LONG_CALL_ void * __rtl_memcpy_v1_00(void * __restrict dst0 , const void * __restrict src0 , size_t len0);
//
// rtl eabi functions
//
#define __rtl_itod __rtl_itod_v1_00
#define __rtl_dtoi __rtl_dtoi_v1_00
#define __rtl_uitof __rtl_uitof_v1_00
#define __rtl_uitod __rtl_uitod_v1_00
#define __rtl_dcmpeq __rtl_dcmpeq_v1_00
#define __rtl_dcmplt __rtl_dcmplt_v1_00
#define __rtl_dcmpgt __rtl_dcmpgt_v1_00
#define __rtl_dadd __rtl_dadd_v1_00
#define __rtl_dsub __rtl_dsub_v1_00
#define __rtl_dmul __rtl_dmul_v1_00
#define __rtl_ddiv __rtl_ddiv_v1_00
extern _LONG_CALL_ double __rtl_itod_v1_00(int lval);
extern _LONG_CALL_ int __rtl_dtoi_v1_00(double d);
extern _LONG_CALL_ float __rtl_uitof_v1_00(unsigned int lval);
extern _LONG_CALL_ double __rtl_uitod_v1_00(unsigned int lval);
extern _LONG_CALL_ int __rtl_dcmpeq_v1_00(double a, double b);
extern _LONG_CALL_ int __rtl_dcmplt_v1_00(double a, double b);
extern _LONG_CALL_ int __rtl_dcmpgt_v1_00(double a, double b);
extern _LONG_CALL_ double __rtl_dadd_v1_00(double a, double b);
extern _LONG_CALL_ double __rtl_dsub_v1_00(double a, double b);
extern _LONG_CALL_ double __rtl_dmul_v1_00(double a, double b);
extern _LONG_CALL_ double __rtl_ddiv_v1_00(double a, double b);
//
// mprec
//
#include <reent.h>
typedef struct _Bigint _Bigint;
#define __rtl_Balloc __rtl_Balloc_v1_00
#define __rtl_Bfree __rtl_Bfree_v1_00
#define __rtl_d2b __rtl_d2b_v1_00
#define __rtl_i2b __rtl_i2b_v1_00
#define __rtl_pow5mult __rtl_pow5mult_v1_00
#define __rtl_multadd __rtl_multadd_v1_00
#define __rtl_mult __rtl_mult_v1_00
#define __rtl_hi0bits __rtl_hi0bits_v1_00
#define __rtl_lshift __rtl_lshift_v1_00
#define __rtl_cmp __rtl_cmp_v1_00
#define __rtl_diff __rtl_diff_v1_00
extern _LONG_CALL_ _Bigint * __rtl_Balloc_v1_00(struct _reent *ptr, int k);
extern _LONG_CALL_ void __rtl_Bfree_v1_00(struct _reent *ptr, _Bigint * v);
extern _LONG_CALL_ _Bigint * __rtl_d2b_v1_00(struct _reent * ptr, double _d, int *e, int *bits);
extern _LONG_CALL_ _Bigint * __rtl_i2b_v1_00(struct _reent *ptr, int i );
extern _LONG_CALL_ _Bigint * __rtl_pow5mult_v1_00(struct _reent * ptr, _Bigint *b, int k);
extern _LONG_CALL_ _Bigint * __rtl_multadd_v1_00(struct _reent *ptr, _Bigint * b, int m, int a);
extern _LONG_CALL_ _Bigint * __rtl_mult_v1_00(struct _reent *ptr, _Bigint *a, _Bigint *b);
extern _LONG_CALL_ int __rtl_hi0bits_v1_00(register __ULong x);
extern _LONG_CALL_ _Bigint *__rtl_lshift_v1_00(struct _reent *ptr, _Bigint *b, int k);
extern _LONG_CALL_ int __rtl_cmp_v1_00(_Bigint *a, _Bigint *b);
extern _LONG_CALL_ _Bigint *__rtl_diff_v1_00(struct _reent* ptr, _Bigint *a, _Bigint *b);
//
// dtoa
//
#define __rtl_dtoa_r __rtl_dtoa_r_v1_00
extern char * __rtl_dtoa_r_v1_00(struct _reent *ptr, double _d, int mode, int ndigits, int *decpt, int *sign, char **rve);
//
// mallocr
//
#include <sys/config.h>
#include <reent.h>
#define __rom_mallocr_init __rom_mallocr_init_v1_00
#define __rtl_calloc_r __rtl_calloc_r_v1_00
#define __rtl_cfree_r __rtl_cfree_r_v1_00
#define __rtl_malloc_r __rtl_malloc_r_v1_00
#define __rtl_free_r __rtl_free_r_v1_00
#define __rtl_realloc_r __rtl_realloc_r_v1_00
#define __rtl_memalign_r __rtl_memalign_r_v1_00
#define __rtl_valloc_r __rtl_valloc_r_v1_00
#define __rtl_pvalloc_r __rtl_pvalloc_r_v1_00
extern _LONG_CALL_ void __rom_mallocr_init_v1_00(void);
#define RARG struct _reent *reent_ptr,
extern _LONG_CALL_ void* __rtl_calloc_r_v1_00(RARG size_t n, size_t elem_size);
extern _LONG_CALL_ void __rtl_cfree_r_v1_00(void *mem);
extern _LONG_CALL_ void* __rtl_malloc_r_v1_00(RARG size_t bytes);
extern _LONG_CALL_ void __rtl_free_r_v1_00(RARG void* mem);
extern _LONG_CALL_ void* __rtl_realloc_r_v1_00(RARG void* oldmem, size_t bytes);
extern _LONG_CALL_ void* __rtl_memalign_r_v1_00(RARG size_t alignment, size_t bytes);
extern _LONG_CALL_ void* __rtl_valloc_r_v1_00(RARG size_t bytes);
extern _LONG_CALL_ void* __rtl_pvalloc_r_v1_00(RARG size_t bytes);
//
// stdio
//
extern int __rtl_errno;
#ifndef _READ_WRITE_RETURN_TYPE
#define _READ_WRITE_RETURN_TYPE _ssize_t
#endif
#ifndef _READ_WRITE_BUFSIZE_TYPE
#define _READ_WRITE_BUFSIZE_TYPE int
#endif
#define __rtl_sread __rtl_sread_v1_00
#define __rtl_swrite __rtl_swrite_v1_00
#define __rtl_seofread __rtl_seofread_v1_00
#define __rtl_sseek __rtl_sseek_v1_00
#define __rtl_sclose __rtl_sclose_v1_00
#define __rtl_sbrk_r __rtl_sbrk_r_v1_00
extern _LONG_CALL_ _READ_WRITE_RETURN_TYPE __rtl_sread_v1_00(
struct _reent *ptr,
void *cookie,
char *buf,
_READ_WRITE_BUFSIZE_TYPE n);
extern _LONG_CALL_ _READ_WRITE_RETURN_TYPE __rtl_swrite_v1_00(
struct _reent *ptr,
void *cookie,
char const *buf,
_READ_WRITE_BUFSIZE_TYPE n);
extern _LONG_CALL_ _READ_WRITE_RETURN_TYPE __rtl_seofread_v1_00(
struct _reent *_ptr,
_PTR cookie,
char *buf,
_READ_WRITE_BUFSIZE_TYPE len);
extern _LONG_CALL_ _fpos_t __rtl_sseek_v1_00(
struct _reent *ptr _AND
void *cookie _AND
_fpos_t offset _AND
int whence);
extern _LONG_CALL_ int __rtl_sclose_v1_00(
struct _reent *ptr _AND
void *cookie);
extern _LONG_CALL_ void * __rtl_sbrk_r_v1_00(
struct _reent *ptr,
ptrdiff_t incr);
//
// vfprintf
//
#include <stdio.h>
#include <stdarg.h>
#define __rtl_vfprintf_r __rtl_vfprintf_r_v1_00
extern _LONG_CALL_ int __rtl_vfprintf_r_v1_00(struct _reent *, FILE *, const char *, va_list);
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#define __rtl_fflush_r __rtl_fflush_r_v1_00
extern _LONG_CALL_ int __rtl_fflush_r_v1_00(struct _reent *ptr, register FILE * fp);
#endif
#endif /* _RTL_LIB_ROM_H_ */

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/*
* rtl_lib.h
*
* Definitions for RTL library functions
*/
#ifndef _RTL_LIB_H_
#define _RTL_LIB_H_
#include <basic_types.h>
#include <diag.h>
extern int __rtl_errno;
void init_rom_libgloss_ram_map(void);
//
// RTL library functions for Libc::stdio
//
extern int rtl_printf(IN const char* fmt, ...);
extern int rtl_vprintf(const char *fmt, void *param);
extern int rtl_sprintf(char* str, const char* fmt, ...);
extern int rtl_snprintf(char* str, size_t size, const char* fmt, ...);
extern int rtl_vsnprintf(char *str, size_t size, const char *fmt, void *param);
//
// RTL library functions for string
//
extern void * rtl_memchr(const void * src_void , int c , size_t length);
extern int rtl_memcmp(const void * m1 , const void * m2 , size_t n);
extern void * rtl_memcpy(void * dst0 , const void * src0 , size_t len0);
extern void * rtl_memmove( void * dst_void , const void * src_void , size_t length);
extern void * rtl_memset(void * m , int c , size_t n);
extern char * rtl_strcat(char * s1 , const char * s2);
extern char * rtl_strchr(const char *s1 , int i);
extern int rtl_strcmp(const char *s1 , const char *s2);
extern char* rtl_strcpy(char *dst0 , const char *src0);
extern size_t rtl_strlen(const char *str);
extern char * rtl_strncat(char * s1 , const char * s2 , size_t n);
extern int rtl_strncmp(const char *s1 , const char *s2 , size_t n);
extern char * rtl_strncpy(char * dst0 , const char * src0 , size_t count);
extern char * rtl_strstr(const char *searchee , const char *lookfor);
extern char * rtl_strsep(char **source_ptr , const char *delim);
extern char * rtl_strtok(char * s , const char * delim);
//
// RTL library functions for math
//
extern double rtl_fabs(double);
extern float rtl_fabsf(float a);
extern float rtl_cos_f32(float a);
extern float rtl_sin_f32(float a);
extern float rtl_fadd(float a, float b);
extern float rtl_fsub(float a, float b);
extern float rtl_fmul(float a, float b);
extern float rtl_fdiv(float a, float b);
extern int rtl_fcmplt(float a, float b);
extern int rtl_fcmpgt(float a, float b);
//
// RTL eabi functions
extern double rtl_ftod(float f);
extern double rtl_ddiv(double a, double b);
//
// Macro Library Functions
//
typedef union
{
float value;
u32 word;
} ieee_float_shape_type;
/* Get a 32 bit int from a float. */
#define GET_FLOAT_WORD(i,d) \
do { \
ieee_float_shape_type gf_u; \
gf_u.value = (d); \
(i) = gf_u.word; \
} while (0)
/* Set a float from a 32 bit int. */
#define SET_FLOAT_WORD(d,i) \
do { \
ieee_float_shape_type sf_u; \
sf_u.word = (i); \
(d) = sf_u.value; \
} while (0)
static inline
float rtl_nanf(void)
{
float x;
SET_FLOAT_WORD(x,0x7fc00000);
return x;
}
//
// Library Test functions
//
extern int rtl_lib_test(IN u16 argc, IN u8 *argv[]);
extern int rtl_math_test(IN u16 argc, IN u8 *argv[]);
extern int rtl_string_test(IN u16 argc, IN u8 *argv[]);
//
// Macro functions
//
#undef dbg_printf
#define dbg_printf(fmt, args...) \
rtl_printf("%s():%d : " fmt "\n", __FUNCTION__, __LINE__, ##args);
#undef err_printf
#define err_printf(fmt, args...) \
rtl_printf("%s():%d : " fmt "\n", __FUNCTION__, __LINE__, ##args);
#endif /* _RTL_LIB_H_ */