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pvvx 2016-11-09 03:56:41 +03:00
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389
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_adc.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "platform_autoconf.h"
#include "diag.h"
#include "rtl8195a_adc.h"
#include "hal_adc.h"
#ifdef CONFIG_ADC_EN
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCInit8195a(
IN VOID *Data
)
{
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
u32 AdcTempDat;
u8 AdcTempIdx = pHalAdcInitData->ADCIdx;
/* Enable ADC power cut */
/*
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat |= BIT_ADC_PWR_AUTO;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
*/
/* ADC Control register set-up*/
AdcTempDat = 0;
AdcTempDat |= (BIT_CTRL_ADC_COMP_ONLY(pHalAdcInitData->ADCCompOnly) |
BIT_CTRL_ADC_ONESHOT(pHalAdcInitData->ADCOneShotEn) |
BIT_CTRL_ADC_OVERWRITE(pHalAdcInitData->ADCOverWREn) |
BIT_CTRL_ADC_ENDIAN(pHalAdcInitData->ADCEndian) |
BIT_CTRL_ADC_BURST_SIZE(pHalAdcInitData->ADCBurstSz) |
BIT_CTRL_ADC_THRESHOLD(pHalAdcInitData->ADCOneShotTD) |
BIT_CTRL_ADC_DBG_SEL(pHalAdcInitData->ADCDbgSel));
HAL_ADC_WRITE32(REG_ADC_CONTROL,AdcTempDat);
DBG_8195A_ADC_LVL(HAL_ADC_LVL,"REG_ADC_CONTROL:%x\n", HAL_ADC_READ32(REG_ADC_CONTROL));
/* ADC compare value and compare method setting*/
switch (AdcTempIdx) {
case ADC0_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
AdcTempDat &= ~(BIT_ADC_COMP_TH_0(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_0(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
break;
case ADC1_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
AdcTempDat &= ~(BIT_ADC_COMP_TH_1(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_1(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
break;
case ADC2_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
AdcTempDat &= ~(BIT_ADC_COMP_TH_2(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_2(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
break;
case ADC3_SEL:
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
AdcTempDat &= ~(BIT_ADC_COMP_TH_3(0xFFFF));
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_3(pHalAdcInitData->ADCCompTD);
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
break;
default:
return _EXIT_FAILURE;
}
/* ADC compare mode setting */
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_SET);
AdcTempDat &= (~(0x01 << pHalAdcInitData->ADCIdx));
AdcTempDat |= (BIT_CTRL_ADC_COMP_0_EN(pHalAdcInitData->ADCCompCtrl) <<
pHalAdcInitData->ADCIdx);
HAL_ADC_WRITE32(REG_ADC_COMP_SET, AdcTempDat);
/* ADC audio mode set-up */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
AdcTempDat &= ~(BIT_ADC_AUDIO_EN);
AdcTempDat |= BIT_CTRL_ADC_AUDIO_EN(pHalAdcInitData->ADCAudioEn);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
/* ADC enable manually setting */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
AdcTempDat &= ~(BIT_ADC_EN_MANUAL);
AdcTempDat |= BIT_CTRL_ADC_EN_MANUAL(pHalAdcInitData->ADCEnManul);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
/* ADC analog parameter 0 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
//AdcTempDat |= (BIT0);
if (pHalAdcInitData->ADCInInput == 1){
AdcTempDat &= (~BIT14);
}
else {
AdcTempDat |= (BIT14);
}
AdcTempDat &= (~(BIT3|BIT2));
/* Adjust VCM for C-Cut*/
#ifdef CONFIG_CHIP_C_CUT
AdcTempDat |= (BIT22);
#endif
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
/* ADC analog parameter 1 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
AdcTempDat &= (~BIT1);
AdcTempDat |= (BIT2|BIT0);
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
DBG_ADC_INFO("AD1:%x\n", AdcTempDat);
/* ADC analog parameter 2 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
AdcTempDat = 0x67884400;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD2, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
/* ADC analog parameter 3 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
AdcTempDat = 0x77780039;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD3, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
/* ADC analog parameter 4 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
AdcTempDat = 0x0004d501;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD4, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
/* ADC analog parameter 5 */
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
AdcTempDat = 0x1E010800;
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD5, AdcTempDat);
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCDeInit8195a(
IN VOID *Data
)
{
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat &= ~(BIT_ADC_PWR_AUTO);
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCEnableRtl8195a(
IN VOID *Data
){
//PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
u32 AdcTempDat;
DBG_ADC_INFO("HalADCEnableRtl8195a\n");
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
AdcTempDat &= (~BIT_ADC_PWR_AUTO);
AdcTempDat |= 0x02;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat |= 0x04;
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat &= (~0x08);
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER);
DBG_ADC_INFO("HalADCEnableRtl8195a, power reg:%x\n",AdcTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalADCIntrCtrl8195a(
IN VOID *Data
){
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
HAL_ADC_WRITE32(REG_ADC_INTR_EN, pHalAdcInitData->ADCIntrMSK);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReceiveRtl8195a
//
// Description:
// Directly read one data byte a I2C data fifo.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The first data fifo content.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u32
HalADCReceiveRtl8195a(
IN VOID *Data
){
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(REG_ADC_FIFO_READ);
return (AdcTempDat);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReadRegRtl8195a
//
// Description:
// Directly read a I2C register according to the register offset.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
// [in] I2CReg -
// The I2C register offset.
//
// Return:
// The register content in u32 format.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u32
HalADCReadRegRtl8195a(
IN VOID *Data,
IN u8 I2CReg
){
u32 AdcTempDat;
AdcTempDat = HAL_ADC_READ32(I2CReg);
return (AdcTempDat);
}
#endif // CONFIG_ADC_EN

269
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_dac.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_dac.h"
#include "hal_dac.h"
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalDACInit8195a
//
// Description:
// To initialize DAC module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The DAC parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-15.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACInit8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
u8 DacTempIdx = pHalDacInitData->DACIdx;
/* Enable DAC power cut */
DacTempDat = HAL_DAC_READ32(0, REG_DAC_PWR_CTRL);
DacTempDat |= BIT_DAC_PWR_AUTO;
HAL_DAC_WRITE32(0, REG_DAC_PWR_CTRL, DacTempDat);
/* Disable DAC module first */
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, 0);
/* Setup DAC module */
DacTempDat = 0;
DacTempDat |= (BIT_CTRL_DAC_SPEED(pHalDacInitData->DACDataRate) |
BIT_CTRL_DAC_ENDIAN(pHalDacInitData->DACEndian) |
BIT_CTRL_DAC_FILTER_SETTLE(pHalDacInitData->DACFilterSet) |
BIT_CTRL_DAC_BURST_SIZE(pHalDacInitData->DACBurstSz) |
BIT_CTRL_DAC_DBG_SEL(pHalDacInitData->DACDbgSel) |
BIT_CTRL_DAC_DSC_DBG_SEL(pHalDacInitData->DACDscDbgSel) |
BIT_CTRL_DAC_BYPASS_DSC(pHalDacInitData->DACBPDsc) |
BIT_CTRL_DAC_DELTA_SIGMA(pHalDacInitData->DACDeltaSig));
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACDeInit8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
DacTempDat = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL);
DacTempDat &= (~BIT_DAC_FIFO_EN);
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL ,DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACEnableRtl8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
u32 DacTempDat;
u8 DacTempIdx = pHalDacInitData->DACIdx;
DacTempDat = HAL_DAC_READ32(DacTempIdx, REG_DAC_CTRL);
DacTempDat &= (~BIT_DAC_FIFO_EN);
DacTempDat |= BIT_CTRL_DAC_FIFO_EN(pHalDacInitData->DACEn);
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CIntrCtrl8195a
//
// Description:
// Modify the I2C interrupt mask according to the given value
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
RTK_STATUS
HalDACIntrCtrl8195a(
IN VOID *Data
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, pHalDacInitData->DACIntrMSK);
return _EXIT_SUCCESS;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CReceiveRtl8195a
//
// Description:
// Directly read one data byte a I2C data fifo.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The first data fifo content.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
u8
HalDACSendRtl8195a(
IN VOID *Data
){
return (0);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalDACReadRegRtl8195a
//
// Description:
//
//
// Arguments:
// [in] VOID *Data -
// The DAC parameter data struct.
// [in] I2CReg -
// The DAC register offset.
//
// Return:
// The DAC register content in u32 format.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-15.
//
//---------------------------------------------------------------------------------------------------
u32
HalDACReadRegRtl8195a(
IN VOID *Data,
IN u8 I2CReg
){
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
//DBG_8195A_DAC("dac read reg idx:%x\n",pHalDacInitData->DACIdx);
//DBG_8195A_DAC("dac read reg offset:%x\n",I2CReg);
return (u32)HAL_DAC_READ32(pHalDacInitData->DACIdx, I2CReg);
}

295
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_gdma.h"
#include "hal_gdma.h"
#ifdef CONFIG_GDMA_EN
#ifndef CONFIG_CHIP_E_CUT
BOOL
HalGdmaChBlockSetingRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pGdmaChLli;
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 ChEn = pHalGdmaAdapter->ChEn;
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
u8 PendingIsrIndex;
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
HalGdmaChDisRtl8195a(Data);
}
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
u32 PendRaw, PendStstus;
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
//4 Clear Pending Isr
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
(PendStstus & (GdmaChIsrBitmap))
);
}
}
//4 Fill in SARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChSar)
);
//4 Fill in DARx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
(pHalGdmaAdapter->ChDar)
);
//4 3) Process CTLx
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
//4 Clear Config low register bits
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
BIT_INVC_CTLX_LO_DINC &
BIT_INVC_CTLX_LO_SINC &
BIT_INVC_CTLX_LO_DEST_MSIZE &
BIT_INVC_CTLX_LO_SRC_MSIZE &
BIT_INVC_CTLX_LO_TT_FC &
BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
//4 Clear Config upper register bits
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
BIT_INVC_CTLX_UP_DONE);
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
CtlxLow;
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
CtlxUp;
//4 Fill in CTLx register
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
CtlxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
CtlxUp
);
//4 4) Program CFGx
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
BIT_INVC_CFGX_LO_CH_SUSP &
BIT_INVC_CFGX_LO_HS_SEL_DST &
BIT_INVC_CFGX_LO_HS_SEL_SRC &
BIT_INVC_CFGX_LO_LOCK_CH_L &
BIT_INVC_CFGX_LO_LOCK_B_L &
BIT_INVC_CFGX_LO_LOCK_CH &
BIT_INVC_CFGX_LO_LOCK_B &
BIT_INVC_CFGX_LO_RELOAD_SRC &
BIT_INVC_CFGX_LO_RELOAD_DST);
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
BIT_INVC_CFGX_UP_DS_UPD_EN &
BIT_INVC_CFGX_UP_SS_UPD_EN &
BIT_INVC_CFGX_UP_SRC_PER &
BIT_INVC_CFGX_UP_DEST_PER);
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
CfgxLow;
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
CfgxUp;
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
CfgxUp
);
//4 Check 4 Bytes Alignment
if ((u32)(pLliEle) & 0x3) {
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
pHalGdmaAdapter->pLli);
return _FALSE;
}
HAL_GDMAX_WRITE32(GdmaIndex,
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
pLliEle
);
//4 Update the first llp0
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
while (MultiBlockCount > 1) {
MultiBlockCount--;
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
pLliEle = pGdmaChLli->pLliEle;
if (NULL == pLliEle) {
DBG_GDMA_ERR("pLliEle Null Point!!!!!\n");
return _FALSE;
}
//4 Clear the last element llp enable bit
if (1 == MultiBlockCount) {
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
BIT_INVC_CTLX_LO_LLP_SRC_EN);
}
}
//4 Update block size for transfer
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
//4 Update tje Lli and Block size list point to next llp
pGdmaChLli = pGdmaChLli->pNextLli;
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
//4 Updatethe Llpx context
pLliEle->CtlxLow = CtlxLow;
pLliEle->CtlxUp = CtlxUp;
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
}
return _TRUE;
}
u32
HalGdmaQueryDArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
u32
HalGdmaQuerySArRtl8195a(
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
u8 ChNum = pHalGdmaAdapter->ChNum;
u32 dar;
dar = HAL_GDMAX_READ32(GdmaIndex,
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
return dar;
}
BOOL
HalGdmaQueryChEnRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
return 1;
} else {
return 0;
}
}
#endif
#endif // CONFIG_GDMA_EN

56
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gpio.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_gpio.h"
#include "rtl8195a_gpio.h"
#include "gpio_irq_api.h"
#ifdef CONFIG_GPIO_EN
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
/**
* @brief Clear the pending interrupt of a specified pin
*
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
*
* @retval None
*/
HAL_Status
HAL_GPIO_ClearISR_8195a(
HAL_GPIO_PIN *GPIO_Pin
)
{
u8 port_num;
u8 pin_num;
HAL_GPIO_PIN_MODE pin_mode;
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
pin_mode = GPIO_Pin->pin_mode;
if ((pin_mode & HAL_GPIO_PIN_INT_MODE)==0 || (port_num != GPIO_PORT_A)) {
DBG_GPIO_WARN("HAL_GPIO_ClearISR_8195a: This pin(%x:%x) is'nt an interrupt pin\n", GPIO_Pin->pin_name, GPIO_Pin->pin_mode);
return HAL_ERR_PARA;
}
if (GPIO_Lock() != HAL_OK) {
return HAL_BUSY;
}
// Clear pending interrupt before unmask it
HAL_WRITE32(GPIO_REG_BASE, GPIO_PORTA_EOI, (1<<pin_num));
GPIO_UnLock();
return HAL_OK;
}
#endif // CONFIG_GPIO_EN

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#ifdef CONFIG_I2C_EN
/* Used only for A~C Version */
#ifndef CONFIG_CHIP_E_CUT
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CSendRtl8195a
//
// Description:
// Send one byte to the I2C internal fifo, it will generate START and STOP bit
// automatically.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// _EXIT_SUCCESS if the sending succeeded.
// _EXIT_FAILURE if the sending failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CSendRtl8195a_Patch(
IN VOID *Data
){
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 I2CIdx = pHalI2CInitData->I2CIdx;
u8 *pDat = pHalI2CInitData->I2CRWData;
u8 I2CCmd = pHalI2CInitData->I2CCmd;
u8 I2CStop = pHalI2CInitData->I2CStop;
u8 I2CReSTR= pHalI2CInitData->I2CReSTR;
DBG_I2C_INFO("HalI2CSendRtl8195a\n");
DBG_I2C_INFO("I2C Index: %x\n",I2CIdx);
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DATA_CMD,
*(pDat) |
BIT_CTRL_IC_DATA_CMD_RESTART(I2CReSTR)|
BIT_CTRL_IC_DATA_CMD_CMD(I2CCmd) |
BIT_CTRL_IC_DATA_CMD_STOP(I2CStop));
return (HAL_OK);
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CMassSendRtl8195a_Patch(
IN VOID *Data
){
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 I2CIdx = pHalI2CInitData->I2CIdx;
u8 I2CCmd = pHalI2CInitData->I2CCmd;
u8 I2CDatLen = pHalI2CInitData->I2CDataLen;
u8 *pDat = pHalI2CInitData->I2CRWData;
u8 I2CStopSet = pHalI2CInitData->I2CStop;
u8 I2CSTP;
u8 I2CReSRT = 0;
u8 DatCnt = 0;
/* Send I2C data one by one. The STOP bit is only used for the last byte.*/
for (DatCnt = 0; DatCnt < I2CDatLen; DatCnt++)
{
I2CSTP = 0;
if ((DatCnt == (I2CDatLen - 1)) && (I2CStopSet != 0)) {
I2CSTP = 1;
}
if ((DatCnt == 0) && ((pHalI2CInitData->RSVD0 & BIT0) != 0)) {
I2CReSRT = 1;
}
else {
I2CReSRT = 0;
}
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DATA_CMD,
*(pDat+DatCnt) |
BIT_CTRL_IC_DATA_CMD_CMD(I2CCmd) |
BIT_CTRL_IC_DATA_CMD_RESTART(I2CReSRT) |
BIT_CTRL_IC_DATA_CMD_STOP(I2CSTP));
}
return HAL_OK;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CInit8195a
//
// Description:
// To initialize I2C module by using the given data.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the DeInit process.
// _EXIT_SUCCESS if the initialization succeeded.
// _EXIT_FAILURE if the initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-04-02.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CInit8195a_Patch(
IN VOID *Data
)
{
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 Master;
u8 I2CIdx;
u8 SpdMd;
u8 AddrMd;
u8 ReSTR;
u8 StartByte;
u8 Specical;
u8 GC;
u16 I2CAckAddr;
u16 SdaHd;
u8 SdaSetup;
u8 RXTL;
u8 TXTL;
u8 SlvNoAck;
u32 INTRMsk;
u8 TxDMARqLv;
u8 RxDMARqLv;
u32 I2CTmp;
/* Get the I2C parameters*/
I2CIdx = pHalI2CInitData->I2CIdx;
SpdMd = pHalI2CInitData->I2CSpdMod;
AddrMd = pHalI2CInitData->I2CAddrMod;
I2CAckAddr = pHalI2CInitData->I2CAckAddr;
Master = pHalI2CInitData->I2CMaster;
SdaHd = pHalI2CInitData->I2CSdaHd;
SdaSetup = pHalI2CInitData->I2CSetup;
ReSTR = pHalI2CInitData->I2CReSTR;
GC = pHalI2CInitData->I2CGC;
StartByte = pHalI2CInitData->I2CStartB;
SlvNoAck = pHalI2CInitData->I2CSlvNoAck;
RXTL = pHalI2CInitData->I2CRXTL;
TXTL = pHalI2CInitData->I2CTXTL;
TxDMARqLv = pHalI2CInitData->I2CTxDMARqLv;
RxDMARqLv = pHalI2CInitData->I2CRxDMARqLv;
/* Disable the IC first */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_ENABLE,BIT_CTRL_IC_ENABLE(0));
/* Master case*/
if (Master) {
/*RESTART MUST be set in these condition in Master mode.
But it might be NOT compatible in old slaves.*/
if ((AddrMd == I2C_ADDR_10BIT) || (SpdMd == I2C_HS_MODE))
ReSTR = 1;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_CON,
(BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(1) |
BIT_CTRL_IC_CON_IC_RESTART_EN(ReSTR) |
BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(AddrMd) |
BIT_CTRL_IC_CON_SPEED(SpdMd) |
BIT_CTRL_IC_CON_MASTER_MODE(Master)));
DBG_I2C_INFO("Init master, IC_CON%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_CON, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON));
/* To set target addr.*/
Specical = 0;
if ((GC!=0) || (StartByte!=0))
Specical = 1;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_TAR,
(BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(AddrMd) |
BIT_CTRL_IC_TAR_SPECIAL(Specical) |
BIT_CTRL_IC_TAR_GC_OR_START(StartByte) |
BIT_CTRL_IC_TAR(I2CAckAddr)));
/* To Set I2C clock*/
HalI2CSetCLKRtl8195a_Patch(pHalI2CInitData);
DBG_I2C_INFO("Init master, IC_TAR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_TAR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_TAR));
} /*if (Master)*/
else {
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_CON,
BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(AddrMd) |
BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(Master) |
BIT_CTRL_IC_CON_SPEED(SpdMd)|
BIT_CTRL_IC_CON_MASTER_MODE(Master));
DBG_I2C_INFO("Init slave, IC_CON%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_CON, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON));
/* To set slave addr. */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SAR,BIT_CTRL_IC_SAR(I2CAckAddr));
DBG_I2C_INFO("Init slave, IC_SAR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_SAR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SAR));
/* To set slave no ack */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SLV_DATA_NACK_ONLY,BIT_CTRL_IC_SLV_DATA_NACK_ONLY(SlvNoAck));
/* Set ack general call. */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_ACK_GENERAL_CALL,BIT_CTRL_IC_ACK_GENERAL_CALL(pHalI2CInitData->I2CSlvAckGC));
DBG_I2C_INFO("Init slave, I2C_IC_ACK_GC%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_ACK_GENERAL_CALL, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_ACK_GENERAL_CALL));
/* to set SDA hold time */
//HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd));
//4
/* to set SDA setup time */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_SETUP,BIT_CTRL_IC_SDA_SETUP(SdaSetup));
}
/* to set SDA hold time */
INTRMsk = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON);
if (BIT_GET_IC_CON_SPEED(INTRMsk) == I2C_SS_MODE) {
I2CTmp = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT);
} else if (BIT_GET_IC_CON_SPEED(INTRMsk) == I2C_FS_MODE) {
I2CTmp = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT);
} else {
I2CTmp = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT);
}
if (Master) {
if (SdaHd > (I2CTmp -2)) {
I2CTmp = I2CTmp -2;
if (I2CTmp < 1) {
I2CTmp = 1 + 1;
}
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(I2CTmp));
} else {
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd));
}
} else {
if (SdaHd > (I2CTmp -2)) {
I2CTmp = I2CTmp -2;
if (I2CTmp < 7) {
I2CTmp = 7 + 1;
}
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(I2CTmp));
} else {
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd));
}
}
//DBG_8195A("SDA:%x\n", HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD));
/* To set TX_Empty Level */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_TX_TL,TXTL);
/* To set RX_Full Level */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_RX_TL,RXTL);
/* To set TX/RX FIFO level */
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DMA_TDLR,TxDMARqLv);
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DMA_RDLR,RxDMARqLv);
DBG_I2C_INFO("Init i2c dev, I2C_IC_DMA_TDLR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_DMA_TDLR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_DMA_TDLR));
DBG_I2C_INFO("Init i2c dev, I2C_IC_DMA_RDLR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_DMA_RDLR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_DMA_RDLR));
/*I2C Clear all interrupts first*/
HalI2CClrAllIntrRtl8195a(pHalI2CInitData);
/*I2C Disable all interrupts first*/
INTRMsk = pHalI2CInitData->I2CIntrMSK;
pHalI2CInitData->I2CIntrMSK = 0;
HalI2CIntrCtrl8195a(pHalI2CInitData);
pHalI2CInitData->I2CIntrMSK = INTRMsk;
return HAL_OK;
}
//---------------------------------------------------------------------------------------------------
//Function Name:
// HalI2CSetCLKRtl8195a
//
// Description:
// To set I2C bus clock rate.
//
// Arguments:
// [in] VOID *Data -
// The I2C parameter data struct.
//
// Return:
// The status of the enable process.
// _EXIT_SUCCESS if the de-initialization succeeded.
// _EXIT_FAILURE if the de-initialization failed.
//
// Note:
// None
//
// See Also:
// NA
//
// Author:
// By Jason Deng, 2014-02-18.
//
//---------------------------------------------------------------------------------------------------
HAL_Status
HalI2CSetCLKRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 SpdMd = pHalI2CInitData->I2CSpdMod;
u32 I2CClk = pHalI2CInitData->I2CClk;
u8 I2CIdx = pHalI2CInitData->I2CIdx;
u32 ICHLcnt;
u32 ICHtime;
u32 ICLtime;
/* Get the IC-Clk setting first for the following process*/
#ifdef CONFIG_FPGA
u32 IcClk = SYSTEM_CLK/1000000;
#else
u32 IcClk;
u32 ClkSELTmp = 0;
u32 CpuClkTmp = 0;
#if defined(CONFIG_CHIP_A_CUT)
CpuClkTmp = StartupHalGetCpuClk();
#elif (defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT))
CpuClkTmp = HalGetCpuClk();
#endif
DBG_I2C_INFO("%s, CPU Clk:%x\n",__func__, CpuClkTmp);
ClkSELTmp = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_SEL);
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
IcClk = (CpuClkTmp/1000000)>>1;
#if 0
if ((I2CClk > 0) && (I2CClk <= 400)) {
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
IcClk = ClkSELTmp/1000000; /*actually it's 12.5MHz*/
}
else {
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
IcClk = 100;
}
#endif
#endif
switch (SpdMd)
{
case I2C_SS_MODE:
{
ICHtime = ((1000000/I2CClk)*I2C_SS_MIN_SCL_HTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2CClk)*I2C_SS_MIN_SCL_LTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IcClk)/1000;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT,ICHLcnt);
DBG_I2C_INFO("IC_SS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_SS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT));
ICHLcnt = (ICLtime * IcClk)/1000;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT,ICHLcnt);
DBG_I2C_INFO("IC_SS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_SS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT));
break;
}
case I2C_FS_MODE:
{
ICHtime = ((1000000/I2CClk)*I2C_FS_MIN_SCL_HTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
ICLtime = ((1000000/I2CClk)*I2C_FS_MIN_SCL_LTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
ICHLcnt = (ICHtime * IcClk)/1000;
if (ICHLcnt>4)/*this part is according to the fine-tune result*/
ICHLcnt -= 4;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT,ICHLcnt);
DBG_I2C_INFO("IC_FS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_FS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT));
ICHLcnt = (ICLtime * IcClk)/1000;
if (ICHLcnt>3)/*this part is according to the fine-tune result*/
ICHLcnt -= 3;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT,ICHLcnt);
DBG_I2C_INFO("IC_FS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_FS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT));
break;
}
case I2C_HS_MODE:
{
ICHLcnt = 400;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT,ICHLcnt);
ICHLcnt = 470;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT,ICHLcnt);
ICHLcnt = 60;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT,ICHLcnt);
ICHLcnt = 130;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT,ICHLcnt);
ICHtime = ((1000000/I2CClk)*I2C_HS_MIN_SCL_HTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
ICLtime = ((1000000/I2CClk)*I2C_HS_MIN_SCL_LTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
DBG_I2C_INFO("ICHtime:%x\n",ICHtime);
DBG_I2C_INFO("ICLtime:%x\n",ICLtime);
ICHLcnt = (ICHtime * IcClk)/1000;
if (ICHLcnt>8)/*this part is according to the fine-tune result*/
ICHLcnt -= 3;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_HS_SCL_HCNT,ICHLcnt);
DBG_I2C_INFO("IC_HS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_HS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_HCNT));
ICHLcnt = (ICLtime * IcClk)/1000;
if (ICHLcnt>6)/*this part is according to the fine-tune result*/
ICHLcnt -= 6;
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT,ICHLcnt);
DBG_I2C_INFO("IC_HS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
REG_DW_I2C_IC_HS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT));
break;
}
default:
break;
}
return HAL_OK;
}
HAL_Status
HalI2CEnableRtl8195a_Patch(
IN VOID *Data
){
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
u8 I2CIdx = pHalI2CInitData->I2CIdx;
u8 I2CICEn = pHalI2CInitData->I2CEn;
u32 I2CTimeoutCount;
u32 I2CStartCount;
/* Enable I2C module */
HAL_I2C_WRITE32(I2CIdx, REG_DW_I2C_IC_ENABLE, BIT_CTRL_IC_ENABLE(I2CICEn));
I2CTimeoutCount = ((10000/pHalI2CInitData->I2CClk) /TIMER_TICK_US) +1;
I2CStartCount = HalTimerOp.HalTimerReadCount(1);
if (!I2CICEn) {
while (HAL_I2C_READ32(I2CIdx, REG_DW_I2C_IC_ENABLE_STATUS) & BIT_IC_ENABLE_STATUS_IC_EN) {
if (HAL_TIMEOUT == I2CIsTimeout(I2CStartCount, I2CTimeoutCount)) {
return HAL_TIMEOUT;
}
}
} else {
while (!(HAL_I2C_READ32(I2CIdx, REG_DW_I2C_IC_ENABLE_STATUS) & BIT_IC_ENABLE_STATUS_IC_EN)) {
if (HAL_TIMEOUT == I2CIsTimeout(I2CStartCount, I2CTimeoutCount)) {
return HAL_TIMEOUT;
}
}
}
return HAL_OK;
}
#endif
#endif // CONFIG_I2C_EN

398
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_i2s.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_i2s.h"
#include "hal_i2s.h"
#ifdef CONFIG_I2S_EN
extern void *
_memset( void *s, int c, SIZE_T n );
RTK_STATUS
HalI2SInitRtl8195a_Patch(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
//u8 I2SEn;
u8 I2SMaster;
u8 I2SWordLen;
u8 I2SChNum;
u8 I2SPageNum;
u16 I2SPageSize;
u16 I2SRate;
u32 I2STxIntrMSK;
u32 I2SRxIntrMSK;
u8 I2STRxAct;
u8 *I2STxData;
u8 *I2SRxData;
u32 Tmp;
I2SIdx = pHalI2SInitData->I2SIdx;
//I2SEn = pHalI2SInitData->I2SEn;
I2SMaster = pHalI2SInitData->I2SMaster;
I2SWordLen = pHalI2SInitData->I2SWordLen;
I2SChNum = pHalI2SInitData->I2SChNum;
I2SPageNum = pHalI2SInitData->I2SPageNum;
I2SPageSize = pHalI2SInitData->I2SPageSize;
I2SRate = pHalI2SInitData->I2SRate;
I2STRxAct = pHalI2SInitData->I2STRxAct;
I2STxData = pHalI2SInitData->I2STxData;
I2SRxData = pHalI2SInitData->I2SRxData;
/* Disable the I2S first, and reset to default */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(0));
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
Tmp = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
Tmp |= BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(1);
if (I2SRate & 0x10)
{
Tmp |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
}
Tmp |= (BIT_CTRL_CTLX_I2S_WL(I2SWordLen) | BIT_CTRL_CTLX_I2S_CH_NUM(I2SChNum) |
BIT_CTRL_CTLX_I2S_SLAVE_MODE(I2SMaster) | BIT_CTRL_CTLX_I2S_TRX_ACT(I2STRxAct));
/* set 44.1khz clock source, word length, channel number, master or slave, trx act */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, Tmp);
Tmp = BIT_CTRL_SETTING_I2S_PAGE_SZ(I2SPageSize) | BIT_CTRL_SETTING_I2S_PAGE_NUM(I2SPageNum) |
BIT_CTRL_SETTING_I2S_SAMPLE_RATE(I2SRate);
/* set page size, page number, sample rate */
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, Tmp);
/* need tx rx buffer? need rx page own bit */
if (I2STxData != NULL) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (u32)I2STxData);
}
if (I2SRxData != NULL) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (u32)I2SRxData);
}
pHalI2SInitData->I2STxIdx = 0;
pHalI2SInitData->I2SRxIdx = 0;
pHalI2SInitData->I2SHWTxIdx = 0;
pHalI2SInitData->I2SHWRxIdx = 0;
/* I2S Clear all interrupts first */
HalI2SClrAllIntrRtl8195a(pHalI2SInitData);
/* I2S Disable all interrupts first */
I2STxIntrMSK = pHalI2SInitData->I2STxIntrMSK;
I2SRxIntrMSK = pHalI2SInitData->I2SRxIntrMSK;
pHalI2SInitData->I2STxIntrMSK = 0;
pHalI2SInitData->I2SRxIntrMSK = 0;
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
pHalI2SInitData->I2STxIntrMSK = I2STxIntrMSK;
pHalI2SInitData->I2SRxIntrMSK = I2SRxIntrMSK;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetRateRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_CLK_SRC << BIT_SHIFT_CTLX_I2S_CLK_SRC);
if (pHalI2SInitData->I2SRate & 0x10)
{
reg_value |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
}
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_SAMPLE_RATE << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE);
reg_value |= BIT_CTRL_SETTING_I2S_SAMPLE_RATE(pHalI2SInitData->I2SRate);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetWordLenRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_WL << BIT_SHIFT_CTLX_I2S_WL);
reg_value |= BIT_CTRL_CTLX_I2S_WL(pHalI2SInitData->I2SWordLen);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetChNumRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_CH_NUM << BIT_SHIFT_CTLX_I2S_CH_NUM);
reg_value |= BIT_CTRL_CTLX_I2S_CH_NUM(pHalI2SInitData->I2SChNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetPageNumRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetPageSizeRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetDirectionRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
reg_value &= ~(BIT_MASK_CTLX_I2S_TRX_ACT << BIT_SHIFT_CTLX_I2S_TRX_ACT);
reg_value |= BIT_CTRL_CTLX_I2S_TRX_ACT(pHalI2SInitData->I2STRxAct);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SSetDMABufRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 reg_value;
u32 page_num;
I2SIdx = pHalI2SInitData->I2SIdx;
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
page_num = pHalI2SInitData->I2SPageNum + 1;
if (pHalI2SInitData->I2STxData) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2STxData);
pHalI2SInitData->I2STxIntrMSK = (1<<page_num) - 1;
} else {
pHalI2SInitData->I2STxIntrMSK = 0;
}
if (pHalI2SInitData->I2SRxData) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2SRxData);
pHalI2SInitData->I2SRxIntrMSK = (1<<page_num) - 1;
} else {
pHalI2SInitData->I2SRxIntrMSK = 0;
}
// According to the page number to modify the ISR mask
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
return _EXIT_SUCCESS;
}
u8
HalI2SGetTxPageRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
u32 reg;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(I2STxIdx<<2));
if ((reg & (1<<31)) == 0) {
return I2STxIdx;
} else {
return 0xFF;
}
}
u8
HalI2SGetRxPageRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
u32 reg;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
if ((reg & (1<<31)) == 0) {
return I2SRxIdx;
} else {
return 0xFF;
}
}
RTK_STATUS
HalI2SPageSendRtl8195a(
IN VOID *Data,
IN u8 PageIdx
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
u8 I2SIdx;
if (I2STxIdx != PageIdx) {
DBG_I2S_ERR("HalI2SPageSendRtl8195a: UnExpected Page Index. TxPage=%d, Expected:%d\r\n",
PageIdx, I2STxIdx);
}
I2SIdx = pHalI2SInitData->I2SIdx;
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN + 4 * PageIdx, BIT_PAGE_I2S_OWN_BIT);
I2STxIdx = PageIdx + 1;
if (I2STxIdx > I2SPageNum) {
I2STxIdx = 0;
}
pHalI2SInitData->I2STxIdx = I2STxIdx;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SPageRecvRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
u32 reg;
u8 I2SIdx;
I2SIdx = pHalI2SInitData->I2SIdx;
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
if ((reg & (1<<31)) != 0) {
DBG_I2S_ERR("HalI2SPageRecvRtl8195a: No Idle Rx Page\r\n");
return _EXIT_FAILURE;
}
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx<<2), 1<<31);
I2SRxIdx += 1;
if (I2SRxIdx > I2SPageNum) {
I2SRxIdx = 0;
}
pHalI2SInitData->I2SRxIdx = I2SRxIdx;
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SClearAllOwnBitRtl8195a(
IN VOID *Data
)
{
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
u8 I2SIdx;
u32 i;
I2SIdx = pHalI2SInitData->I2SIdx;
for (i=0;i<4;i++) {
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(i<<2), 0);
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(i<<2), 0);
}
return _EXIT_SUCCESS;
}
RTK_STATUS
HalI2SDMACtrlRtl8195a(
IN VOID *Data
)
{
return _EXIT_SUCCESS;
}
#endif // CONFIG_I2S_EN

1082
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_mii.c Normal file
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File diff suppressed because it is too large Load diff

2023
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_nfc.c Normal file
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File diff suppressed because it is too large Load diff

359
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_pcm.h"
#include "hal_pcm.h"
extern void *
_memset( void *s, int c, SIZE_T n );
VOID
HalPcmOnOffRtl8195a (
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
//todo on off pcm
}
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
// master mode, enable endian swap
// Question: need local tx/rx page?
BOOL
HalPcmInitRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
//4 1) Initial PcmChCNR03 Register
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
//4 1) Initial PcmTSR03 Register
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
//4 1) Initial PcmBSize03 Register
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
//4 2) Initial Ctl Register
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
pHalPcmAdapter->PcmCtl.FsInv = 0;
pHalPcmAdapter->PcmCtl.LinearMode = 0;
pHalPcmAdapter->PcmCtl.LoopBack = 0;
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
return _TRUE;
}
BOOL
HalPcmSettingRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
u32 Isr03;
PcmCh=0;
//4 1) Check Pcm index is avaliable
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
//4 2) Check if there are the pending isr
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
Isr03 &= 0xff000000;
//4 Clear Pending Isr
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
//}
//4 3) Process RegCtl
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
//4 Clear Ctl register bits
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
BIT_INV_CTLX_FSINV &
BIT_INV_CTLX_PCM_EN &
BIT_INV_CTLX_LINEARMODE &
BIT_INV_CTLX_LOOP_BACK &
BIT_INV_CTLX_ENDIAN_SWAP);
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
RegCtl;
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
//4 4) Program ChCNR03 Register
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
BIT_INV_CHCNR03_CH0TE &
BIT_INV_CHCNR03_CH0MUA &
BIT_INV_CHCNR03_CH0BAND);
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
RegChCNR03;
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
// time slot
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
RegTSR03;
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
// buffer size
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
RegBSize03;
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
return _TRUE;
}
BOOL
HalPcmEnRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 1;
//4 1) Check Pcm index is avaliable
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
if (RegChCNR03 & (BIT24|BIT25)) {
//4 Pcm index is running, stop first
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
return _FALSE;
}
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
return _TRUE;
}
BOOL
HalPcmDisRtl8195a(
IN VOID *Data
)
{
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
u8 PcmCh = pHalPcmAdapter->PcmCh;
u32 RegChCNR03;
PcmCh=0;
pHalPcmAdapter->Enable = 0;
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
return _TRUE;
}
BOOL
HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
((~pHalGdmaAdapter->ChEn) & IsrMask));
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
Addr,
IsrCtrl
);
}
}
*/
return _TRUE;
}
BOOL
HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
BOOL
HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
return _TRUE;
}
/*
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
)
{
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrStatus;
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
);
IsrActBitMap |= BIT_(IsrTypeIndex);
}
}
return IsrActBitMap;
}
VOID
HalGdmaChCleanAutoSrcRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
VOID
HalGdmaChCleanAutoDstRtl8195a (
IN VOID *Data
)
{
u32 CfgxLow;
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
CfgxLow
);
DBG_8195A_DMA("CFG Low data:0x%x\n",
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "hal_peri_on.h"
#ifdef CONFIG_PWM_EN
#include "rtl8195a_pwm.h"
#include "hal_pwm.h"
extern HAL_PWM_ADAPTER PWMPin[];
extern HAL_TIMER_OP HalTimerOp;
/**
* @brief Configure a G-Timer to generate a tick with certain time.
*
* @param pwm_id: the PWM pin index
* @param tick_time: the time (micro-second) of a tick
*
* @retval None
*/
void
Pwm_SetTimerTick_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 tick_time
)
{
TIMER_ADAPTER TimerAdapter;
if (tick_time <= MIN_GTIMER_TIMEOUT) {
tick_time = MIN_GTIMER_TIMEOUT;
}
else {
tick_time = (((tick_time-1)/TIMER_TICK_US)+1) * TIMER_TICK_US;
}
// Initial a G-Timer for the PWM pin
if (pPwmAdapt->tick_time != tick_time) {
TimerAdapter.IrqDis = 1; // Disable Irq
TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) NULL;
TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
TimerAdapter.IrqHandle.Priority = 10;
TimerAdapter.IrqHandle.Data = (u32)NULL;
TimerAdapter.TimerId = pPwmAdapt->gtimer_id;
TimerAdapter.TimerIrqPriority = 0;
TimerAdapter.TimerLoadValueUs = tick_time-1;
TimerAdapter.TimerMode = 1; // auto-reload with user defined value
HalTimerOp.HalTimerInit((VOID*) &TimerAdapter);
pPwmAdapt->tick_time = tick_time;
DBG_PWM_INFO("%s: Timer_Id=%d Count=%d\n", __FUNCTION__, pPwmAdapt->gtimer_id, tick_time);
}
}
/**
* @brief Set the duty ratio of the PWM pin.
*
* @param pwm_id: the PWM pin index
* @param period: the period time, in micro-second.
* @param pulse_width: the pulse width time, in micro-second.
*
* @retval None
*/
void
HAL_Pwm_SetDuty_8195a(
HAL_PWM_ADAPTER *pPwmAdapt,
u32 period,
u32 pulse_width
)
{
u32 RegAddr;
u32 RegValue;
u32 period_tick;
u32 pulsewidth_tick;
u32 tick_time;
u8 timer_id;
u8 pwm_id;
pwm_id = pPwmAdapt->pwm_id;
// Adjust the tick time to a proper value
if (period < (MIN_GTIMER_TIMEOUT*2)) {
DBG_PWM_ERR ("HAL_Pwm_SetDuty_8195a: Invalid PWM period(%d), too short!!\n", period);
tick_time = MIN_GTIMER_TIMEOUT;
period = MIN_GTIMER_TIMEOUT*2;
}
else {
tick_time = period / 0x3fc; // a duty cycle be devided into 1020 ticks
if (tick_time < MIN_GTIMER_TIMEOUT) {
tick_time = MIN_GTIMER_TIMEOUT;
}
}
Pwm_SetTimerTick_8195a(pPwmAdapt, tick_time);
tick_time = pPwmAdapt->tick_time;
#if 0
// Check if current tick time needs adjustment
if ((pPwmAdapt->tick_time << 12) <= period) {
// need a longger tick time
}
else if ((pPwmAdapt->tick_time >> 2) >= period) {
// need a shorter tick time
}
#endif
period_tick = period/tick_time;
if (period_tick == 0) {
period_tick = 1;
}
if (pulse_width >= period) {
// pulse_width = period-1;
pulse_width = period;
}
pulsewidth_tick = pulse_width/tick_time;
if (pulsewidth_tick == 0) {
// pulsewidth_tick = 1;
}
timer_id = pPwmAdapt->gtimer_id;
pPwmAdapt->period = period_tick & 0x3ff;
pPwmAdapt->pulsewidth = pulsewidth_tick & 0x3ff;
RegAddr = REG_PERI_PWM0_CTRL + (pwm_id*4);
RegValue = BIT31 | (timer_id<<24) | (pulsewidth_tick<<12) | period_tick;
HAL_WRITE32(PERI_ON_BASE, RegAddr, RegValue);
}
/**
* @brief Initializes and enable a PWM control pin.
*
* @param pwm_id: the PWM pin index
* @param sel: pin mux selection
* @param timer_id: the G-timer index assigned to this PWM
*
* @retval HAL_Status
*/
HAL_Status
HAL_Pwm_Init_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
)
{
u32 pwm_id;
u32 pin_sel;
pwm_id = pPwmAdapt->pwm_id;
pin_sel = pPwmAdapt->sel;
// Initial a G-Timer for the PWM pin
Pwm_SetTimerTick_8195a(pPwmAdapt, MIN_GTIMER_TIMEOUT);
// Set default duty ration
HAL_Pwm_SetDuty_8195a(pPwmAdapt, 20000, 10000);
// Configure the Pin Mux
PinCtrl((PWM0+pwm_id), pin_sel, 1);
return HAL_OK;
}
/**
* @brief Enable a PWM control pin.
*
* @param pwm_id: the PWM pin index
*
* @retval None
*/
void
HAL_Pwm_Enable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
)
{
u32 pwm_id;
pwm_id = pPwmAdapt->pwm_id;
// Configure the Pin Mux
if (!pPwmAdapt->enable) {
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 1);
HalTimerOp.HalTimerEn(pPwmAdapt->gtimer_id);
pPwmAdapt->enable = 1;
}
}
/**
* @brief Disable a PWM control pin.
*
* @param pwm_id: the PWM pin index
*
* @retval None
*/
void
HAL_Pwm_Disable_8195a(
HAL_PWM_ADAPTER *pPwmAdapt
)
{
u32 pwm_id;
pwm_id = pPwmAdapt->pwm_id;
// Configure the Pin Mux
if (pPwmAdapt->enable) {
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 0);
HalTimerOp.HalTimerDis(pPwmAdapt->gtimer_id);
pPwmAdapt->enable = 0;
}
}
#endif //CONFIG_PWM_EN

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "rtl8195a_timer.h"
#ifdef CONFIG_TIMER_EN
extern u32 gTimerRecord;
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
#ifdef CONFIG_CHIP_A_CUT
HAL_RAM_BSS_SECTION u32 gTimerRecord;
#endif
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#else
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
#endif
VOID
HalTimerIrq2To7Handle_Patch(
IN VOID *Data
)
{
u32 TimerIrqStatus = 0, CheckIndex;
IRQ_FUN pHandler;
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
//3 Check IRQ status bit and Timer X IRQ enable bit
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
//3 Execute Timer callback function
pHandler = Timer2To7VectorTable[CheckIndex-2];
if (pHandler != NULL) {
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
}
//3 Clear Timer ISR
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
}
}
}
HAL_Status
HalTimerIrqRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
IRQ_HANDLE TimerIrqHandle;
//IRQ_FUN BackUpIrqFun = NULL;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
(uint32_t) pHalTimerAdap->IrqHandle.Data;
}
else {
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
}
TimerIrqHandle.Data = (u32)pHalTimerAdap;
InterruptRegister(&TimerIrqHandle);
}
return HAL_OK;
}
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
// Patch for A/B Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
u32 ControlReg;
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_BUSY;
}
//4 1) Config Timer Setting
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
/*
set TimerControlReg
0: Timer enable (0,disable; 1,enable)
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
2: Timer Interrupt Mask (0, not masked; 1,masked)
*/
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
ControlReg);
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
else {
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
0xFFFFFFFF);
}
//4 2) Setting Timer IRQ
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
//4 2.1) Initial TimerIRQHandle
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
if (HAL_OK != ret) {
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return ret;
}
//4 2.2) Enable TimerIRQ for Platform
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
}
else {
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
return HAL_ERR_PARA;
}
}
//4 4) Enable Timer
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
// (ControlReg|0x1));
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
return ret;
}
#elif defined(CONFIG_CHIP_C_CUT)
// Patch for C Cut
HAL_Status
HalTimerInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
HAL_Status ret=HAL_OK;
ret = HalTimerInitRtl8195aV02(Data);
// Patch the Rom code to load the correct count value
if (pHalTimerAdap->TimerMode) {
//User-defined Mode
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
}
return ret;
}
#endif
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
HAL_Status
HalTimerIrqUnRegisterRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
PIRQ_HANDLE pTimerIrqHandle;
u32 i;
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
if (pHalTimerAdap->TimerId > 7) {
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
return HAL_ERR_PARA;
}
else {
if (pHalTimerAdap->TimerId > 1) {
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
if (Timer2To7VectorTable[i] != NULL) {
break;
}
}
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
// All timer UnRegister Interrupt
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
InterruptUnRegister(pTimerIrqHandle);
}
}
else {
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
InterruptUnRegister(pTimerIrqHandle);
}
}
return HAL_OK;
}
VOID
HalTimerDeInitRtl8195a_Patch(
IN VOID *Data
)
{
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
u32 timer_id;
timer_id = pHalTimerAdap->TimerId;
HalTimerDisRtl8195a (timer_id);
if (!pHalTimerAdap->IrqDis) {
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
}
}
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
}
u32
HalTimerReadCountRtl8195a_Patch(
IN u32 TimerId
)
{
u32 TimerCountOld;
u32 TimerCountNew;
u32 TimerRDCnt;
TimerRDCnt = 0;
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
while(1) {
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
if (TimerCountOld == TimerCountNew) {
return (u32)TimerCountOld;
}
else {
TimerRDCnt++;
TimerCountOld = TimerCountNew;
if (TimerRDCnt >= 2){
return (u32)TimerCountOld;
}
}
}
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerReLoadRtl8195a_Patch(
IN u32 TimerId,
IN u32 LoadUs
)
{
u32 LoadCount = 0;
u32 ms125; // how many 125ms
u32 remain_us;
ms125 = LoadUs/125000;
remain_us = LoadUs - (ms125*125000);
LoadCount = ms125 * (GTIMER_CLK_HZ/8);
LoadCount += (remain_us*GTIMER_CLK_HZ)/1000000;
if (LoadCount == 0) {
LoadCount = 1;
}
// DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
// set TimerLoadCount Register
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
LoadCount);
}
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
VOID
HalTimerIrqEnRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
}
VOID
HalTimerIrqDisRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
}
VOID
HalTimerClearIsrRtl8195a(
IN u32 TimerId
)
{
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_EOI_OFF);
}
VOID
HalTimerEnRtl8195a_Patch(
IN u32 TimerId
)
{
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
}
VOID
HalTimerDisRtl8195a_Patch(
IN u32 TimerId
)
{
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
}
#endif // CONFIG_TIMER_EN

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