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pvvx
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792 changed files with 336059 additions and 0 deletions
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _HAL_8195A_H_
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#define _HAL_8195A_H_
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#include "platform_autoconf.h"
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#include "basic_types.h"
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#include "section_config.h"
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#include "rtl8195a_sys_on.h"
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#include "rtl8195a_peri_on.h"
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#include "hal_platform.h"
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#include "hal_pinmux.h"
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#include "hal_api.h"
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#include "hal_peri_on.h"
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#include "hal_misc.h"
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#include "hal_irqn.h"
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#include "hal_vector_table.h"
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#include "hal_diag.h"
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#include "hal_spi_flash.h"
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#include "rtl8195a_spi_flash.h"
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#include "hal_timer.h"
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#include "hal_util.h"
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#include "hal_efuse.h"
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#include "hal_soc_ps_monitor.h"
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#include "diag.h"
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#include "hal_common.h"
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#include "hal_soc_ps_monitor.h"
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/* ----------------------------------------------------------------------------
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-- Cortex M3 Core Configuration
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
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* @{
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*/
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#define __CM3_REV 0x0200 /**< Core revision r0p0 */
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#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
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#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
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#define __Vendor_SysTickConfig 1 /**< Vendor specific implementation of SysTickConfig is defined */
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#include "core_cm3.h"
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#ifdef CONFIG_TIMER_EN
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#include "hal_timer.h"
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#endif
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#ifdef CONFIG_GDMA_EN
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#include "hal_gdma.h"
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#include "rtl8195a_gdma.h"
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#endif
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#ifdef CONFIG_GPIO_EN
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#include "hal_gpio.h"
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#include "rtl8195a_gpio.h"
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#endif
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#ifdef CONFIG_SPI_COM_EN
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#include "hal_ssi.h"
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#include "rtl8195a_ssi.h"
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#endif
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#ifdef CONFIG_UART_EN
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#include "hal_uart.h"
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#include "rtl8195a_uart.h"
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#endif
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#ifdef CONFIG_I2C_EN
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#include "hal_i2c.h"
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#include "rtl8195a_i2c.h"
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#endif
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#ifdef CONFIG_PCM_EN
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#include "hal_pcm.h"
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#include "rtl8195a_pcm.h"
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#endif
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#ifdef CONFIG_PWM_EN
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#include "hal_pwm.h"
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#include "rtl8195a_pwm.h"
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#endif
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#ifdef CONFIG_I2S_EN
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#include "hal_i2s.h"
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#include "rtl8195a_i2s.h"
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#endif
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#ifdef CONFIG_DAC_EN
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#include "hal_dac.h"
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#include "rtl8195a_dac.h"
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#endif
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#ifdef CONFIG_ADC_EN
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#include "hal_adc.h"
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#include "rtl8195a_adc.h"
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#endif
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#ifdef CONFIG_SDR_EN
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#endif
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#ifdef CONFIG_SPIC_EN
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#endif
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#ifdef CONFIG_SDIO_DEVICE_EN
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#include "hal_sdio.h"
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#endif
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#ifdef CONFIG_NFC_EN
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#include "hal_nfc.h"
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#include "rtl8195a_nfc.h"
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#endif
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#ifdef CONFIG_WDG
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#include "rtl8195a_wdt.h"
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#endif
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#ifdef CONFIG_USB_EN
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#include "hal_usb.h"
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#include "rtl8195a_usb.h"
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#endif
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#include "hal_log_uart.h"
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#ifdef CONFIG_MII_EN
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#include "hal_mii.h"
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#include "rtl8195a_mii.h"
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#endif
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// firmware information, located at the header of Image2
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#define FW_VERSION (0x0100)
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#define FW_SUBVERSION (0x0001)
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#define FW_CHIP_ID (0x8195)
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#define FW_CHIP_VER (0x01)
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#define FW_BUS_TYPE (0x01) // the iNIC firmware type: USB/SDIO
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#define FW_INFO_RSV1 (0x00) // the firmware information reserved
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#define FW_INFO_RSV2 (0x00) // the firmware information reserved
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#define FW_INFO_RSV3 (0x00) // the firmware information reserved
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#define FW_INFO_RSV4 (0x00) // the firmware information reserved
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#define FLASH_RESERVED_DATA_BASE 0x8000 // reserve 32K for Image1
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#define FLASH_SYSTEM_DATA_ADDR 0x9000 // reserve 32K+4K for Image1 + Reserved data
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// Flash Map for Calibration data
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#define FLASH_CAL_DATA_BASE 0xA000
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#define FLASH_CAL_DATA_ADDR(_offset) (FLASH_CAL_DATA_BASE + _offset)
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#define FLASH_CAL_DATA_SIZE 0x1000
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#define FLASH_SECTOR_SIZE 0x1000
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// SPIC Calibration Data
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#define FLASH_SPIC_PARA_OFFSET 0x80
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#define FLASH_SPIC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SPIC_PARA_OFFSET)
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// SDRC Calibration Data
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#define FLASH_SDRC_PARA_OFFSET 0x180
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#define FLASH_SDRC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_SDRC_PARA_OFFSET)
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// ADC Calibration Data
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#define FLASH_ADC_PARA_OFFSET 0x200
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#define FLASH_ADC_PARA_BASE (FLASH_SYSTEM_DATA_ADDR+FLASH_ADC_PARA_OFFSET)
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#endif //_HAL_8195A_H_
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _RTL8195A_ADC_H_
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#define _RTL8195A_ADC_H_
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//================ Register Bit Field ==========================
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//2 REG_ADC_FIFO_READ
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#define BIT_SHIFT_ADC_FIFO_RO 0
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#define BIT_MASK_ADC_FIFO_RO 0xffffffffL
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#define BIT_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
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#define BIT_CTRL_ADC_FIFO_RO(x) (((x) & BIT_MASK_ADC_FIFO_RO) << BIT_SHIFT_ADC_FIFO_RO)
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#define BIT_GET_ADC_FIFO_RO(x) (((x) >> BIT_SHIFT_ADC_FIFO_RO) & BIT_MASK_ADC_FIFO_RO)
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//2 REG_ADC_CONTROL
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#define BIT_SHIFT_ADC_DBG_SEL 24
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#define BIT_MASK_ADC_DBG_SEL 0x7
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#define BIT_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
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#define BIT_CTRL_ADC_DBG_SEL(x) (((x) & BIT_MASK_ADC_DBG_SEL) << BIT_SHIFT_ADC_DBG_SEL)
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#define BIT_GET_ADC_DBG_SEL(x) (((x) >> BIT_SHIFT_ADC_DBG_SEL) & BIT_MASK_ADC_DBG_SEL)
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#define BIT_SHIFT_ADC_THRESHOLD 16
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#define BIT_MASK_ADC_THRESHOLD 0x3f
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#define BIT_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
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#define BIT_CTRL_ADC_THRESHOLD(x) (((x) & BIT_MASK_ADC_THRESHOLD) << BIT_SHIFT_ADC_THRESHOLD)
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#define BIT_GET_ADC_THRESHOLD(x) (((x) >> BIT_SHIFT_ADC_THRESHOLD) & BIT_MASK_ADC_THRESHOLD)
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#define BIT_SHIFT_ADC_BURST_SIZE 8
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#define BIT_MASK_ADC_BURST_SIZE 0x1f
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#define BIT_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
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#define BIT_CTRL_ADC_BURST_SIZE(x) (((x) & BIT_MASK_ADC_BURST_SIZE) << BIT_SHIFT_ADC_BURST_SIZE)
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#define BIT_GET_ADC_BURST_SIZE(x) (((x) >> BIT_SHIFT_ADC_BURST_SIZE) & BIT_MASK_ADC_BURST_SIZE)
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#define BIT_ADC_ENDIAN BIT(3)
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#define BIT_SHIFT_ADC_ENDIAN 3
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#define BIT_MASK_ADC_ENDIAN 0x1
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#define BIT_CTRL_ADC_ENDIAN(x) (((x) & BIT_MASK_ADC_ENDIAN) << BIT_SHIFT_ADC_ENDIAN)
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#define BIT_ADC_OVERWRITE BIT(2)
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#define BIT_SHIFT_ADC_OVERWRITE 2
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#define BIT_MASK_ADC_OVERWRITE 0x1
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#define BIT_CTRL_ADC_OVERWRITE(x) (((x) & BIT_MASK_ADC_OVERWRITE) << BIT_SHIFT_ADC_OVERWRITE)
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#define BIT_ADC_ONESHOT BIT(1)
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#define BIT_SHIFT_ADC_ONESHOT 1
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#define BIT_MASK_ADC_ONESHOT 0x1
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#define BIT_CTRL_ADC_ONESHOT(x) (((x) & BIT_MASK_ADC_ONESHOT) << BIT_SHIFT_ADC_ONESHOT)
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#define BIT_ADC_COMP_ONLY BIT(0)
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#define BIT_SHIFT_ADC_COMP_ONLY 0
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#define BIT_MASK_ADC_COMP_ONLY 0x1
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#define BIT_CTRL_ADC_COMP_ONLY(x) (((x) & BIT_MASK_ADC_COMP_ONLY) << BIT_SHIFT_ADC_COMP_ONLY)
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//2 REG_ADC_INTR_EN
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#define BIT_ADC_AWAKE_CPU_EN BIT(7)
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#define BIT_SHIFT_ADC_AWAKE_CPU_EN 7
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#define BIT_MASK_ADC_AWAKE_CPU_EN 0x1
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#define BIT_CTRL_ADC_AWAKE_CPU_EN(x) (((x) & BIT_MASK_ADC_AWAKE_CPU_EN) << BIT_SHIFT_ADC_AWAKE_CPU_EN)
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#define BIT_ADC_FIFO_RD_ERROR_EN BIT(6)
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#define BIT_SHIFT_ADC_FIFO_RD_ERROR_EN 6
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#define BIT_MASK_ADC_FIFO_RD_ERROR_EN 0x1
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#define BIT_CTRL_ADC_FIFO_RD_ERROR_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_EN) << BIT_SHIFT_ADC_FIFO_RD_ERROR_EN)
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#define BIT_ADC_FIFO_RD_REQ_EN BIT(5)
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#define BIT_SHIFT_ADC_FIFO_RD_REQ_EN 5
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#define BIT_MASK_ADC_FIFO_RD_REQ_EN 0x1
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#define BIT_CTRL_ADC_FIFO_RD_REQ_EN(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_EN) << BIT_SHIFT_ADC_FIFO_RD_REQ_EN)
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#define BIT_ADC_FIFO_FULL_EN BIT(4)
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#define BIT_SHIFT_ADC_FIFO_FULL_EN 4
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#define BIT_MASK_ADC_FIFO_FULL_EN 0x1
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#define BIT_CTRL_ADC_FIFO_FULL_EN(x) (((x) & BIT_MASK_ADC_FIFO_FULL_EN) << BIT_SHIFT_ADC_FIFO_FULL_EN)
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#define BIT_ADC_COMP_3_EN BIT(3)
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#define BIT_SHIFT_ADC_COMP_3_EN 3
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#define BIT_MASK_ADC_COMP_3_EN 0x1
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#define BIT_CTRL_ADC_COMP_3_EN(x) (((x) & BIT_MASK_ADC_COMP_3_EN) << BIT_SHIFT_ADC_COMP_3_EN)
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#define BIT_ADC_COMP_2_EN BIT(2)
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#define BIT_SHIFT_ADC_COMP_2_EN 2
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#define BIT_MASK_ADC_COMP_2_EN 0x1
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#define BIT_CTRL_ADC_COMP_2_EN(x) (((x) & BIT_MASK_ADC_COMP_2_EN) << BIT_SHIFT_ADC_COMP_2_EN)
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#define BIT_ADC_COMP_1_EN BIT(1)
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#define BIT_SHIFT_ADC_COMP_1_EN 1
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#define BIT_MASK_ADC_COMP_1_EN 0x1
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#define BIT_CTRL_ADC_COMP_1_EN(x) (((x) & BIT_MASK_ADC_COMP_1_EN) << BIT_SHIFT_ADC_COMP_1_EN)
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#define BIT_ADC_COMP_0_EN BIT(0)
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#define BIT_SHIFT_ADC_COMP_0_EN 0
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#define BIT_MASK_ADC_COMP_0_EN 0x1
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#define BIT_CTRL_ADC_COMP_0_EN(x) (((x) & BIT_MASK_ADC_COMP_0_EN) << BIT_SHIFT_ADC_COMP_0_EN)
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//2 REG_ADC_INTR_STS
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#define BIT_ADC_FIFO_THRESHOLD BIT(7)
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#define BIT_SHIFT_ADC_FIFO_THRESHOLD 7
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#define BIT_MASK_ADC_FIFO_THRESHOLD 0x1
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#define BIT_CTRL_ADC_FIFO_THRESHOLD(x) (((x) & BIT_MASK_ADC_FIFO_THRESHOLD) << BIT_SHIFT_ADC_FIFO_THRESHOLD)
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#define BIT_ADC_FIFO_RD_ERROR_ST BIT(6)
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#define BIT_SHIFT_ADC_FIFO_RD_ERROR_ST 6
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#define BIT_MASK_ADC_FIFO_RD_ERROR_ST 0x1
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#define BIT_CTRL_ADC_FIFO_RD_ERROR_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_ERROR_ST) << BIT_SHIFT_ADC_FIFO_RD_ERROR_ST)
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#define BIT_ADC_FIFO_RD_REQ_ST BIT(5)
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#define BIT_SHIFT_ADC_FIFO_RD_REQ_ST 5
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#define BIT_MASK_ADC_FIFO_RD_REQ_ST 0x1
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#define BIT_CTRL_ADC_FIFO_RD_REQ_ST(x) (((x) & BIT_MASK_ADC_FIFO_RD_REQ_ST) << BIT_SHIFT_ADC_FIFO_RD_REQ_ST)
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#define BIT_ADC_FIFO_FULL_ST BIT(4)
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#define BIT_SHIFT_ADC_FIFO_FULL_ST 4
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#define BIT_MASK_ADC_FIFO_FULL_ST 0x1
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#define BIT_CTRL_ADC_FIFO_FULL_ST(x) (((x) & BIT_MASK_ADC_FIFO_FULL_ST) << BIT_SHIFT_ADC_FIFO_FULL_ST)
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#define BIT_ADC_COMP_3_ST BIT(3)
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#define BIT_SHIFT_ADC_COMP_3_ST 3
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#define BIT_MASK_ADC_COMP_3_ST 0x1
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#define BIT_CTRL_ADC_COMP_3_ST(x) (((x) & BIT_MASK_ADC_COMP_3_ST) << BIT_SHIFT_ADC_COMP_3_ST)
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#define BIT_ADC_COMP_2_ST BIT(2)
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#define BIT_SHIFT_ADC_COMP_2_ST 2
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#define BIT_MASK_ADC_COMP_2_ST 0x1
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#define BIT_CTRL_ADC_COMP_2_ST(x) (((x) & BIT_MASK_ADC_COMP_2_ST) << BIT_SHIFT_ADC_COMP_2_ST)
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#define BIT_ADC_COMP_1_ST BIT(1)
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#define BIT_SHIFT_ADC_COMP_1_ST 1
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#define BIT_MASK_ADC_COMP_1_ST 0x1
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#define BIT_CTRL_ADC_COMP_1_ST(x) (((x) & BIT_MASK_ADC_COMP_1_ST) << BIT_SHIFT_ADC_COMP_1_ST)
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#define BIT_ADC_COMP_0_ST BIT(0)
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#define BIT_SHIFT_ADC_COMP_0_ST 0
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#define BIT_MASK_ADC_COMP_0_ST 0x1
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#define BIT_CTRL_ADC_COMP_0_ST(x) (((x) & BIT_MASK_ADC_COMP_0_ST) << BIT_SHIFT_ADC_COMP_0_ST)
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//2 REG_ADC_COMP_VALUE_L
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#define BIT_SHIFT_ADC_COMP_TH_1 16
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#define BIT_MASK_ADC_COMP_TH_1 0xffff
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#define BIT_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
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#define BIT_CTRL_ADC_COMP_TH_1(x) (((x) & BIT_MASK_ADC_COMP_TH_1) << BIT_SHIFT_ADC_COMP_TH_1)
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#define BIT_GET_ADC_COMP_TH_1(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_1) & BIT_MASK_ADC_COMP_TH_1)
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#define BIT_SHIFT_ADC_COMP_TH_0 0
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#define BIT_MASK_ADC_COMP_TH_0 0xffff
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#define BIT_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
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#define BIT_CTRL_ADC_COMP_TH_0(x) (((x) & BIT_MASK_ADC_COMP_TH_0) << BIT_SHIFT_ADC_COMP_TH_0)
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#define BIT_GET_ADC_COMP_TH_0(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_0) & BIT_MASK_ADC_COMP_TH_0)
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//2 REG_ADC_COMP_VALUE_H
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#define BIT_SHIFT_ADC_COMP_TH_3 16
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#define BIT_MASK_ADC_COMP_TH_3 0xffff
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#define BIT_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
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#define BIT_CTRL_ADC_COMP_TH_3(x) (((x) & BIT_MASK_ADC_COMP_TH_3) << BIT_SHIFT_ADC_COMP_TH_3)
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#define BIT_GET_ADC_COMP_TH_3(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_3) & BIT_MASK_ADC_COMP_TH_3)
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#define BIT_SHIFT_ADC_COMP_TH_2 0
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#define BIT_MASK_ADC_COMP_TH_2 0xffff
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#define BIT_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
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#define BIT_CTRL_ADC_COMP_TH_2(x) (((x) & BIT_MASK_ADC_COMP_TH_2) << BIT_SHIFT_ADC_COMP_TH_2)
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#define BIT_GET_ADC_COMP_TH_2(x) (((x) >> BIT_SHIFT_ADC_COMP_TH_2) & BIT_MASK_ADC_COMP_TH_2)
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//2 REG_ADC_COMP_SET
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#define BIT_SHIFT_ADC_GREATER_THAN 0
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#define BIT_MASK_ADC_GREATER_THAN 0xf
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#define BIT_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
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#define BIT_CTRL_ADC_GREATER_THAN(x) (((x) & BIT_MASK_ADC_GREATER_THAN) << BIT_SHIFT_ADC_GREATER_THAN)
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#define BIT_GET_ADC_GREATER_THAN(x) (((x) >> BIT_SHIFT_ADC_GREATER_THAN) & BIT_MASK_ADC_GREATER_THAN)
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//2 REG_ADC_POWER
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#define BIT_SHIFT_ADC_PWR_CUT_CNTR 16
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#define BIT_MASK_ADC_PWR_CUT_CNTR 0xff
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#define BIT_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
|
||||
#define BIT_CTRL_ADC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_ADC_PWR_CUT_CNTR) << BIT_SHIFT_ADC_PWR_CUT_CNTR)
|
||||
#define BIT_GET_ADC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_ADC_PWR_CUT_CNTR) & BIT_MASK_ADC_PWR_CUT_CNTR)
|
||||
|
||||
#define BIT_ADC_FIFO_ON_ST BIT(11)
|
||||
#define BIT_SHIFT_ADC_FIFO_ON_ST 11
|
||||
#define BIT_MASK_ADC_FIFO_ON_ST 0x1
|
||||
#define BIT_CTRL_ADC_FIFO_ON_ST(x) (((x) & BIT_MASK_ADC_FIFO_ON_ST) << BIT_SHIFT_ADC_FIFO_ON_ST)
|
||||
|
||||
#define BIT_ADC_ISO_ON_ST BIT(10)
|
||||
#define BIT_SHIFT_ADC_ISO_ON_ST 10
|
||||
#define BIT_MASK_ADC_ISO_ON_ST 0x1
|
||||
#define BIT_CTRL_ADC_ISO_ON_ST(x) (((x) & BIT_MASK_ADC_ISO_ON_ST) << BIT_SHIFT_ADC_ISO_ON_ST)
|
||||
|
||||
#define BIT_ADC_PWR33_ON_ST BIT(9)
|
||||
#define BIT_SHIFT_ADC_PWR33_ON_ST 9
|
||||
#define BIT_MASK_ADC_PWR33_ON_ST 0x1
|
||||
#define BIT_CTRL_ADC_PWR33_ON_ST(x) (((x) & BIT_MASK_ADC_PWR33_ON_ST) << BIT_SHIFT_ADC_PWR33_ON_ST)
|
||||
|
||||
#define BIT_ADC_PWR12_ON_ST BIT(8)
|
||||
#define BIT_SHIFT_ADC_PWR12_ON_ST 8
|
||||
#define BIT_MASK_ADC_PWR12_ON_ST 0x1
|
||||
#define BIT_CTRL_ADC_PWR12_ON_ST(x) (((x) & BIT_MASK_ADC_PWR12_ON_ST) << BIT_SHIFT_ADC_PWR12_ON_ST)
|
||||
|
||||
#define BIT_ADC_ISO_MANUAL BIT(3)
|
||||
#define BIT_SHIFT_ADC_ISO_MANUAL 3
|
||||
#define BIT_MASK_ADC_ISO_MANUAL 0x1
|
||||
#define BIT_CTRL_ADC_ISO_MANUAL(x) (((x) & BIT_MASK_ADC_ISO_MANUAL) << BIT_SHIFT_ADC_ISO_MANUAL)
|
||||
|
||||
#define BIT_ADC_PWR33_MANUAL BIT(2)
|
||||
#define BIT_SHIFT_ADC_PWR33_MANUAL 2
|
||||
#define BIT_MASK_ADC_PWR33_MANUAL 0x1
|
||||
#define BIT_CTRL_ADC_PWR33_MANUAL(x) (((x) & BIT_MASK_ADC_PWR33_MANUAL) << BIT_SHIFT_ADC_PWR33_MANUAL)
|
||||
|
||||
#define BIT_ADC_PWR12_MANUAL BIT(1)
|
||||
#define BIT_SHIFT_ADC_PWR12_MANUAL 1
|
||||
#define BIT_MASK_ADC_PWR12_MANUAL 0x1
|
||||
#define BIT_CTRL_ADC_PWR12_MANUAL(x) (((x) & BIT_MASK_ADC_PWR12_MANUAL) << BIT_SHIFT_ADC_PWR12_MANUAL)
|
||||
|
||||
#define BIT_ADC_PWR_AUTO BIT(0)
|
||||
#define BIT_SHIFT_ADC_PWR_AUTO 0
|
||||
#define BIT_MASK_ADC_PWR_AUTO 0x1
|
||||
#define BIT_CTRL_ADC_PWR_AUTO(x) (((x) & BIT_MASK_ADC_PWR_AUTO) << BIT_SHIFT_ADC_PWR_AUTO)
|
||||
|
||||
|
||||
//2 REG_ADC_ANAPAR_AD0
|
||||
|
||||
#define BIT_SHIFT_ADC_ANAPAR_AD0 2
|
||||
#define BIT_MASK_ADC_ANAPAR_AD0 0x3fffffff
|
||||
#define BIT_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
|
||||
#define BIT_CTRL_ADC_ANAPAR_AD0(x) (((x) & BIT_MASK_ADC_ANAPAR_AD0) << BIT_SHIFT_ADC_ANAPAR_AD0)
|
||||
#define BIT_GET_ADC_ANAPAR_AD0(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD0) & BIT_MASK_ADC_ANAPAR_AD0)
|
||||
|
||||
#define BIT_ADC_AUDIO_EN BIT(1)
|
||||
#define BIT_SHIFT_ADC_AUDIO_EN 1
|
||||
#define BIT_MASK_ADC_AUDIO_EN 0x1
|
||||
#define BIT_CTRL_ADC_AUDIO_EN(x) (((x) & BIT_MASK_ADC_AUDIO_EN) << BIT_SHIFT_ADC_AUDIO_EN)
|
||||
|
||||
#define BIT_ADC_EN_MANUAL BIT(0)
|
||||
#define BIT_SHIFT_ADC_EN_MANUAL 0
|
||||
#define BIT_MASK_ADC_EN_MANUAL 0x1
|
||||
#define BIT_CTRL_ADC_EN_MANUAL(x) (((x) & BIT_MASK_ADC_EN_MANUAL) << BIT_SHIFT_ADC_EN_MANUAL)
|
||||
|
||||
|
||||
//2 REG_ADC_ANAPAR_AD1
|
||||
|
||||
#define BIT_SHIFT_ADC_ANAPAR_AD1 0
|
||||
#define BIT_MASK_ADC_ANAPAR_AD1 0xffffffffL
|
||||
#define BIT_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
|
||||
#define BIT_CTRL_ADC_ANAPAR_AD1(x) (((x) & BIT_MASK_ADC_ANAPAR_AD1) << BIT_SHIFT_ADC_ANAPAR_AD1)
|
||||
#define BIT_GET_ADC_ANAPAR_AD1(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD1) & BIT_MASK_ADC_ANAPAR_AD1)
|
||||
|
||||
|
||||
//2 REG_ADC_ANAPAR_AD2
|
||||
|
||||
#define BIT_SHIFT_ADC_ANAPAR_AD2 0
|
||||
#define BIT_MASK_ADC_ANAPAR_AD2 0xffffffffL
|
||||
#define BIT_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
|
||||
#define BIT_CTRL_ADC_ANAPAR_AD2(x) (((x) & BIT_MASK_ADC_ANAPAR_AD2) << BIT_SHIFT_ADC_ANAPAR_AD2)
|
||||
#define BIT_GET_ADC_ANAPAR_AD2(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD2) & BIT_MASK_ADC_ANAPAR_AD2)
|
||||
|
||||
|
||||
//2 REG_ADC_ANAPAR_AD3
|
||||
|
||||
#define BIT_SHIFT_ADC_ANAPAR_AD3 0
|
||||
#define BIT_MASK_ADC_ANAPAR_AD3 0xffffffffL
|
||||
#define BIT_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
|
||||
#define BIT_CTRL_ADC_ANAPAR_AD3(x) (((x) & BIT_MASK_ADC_ANAPAR_AD3) << BIT_SHIFT_ADC_ANAPAR_AD3)
|
||||
#define BIT_GET_ADC_ANAPAR_AD3(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD3) & BIT_MASK_ADC_ANAPAR_AD3)
|
||||
|
||||
|
||||
//2 REG_ADC_ANAPAR_AD4
|
||||
|
||||
#define BIT_SHIFT_ADC_ANAPAR_AD4 0
|
||||
#define BIT_MASK_ADC_ANAPAR_AD4 0xffffffffL
|
||||
#define BIT_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
|
||||
#define BIT_CTRL_ADC_ANAPAR_AD4(x) (((x) & BIT_MASK_ADC_ANAPAR_AD4) << BIT_SHIFT_ADC_ANAPAR_AD4)
|
||||
#define BIT_GET_ADC_ANAPAR_AD4(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD4) & BIT_MASK_ADC_ANAPAR_AD4)
|
||||
|
||||
|
||||
//2 REG_ADC_ANAPAR_AD5
|
||||
|
||||
#define BIT_SHIFT_ADC_ANAPAR_AD5 0
|
||||
#define BIT_MASK_ADC_ANAPAR_AD5 0xffffffffL
|
||||
#define BIT_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
|
||||
#define BIT_CTRL_ADC_ANAPAR_AD5(x) (((x) & BIT_MASK_ADC_ANAPAR_AD5) << BIT_SHIFT_ADC_ANAPAR_AD5)
|
||||
#define BIT_GET_ADC_ANAPAR_AD5(x) (((x) >> BIT_SHIFT_ADC_ANAPAR_AD5) & BIT_MASK_ADC_ANAPAR_AD5)
|
||||
|
||||
|
||||
//2 REG_ADC_CALI_DATA
|
||||
|
||||
#define BIT_SHIFT_ADC_CALI_DATA_6 16
|
||||
#define BIT_MASK_ADC_CALI_DATA_6 0xffff
|
||||
#define BIT_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
|
||||
#define BIT_CTRL_ADC_CALI_DATA_6(x) (((x) & BIT_MASK_ADC_CALI_DATA_6) << BIT_SHIFT_ADC_CALI_DATA_6)
|
||||
#define BIT_GET_ADC_CALI_DATA_6(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_6) & BIT_MASK_ADC_CALI_DATA_6)
|
||||
|
||||
|
||||
#define BIT_SHIFT_ADC_CALI_DATA_0 0
|
||||
#define BIT_MASK_ADC_CALI_DATA_0 0xffff
|
||||
#define BIT_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
|
||||
#define BIT_CTRL_ADC_CALI_DATA_0(x) (((x) & BIT_MASK_ADC_CALI_DATA_0) << BIT_SHIFT_ADC_CALI_DATA_0)
|
||||
#define BIT_GET_ADC_CALI_DATA_0(x) (((x) >> BIT_SHIFT_ADC_CALI_DATA_0) & BIT_MASK_ADC_CALI_DATA_0)
|
||||
|
||||
//================ Register Reg Field =========================
|
||||
#define REG_ADC_FIFO_READ 0x0000
|
||||
#define REG_ADC_CONTROL 0x0004
|
||||
#define REG_ADC_INTR_EN 0x0008
|
||||
#define REG_ADC_INTR_STS 0x000C
|
||||
#define REG_ADC_COMP_VALUE_L 0x0010
|
||||
#define REG_ADC_COMP_VALUE_H 0x0014
|
||||
#define REG_ADC_COMP_SET 0x0018
|
||||
#define REG_ADC_POWER 0x001C
|
||||
#define REG_ADC_ANAPAR_AD0 0x0020
|
||||
#define REG_ADC_ANAPAR_AD1 0x0024
|
||||
#define REG_ADC_ANAPAR_AD2 0x0028
|
||||
#define REG_ADC_ANAPAR_AD3 0x002C
|
||||
#define REG_ADC_ANAPAR_AD4 0x0030
|
||||
#define REG_ADC_ANAPAR_AD5 0x0034
|
||||
#define REG_ADC_CALI_DATA 0x0038
|
||||
|
||||
//================ ADC HAL related enumeration ==================
|
||||
|
||||
//================ ADC Function Prototypes =====================
|
||||
#define HAL_ADC_WRITE32(addr, value) HAL_WRITE32(ADC_REG_BASE,addr,value)
|
||||
#define HAL_ADC_READ32(addr) HAL_READ32(ADC_REG_BASE,addr)
|
||||
|
||||
RTK_STATUS HalADCInit8195a(IN VOID *Data);
|
||||
RTK_STATUS HalADCDeInit8195a(IN VOID *Data);
|
||||
RTK_STATUS HalADCEnableRtl8195a(IN VOID *Data);
|
||||
RTK_STATUS HalADCIntrCtrl8195a(IN VOID *Data);
|
||||
u32 HalADCReceiveRtl8195a(IN VOID *Data);
|
||||
u32 HalADCReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,294 @@
|
|||
#ifndef _RTL8195A_DAC_H_
|
||||
#define _RTL8195A_DAC_H_
|
||||
|
||||
//================ Register Bit Field ==========================
|
||||
//2 REG_DAC0_FIFO_WR
|
||||
|
||||
#define BIT_SHIFT_DAC0_FIFO_WO 0
|
||||
#define BIT_MASK_DAC0_FIFO_WO 0xffffffffL
|
||||
#define BIT_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
|
||||
#define BIT_CTRL_DAC0_FIFO_WO(x) (((x) & BIT_MASK_DAC0_FIFO_WO) << BIT_SHIFT_DAC0_FIFO_WO)
|
||||
#define BIT_GET_DAC0_FIFO_WO(x) (((x) >> BIT_SHIFT_DAC0_FIFO_WO) & BIT_MASK_DAC0_FIFO_WO)
|
||||
|
||||
|
||||
//2 REG_DAC_CTRL
|
||||
|
||||
#define BIT_SHIFT_DAC_DELTA_SIGMA 25
|
||||
#define BIT_MASK_DAC_DELTA_SIGMA 0x7
|
||||
#define BIT_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
|
||||
#define BIT_CTRL_DAC_DELTA_SIGMA(x) (((x) & BIT_MASK_DAC_DELTA_SIGMA) << BIT_SHIFT_DAC_DELTA_SIGMA)
|
||||
#define BIT_GET_DAC_DELTA_SIGMA(x) (((x) >> BIT_SHIFT_DAC_DELTA_SIGMA) & BIT_MASK_DAC_DELTA_SIGMA)
|
||||
|
||||
#define BIT_DAC_BYPASS_DSC BIT(24)
|
||||
#define BIT_SHIFT_DAC_BYPASS_DSC 24
|
||||
#define BIT_MASK_DAC_BYPASS_DSC 0x1
|
||||
#define BIT_CTRL_DAC_BYPASS_DSC(x) (((x) & BIT_MASK_DAC_BYPASS_DSC) << BIT_SHIFT_DAC_BYPASS_DSC)
|
||||
|
||||
|
||||
#define BIT_SHIFT_DAC_DSC_DBG_SEL 19
|
||||
#define BIT_MASK_DAC_DSC_DBG_SEL 0x3
|
||||
#define BIT_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
|
||||
#define BIT_CTRL_DAC_DSC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DSC_DBG_SEL) << BIT_SHIFT_DAC_DSC_DBG_SEL)
|
||||
#define BIT_GET_DAC_DSC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DSC_DBG_SEL) & BIT_MASK_DAC_DSC_DBG_SEL)
|
||||
|
||||
|
||||
#define BIT_SHIFT_DAC_DBG_SEL 16
|
||||
#define BIT_MASK_DAC_DBG_SEL 0x7
|
||||
#define BIT_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
|
||||
#define BIT_CTRL_DAC_DBG_SEL(x) (((x) & BIT_MASK_DAC_DBG_SEL) << BIT_SHIFT_DAC_DBG_SEL)
|
||||
#define BIT_GET_DAC_DBG_SEL(x) (((x) >> BIT_SHIFT_DAC_DBG_SEL) & BIT_MASK_DAC_DBG_SEL)
|
||||
|
||||
|
||||
#define BIT_SHIFT_DAC_BURST_SIZE 8
|
||||
#define BIT_MASK_DAC_BURST_SIZE 0xf
|
||||
#define BIT_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
|
||||
#define BIT_CTRL_DAC_BURST_SIZE(x) (((x) & BIT_MASK_DAC_BURST_SIZE) << BIT_SHIFT_DAC_BURST_SIZE)
|
||||
#define BIT_GET_DAC_BURST_SIZE(x) (((x) >> BIT_SHIFT_DAC_BURST_SIZE) & BIT_MASK_DAC_BURST_SIZE)
|
||||
|
||||
#define BIT_DAC_FILTER_SETTLE BIT(4)
|
||||
#define BIT_SHIFT_DAC_FILTER_SETTLE 4
|
||||
#define BIT_MASK_DAC_FILTER_SETTLE 0x1
|
||||
#define BIT_CTRL_DAC_FILTER_SETTLE(x) (((x) & BIT_MASK_DAC_FILTER_SETTLE) << BIT_SHIFT_DAC_FILTER_SETTLE)
|
||||
|
||||
#define BIT_DAC_OV_OPTION BIT(3)
|
||||
#define BIT_SHIFT_DAC_OV_OPTION 3
|
||||
#define BIT_MASK_DAC_OV_OPTION 0x1
|
||||
#define BIT_CTRL_DAC_OV_OPTION(x) (((x) & BIT_MASK_DAC_OV_OPTION) << BIT_SHIFT_DAC_OV_OPTION)
|
||||
|
||||
#define BIT_DAC_ENDIAN BIT(2)
|
||||
#define BIT_SHIFT_DAC_ENDIAN 2
|
||||
#define BIT_MASK_DAC_ENDIAN 0x1
|
||||
#define BIT_CTRL_DAC_ENDIAN(x) (((x) & BIT_MASK_DAC_ENDIAN) << BIT_SHIFT_DAC_ENDIAN)
|
||||
|
||||
#define BIT_DAC_SPEED BIT(1)
|
||||
#define BIT_SHIFT_DAC_SPEED 1
|
||||
#define BIT_MASK_DAC_SPEED 0x1
|
||||
#define BIT_CTRL_DAC_SPEED(x) (((x) & BIT_MASK_DAC_SPEED) << BIT_SHIFT_DAC_SPEED)
|
||||
|
||||
#define BIT_DAC_FIFO_EN BIT(0)
|
||||
#define BIT_SHIFT_DAC_FIFO_EN 0
|
||||
#define BIT_MASK_DAC_FIFO_EN 0x1
|
||||
#define BIT_CTRL_DAC_FIFO_EN(x) (((x) & BIT_MASK_DAC_FIFO_EN) << BIT_SHIFT_DAC_FIFO_EN)
|
||||
|
||||
|
||||
//2 REG_DAC_INTR_CTRL
|
||||
#define BIT_DAC_DSC_OVERFLOW1_EN BIT(6)
|
||||
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_EN 6
|
||||
#define BIT_MASK_DAC_DSC_OVERFLOW1_EN 0x1
|
||||
#define BIT_CTRL_DAC_DSC_OVERFLOW1_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW1_EN)
|
||||
|
||||
#define BIT_DAC_DSC_OVERFLOW0_EN BIT(5)
|
||||
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_EN 5
|
||||
#define BIT_MASK_DAC_DSC_OVERFLOW0_EN 0x1
|
||||
#define BIT_CTRL_DAC_DSC_OVERFLOW0_EN(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_EN) << BIT_SHIFT_DAC_DSC_OVERFLOW0_EN)
|
||||
|
||||
#define BIT_DAC__WRITE_ERROR_EN BIT(4)
|
||||
#define BIT_SHIFT_DAC__WRITE_ERROR_EN 4
|
||||
#define BIT_MASK_DAC__WRITE_ERROR_EN 0x1
|
||||
#define BIT_CTRL_DAC__WRITE_ERROR_EN(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_EN) << BIT_SHIFT_DAC__WRITE_ERROR_EN)
|
||||
|
||||
#define BIT_DAC_FIFO_STOP_EN BIT(3)
|
||||
#define BIT_SHIFT_DAC_FIFO_STOP_EN 3
|
||||
#define BIT_MASK_DAC_FIFO_STOP_EN 0x1
|
||||
#define BIT_CTRL_DAC_FIFO_STOP_EN(x) (((x) & BIT_MASK_DAC_FIFO_STOP_EN) << BIT_SHIFT_DAC_FIFO_STOP_EN)
|
||||
|
||||
#define BIT_DAC_FIFO_OVERFLOW_EN BIT(2)
|
||||
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_EN 2
|
||||
#define BIT_MASK_DAC_FIFO_OVERFLOW_EN 0x1
|
||||
#define BIT_CTRL_DAC_FIFO_OVERFLOW_EN(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_EN) << BIT_SHIFT_DAC_FIFO_OVERFLOW_EN)
|
||||
|
||||
#define BIT_DAC_FIFO_WR_REQ_EN BIT(1)
|
||||
#define BIT_SHIFT_DAC_FIFO_WR_REQ_EN 1
|
||||
#define BIT_MASK_DAC_FIFO_WR_REQ_EN 0x1
|
||||
#define BIT_CTRL_DAC_FIFO_WR_REQ_EN(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_EN) << BIT_SHIFT_DAC_FIFO_WR_REQ_EN)
|
||||
|
||||
#define BIT_DAC_FIFO_FULL_EN BIT(0)
|
||||
#define BIT_SHIFT_DAC_FIFO_FULL_EN 0
|
||||
#define BIT_MASK_DAC_FIFO_FULL_EN 0x1
|
||||
#define BIT_CTRL_DAC_FIFO_FULL_EN(x) (((x) & BIT_MASK_DAC_FIFO_FULL_EN) << BIT_SHIFT_DAC_FIFO_FULL_EN)
|
||||
|
||||
|
||||
//2 REG_DAC_INTR_STS
|
||||
#define BIT_DAC_DSC_OVERFLOW1_ST BIT(6)
|
||||
#define BIT_SHIFT_DAC_DSC_OVERFLOW1_ST 6
|
||||
#define BIT_MASK_DAC_DSC_OVERFLOW1_ST 0x1
|
||||
#define BIT_CTRL_DAC_DSC_OVERFLOW1_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW1_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW1_ST)
|
||||
|
||||
#define BIT_DAC_DSC_OVERFLOW0_ST BIT(5)
|
||||
#define BIT_SHIFT_DAC_DSC_OVERFLOW0_ST 5
|
||||
#define BIT_MASK_DAC_DSC_OVERFLOW0_ST 0x1
|
||||
#define BIT_CTRL_DAC_DSC_OVERFLOW0_ST(x) (((x) & BIT_MASK_DAC_DSC_OVERFLOW0_ST) << BIT_SHIFT_DAC_DSC_OVERFLOW0_ST)
|
||||
|
||||
#define BIT_DAC__WRITE_ERROR_ST BIT(4)
|
||||
#define BIT_SHIFT_DAC__WRITE_ERROR_ST 4
|
||||
#define BIT_MASK_DAC__WRITE_ERROR_ST 0x1
|
||||
#define BIT_CTRL_DAC__WRITE_ERROR_ST(x) (((x) & BIT_MASK_DAC__WRITE_ERROR_ST) << BIT_SHIFT_DAC__WRITE_ERROR_ST)
|
||||
|
||||
#define BIT_DAC_FIFO_STOP_ST BIT(3)
|
||||
#define BIT_SHIFT_DAC_FIFO_STOP_ST 3
|
||||
#define BIT_MASK_DAC_FIFO_STOP_ST 0x1
|
||||
#define BIT_CTRL_DAC_FIFO_STOP_ST(x) (((x) & BIT_MASK_DAC_FIFO_STOP_ST) << BIT_SHIFT_DAC_FIFO_STOP_ST)
|
||||
|
||||
#define BIT_DAC_FIFO_OVERFLOW_ST BIT(2)
|
||||
#define BIT_SHIFT_DAC_FIFO_OVERFLOW_ST 2
|
||||
#define BIT_MASK_DAC_FIFO_OVERFLOW_ST 0x1
|
||||
#define BIT_CTRL_DAC_FIFO_OVERFLOW_ST(x) (((x) & BIT_MASK_DAC_FIFO_OVERFLOW_ST) << BIT_SHIFT_DAC_FIFO_OVERFLOW_ST)
|
||||
|
||||
#define BIT_DAC_FIFO_WR_REQ_ST BIT(1)
|
||||
#define BIT_SHIFT_DAC_FIFO_WR_REQ_ST 1
|
||||
#define BIT_MASK_DAC_FIFO_WR_REQ_ST 0x1
|
||||
#define BIT_CTRL_DAC_FIFO_WR_REQ_ST(x) (((x) & BIT_MASK_DAC_FIFO_WR_REQ_ST) << BIT_SHIFT_DAC_FIFO_WR_REQ_ST)
|
||||
|
||||
#define BIT_DAC_FIFO_FULL_ST BIT(0)
|
||||
#define BIT_SHIFT_DAC_FIFO_FULL_ST 0
|
||||
#define BIT_MASK_DAC_FIFO_FULL_ST 0x1
|
||||
#define BIT_CTRL_DAC_FIFO_FULL_ST(x) (((x) & BIT_MASK_DAC_FIFO_FULL_ST) << BIT_SHIFT_DAC_FIFO_FULL_ST)
|
||||
|
||||
|
||||
//2 REG_DAC_PWR_CTRL
|
||||
|
||||
#define BIT_SHIFT_DAC_PWR_CUT_CNTR 16
|
||||
#define BIT_MASK_DAC_PWR_CUT_CNTR 0xff
|
||||
#define BIT_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
|
||||
#define BIT_CTRL_DAC_PWR_CUT_CNTR(x) (((x) & BIT_MASK_DAC_PWR_CUT_CNTR) << BIT_SHIFT_DAC_PWR_CUT_CNTR)
|
||||
#define BIT_GET_DAC_PWR_CUT_CNTR(x) (((x) >> BIT_SHIFT_DAC_PWR_CUT_CNTR) & BIT_MASK_DAC_PWR_CUT_CNTR)
|
||||
|
||||
#define BIT_ST_DAC_FIFO_ON BIT(11)
|
||||
#define BIT_SHIFT_ST_DAC_FIFO_ON 11
|
||||
#define BIT_MASK_ST_DAC_FIFO_ON 0x1
|
||||
#define BIT_CTRL_ST_DAC_FIFO_ON(x) (((x) & BIT_MASK_ST_DAC_FIFO_ON) << BIT_SHIFT_ST_DAC_FIFO_ON)
|
||||
|
||||
#define BIT_ST_DAC_ISO_ON BIT(10)
|
||||
#define BIT_SHIFT_ST_DAC_ISO_ON 10
|
||||
#define BIT_MASK_ST_DAC_ISO_ON 0x1
|
||||
#define BIT_CTRL_ST_DAC_ISO_ON(x) (((x) & BIT_MASK_ST_DAC_ISO_ON) << BIT_SHIFT_ST_DAC_ISO_ON)
|
||||
|
||||
#define BIT_ST_DAC_PWR33_ON BIT(9)
|
||||
#define BIT_SHIFT_ST_DAC_PWR33_ON 9
|
||||
#define BIT_MASK_ST_DAC_PWR33_ON 0x1
|
||||
#define BIT_CTRL_ST_DAC_PWR33_ON(x) (((x) & BIT_MASK_ST_DAC_PWR33_ON) << BIT_SHIFT_ST_DAC_PWR33_ON)
|
||||
|
||||
#define BIT_ST_DAC_PWR12_ON BIT(8)
|
||||
#define BIT_SHIFT_ST_DAC_PWR12_ON 8
|
||||
#define BIT_MASK_ST_DAC_PWR12_ON 0x1
|
||||
#define BIT_CTRL_ST_DAC_PWR12_ON(x) (((x) & BIT_MASK_ST_DAC_PWR12_ON) << BIT_SHIFT_ST_DAC_PWR12_ON)
|
||||
|
||||
#define BIT_DAC_ISO_MANU BIT(3)
|
||||
#define BIT_SHIFT_DAC_ISO_MANU 3
|
||||
#define BIT_MASK_DAC_ISO_MANU 0x1
|
||||
#define BIT_CTRL_DAC_ISO_MANU(x) (((x) & BIT_MASK_DAC_ISO_MANU) << BIT_SHIFT_DAC_ISO_MANU)
|
||||
|
||||
#define BIT_DAC_PWR33_MANU BIT(2)
|
||||
#define BIT_SHIFT_DAC_PWR33_MANU 2
|
||||
#define BIT_MASK_DAC_PWR33_MANU 0x1
|
||||
#define BIT_CTRL_DAC_PWR33_MANU(x) (((x) & BIT_MASK_DAC_PWR33_MANU) << BIT_SHIFT_DAC_PWR33_MANU)
|
||||
|
||||
#define BIT_DAC_PWR12_MANU BIT(1)
|
||||
#define BIT_SHIFT_DAC_PWR12_MANU 1
|
||||
#define BIT_MASK_DAC_PWR12_MANU 0x1
|
||||
#define BIT_CTRL_DAC_PWR12_MANU(x) (((x) & BIT_MASK_DAC_PWR12_MANU) << BIT_SHIFT_DAC_PWR12_MANU)
|
||||
|
||||
#define BIT_DAC_PWR_AUTO BIT(0)
|
||||
#define BIT_SHIFT_DAC_PWR_AUTO 0
|
||||
#define BIT_MASK_DAC_PWR_AUTO 0x1
|
||||
#define BIT_CTRL_DAC_PWR_AUTO(x) (((x) & BIT_MASK_DAC_PWR_AUTO) << BIT_SHIFT_DAC_PWR_AUTO)
|
||||
|
||||
|
||||
//2 REG_DAC_ANAPAR_DA0
|
||||
|
||||
#define BIT_SHIFT_PWR_ALL_CNTR 12
|
||||
#define BIT_MASK_PWR_ALL_CNTR 0xfffff
|
||||
#define BIT_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
|
||||
#define BIT_CTRL_PWR_ALL_CNTR(x) (((x) & BIT_MASK_PWR_ALL_CNTR) << BIT_SHIFT_PWR_ALL_CNTR)
|
||||
#define BIT_GET_PWR_ALL_CNTR(x) (((x) >> BIT_SHIFT_PWR_ALL_CNTR) & BIT_MASK_PWR_ALL_CNTR)
|
||||
|
||||
|
||||
#define BIT_SHIFT_PWR_FUP_CNTR 0
|
||||
#define BIT_MASK_PWR_FUP_CNTR 0xfff
|
||||
#define BIT_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
|
||||
#define BIT_CTRL_PWR_FUP_CNTR(x) (((x) & BIT_MASK_PWR_FUP_CNTR) << BIT_SHIFT_PWR_FUP_CNTR)
|
||||
#define BIT_GET_PWR_FUP_CNTR(x) (((x) >> BIT_SHIFT_PWR_FUP_CNTR) & BIT_MASK_PWR_FUP_CNTR)
|
||||
|
||||
|
||||
//2 REG_DAC_ANAPAR_DA1
|
||||
#define BIT_FUP_EN BIT(31)
|
||||
#define BIT_SHIFT_FUP_EN 31
|
||||
#define BIT_MASK_FUP_EN 0x1
|
||||
#define BIT_CTRL_FUP_EN(x) (((x) & BIT_MASK_FUP_EN) << BIT_SHIFT_FUP_EN)
|
||||
|
||||
|
||||
#define BIT_SHIFT_ANAPAR_DA 8
|
||||
#define BIT_MASK_ANAPAR_DA 0x7fffff
|
||||
#define BIT_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
|
||||
#define BIT_CTRL_ANAPAR_DA(x) (((x) & BIT_MASK_ANAPAR_DA) << BIT_SHIFT_ANAPAR_DA)
|
||||
#define BIT_GET_ANAPAR_DA(x) (((x) >> BIT_SHIFT_ANAPAR_DA) & BIT_MASK_ANAPAR_DA)
|
||||
|
||||
#define BIT_D_POW_DACVREF BIT(7)
|
||||
#define BIT_SHIFT_D_POW_DACVREF 7
|
||||
#define BIT_MASK_D_POW_DACVREF 0x1
|
||||
#define BIT_CTRL_D_POW_DACVREF(x) (((x) & BIT_MASK_D_POW_DACVREF) << BIT_SHIFT_D_POW_DACVREF)
|
||||
|
||||
#define BIT_D_POW_VREF2 BIT(6)
|
||||
#define BIT_SHIFT_D_POW_VREF2 6
|
||||
#define BIT_MASK_D_POW_VREF2 0x1
|
||||
#define BIT_CTRL_D_POW_VREF2(x) (((x) & BIT_MASK_D_POW_VREF2) << BIT_SHIFT_D_POW_VREF2)
|
||||
|
||||
#define BIT_D_POW_MBIAS BIT(5)
|
||||
#define BIT_SHIFT_D_POW_MBIAS 5
|
||||
#define BIT_MASK_D_POW_MBIAS 0x1
|
||||
#define BIT_CTRL_D_POW_MBIAS(x) (((x) & BIT_MASK_D_POW_MBIAS) << BIT_SHIFT_D_POW_MBIAS)
|
||||
|
||||
#define BIT_D_POW_DIV4 BIT(4)
|
||||
#define BIT_SHIFT_D_POW_DIV4 4
|
||||
#define BIT_MASK_D_POW_DIV4 0x1
|
||||
#define BIT_CTRL_D_POW_DIV4(x) (((x) & BIT_MASK_D_POW_DIV4) << BIT_SHIFT_D_POW_DIV4)
|
||||
|
||||
#define BIT_D_POW_DF1SE_R BIT(3)
|
||||
#define BIT_SHIFT_D_POW_DF1SE_R 3
|
||||
#define BIT_MASK_D_POW_DF1SE_R 0x1
|
||||
#define BIT_CTRL_D_POW_DF1SE_R(x) (((x) & BIT_MASK_D_POW_DF1SE_R) << BIT_SHIFT_D_POW_DF1SE_R)
|
||||
|
||||
#define BIT_D_POW_DF2SE_L BIT(2)
|
||||
#define BIT_SHIFT_D_POW_DF2SE_L 2
|
||||
#define BIT_MASK_D_POW_DF2SE_L 0x1
|
||||
#define BIT_CTRL_D_POW_DF2SE_L(x) (((x) & BIT_MASK_D_POW_DF2SE_L) << BIT_SHIFT_D_POW_DF2SE_L)
|
||||
|
||||
#define BIT_D_POW_DAC_R BIT(1)
|
||||
#define BIT_SHIFT_D_POW_DAC_R 1
|
||||
#define BIT_MASK_D_POW_DAC_R 0x1
|
||||
#define BIT_CTRL_D_POW_DAC_R(x) (((x) & BIT_MASK_D_POW_DAC_R) << BIT_SHIFT_D_POW_DAC_R)
|
||||
|
||||
#define BIT_D_POW_DAC_L BIT(0)
|
||||
#define BIT_SHIFT_D_POW_DAC_L 0
|
||||
#define BIT_MASK_D_POW_DAC_L 0x1
|
||||
#define BIT_CTRL_D_POW_DAC_L(x) (((x) & BIT_MASK_D_POW_DAC_L) << BIT_SHIFT_D_POW_DAC_L)
|
||||
|
||||
|
||||
//================ Register Reg Field =========================
|
||||
#define REG_DAC0_FIFO_WR 0x0000
|
||||
#define REG_DAC_CTRL 0x0004
|
||||
#define REG_DAC_INTR_CTRL 0x0008
|
||||
#define REG_DAC_INTR_STS 0x000C
|
||||
#define REG_DAC_PWR_CTRL 0x0010
|
||||
#define REG_DAC_ANAPAR_DA0 0x0014
|
||||
#define REG_DAC_ANAPAR_DA1 0x0018
|
||||
|
||||
|
||||
//================ DAC HAL related enumeration ==================
|
||||
|
||||
|
||||
//================ DAC HAL Macro ===========================
|
||||
#define HAL_DAC_WRITE32(dacidx, addr, value) HAL_WRITE32(DAC_REG_BASE+dacidx*0x800 \
|
||||
,addr,value)
|
||||
#define HAL_DAC_READ32(dacidx, addr) HAL_READ32(DAC_REG_BASE+dacidx*0x800,addr)
|
||||
|
||||
|
||||
//================ DAC Function Prototypes =====================
|
||||
RTK_STATUS HalDACInit8195a(IN VOID *Data);
|
||||
RTK_STATUS HalDACDeInit8195a(IN VOID *Data);
|
||||
RTK_STATUS HalDACEnableRtl8195a(IN VOID *Data);
|
||||
RTK_STATUS HalDACIntrCtrl8195a(IN VOID *Data);
|
||||
u8 HalDACSendRtl8195a(IN VOID *Data);
|
||||
u32 HalDACReadRegRtl8195a(IN VOID *Data,IN u8 I2CReg);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,528 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RTL8195A_GDMA_H_
|
||||
#define _RTL8195A_GDMA_H_
|
||||
|
||||
// Define GDMA Handshake interface with peripheral, 0 -> GDMA0, 1-> GDMA1
|
||||
// Set this Hnadshake interface map to register REG_PESOC_SOC_CTRL
|
||||
#define GDMA_HANDSHAKE_UART0_TX 0
|
||||
#define GDMA_HANDSHAKE_UART0_RX 1
|
||||
#define GDMA_HANDSHAKE_UART1_TX 2
|
||||
#define GDMA_HANDSHAKE_UART1_RX 3
|
||||
#define GDMA_HANDSHAKE_UART2_TX 14 // Only on GDMA 0, hardware fixed
|
||||
#define GDMA_HANDSHAKE_UART2_RX 14 // Only on GDMA 1, hardware fixed
|
||||
|
||||
#define GDMA_HANDSHAKE_SSI0_TX 4
|
||||
#define GDMA_HANDSHAKE_SSI0_RX 5
|
||||
#define GDMA_HANDSHAKE_SSI1_TX 6
|
||||
#define GDMA_HANDSHAKE_SSI1_RX 7
|
||||
#define GDMA_HANDSHAKE_SSI2_TX 15 // Only on GDMA 0, hardware fixed
|
||||
#define GDMA_HANDSHAKE_SSI2_RX 15 // Only on GDMA 1, hardware fixed
|
||||
|
||||
#define GDMA_HANDSHAKE_I2C0_TX 8
|
||||
#define GDMA_HANDSHAKE_I2C0_RX 9
|
||||
#define GDMA_HANDSHAKE_I2C1_TX 10
|
||||
#define GDMA_HANDSHAKE_I2C1_RX 11
|
||||
|
||||
#define GDMA_HANDSHAKE_ADC 12
|
||||
#define GDMA_HANDSHAKE_DAC0 13 // Only on GDMA 0, hardware fixed
|
||||
#define GDMA_HANDSHAKE_DAC1 13 // Only on GDMA 1, hardware fixed
|
||||
|
||||
#define HAL_GDMAX_READ32(GdmaIndex, addr) \
|
||||
HAL_READ32(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
|
||||
#define HAL_GDMAX_WRITE32(GdmaIndex, addr, value) \
|
||||
HAL_WRITE32((GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF)), addr, value)
|
||||
#define HAL_GDMAX_READ16(GdmaIndex, addr) \
|
||||
HAL_READ16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
|
||||
#define HAL_GDMAX_WRITE16(GdmaIndex, addr, value) \
|
||||
HAL_WRITE16(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
|
||||
#define HAL_GDMAX_READ8(GdmaIndex, addr) \
|
||||
HAL_READ8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr)
|
||||
#define HAL_GDMAX_WRITE8(GdmaIndex, addr, value) \
|
||||
HAL_WRITE8(GDMA0_REG_BASE+ (GdmaIndex*GDMA1_REG_OFF), addr, value)
|
||||
|
||||
|
||||
#define GDMA_CH_MAX 0x06
|
||||
|
||||
#define REG_GDMA_CH_OFF 0x058
|
||||
#define REG_GDMA_CH_SAR 0x000
|
||||
#define REG_GDMA_CH_DAR 0x008
|
||||
#define REG_GDMA_CH_LLP 0x010
|
||||
#define REG_GDMA_CH_CTL 0x018
|
||||
#define REG_GDMA_CH_SSTAT 0x020
|
||||
#define REG_GDMA_CH_DSTAT 0x028
|
||||
#define REG_GDMA_CH_SSTATAR 0x030
|
||||
#define REG_GDMA_CH_DSTATAR 0x038
|
||||
#define REG_GDMA_CH_CFG 0x040
|
||||
#define REG_GDMA_CH_SGR 0x048
|
||||
#define REG_GDMA_CH_DSR 0x050
|
||||
|
||||
#define MAX_DMA_BLOCK_SIZE 4092
|
||||
|
||||
//3 Interrupt Registers
|
||||
#define REG_GDMA_RAW_INT_BASE 0x2C0
|
||||
#define REG_GDMA_RAW_INT_TFR 0x2C0
|
||||
#define REG_GDMA_RAW_INT_BLOCK 0x2c8
|
||||
#define REG_GDMA_RAW_INT_SRC_TRAN 0x2D0
|
||||
#define REG_GDMA_RAW_INT_DST_TRAN 0x2D8
|
||||
#define REG_GDMA_RAW_INT_ERR 0x2E0
|
||||
|
||||
#define REG_GDMA_STATUS_INT_BASE 0x2E8
|
||||
#define REG_GDMA_STATUS_INT_TFR 0x2E8
|
||||
#define REG_GDMA_STATUS_INT_BLOCK 0x2F0
|
||||
#define REG_GDMA_STATUS_INT_SRC_TRAN 0x2F8
|
||||
#define REG_GDMA_STATUS_INT_DST_TRAN 0x300
|
||||
#define REG_GDMA_STATUS_INT_ERR 0x308
|
||||
|
||||
#define REG_GDMA_MASK_INT_BASE 0x310
|
||||
#define REG_GDMA_MASK_INT_TFR 0x310
|
||||
#define REG_GDMA_MASK_INT_BLOCK 0x318
|
||||
#define REG_GDMA_MASK_INT_SRC_TRAN 0x320
|
||||
#define REG_GDMA_MASK_INT_DST_TRAN 0x328
|
||||
#define REG_GDMA_MASK_INT_INT_ERR 0x330
|
||||
|
||||
#define REG_GDMA_CLEAR_INT_BASE 0x338
|
||||
#define REG_GDMA_CLEAR_INT_TFR 0x338
|
||||
#define REG_GDMA_CLEAR_INT_BLOCK 0x340
|
||||
#define REG_GDMA_CLEAR_INT_SRC_TRAN 0x348
|
||||
#define REG_GDMA_CLEAR_INT_DST_TRAN 0x350
|
||||
#define REG_GDMA_CLEAR_INT_ERR 0x358
|
||||
#define REG_GDMA_STATUS_INT 0x360
|
||||
|
||||
//3 Software handshaking Registers
|
||||
#define REG_GDMA_REQ_SRC 0x368
|
||||
#define REG_GDMA_REQ_DST 0x370
|
||||
#define REG_GDMA_REQ_SGL_REQ 0x378
|
||||
#define REG_GDMA_REQ_DST_REQ 0x380
|
||||
#define REG_GDMA_REQ_LST_SRC 0x388
|
||||
#define REG_GDMA_REQ_LST_DST 0x390
|
||||
|
||||
//3 Miscellaneous Registers
|
||||
#define REG_GDMA_DMAC_CFG 0x398
|
||||
#define REG_GDMA_CH_EN 0x3A0
|
||||
#define REG_GDMA_DMA_ID 0x3A8
|
||||
#define REG_GDMA_DMA_TEST 0x3B0
|
||||
#define REG_GDMA_DMA_COM_PARAMS6 0x3C8
|
||||
#define REG_GDMA_DMA_COM_PARAMS5 0x3D0
|
||||
#define REG_GDMA_DMA_COM_PARAMS4 0x3D8
|
||||
#define REG_GDMA_DMA_COM_PARAMS3 0x3E0
|
||||
#define REG_GDMA_DMA_COM_PARAMS2 0x3E8
|
||||
#define REG_GDMA_DMA_COM_PARAMS1 0x3F0
|
||||
#define REG_GDMA_DMA_COM_PARAMS0 0x3F8
|
||||
|
||||
//3 CTL Register Bit Control
|
||||
#define BIT_SHIFT_CTLX_LO_INT_EN 0
|
||||
#define BIT_MASK_CTLX_LO_INT_EN 0x1
|
||||
#define BIT_CTLX_LO_INT_EN(x)(((x) & BIT_MASK_CTLX_LO_INT_EN) << BIT_SHIFT_CTLX_LO_INT_EN)
|
||||
#define BIT_INVC_CTLX_LO_INT_EN (~(BIT_MASK_CTLX_LO_INT_EN << BIT_SHIFT_CTLX_LO_INT_EN))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_DST_TR_WIDTH 1
|
||||
#define BIT_MASK_CTLX_LO_DST_TR_WIDTH 0x7
|
||||
#define BIT_CTLX_LO_DST_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_DST_TR_WIDTH) << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH)
|
||||
#define BIT_INVC_CTLX_LO_DST_TR_WIDTH (~(BIT_MASK_CTLX_LO_DST_TR_WIDTH << BIT_SHIFT_CTLX_LO_DST_TR_WIDTH))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH 4
|
||||
#define BIT_MASK_CTLX_LO_SRC_TR_WIDTH 0x7
|
||||
#define BIT_CTLX_LO_SRC_TR_WIDTH(x) (((x) & BIT_MASK_CTLX_LO_SRC_TR_WIDTH) << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH)
|
||||
#define BIT_INVC_CTLX_LO_SRC_TR_WIDTH (~(BIT_MASK_CTLX_LO_SRC_TR_WIDTH << BIT_SHIFT_CTLX_LO_SRC_TR_WIDTH))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_DINC 7
|
||||
#define BIT_MASK_CTLX_LO_DINC 0x3
|
||||
#define BIT_CTLX_LO_DINC(x)(((x) & BIT_MASK_CTLX_LO_DINC) << BIT_SHIFT_CTLX_LO_DINC)
|
||||
#define BIT_INVC_CTLX_LO_DINC (~(BIT_MASK_CTLX_LO_DINC << BIT_SHIFT_CTLX_LO_DINC))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_SINC 9
|
||||
#define BIT_MASK_CTLX_LO_SINC 0x3
|
||||
#define BIT_CTLX_LO_SINC(x)(((x) & BIT_MASK_CTLX_LO_SINC) << BIT_SHIFT_CTLX_LO_SINC)
|
||||
#define BIT_INVC_CTLX_LO_SINC (~(BIT_MASK_CTLX_LO_SINC << BIT_SHIFT_CTLX_LO_SINC))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_DEST_MSIZE 11
|
||||
#define BIT_MASK_CTLX_LO_DEST_MSIZE 0x7
|
||||
#define BIT_CTLX_LO_DEST_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_DEST_MSIZE) << BIT_SHIFT_CTLX_LO_DEST_MSIZE)
|
||||
#define BIT_INVC_CTLX_LO_DEST_MSIZE (~(BIT_MASK_CTLX_LO_DEST_MSIZE << BIT_SHIFT_CTLX_LO_DEST_MSIZE))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_SRC_MSIZE 14
|
||||
#define BIT_MASK_CTLX_LO_SRC_MSIZE 0x7
|
||||
#define BIT_CTLX_LO_SRC_MSIZE(x)(((x) & BIT_MASK_CTLX_LO_SRC_MSIZE) << BIT_SHIFT_CTLX_LO_SRC_MSIZE)
|
||||
#define BIT_INVC_CTLX_LO_SRC_MSIZE (~(BIT_MASK_CTLX_LO_SRC_MSIZE << BIT_SHIFT_CTLX_LO_SRC_MSIZE))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_SRC_GATHER_EN 17
|
||||
#define BIT_MASK_CTLX_LO_SRC_GATHER_EN 0x1
|
||||
#define BIT_CTLX_LO_SRC_GATHER_EN(x)(((x) & BIT_MASK_CTLX_LO_SRC_GATHER_EN) << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN)
|
||||
#define BIT_INVC_CTLX_LO_SRC_GATHER_EN (~(BIT_MASK_CTLX_LO_SRC_GATHER_EN << BIT_SHIFT_CTLX_LO_SRC_GATHER_EN))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_DST_SCATTER_EN 18
|
||||
#define BIT_MASK_CTLX_LO_DST_SCATTER_EN 0x1
|
||||
#define BIT_CTLX_LO_DST_SCATTER_EN(x)(((x) & BIT_MASK_CTLX_LO_DST_SCATTER_EN) << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN)
|
||||
#define BIT_INVC_CTLX_LO_DST_SCATTER_EN (~(BIT_MASK_CTLX_LO_DST_SCATTER_EN << BIT_SHIFT_CTLX_LO_DST_SCATTER_EN))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_TT_FC 20
|
||||
#define BIT_MASK_CTLX_LO_TT_FC 0x7
|
||||
#define BIT_CTLX_LO_TT_FC(x)(((x) & BIT_MASK_CTLX_LO_TT_FC) << BIT_SHIFT_CTLX_LO_TT_FC)
|
||||
#define BIT_INVC_CTLX_LO_TT_FC (~(BIT_MASK_CTLX_LO_TT_FC << BIT_SHIFT_CTLX_LO_TT_FC))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_DMS 23
|
||||
#define BIT_MASK_CTLX_LO_DMS 0x3
|
||||
#define BIT_CTLX_LO_DMS(x)(((x) & BIT_MASK_CTLX_LO_DMS) << BIT_MASK_CTLX_LO_DMS)
|
||||
#define BIT_INVC_CTLX_LO_DMS (~(BIT_MASK_CTLX_LO_DMS << BIT_SHIFT_CTLX_LO_DMS))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_SMS 25
|
||||
#define BIT_MASK_CTLX_LO_SMS 0x3
|
||||
#define BIT_CTLX_LO_SMS(x)(((x) & BIT_MASK_CTLX_LO_SMS) << BIT_SHIFT_CTLX_LO_SMS)
|
||||
#define BIT_INVC_CTLX_LO_SMS (~(BIT_MASK_CTLX_LO_SMS << BIT_SHIFT_CTLX_LO_SMS))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_LLP_DST_EN 27
|
||||
#define BIT_MASK_CTLX_LO_LLP_DST_EN 0x1
|
||||
#define BIT_CTLX_LO_LLP_DST_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_DST_EN) << BIT_SHIFT_CTLX_LO_LLP_DST_EN)
|
||||
#define BIT_INVC_CTLX_LO_LLP_DST_EN (~(BIT_MASK_CTLX_LO_LLP_DST_EN << BIT_SHIFT_CTLX_LO_LLP_DST_EN))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LO_LLP_SRC_EN 28
|
||||
#define BIT_MASK_CTLX_LO_LLP_SRC_EN 0x1
|
||||
#define BIT_CTLX_LO_LLP_SRC_EN(x)(((x) & BIT_MASK_CTLX_LO_LLP_SRC_EN) << BIT_SHIFT_CTLX_LO_LLP_SRC_EN)
|
||||
#define BIT_INVC_CTLX_LO_LLP_SRC_EN (~(BIT_MASK_CTLX_LO_LLP_SRC_EN << BIT_SHIFT_CTLX_LO_LLP_SRC_EN))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CTLX_UP_BLOCK_BS 0
|
||||
#define BIT_MASK_CTLX_UP_BLOCK_BS 0xFFF
|
||||
#define BIT_CTLX_UP_BLOCK_BS(x)(((x) & BIT_MASK_CTLX_UP_BLOCK_BS) << BIT_SHIFT_CTLX_UP_BLOCK_BS)
|
||||
#define BIT_INVC_CTLX_UP_BLOCK_BS (~(BIT_MASK_CTLX_UP_BLOCK_BS << BIT_SHIFT_CTLX_UP_BLOCK_BS))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CTLX_UP_DONE 12
|
||||
#define BIT_MASK_CTLX_UP_DONE 0x1
|
||||
#define BIT_CTLX_UP_DONE(x)(((x) & BIT_MASK_CTLX_UP_DONE) << BIT_SHIFT_CTLX_UP_DONE)
|
||||
#define BIT_INVC_CTLX_UP_DONE (~(BIT_MASK_CTLX_UP_DONE << BIT_SHIFT_CTLX_UP_DONE))
|
||||
|
||||
|
||||
//3 CFG Register Bit Control
|
||||
#define BIT_SHIFT_CFGX_LO_CH_PRIOR 5
|
||||
#define BIT_MASK_CFGX_LO_CH_PRIOR 0x7
|
||||
#define BIT_CFGX_LO_CH_PRIOR(x)(((x) & BIT_MASK_CFGX_LO_CH_PRIOR) << BIT_SHIFT_CFGX_LO_CH_PRIOR)
|
||||
#define BIT_INVC_CFGX_LO_CH_PRIOR (~(BIT_MASK_CFGX_LO_CH_PRIOR << BIT_SHIFT_CFGX_LO_CH_PRIOR))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_CH_SUSP 8
|
||||
#define BIT_MASK_CFGX_LO_CH_SUSP 0x1
|
||||
#define BIT_CFGX_LO_CH_SUSP(x)(((x) & BIT_MASK_CFGX_LO_CH_SUSP) << BIT_SHIFT_CFGX_LO_CH_SUSP)
|
||||
#define BIT_INVC_CFGX_LO_CH_SUSP (~(BIT_MASK_CFGX_LO_CH_SUSP << BIT_SHIFT_CFGX_LO_CH_SUSP))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_FIFO_EMPTY 9
|
||||
#define BIT_MASK_CFGX_LO_FIFO_EMPTY 0x1
|
||||
#define BIT_CFGX_LO_FIFO_EMPTY(x)(((x) & BIT_MASK_CFGX_LO_FIFO_EMPTY) << BIT_SHIFT_CFGX_LO_FIFO_EMPTY)
|
||||
#define BIT_INVC_CFGX_LO_FIFO_EMPTY (~(BIT_MASK_CFGX_LO_FIFO_EMPTY << BIT_SHIFT_CFGX_LO_FIFO_EMPTY))
|
||||
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_HS_SEL_DST 10
|
||||
#define BIT_MASK_CFGX_LO_HS_SEL_DST 0x1
|
||||
#define BIT_CFGX_LO_HS_SEL_DST(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_DST) << BIT_SHIFT_CFGX_LO_HS_SEL_DST)
|
||||
#define BIT_INVC_CFGX_LO_HS_SEL_DST (~(BIT_MASK_CFGX_LO_HS_SEL_DST << BIT_SHIFT_CFGX_LO_HS_SEL_DST))
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_HS_SEL_SRC 11
|
||||
#define BIT_MASK_CFGX_LO_HS_SEL_SRC 0x1
|
||||
#define BIT_CFGX_LO_HS_SEL_SRC(x)(((x) & BIT_MASK_CFGX_LO_HS_SEL_SRC) << BIT_SHIFT_CFGX_LO_HS_SEL_SRC)
|
||||
#define BIT_INVC_CFGX_LO_HS_SEL_SRC (~(BIT_MASK_CFGX_LO_HS_SEL_SRC << BIT_SHIFT_CFGX_LO_HS_SEL_SRC))
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_LOCK_CH_L 12
|
||||
#define BIT_MASK_CFGX_LO_LOCK_CH_L 0x3
|
||||
#define BIT_CFGX_LO_LOCK_CH_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH_L) << BIT_SHIFT_CFGX_LO_LOCK_CH_L)
|
||||
#define BIT_INVC_CFGX_LO_LOCK_CH_L (~(BIT_MASK_CFGX_LO_LOCK_CH_L << BIT_SHIFT_CFGX_LO_LOCK_CH_L))
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_LOCK_B_L 14
|
||||
#define BIT_MASK_CFGX_LO_LOCK_B_L 0x3
|
||||
#define BIT_CFGX_LO_LOCK_B_L(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B_L) << BIT_SHIFT_CFGX_LO_LOCK_B_L)
|
||||
#define BIT_INVC_CFGX_LO_LOCK_B_L (~(BIT_MASK_CFGX_LO_LOCK_B_L << BIT_SHIFT_CFGX_LO_LOCK_B_L))
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_LOCK_CH 16
|
||||
#define BIT_MASK_CFGX_LO_LOCK_CH 0x1
|
||||
#define BIT_CFGX_LO_LOCK_CH(x)(((x) & BIT_MASK_CFGX_LO_LOCK_CH) << BIT_SHIFT_CFGX_LO_LOCK_CH)
|
||||
#define BIT_INVC_CFGX_LO_LOCK_CH (~(BIT_MASK_CFGX_LO_LOCK_CH << BIT_SHIFT_CFGX_LO_LOCK_CH))
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_LOCK_B 17
|
||||
#define BIT_MASK_CFGX_LO_LOCK_B 0x1
|
||||
#define BIT_CFGX_LO_LOCK_B(x)(((x) & BIT_MASK_CFGX_LO_LOCK_B) << BIT_SHIFT_CFGX_LO_LOCK_B)
|
||||
#define BIT_INVC_CFGX_LO_LOCK_B (~(BIT_MASK_CFGX_LO_LOCK_B << BIT_SHIFT_CFGX_LO_LOCK_B))
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_DST_HS_POL 18
|
||||
#define BIT_MASK_CFGX_LO_DST_HS_POL 0x1
|
||||
#define BIT_CFGX_LO_DST_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_DST_HS_POL) << BIT_SHIFT_CFGX_LO_DST_HS_POL)
|
||||
#define BIT_INVC_CFGX_LO_DST_HS_POL (~(BIT_MASK_CFGX_LO_DST_HS_POL << BIT_SHIFT_CFGX_LO_DST_HS_POL))
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_SRC_HS_POL 19
|
||||
#define BIT_MASK_CFGX_LO_SRC_HS_POL 0x1
|
||||
#define BIT_CFGX_LO_SRC_HS_POL(x)(((x) & BIT_MASK_CFGX_LO_SRC_HS_POL) << BIT_SHIFT_CFGX_LO_SRC_HS_POL)
|
||||
#define BIT_INVC_CFGX_LO_SRC_HS_POL (~(BIT_MASK_CFGX_LO_SRC_HS_POL << BIT_SHIFT_CFGX_LO_SRC_HS_POL))
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_MAX_ABRST 20
|
||||
#define BIT_MASK_CFGX_LO_MAX_ABRST 0x3FF
|
||||
#define BIT_CFGX_LO_MAX_ABRST(x)(((x) & BIT_MASK_CFGX_LO_MAX_ABRST) << BIT_SHIFT_CFGX_LO_MAX_ABRST)
|
||||
#define BIT_INVC_CFGX_LO_MAX_ABRST (~(BIT_MASK_CFGX_LO_MAX_ABRST << BIT_SHIFT_CFGX_LO_MAX_ABRST))
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_RELOAD_SRC 30
|
||||
#define BIT_MASK_CFGX_LO_RELOAD_SRC 0x1
|
||||
#define BIT_CFGX_LO_RELOAD_SRC(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_SRC) << BIT_SHIFT_CFGX_LO_RELOAD_SRC)
|
||||
#define BIT_INVC_CFGX_LO_RELOAD_SRC (~(BIT_MASK_CFGX_LO_RELOAD_SRC << BIT_SHIFT_CFGX_LO_RELOAD_SRC))
|
||||
|
||||
#define BIT_SHIFT_CFGX_LO_RELOAD_DST 31
|
||||
#define BIT_MASK_CFGX_LO_RELOAD_DST 0x1
|
||||
#define BIT_CFGX_LO_RELOAD_DST(x)(((x) & BIT_MASK_CFGX_LO_RELOAD_DST) << BIT_SHIFT_CFGX_LO_RELOAD_DST)
|
||||
#define BIT_INVC_CFGX_LO_RELOAD_DST (~(BIT_MASK_CFGX_LO_RELOAD_DST << BIT_SHIFT_CFGX_LO_RELOAD_DST))
|
||||
|
||||
#define BIT_SHIFT_CFGX_UP_FCMODE 0
|
||||
#define BIT_MASK_CFGX_UP_FCMODE 0x1
|
||||
#define BIT_CFGX_UP_FCMODE(x)(((x) & BIT_MASK_CFGX_UP_FCMODE) << BIT_SHIFT_CFGX_UP_FCMODE)
|
||||
#define BIT_INVC_CFGX_UP_FCMODE (~(BIT_MASK_CFGX_UP_FCMODE << BIT_SHIFT_CFGX_UP_FCMODE))
|
||||
|
||||
#define BIT_SHIFT_CFGX_UP_FIFO_MODE 1
|
||||
#define BIT_MASK_CFGX_UP_FIFO_MODE 0x1
|
||||
#define BIT_CFGX_UP_FIFO_MODE(x)(((x) & BIT_MASK_CFGX_UP_FIFO_MODE) << BIT_SHIFT_CFGX_UP_FIFO_MODE)
|
||||
#define BIT_INVC_CFGX_UP_FIFO_MODE (~(BIT_MASK_CFGX_UP_FIFO_MODE << BIT_SHIFT_CFGX_UP_FIFO_MODE))
|
||||
|
||||
#define BIT_SHIFT_CFGX_UP_PROTCTL 2
|
||||
#define BIT_MASK_CFGX_UP_PROTCTL 0x7
|
||||
#define BIT_CFGX_UP_PROTCTL(x)(((x) & BIT_MASK_CFGX_UP_PROTCTL) << BIT_SHIFT_CFGX_UP_PROTCTL)
|
||||
#define BIT_INVC_CFGX_UP_PROTCTL (~(BIT_MASK_CFGX_UP_PROTCTL << BIT_SHIFT_CFGX_UP_PROTCTL))
|
||||
|
||||
#define BIT_SHIFT_CFGX_UP_DS_UPD_EN 5
|
||||
#define BIT_MASK_CFGX_UP_DS_UPD_EN 0x1
|
||||
#define BIT_CFGX_UP_DS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_DS_UPD_EN) << BIT_SHIFT_CFGX_UP_DS_UPD_EN)
|
||||
#define BIT_INVC_CFGX_UP_DS_UPD_EN (~(BIT_MASK_CFGX_UP_DS_UPD_EN << BIT_SHIFT_CFGX_UP_DS_UPD_EN))
|
||||
|
||||
#define BIT_SHIFT_CFGX_UP_SS_UPD_EN 6
|
||||
#define BIT_MASK_CFGX_UP_SS_UPD_EN 0x1
|
||||
#define BIT_CFGX_UP_SS_UPD_EN(x)(((x) & BIT_MASK_CFGX_UP_SS_UPD_EN) << BIT_SHIFT_CFGX_UP_SS_UPD_EN)
|
||||
#define BIT_INVC_CFGX_UP_SS_UPD_EN (~(BIT_MASK_CFGX_UP_SS_UPD_EN << BIT_SHIFT_CFGX_UP_SS_UPD_EN))
|
||||
|
||||
#define BIT_SHIFT_CFGX_UP_SRC_PER 7
|
||||
#define BIT_MASK_CFGX_UP_SRC_PER 0xF
|
||||
#define BIT_CFGX_UP_SRC_PER(x)(((x) & BIT_MASK_CFGX_UP_SRC_PER) << BIT_SHIFT_CFGX_UP_SRC_PER)
|
||||
#define BIT_INVC_CFGX_UP_SRC_PER (~(BIT_MASK_CFGX_UP_SRC_PER << BIT_SHIFT_CFGX_UP_SRC_PER))
|
||||
|
||||
#define BIT_SHIFT_CFGX_UP_DEST_PER 11
|
||||
#define BIT_MASK_CFGX_UP_DEST_PER 0xF
|
||||
#define BIT_CFGX_UP_DEST_PER(x)(((x) & BIT_MASK_CFGX_UP_DEST_PER) << BIT_SHIFT_CFGX_UP_DEST_PER)
|
||||
#define BIT_INVC_CFGX_UP_DEST_PER (~(BIT_MASK_CFGX_UP_DEST_PER << BIT_SHIFT_CFGX_UP_DEST_PER))
|
||||
|
||||
typedef enum _GDMA_CHANNEL_NUM_ {
|
||||
GdmaNoCh = 0x0000,
|
||||
GdmaCh0 = 0x0101,
|
||||
GdmaCh1 = 0x0202,
|
||||
GdmaCh2 = 0x0404,
|
||||
GdmaCh3 = 0x0808,
|
||||
GdmaCh4 = 0x1010,
|
||||
GdmaCh5 = 0x2020,
|
||||
GdmaCh6 = 0x4040,
|
||||
GdmaCh7 = 0x8080,
|
||||
GdmaAllCh = 0xffff
|
||||
}GDMA_CHANNEL_NUM, *PGDMA_CHANNEL_NUM;
|
||||
|
||||
|
||||
//3 CTL register struct
|
||||
|
||||
typedef enum _GDMA_CTL_TT_FC_TYPE_ {
|
||||
TTFCMemToMem = 0x00,
|
||||
TTFCMemToPeri = 0x01,
|
||||
TTFCPeriToMem = 0x02
|
||||
}GDMA_CTL_TT_FC_TYPE, *PGDMA_CTL_TT_FC_TYPE;
|
||||
|
||||
//Max type = Bus Width
|
||||
typedef enum _GDMA_CTL_TR_WIDTH_ {
|
||||
TrWidthOneByte = 0x00,
|
||||
TrWidthTwoBytes = 0x01,
|
||||
TrWidthFourBytes = 0x02
|
||||
}GDMA_CTL_TR_WIDTH, *PGDMA_CTL_TR_WIDTH;
|
||||
|
||||
typedef enum _GDMA_CTL_MSIZE_ {
|
||||
MsizeOne = 0x00,
|
||||
MsizeFour = 0x01,
|
||||
MsizeEight = 0x02
|
||||
}GDMA_CTL_MSIZE, *PGDMA_CTL_MSIZE;
|
||||
|
||||
typedef enum _GDMA_INC_TYPE_ {
|
||||
IncType = 0x00,
|
||||
DecType = 0x01,
|
||||
NoChange = 0x02
|
||||
}GDMA_INC_TYPE, *PGDMA_INC_TYPE;
|
||||
|
||||
|
||||
typedef struct _GDMA_CTL_REG_ {
|
||||
GDMA_CTL_TT_FC_TYPE TtFc;
|
||||
GDMA_CTL_TR_WIDTH DstTrWidth;
|
||||
GDMA_CTL_TR_WIDTH SrcTrWidth;
|
||||
GDMA_INC_TYPE Dinc;
|
||||
GDMA_INC_TYPE Sinc;
|
||||
GDMA_CTL_MSIZE DestMsize;
|
||||
GDMA_CTL_MSIZE SrcMsize;
|
||||
|
||||
u8 IntEn :1; // Bit 0
|
||||
u8 SrcGatherEn :1; // Bit 1
|
||||
u8 DstScatterEn :1; // Bit 2
|
||||
u8 LlpDstEn :1; // Bit 3
|
||||
u8 LlpSrcEn :1; // Bit 4
|
||||
u8 Done :1; // Bit 5
|
||||
u8 Rsvd6To7 :2; //Bit 6 -7
|
||||
u16 BlockSize;
|
||||
|
||||
}GDMA_CTL_REG, *PGDMA_CTL_REG;
|
||||
|
||||
|
||||
//3 CFG Register Structure
|
||||
|
||||
typedef enum _GDMA_CH_PRIORITY_ {
|
||||
Prior0 = 0,
|
||||
Prior1 = 1,
|
||||
Prior2 = 2,
|
||||
Prior3 = 3,
|
||||
Prior4 = 4,
|
||||
Prior5 = 5,
|
||||
Prior6 = 6,
|
||||
Prior7 = 7
|
||||
}GDMA_CH_PRIORITY, *PGDMA_CH_PRIORITY;
|
||||
|
||||
typedef enum _GDMA_LOCK_LEVEL_ {
|
||||
OverComplDmaTransfer = 0x00,
|
||||
OverComplDmaBlockTransfer = 0x01,
|
||||
OverComplDmaTransation = 0x02
|
||||
}GDMA_LOCK_LEVEL, *PGDMA_LOCK_LEVEL;
|
||||
|
||||
|
||||
typedef struct _GDMA_CFG_REG_ {
|
||||
GDMA_CH_PRIORITY ChPrior;
|
||||
GDMA_LOCK_LEVEL LockBL;
|
||||
GDMA_LOCK_LEVEL LockChL;
|
||||
u16 MaxAbrst;
|
||||
u8 SrcPer;
|
||||
u8 DestPer;
|
||||
u16 ChSusp :1; //Bit 0
|
||||
u16 FifoEmpty :1; //Bit 1
|
||||
u16 HsSelDst :1; //Bit 2
|
||||
u16 HsSelSrc :1; //Bit 3
|
||||
u16 LockCh :1; //Bit 4
|
||||
u16 LockB :1; //Bit 5
|
||||
u16 DstHsPol :1; //Bit 6
|
||||
u16 SrcHsPol :1; //Bit 7
|
||||
u16 ReloadSrc :1; //Bit 8
|
||||
u16 ReloadDst :1; //Bit 9
|
||||
u16 FifoMode :1; //Bit 10
|
||||
u16 DsUpdEn :1; //Bit 11
|
||||
u16 SsUpdEn :1; //Bit 12
|
||||
u16 Rsvd13To15 :3;
|
||||
}GDMA_CFG_REG, *PGDMA_CFG_REG;
|
||||
|
||||
typedef enum _GDMA_ISR_TYPE_ {
|
||||
TransferType = 0x1,
|
||||
BlockType = 0x2,
|
||||
SrcTransferType = 0x4,
|
||||
DstTransferType = 0x8,
|
||||
ErrType = 0x10
|
||||
}GDMA_ISR_TYPE, *PGDMA_ISR_TYPE;
|
||||
|
||||
|
||||
VOID
|
||||
HalGdmaOnOffRtl8195a (
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalGdamChInitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalGdmaChSetingRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalGdmaChBlockSetingRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalGdmaChBlockSetingRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalGdmaChDisRtl8195a (
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalGdmaChEnRtl8195a (
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalGdmaChIsrEnAndDisRtl8195a (
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u8
|
||||
HalGdmaChIsrCleanRtl8195a (
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalGdmaChCleanAutoSrcRtl8195a (
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalGdmaChCleanAutoDstRtl8195a (
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u32
|
||||
HalGdmaQueryDArRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u32
|
||||
HalGdmaQuerySArRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalGdmaQueryChEnRtl8195a (
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#ifdef CONFIG_CHIP_E_CUT
|
||||
_LONG_CALL_ BOOL
|
||||
HalGdmaChBlockSetingRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ u32
|
||||
HalGdmaQueryDArRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ u32
|
||||
HalGdmaQuerySArRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ BOOL
|
||||
HalGdmaQueryChEnRtl8195a_V04 (
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#endif // #ifdef CONFIG_CHIP_E_CUT
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,398 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RTL8195A_GPIO_H_
|
||||
#define _RTL8195A_GPIO_H_
|
||||
|
||||
#include "hal_api.h"
|
||||
#include "hal_gpio.h"
|
||||
|
||||
#define GPIO_PORTA_DR 0x00 // data register
|
||||
#define GPIO_PORTA_DDR 0x04 // data direction
|
||||
#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define GPIO_PORTB_DR 0x0c // data register
|
||||
#define GPIO_PORTB_DDR 0x10 // data direction
|
||||
#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define GPIO_PORTC_DR 0x18 // data register
|
||||
#define GPIO_PORTC_DDR 0x1c // data direction
|
||||
#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
|
||||
|
||||
//1 Only the PORTA can be configured to generate interrupts
|
||||
#define GPIO_INT_EN 0x30 // Interrupt enable register
|
||||
#define GPIO_INT_MASK 0x34 // Interrupt mask
|
||||
#define GPIO_INT_TYPE 0x38 // Interrupt type(level/edge) register
|
||||
#define GPIO_INT_POLARITY 0x3C // Interrupt polarity(Active low/high) register
|
||||
#define GPIO_INT_STATUS 0x40 // Interrupt status
|
||||
#define GPIO_INT_RAWSTATUS 0x44 // Interrupt status without mask
|
||||
#define GPIO_DEBOUNCE 0x48 // Interrupt signal debounce
|
||||
#define GPIO_PORTA_EOI 0x4c // Clear interrupt
|
||||
|
||||
#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back
|
||||
#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back
|
||||
#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back
|
||||
|
||||
#define GPIO_INT_SYNC 0x60 // Is level-sensitive interrupt being sync sith PCLK
|
||||
|
||||
enum {
|
||||
HAL_GPIO_HIGHZ = 0,
|
||||
HAL_GPIO_PULL_LOW = 1,
|
||||
HAL_GPIO_PULL_HIGH = 2
|
||||
};
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_INT = 0x02, /*!< GPIO Interrupt Mode */
|
||||
GPIO_Mode_MAX = 0x03,
|
||||
}GPIOMode_TypeDef;
|
||||
|
||||
/**
|
||||
* @brief GPIO Configuration PullUp PullDown enumeration
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PuPd_NOPULL = 0x00, /*!< GPIO Interrnal HIGHZ */
|
||||
GPIO_PuPd_DOWN = 0x01, /*!< GPIO Interrnal Pull DOWN */
|
||||
GPIO_PuPd_UP = 0x02, /*!< GPIO Interrnal Pull UP */
|
||||
}GPIOPuPd_TypeDef;
|
||||
|
||||
/**
|
||||
* @brief Setting interrupt's trigger type
|
||||
*
|
||||
* Setting interrupt's trigger type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_INT_Trigger_LEVEL = 0x0, /**< This interrupt is level trigger */
|
||||
GPIO_INT_Trigger_EDGE = 0x1, /**< This interrupt is edge trigger */
|
||||
}GPIOIT_LevelType;
|
||||
|
||||
/**
|
||||
* @brief Setting interrupt active mode
|
||||
*
|
||||
* Setting interrupt active mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_INT_POLARITY_ACTIVE_LOW = 0x0, /**< Setting interrupt to low active: falling edge or low level */
|
||||
GPIO_INT_POLARITY_ACTIVE_HIGH = 0x1, /**< Setting interrupt to high active: rising edge or high level */
|
||||
}GPIOIT_PolarityType;
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable interrupt debounce mode
|
||||
*
|
||||
* Enable/Disable interrupt debounce mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_INT_DEBOUNCE_DISABLE = 0x0, /**< Disable interrupt debounce */
|
||||
GPIO_INT_DEBOUNCE_ENABLE = 0x1, /**< Enable interrupt debounce */
|
||||
}GPIOIT_DebounceType;
|
||||
|
||||
|
||||
typedef struct {
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. */
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. */
|
||||
GPIOIT_LevelType GPIO_ITTrigger; /**< Interrupt mode is level or edge trigger */
|
||||
GPIOIT_PolarityType GPIO_ITPolarity; /**< Interrupt mode is high or low active trigger */
|
||||
GPIOIT_DebounceType GPIO_ITDebounce; /**< Enable or disable de-bounce for interrupt */
|
||||
u32 GPIO_Pin; // Pin: [7:5]: port number, [4:0]: pin number
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
//======================================================
|
||||
// ROM Function prototype
|
||||
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
|
||||
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
|
||||
static __inline HAL_Status
|
||||
GPIO_Lock (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
HAL_Status Status;
|
||||
|
||||
if (_pHAL_Gpio_Adapter->EnterCritical) {
|
||||
_pHAL_Gpio_Adapter->EnterCritical();
|
||||
}
|
||||
|
||||
if(_pHAL_Gpio_Adapter->Locked) {
|
||||
Status = HAL_BUSY;
|
||||
}
|
||||
else {
|
||||
_pHAL_Gpio_Adapter->Locked = 1;
|
||||
Status = HAL_OK;
|
||||
}
|
||||
|
||||
if (_pHAL_Gpio_Adapter->ExitCritical) {
|
||||
_pHAL_Gpio_Adapter->ExitCritical();
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
|
||||
static __inline VOID
|
||||
GPIO_UnLock (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
if (_pHAL_Gpio_Adapter->EnterCritical) {
|
||||
_pHAL_Gpio_Adapter->EnterCritical();
|
||||
}
|
||||
|
||||
_pHAL_Gpio_Adapter->Locked = 0;
|
||||
|
||||
if (_pHAL_Gpio_Adapter->ExitCritical) {
|
||||
_pHAL_Gpio_Adapter->ExitCritical();
|
||||
}
|
||||
}
|
||||
#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES
|
||||
|
||||
_LONG_CALL_ extern u32
|
||||
HAL_GPIO_IrqHandler_8195a(
|
||||
IN VOID *pData
|
||||
);
|
||||
|
||||
_LONG_CALL_ extern u32
|
||||
HAL_GPIO_MbedIrqHandler_8195a(
|
||||
IN VOID *pData
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_IntCtrl_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin,
|
||||
u32 En
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_Init_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_DeInit_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_GPIO_PIN_STATE
|
||||
HAL_GPIO_ReadPin_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_WritePin_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin,
|
||||
HAL_GPIO_PIN_STATE Pin_State
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_RegIrq_8195a(
|
||||
IN PIRQ_HANDLE pIrqHandle
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_UnRegIrq_8195a(
|
||||
IN PIRQ_HANDLE pIrqHandle
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_UserRegIrq_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin,
|
||||
VOID *IrqHandler,
|
||||
VOID *IrqData
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_UserUnRegIrq_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_MaskIrq_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_UnMaskIrq_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_IntDebounce_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin,
|
||||
u8 Enable
|
||||
);
|
||||
|
||||
_LONG_CALL_ u32
|
||||
HAL_GPIO_GetIPPinName_8195a(
|
||||
u32 chip_pin
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HAL_GPIO_PullCtrl_8195a(
|
||||
u32 chip_pin,
|
||||
u8 pull_type
|
||||
);
|
||||
|
||||
_LONG_CALL_ u32
|
||||
GPIO_GetChipPinName_8195a(
|
||||
u32 port,
|
||||
u32 pin
|
||||
);
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
GPIO_PullCtrl_8195a(
|
||||
u32 chip_pin,
|
||||
u8 pull_type
|
||||
);
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
GPIO_Int_SetType_8195a(
|
||||
u8 pin_num,
|
||||
u8 int_mode
|
||||
);
|
||||
|
||||
|
||||
_LONG_CALL_ HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN *GPIO_Pin, u32 En);
|
||||
_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr);
|
||||
|
||||
HAL_Status
|
||||
HAL_GPIO_ClearISR_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
);
|
||||
|
||||
|
||||
/********** HAL In-Line Functions **********/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
|
||||
*
|
||||
* @retval The input port pin current status(High or Low).
|
||||
*/
|
||||
static __inline s32
|
||||
HAL_GPIO_ReadPin(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
)
|
||||
{
|
||||
return (s32)HAL_GPIO_ReadPin_8195a(GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write the specified output port pin.
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
|
||||
*
|
||||
* @param Pin_State: The state going to be set to the assigned GPIO pin.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static __inline VOID
|
||||
HAL_GPIO_WritePin(
|
||||
HAL_GPIO_PIN *GPIO_Pin,
|
||||
u32 Value
|
||||
)
|
||||
{
|
||||
HAL_GPIO_WritePin_8195a(GPIO_Pin, (HAL_GPIO_PIN_STATE)Value);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief To register a user interrupt handler for a specified pin
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
|
||||
*
|
||||
* @param IrqHandler: The IRQ handler to be assigned to the specified pin
|
||||
*
|
||||
* @param IrqData: The pointer will be pass the the IRQ handler
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static __inline VOID
|
||||
HAL_GPIO_UserRegIrq(
|
||||
HAL_GPIO_PIN *GPIO_Pin,
|
||||
VOID *IrqHandler,
|
||||
VOID *IrqData
|
||||
)
|
||||
{
|
||||
HAL_GPIO_UserRegIrq_8195a(GPIO_Pin, IrqHandler, IrqData);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief To un-register a user interrupt handler for a specified pin
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static __inline VOID
|
||||
HAL_GPIO_UserUnRegIrq(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
)
|
||||
{
|
||||
HAL_GPIO_UserUnRegIrq_8195a(GPIO_Pin);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable GPIO interrupt
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin initialization.
|
||||
*
|
||||
* @param En: Enable (1) or Disable (0)
|
||||
*
|
||||
* @retval HAL_Status
|
||||
*/
|
||||
static __inline VOID
|
||||
HAL_GPIO_IntCtrl(
|
||||
HAL_GPIO_PIN *GPIO_Pin,
|
||||
u32 En
|
||||
)
|
||||
{
|
||||
HAL_GPIO_IntCtrl_8195a(GPIO_Pin, En);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Mask the interrupt of a specified pin
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static __inline VOID
|
||||
HAL_GPIO_MaskIrq(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
)
|
||||
{
|
||||
HAL_GPIO_MaskIrq_8195a(GPIO_Pin);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief UnMask the interrupt of a specified pin
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
static __inline VOID
|
||||
HAL_GPIO_UnMaskIrq(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
)
|
||||
{
|
||||
HAL_GPIO_ClearISR_8195a(GPIO_Pin);
|
||||
HAL_GPIO_UnMaskIrq_8195a(GPIO_Pin);
|
||||
}
|
||||
|
||||
|
||||
#endif // end of "#define _RTL8195A_GPIO_H_"
|
||||
|
||||
|
|
@ -0,0 +1,404 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __RTL8195A_GSPI_H__
|
||||
#define __RTL8195A_GSPI_H__
|
||||
|
||||
#define SPI_LOCAL_DOMAIN 0x0
|
||||
#define SPI_TXFIFO_DOMAIN 0xc
|
||||
#define SPI_RXFIFO_DOMAIN 0x1f
|
||||
|
||||
//IO Bus domain address mapping
|
||||
#define DEFUALT_OFFSET 0x0
|
||||
#define SPI_LOCAL_OFFSET 0x10250000
|
||||
#define SPI_TX_FIFO_OFFSET 0x10310000
|
||||
#define SPI_RX_FIFO_OFFSET 0x10340000
|
||||
|
||||
#define SPI_LOCAL_DEVICE_ID 0
|
||||
#define SPI_TXQ_FIFO_DEVICE_ID 3
|
||||
#define SPI_RXQ_FIFO_DEVICE_ID 7
|
||||
#define SPI_UNDEFINED_DEVICE_ID (-1)
|
||||
|
||||
|
||||
//SPI Local registers
|
||||
#define SPI_REG_INT_CTRL 0x0004 // 4 bytes, SPI INT Control
|
||||
#define SPI_REG_INT_TIMEOUT 0x0006 // 2 bytes, SPI 32us INT timout
|
||||
#define SPI_REG_HIMR 0x0014 // 4 bytes, SPI Host Interrupt Mask
|
||||
#define SPI_REG_HISR 0x0018 // 4 bytes, SPI Host Interrupt Service Routine
|
||||
#define SPI_REG_RX0_REQ_LEN 0x001C // 4 bytes, RXDMA Request Length
|
||||
#define SPI_REG_FREE_TX_SPACE 0x0020 // 4 bytes, Free Tx Buffer Page
|
||||
#define SPI_REG_TX_SEQNUM 0x0024 // 1 byte, TX Sequence Number Definition
|
||||
#define SPI_REG_HCPWM 0x0038 // 1 byte, HCI Current Power Mode
|
||||
#define SPI_REG_HCPWM2 0x003A // 2 bytes, HCI Current Power Mode 2
|
||||
#define SPI_REG_AVAI_PATH_L 0x0040 // 4 bytes, SPI TX Available Low Size reg
|
||||
#define SPI_REG_AVAI_PATH_H 0x0044 // 4 bytes, SPI TX Available High Size reg
|
||||
#define SPI_REG_RX_AGG_CTL 0x0048 // 4 bytes, SPI RX AGG control
|
||||
#define SPI_REG_H2C_MSG 0x004C // 4 bytes, SPI_REG_H2C_MSG
|
||||
#define SPI_REG_C2H_MSG 0x0050 // 4 bytes, SPI_REG_C2H_MSG
|
||||
#define SPI_REG_HRPWM 0x0080 // 1 byte, SPI_REG_HRPWM
|
||||
#define SPI_REG_HPS_CLKR 0x0084 // 1 byte, not uesd
|
||||
#define SPI_REG_CPU_IND 0x0087 // 1 byte, firmware indication to host
|
||||
#define SPI_REG_32K_TRANS_CTL 0x0088 // 1 byte, 32K transparent control, BIT0 EN32K_TRANS
|
||||
#define SPI_REG_32K_IDLE_TIME 0x008B // 1 byte, 32K idle time,
|
||||
#define SPI_REG_DELY_LINE_SEL 0x008C // 1 byte, Delay line selection,
|
||||
#define SPI_REG_SPI_CFG 0x00F0 // 1 byte, SPI configuration,
|
||||
|
||||
#define LOCAL_REG_FREE_TX_SPACE (SPI_LOCAL_OFFSET | SPI_REG_FREE_TX_SPACE)
|
||||
|
||||
// Register SPI_REG_CPU_IND
|
||||
#define SPI_CPU_RDY_IND (BIT0)
|
||||
|
||||
|
||||
/************************************************/
|
||||
// SPI_REG_HISR: SDIO Host Interrupt Service Routine
|
||||
#define SPI_HISR_RX_REQUEST (BIT0)
|
||||
#define SPI_HISR_AVAL_INT (BIT1)
|
||||
#define SPI_HISR_TXPKT_OVER_BUFF (BIT2)
|
||||
#define SPI_HISR_TX_AGG_SIZE_MISMATCH (BIT3)
|
||||
#define SPI_HISR_TXBD_OVF (BIT4)
|
||||
//BIT5~16 not used
|
||||
#define SPI_HISR_C2H_MSG_INT (BIT17)
|
||||
#define SPI_HISR_CPWM1_INT (BIT18)
|
||||
#define SPI_HISR_CPWM2_INT (BIT19)
|
||||
//BIT20~31 not used
|
||||
#define SPI_HISR_CPU_NOT_RDY (BIT22)
|
||||
|
||||
|
||||
#define MASK_SPI_HISR_CLEAR (SPI_HISR_RX_REQUEST |\
|
||||
SPI_HISR_AVAL_INT |\
|
||||
SPI_HISR_TXPKT_OVER_BUFF |\
|
||||
SPI_HISR_TX_AGG_SIZE_MISMATCH |\
|
||||
SPI_HISR_TXBD_OVF |\
|
||||
SPI_HISR_C2H_MSG_INT |\
|
||||
SPI_HISR_CPWM1_INT |\
|
||||
SPI_HISR_CPWM2_INT)
|
||||
|
||||
// RTL8195A SPI Host Interrupt Mask Register
|
||||
#define SPI_HIMR_RX_REQUEST_MSK (BIT0)
|
||||
#define SPI_HIMR_AVAL_MSK (BIT1)
|
||||
#define SPI_HIMR_TXPKT_SIZE_OVER_BUFF_MSK (BIT2)
|
||||
#define SPI_HIMR_AGG_SIZE_MISMATCH_MSK (BIT3)
|
||||
#define SPI_HIMR_TXBD_OVF_MSK (BIT4)
|
||||
//BIT5~16 not used
|
||||
#define SPI_HIMR_C2H_MSG_INT_MSK (BIT17)
|
||||
#define SPI_HIMR_CPWM1_INT_MSK (BIT18)
|
||||
#define SPI_HIMR_CPWM2_INT_MSK (BIT19)
|
||||
//BIT20~31 not used
|
||||
#define SPI_HIMR_DISABLED 0
|
||||
|
||||
// Register SPI_REG_HCPWM
|
||||
#define SPI_HCPWM_WLAN_TRX (BIT1)
|
||||
|
||||
|
||||
enum{
|
||||
SPI_LITTLE_ENDIAN = 2,
|
||||
SPI_BIG_ENDIAN = 0
|
||||
};
|
||||
enum{
|
||||
SPI_WORD_LEN_16 = 0,
|
||||
SPI_WORD_LEN_32 = 1
|
||||
};
|
||||
|
||||
typedef enum{
|
||||
SPI_LITTLE_ENDIAN_16 = SPI_LITTLE_ENDIAN|SPI_WORD_LEN_16,
|
||||
SPI_LITTLE_ENDIAN_32 = SPI_LITTLE_ENDIAN|SPI_WORD_LEN_32, // default configure
|
||||
SPI_BIG_ENDIAN_16 = SPI_BIG_ENDIAN|SPI_WORD_LEN_16,
|
||||
SPI_BIG_ENDIAN_32 = SPI_BIG_ENDIAN|SPI_WORD_LEN_32
|
||||
}_gspi_conf_t;
|
||||
|
||||
#define GSPI_CMD_LEN 4
|
||||
#define GSPI_STATUS_LEN 8
|
||||
|
||||
|
||||
#define FILL_SPI_CMD(byte_en, addr, domain_id, fun, write_flag) ((byte_en & 0xff) | ((addr & 0xffff) << 8) \
|
||||
| ((domain_id & 0x1f) << 24) | ((fun & 0x3) << 29) | ((write_flag & 0x1) << 31))
|
||||
|
||||
|
||||
#define GET_STATUS_HISR(status) ((((*(u32*)status)) & 0x3) |((((*(u32*)status) >> 2) & 0x7) << 17))
|
||||
#define GET_STATUS_FREE_TX(status) ((((*(u32*)status) >> 5) & 0x7ffffff) << 2)
|
||||
#define GET_STATUS_RXQ_REQ_LEN(status) (((*(u32*)((u8 *)status + 4))) & 0xffffff)
|
||||
#define GET_STATUS_TX_SEQ(status) (((*(u32*)((u8 *)status + 4)) >> 24) & 0xff)
|
||||
|
||||
#define GSPI_CMD_TX 0x83 //
|
||||
#define GSPI_CMD_RX 0X82
|
||||
|
||||
// define transmit packat type
|
||||
#define GPSI_TX_PACKET_802_3 (0x83)
|
||||
#define GSPI_TX_PACKET_802_11 (0x81)
|
||||
#define GSPI_TX_H2C_CMD (0x11)
|
||||
#define GSPI_TX_MEM_READ (0x51)
|
||||
#define GSPI_TX_MEM_WRITE (0x53)
|
||||
#define GSPI_TX_MEM_SET (0x55)
|
||||
#define GSPI_TX_FM_FREETOGO (0x61)
|
||||
|
||||
//define receive packet type
|
||||
#define GSPI_RX_PACKET_802_3 (0x82)
|
||||
#define GSPI_RX_PACKET_802_11 (0x80)
|
||||
#define GSPI_RX_C2H_CMD (0x10)
|
||||
#define GSPI_RX_MEM_READ (0x50)
|
||||
#define GSPI_RX_MEM_WRITE (0x52)
|
||||
#define GSPI_RX_MEM_SET (0x54)
|
||||
#define GSPI_RX_FM_FREETOGO (0x60)
|
||||
|
||||
|
||||
typedef struct _GSPI_TX_DESC{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
#else
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
u32 rsvd0:24;
|
||||
#else
|
||||
u32 rsvd0:24;
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 rsvd1;
|
||||
|
||||
// u4Byte 3
|
||||
u32 rsvd2;
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} GSPI_TX_DESC, *PGSPI_TX_DESC;
|
||||
|
||||
typedef struct _GSPI_RX_DESC{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 rsvd0:6; // bit[29:24]
|
||||
u32 icv:1; // bit[30], ICV error
|
||||
u32 crc:1; // bit[31], CRC error
|
||||
#else
|
||||
u32 crc:1; // bit[31], CRC error
|
||||
u32 icv:1; // bit[30], ICV error
|
||||
u32 rsvd0:6; // bit[29:24]
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
#else
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 rsvd2;
|
||||
|
||||
// u4Byte 3
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd4;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd5;
|
||||
} GSPI_RX_DESC, *PGSPI_RX_DESC;
|
||||
|
||||
#define SIZE_TX_DESC (sizeof(GSPI_TX_DESC))
|
||||
#define SIZE_RX_DESC (sizeof(GSPI_RX_DESC))
|
||||
|
||||
// For memory read command
|
||||
typedef struct _GSPI_DESC_MR{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 rsvd0:8; // bit[31:24]
|
||||
#else
|
||||
u32 rsvd0:8; // bit[31:24]
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
#else
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_addr;
|
||||
|
||||
// u4Byte 3
|
||||
u32 rsvd2;
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} GSPI_DESC_MR, *PGSPI_DESC_MR;
|
||||
|
||||
// For memory write reply command
|
||||
typedef struct _GSPI_DESC_MW{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
#else
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
u32 reply:1; // bit[8], request to send a reply message
|
||||
u32 rsvd0:23;
|
||||
#else
|
||||
u32 rsvd0:23;
|
||||
u32 reply:1; // bit[8], request to send a reply message
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_addr; // memory write start address
|
||||
|
||||
// u4Byte 3
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 write_len:16; // bit[15:0], the length to write
|
||||
u32 rsvd2:16; // bit[31:16]
|
||||
#else
|
||||
u32 rsvd2:16; // bit[31:16]
|
||||
u32 write_len:16; // bit[15:0], the length to write
|
||||
#endif
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} GSPI_DESC_MW, *PGSPI_DESC_MW;
|
||||
|
||||
// For memory set command
|
||||
typedef struct _GSPI_DESC_MS{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
#else
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
u32 data:8; // bit[8:15], the value to be written to the memory
|
||||
u32 reply:1; // bit[16], request to send a reply message
|
||||
u32 rsvd0:15;
|
||||
#else
|
||||
u32 rsvd0:15;
|
||||
u32 reply:1; // bit[16], request to send a reply message
|
||||
u32 data:8; // bit[8:15], the value to be written to the memory
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_addr; // memory write start address
|
||||
|
||||
// u4Byte 3
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 write_len:16; // bit[15:0], the length to write
|
||||
u32 rsvd2:16; // bit[31:16]
|
||||
#else
|
||||
u32 rsvd2:16; // bit[31:16]
|
||||
u32 write_len:16; // bit[15:0], the length to write
|
||||
#endif
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} GSPI_DESC_MS, *PGSPI_DESC_MS;
|
||||
// TX Desc for Jump to Start command
|
||||
typedef struct _GSPI_DESC_JS{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
#else
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
u32 offset:8; // bit[23:16], store the sizeof(TX_DESC)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
u32 rsvd0:24;
|
||||
#else
|
||||
u32 rsvd0:24;
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_fun; // the pointer of the startup function
|
||||
|
||||
// u4Byte 3
|
||||
u32 rsvd2;
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} GSPI_DESC_JS, *PGSPI_DESC_JS;
|
||||
|
||||
|
||||
// CCPWM2 bit map definition for Firmware download
|
||||
#define GSPI_INIT_DONE (BIT0)
|
||||
#define GSPI_MEM_WR_DONE (BIT1)
|
||||
#define GSPI_MEM_RD_DONE (BIT2)
|
||||
#define GSPI_MEM_ST_DONE (BIT3)
|
||||
#define GSPI_CPWM2_TOGGLE (BIT15)
|
||||
|
||||
// Register REG_SPDIO_CPU_IND
|
||||
#define GPSI_SYSTEM_TRX_RDY_IND (BIT0)
|
||||
|
||||
#endif //__GSPI_REG_H__
|
||||
|
||||
|
|
@ -0,0 +1,860 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#ifndef _RTL8195A_I2C_H_
|
||||
#define _RTL8195A_I2C_H_
|
||||
|
||||
#include "hal_api.h"
|
||||
|
||||
//================ Register Bit Field ==================
|
||||
//2 REG_DW_I2C_IC_CON
|
||||
#define BIT_IC_CON_IC_SLAVE_DISABLE BIT(6)
|
||||
#define BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE 6
|
||||
#define BIT_MASK_IC_CON_IC_SLAVE_DISABLE 0x1
|
||||
#define BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(x) (((x) & BIT_MASK_IC_CON_IC_SLAVE_DISABLE) << BIT_SHIFT_IC_CON_IC_SLAVE_DISABLE)
|
||||
|
||||
#define BIT_IC_CON_IC_RESTART_EN BIT(5)
|
||||
#define BIT_SHIFT_IC_CON_IC_RESTART_EN 5
|
||||
#define BIT_MASK_IC_CON_IC_RESTART_EN 0x1
|
||||
#define BIT_CTRL_IC_CON_IC_RESTART_EN(x) (((x) & BIT_MASK_IC_CON_IC_RESTART_EN) << BIT_SHIFT_IC_CON_IC_RESTART_EN)
|
||||
|
||||
#define BIT_IC_CON_IC_10BITADDR_MASTER BIT(4)
|
||||
#define BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER 4
|
||||
#define BIT_MASK_IC_CON_IC_10BITADDR_MASTER 0x1
|
||||
#define BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_CON_IC_10BITADDR_MASTER)
|
||||
|
||||
#define BIT_IC_CON_IC_10BITADDR_SLAVE BIT(3)
|
||||
#define BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE 3
|
||||
#define BIT_MASK_IC_CON_IC_10BITADDR_SLAVE 0x1
|
||||
#define BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(x) (((x) & BIT_MASK_IC_CON_IC_10BITADDR_SLAVE) << BIT_SHIFT_IC_CON_IC_10BITADDR_SLAVE)
|
||||
|
||||
|
||||
#define BIT_SHIFT_IC_CON_SPEED 1
|
||||
#define BIT_MASK_IC_CON_SPEED 0x3
|
||||
#define BIT_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
|
||||
#define BIT_CTRL_IC_CON_SPEED(x) (((x) & BIT_MASK_IC_CON_SPEED) << BIT_SHIFT_IC_CON_SPEED)
|
||||
#define BIT_GET_IC_CON_SPEED(x) (((x) >> BIT_SHIFT_IC_CON_SPEED) & BIT_MASK_IC_CON_SPEED)
|
||||
|
||||
#define BIT_IC_CON_MASTER_MODE BIT(0)
|
||||
#define BIT_SHIFT_IC_CON_MASTER_MODE 0
|
||||
#define BIT_MASK_IC_CON_MASTER_MODE 0x1
|
||||
#define BIT_CTRL_IC_CON_MASTER_MODE(x) (((x) & BIT_MASK_IC_CON_MASTER_MODE) << BIT_SHIFT_IC_CON_MASTER_MODE)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_TAR
|
||||
#define BIT_IC_TAR_IC_10BITADDR_MASTER BIT(12)
|
||||
#define BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER 12
|
||||
#define BIT_MASK_IC_TAR_IC_10BITADDR_MASTER 0x1
|
||||
#define BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(x) (((x) & BIT_MASK_IC_TAR_IC_10BITADDR_MASTER) << BIT_SHIFT_IC_TAR_IC_10BITADDR_MASTER)
|
||||
|
||||
#define BIT_IC_TAR_SPECIAL BIT(11)
|
||||
#define BIT_SHIFT_IC_TAR_SPECIAL 11
|
||||
#define BIT_MASK_IC_TAR_SPECIAL 0x1
|
||||
#define BIT_CTRL_IC_TAR_SPECIAL(x) (((x) & BIT_MASK_IC_TAR_SPECIAL) << BIT_SHIFT_IC_TAR_SPECIAL)
|
||||
|
||||
#define BIT_IC_TAR_GC_OR_START BIT(10)
|
||||
#define BIT_SHIFT_IC_TAR_GC_OR_START 10
|
||||
#define BIT_MASK_IC_TAR_GC_OR_START 0x1
|
||||
#define BIT_CTRL_IC_TAR_GC_OR_START(x) (((x) & BIT_MASK_IC_TAR_GC_OR_START) << BIT_SHIFT_IC_TAR_GC_OR_START)
|
||||
|
||||
|
||||
#define BIT_SHIFT_IC_TAR 0
|
||||
#define BIT_MASK_IC_TAR 0x3ff
|
||||
#define BIT_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
|
||||
#define BIT_CTRL_IC_TAR(x) (((x) & BIT_MASK_IC_TAR) << BIT_SHIFT_IC_TAR)
|
||||
#define BIT_GET_IC_TAR(x) (((x) >> BIT_SHIFT_IC_TAR) & BIT_MASK_IC_TAR)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_SAR
|
||||
|
||||
#define BIT_SHIFT_IC_SAR 0
|
||||
#define BIT_MASK_IC_SAR 0x3ff
|
||||
#define BIT_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
|
||||
#define BIT_CTRL_IC_SAR(x) (((x) & BIT_MASK_IC_SAR) << BIT_SHIFT_IC_SAR)
|
||||
#define BIT_GET_IC_SAR(x) (((x) >> BIT_SHIFT_IC_SAR) & BIT_MASK_IC_SAR)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_HS_MADDR
|
||||
|
||||
#define BIT_SHIFT_IC_HS_MADDR 0
|
||||
#define BIT_MASK_IC_HS_MADDR 0x7
|
||||
#define BIT_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
|
||||
#define BIT_CTRL_IC_HS_MADDR(x) (((x) & BIT_MASK_IC_HS_MADDR) << BIT_SHIFT_IC_HS_MADDR)
|
||||
#define BIT_GET_IC_HS_MADDR(x) (((x) >> BIT_SHIFT_IC_HS_MADDR) & BIT_MASK_IC_HS_MADDR)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_DATA_CMD
|
||||
#define BIT_IC_DATA_CMD_RESTART BIT(10)
|
||||
#define BIT_SHIFT_IC_DATA_CMD_RESTART 10
|
||||
#define BIT_MASK_IC_DATA_CMD_RESTART 0x1
|
||||
#define BIT_CTRL_IC_DATA_CMD_RESTART(x) (((x) & BIT_MASK_IC_DATA_CMD_RESTART) << BIT_SHIFT_IC_DATA_CMD_RESTART)
|
||||
|
||||
#define BIT_IC_DATA_CMD_STOP BIT(9)
|
||||
#define BIT_SHIFT_IC_DATA_CMD_STOP 9
|
||||
#define BIT_MASK_IC_DATA_CMD_STOP 0x1
|
||||
#define BIT_CTRL_IC_DATA_CMD_STOP(x) (((x) & BIT_MASK_IC_DATA_CMD_STOP) << BIT_SHIFT_IC_DATA_CMD_STOP)
|
||||
|
||||
#define BIT_IC_DATA_CMD_CMD BIT(8)
|
||||
#define BIT_SHIFT_IC_DATA_CMD_CMD 8
|
||||
#define BIT_MASK_IC_DATA_CMD_CMD 0x1
|
||||
#define BIT_CTRL_IC_DATA_CMD_CMD(x) (((x) & BIT_MASK_IC_DATA_CMD_CMD) << BIT_SHIFT_IC_DATA_CMD_CMD)
|
||||
|
||||
|
||||
#define BIT_SHIFT_IC_DATA_CMD_DAT 0
|
||||
#define BIT_MASK_IC_DATA_CMD_DAT 0xff
|
||||
#define BIT_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
|
||||
#define BIT_CTRL_IC_DATA_CMD_DAT(x) (((x) & BIT_MASK_IC_DATA_CMD_DAT) << BIT_SHIFT_IC_DATA_CMD_DAT)
|
||||
#define BIT_GET_IC_DATA_CMD_DAT(x) (((x) >> BIT_SHIFT_IC_DATA_CMD_DAT) & BIT_MASK_IC_DATA_CMD_DAT)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_SS_SCL_HCNT
|
||||
|
||||
#define BIT_SHIFT_IC_SS_SCL_HCNT 0
|
||||
#define BIT_MASK_IC_SS_SCL_HCNT 0xffff
|
||||
#define BIT_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
|
||||
#define BIT_CTRL_IC_SS_SCL_HCNT(x) (((x) & BIT_MASK_IC_SS_SCL_HCNT) << BIT_SHIFT_IC_SS_SCL_HCNT)
|
||||
#define BIT_GET_IC_SS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_HCNT) & BIT_MASK_IC_SS_SCL_HCNT)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_SS_SCL_LCNT
|
||||
|
||||
#define BIT_SHIFT_IC_SS_SCL_LCNT 0
|
||||
#define BIT_MASK_IC_SS_SCL_LCNT 0xffff
|
||||
#define BIT_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
|
||||
#define BIT_CTRL_IC_SS_SCL_LCNT(x) (((x) & BIT_MASK_IC_SS_SCL_LCNT) << BIT_SHIFT_IC_SS_SCL_LCNT)
|
||||
#define BIT_GET_IC_SS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_SS_SCL_LCNT) & BIT_MASK_IC_SS_SCL_LCNT)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_FS_SCL_HCNT
|
||||
|
||||
#define BIT_SHIFT_IC_FS_SCL_HCNT 0
|
||||
#define BIT_MASK_IC_FS_SCL_HCNT 0xffff
|
||||
#define BIT_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
|
||||
#define BIT_CTRL_IC_FS_SCL_HCNT(x) (((x) & BIT_MASK_IC_FS_SCL_HCNT) << BIT_SHIFT_IC_FS_SCL_HCNT)
|
||||
#define BIT_GET_IC_FS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_HCNT) & BIT_MASK_IC_FS_SCL_HCNT)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_FS_SCL_LCNT
|
||||
|
||||
#define BIT_SHIFT_IC_FS_SCL_LCNT 0
|
||||
#define BIT_MASK_IC_FS_SCL_LCNT 0xffff
|
||||
#define BIT_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
|
||||
#define BIT_CTRL_IC_FS_SCL_LCNT(x) (((x) & BIT_MASK_IC_FS_SCL_LCNT) << BIT_SHIFT_IC_FS_SCL_LCNT)
|
||||
#define BIT_GET_IC_FS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_FS_SCL_LCNT) & BIT_MASK_IC_FS_SCL_LCNT)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_HS_SCL_HCNT
|
||||
|
||||
#define BIT_SHIFT_IC_HS_SCL_HCNT 0
|
||||
#define BIT_MASK_IC_HS_SCL_HCNT 0xffff
|
||||
#define BIT_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
|
||||
#define BIT_CTRL_IC_HS_SCL_HCNT(x) (((x) & BIT_MASK_IC_HS_SCL_HCNT) << BIT_SHIFT_IC_HS_SCL_HCNT)
|
||||
#define BIT_GET_IC_HS_SCL_HCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_HCNT) & BIT_MASK_IC_HS_SCL_HCNT)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_HS_SCL_LCNT
|
||||
|
||||
#define BIT_SHIFT_IC_HS_SCL_LCNT 0
|
||||
#define BIT_MASK_IC_HS_SCL_LCNT 0xffff
|
||||
#define BIT_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
|
||||
#define BIT_CTRL_IC_HS_SCL_LCNT(x) (((x) & BIT_MASK_IC_HS_SCL_LCNT) << BIT_SHIFT_IC_HS_SCL_LCNT)
|
||||
#define BIT_GET_IC_HS_SCL_LCNT(x) (((x) >> BIT_SHIFT_IC_HS_SCL_LCNT) & BIT_MASK_IC_HS_SCL_LCNT)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_INTR_STAT
|
||||
#define BIT_IC_INTR_STAT_R_GEN_CALL BIT(11)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL 11
|
||||
#define BIT_MASK_IC_INTR_STAT_R_GEN_CALL 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_GEN_CALL) << BIT_SHIFT_IC_INTR_STAT_R_GEN_CALL)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_START_DET BIT(10)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_START_DET 10
|
||||
#define BIT_MASK_IC_INTR_STAT_R_START_DET 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_START_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_START_DET) << BIT_SHIFT_IC_INTR_STAT_R_START_DET)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_STOP_DET BIT(9)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_STOP_DET 9
|
||||
#define BIT_MASK_IC_INTR_STAT_R_STOP_DET 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_STAT_R_STOP_DET) << BIT_SHIFT_IC_INTR_STAT_R_STOP_DET)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_ACTIVITY BIT(8)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY 8
|
||||
#define BIT_MASK_IC_INTR_STAT_R_ACTIVITY 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_ACTIVITY) << BIT_SHIFT_IC_INTR_STAT_R_ACTIVITY)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_RX_DONE BIT(7)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_RX_DONE 7
|
||||
#define BIT_MASK_IC_INTR_STAT_R_RX_DONE 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_DONE) << BIT_SHIFT_IC_INTR_STAT_R_RX_DONE)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_TX_ABRT BIT(6)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT 6
|
||||
#define BIT_MASK_IC_INTR_STAT_R_TX_ABRT 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_ABRT) << BIT_SHIFT_IC_INTR_STAT_R_TX_ABRT)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_RD_REQ BIT(5)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_RD_REQ 5
|
||||
#define BIT_MASK_IC_INTR_STAT_R_RD_REQ 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RD_REQ) << BIT_SHIFT_IC_INTR_STAT_R_RD_REQ)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_TX_EMPTY BIT(4)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY 4
|
||||
#define BIT_MASK_IC_INTR_STAT_R_TX_EMPTY 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_EMPTY) << BIT_SHIFT_IC_INTR_STAT_R_TX_EMPTY)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_TX_OVER BIT(3)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_TX_OVER 3
|
||||
#define BIT_MASK_IC_INTR_STAT_R_TX_OVER 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_TX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_TX_OVER)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_RX_FULL BIT(2)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_RX_FULL 2
|
||||
#define BIT_MASK_IC_INTR_STAT_R_RX_FULL 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_FULL) << BIT_SHIFT_IC_INTR_STAT_R_RX_FULL)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_RX_OVER BIT(1)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_RX_OVER 1
|
||||
#define BIT_MASK_IC_INTR_STAT_R_RX_OVER 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_OVER) << BIT_SHIFT_IC_INTR_STAT_R_RX_OVER)
|
||||
|
||||
#define BIT_IC_INTR_STAT_R_RX_UNDER BIT(0)
|
||||
#define BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER 0
|
||||
#define BIT_MASK_IC_INTR_STAT_R_RX_UNDER 0x1
|
||||
#define BIT_CTRL_IC_INTR_STAT_R_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_STAT_R_RX_UNDER) << BIT_SHIFT_IC_INTR_STAT_R_RX_UNDER)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_INTR_MASK
|
||||
#define BIT_IC_INTR_MASK_M_GEN_CALL BIT(11)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL 11
|
||||
#define BIT_MASK_IC_INTR_MASK_M_GEN_CALL 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_GEN_CALL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_GEN_CALL) << BIT_SHIFT_IC_INTR_MASK_M_GEN_CALL)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_START_DET BIT(10)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_START_DET 10
|
||||
#define BIT_MASK_IC_INTR_MASK_M_START_DET 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_START_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_START_DET) << BIT_SHIFT_IC_INTR_MASK_M_START_DET)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_STOP_DET BIT(9)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_STOP_DET 9
|
||||
#define BIT_MASK_IC_INTR_MASK_M_STOP_DET 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_STOP_DET(x) (((x) & BIT_MASK_IC_INTR_MASK_M_STOP_DET) << BIT_SHIFT_IC_INTR_MASK_M_STOP_DET)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_ACTIVITY BIT(8)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY 8
|
||||
#define BIT_MASK_IC_INTR_MASK_M_ACTIVITY 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_ACTIVITY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_ACTIVITY) << BIT_SHIFT_IC_INTR_MASK_M_ACTIVITY)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_RX_DONE BIT(7)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_RX_DONE 7
|
||||
#define BIT_MASK_IC_INTR_MASK_M_RX_DONE 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_RX_DONE(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_DONE) << BIT_SHIFT_IC_INTR_MASK_M_RX_DONE)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_TX_ABRT BIT(6)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT 6
|
||||
#define BIT_MASK_IC_INTR_MASK_M_TX_ABRT 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_TX_ABRT(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_ABRT) << BIT_SHIFT_IC_INTR_MASK_M_TX_ABRT)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_RD_REQ BIT(5)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_RD_REQ 5
|
||||
#define BIT_MASK_IC_INTR_MASK_M_RD_REQ 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_RD_REQ(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RD_REQ) << BIT_SHIFT_IC_INTR_MASK_M_RD_REQ)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_TX_EMPTY BIT(4)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY 4
|
||||
#define BIT_MASK_IC_INTR_MASK_M_TX_EMPTY 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_TX_EMPTY(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_EMPTY) << BIT_SHIFT_IC_INTR_MASK_M_TX_EMPTY)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_TX_OVER BIT(3)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_TX_OVER 3
|
||||
#define BIT_MASK_IC_INTR_MASK_M_TX_OVER 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_TX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_TX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_TX_OVER)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_RX_FULL BIT(2)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_RX_FULL 2
|
||||
#define BIT_MASK_IC_INTR_MASK_M_RX_FULL 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_RX_FULL(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_FULL) << BIT_SHIFT_IC_INTR_MASK_M_RX_FULL)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_RX_OVER BIT(1)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_RX_OVER 1
|
||||
#define BIT_MASK_IC_INTR_MASK_M_RX_OVER 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_RX_OVER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_OVER) << BIT_SHIFT_IC_INTR_MASK_M_RX_OVER)
|
||||
|
||||
#define BIT_IC_INTR_MASK_M_RX_UNDER BIT(0)
|
||||
#define BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER 0
|
||||
#define BIT_MASK_IC_INTR_MASK_M_RX_UNDER 0x1
|
||||
#define BIT_CTRL_IC_INTR_MASK_M_RX_UNDER(x) (((x) & BIT_MASK_IC_INTR_MASK_M_RX_UNDER) << BIT_SHIFT_IC_INTR_MASK_M_RX_UNDER)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_RAW_INTR_STAT
|
||||
#define BIT_IC_RAW_INTR_STAT_GEN_CALL BIT(11)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL 11
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_GEN_CALL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_GEN_CALL) << BIT_SHIFT_IC_RAW_INTR_STAT_GEN_CALL)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_START_DET BIT(10)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_START_DET 10
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_START_DET 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_START_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_START_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_START_DET)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_STOP_DET BIT(9)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET 9
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_STOP_DET 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_STOP_DET(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_STOP_DET) << BIT_SHIFT_IC_RAW_INTR_STAT_STOP_DET)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_ACTIVITY BIT(8)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY 8
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_ACTIVITY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_ACTIVITY) << BIT_SHIFT_IC_RAW_INTR_STAT_ACTIVITY)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_RX_DONE BIT(7)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE 7
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_RX_DONE 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_DONE(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_DONE) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_DONE)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_TX_ABRT BIT(6)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT 6
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_ABRT(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_ABRT) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_ABRT)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_RD_REQ BIT(5)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ 5
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_RD_REQ 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_RD_REQ(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RD_REQ) << BIT_SHIFT_IC_RAW_INTR_STAT_RD_REQ)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_TX_EMPTY BIT(4)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY 4
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_EMPTY(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_EMPTY) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_EMPTY)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_TX_OVER BIT(3)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER 3
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_TX_OVER 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_TX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_TX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_TX_OVER)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_RX_FULL BIT(2)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL 2
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_RX_FULL 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_FULL(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_FULL) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_FULL)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_RX_OVER BIT(1)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER 1
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_RX_OVER 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_OVER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_OVER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_OVER)
|
||||
|
||||
#define BIT_IC_RAW_INTR_STAT_RX_UNDER BIT(0)
|
||||
#define BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER 0
|
||||
#define BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER 0x1
|
||||
#define BIT_CTRL_IC_RAW_INTR_STAT_RX_UNDER(x) (((x) & BIT_MASK_IC_RAW_INTR_STAT_RX_UNDER) << BIT_SHIFT_IC_RAW_INTR_STAT_RX_UNDER)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_RX_TL
|
||||
|
||||
#define BIT_SHIFT_IC_RX_TL 0
|
||||
#define BIT_MASK_IC_RX_TL 0xff
|
||||
#define BIT_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
|
||||
#define BIT_CTRL_IC_RX_TL(x) (((x) & BIT_MASK_IC_RX_TL) << BIT_SHIFT_IC_RX_TL)
|
||||
#define BIT_GET_IC_RX_TL(x) (((x) >> BIT_SHIFT_IC_RX_TL) & BIT_MASK_IC_RX_TL)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_TX_TL
|
||||
|
||||
#define BIT_SHIFT_IC_TX_TL 0
|
||||
#define BIT_MASK_IC_TX_TL 0xff
|
||||
#define BIT_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
|
||||
#define BIT_CTRL_IC_TX_TL(x) (((x) & BIT_MASK_IC_TX_TL) << BIT_SHIFT_IC_TX_TL)
|
||||
#define BIT_GET_IC_TX_TL(x) (((x) >> BIT_SHIFT_IC_TX_TL) & BIT_MASK_IC_TX_TL)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_INTR
|
||||
#define BIT_IC_CLR_INTR BIT(0)
|
||||
#define BIT_SHIFT_IC_CLR_INTR 0
|
||||
#define BIT_MASK_IC_CLR_INTR 0x1
|
||||
#define BIT_CTRL_IC_CLR_INTR(x) (((x) & BIT_MASK_IC_CLR_INTR) << BIT_SHIFT_IC_CLR_INTR)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_RX_UNDER
|
||||
#define BIT_IC_CLR_RX_UNDER BIT(0)
|
||||
#define BIT_SHIFT_IC_CLR_RX_UNDER 0
|
||||
#define BIT_MASK_IC_CLR_RX_UNDER 0x1
|
||||
#define BIT_CTRL_IC_CLR_RX_UNDER(x) (((x) & BIT_MASK_IC_CLR_RX_UNDER) << BIT_SHIFT_IC_CLR_RX_UNDER)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_RX_OVER
|
||||
#define BIT_IC_CLR_RX_OVER BIT(0)
|
||||
#define BIT_SHIFT_IC_CLR_RX_OVER 0
|
||||
#define BIT_MASK_IC_CLR_RX_OVER 0x1
|
||||
#define BIT_CTRL_IC_CLR_RX_OVER(x) (((x) & BIT_MASK_IC_CLR_RX_OVER) << BIT_SHIFT_IC_CLR_RX_OVER)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_TX_OVER
|
||||
#define BIT_IC_CLR_TX_OVER BIT(0)
|
||||
#define BIT_SHIFT_IC_CLR_TX_OVER 0
|
||||
#define BIT_MASK_IC_CLR_TX_OVER 0x1
|
||||
#define BIT_CTRL_IC_CLR_TX_OVER(x) (((x) & BIT_MASK_IC_CLR_TX_OVER) << BIT_SHIFT_IC_CLR_TX_OVER)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_RD_REQ
|
||||
#define BIT_IC_CLR_RD_REQ BIT(0)
|
||||
#define BIT_SHIFT_IC_CLR_RD_REQ 0
|
||||
#define BIT_MASK_IC_CLR_RD_REQ 0x1
|
||||
#define BIT_CTRL_IC_CLR_RD_REQ(x) (((x) & BIT_MASK_IC_CLR_RD_REQ) << BIT_SHIFT_IC_CLR_RD_REQ)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_TX_ABRT
|
||||
#define BIT_CLR_RD_REQ BIT(0)
|
||||
#define BIT_SHIFT_CLR_RD_REQ 0
|
||||
#define BIT_MASK_CLR_RD_REQ 0x1
|
||||
#define BIT_CTRL_CLR_RD_REQ(x) (((x) & BIT_MASK_CLR_RD_REQ) << BIT_SHIFT_CLR_RD_REQ)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_RX_DONE
|
||||
#define BIT_IC_CLR_RX_DONE BIT(0)
|
||||
#define BIT_SHIFT_IC_CLR_RX_DONE 0
|
||||
#define BIT_MASK_IC_CLR_RX_DONE 0x1
|
||||
#define BIT_CTRL_IC_CLR_RX_DONE(x) (((x) & BIT_MASK_IC_CLR_RX_DONE) << BIT_SHIFT_IC_CLR_RX_DONE)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_ACTIVITY
|
||||
#define BIT_IC_CLR_ACTIVITY BIT(0)
|
||||
#define BIT_SHIFT_IC_CLR_ACTIVITY 0
|
||||
#define BIT_MASK_IC_CLR_ACTIVITY 0x1
|
||||
#define BIT_CTRL_IC_CLR_ACTIVITY(x) (((x) & BIT_MASK_IC_CLR_ACTIVITY) << BIT_SHIFT_IC_CLR_ACTIVITY)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_STOP_DET
|
||||
#define BIT_IC_CLR_STOP_DET BIT(0)
|
||||
#define BIT_SHIFT_IC_CLR_STOP_DET 0
|
||||
#define BIT_MASK_IC_CLR_STOP_DET 0x1
|
||||
#define BIT_CTRL_IC_CLR_STOP_DET(x) (((x) & BIT_MASK_IC_CLR_STOP_DET) << BIT_SHIFT_IC_CLR_STOP_DET)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_START_DET
|
||||
#define BIT_IC_CLR_START_DET BIT(0)
|
||||
#define BIT_SHIFT_IC_CLR_START_DET 0
|
||||
#define BIT_MASK_IC_CLR_START_DET 0x1
|
||||
#define BIT_CTRL_IC_CLR_START_DET(x) (((x) & BIT_MASK_IC_CLR_START_DET) << BIT_SHIFT_IC_CLR_START_DET)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_CLR_GEN_CALL
|
||||
#define BIT_IC_CLR_GEN_CALL BIT(0)
|
||||
#define BIT_SHIFT_IC_CLR_GEN_CALL 0
|
||||
#define BIT_MASK_IC_CLR_GEN_CALL 0x1
|
||||
#define BIT_CTRL_IC_CLR_GEN_CALL(x) (((x) & BIT_MASK_IC_CLR_GEN_CALL) << BIT_SHIFT_IC_CLR_GEN_CALL)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_ENABLE
|
||||
#define BIT_IC_ENABLE BIT(0)
|
||||
#define BIT_SHIFT_IC_ENABLE 0
|
||||
#define BIT_MASK_IC_ENABLE 0x1
|
||||
#define BIT_CTRL_IC_ENABLE(x) (((x) & BIT_MASK_IC_ENABLE) << BIT_SHIFT_IC_ENABLE)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_STATUS
|
||||
#define BIT_IC_STATUS_SLV_ACTIVITY BIT(6)
|
||||
#define BIT_SHIFT_IC_STATUS_SLV_ACTIVITY 6
|
||||
#define BIT_MASK_IC_STATUS_SLV_ACTIVITY 0x1
|
||||
#define BIT_CTRL_IC_STATUS_SLV_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_SLV_ACTIVITY) << BIT_SHIFT_IC_STATUS_SLV_ACTIVITY)
|
||||
|
||||
#define BIT_IC_STATUS_MST_ACTIVITY BIT(5)
|
||||
#define BIT_SHIFT_IC_STATUS_MST_ACTIVITY 5
|
||||
#define BIT_MASK_IC_STATUS_MST_ACTIVITY 0x1
|
||||
#define BIT_CTRL_IC_STATUS_MST_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_MST_ACTIVITY) << BIT_SHIFT_IC_STATUS_MST_ACTIVITY)
|
||||
|
||||
#define BIT_IC_STATUS_RFF BIT(4)
|
||||
#define BIT_SHIFT_IC_STATUS_RFF 4
|
||||
#define BIT_MASK_IC_STATUS_RFF 0x1
|
||||
#define BIT_CTRL_IC_STATUS_RFF(x) (((x) & BIT_MASK_IC_STATUS_RFF) << BIT_SHIFT_IC_STATUS_RFF)
|
||||
|
||||
#define BIT_IC_STATUS_RFNE BIT(3)
|
||||
#define BIT_SHIFT_IC_STATUS_RFNE 3
|
||||
#define BIT_MASK_IC_STATUS_RFNE 0x1
|
||||
#define BIT_CTRL_IC_STATUS_RFNE(x) (((x) & BIT_MASK_IC_STATUS_RFNE) << BIT_SHIFT_IC_STATUS_RFNE)
|
||||
|
||||
#define BIT_IC_STATUS_TFE BIT(2)
|
||||
#define BIT_SHIFT_IC_STATUS_TFE 2
|
||||
#define BIT_MASK_IC_STATUS_TFE 0x1
|
||||
#define BIT_CTRL_IC_STATUS_TFE(x) (((x) & BIT_MASK_IC_STATUS_TFE) << BIT_SHIFT_IC_STATUS_TFE)
|
||||
|
||||
#define BIT_IC_STATUS_TFNF BIT(1)
|
||||
#define BIT_SHIFT_IC_STATUS_TFNF 1
|
||||
#define BIT_MASK_IC_STATUS_TFNF 0x1
|
||||
#define BIT_CTRL_IC_STATUS_TFNF(x) (((x) & BIT_MASK_IC_STATUS_TFNF) << BIT_SHIFT_IC_STATUS_TFNF)
|
||||
|
||||
#define BIT_IC_STATUS_ACTIVITY BIT(0)
|
||||
#define BIT_SHIFT_IC_STATUS_ACTIVITY 0
|
||||
#define BIT_MASK_IC_STATUS_ACTIVITY 0x1
|
||||
#define BIT_CTRL_IC_STATUS_ACTIVITY(x) (((x) & BIT_MASK_IC_STATUS_ACTIVITY) << BIT_SHIFT_IC_STATUS_ACTIVITY)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_TXFLR
|
||||
|
||||
#define BIT_SHIFT_IC_TXFLR 0
|
||||
#define BIT_MASK_IC_TXFLR 0x3f
|
||||
#define BIT_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
|
||||
#define BIT_CTRL_IC_TXFLR(x) (((x) & BIT_MASK_IC_TXFLR) << BIT_SHIFT_IC_TXFLR)
|
||||
#define BIT_GET_IC_TXFLR(x) (((x) >> BIT_SHIFT_IC_TXFLR) & BIT_MASK_IC_TXFLR)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_RXFLR
|
||||
|
||||
#define BIT_SHIFT_IC_RXFLR 0
|
||||
#define BIT_MASK_IC_RXFLR 0x1f
|
||||
#define BIT_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
|
||||
#define BIT_CTRL_IC_RXFLR(x) (((x) & BIT_MASK_IC_RXFLR) << BIT_SHIFT_IC_RXFLR)
|
||||
#define BIT_GET_IC_RXFLR(x) (((x) >> BIT_SHIFT_IC_RXFLR) & BIT_MASK_IC_RXFLR)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_SDA_HOLD
|
||||
|
||||
#define BIT_SHIFT_IC_SDA_HOLD 0
|
||||
#define BIT_MASK_IC_SDA_HOLD 0xffff
|
||||
#define BIT_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
|
||||
#define BIT_CTRL_IC_SDA_HOLD(x) (((x) & BIT_MASK_IC_SDA_HOLD) << BIT_SHIFT_IC_SDA_HOLD)
|
||||
#define BIT_GET_IC_SDA_HOLD(x) (((x) >> BIT_SHIFT_IC_SDA_HOLD) & BIT_MASK_IC_SDA_HOLD)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_TX_ABRT_SOURCE
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX BIT(15)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 15
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST BIT(14)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 14
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO BIT(13)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 13
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST 12
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ARB_LOST(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ARB_LOST) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ARB_LOST)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS BIT(11)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 11
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT BIT(10)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 10
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 9
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT BIT(8)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 8
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET BIT(7)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 7
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET BIT(6)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 6
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ BIT(5)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 5
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK BIT(4)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 4
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK BIT(3)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 3
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK BIT(2)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 2
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK BIT(1)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 1
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK)
|
||||
|
||||
#define BIT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK BIT(0)
|
||||
#define BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0
|
||||
#define BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK 0x1
|
||||
#define BIT_CTRL_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK(x) (((x) & BIT_MASK_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK) << BIT_SHIFT_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_SLV_DATA_NACK_ONLY
|
||||
#define BIT_IC_SLV_DATA_NACK_ONLY BIT(0)
|
||||
#define BIT_SHIFT_IC_SLV_DATA_NACK_ONLY 0
|
||||
#define BIT_MASK_IC_SLV_DATA_NACK_ONLY 0x1
|
||||
#define BIT_CTRL_IC_SLV_DATA_NACK_ONLY(x) (((x) & BIT_MASK_IC_SLV_DATA_NACK_ONLY) << BIT_SHIFT_IC_SLV_DATA_NACK_ONLY)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_DMA_CR
|
||||
#define BIT_IC_DMA_CR_TDMAE BIT(1)
|
||||
#define BIT_SHIFT_IC_DMA_CR_TDMAE 1
|
||||
#define BIT_MASK_IC_DMA_CR_TDMAE 0x1
|
||||
#define BIT_CTRL_IC_DMA_CR_TDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_TDMAE) << BIT_SHIFT_IC_DMA_CR_TDMAE)
|
||||
|
||||
#define BIT_IC_DMA_CR_RDMAE BIT(0)
|
||||
#define BIT_SHIFT_IC_DMA_CR_RDMAE 0
|
||||
#define BIT_MASK_IC_DMA_CR_RDMAE 0x1
|
||||
#define BIT_CTRL_IC_DMA_CR_RDMAE(x) (((x) & BIT_MASK_IC_DMA_CR_RDMAE) << BIT_SHIFT_IC_DMA_CR_RDMAE)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_DMA_TDLR
|
||||
|
||||
#define BIT_SHIFT_IC_DMA_TDLR_DMATDL 0
|
||||
#define BIT_MASK_IC_DMA_TDLR_DMATDL 0x1f
|
||||
#define BIT_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
|
||||
#define BIT_CTRL_IC_DMA_TDLR_DMATDL(x) (((x) & BIT_MASK_IC_DMA_TDLR_DMATDL) << BIT_SHIFT_IC_DMA_TDLR_DMATDL)
|
||||
#define BIT_GET_IC_DMA_TDLR_DMATDL(x) (((x) >> BIT_SHIFT_IC_DMA_TDLR_DMATDL) & BIT_MASK_IC_DMA_TDLR_DMATDL)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_DMA_RDLR
|
||||
|
||||
#define BIT_SHIFT_IC_DMA_RDLR_DMARDL 0
|
||||
#define BIT_MASK_IC_DMA_RDLR_DMARDL 0xf
|
||||
#define BIT_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
|
||||
#define BIT_CTRL_IC_DMA_RDLR_DMARDL(x) (((x) & BIT_MASK_IC_DMA_RDLR_DMARDL) << BIT_SHIFT_IC_DMA_RDLR_DMARDL)
|
||||
#define BIT_GET_IC_DMA_RDLR_DMARDL(x) (((x) >> BIT_SHIFT_IC_DMA_RDLR_DMARDL) & BIT_MASK_IC_DMA_RDLR_DMARDL)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_SDA_SETUP
|
||||
|
||||
#define BIT_SHIFT_IC_SDA_SETUP 0
|
||||
#define BIT_MASK_IC_SDA_SETUP 0xff
|
||||
#define BIT_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
|
||||
#define BIT_CTRL_IC_SDA_SETUP(x) (((x) & BIT_MASK_IC_SDA_SETUP) << BIT_SHIFT_IC_SDA_SETUP)
|
||||
#define BIT_GET_IC_SDA_SETUP(x) (((x) >> BIT_SHIFT_IC_SDA_SETUP) & BIT_MASK_IC_SDA_SETUP)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_ACK_GENERAL_CALL
|
||||
#define BIT_IC_ACK_GENERAL_CALL BIT(0)
|
||||
#define BIT_SHIFT_IC_ACK_GENERAL_CALL 0
|
||||
#define BIT_MASK_IC_ACK_GENERAL_CALL 0x1
|
||||
#define BIT_CTRL_IC_ACK_GENERAL_CALL(x) (((x) & BIT_MASK_IC_ACK_GENERAL_CALL) << BIT_SHIFT_IC_ACK_GENERAL_CALL)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_ENABLE_STATUS
|
||||
#define BIT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST BIT(2)
|
||||
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 2
|
||||
#define BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST 0x1
|
||||
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_RX_DATA_LOST(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_RX_DATA_LOST) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_RX_DATA_LOST)
|
||||
|
||||
#define BIT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY BIT(1)
|
||||
#define BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 1
|
||||
#define BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY 0x1
|
||||
#define BIT_CTRL_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY) << BIT_SHIFT_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY)
|
||||
|
||||
#define BIT_IC_ENABLE_STATUS_IC_EN BIT(0)
|
||||
#define BIT_SHIFT_IC_ENABLE_STATUS_IC_EN 0
|
||||
#define BIT_MASK_IC_ENABLE_STATUS_IC_EN 0x1
|
||||
#define BIT_CTRL_IC_ENABLE_STATUS_IC_EN(x) (((x) & BIT_MASK_IC_ENABLE_STATUS_IC_EN) << BIT_SHIFT_IC_ENABLE_STATUS_IC_EN)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_COMP_PARAM_1
|
||||
|
||||
#define BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 16
|
||||
#define BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH 0xff
|
||||
#define BIT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
|
||||
#define BIT_CTRL_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
|
||||
#define BIT_GET_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_TX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_TX_BUFFER_DEPTH)
|
||||
|
||||
|
||||
#define BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 8
|
||||
#define BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH 0xff
|
||||
#define BIT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
|
||||
#define BIT_CTRL_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) << BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
|
||||
#define BIT_GET_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_RX_BUFFER_DEPTH) & BIT_MASK_IC_COMP_PARAM_1_RX_BUFFER_DEPTH)
|
||||
|
||||
#define BIT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS BIT(7)
|
||||
#define BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 7
|
||||
#define BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS 0x1
|
||||
#define BIT_CTRL_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS) << BIT_SHIFT_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS)
|
||||
|
||||
#define BIT_IC_COMP_PARAM_1_HAS_DMA BIT(6)
|
||||
#define BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA 6
|
||||
#define BIT_MASK_IC_COMP_PARAM_1_HAS_DMA 0x1
|
||||
#define BIT_CTRL_IC_COMP_PARAM_1_HAS_DMA(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HAS_DMA) << BIT_SHIFT_IC_COMP_PARAM_1_HAS_DMA)
|
||||
|
||||
#define BIT_IC_COMP_PARAM_1_INTR_IO BIT(5)
|
||||
#define BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO 5
|
||||
#define BIT_MASK_IC_COMP_PARAM_1_INTR_IO 0x1
|
||||
#define BIT_CTRL_IC_COMP_PARAM_1_INTR_IO(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_INTR_IO) << BIT_SHIFT_IC_COMP_PARAM_1_INTR_IO)
|
||||
|
||||
#define BIT_IC_COMP_PARAM_1_HC_COUNT_VALUES BIT(4)
|
||||
#define BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES 4
|
||||
#define BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES 0x1
|
||||
#define BIT_CTRL_IC_COMP_PARAM_1_HC_COUNT_VALUES(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_HC_COUNT_VALUES) << BIT_SHIFT_IC_COMP_PARAM_1_HC_COUNT_VALUES)
|
||||
|
||||
|
||||
#define BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE 2
|
||||
#define BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE 0x3
|
||||
#define BIT_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
|
||||
#define BIT_CTRL_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE) << BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE)
|
||||
#define BIT_GET_IC_COMP_PARAM_1_MAX_SPEED_MODE(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_MAX_SPEED_MODE) & BIT_MASK_IC_COMP_PARAM_1_MAX_SPEED_MODE)
|
||||
|
||||
|
||||
#define BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH 0
|
||||
#define BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH 0x3
|
||||
#define BIT_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
|
||||
#define BIT_CTRL_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH) << BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH)
|
||||
#define BIT_GET_IC_COMP_PARAM_1_APB_DATA_WIDTH(x) (((x) >> BIT_SHIFT_IC_COMP_PARAM_1_APB_DATA_WIDTH) & BIT_MASK_IC_COMP_PARAM_1_APB_DATA_WIDTH)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_COMP_VERSION
|
||||
|
||||
#define BIT_SHIFT_IC_COMP_VERSION 0
|
||||
#define BIT_MASK_IC_COMP_VERSION 0xffffffffL
|
||||
#define BIT_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
|
||||
#define BIT_CTRL_IC_COMP_VERSION(x) (((x) & BIT_MASK_IC_COMP_VERSION) << BIT_SHIFT_IC_COMP_VERSION)
|
||||
#define BIT_GET_IC_COMP_VERSION(x) (((x) >> BIT_SHIFT_IC_COMP_VERSION) & BIT_MASK_IC_COMP_VERSION)
|
||||
|
||||
|
||||
//2 REG_DW_I2C_IC_COMP_TYPE
|
||||
|
||||
#define BIT_SHIFT_IC_COMP_TYPE 0
|
||||
#define BIT_MASK_IC_COMP_TYPE 0xffffffffL
|
||||
#define BIT_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
|
||||
#define BIT_CTRL_IC_COMP_TYPE(x) (((x) & BIT_MASK_IC_COMP_TYPE) << BIT_SHIFT_IC_COMP_TYPE)
|
||||
#define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE)
|
||||
|
||||
//======================== Register Address Definition ========================
|
||||
#define REG_DW_I2C_IC_CON 0x0000
|
||||
#define REG_DW_I2C_IC_TAR 0x0004
|
||||
#define REG_DW_I2C_IC_SAR 0x0008
|
||||
#define REG_DW_I2C_IC_HS_MADDR 0x000C
|
||||
#define REG_DW_I2C_IC_DATA_CMD 0x0010
|
||||
#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014
|
||||
#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018
|
||||
#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C
|
||||
#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020
|
||||
#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024
|
||||
#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028
|
||||
#define REG_DW_I2C_IC_INTR_STAT 0x002C
|
||||
#define REG_DW_I2C_IC_INTR_MASK 0x0030
|
||||
#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034
|
||||
#define REG_DW_I2C_IC_RX_TL 0x0038
|
||||
#define REG_DW_I2C_IC_TX_TL 0x003C
|
||||
#define REG_DW_I2C_IC_CLR_INTR 0x0040
|
||||
#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044
|
||||
#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048
|
||||
#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C
|
||||
#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050
|
||||
#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054
|
||||
#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058
|
||||
#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C
|
||||
#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060
|
||||
#define REG_DW_I2C_IC_CLR_START_DET 0x0064
|
||||
#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068
|
||||
#define REG_DW_I2C_IC_ENABLE 0x006C
|
||||
#define REG_DW_I2C_IC_STATUS 0x0070
|
||||
#define REG_DW_I2C_IC_TXFLR 0x0074
|
||||
#define REG_DW_I2C_IC_RXFLR 0x0078
|
||||
#define REG_DW_I2C_IC_SDA_HOLD 0x007C
|
||||
#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080
|
||||
#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084
|
||||
#define REG_DW_I2C_IC_DMA_CR 0x0088
|
||||
#define REG_DW_I2C_IC_DMA_TDLR 0x008C
|
||||
#define REG_DW_I2C_IC_DMA_RDLR 0x0090
|
||||
#define REG_DW_I2C_IC_SDA_SETUP 0x0094
|
||||
#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098
|
||||
#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C
|
||||
#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4
|
||||
#define REG_DW_I2C_IC_COMP_VERSION 0x00F8
|
||||
#define REG_DW_I2C_IC_COMP_TYPE 0x00FC
|
||||
|
||||
//======================================================
|
||||
// I2C related enumeration
|
||||
// I2C Address Mode
|
||||
typedef enum _I2C_ADDR_MODE_ {
|
||||
I2C_ADDR_7BIT = 0,
|
||||
I2C_ADDR_10BIT = 1,
|
||||
}I2C_ADDR_MODE,*PI2C_ADDR_MODE;
|
||||
|
||||
// I2C Speed Mode
|
||||
typedef enum _I2C_SPD_MODE_ {
|
||||
I2C_SS_MODE = 1,
|
||||
I2C_FS_MODE = 2,
|
||||
I2C_HS_MODE = 3,
|
||||
}I2C_SPD_MODE,*PI2C_SPD_MODE;
|
||||
|
||||
//I2C Timing Parameters
|
||||
#define I2C_SS_MIN_SCL_HTIME 4000 //the unit is ns.
|
||||
#define I2C_SS_MIN_SCL_LTIME 4700 //the unit is ns.
|
||||
|
||||
#define I2C_FS_MIN_SCL_HTIME 600 //the unit is ns.
|
||||
#define I2C_FS_MIN_SCL_LTIME 1300 //the unit is ns.
|
||||
|
||||
#define I2C_HS_MIN_SCL_HTIME_100 60 //the unit is ns, with bus loading = 100pf
|
||||
#define I2C_HS_MIN_SCL_LTIME_100 120 //the unit is ns., with bus loading = 100pf
|
||||
|
||||
#define I2C_HS_MIN_SCL_HTIME_400 160 //the unit is ns, with bus loading = 400pf
|
||||
#define I2C_HS_MIN_SCL_LTIME_400 320 //the unit is ns., with bus loading = 400pf
|
||||
|
||||
|
||||
//======================================================
|
||||
//I2C Essential functions and macros
|
||||
_LONG_CALL_ROM_ VOID HalI2CWrite32(IN u8 I2CIdx, IN u8 I2CReg, IN u32 I2CVal);
|
||||
_LONG_CALL_ROM_ u32 HalI2CRead32(IN u8 I2CIdx, IN u8 I2CReg);
|
||||
|
||||
#define HAL_I2C_WRITE32(I2CIdx, addr, value) HalI2CWrite32(I2CIdx,addr,value)
|
||||
#define HAL_I2C_READ32(I2CIdx, addr) HalI2CRead32(I2CIdx,addr)
|
||||
|
||||
// Rtl8195a I2C function prototypes
|
||||
_LONG_CALL_ HAL_Status HalI2CEnableRtl8195a(IN VOID *Data);
|
||||
_LONG_CALL_ HAL_Status HalI2CInit8195a(IN VOID *Data);
|
||||
_LONG_CALL_ HAL_Status HalI2CDeInit8195a(IN VOID *Data);
|
||||
_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195a(IN VOID *Data);
|
||||
_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a(IN VOID *Data);
|
||||
_LONG_CALL_ HAL_Status HalI2CSendRtl8195a(IN VOID *Data);
|
||||
_LONG_CALL_ u8 HalI2CReceiveRtl8195a(IN VOID *Data);
|
||||
_LONG_CALL_ROM_ HAL_Status HalI2CIntrCtrl8195a(IN VOID *Data);
|
||||
_LONG_CALL_ HAL_Status HalI2CClrIntrRtl8195a(IN VOID *Data);
|
||||
_LONG_CALL_ROM_ HAL_Status HalI2CClrAllIntrRtl8195a(IN VOID *Data);
|
||||
_LONG_CALL_ HAL_Status HalI2CDMACtrl8195a(IN VOID *Data);
|
||||
_LONG_CALL_ u32 HalI2CReadRegRtl8195a(IN VOID *Data, IN u8 I2CReg);
|
||||
_LONG_CALL_ HAL_Status HalI2CWriteRegRtl8195a(IN VOID *Data, IN u8 I2CReg, IN u32 RegVal);
|
||||
|
||||
//Rtl8195a I2C V02 function prototype
|
||||
_LONG_CALL_ HAL_Status HalI2CSendRtl8195aV02(IN VOID *Data);
|
||||
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
|
||||
_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
|
||||
#elif defined(CONFIG_CHIP_E_CUT)
|
||||
_LONG_CALL_ROM_ HAL_Status HalI2CSetCLKRtl8195aV02(IN VOID *Data);
|
||||
#endif
|
||||
//Rtl8195a I2C V02 function prototype END
|
||||
|
||||
//Rtl8195a I2C V04 function prototype
|
||||
_LONG_CALL_ HAL_Status HalI2CSendRtl8195a_V04(IN VOID *Data);
|
||||
_LONG_CALL_ HAL_Status HalI2CMassSendRtl8195a_V04(IN VOID *Data);
|
||||
_LONG_CALL_ HAL_Status HalI2CInit8195a_V04(IN VOID *Data);
|
||||
_LONG_CALL_ HAL_Status HalI2CSetCLKRtl8195a_V04(IN VOID *Data);
|
||||
//Rtl8195a I2C V04 function prototype END
|
||||
|
||||
HAL_Status HalI2CInit8195a_Patch(IN VOID *Data);
|
||||
HAL_Status HalI2CSendRtl8195a_Patch(IN VOID *Data);
|
||||
HAL_Status HalI2CSetCLKRtl8195a_Patch(IN VOID *Data);
|
||||
HAL_Status HalI2CMassSendRtl8195a_Patch(IN VOID *Data);
|
||||
HAL_Status HalI2CEnableRtl8195a_Patch(IN VOID *Data);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,723 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RTL8195A_I2S_H_
|
||||
#define _RTL8195A_I2S_H_
|
||||
|
||||
|
||||
//=============== Register Bit Field Definition ====================
|
||||
// REG_I2S_CONTROL
|
||||
#define BIT_CTLX_I2S_EN BIT(0)
|
||||
#define BIT_SHIFT_CTLX_I2S_EN 0
|
||||
#define BIT_MASK_CTLX_I2S_EN 0x1
|
||||
#define BIT_CTRL_CTLX_I2S_EN(x) (((x) & BIT_MASK_CTLX_I2S_EN) << BIT_SHIFT_CTLX_I2S_EN)
|
||||
|
||||
#define BIT_SHIFT_CTLX_I2S_TRX_ACT 1
|
||||
#define BIT_MASK_CTLX_I2S_TRX_ACT 0x3
|
||||
#define BIT_CTRL_CTLX_I2S_TRX_ACT(x) (((x) & BIT_MASK_CTLX_I2S_TRX_ACT) << BIT_SHIFT_CTLX_I2S_TRX_ACT)
|
||||
#define BIT_GET_CTLX_I2S_TRX_ACT(x) (((x) >> BIT_SHIFT_CTLX_I2S_TRX_ACT) & BIT_MASK_CTLX_I2S_TRX_ACT)
|
||||
|
||||
#define BIT_SHIFT_CTLX_I2S_CH_NUM 3
|
||||
#define BIT_MASK_CTLX_I2S_CH_NUM 0x3
|
||||
#define BIT_CTRL_CTLX_I2S_CH_NUM(x) (((x) & BIT_MASK_CTLX_I2S_CH_NUM) << BIT_SHIFT_CTLX_I2S_CH_NUM)
|
||||
#define BIT_GET_CTLX_I2S_CH_NUM(x) (((x) >> BIT_SHIFT_CTLX_I2S_CH_NUM) & BIT_MASK_CTLX_I2S_CH_NUM)
|
||||
//pvvx?
|
||||
#define BIT_CTLX_I2S_EDGE_SW 5
|
||||
#define BIT_MASK_CTLX_EDGE_SW 0x1
|
||||
#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW)
|
||||
#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW))
|
||||
|
||||
#define BIT_CTLX_I2S_WL BIT(6)
|
||||
#define BIT_SHIFT_CTLX_I2S_WL 6
|
||||
#define BIT_MASK_CTLX_I2S_WL 0x1
|
||||
#define BIT_CTRL_CTLX_I2S_WL(x) (((x) & BIT_MASK_CTLX_I2S_WL) << BIT_SHIFT_CTLX_I2S_WL)
|
||||
//pvvx?
|
||||
#define BIT_CTLX_I2S_LOOP_BACK 7
|
||||
#define BIT_MASK_CTLX_LOOP_BACK 0x1
|
||||
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_CTLX_I2S_LOOP_BACK)
|
||||
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_CTLX_I2S_LOOP_BACK))
|
||||
//pvvx?
|
||||
#define BIT_CTLX_I2S_FORMAT 8
|
||||
#define BIT_MASK_CTLX_FORMAT 0x3
|
||||
#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_CTLX_I2S_FORMAT)
|
||||
#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_CTLX_I2S_FORMAT))
|
||||
|
||||
#define BIT_CTLX_I2S_LRSWAP BIT(10)
|
||||
#define BIT_SHIFT_CTLX_I2S_LRSWAP 10
|
||||
#define BIT_MASK_CTLX_I2S_LRSWAP 0x1
|
||||
#define BIT_CTRL_CTLX_I2S_LRSWAP(x) (((x) & BIT_MASK_CTLX_I2S_LRSWAP) << BIT_SHIFT_CTLX_I2S_LRSWAP)
|
||||
|
||||
#define BIT_CTLX_I2S_SCK_INV BIT(11)
|
||||
#define BIT_SHIFT_CTLX_I2S_SCK_INV 11
|
||||
#define BIT_MASK_CTLX_I2S_SCK_INV 0x1
|
||||
#define BIT_CTRL_CTLX_I2S_SCK_INV(x) (((x) & BIT_MASK_CTLX_I2S_SCK_INV) << BIT_SHIFT_CTLX_I2S_SCK_INV)
|
||||
|
||||
#define BIT_CTLX_I2S_ENDIAN_SWAP BIT(12)
|
||||
#define BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP 12
|
||||
#define BIT_MASK_CTLX_I2S_ENDIAN_SWAP 0x1
|
||||
#define BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_I2S_ENDIAN_SWAP) << BIT_SHIFT_CTLX_I2S_ENDIAN_SWAP)
|
||||
|
||||
#define BIT_CTLX_I2S_SLAVE_MODE BIT(29)
|
||||
#define BIT_SHIFT_CTLX_I2S_SLAVE_MODE 29
|
||||
#define BIT_MASK_CTLX_I2S_SLAVE_MODE 0x1
|
||||
#define BIT_CTRL_CTLX_I2S_SLAVE_MODE(x) (((x) & BIT_MASK_CTLX_I2S_SLAVE_MODE) << BIT_SHIFT_CTLX_I2S_SLAVE_MODE)
|
||||
|
||||
#define BIT_CTLX_I2S_CLK_SRC BIT(30)
|
||||
#define BIT_SHIFT_CTLX_I2S_CLK_SRC 30
|
||||
#define BIT_MASK_CTLX_I2S_CLK_SRC 0x1
|
||||
#define BIT_CTRL_CTLX_I2S_CLK_SRC(x) (((x) & BIT_MASK_CTLX_I2S_CLK_SRC) << BIT_SHIFT_CTLX_I2S_CLK_SRC)
|
||||
|
||||
#define BIT_CTLX_I2S_SW_RSTN BIT(31)
|
||||
#define BIT_SHIFT_CTLX_I2S_SW_RSTN 31
|
||||
#define BIT_MASK_CTLX_I2S_SW_RSTN 0x1
|
||||
#define BIT_CTRL_CTLX_I2S_SW_RSTN(x) (((x) & BIT_MASK_CTLX_I2S_SW_RSTN) << BIT_SHIFT_CTLX_I2S_SW_RSTN)
|
||||
|
||||
// REG_I2S_SETTING
|
||||
#define BIT_SHIFT_SETTING_I2S_PAGE_SZ 0
|
||||
#define BIT_MASK_SETTING_I2S_PAGE_SZ 0xFFF
|
||||
#define BIT_CTRL_SETTING_I2S_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_SZ) << BIT_SHIFT_SETTING_I2S_PAGE_SZ)
|
||||
#define BIT_GET_SETTING_I2S_PAGE_SZ(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_SZ) & BIT_MASK_SETTING_I2S_PAGE_SZ)
|
||||
|
||||
#define BIT_SHIFT_SETTING_I2S_PAGE_NUM 12
|
||||
#define BIT_MASK_SETTING_I2S_PAGE_NUM 0x3
|
||||
#define BIT_CTRL_SETTING_I2S_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_I2S_PAGE_NUM) << BIT_SHIFT_SETTING_I2S_PAGE_NUM)
|
||||
#define BIT_GET_SETTING_I2S_PAGE_NUM(x) (((x) >> BIT_SHIFT_SETTING_I2S_PAGE_NUM) & BIT_MASK_SETTING_I2S_PAGE_NUM)
|
||||
|
||||
#define BIT_SHIFT_SETTING_I2S_SAMPLE_RATE 14
|
||||
#define BIT_MASK_SETTING_I2S_SAMPLE_RATE 0x7
|
||||
#define BIT_CTRL_SETTING_I2S_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_I2S_SAMPLE_RATE) << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE)
|
||||
#define BIT_GET_SETTING_I2S_SAMPLE_RATE(x) (((x) >> BIT_SHIFT_SETTING_I2S_SAMPLE_RATE) & BIT_MASK_SETTING_I2S_SAMPLE_RATE)
|
||||
|
||||
// i2s trx page own bit
|
||||
#define BIT_PAGE_I2S_OWN_BIT BIT(31)
|
||||
#define BIT_SHIFT_PAGE_I2S_OWN_BIT 31
|
||||
#define BIT_MASK_PAGE_I2S_OWN_BIT 0x1
|
||||
#define BIT_CTRL_PAGE_I2S_OWN_BIT(x) (((x) & BIT_MASK_PAGE_I2S_OWN_BIT) << BIT_SHIFT_PAGE_I2S_OWN_BIT)
|
||||
|
||||
//=============== Register Address Definition ====================
|
||||
#define REG_I2S_PAGE_OWN_OFF 0x004
|
||||
|
||||
#define REG_I2S_CTL 0x000
|
||||
#define REG_I2S_TX_PAGE_PTR 0x004
|
||||
#define REG_I2S_RX_PAGE_PTR 0x008
|
||||
#define REG_I2S_SETTING 0x00C
|
||||
|
||||
#define REG_I2S_TX_MASK_INT 0x010
|
||||
#define REG_I2S_TX_STATUS_INT 0x014
|
||||
#define REG_I2S_RX_MASK_INT 0x018
|
||||
#define REG_I2S_RX_STATUS_INT 0x01c
|
||||
|
||||
#define REG_I2S_TX_PAGE0_OWN 0x020
|
||||
#define REG_I2S_TX_PAGE1_OWN 0x024
|
||||
#define REG_I2S_TX_PAGE2_OWN 0x028
|
||||
#define REG_I2S_TX_PAGE3_OWN 0x02C
|
||||
#define REG_I2S_RX_PAGE0_OWN 0x030
|
||||
#define REG_I2S_RX_PAGE1_OWN 0x034
|
||||
#define REG_I2S_RX_PAGE2_OWN 0x038
|
||||
#define REG_I2S_RX_PAGE3_OWN 0x03C
|
||||
|
||||
/*I2S Essential Functions and Macros*/
|
||||
VOID
|
||||
HalI2SWrite32(
|
||||
IN u8 I2SIdx,
|
||||
IN u8 I2SReg,
|
||||
IN u32 I2SVal
|
||||
);
|
||||
|
||||
u32
|
||||
HalI2SRead32(
|
||||
IN u8 I2SIdx,
|
||||
IN u8 I2SReg
|
||||
);
|
||||
|
||||
/*
|
||||
#define HAL_I2SX_READ32(I2sIndex, addr) \
|
||||
HAL_READ32(I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF), addr)
|
||||
#define HAL_I2SX_WRITE32(I2sIndex, addr, value) \
|
||||
HAL_WRITE32((I2S0_REG_BASE+ (I2sIndex*I2S1_REG_OFF)), addr, value)
|
||||
*/
|
||||
|
||||
#define HAL_I2S_WRITE32(I2SIdx, addr, value) HalI2SWrite32(I2SIdx,addr,value)
|
||||
#define HAL_I2S_READ32(I2SIdx, addr) HalI2SRead32(I2SIdx,addr)
|
||||
|
||||
/* I2S debug output*/
|
||||
#define I2S_PREFIX "RTL8195A[i2s]: "
|
||||
#define I2S_PREFIX_LVL " [i2s_DBG]: "
|
||||
|
||||
typedef enum _I2S_DBG_LVL_ {
|
||||
HAL_I2S_LVL = 0x01,
|
||||
SAL_I2S_LVL = 0x02,
|
||||
VERI_I2S_LVL = 0x03,
|
||||
}I2S_DBG_LVL,*PI2S_DBG_LVL;
|
||||
|
||||
#if CONFIG_DEBUG_LOG > 0
|
||||
#ifdef CONFIG_DEBUG_LOG_I2S_HAL
|
||||
|
||||
#define DBG_8195A_I2S(...) do{ \
|
||||
_DbgDump(I2S_PREFIX __VA_ARGS__);\
|
||||
}while(0)
|
||||
|
||||
|
||||
#define I2SDBGLVL 0xFF
|
||||
#define DBG_8195A_I2S_LVL(LVL,...) do{\
|
||||
if (LVL&I2SDBGLVL){\
|
||||
_DbgDump(I2S_PREFIX_LVL __VA_ARGS__);\
|
||||
}\
|
||||
}while(0)
|
||||
#else
|
||||
#define DBG_I2S_LOG_PERD 100
|
||||
#define DBG_8195A_I2S(...)
|
||||
#define DBG_8195A_I2S_LVL(...)
|
||||
#endif
|
||||
#else
|
||||
#define DBG_I2S_LOG_PERD 100
|
||||
#define DBG_8195A_I2S(...)
|
||||
#define DBG_8195A_I2S_LVL(...)
|
||||
#endif
|
||||
|
||||
/*
|
||||
#define REG_I2S_PAGE_OWN_OFF 0x004
|
||||
#define REG_I2S_CTL 0x000
|
||||
#define REG_I2S_TX_PAGE_PTR 0x004
|
||||
#define REG_I2S_RX_PAGE_PTR 0x008
|
||||
#define REG_I2S_SETTING 0x00C
|
||||
|
||||
#define REG_I2S_TX_MASK_INT 0x010
|
||||
#define REG_I2S_TX_STATUS_INT 0x014
|
||||
#define REG_I2S_RX_MASK_INT 0x018
|
||||
#define REG_I2S_RX_STATUS_INT 0x01c
|
||||
|
||||
|
||||
|
||||
#define REG_I2S_TX_PAGE0_OWN 0x020
|
||||
#define REG_I2S_TX_PAGE1_OWN 0x024
|
||||
#define REG_I2S_TX_PAGE2_OWN 0x028
|
||||
#define REG_I2S_TX_PAGE3_OWN 0x02C
|
||||
#define REG_I2S_RX_PAGE0_OWN 0x030
|
||||
#define REG_I2S_RX_PAGE1_OWN 0x034
|
||||
#define REG_I2S_RX_PAGE2_OWN 0x038
|
||||
#define REG_I2S_RX_PAGE3_OWN 0x03C
|
||||
*/
|
||||
/* template
|
||||
#define BIT_SHIFT_CTLX_ 7
|
||||
#define BIT_MASK_CTLX_ 0x1
|
||||
#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
|
||||
#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
|
||||
*//*
|
||||
#define BIT_SHIFT_CTLX_IIS_EN 0
|
||||
#define BIT_MASK_CTLX_IIS_EN 0x1
|
||||
#define BIT_CTLX_IIS_EN(x) (((x) & BIT_MASK_CTLX_IIS_EN) << BIT_SHIFT_CTLX_IIS_EN)
|
||||
#define BIT_INV_CTLX_IIS_EN (~(BIT_MASK_CTLX_IIS_EN << BIT_SHIFT_CTLX_IIS_EN))
|
||||
|
||||
#define BIT_SHIFT_CTLX_TRX 1
|
||||
#define BIT_MASK_CTLX_TRX 0x3
|
||||
#define BIT_CTLX_TRX(x) (((x) & BIT_MASK_CTLX_TRX) << BIT_SHIFT_CTLX_TRX)
|
||||
#define BIT_INV_CTLX_TRX (~(BIT_MASK_CTLX_TRX << BIT_SHIFT_CTLX_TRX))
|
||||
|
||||
#define BIT_SHIFT_CTLX_CH_NUM 3
|
||||
#define BIT_MASK_CTLX_CH_NUM 0x3
|
||||
#define BIT_CTLX_CH_NUM(x) (((x) & BIT_MASK_CTLX_CH_NUM) << BIT_SHIFT_CTLX_CH_NUM)
|
||||
#define BIT_INV_CTLX_CH_NUM (~(BIT_MASK_CTLX_CH_NUM << BIT_SHIFT_CTLX_CH_NUM))
|
||||
|
||||
#define BIT_SHIFT_CTLX_EDGE_SW 5
|
||||
#define BIT_MASK_CTLX_EDGE_SW 0x1
|
||||
#define BIT_CTLX_EDGE_SW(x) (((x) & BIT_MASK_CTLX_EDGE_SW) << BIT_SHIFT_CTLX_EDGE_SW)
|
||||
#define BIT_INV_CTLX_EDGE_SW (~(BIT_MASK_CTLX_EDGE_SW << BIT_SHIFT_CTLX_EDGE_SW))
|
||||
|
||||
#define BIT_SHIFT_CTLX_WL 6
|
||||
#define BIT_MASK_CTLX_WL 0x1
|
||||
#define BIT_CTLX_WL(x) (((x) & BIT_MASK_CTLX_WL) << BIT_SHIFT_CTLX_WL)
|
||||
#define BIT_INV_CTLX_WL (~(BIT_MASK_CTLX_WL << BIT_SHIFT_CTLX_WL))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LOOP_BACK 7
|
||||
#define BIT_MASK_CTLX_LOOP_BACK 0x1
|
||||
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
|
||||
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
|
||||
|
||||
#define BIT_SHIFT_CTLX_FORMAT 8
|
||||
#define BIT_MASK_CTLX_FORMAT 0x3
|
||||
#define BIT_CTLX_FORMAT(x) (((x) & BIT_MASK_CTLX_FORMAT) << BIT_SHIFT_CTLX_FORMAT)
|
||||
#define BIT_INV_CTLX_FORMAT (~(BIT_MASK_CTLX_FORMAT << BIT_SHIFT_CTLX_FORMAT))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LRSWAP 10
|
||||
#define BIT_MASK_CTLX_LRSWAP 0x1
|
||||
#define BIT_CTLX_LRSWAP(x) (((x) & BIT_MASK_CTLX_LRSWAP) << BIT_SHIFT_CTLX_LRSWAP)
|
||||
#define BIT_INV_CTLX_LRSWAP (~(BIT_MASK_CTLX_LRSWAP << BIT_SHIFT_CTLX_LRSWAP))
|
||||
|
||||
#define BIT_SHIFT_CTLX_SCK_INV 11
|
||||
#define BIT_MASK_CTLX_SCK_INV 0x1
|
||||
#define BIT_CTLX_SCK_INV(x) (((x) & BIT_MASK_CTLX_SCK_INV) << BIT_SHIFT_CTLX_SCK_INV)
|
||||
#define BIT_INV_CTLX_SCK_INV (~(BIT_MASK_CTLX_SCK_INV << BIT_SHIFT_CTLX_SCK_INV))
|
||||
|
||||
#define BIT_SHIFT_CTLX_ENDIAN_SWAP 12
|
||||
#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1
|
||||
#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
|
||||
#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
|
||||
|
||||
#define BIT_SHIFT_CTLX_DEBUG_SWITCH 15
|
||||
#define BIT_MASK_CTLX_DEBUG_SWITCH 0x3
|
||||
#define BIT_CTLX_DEBUG_SWITCH(x) (((x) & BIT_MASK_CTLX_DEBUG_SWITCH) << BIT_SHIFT_CTLX_DEBUG_SWITCH)
|
||||
#define BIT_INV_CTLX_DEBUG_SWITCH (~(BIT_MASK_CTLX_DEBUG_SWITCH << BIT_SHIFT_CTLX_DEBUG_SWITCH))
|
||||
|
||||
#define BIT_SHIFT_CTLX_SLAVE_SEL 29
|
||||
#define BIT_MASK_CTLX_SLAVE_SEL 0x1
|
||||
#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
|
||||
#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
|
||||
|
||||
#define BIT_SHIFT_CTLX_CLK_SRC 30
|
||||
#define BIT_MASK_CTLX_CLK_SRC 0x1
|
||||
#define BIT_CTLX_CLK_SRC(x) (((x) & BIT_MASK_CTLX_CLK_SRC) << BIT_SHIFT_CTLX_CLK_SRC)
|
||||
#define BIT_INV_CTLX_CLK_SRC (~(BIT_MASK_CTLX_CLK_SRC << BIT_SHIFT_CTLX_CLK_SRC))
|
||||
|
||||
#define BIT_SHIFT_CTLX_SW_RSTN 31
|
||||
#define BIT_MASK_CTLX_SW_RSTN 0x1
|
||||
#define BIT_CTLX_SW_RSTN(x) (((x) & BIT_MASK_CTLX_SW_RSTN) << BIT_SHIFT_CTLX_SW_RSTN)
|
||||
#define BIT_INV_CTLX_SW_RSTN (~(BIT_MASK_CTLX_SW_RSTN << BIT_SHIFT_CTLX_SW_RSTN))
|
||||
|
||||
|
||||
#define BIT_SHIFT_SETTING_PAGE_SZ 0
|
||||
#define BIT_MASK_SETTING_PAGE_SZ 0xFFF
|
||||
#define BIT_SETTING_PAGE_SZ(x) (((x) & BIT_MASK_SETTING_PAGE_SZ) << BIT_SHIFT_SETTING_PAGE_SZ)
|
||||
#define BIT_INV_SETTING_PAGE_SZ (~(BIT_MASK_SETTING_PAGE_SZ << BIT_SHIFT_SETTING_PAGE_SZ))
|
||||
|
||||
#define BIT_SHIFT_SETTING_PAGE_NUM 12
|
||||
#define BIT_MASK_SETTING_PAGE_NUM 0x3
|
||||
#define BIT_SETTING_PAGE_NUM(x) (((x) & BIT_MASK_SETTING_PAGE_NUM) << BIT_SHIFT_SETTING_PAGE_NUM)
|
||||
#define BIT_INV_SETTING_PAGE_NUM (~(BIT_MASK_SETTING_PAGE_NUM << BIT_SHIFT_SETTING_PAGE_NUM))
|
||||
|
||||
#define BIT_SHIFT_SETTING_SAMPLE_RATE 14
|
||||
#define BIT_MASK_SETTING_SAMPLE_RATE 0x7
|
||||
#define BIT_SETTING_SAMPLE_RATE(x) (((x) & BIT_MASK_SETTING_SAMPLE_RATE) << BIT_SHIFT_SETTING_SAMPLE_RATE)
|
||||
#define BIT_INV_SETTING_SAMPLE_RATE (~(BIT_MASK_SETTING_SAMPLE_RATE << BIT_SHIFT_SETTING_SAMPLE_RATE))
|
||||
*/
|
||||
|
||||
typedef enum _I2S_CTL_FORMAT {
|
||||
FormatI2s = 0x00,
|
||||
FormatLeftJustified = 0x01,
|
||||
FormatRightJustified = 0x02
|
||||
}I2S_CTL_FORMAT, *PI2S_CTL_FORMAT;
|
||||
|
||||
typedef enum _I2S_CTL_CHNUM {
|
||||
ChannelStereo = 0x00,
|
||||
Channel5p1 = 0x01,
|
||||
ChannelMono = 0x02
|
||||
}I2S_CTL_CHNUM, *PI2S_CTL_CHNUM;
|
||||
|
||||
typedef enum _I2S_CTL_TRX_ACT {
|
||||
RxOnly = 0x00,
|
||||
TxOnly = 0x01,
|
||||
TXRX = 0x02
|
||||
}I2S_CTL_TRX_ACT, *PI2S_CTL_TRX_ACT;
|
||||
/*
|
||||
typedef struct _I2S_CTL_REG_ {
|
||||
I2S_CTL_FORMAT Format;
|
||||
I2S_CTL_CHNUM ChNum;
|
||||
I2S_CTL_TRX_ACT TrxAct;
|
||||
|
||||
u32 I2s_En :1; // Bit 0
|
||||
u32 Rsvd1to4 :4; // Bit 1-4 is TrxAct, ChNum
|
||||
u32 EdgeSw :1; // Bit 5 Edge switch
|
||||
u32 WordLength :1; // Bit 6
|
||||
u32 LoopBack :1; // Bit 7
|
||||
u32 Rsvd8to9 :2; // Bit 8-9 is Format
|
||||
u32 DacLrSwap :1; // Bit 10
|
||||
u32 SckInv :1; // Bit 11
|
||||
u32 EndianSwap :1; // Bit 12
|
||||
u32 Rsvd13to14 :2; // Bit 11-14
|
||||
u32 DebugSwitch :2; // Bit 15-16
|
||||
u32 Rsvd17to28 :12; // Bit 17-28
|
||||
u32 SlaveMode :1; // Bit 29
|
||||
u32 SR44p1KHz :1; // Bit 30
|
||||
u32 SwRstn :1; // Bit 31
|
||||
} I2S_CTL_REG, *PI2S_CTL_REG;
|
||||
*/
|
||||
typedef enum _I2S_SETTING_PAGE_NUM {
|
||||
I2s1Page = 0x00,
|
||||
I2s2Page = 0x01,
|
||||
I2s3Page = 0x02,
|
||||
I2s4Page = 0x03
|
||||
}I2S_SETTING_PAGE_NUM, *PI2S_SETTING_PAGE_NUM;
|
||||
|
||||
//sampling rate
|
||||
typedef enum _I2S_SETTING_SR {
|
||||
I2sSR8K = 0x00,
|
||||
I2sSR16K = 0x01,
|
||||
I2sSR24K = 0x02,
|
||||
I2sSR32K = 0x03,
|
||||
I2sSR48K = 0x05,
|
||||
I2sSR44p1K = 0x15,
|
||||
I2sSR96K = 0x06,
|
||||
I2sSR88p2K = 0x16
|
||||
}I2S_SETTING_SR, *PI2S_SETTING_SR;
|
||||
/*
|
||||
typedef struct _I2S_SETTING_REG_ {
|
||||
I2S_SETTING_PAGE_NUM PageNum;
|
||||
I2S_SETTING_SR SampleRate;
|
||||
|
||||
u32 PageSize:12; // Bit 0-11
|
||||
}I2S_SETTING_REG, *PI2S_SETTING_REG;
|
||||
|
||||
typedef enum _I2S_TX_ISR {
|
||||
I2sTxP0OK = 0x01,
|
||||
I2sTxP1OK = 0x02,
|
||||
I2sTxP2OK = 0x04,
|
||||
I2sTxP3OK = 0x08,
|
||||
I2sTxPageUn = 0x10,
|
||||
I2sTxFifoEmpty = 0x20
|
||||
}I2S_TX_ISR, *PI2S_TX_ISR;
|
||||
|
||||
typedef enum _I2S_RX_ISR {
|
||||
I2sRxP0OK = 0x01,
|
||||
I2sRxP1OK = 0x02,
|
||||
I2sRxP2OK = 0x04,
|
||||
I2sRxP3OK = 0x08,
|
||||
I2sRxPageUn = 0x10,
|
||||
I2sRxFifoFull = 0x20
|
||||
}I2S_RX_ISR, *PI2S_RX_ISR;
|
||||
*/
|
||||
|
||||
/* Hal I2S function prototype*/
|
||||
RTK_STATUS
|
||||
HalI2SInitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SInitRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SDeInitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2STxRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 *pBuff
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SRxRtl8195a(
|
||||
IN VOID *Data,
|
||||
OUT u8 *pBuff
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SEnableRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SIntrCtrlRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u32
|
||||
HalI2SReadRegRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 I2SReg
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetRateRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetWordLenRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetChNumRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetPageNumRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetPageSizeRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetDirectionRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetDMABufRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SClrIntrRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SClrAllIntrRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SDMACtrlRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u8
|
||||
HalI2SGetTxPageRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u8
|
||||
HalI2SGetRxPageRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SPageSendRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 PageIdx
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SPageRecvRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SClearAllOwnBitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#ifdef CONFIG_CHIP_E_CUT
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SInitRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SSetRateRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SSetWordLenRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SSetChNumRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SSetPageNumRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SSetPageSizeRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SSetDirectionRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SSetDMABufRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ u8
|
||||
HalI2SGetTxPageRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ u8
|
||||
HalI2SGetRxPageRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SPageSendRtl8195a_V04(
|
||||
IN VOID *Data,
|
||||
IN u8 PageIdx
|
||||
);
|
||||
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SPageRecvRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ RTK_STATUS
|
||||
HalI2SClearAllOwnBitRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#endif // #ifdef CONFIG_CHIP_E_CUT
|
||||
|
||||
// HAL functions Wrapper
|
||||
static __inline VOID
|
||||
HalI2SSetRate(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
HalI2SSetRateRtl8195a(Data);
|
||||
#else
|
||||
HalI2SSetRateRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalI2SSetWordLen(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
HalI2SSetWordLenRtl8195a(Data);
|
||||
#else
|
||||
HalI2SSetWordLenRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalI2SSetChNum(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
HalI2SSetChNumRtl8195a(Data);
|
||||
#else
|
||||
HalI2SSetChNumRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalI2SSetPageNum(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
HalI2SSetPageNumRtl8195a(Data);
|
||||
#else
|
||||
HalI2SSetPageNumRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalI2SSetPageSize(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
HalI2SSetPageSizeRtl8195a(Data);
|
||||
#else
|
||||
HalI2SSetPageSizeRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalI2SSetDirection(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
HalI2SSetDirectionRtl8195a(Data);
|
||||
#else
|
||||
HalI2SSetDirectionRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalI2SSetDMABuf(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
HalI2SSetDMABufRtl8195a(Data);
|
||||
#else
|
||||
HalI2SSetDMABufRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline u8
|
||||
HalI2SGetTxPage(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
return HalI2SGetTxPageRtl8195a(Data);
|
||||
#else
|
||||
return HalI2SGetTxPageRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline u8
|
||||
HalI2SGetRxPage(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
return HalI2SGetRxPageRtl8195a(Data);
|
||||
#else
|
||||
return HalI2SGetRxPageRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalI2SPageSend(
|
||||
IN VOID *Data,
|
||||
IN u8 PageIdx
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
HalI2SPageSendRtl8195a(Data, PageIdx);
|
||||
#else
|
||||
HalI2SPageSendRtl8195a_V04(Data, PageIdx);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalI2SPageRecv(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
HalI2SPageRecvRtl8195a(Data);
|
||||
#else
|
||||
HalI2SPageRecvRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalI2SClearAllOwnBit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
HalI2SClearAllOwnBitRtl8195a(Data);
|
||||
#else
|
||||
HalI2SClearAllOwnBitRtl8195a_V04(Data);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* _RTL8195A_I2S_H_ */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,675 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#ifndef _RTL8195A_MII_H_
|
||||
#define _RTL8195A_MII_H_
|
||||
|
||||
#include "basic_types.h"
|
||||
#include "hal_api.h"
|
||||
|
||||
|
||||
|
||||
#define MII_TX_DESC_NO 8
|
||||
#define MII_RX_DESC_NO 8
|
||||
#define MII_BUF_SIZE 1536
|
||||
#define MAX_FRAME_SIZE 1514
|
||||
|
||||
|
||||
#define HAL_MII_READ32(addr) HAL_READ32(MII_REG_BASE, addr)
|
||||
#define HAL_MII_WRITE32(addr, value) HAL_WRITE32(MII_REG_BASE, addr, value)
|
||||
#define HAL_MII_READ16(addr) HAL_READ16(MII_REG_BASE, addr)
|
||||
#define HAL_MII_WRITE16(addr, value) HAL_WRITE16(MII_REG_BASE, addr, value)
|
||||
#define HAL_MII_READ8(addr) HAL_READ8(MII_REG_BASE, addr)
|
||||
#define HAL_MII_WRITE8(addr, value) HAL_WRITE8(MII_REG_BASE, addr, value)
|
||||
|
||||
/* =============== MAC Register Offset Definition =============== */
|
||||
#define REG_MII_IDR0 0x0000
|
||||
#define REG_MII_IDR4 0x0004
|
||||
#define REG_MII_COM 0x0038
|
||||
#define REG_MII_ISRIMR 0x003C
|
||||
#define REG_MII_TC 0x0040
|
||||
#define REG_MII_RC 0x0044
|
||||
#define REG_MII_MS 0x0058
|
||||
#define REG_MII_MIIA 0x005C
|
||||
|
||||
#define REG_MII_TXFDP1 0x1300
|
||||
#define REG_MII_RXFDP1 0x13F0
|
||||
#define REG_MII_ETNRXCPU1 0x1430
|
||||
#define REG_MII_IOCMD 0x1434
|
||||
#define REG_MII_IOCMD1 0x1438
|
||||
|
||||
/* =============== MAC Register BIT Definition =============== */
|
||||
/* Command Register (0x38) */
|
||||
#define COM_RST BIT0
|
||||
#define COM_RXCHKSUM BIT1
|
||||
#define COM_RXJUMBO BIT3
|
||||
|
||||
/* Interrupt Status & Interrupt Mask Register (0x3C & 0x3E) */
|
||||
#define ISR_RXOK BIT0
|
||||
#define ISR_RER_RUNT BIT2
|
||||
#define ISR_RER_OVF BIT4
|
||||
#define ISR_RDU BIT5
|
||||
#define ISR_TXOK BIT6
|
||||
#define ISR_TER BIT7
|
||||
#define ISR_LINKCHG BIT8
|
||||
#define ISR_TDU BIT9
|
||||
#define ISR_CLR_ALL 0x0000FFFF
|
||||
#define IMR_RXOK BIT16
|
||||
#define IMR_RER_RUNT BIT18
|
||||
#define IMR_RER_OVF BIT20
|
||||
#define IMR_RDU BIT21
|
||||
#define IMR_TXOK BIT22
|
||||
#define IMR_TER BIT23
|
||||
#define IMR_LINKCHG BIT24
|
||||
#define IMR_TDU BIT25
|
||||
|
||||
/* Transmit Configuration Register (0x40) */
|
||||
#define TC_TX_NOPADDING BIT0
|
||||
#define TC_NORMAL_MODE 0
|
||||
#define TC_LBK_R2T 1
|
||||
#define TC_LBK_T2R 3
|
||||
#define TC_LBK_MASK 0x00000300 // bit[9:8]
|
||||
#define TC_IFG_TIME 3 // 9.6 us for 10Mbps, 960 ns for 100Mbps
|
||||
#define TC_IFG_MASK 0x00001C00 // bit[12:10]
|
||||
|
||||
/* Receive Configuration Register (0x44) */
|
||||
#define RC_AAP BIT0
|
||||
#define RC_APM BIT1
|
||||
#define RC_AM BIT2
|
||||
#define RC_AB BIT3
|
||||
#define RC_AR BIT4
|
||||
#define RC_AER BIT5
|
||||
|
||||
/* Media Status Register (0x58) */
|
||||
#define MS_LINKB BIT26
|
||||
|
||||
/* MII Access Register (0x5C) */
|
||||
#define MIIA_FLAG BIT31 // 1: Write, 0: Read
|
||||
#define MIIA_PHY_ADDR_MASK 0x7C000000 // bit[30:26]
|
||||
#define MIIA_PHY_REG_ADDR_MASK 0x001F0000 // bit[20:16]
|
||||
|
||||
/* IO Command Register (0x1434) */
|
||||
#define IOCMD_TXFN1ST BIT0
|
||||
#define IOCMD_TE BIT4
|
||||
#define IOCMD_RE BIT5
|
||||
#define IOCMD_RXFTH_1024 0
|
||||
#define IOCMD_RXFTH_128 1
|
||||
#define IOCMD_RXFTH_256 2
|
||||
#define IOCMD_RXFTH_512 3
|
||||
#define IOCMD_RXFTH_MASK 0x00001800 // bit[12:11]
|
||||
#define IOCMD_TXFTH_128 0
|
||||
#define IOCMD_TXFTH_256 1
|
||||
#define IOCMD_TXFTH_512 2
|
||||
#define IOCMD_TXFTH_1024 3
|
||||
#define IOCMD_TXFTH_MASK 0x00180000 // bit[20:19]
|
||||
#define IOCMD_SHORT_DES_FMT BIT30
|
||||
|
||||
/* IO Command1 Register (0x1438) */
|
||||
#define IOCMD1_RXRING1 BIT16
|
||||
#define IOCMD1_EN_1GB BIT24
|
||||
#define IOCMD1_DSC_FMT_EXTRA 0x3 // 011
|
||||
#define IOCMD1_DSCFMTEXTRA_MASK 0x70000000 // bit[30:28]
|
||||
|
||||
/* =============== PHY (RTL8201F) Register Bit Definition =============== */
|
||||
#define PHY_ADDRESS 0x1 // 5 bits
|
||||
#define PHY_REG0_ADDR 0x0 // 5 bits
|
||||
#define PHY_REG1_ADDR 0x1 // 5 bits
|
||||
|
||||
/* Register 0 */
|
||||
#define PHY_SPEED_MSB BIT6
|
||||
#define PHY_DUPLEX_MODE BIT8
|
||||
#define PHY_RESTART_NWAY BIT9
|
||||
#define PHY_NWAY_EN BIT12
|
||||
#define PHY_SPEED_LSB BIT13
|
||||
#define PHY_SW_RESET BIT15
|
||||
|
||||
/* Register 1 */
|
||||
#define PHY_LINK_STATUS BIT2
|
||||
#define PHY_NWAY_COMPLETE BIT5
|
||||
|
||||
/* =============== Tx/Rx Descriptor Bit Definition =============== */
|
||||
#define TX_DESC_OWN BIT31
|
||||
#define TX_DESC_EOR BIT30
|
||||
#define TX_DESC_FS BIT29
|
||||
#define TX_DESC_LS BIT28
|
||||
#define TX_DESC_CRC BIT23
|
||||
#define TX_DESC_DATA_LEN_MASK 0x1FFFF // bit[16:0]
|
||||
#define TX_DESC_VLAN_INTACT 0
|
||||
#define TX_DESC_VLAN_INSERT 1
|
||||
#define TX_DESC_VLAN_REMOVE 2
|
||||
#define TX_DESC_VLAN_REMARKING 3
|
||||
#define TX_DESC_VLAN_ACT_MASK 0x06000000
|
||||
#define C_VLAN_HDR 0x8100279F
|
||||
#define S_VLAN_HDR 0x88A8279F
|
||||
#define TX_DESC_VLAN_TAG_MASK 0x0000FFFF
|
||||
|
||||
#define RX_DESC_OWN BIT31
|
||||
#define RX_DESC_EOR BIT30
|
||||
#define RX_DESC_PKT_TYPE_MASK 0x001E0000 // bit[20:17]
|
||||
#define RX_DESC_DATA_LEN_MASK 0xFFF // bit[11:0]
|
||||
|
||||
|
||||
typedef struct _TX_DESC_FMT_
|
||||
{
|
||||
u32 dw1; // offset 0
|
||||
u32 addr; // offset 4
|
||||
u32 dw2; // offset 8
|
||||
u32 dw3; // offset 12
|
||||
u32 dw4; // offset 16
|
||||
}TX_DESC_FMT, *PTX_DESC_FMT;
|
||||
|
||||
typedef struct _RX_DESC_FMT_
|
||||
{
|
||||
u32 dw1; // offset 0
|
||||
u32 addr; // offset 4
|
||||
u32 dw2; // offset 8
|
||||
u32 dw3; // offset 12
|
||||
}RX_DESC_FMT, *PRX_DESC_FMT;
|
||||
|
||||
|
||||
|
||||
VOID
|
||||
HalMiiInitIrqRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
s32
|
||||
HalMiiInitRtl8195a(
|
||||
IN VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiDeInitRtl8195a(
|
||||
IN VOID
|
||||
);
|
||||
|
||||
s32
|
||||
HalMiiWriteDataRtl8195a(
|
||||
IN const char *Data,
|
||||
IN u32 Size
|
||||
);
|
||||
|
||||
u32
|
||||
HalMiiSendPacketRtl8195a(
|
||||
IN VOID
|
||||
);
|
||||
|
||||
u32
|
||||
HalMiiReceivePacketRtl8195a(
|
||||
IN VOID
|
||||
);
|
||||
|
||||
u32
|
||||
HalMiiReadDataRtl8195a(
|
||||
IN u8 *Data,
|
||||
IN u32 Size
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiGetMacAddressRtl8195a(
|
||||
IN u8 *Addr
|
||||
);
|
||||
|
||||
u32
|
||||
HalMiiGetLinkStatusRtl8195a(
|
||||
IN VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiForceLinkRtl8195a(
|
||||
IN s32 Speed,
|
||||
IN s32 Duplex
|
||||
);
|
||||
|
||||
|
||||
|
||||
#ifdef CONFIG_MII_VERIFY
|
||||
|
||||
/* Ethernet Module registers */
|
||||
#define REG_RTL_MII_IDR0 0x0000 // Table 2 IDR0 (Offset 0000h-0003h, R/W)
|
||||
#define REG_RTL_MII_IDR4 0x0004 // Table 3 IDR4 (Offset 0004h-0007h, R/W)
|
||||
#define REG_RTL_MII_MAR0 0x0008 // Table 4 MAR0 (Offset 0008h-000bh, R/W)
|
||||
#define REG_RTL_MII_MAR4 0x000C // Table 5 MAR4 (Offset 000ch-000fh, R/W)
|
||||
#define REG_RTL_MII_CR 0x0038 // Table 21 Command Register (COM_REG, Offset 0038-003Bh, R/W)
|
||||
#define REG_RTL_MII_IMRISR 0x003C // Table 22 + Table 23
|
||||
#define REG_RTL_MII_TCR 0x0040 // Table 24 Transmit Configuration Register (TC_REG, Offset 0040h-0043h, R/W)
|
||||
#define REG_RTL_MII_RCR 0x0044 // Table 25 Receive Configuration Register (RC_REG, Offset 0044h-0047h, R/W)
|
||||
#define REG_RTL_MII_CTCR 0x0048 // Table 26 CPU Tag Control Register (CPUTAG_REG, Offset 0048h-004bh, R/W)
|
||||
#define REG_RTL_MII_CONFIG 0x004C // Table 27 Configuration Register (CONFIG_REG, Offset 004ch-004fh, R/W)
|
||||
#define REG_RTL_MII_CTCR1 0x0050 // Table 28 CPUTAG1 Register (CPUTAG1_REG, Offset 0050h-0053h, R/W)
|
||||
#define REG_RTL_MII_MSR 0x0058 // Table 29 Media Status Register (MS_reg: Offset 0058h ??005bh, R/W)
|
||||
#define REG_RTL_MII_MIIAR 0x005C // Table 30 MII Access Register (MIIA_REG, Offset 005c-005fh, R/W)
|
||||
#define REG_RTL_MII_VR 0x0064 // Table 32 VLAN Register (VLAN_REG, Offset 0064-0067h, R/W)
|
||||
#define REG_RTL_MII_IMR0 0x00D0 // Table 50 IMR0_REG (IMR0_REG, Offset D0h-D3h)
|
||||
#define REG_RTL_MII_IMR1 0x00D4 // Table 51 IMR1_REG (IMR1_REG, Offset d4h-d7h)
|
||||
#define REG_RTL_MII_ISR1 0x00D8 // Table 52 ISR1 Register (ISR1_REG, Offset D8h-DBh)
|
||||
#define REG_RTL_MII_INTR 0x00DC // Table 53 Interrupt routing register (INTR_REG, Offset DCh-DFh)
|
||||
#define REG_RTL_MII_CCR 0x00E4 // Table xx Clock Control Register (CLKCTL_REG, Offset E4h-E7h)
|
||||
|
||||
/* CPU Interface registers */
|
||||
#define REG_RTL_MII_TXFDP1 0x1300 // Table 55 TxFDP1 register (TXFDP1_REG, offset 1300h-1303h)
|
||||
#define REG_RTL_MII_TXCDO1 0x1304 // Table 56 TxCDO1 register (TXCDO1_REG, offset 1304h-1305h)
|
||||
#define REG_RTL_MII_TXFDP2 0x1310 // Table 57 TxFDP2 register (TXFDP2_REG, offset 1310h-1313h)
|
||||
#define REG_RTL_MII_TXCDO2 0x1314 // Table 58 TxCDO2 register (TXCDO2_REG, offset 1314h-1315h)
|
||||
#define REG_RTL_MII_TXFDP3 0x1320 // Table 59 TxFDP3 register (TXFDP3_REG, offset 1320h-1323h)
|
||||
#define REG_RTL_MII_TXCDO3 0x1324 // Table 60 TxCDO3 register (TXCDO3_REG, offset 1324h-1325h)
|
||||
#define REG_RTL_MII_TXFDP4 0x1330 // Table 61 TxFDP4 register (TXFDP4_REG, offset 1330h-1333h)
|
||||
#define REG_RTL_MII_TXCDO4 0x1334 // Table 62 TxCDO4 register (TXCDO4_REG, offset 1334h-1335h)
|
||||
#define REG_RTL_MII_TXFDP5 0x1340 // Table 63 TxFDP5 register (TXFDP5_REG, offset 1340h-1343h)
|
||||
#define REG_RTL_MII_TXCDO5 0x1344 // Table 64 TxCDO5 register (TXCDO5_REG, offset 1344h-1345h)
|
||||
#define REG_RTL_MII_RXFDP2 0x1390 // Table 66 RxFDP2 register (RXFDP#_REG, offset 1390h-1393h)
|
||||
#define REG_RTL_MII_RXFDP1 0x13F0 // Table 71 RxFDP1 register (RXFDP1_REG, offset 13F0h-13F3h)
|
||||
#define REG_RTL_MII_RXRS1 0x13F6 // Table 73 Rx Ring Size1 register (RX_RS1_REG, offset 13F6h-13F7h)
|
||||
|
||||
#define REG_RTL_MII_RX_PSE1 0x142C // Table 77 Rx_Pse_Des_Thres_1_h (RX_PSE1_REG, Offset 142ch)
|
||||
#define REG_RTL_MII_ETNRXCPU1 0x1430 // Table 79 EhtrntRxCPU_Des_Num1 (ETNRXCPU1_REG, Offset 1430h-1433h)
|
||||
#define REG_RTL_MII_IOCMD 0x1434 // Table 80 Ethernet_IO_CMD (ETN_IO_CMD_REG, Offset 1434h-1437h)
|
||||
#define REG_RTL_MII_IOCMD1 0x1438 // Table 81 Ethernet_IO_CMD1 (IO_CMD1_REG: Offset 1438h-143bh)
|
||||
|
||||
|
||||
#define CMD_CONFIG 0x00081000
|
||||
|
||||
//2014-04-29 yclin (disable [27] r_en_precise_dma)
|
||||
// #define CMD1_CONFIG 0x39000000
|
||||
#define CMD1_CONFIG 0x31000000
|
||||
|
||||
// #define MAX_RX_DESC_SIZE 6
|
||||
#define MAX_RX_DESC_SIZE 1
|
||||
#define MAX_TX_DESC_SIZE 5
|
||||
|
||||
// 0058h
|
||||
#define BIT_SHIFT_MSR_FORCE_SPEED_SELECT 16
|
||||
#define BIT_MASK_MSR_FORCE_SPEED_SELECT 0x3
|
||||
#define BIT_MSR_FORCE_SPEED_SELECT(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_SELECT) << BIT_SHIFT_MSR_FORCE_SPEED_SELECT)
|
||||
#define BIT_INVC_MSR_FORCE_SPEED_SELECT (~(BIT_MASK_MSR_FORCE_SPEED_SELECT << BIT_SHIFT_MSR_FORCE_SPEED_SELECT))
|
||||
|
||||
#define BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE 10
|
||||
#define BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE 0x1
|
||||
#define BIT_MSR_FORCE_SPEED_MODE_ENABLE(x)(((x) & BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE) << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE)
|
||||
#define BIT_INVC_MSR_FORCE_SPEED_MODE_ENABLE (~(BIT_MASK_MSR_FORCE_SPEED_MODE_ENABLE << BIT_SHIFT_MSR_FORCE_SPEED_MODE_ENABLE))
|
||||
|
||||
// 1434h
|
||||
#define BIT_SHIFT_IOCMD_RXENABLE 5
|
||||
#define BIT_MASK_IOCMD_RXENABLE 0x1
|
||||
#define BIT_IOCMD_RXENABLE(x)(((x) & BIT_MASK_IOCMD_RXENABLE) << BIT_SHIFT_IOCMD_RXENABLE)
|
||||
#define BIT_INVC_IOCMD_RXENABLE (~(BIT_MASK_IOCMD_RXENABLE << BIT_SHIFT_IOCMD_RXENABLE))
|
||||
|
||||
#define BIT_SHIFT_IOCMD_TXENABLE 4
|
||||
#define BIT_MASK_IOCMD_TXENABLE 0x1
|
||||
#define BIT_IOCMD_TXENABLE(x)(((x) & BIT_MASK_IOCMD_TXENABLE) << BIT_SHIFT_IOCMD_TXENABLE)
|
||||
#define BIT_INVC_IOCMD_TXENABLE (~(BIT_MASK_IOCMD_TXENABLE << BIT_SHIFT_IOCMD_TXENABLE))
|
||||
|
||||
#define BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE 0
|
||||
#define BIT_MASK_IOCMD_FIRST_DMATX_ENABLE 0x1
|
||||
#define BIT_IOCMD_FIRST_DMATX_ENABLE(x)(((x) & BIT_MASK_IOCMD_FIRST_DMATX_ENABLE) << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE)
|
||||
#define BIT_INVC_IOCMD_FIRST_DMATX_ENABLE (~(BIT_MASK_IOCMD_FIRST_DMATX_ENABLE << BIT_SHIFT_IOCMD_FIRST_DMATX_ENABLE))
|
||||
|
||||
// 1438h
|
||||
#define BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE 16
|
||||
#define BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE 0x1
|
||||
#define BIT_IOCMD1_FIRST_DMARX_ENABLE(x)(((x) & BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE) << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE)
|
||||
#define BIT_INVC_IOCMD1_FIRST_DMARX_ENABLE (~(BIT_MASK_IOCMD1_FIRST_DMARX_ENABLE << BIT_SHIFT_IOCMD1_FIRST_DMARX_ENABLE))
|
||||
|
||||
|
||||
/**
|
||||
* 1.4.1.7 Tx command descriptor used in RL6266
|
||||
* 5 dobule words
|
||||
*/
|
||||
typedef struct _TX_INFO_ {
|
||||
union {
|
||||
struct {
|
||||
u32 own:1; //31
|
||||
u32 eor:1; //30
|
||||
u32 fs:1; //29
|
||||
u32 ls:1; //28
|
||||
u32 ipcs:1; //27
|
||||
u32 l4cs:1; //26
|
||||
u32 keep:1; //25
|
||||
u32 blu:1; //24
|
||||
u32 crc:1; //23
|
||||
u32 vsel:1; //22
|
||||
u32 dislrn:1; //21
|
||||
u32 cputag_ipcs:1; //20
|
||||
u32 cputag_l4cs:1; //19
|
||||
u32 cputag_psel:1; //18
|
||||
u32 rsvd:1; //17
|
||||
u32 data_length:17; //0~16
|
||||
} bit;
|
||||
u32 dw; //double word
|
||||
} opts1;
|
||||
|
||||
u32 addr;
|
||||
|
||||
union {
|
||||
struct {
|
||||
u32 cputag:1; //31
|
||||
u32 aspri:1; //30
|
||||
u32 cputag_pri:3; //27~29
|
||||
u32 tx_vlan_action:2; //25~26
|
||||
u32 tx_pppoe_action:2; //23~24
|
||||
u32 tx_pppoe_idx:3; //20~22
|
||||
u32 efid:1; //19
|
||||
u32 enhance_fid:3; //16~18
|
||||
u32 vidl:8; // 8~15
|
||||
u32 prio:3; // 5~7
|
||||
u32 cfi:1; // 4
|
||||
u32 vidh:4; // 0~3
|
||||
} bit;
|
||||
u32 dw; //double word
|
||||
} opts2;
|
||||
|
||||
union {
|
||||
struct {
|
||||
u32 extspa:3; //29~31
|
||||
u32 tx_portmask:6; //23~28
|
||||
u32 tx_dst_stream_id:7; //16~22
|
||||
u32 rsvd:14; // 2~15
|
||||
u32 l34keep:1; // 1
|
||||
u32 ptp:1; // 0
|
||||
} bit;
|
||||
u32 dw; //double word
|
||||
} opts3;
|
||||
|
||||
union {
|
||||
struct {
|
||||
u32 lgsen:1; //31
|
||||
u32 lgmss:11; //20~30
|
||||
u32 rsvd:20; // 0~19
|
||||
} bit;
|
||||
u32 dw; //double word
|
||||
} opts4;
|
||||
|
||||
} TX_INFO, *PTX_INFO;
|
||||
|
||||
typedef struct _RX_INFO_ {
|
||||
union{
|
||||
struct{
|
||||
u32 own:1; //31
|
||||
u32 eor:1; //30
|
||||
u32 fs:1; //29
|
||||
u32 ls:1; //28
|
||||
u32 crcerr:1; //27
|
||||
u32 ipv4csf:1; //26
|
||||
u32 l4csf:1; //25
|
||||
u32 rcdf:1; //24
|
||||
u32 ipfrag:1; //23
|
||||
u32 pppoetag:1; //22
|
||||
u32 rwt:1; //21
|
||||
u32 pkttype:4; //20-17
|
||||
u32 l3routing:1; //16
|
||||
u32 origformat:1; //15
|
||||
u32 pctrl:1; //14
|
||||
#ifdef CONFIG_RG_JUMBO_FRAME
|
||||
u32 data_length:14; //13~0
|
||||
#else
|
||||
u32 rsvd:2; //13~12
|
||||
u32 data_length:12; //11~0
|
||||
#endif
|
||||
}bit;
|
||||
u32 dw; //double word
|
||||
}opts1;
|
||||
|
||||
u32 addr;
|
||||
|
||||
union{
|
||||
struct{
|
||||
u32 cputag:1; //31
|
||||
u32 ptp_in_cpu_tag_exist:1; //30
|
||||
u32 svlan_tag_exist:1; //29
|
||||
u32 rsvd_2:2; //27~28
|
||||
u32 pon_stream_id:7; //20~26
|
||||
u32 rsvd_1:3; //17~19
|
||||
u32 ctagva:1; //16
|
||||
u32 cvlan_tag:16; //15~0
|
||||
}bit;
|
||||
u32 dw; //double word
|
||||
}opts2;
|
||||
|
||||
union{
|
||||
struct{
|
||||
u32 src_port_num:5; //27~31
|
||||
u32 dst_port_mask:6; //21~26
|
||||
u32 reason:8; //13~20
|
||||
u32 internal_priority:3; //10~12
|
||||
u32 ext_port_ttl_1:5; //5~9
|
||||
u32 rsvd:5; //4~0
|
||||
}bit;
|
||||
u32 dw; //double word
|
||||
}opts3;
|
||||
} RX_INFO, *PRX_INFO;
|
||||
|
||||
/**
|
||||
* GMAC_STATUS_REGS
|
||||
*/
|
||||
// TX/RX Descriptor Common
|
||||
#define BIT_SHIFT_GMAC_DESCOWN 31
|
||||
#define BIT_MASK_GMAC_DESCOWN 0x1
|
||||
#define BIT_GMAC_DESCOWN(x)(((x) & BIT_MASK_GMAC_DESCOWN) << BIT_SHIFT_GMAC_DESCOWN)
|
||||
#define BIT_INVC_GMAC_DESCOWN (~(BIT_MASK_GMAC_DESCOWN << BIT_SHIFT_GMAC_DESCOWN))
|
||||
|
||||
#define BIT_SHIFT_GMAC_RINGEND 30
|
||||
#define BIT_MASK_GMAC_RINGEND 0x1
|
||||
#define BIT_GMAC_RINGEND(x)(((x) & BIT_MASK_GMAC_RINGEND) << BIT_SHIFT_GMAC_RINGEND)
|
||||
#define BIT_INVC_GMAC_RINGEND (~(BIT_MASK_GMAC_RINGEND << BIT_SHIFT_GMAC_RINGEND))
|
||||
|
||||
#define BIT_SHIFT_GMAC_FIRSTFRAG 29
|
||||
#define BIT_MASK_GMAC_FIRSTFRAG 0x1
|
||||
#define BIT_GMAC_FIRSTFRAG(x)(((x) & BIT_MASK_GMAC_FIRSTFRAG) << BIT_SHIFT_GMAC_FIRSTFRAG)
|
||||
#define BIT_INVC_GMAC_FIRSTFRAG (~(BIT_MASK_GMAC_FIRSTFRAG << BIT_SHIFT_GMAC_FIRSTFRAG))
|
||||
|
||||
#define BIT_SHIFT_GMAC_LASTFRAG 28
|
||||
#define BIT_MASK_GMAC_LASTFRAG 0x1
|
||||
#define BIT_GMAC_LASTFRAG(x)(((x) & BIT_MASK_GMAC_LASTFRAG) << BIT_SHIFT_GMAC_LASTFRAG)
|
||||
#define BIT_INVC_GMAC_LASTFRAG (~(BIT_MASK_GMAC_LASTFRAG << BIT_SHIFT_GMAC_LASTFRAG))
|
||||
|
||||
// TX Descriptor opts1
|
||||
#define BIT_SHIFT_GMAC_IPCS 27
|
||||
#define BIT_MASK_GMAC_IPCS 0x1
|
||||
#define BIT_GMAC_IPCS(x)(((x) & BIT_MASK_GMAC_IPCS) << BIT_SHIFT_GMAC_IPCS)
|
||||
#define BIT_INVC_GMAC_IPCS (~(BIT_MASK_GMAC_IPCS << BIT_SHIFT_GMAC_IPCS))
|
||||
|
||||
#define BIT_SHIFT_GMAC_L4CS 26
|
||||
#define BIT_MASK_GMAC_L4CS 0x1
|
||||
#define BIT_GMAC_L4CS(x)(((x) & BIT_MASK_GMAC_L4CS) << BIT_SHIFT_GMAC_L4CS)
|
||||
#define BIT_INVC_GMAC_L4CS (~(BIT_MASK_GMAC_L4CS << BIT_SHIFT_GMAC_L4CS))
|
||||
|
||||
#define BIT_SHIFT_GMAC_KEEP 25
|
||||
#define BIT_MASK_GMAC_KEEP 0x1
|
||||
#define BIT_GMAC_KEEP(x)(((x) & BIT_MASK_GMAC_KEEP) << BIT_SHIFT_GMAC_KEEP)
|
||||
#define BIT_INVC_GMAC_KEEP (~(BIT_MASK_GMAC_KEEP << BIT_SHIFT_GMAC_KEEP))
|
||||
|
||||
#define BIT_SHIFT_GMAC_BLU 24
|
||||
#define BIT_MASK_GMAC_BLU 0x1
|
||||
#define BIT_GMAC_BLU(x)(((x) & BIT_MASK_GMAC_BLU) << BIT_SHIFT_GMAC_BLU)
|
||||
#define BIT_INVC_GMAC_BLU (~(BIT_MASK_GMAC_BLU << BIT_SHIFT_GMAC_BLU))
|
||||
|
||||
#define BIT_SHIFT_GMAC_TXCRC 23
|
||||
#define BIT_MASK_GMAC_TXCRC 0x1
|
||||
#define BIT_GMAC_TXCRC(x)(((x) & BIT_MASK_GMAC_TXCRC) << BIT_SHIFT_GMAC_TXCRC)
|
||||
#define BIT_INVC_GMAC_TXCRC (~(BIT_MASK_GMAC_TXCRC << BIT_SHIFT_GMAC_TXCRC))
|
||||
|
||||
#define BIT_SHIFT_GMAC_VSEL 22
|
||||
#define BIT_MASK_GMAC_VSEL 0x1
|
||||
#define BIT_GMAC_VSEL(x)(((x) & BIT_MASK_GMAC_VSEL) << BIT_SHIFT_GMAC_VSEL)
|
||||
#define BIT_INVC_GMAC_VSEL (~(BIT_MASK_GMAC_VSEL << BIT_SHIFT_GMAC_VSEL))
|
||||
|
||||
#define BIT_SHIFT_GMAC_DISLRN 21
|
||||
#define BIT_MASK_GMAC_DISLRN 0x1
|
||||
#define BIT_GMAC_DISLRN(x)(((x) & BIT_MASK_GMAC_DISLRN) << BIT_SHIFT_GMAC_DISLRN)
|
||||
#define BIT_INVC_GMAC_DISLRN (~(BIT_MASK_GMAC_DISLRN << BIT_SHIFT_GMAC_DISLRN))
|
||||
|
||||
#define BIT_SHIFT_GMAC_CPUTAG_IPCS 20
|
||||
#define BIT_MASK_GMAC_CPUTAG_IPCS 0x1
|
||||
#define BIT_GMAC_CPUTAG_IPCS(x)(((x) & BIT_MASK_GMAC_CPUTAG_IPCS) << BIT_SHIFT_GMAC_CPUTAG_IPCS)
|
||||
#define BIT_INVC_GMAC_CPUTAG_IPCS (~(BIT_MASK_GMAC_CPUTAG_IPCS << BIT_SHIFT_GMAC_CPUTAG_IPCS))
|
||||
|
||||
#define BIT_SHIFT_GMAC_CPUTAG_L4CS 19
|
||||
#define BIT_MASK_GMAC_CPUTAG_L4CS 0x1
|
||||
#define BIT_GMAC_CPUTAG_L4CS(x)(((x) & BIT_MASK_GMAC_CPUTAG_L4CS) << BIT_SHIFT_GMAC_CPUTAG_L4CS)
|
||||
#define BIT_INVC_GMAC_CPUTAG_L4CS (~(BIT_MASK_GMAC_CPUTAG_L4CS << BIT_SHIFT_GMAC_CPUTAG_L4CS))
|
||||
|
||||
#define BIT_SHIFT_GMAC_CPUTAG_PSEL 18
|
||||
#define BIT_MASK_GMAC_CPUTAG_PSEL 0x1
|
||||
#define BIT_GMAC_CPUTAG_PSEL(x)(((x) & BIT_MASK_GMAC_CPUTAG_PSEL) << BIT_SHIFT_GMAC_CPUTAG_PSEL)
|
||||
#define BIT_INVC_GMAC_CPUTAG_PSEL (~(BIT_MASK_GMAC_CPUTAG_PSEL << BIT_SHIFT_GMAC_CPUTAG_PSEL))
|
||||
|
||||
|
||||
typedef struct _PHY_MODE_INFO_ {
|
||||
u8 PhyAddress;
|
||||
u8 PhyMode;
|
||||
u8 PhyInterface;
|
||||
} PHY_MODE_INFO, *PPHY_MODE_INFO;
|
||||
|
||||
typedef enum _PHY_MODE_SWITCH_ {
|
||||
PHY_MODE_DISABLE = 0,
|
||||
PHY_MODE_ENABLE = 1
|
||||
} PHY_MODE_SWITCH, *PPHY_MODE_SWITCH;
|
||||
|
||||
typedef enum _PHY_INTERFACE_SELECT_ {
|
||||
PHY_INTERFACE_ONE_WORKS = 0,
|
||||
PHY_INTERFACE_ZERO_WORKS = 1
|
||||
} PHY_INTERFACE_SELECT, *PPHY_INTERFACE_SELECT;
|
||||
|
||||
typedef enum _GMAC_MSR_FORCE_SPEED_ {
|
||||
FORCE_SPD_100M = 0,
|
||||
FORCE_SPD_10M = 1,
|
||||
FORCE_SPD_GIGA = 2,
|
||||
NO_FORCE_SPD = 3
|
||||
}GMAC_MSR_FORCE_SPEED, *PGMAC_MSR_FORCE_SPEED;
|
||||
|
||||
typedef enum _GMAC_INTERRUPT_MASK_ {
|
||||
GMAC_IMR_ROK = BIT16,
|
||||
GMAC_IMR_CNT_WRAP = BIT17,
|
||||
GMAC_IMR_RER_RUNT = BIT18,
|
||||
// BIT19 Reserved
|
||||
GMAC_IMR_RER_OVF = BIT20,
|
||||
GMAC_IMR_RDU = BIT21,
|
||||
GMAC_IMR_TOK_TI = BIT22,
|
||||
GMAC_IMR_TER = BIT23,
|
||||
GMAC_IMR_LINKCHG = BIT24,
|
||||
GMAC_IMR_TDU = BIT25,
|
||||
GMAC_IMR_SWINT = BIT26,
|
||||
GMAC_IMR_RDU2 = BIT27,
|
||||
GMAC_IMR_RDU3 = BIT28,
|
||||
GMAC_IMR_RDU4 = BIT29,
|
||||
GMAC_IMR_RDU5 = BIT30,
|
||||
GMAC_IMR_RDU6 = BIT31,
|
||||
} GMAC_INTERRUPT_MASK, *PGMAC_INTERRUPT_MASK;
|
||||
|
||||
typedef enum _GMAC_INTERRUPT_STATUS_ {
|
||||
GMAC_ISR_ROK = BIT0,
|
||||
GMAC_ISR_CNT_WRAP = BIT1,
|
||||
GMAC_ISR_RER_RUNT = BIT2,
|
||||
// BIT3 Reserved
|
||||
GMAC_ISR_RER_OVF = BIT4,
|
||||
GMAC_ISR_RDU = BIT5,
|
||||
GMAC_ISR_TOK_TI = BIT6,
|
||||
GMAC_ISR_TER = BIT7,
|
||||
GMAC_ISR_LINKCHG = BIT8,
|
||||
GMAC_ISR_TDU = BIT9,
|
||||
GMAC_ISR_SWINT = BIT10,
|
||||
GMAC_ISR_RDU2 = BIT11,
|
||||
GMAC_ISR_RDU3 = BIT12,
|
||||
GMAC_ISR_RDU4 = BIT13,
|
||||
GMAC_ISR_RDU5 = BIT14,
|
||||
GMAC_ISR_RDU6 = BIT15,
|
||||
} GMAC_INTERRUPT_STATUS, *PGMAC_INTERRUPT_STATUS;
|
||||
|
||||
typedef enum _GMAC_TX_VLAN_ACTION_ {
|
||||
INTACT = 0,
|
||||
INSERT_VLAN_HDR = 1,
|
||||
REMOVE_VLAN_HDR = 2,
|
||||
REMARKING_VID = 3
|
||||
}GMAC_TX_VLAN_ACTION, *PGMAC_TX_VLAN_ACTION;
|
||||
|
||||
typedef enum _GMAC_RX_PACKET_TYPE_ {
|
||||
TYPE_ETHERNET = 0,
|
||||
TYPE_IPV4 = 1,
|
||||
TYPE_IPV4_PPTP = 2,
|
||||
TYPE_IPV4_ICMP = 3,
|
||||
TYPE_IPV4_IGMP = 4,
|
||||
TYPE_IPV4_TCP = 5,
|
||||
TYPE_IPV4_UDP = 6,
|
||||
TYPE_IPV6 = 7,
|
||||
TYPE_ICMPV6 = 8,
|
||||
TYPE_IPV6_TCP = 9,
|
||||
TYPE_IPV6_UDP = 10
|
||||
}GMAC_RX_PACKET_TYPE, *PGMAC_RX_PACKET_TYPE;
|
||||
|
||||
|
||||
|
||||
BOOL
|
||||
HalMiiGmacInitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalMiiGmacResetRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalMiiGmacEnablePhyModeRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u32
|
||||
HalMiiGmacXmitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiGmacCleanTxRingRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiGmacFillTxInfoRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiGmacFillRxInfoRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiGmacTxRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiGmacRxRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiGmacSetDefaultEthIoCmdRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiGmacInitIrqRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u32
|
||||
HalMiiGmacGetInterruptStatusRtl8195a(
|
||||
VOID
|
||||
);
|
||||
|
||||
VOID
|
||||
HalMiiGmacClearInterruptStatusRtl8195a(
|
||||
u32 IsrStatus
|
||||
);
|
||||
#endif // #ifdef CONFIG_MII_VERIFY
|
||||
|
||||
#endif // #ifndef _RTL8195A_MII_H_
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,155 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RTL8195A_NFC_H_
|
||||
#define _RTL8195A_NFC_H_
|
||||
|
||||
#include "hal_api.h"
|
||||
//#include "osdep_api.h"
|
||||
#ifdef CONFIG_NFC_VERIFY
|
||||
#include "../test/nfc/rtl8195a_nfc_test.h"
|
||||
#endif
|
||||
|
||||
#if CONFIG_NFC_NORMAL
|
||||
//===================== Register Bit Field Definition =====================
|
||||
// TODO:
|
||||
//===================== Register Address Definition =====================
|
||||
//TODO:
|
||||
//#include "osdep_api.h"
|
||||
#define N2A_Q_LENGTH 10
|
||||
#define N2ARLENGTH 4
|
||||
//#define NFCTAGLENGTH 36 // maximum 36*4=144 bytes
|
||||
#define NFCTAG_BASE 0x7F000
|
||||
#define NFCTAG_PAGESIZE 256
|
||||
#define NFCTAG_MAXPAGEIDX 16//(4*(1024/NFCTAG_PAGESIZE))
|
||||
#define A2NWCLENGTH 4
|
||||
|
||||
#define FLASHAPPLENGTH 31
|
||||
#define FLASHAPP_BASE 0x7E000
|
||||
#define FLASH_PAGESIZE 128
|
||||
#define FLASH_MAXPAGEIDX 32//(4*(1024/FLASH_PAGESIZE))
|
||||
|
||||
typedef struct _A2N_CATCH_W_ {
|
||||
//u8 Vaild;
|
||||
u8 A2NCatchRPage;
|
||||
u32 A2NCatchWData[A2NWCLENGTH];
|
||||
}A2N_CATCH_W_QUEUE, *PA2N_CATCH_W_QUEUE;
|
||||
|
||||
typedef struct _A2N_MAILBOX_Q_ {
|
||||
u8 Length;
|
||||
u8 Response;
|
||||
u32 Content[A2NWCLENGTH+1];
|
||||
}A2N_MAILBOX_Q,*PA2N_MAILBOX_Q;
|
||||
|
||||
typedef struct _N2A_CATCH_R_ {
|
||||
u8 Vaild;
|
||||
u8 N2ACatchRPage;
|
||||
u32 N2ACatchRData[N2ARLENGTH];
|
||||
}N2A_CATCH_R_QUEUE, *PN2A_CATCH_R_QUEUE;
|
||||
|
||||
|
||||
typedef struct _N2A_R_ {
|
||||
u8 Vaild;
|
||||
u8 N2ARPage;
|
||||
}N2A_R_QUEUE, *PN2A_R_QUEUE;
|
||||
|
||||
typedef struct _N2A_W_ {
|
||||
u8 Vaild;
|
||||
u8 N2AWPage;
|
||||
u32 N2AWData;
|
||||
}N2A_W_QUEUE, *PN2A_W_QUEUE;
|
||||
|
||||
typedef struct _NFC_ADAPTER_ {
|
||||
u8 Function;
|
||||
u32 NFCIsr;
|
||||
u8 N2ABoxOpen;
|
||||
u8 A2NSeq;
|
||||
//u8 NFCTagFlashWIdx;
|
||||
//u8 NFCTagFlashRIdx;
|
||||
// u32 NFCTag[NFCTAGLENGTH];
|
||||
#if !TASK_SCHEDULER_DISABLED
|
||||
void * VeriSema;
|
||||
#else
|
||||
u32 VeriSema;
|
||||
#endif
|
||||
#ifdef PLATFORM_FREERTOS
|
||||
void * NFCTask;
|
||||
#else
|
||||
u32 NFCTask;
|
||||
#endif
|
||||
#ifdef CONFIG_NFC_VERIFY
|
||||
//N2A Write Tag
|
||||
u8 N2AWQRIdx;
|
||||
u8 N2AWQWIdx;
|
||||
N2A_W_QUEUE N2AWQ[N2A_Q_LENGTH];
|
||||
//N2A Read Tag
|
||||
u8 N2ARQRIdx;
|
||||
u8 N2ARQWIdx;
|
||||
N2A_R_QUEUE N2ARQ[N2A_Q_LENGTH];
|
||||
//N2A Read Catch
|
||||
u8 N2ARCRIdx;
|
||||
u8 N2ARCWIdx;
|
||||
N2A_CATCH_R_QUEUE N2ACatchR[N2A_Q_LENGTH];
|
||||
#endif
|
||||
//A2N Write Catch
|
||||
//u8 A2NWCRIdx;
|
||||
//u8 A2NWCWIdx;
|
||||
//A2N_CATCH_W_QUEUE A2NCatchW[N2A_Q_LENGTH];
|
||||
|
||||
//A2N Write mailbox queue
|
||||
u8 A2NWMailBox;
|
||||
u8 A2NWQRIdx;
|
||||
u8 A2NWQWIdx;
|
||||
A2N_MAILBOX_Q A2NMAILQ[N2A_Q_LENGTH];
|
||||
|
||||
u8 TaskStop;
|
||||
void *nfc_obj;
|
||||
}NFC_ADAPTER, *PNFC_ADAPTER;
|
||||
|
||||
typedef enum _N2A_CMD_ {
|
||||
TAG_READ = 0,
|
||||
TAG_WRITE = 1,
|
||||
CATCH_READ_DATA = 2,
|
||||
NFC_R_PRESENT = 4,
|
||||
N2A_MAILBOX_STATE = 5,
|
||||
EXT_CLK_REQ = 6,
|
||||
MAX_N2ACMD
|
||||
} N2A_CMD, *PN2A_CMD;
|
||||
|
||||
typedef enum _A2N_CMD_ {
|
||||
TAG_READ_DATA = 0,
|
||||
CATCH_READ = 2,
|
||||
CATCH_WRITE = 3,
|
||||
A2N_MAILBOX_STATE = 4,
|
||||
CONFIRM_N2A_BOX_STATE = 5,
|
||||
EXT_CLK_RSP = 6,
|
||||
MAX_A2NCMD
|
||||
} A2N_CMD, *PA2N_CMD;
|
||||
|
||||
// Callback event defination
|
||||
typedef enum _NFC_HAL_EVENT_ {
|
||||
NFC_HAL_READER_PRESENT = (1<<0),
|
||||
NFC_HAL_READ = (1<<1),
|
||||
NFC_HAL_WRITE = (1<<2),
|
||||
NFC_HAL_ERR = (1<<3),
|
||||
NFC_HAL_CACHE_RD = (1<<4)
|
||||
}NFC_CB_EVENT, *PNFC_CB_EVENT;
|
||||
|
||||
VOID A2NWriteCatch(IN VOID *pNFCAdapte, IN u8 N2AWPage,
|
||||
IN u8 Length, IN u32 *WData);
|
||||
VOID A2NReadCatch(IN VOID *pNFCAdapte, IN u8 A2NRPage);
|
||||
VOID HalNFCDmemInit(IN u32 *pTagData, IN u32 TagLen);
|
||||
VOID HalNFCInit(PNFC_ADAPTER pNFCAdp);
|
||||
VOID HalNFCDeinit(PNFC_ADAPTER pNFCAdp);
|
||||
VOID HalNFCFwDownload(VOID);
|
||||
u32 HalNFCDbgRead32(IN u32 Addr);
|
||||
VOID HalNFCDbgWrite32(IN u32 Addr, IN u32 Data);
|
||||
#endif //CONFIG_NFC_NORMAL
|
||||
#endif // #ifndef _RTL8195A_NFC_H_
|
||||
|
|
@ -0,0 +1,449 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RTL8195A_PCM_H_
|
||||
#define _RTL8195A_PCM_H_
|
||||
|
||||
#include "basic_types.h"
|
||||
#include "hal_api.h"
|
||||
|
||||
#define HAL_PCMX_READ32(PcmIndex, addr) \
|
||||
HAL_READ32(PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF), addr)
|
||||
#define HAL_PCMX_WRITE32(PcmIndex, addr, value) \
|
||||
HAL_WRITE32((PCM0_REG_BASE+ (PcmIndex*PCM1_REG_OFF)), addr, value)
|
||||
|
||||
#define REG_PCM_TRXBSA_OFF 0x004
|
||||
#define REG_PCM_CTL 0x000
|
||||
#define REG_PCM_CHCNR03 0x004
|
||||
#define REG_PCM_TSR03 0x008
|
||||
#define REG_PCM_BSIZE03 0x00C
|
||||
|
||||
#define REG_PCM_CH0TXBSA 0x010
|
||||
#define REG_PCM_CH1TXBSA 0x014
|
||||
#define REG_PCM_CH2TXBSA 0x018
|
||||
#define REG_PCM_CH3TXBSA 0x01c
|
||||
#define REG_PCM_CH0RXBSA 0x020
|
||||
#define REG_PCM_CH1RXBSA 0x024
|
||||
#define REG_PCM_CH2RXBSA 0x028
|
||||
#define REG_PCM_CH3RXBSA 0x02c
|
||||
|
||||
#define REG_PCM_IMR03 0x030
|
||||
#define REG_PCM_ISR03 0x034
|
||||
|
||||
#define REG_PCM_CHCNR47 0x038
|
||||
#define REG_PCM_TSR47 0x03c
|
||||
#define REG_PCM_BSIZE47 0x040
|
||||
#define REG_PCM_CH4TXBSA 0x044
|
||||
#define REG_PCM_CH5TXBSA 0x048
|
||||
#define REG_PCM_CH6TXBSA 0x04c
|
||||
#define REG_PCM_CH7TXBSA 0x050
|
||||
#define REG_PCM_CH4RXBSA 0x054
|
||||
#define REG_PCM_CH5RXBSA 0x058
|
||||
#define REG_PCM_CH6RXBSA 0x05c
|
||||
#define REG_PCM_CH7RXBSA 0x060
|
||||
|
||||
#define REG_PCM_IMR47 0x064
|
||||
#define REG_PCM_ISR47 0x068
|
||||
|
||||
#define REG_PCM_CHCNR811 0x06c
|
||||
#define REG_PCM_TSR811 0x070
|
||||
#define REG_PCM_BSIZE811 0x074
|
||||
#define REG_PCM_CH8TXBSA 0x078
|
||||
#define REG_PCM_CH9TXBSA 0x07c
|
||||
#define REG_PCM_CH10TXBSA 0x080
|
||||
#define REG_PCM_CH11TXBSA 0x084
|
||||
#define REG_PCM_CH8RXBSA 0x088
|
||||
#define REG_PCM_CH9RXBSA 0x08c
|
||||
#define REG_PCM_CH10RXBSA 0x090
|
||||
#define REG_PCM_CH11RXBSA 0x094
|
||||
|
||||
#define REG_PCM_IMR811 0x098
|
||||
#define REG_PCM_ISR811 0x09c
|
||||
|
||||
#define REG_PCM_CHCNR1215 0x0a0
|
||||
#define REG_PCM_TSR1215 0x0a4
|
||||
#define REG_PCM_BSIZE1215 0x0a8
|
||||
#define REG_PCM_CH12TXBSA 0x0ac
|
||||
#define REG_PCM_CH13TXBSA 0x0b0
|
||||
#define REG_PCM_CH14TXBSA 0x0b4
|
||||
#define REG_PCM_CH15TXBSA 0x0b8
|
||||
#define REG_PCM_CH12RXBSA 0x0bc
|
||||
#define REG_PCM_CH13RXBSA 0x0c0
|
||||
#define REG_PCM_CH14RXBSA 0x0c4
|
||||
#define REG_PCM_CH15RXBSA 0x0c8
|
||||
|
||||
#define REG_PCM_IMR1215 0x0cc
|
||||
#define REG_PCM_ISR1215 0x0d0
|
||||
|
||||
#define REG_PCM_INTMAP 0x0d4
|
||||
#define REG_PCM_WTSR03 0x0d8
|
||||
#define REG_PCM_WTSR47 0x0dc
|
||||
|
||||
#define REG_PCM_RX_BUFOW 0x0e0
|
||||
|
||||
/* template
|
||||
#define BIT_SHIFT_CTLX_ 7
|
||||
#define BIT_MASK_CTLX_ 0x1
|
||||
#define BIT_CTLX_(x) (((x) & BIT_MASK_CTLX_) << BIT_SHIFT_CTLX_)
|
||||
#define BIT_INV_CTLX_ (~(BIT_MASK_CTLX_ << BIT_SHIFT_CTLX_))
|
||||
*/
|
||||
#define BIT_SHIFT_CTLX_SLAVE_SEL 8
|
||||
#define BIT_MASK_CTLX_SLAVE_SEL 0x1
|
||||
#define BIT_CTLX_SLAVE_SEL(x) (((x) & BIT_MASK_CTLX_SLAVE_SEL) << BIT_SHIFT_CTLX_SLAVE_SEL)
|
||||
#define BIT_INV_CTLX_SLAVE_SEL (~(BIT_MASK_CTLX_SLAVE_SEL << BIT_SHIFT_CTLX_SLAVE_SEL))
|
||||
|
||||
#define BIT_SHIFT_CTLX_FSINV 9
|
||||
#define BIT_MASK_CTLX_FSINV 0x1
|
||||
#define BIT_CTLX_FSINV(x) (((x) & BIT_MASK_CTLX_FSINV) << BIT_SHIFT_CTLX_FSINV)
|
||||
#define BIT_INV_CTLX_FSINV (~(BIT_MASK_CTLX_FSINV << BIT_SHIFT_CTLX_FSINV))
|
||||
|
||||
#define BIT_SHIFT_CTLX_PCM_EN 12
|
||||
#define BIT_MASK_CTLX_PCM_EN 0x1
|
||||
#define BIT_CTLX_PCM_EN(x) (((x) & BIT_MASK_CTLX_PCM_EN) << BIT_SHIFT_CTLX_PCM_EN)
|
||||
#define BIT_INV_CTLX_PCM_EN (~(BIT_MASK_CTLX_PCM_EN << BIT_SHIFT_CTLX_PCM_EN))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LINEARMODE 13
|
||||
#define BIT_MASK_CTLX_LINEARMODE 0x1
|
||||
#define BIT_CTLX_LINEARMODE(x) (((x) & BIT_MASK_CTLX_LINEARMODE) << BIT_SHIFT_CTLX_LINEARMODE)
|
||||
#define BIT_INV_CTLX_LINEARMODE (~(BIT_MASK_CTLX_LINEARMODE << BIT_SHIFT_CTLX_LINEARMODE))
|
||||
|
||||
#define BIT_SHIFT_CTLX_LOOP_BACK 14
|
||||
#define BIT_MASK_CTLX_LOOP_BACK 0x1
|
||||
#define BIT_CTLX_LOOP_BACK(x) (((x) & BIT_MASK_CTLX_LOOP_BACK) << BIT_SHIFT_CTLX_LOOP_BACK)
|
||||
#define BIT_INV_CTLX_LOOP_BACK (~(BIT_MASK_CTLX_LOOP_BACK << BIT_SHIFT_CTLX_LOOP_BACK))
|
||||
|
||||
#define BIT_SHIFT_CTLX_ENDIAN_SWAP 17
|
||||
#define BIT_MASK_CTLX_ENDIAN_SWAP 0x1
|
||||
#define BIT_CTLX_ENDIAN_SWAP(x) (((x) & BIT_MASK_CTLX_ENDIAN_SWAP) << BIT_SHIFT_CTLX_ENDIAN_SWAP)
|
||||
#define BIT_INV_CTLX_ENDIAN_SWAP (~(BIT_MASK_CTLX_ENDIAN_SWAP << BIT_SHIFT_CTLX_ENDIAN_SWAP))
|
||||
|
||||
#define BIT_SHIFT_CHCNR03_CH0RE 24
|
||||
#define BIT_MASK_CHCNR03_CH0RE 0x1
|
||||
#define BIT_CHCNR03_CH0RE(x) (((x) & BIT_MASK_CHCNR03_CH0RE) << BIT_SHIFT_CHCNR03_CH0RE)
|
||||
#define BIT_INV_CHCNR03_CH0RE (~(BIT_MASK_CHCNR03_CH0RE << BIT_SHIFT_CHCNR03_CH0RE))
|
||||
|
||||
#define BIT_SHIFT_CHCNR03_CH0TE 25
|
||||
#define BIT_MASK_CHCNR03_CH0TE 0x1
|
||||
#define BIT_CHCNR03_CH0TE(x) (((x) & BIT_MASK_CHCNR03_CH0TE) << BIT_SHIFT_CHCNR03_CH0TE)
|
||||
#define BIT_INV_CHCNR03_CH0TE (~(BIT_MASK_CHCNR03_CH0TE << BIT_SHIFT_CHCNR03_CH0TE))
|
||||
|
||||
#define BIT_SHIFT_CHCNR03_CH1RE 16
|
||||
#define BIT_MASK_CHCNR03_CH1RE 0x1
|
||||
#define BIT_CHCNR03_CH1RE(x) (((x) & BIT_MASK_CHCNR03_CH1RE) << BIT_SHIFT_CHCNR03_CH1RE)
|
||||
#define BIT_INV_CHCNR03_CH1RE (~(BIT_MASK_CHCNR03_CH1RE << BIT_SHIFT_CHCNR03_CH1RE))
|
||||
|
||||
#define BIT_SHIFT_CHCNR03_CH1TE 17
|
||||
#define BIT_MASK_CHCNR03_CH1TE 0x1
|
||||
#define BIT_CHCNR03_CH1TE(x) (((x) & BIT_MASK_CHCNR03_CH1TE) << BIT_SHIFT_CHCNR03_CH1TE)
|
||||
#define BIT_INV_CHCNR03_CH1TE (~(BIT_MASK_CHCNR03_CH1TE << BIT_SHIFT_CHCNR03_CH1TE))
|
||||
|
||||
#define BIT_SHIFT_CHCNR03_CH2RE 8
|
||||
#define BIT_MASK_CHCNR03_CH2RE 0x1
|
||||
#define BIT_CHCNR03_CH2RE(x) (((x) & BIT_MASK_CHCNR03_CH2RE) << BIT_SHIFT_CHCNR03_CH2RE)
|
||||
#define BIT_INV_CHCNR03_CH2RE (~(BIT_MASK_CHCNR03_CH2RE << BIT_SHIFT_CHCNR03_CH2RE))
|
||||
|
||||
#define BIT_SHIFT_CHCNR03_CH2TE 9
|
||||
#define BIT_MASK_CHCNR03_CH2TE 0x1
|
||||
#define BIT_CHCNR03_CH2TE(x) (((x) & BIT_MASK_CHCNR03_CH2TE) << BIT_SHIFT_CHCNR03_CH2TE)
|
||||
#define BIT_INV_CHCNR03_CH2TE (~(BIT_MASK_CHCNR03_CH2TE << BIT_SHIFT_CHCNR03_CH2TE))
|
||||
|
||||
#define BIT_SHIFT_CHCNR03_CH3RE 0
|
||||
#define BIT_MASK_CHCNR03_CH3RE 0x1
|
||||
#define BIT_CHCNR03_CH3RE(x) (((x) & BIT_MASK_CHCNR03_CH3RE) << BIT_SHIFT_CHCNR03_CH3RE)
|
||||
#define BIT_INV_CHCNR03_CH3RE (~(BIT_MASK_CHCNR03_CH3RE << BIT_SHIFT_CHCNR03_CH3RE))
|
||||
|
||||
#define BIT_SHIFT_CHCNR03_CH3TE 1
|
||||
#define BIT_MASK_CHCNR03_CH3TE 0x1
|
||||
#define BIT_CHCNR03_CH3TE(x) (((x) & BIT_MASK_CHCNR03_CH3TE) << BIT_SHIFT_CHCNR03_CH3TE)
|
||||
#define BIT_INV_CHCNR03_CH3TE (~(BIT_MASK_CHCNR03_CH3TE << BIT_SHIFT_CHCNR03_CH3TE))
|
||||
|
||||
#define BIT_SHIFT_CHCNR03_CH0MUA 26
|
||||
#define BIT_MASK_CHCNR03_CH0MUA 0x1
|
||||
#define BIT_CHCNR03_CH0MUA(x) (((x) & BIT_MASK_CHCNR03_CH0MUA) << BIT_SHIFT_CHCNR03_CH0MUA)
|
||||
#define BIT_INV_CHCNR03_CH0MUA (~(BIT_MASK_CHCNR03_CH0MUA << BIT_SHIFT_CHCNR03_CH0MUA))
|
||||
|
||||
#define BIT_SHIFT_CHCNR03_CH0BAND 27
|
||||
#define BIT_MASK_CHCNR03_CH0BAND 0x1
|
||||
#define BIT_CHCNR03_CH0BAND(x) (((x) & BIT_MASK_CHCNR03_CH0BAND) << BIT_SHIFT_CHCNR03_CH0BAND)
|
||||
#define BIT_INV_CHCNR03_CH0BAND (~(BIT_MASK_CHCNR03_CH0BAND << BIT_SHIFT_CHCNR03_CH0BAND))
|
||||
|
||||
#define BIT_SHIFT_TSR03_CH0TSA 24
|
||||
#define BIT_MASK_TSR03_CH0TSA 0x1F
|
||||
#define BIT_TSR03_CH0TSA(x) (((x) & BIT_MASK_TSR03_CH0TSA) << BIT_SHIFT_TSR03_CH0TSA)
|
||||
#define BIT_INV_TSR03_CH0TSA (~(BIT_MASK_TSR03_CH0TSA << BIT_SHIFT_TSR03_CH0TSA))
|
||||
|
||||
#define BIT_SHIFT_BSIZE03_CH0BSIZE 24
|
||||
#define BIT_MASK_BSIZE03_CH0BSIZE 0xFF
|
||||
#define BIT_BSIZE03_CH0BSIZE(x) (((x) & BIT_MASK_BSIZE03_CH0BSIZE) << BIT_SHIFT_BSIZE03_CH0BSIZE)
|
||||
#define BIT_INV_BSIZE03_CH0BSIZE (~(BIT_MASK_BSIZE03_CH0BSIZE << BIT_SHIFT_BSIZE03_CH0BSIZE))
|
||||
|
||||
typedef struct _PCM_CTL_REG_ {
|
||||
u32 FCNT :8; // Bit 0-7
|
||||
u32 SlaveMode :1; // Bit 8
|
||||
u32 FsInv :1; // Bit 9
|
||||
u32 Rsvd10to11 :1; // Bit 10-11
|
||||
u32 Pcm_En :1; // Bit 12
|
||||
u32 LinearMode :1; // Bit 13
|
||||
u32 LoopBack :1; // Bit 14
|
||||
u32 Rsvd15to16 :2; // Bit 15-16
|
||||
u32 EndianSwap :1; // Bit 17
|
||||
u32 Rsvd18to31 :14; // Bit 18-31
|
||||
} PCM_CTL_REG, *PPCM_CTL_REG;
|
||||
|
||||
|
||||
|
||||
typedef struct _PCM_CHCNR03_REG_ {
|
||||
u32 CH3RE :1; // Bit 0
|
||||
u32 CH3TE :1; // Bit 1
|
||||
u32 CH3MuA :1; // Bit 2
|
||||
u32 CH3Band :1; // Bit 3
|
||||
u32 CH3SlicSel:4; // Bit 4-7
|
||||
u32 CH2RE :1; // Bit 8
|
||||
u32 CH2TE :1; // Bit 9
|
||||
u32 CH2MuA :1; // Bit 10
|
||||
u32 CH2Band :1; // Bit 11
|
||||
u32 CH2SlicSel:4; // Bit 12-15
|
||||
u32 CH1RE :1; // Bit 16
|
||||
u32 CH1TE :1; // Bit 17
|
||||
u32 CH1MuA :1; // Bit 18
|
||||
u32 CH1Band :1; // Bit 19
|
||||
u32 CH1SlicSel:4; // Bit 20-23
|
||||
u32 CH0RE :1; // Bit 24
|
||||
u32 CH0TE :1; // Bit 25
|
||||
u32 CH0MuA :1; // Bit 26
|
||||
u32 CH0Band :1; // Bit 27
|
||||
u32 CH0SlicSel:4; // Bit 28-31
|
||||
}PCM_CHCNR03_REG, *PPCM_CHCNR03_REG;
|
||||
|
||||
typedef struct _PCM_TSR03_REG_ {
|
||||
u32 CH3TSA :5; // Bit 0-4
|
||||
u32 Rsvd5to7 :3; // Bit 5-7
|
||||
u32 CH2TSA :5; // Bit 8-12
|
||||
u32 Rsvd13to15:3; // Bit 13-15
|
||||
u32 CH1TSA :5; // Bit 16-20
|
||||
u32 Rsvd21to23:3; // Bit 21-23
|
||||
u32 CH0TSA :5; // Bit 24-28
|
||||
u32 Rsvd29to31:3; // Bit 29-31
|
||||
}PCM_TSR03_REG, *PPCM_TSR03_REG;
|
||||
|
||||
typedef struct _PCM_BSIZE03_REG_ {
|
||||
u32 CH3BSize :8; // Bit 0-7
|
||||
u32 CH2BSize :8; // Bit 8-15
|
||||
u32 CH1BSize :8; // Bit 16-23
|
||||
u32 CH0BSize :8; // Bit 24-31
|
||||
}PCM_BSIZE03_REG, *PPCM_BSIZE03_REG;
|
||||
|
||||
typedef struct _PCM_ISR03_REG_ {
|
||||
u32 CH3RXP1UA :1; // Bit 0
|
||||
u32 CH3RXP0UA :1; // Bit 1
|
||||
u32 CH3TXP1UA :1; // Bit 2
|
||||
u32 CH3TXP0UA :1; // Bit 3
|
||||
u32 CH3RXP1IP :1; // Bit 4
|
||||
u32 CH3RXP0IP :1; // Bit 5
|
||||
u32 CH3TXP1IP :1; // Bit 6
|
||||
u32 CH3TXP0IP :1; // Bit 7
|
||||
u32 CH2RXP1UA :1; // Bit 8
|
||||
u32 CH2RXP0UA :1; // Bit 9
|
||||
u32 CH2TXP1UA :1; // Bit 10
|
||||
u32 CH2TXP0UA :1; // Bit 11
|
||||
u32 CH2RXP1IP :1; // Bit 12
|
||||
u32 CH2RXP0IP :1; // Bit 13
|
||||
u32 CH2TXP1IP :1; // Bit 14
|
||||
u32 CH2TXP0IP :1; // Bit 15
|
||||
u32 CH1RXP1UA :1; // Bit 16
|
||||
u32 CH1RXP0UA :1; // Bit 17
|
||||
u32 CH1TXP1UA :1; // Bit 18
|
||||
u32 CH1TXP0UA :1; // Bit 19
|
||||
u32 CH1RXP1IP :1; // Bit 20
|
||||
u32 CH1RXP0IP :1; // Bit 21
|
||||
u32 CH1TXP1IP :1; // Bit 22
|
||||
u32 CH1TXP0IP :1; // Bit 23
|
||||
u32 CH0RXP1UA :1; // Bit 24
|
||||
u32 CH0RXP0UA :1; // Bit 25
|
||||
u32 CH0TXP1UA :1; // Bit 26
|
||||
u32 CH0TXP0UA :1; // Bit 27
|
||||
u32 CH0RXP1IP :1; // Bit 28
|
||||
u32 CH0RXP0IP :1; // Bit 29
|
||||
u32 CH0TXP1IP :1; // Bit 30
|
||||
u32 CH0TXP0IP :1; // Bit 31
|
||||
}PCM_ISR03_REG, *PPCM_ISR03_REG;
|
||||
|
||||
typedef enum _PCM_ISR015 {
|
||||
PcmCh3P1RBU = 0x00000001, //ch0-3
|
||||
PcmCh3P0RBU = 0x00000002,
|
||||
PcmCh3P1TBU = 0x00000004,
|
||||
PcmCh3P0TBU = 0x00000008,
|
||||
PcmCh3P1ROK = 0x00000010,
|
||||
PcmCh3P0ROK = 0x00000020,
|
||||
PcmCh3P1TOK = 0x00000040,
|
||||
PcmCh3P0TOK = 0x00000080,
|
||||
PcmCh2P1RBU = 0x00000100,
|
||||
PcmCh2P0RBU = 0x00000200,
|
||||
PcmCh2P1TBU = 0x00000400,
|
||||
PcmCh2P0TBU = 0x00000800,
|
||||
PcmCh2P1ROK = 0x00001000,
|
||||
PcmCh2P0ROK = 0x00002000,
|
||||
PcmCh2P1TOK = 0x00004000,
|
||||
PcmCh2P0TOK = 0x00008000,
|
||||
PcmCh1P1RBU = 0x00010000,
|
||||
PcmCh1P0RBU = 0x00020000,
|
||||
PcmCh1P1TBU = 0x00040000,
|
||||
PcmCh1P0TBU = 0x00080000,
|
||||
PcmCh1P1ROK = 0x00100000,
|
||||
PcmCh1P0ROK = 0x00200000,
|
||||
PcmCh1P1TOK = 0x00400000,
|
||||
PcmCh1P0TOK = 0x00800000,
|
||||
PcmCh0P1RBU = 0x01000000,
|
||||
PcmCh0P0RBU = 0x02000000,
|
||||
PcmCh0P1TBU = 0x04000000,
|
||||
PcmCh0P0TBU = 0x08000000,
|
||||
PcmCh0P1ROK = 0x10000000,
|
||||
PcmCh0P0ROK = 0x20000000,
|
||||
PcmCh0P1TOK = 0x40000000,
|
||||
PcmCh0P0TOK = 0x80000000,
|
||||
|
||||
PcmCh7P1RBU = 0x00000001, //ch4-7
|
||||
PcmCh7P0RBU = 0x00000002,
|
||||
PcmCh7P1TBU = 0x00000004,
|
||||
PcmCh7P0TBU = 0x00000008,
|
||||
PcmCh7P1ROK = 0x00000010,
|
||||
PcmCh7P0ROK = 0x00000020,
|
||||
PcmCh7P1TOK = 0x00000040,
|
||||
PcmCh7P0TOK = 0x00000080,
|
||||
PcmCh6P1RBU = 0x00000100,
|
||||
PcmCh6P0RBU = 0x00000200,
|
||||
PcmCh6P1TBU = 0x00000400,
|
||||
PcmCh6P0TBU = 0x00000800,
|
||||
PcmCh6P1ROK = 0x00001000,
|
||||
PcmCh6P0ROK = 0x00002000,
|
||||
PcmCh6P1TOK = 0x00004000,
|
||||
PcmCh6P0TOK = 0x00008000,
|
||||
PcmCh5P1RBU = 0x00010000,
|
||||
PcmCh5P0RBU = 0x00020000,
|
||||
PcmCh5P1TBU = 0x00040000,
|
||||
PcmCh5P0TBU = 0x00080000,
|
||||
PcmCh5P1ROK = 0x00100000,
|
||||
PcmCh5P0ROK = 0x00200000,
|
||||
PcmCh5P1TOK = 0x00400000,
|
||||
PcmCh5P0TOK = 0x00800000,
|
||||
PcmCh4P1RBU = 0x01000000,
|
||||
PcmCh4P0RBU = 0x02000000,
|
||||
PcmCh4P1TBU = 0x04000000,
|
||||
PcmCh4P0TBU = 0x08000000,
|
||||
PcmCh4P1ROK = 0x10000000,
|
||||
PcmCh4P0ROK = 0x20000000,
|
||||
PcmCh4P1TOK = 0x40000000,
|
||||
PcmCh4P0TOK = 0x80000000,
|
||||
|
||||
PcmCh11P1RBU = 0x00000001, //ch8-11
|
||||
PcmCh11P0RBU = 0x00000002,
|
||||
PcmCh11P1TBU = 0x00000004,
|
||||
PcmCh11P0TBU = 0x00000008,
|
||||
PcmCh11P1ROK = 0x00000010,
|
||||
PcmCh11P0ROK = 0x00000020,
|
||||
PcmCh11P1TOK = 0x00000040,
|
||||
PcmCh11P0TOK = 0x00000080,
|
||||
PcmCh10P1RBU = 0x00000100,
|
||||
PcmCh10P0RBU = 0x00000200,
|
||||
PcmCh10P1TBU = 0x00000400,
|
||||
PcmCh10P0TBU = 0x00000800,
|
||||
PcmCh10P1ROK = 0x00001000,
|
||||
PcmCh10P0ROK = 0x00002000,
|
||||
PcmCh10P1TOK = 0x00004000,
|
||||
PcmCh10P0TOK = 0x00008000,
|
||||
PcmCh9P1RBU = 0x00010000,
|
||||
PcmCh9P0RBU = 0x00020000,
|
||||
PcmCh9P1TBU = 0x00040000,
|
||||
PcmCh9P0TBU = 0x00080000,
|
||||
PcmCh9P1ROK = 0x00100000,
|
||||
PcmCh9P0ROK = 0x00200000,
|
||||
PcmCh9P1TOK = 0x00400000,
|
||||
PcmCh9P0TOK = 0x00800000,
|
||||
PcmCh8P1RBU = 0x01000000,
|
||||
PcmCh8P0RBU = 0x02000000,
|
||||
PcmCh8P1TBU = 0x04000000,
|
||||
PcmCh8P0TBU = 0x08000000,
|
||||
PcmCh8P1ROK = 0x10000000,
|
||||
PcmCh8P0ROK = 0x20000000,
|
||||
PcmCh8P1TOK = 0x40000000,
|
||||
PcmCh8P0TOK = 0x80000000,
|
||||
|
||||
PcmCh15P1RBU = 0x00000001, //ch12-15
|
||||
PcmCh15P0RBU = 0x00000002,
|
||||
PcmCh15P1TBU = 0x00000004,
|
||||
PcmCh15P0TBU = 0x00000008,
|
||||
PcmCh15P1ROK = 0x00000010,
|
||||
PcmCh15P0ROK = 0x00000020,
|
||||
PcmCh15P1TOK = 0x00000040,
|
||||
PcmCh15P0TOK = 0x00000080,
|
||||
PcmCh14P1RBU = 0x00000100,
|
||||
PcmCh14P0RBU = 0x00000200,
|
||||
PcmCh14P1TBU = 0x00000400,
|
||||
PcmCh14P0TBU = 0x00000800,
|
||||
PcmCh14P1ROK = 0x00001000,
|
||||
PcmCh14P0ROK = 0x00002000,
|
||||
PcmCh14P1TOK = 0x00004000,
|
||||
PcmCh14P0TOK = 0x00008000,
|
||||
PcmCh13P1RBU = 0x00010000,
|
||||
PcmCh13P0RBU = 0x00020000,
|
||||
PcmCh13P1TBU = 0x00040000,
|
||||
PcmCh13P0TBU = 0x00080000,
|
||||
PcmCh13P1ROK = 0x00100000,
|
||||
PcmCh13P0ROK = 0x00200000,
|
||||
PcmCh13P1TOK = 0x00400000,
|
||||
PcmCh13P0TOK = 0x00800000,
|
||||
PcmCh12P1RBU = 0x01000000,
|
||||
PcmCh12P0RBU = 0x02000000,
|
||||
PcmCh12P1TBU = 0x04000000,
|
||||
PcmCh12P0TBU = 0x08000000,
|
||||
PcmCh12P1ROK = 0x10000000,
|
||||
PcmCh12P0ROK = 0x20000000,
|
||||
PcmCh12P1TOK = 0x40000000,
|
||||
PcmCh12P0TOK = 0x80000000
|
||||
}PCM_ISR015, *PPCM_ISR015;
|
||||
|
||||
VOID
|
||||
HalPcmOnOffRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalPcmInitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalPcmSettingRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalPcmEnRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalPcmIsrEnAndDisRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalPcmDumpRegRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
BOOL
|
||||
HalPcmRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#endif /* _RTL8195A_PCM_H_ */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RTL8195A_PWM_H_
|
||||
#define _RTL8195A_PWM_H_
|
||||
#include "basic_types.h"
|
||||
|
||||
extern void
|
||||
HAL_Pwm_SetDuty_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt,
|
||||
u32 period,
|
||||
u32 pulse_width
|
||||
);
|
||||
|
||||
extern HAL_Status
|
||||
HAL_Pwm_Init_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
);
|
||||
|
||||
extern void
|
||||
HAL_Pwm_Enable_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
);
|
||||
|
||||
extern void
|
||||
HAL_Pwm_Disable_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
);
|
||||
|
||||
|
||||
#ifdef CONFIG_CHIP_E_CUT
|
||||
extern _LONG_CALL_ void
|
||||
HAL_Pwm_SetDuty_8195a_V04(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt,
|
||||
u32 period,
|
||||
u32 pulse_width
|
||||
);
|
||||
|
||||
extern _LONG_CALL_ HAL_Status
|
||||
HAL_Pwm_Init_8195a_V04(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
);
|
||||
|
||||
extern _LONG_CALL_ void
|
||||
HAL_Pwm_Enable_8195a_V04(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
);
|
||||
|
||||
extern _LONG_CALL_ void
|
||||
HAL_Pwm_Disable_8195a_V04(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,809 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RTL8195A_SDIO_HOST_H_
|
||||
#define _RTL8195A_SDIO_HOST_H_
|
||||
|
||||
#include "hal_api.h"
|
||||
#include "osdep_api.h"
|
||||
|
||||
|
||||
|
||||
#define HAL_SDIO_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
|
||||
#define HAL_SDIO_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
|
||||
#define HAL_SDIO_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
|
||||
#define HAL_SDIO_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
|
||||
#define HAL_SDIO_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
|
||||
#define HAL_SDIO_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
|
||||
|
||||
/* =============== Register Offset Definition =============== */
|
||||
#define REG_SDIO_HOST_SDMA_SYS_ADDR 0x00 // 4byte
|
||||
#define REG_SDIO_HOST_BLK_SIZE 0x04 // 2byte
|
||||
#define REG_SDIO_HOST_BLK_CNT 0x06 // 2byte
|
||||
#define REG_SDIO_HOST_ARG 0x08 // 4byte
|
||||
#define REG_SDIO_HOST_XFER_MODE 0x0C // 2byte
|
||||
#define REG_SDIO_HOST_CMD 0x0E // 2byte
|
||||
#define REG_SDIO_HOST_RSP0 0x10 // 4byte
|
||||
#define REG_SDIO_HOST_RSP2 0x14 // 4byte
|
||||
#define REG_SDIO_HOST_RSP4 0x18 // 4byte
|
||||
#define REG_SDIO_HOST_RSP6 0x1C // 4byte
|
||||
#define REG_SDIO_HOST_BUF_DATA_PORT 0x20 // 4byte
|
||||
#define REG_SDIO_HOST_PRESENT_STATE 0x24 // 4byte
|
||||
#define REG_SDIO_HOST_HOST_CTRL 0x28 // 1byte
|
||||
#define REG_SDIO_HOST_PWR_CTRL 0x29 // 1byte
|
||||
#define REG_SDIO_HOST_BLK_GAP_CTRL 0x2A // 1byte
|
||||
#define REG_SDIO_HOST_WAKEUP_CTRL 0x2B // 1byte
|
||||
#define REG_SDIO_HOST_CLK_CTRL 0x2C // 2byte
|
||||
#define REG_SDIO_HOST_TIMEOUT_CTRL 0x2E // 1byte
|
||||
#define REG_SDIO_HOST_SW_RESET 0x2F // 1byte
|
||||
#define REG_SDIO_HOST_NORMAL_INT_STATUS 0x30 // 2byte
|
||||
#define REG_SDIO_HOST_ERROR_INT_STATUS 0x32 // 2byte
|
||||
#define REG_SDIO_HOST_NORMAL_INT_STATUS_EN 0x34 // 2byte
|
||||
#define REG_SDIO_HOST_ERROR_INT_STATUS_EN 0x36 // 2byte
|
||||
#define REG_SDIO_HOST_NORMAL_INT_SIG_EN 0x38 // 2byte
|
||||
#define REG_SDIO_HOST_ERROR_INT_SIG_EN 0x3A // 2byte
|
||||
#define REG_SDIO_HOST_CAPABILITIES 0x40 // 8byte
|
||||
#define REG_SDIO_HOST_ADMA_SYS_ADDR 0x58 // 8byte
|
||||
/* =============================================== */
|
||||
|
||||
/* Block Count Register (0x06) */
|
||||
#define BLK_CNT_REG_MAX 0xFFFF // 65535 blocks
|
||||
|
||||
/* Transfer Mode Register (0x0C) */
|
||||
#define XFER_MODE_DMA_EN BIT0
|
||||
#define XFER_MODE_BLK_CNT_EN BIT1
|
||||
#define XFER_MODE_AUTO_CMD12_EN BIT2
|
||||
#define XFER_MODE_DATA_XFER_DIR BIT4
|
||||
#define XFER_MODE_MULT_SINGLE_BLK BIT5
|
||||
|
||||
/* Present State Register (0x24) */
|
||||
#define PRES_STATE_CMD_INHIBIT_CMD BIT0
|
||||
#define PRES_STATE_CMD_INHIBIT_DAT BIT1
|
||||
#define PRES_STATE_DAT_LINE_ACTIVE BIT2
|
||||
#define PRES_STATE_CARD_INSERTED BIT16
|
||||
#define PRES_STATE_DAT0_SIGNAL_LEVEL BIT20
|
||||
|
||||
/* Power Control Register (0x29) */
|
||||
#define PWR_CTRL_SD_BUS_PWR BIT0
|
||||
|
||||
/* Clock Control Register (0x2C) */
|
||||
#define CLK_CTRL_INTERAL_CLK_EN BIT0
|
||||
#define CLK_CTRL_INTERAL_CLK_STABLE BIT1
|
||||
#define CLK_CTRL_SD_CLK_EN BIT2
|
||||
|
||||
/* Software Reset Register (0x2F) */
|
||||
#define SW_RESET_FOR_ALL BIT0
|
||||
#define SW_RESET_FOR_CMD BIT1
|
||||
#define SW_RESET_FOR_DAT BIT2
|
||||
|
||||
/* Normal Interrupt Status (0x30) */
|
||||
#define NOR_INT_STAT_CMD_COMP BIT0
|
||||
#define NOR_INT_STAT_XFER_COMP BIT1
|
||||
#define NOR_INT_STAT_BLK_GAP_EVENT BIT2
|
||||
#define NOR_INT_STAT_DMA_INT BIT3
|
||||
#define NOR_INT_STAT_BUF_WR_RDY BIT4
|
||||
#define NOR_INT_STAT_BUF_RD_RDY BIT5
|
||||
#define NOR_INT_STAT_CARD_INSERT BIT6
|
||||
#define NOR_INT_STAT_CARD_REMOVAL BIT7
|
||||
#define NOR_INT_STAT_CARD_INT BIT8
|
||||
#define NOR_INT_STAT_ERR_INT BIT15
|
||||
|
||||
/* Error Interrupt Status (0x32) */
|
||||
#define ERR_INT_STAT_CMD_TIMEOUT BIT0
|
||||
#define ERR_INT_STAT_CMD_CRC BIT1
|
||||
#define ERR_INT_STAT_CMD_END_BIT BIT2
|
||||
#define ERR_INT_STAT_CMD_IDX BIT3
|
||||
#define ERR_INT_STAT_DATA_TIMEOUT BIT4
|
||||
#define ERR_INT_STAT_DATA_CRC BIT5
|
||||
#define ERR_INT_STAT_DATA_END_BIT BIT6
|
||||
#define ERR_INT_STAT_CUR_LIMIT BIT7
|
||||
#define ERR_INT_STAT_AUTO_CMD12 BIT8
|
||||
#define ERR_INT_STAT_ADMA BIT9
|
||||
|
||||
/* Normal Interrupt Status Enable (0x34) */
|
||||
#define NOR_INT_STAT_EN_CMD_COMP BIT0
|
||||
#define NOR_INT_STAT_EN_XFER_COMP BIT1
|
||||
#define NOR_INT_STAT_EN_BLK_GAP_EVENT BIT2
|
||||
#define NOR_INT_STAT_EN_DMA_INT BIT3
|
||||
#define NOR_INT_STAT_EN_BUF_WR_RDY BIT4
|
||||
#define NOR_INT_STAT_EN_BUF_RD_RDY BIT5
|
||||
#define NOR_INT_STAT_EN_CARD_INSERT BIT6
|
||||
#define NOR_INT_STAT_EN_CARD_REMOVAL BIT7
|
||||
#define NOR_INT_STAT_EN_CARD_INT BIT8
|
||||
|
||||
/* Error Interrupt Status Enable (0x36) */
|
||||
#define ERR_INT_STAT_EN_CMD_TIMEOUT BIT0
|
||||
#define ERR_INT_STAT_EN_CMD_CRC BIT1
|
||||
#define ERR_INT_STAT_EN_CMD_END_BIT BIT2
|
||||
#define ERR_INT_STAT_EN_CMD_IDX BIT3
|
||||
#define ERR_INT_STAT_EN_DATA_TIMEOUT BIT4
|
||||
#define ERR_INT_STAT_EN_DATA_CRC BIT5
|
||||
#define ERR_INT_STAT_EN_DATA_END_BIT BIT6
|
||||
#define ERR_INT_STAT_EN_CUR_LIMIT BIT7
|
||||
#define ERR_INT_STAT_EN_AUTO_CMD BIT8
|
||||
#define ERR_INT_STAT_EN_ADMA BIT9
|
||||
|
||||
/* Normal Interrupt Signal Enable (0x38) */
|
||||
#define NOR_INT_SIG_EN_CMD_COMP BIT0
|
||||
#define NOR_INT_SIG_EN_XFER_COMP BIT1
|
||||
#define NOR_INT_SIG_EN_BLK_GAP_EVENT BIT2
|
||||
#define NOR_INT_SIG_EN_DMA_INT BIT3
|
||||
#define NOR_INT_SIG_EN_BUF_WR_RDY BIT4
|
||||
#define NOR_INT_SIG_EN_BUF_RD_RDY BIT5
|
||||
#define NOR_INT_SIG_EN_CARD_INSERT BIT6
|
||||
#define NOR_INT_SIG_EN_CARD_REMOVAL BIT7
|
||||
#define NOR_INT_SIG_EN_CARD_INT BIT8
|
||||
|
||||
/* Error Interrupt Signal Enable (0x3A) */
|
||||
#define ERR_INT_SIG_EN_CMD_TIMEOUT BIT0
|
||||
#define ERR_INT_SIG_EN_CMD_CRC BIT1
|
||||
#define ERR_INT_SIG_EN_CMD_END_BIT BIT2
|
||||
#define ERR_INT_SIG_EN_CMD_IDX BIT3
|
||||
#define ERR_INT_SIG_EN_DATA_TIMEOUT BIT4
|
||||
#define ERR_INT_SIG_EN_DATA_CRC BIT5
|
||||
#define ERR_INT_SIG_EN_DATA_END_BIT BIT6
|
||||
#define ERR_INT_SIG_EN_CUR_LIMIT BIT7
|
||||
#define ERR_INT_SIG_EN_AUTO_CMD BIT8
|
||||
#define ERR_INT_SIG_EN_ADMA BIT9
|
||||
|
||||
/* Capabilities Register (0x40) */
|
||||
#define CAPA_TIMEOUT_CLK_UNIT BIT7
|
||||
#define CAPA_ADMA2_SUPPORT BIT19
|
||||
#define CAPA_HIGH_SPEED_SUPPORT BIT21
|
||||
#define CAPA_VOLT_SUPPORT_33V BIT24
|
||||
#define CAPA_VOLT_SUPPORT_30V BIT25
|
||||
#define CAPA_VOLT_SUPPORT_18V BIT26
|
||||
|
||||
#define DATA_BLK_LEN 512
|
||||
#define SCR_REG_LEN 8 // 64 bits
|
||||
#define SWITCH_FN_STATUS_LEN 64 // 512 bits
|
||||
#define SD_STATUS_LEN 64 // 512 bits
|
||||
#define CSD_REG_LEN 16 // 128 bits
|
||||
|
||||
/* Switch Function (CMD6) Group */
|
||||
#define SWITCH_FN_GRP1_DEFAULT BIT0
|
||||
#define SWITCH_FN_GRP1_HIGH_SPEED BIT1
|
||||
#define SWITCH_FN_GRP2_DEFAULT BIT0
|
||||
#define SWITCH_FN_GRP2_FOR_EC BIT1
|
||||
#define SWITCH_FN_GRP2_VENDOR_SPECIFIC BIT14
|
||||
|
||||
/* Operating Condition (ACMD41) */
|
||||
#define ACMD41_POLL_INTERVAL 10000 // 10 ms
|
||||
#define ACMD41_INIT_TIMEOUT 1000000 // 1 sec
|
||||
|
||||
/* Card Status (R1) */
|
||||
#define R1_APP_CMD BIT5
|
||||
#define R1_WP_VIOLATION BIT26
|
||||
|
||||
/* Error Interrupt Recovery */
|
||||
#define HAL_SDH_RECOVERED 0x10
|
||||
|
||||
|
||||
/* 0x0C */
|
||||
typedef enum
|
||||
{
|
||||
WRITE_OP = 0,
|
||||
READ_OP = 1
|
||||
}DATA_OPERATION;
|
||||
|
||||
/* 0x0E */
|
||||
typedef enum
|
||||
{
|
||||
CMD_GO_IDLE_STATE = 0,
|
||||
CMD_ALL_SEND_CID = 2,
|
||||
CMD_SEND_RELATIVE_ADDR = 3,
|
||||
CMD_SET_DSR = 4,
|
||||
CMD_SWITCH_FUNC = 6,
|
||||
CMD_SELECT_DESELECT_CARD = 7,
|
||||
CMD_SEND_IF_COND = 8,
|
||||
CMD_SEND_CSD = 9,
|
||||
CMD_SEND_CID = 10,
|
||||
CMD_VOLTAGE_SWITCH = 11,
|
||||
CMD_STOP_TRANSMISSION = 12,
|
||||
CMD_SEND_STATUS = 13,
|
||||
CMD_GO_INACTIVE_STATE = 15,
|
||||
CMD_SET_BLOCKLEN = 16,
|
||||
CMD_READ_SINGLE_BLOCK = 17,
|
||||
CMD_READ_MULTIPLE_BLOCK = 18,
|
||||
CMD_SET_BLOCK_COUNT = 23,
|
||||
CMD_WRITE_BLOCK = 24,
|
||||
CMD_WRITE_MULTIPLE_BLOCK = 25,
|
||||
CMD_PROGRAM_CSD = 27,
|
||||
CMD_ERASE_WR_BLK_START = 32,
|
||||
CMD_ERASE_WR_BLK_END = 33,
|
||||
CMD_ERASE = 38,
|
||||
CMD_SD_SEND_OP_COND = 41,
|
||||
CMD_LOCK_UNLOCK = 42,
|
||||
CMD_SEND_SCR = 51,
|
||||
CMD_APP_CMD = 55
|
||||
}CMD_IDX;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
NORMAL, // 00b
|
||||
SUSPEND, // 01b
|
||||
RESUME, // 10b
|
||||
ABORT // 11b
|
||||
}CMD_TYPE;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
NO_DATA, // 00b
|
||||
WITH_DATA // 01b
|
||||
}DATA_PRESENT_SEL;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
NO_RSP, // 00b
|
||||
RSP_LEN_136, // 01b
|
||||
RSP_LEN_48, // 10b
|
||||
RSP_LEN_48_CHK_BUSY // 11b
|
||||
}RSP_TYPE;
|
||||
|
||||
/* 0x28 */
|
||||
typedef enum
|
||||
{
|
||||
SDMA, // 00b
|
||||
RESERVED, // 01b
|
||||
ADMA2_32BIT, // 10b
|
||||
ADMA2_64BIT // 11b
|
||||
}HOST_DMA_SELECT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
MODE_1_BIT = 0,
|
||||
MODE_4_BIT = 1
|
||||
}HOST_DATA_WIDTH;
|
||||
|
||||
/* 0x29 */
|
||||
typedef enum
|
||||
{
|
||||
VOLT_33V = 7,// 111b
|
||||
VOLT_30V = 6,// 110b
|
||||
VOLT_18V = 5 // 101b
|
||||
}HOST_SD_BUS_VOLT;
|
||||
|
||||
/* 0x2C */
|
||||
typedef enum
|
||||
{
|
||||
BASE_CLK = 0x00,
|
||||
BASE_CLK_DIVIDED_BY_2 = 0x01,
|
||||
BASE_CLK_DIVIDED_BY_4 = 0x02,
|
||||
BASE_CLK_DIVIDED_BY_8 = 0x04,
|
||||
BASE_CLK_DIVIDED_BY_16 = 0x08,
|
||||
BASE_CLK_DIVIDED_BY_32 = 0x10,
|
||||
BASE_CLK_DIVIDED_BY_64 = 0x20,
|
||||
BASE_CLK_DIVIDED_BY_128 = 0x40,
|
||||
BASE_CLK_DIVIDED_BY_256 = 0x80
|
||||
}SD_CLK_DIVISOR;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SD_CLK_162KHZ,
|
||||
SD_CLK_325KHZ,
|
||||
SD_CLK_650KHZ,
|
||||
SD_CLK_1_3MHZ,
|
||||
SD_CLK_2_6MHZ,
|
||||
SD_CLK_5_2MHZ,
|
||||
SD_CLK_10_4MHZ,
|
||||
SD_CLK_20_8MHZ,
|
||||
SD_CLK_41_6MHZ
|
||||
}SD_CLK_FREQUENCY;
|
||||
|
||||
/* Card Status Register */
|
||||
typedef enum
|
||||
{
|
||||
IDLE, // 0
|
||||
READY, // 1
|
||||
IDENTIFICATION, // 2
|
||||
STAND_BY, // 3
|
||||
TRANSFER, // 4
|
||||
SENDING_DATA, // 5
|
||||
RECEIVE_DATA, // 6
|
||||
PROGRAMMING, // 7
|
||||
DISCONNECT, // 8
|
||||
UNKNOWN = 0xFF
|
||||
}CURRENT_STATE;
|
||||
|
||||
/* OCR Register */
|
||||
typedef enum
|
||||
{
|
||||
VDD_27_28 = BIT15,
|
||||
VDD_28_29 = BIT16,
|
||||
VDD_29_30 = BIT17,
|
||||
VDD_30_31 = BIT18,
|
||||
VDD_31_32 = BIT19,
|
||||
VDD_32_33 = BIT20,
|
||||
VDD_33_34 = BIT21,
|
||||
VDD_34_35 = BIT22,
|
||||
VDD_35_36 = BIT23,
|
||||
CARD_CAPA_STATUS = BIT30,
|
||||
CARD_PWR_UP_STATUS = BIT31
|
||||
}OCR_VOLTAGE_PROFILE;
|
||||
|
||||
/* SCR Register */
|
||||
typedef enum
|
||||
{
|
||||
SD_VER_10 = 0,
|
||||
SD_VER_110 = 1,
|
||||
SD_VER_200 = 2
|
||||
}PHYSICAL_LAYER_SPEC_VER;
|
||||
|
||||
/* CSD Register */
|
||||
typedef enum
|
||||
{
|
||||
CLEAR_WRITE_PROTECT = 0,
|
||||
SET_WRITE_PROTECT = 1
|
||||
}TEMPORARY_WRITE_PROTECT_STATUS;
|
||||
|
||||
/* Switch Function (CMD6) Status Data Structure Version */
|
||||
typedef enum
|
||||
{
|
||||
BUSY_STATUS_UNDEFINED = 0, // bits [511:376] are defined
|
||||
BUSY_STATUS_DEFINED = 1 // bits [511:272] are defined
|
||||
}SWITCH_FN_STATUS_DATA_STRUCTURE_VER;
|
||||
|
||||
/* Switch Function (CMD6) Busy Status */
|
||||
typedef enum
|
||||
{
|
||||
READY_STATUS = 0,
|
||||
BUSY_STATUS = 1
|
||||
}SWITCH_FN_BUSY_STATUS;
|
||||
|
||||
/* Switch Function (CMD6) Mode */
|
||||
typedef enum
|
||||
{
|
||||
CHECK_FN = 0x0,
|
||||
SWITCH_FN = 0x1
|
||||
}SWITCH_FN_MODE;
|
||||
|
||||
/* Switch Function (CMD6) Group 1 */
|
||||
typedef enum
|
||||
{
|
||||
FN1_DEFAULT = 0x0,
|
||||
FN1_HIGH_SPEED = 0x1,
|
||||
FN1_KEEP_CURRENT = 0xF
|
||||
}SWITCH_FN_GROUP_1;
|
||||
|
||||
/* Switch Function (CMD6) Group 2 */
|
||||
typedef enum
|
||||
{
|
||||
FN2_DEFAULT = 0x0,
|
||||
FN2_FOR_EC = 0x1,
|
||||
FN2_VENDOR_SPECIFIC = 0xE,
|
||||
FN2_KEEP_CURRENT = 0xF
|
||||
}SWITCH_FN_GROUP_2;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DESEL_CARD = 0,
|
||||
SEL_CARD = 1
|
||||
}CARD_SELECTION;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SDSC_ONLY = 0,
|
||||
SDHC_SUPPORT = 1
|
||||
}HOST_CAPACITY_SUPPORT;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
BUS_1_BIT = 0,
|
||||
BUS_4_BIT = 2
|
||||
}DATA_BUS_WIDTH;
|
||||
|
||||
|
||||
typedef struct _ADMA2_ATTRIB_
|
||||
{
|
||||
u16 Valid:1;
|
||||
u16 End:1;
|
||||
u16 Int:1;
|
||||
u16 Rsvd1:1;
|
||||
u16 Act1:1;
|
||||
u16 Act2:1;
|
||||
u16 Rsvd2:10;
|
||||
}ADMA2_ATTRIB, *PADMA2_ATTRIB;
|
||||
|
||||
typedef struct _ADMA2_DESC_FMT_
|
||||
{
|
||||
ADMA2_ATTRIB Attrib1;
|
||||
u16 Len1;
|
||||
u32 Addr1;
|
||||
/* Link to next descriptor (if needed) */
|
||||
ADMA2_ATTRIB Attrib2;
|
||||
u16 Len2;
|
||||
u32 Addr2;
|
||||
}ADMA2_DESC_FMT, *PADMA2_DESC_FMT;
|
||||
|
||||
/* 0x0E */
|
||||
typedef struct _SDIO_HOST_CMD_FMT_
|
||||
{
|
||||
u16 RespType:2;
|
||||
u16 Rsvd0:1;
|
||||
u16 CmdCrcChkEn:1;
|
||||
u16 CmdIdxChkEn:1;
|
||||
u16 DataPresent:1;
|
||||
u16 CmdType:2;
|
||||
u16 CmdIdx:6;
|
||||
u16 Rsvd1:2;
|
||||
}SDIO_HOST_CMD_FMT, *PSDIO_HOST_CMD_FMT;
|
||||
|
||||
typedef struct _SDIO_HOST_CMD_
|
||||
{
|
||||
SDIO_HOST_CMD_FMT CmdFmt;
|
||||
u32 Arg;
|
||||
}SDIO_HOST_CMD, *PSDIO_HOST_CMD;
|
||||
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostInitHostRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostInitCardRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostDeInitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostEnableRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostDisableRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostIrqInitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostReadBlocksDmaRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u64 ReadAddr,
|
||||
IN u32 BlockCnt
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostWriteBlocksDmaRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u64 WriteAddr,
|
||||
IN u32 BlockCnt
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostStopTransferRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostGetCardStatusRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostGetSdStatusRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostChangeSdClockRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 Frequency
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostEraseRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u64 StartAddr,
|
||||
IN u64 EndAddr
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostGetWriteProtectRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalSdioHostSetWriteProtectRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 Setting
|
||||
);
|
||||
|
||||
|
||||
#ifdef CONFIG_SDIO_HOST_VERIFY
|
||||
|
||||
#define HAL_MMC_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
|
||||
#define HAL_MMC_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
|
||||
#define HAL_MMC_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
|
||||
#define HAL_MMC_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
|
||||
#define HAL_MMC_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
|
||||
#define HAL_MMC_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
|
||||
|
||||
/* RTL8195A Register */
|
||||
// REG_SOC_HCI_COM_FUNC_EN (0x214)
|
||||
#define SD_DEVICE_IP_ON_BLK BIT0
|
||||
#define SD_DEVICE_IP_OFF_BLK BIT1
|
||||
#define SD_HOST_IP_BLK BIT2
|
||||
|
||||
// REG_PESOC_HCI_CLK_CTRL0 (0x240)
|
||||
#define SD_HOST_CLKEN_IN_CPU_RUN_MODE BIT2
|
||||
|
||||
// REG_HCI_PINMUX_CTRL (0x2A0)
|
||||
#define SD_DEVICE_MODE_PINMUX_EN BIT0
|
||||
#define SD_HOST_MODE_PINMUX_EN BIT1
|
||||
|
||||
// 0x40059000
|
||||
#define SD_HOST_CARD_DETECT_CIRCUIT BIT10
|
||||
|
||||
|
||||
|
||||
/* SD Host Register */
|
||||
#define REG_SDMA_SYS_ADDR_ARG 0x00 // 4byte
|
||||
#define REG_BLOCK_SIZE 0x04 // 2byte
|
||||
#define REG_BLOCK_COUNT 0x06 // 2byte
|
||||
#define REG_ARGUMENT1 0x08 // 4byte
|
||||
#define REG_TRANSFER_MODE 0x0C // 2byte
|
||||
#define REG_COMMAND 0x0E // 2byte
|
||||
#define REG_RESPONSE0 0x10 // 4byte
|
||||
#define REG_RESPONSE2 0x14 // 4byte
|
||||
#define REG_RESPONSE4 0x18 // 4byte
|
||||
#define REG_RESPONSE6 0x1C // 4byte
|
||||
#define REG_BUFFER_DATA_PORT 0x20 // 4byte
|
||||
#define REG_PRESENT_STATE 0x24 // 4byte
|
||||
#define REG_HOST_CONTROL1 0x28 // 1byte
|
||||
#define REG_POWER_CONTROL 0x29 // 1byte
|
||||
#define REG_BLOCK_GAP_CONTROL 0x2A // 1byte
|
||||
#define REG_WAKEUP_CONTROL 0x2B // 1byte
|
||||
#define REG_CLOCK_CONTROL 0x2C // 2byte
|
||||
#define REG_TIMEOUT_CONTROL 0x2E // 1byte
|
||||
#define REG_SW_RESET 0x2F // 1byte
|
||||
#define REG_NORMAL_INT_STATUS 0x30 // 2byte
|
||||
#define REG_ERROR_INT_STATUS 0x32 // 2byte
|
||||
#define REG_NORMAL_INT_STATUS_ENABLE 0x34 // 2byte
|
||||
#define REG_ERROR_INT_STATUS_ENABLE 0x36 // 2byte
|
||||
#define REG_NORMAL_INT_SIGNAL_ENABLE 0x38 // 2byte
|
||||
#define REG_ERROR_INT_SIGNAL_ENABLE 0x3A // 2byte
|
||||
#define REG_CAPABILITIES 0x40 // 8byte
|
||||
#define REG_ADMA_ADDRESS 0x58 // 8byte
|
||||
|
||||
// Transfer Mode (0x0C)
|
||||
#define BIT_DMA_EN BIT0
|
||||
#define BIT_BLK_CNT_EN BIT1
|
||||
#define BIT_AUTO_CMD12_EN BIT2
|
||||
#define BIT_AUTO_CMD23_EN BIT3
|
||||
#define BIT_READ_TRANS BIT4
|
||||
#define BIT_MULTI_BLK BIT5
|
||||
|
||||
// Present State (0x24)
|
||||
#define BIT_CMD_INHIBIT_CMD BIT0
|
||||
#define BIT_CMD_INHIBIT_DAT BIT1
|
||||
#define BIT_CARD_INSERTED BIT16
|
||||
#define BIT_WRITE_PROTECT_SWITCH_PIN BIT19
|
||||
|
||||
// Power Control (0x29)
|
||||
#define BIT_POWER_33 0xE
|
||||
#define BIT_POWER_30 0xC
|
||||
#define BIT_POWER_18 0xA
|
||||
|
||||
// Clock Control (0x2C)
|
||||
#define BIT_INTERNAL_CLK_EN BIT0
|
||||
#define BIT_INTERNAL_CLK_STABLE BIT1
|
||||
#define BIT_SD_CLK_EN BIT2
|
||||
|
||||
// Software Reset (0x2F)
|
||||
#define BIT_SW_RESET_ALL BIT0
|
||||
#define BIT_SW_RESET_CMD_LINE BIT1
|
||||
#define BIT_SW_RESET_DAT_LINE BIT2
|
||||
|
||||
// Norma Interrupt Status (0x30)
|
||||
#define BIT_COMMAND_COMPLETE BIT0
|
||||
#define BIT_TRANSFER_COMPLETE BIT1
|
||||
#define BIT_BLOCK_GAP_EVENT BIT2
|
||||
#define BIT_DMA_INT BIT3
|
||||
#define BIT_BUFFER_WRITE_RDY BIT4
|
||||
#define BIT_BUFFER_READ_RDY BIT5
|
||||
#define BIT_CARD_INSERTION BIT6
|
||||
#define BIT_CARD_REMOVAL BIT7
|
||||
#define BIT_CARD_INT BIT8
|
||||
#define BIT_ERROR_INT BIT15
|
||||
|
||||
// Error Interrupt Status (0x32)
|
||||
#define BIT_DATA_TIME_OUT_ERROR BIT4
|
||||
#define BIT_DATA_CRC_ERROR BIT5
|
||||
#define BIT_ADMA_ERROR BIT9
|
||||
|
||||
// Capabilities (0x40)
|
||||
#define BIT_VDD_33 BIT24
|
||||
#define BIT_VDD_30 BIT25
|
||||
#define BIT_VDD_18 BIT26
|
||||
|
||||
|
||||
#define ENABLE 1
|
||||
#define DISABLE 0
|
||||
|
||||
#define ADMA_DESC_NUM 50
|
||||
|
||||
#define BUFFER_UNIT_SIZE 512
|
||||
|
||||
typedef enum _MMC_HOST_TEST_FUNC_ {
|
||||
MMC_HOST_TEST_HW_INIT, // 0
|
||||
MMC_HOST_TEST_CARD_INIT, // 1
|
||||
MMC_HOST_TEST_SEND_CMD, // 2
|
||||
MMC_HOST_TEST_DEBUG, // 3
|
||||
MMC_HOST_TEST_SW_RESET, // 4
|
||||
MMC_HOST_TEST_READ_SINGLE, // 5
|
||||
MMC_HOST_TEST_WRITE_SINGLE, // 6
|
||||
MMC_HOST_TEST_READ_MULTI, // 7
|
||||
MMC_HOST_TEST_WRITE_MULTI, // 8
|
||||
MMC_HOST_TEST_SINGLE_LONGRUN, // 9
|
||||
MMC_HOST_TEST_MULTI_LONGRUN, // 10
|
||||
MMC_HOST_TEST_CARD_DETECTION, // 11
|
||||
MMC_HOST_TEST_WRITE_PROTECT, // 12
|
||||
MMC_HOST_TEST_REGISTER_RW, // 13
|
||||
SD_HOST_HAL_API_VERIFY = 20,
|
||||
SD_HOST_ERASE_TEST = 21,
|
||||
SD_HOST_WP_TEST = 22,
|
||||
SD_HOST_MB_TEST = 23,
|
||||
SD_HOST_ADMA_MAX_TEST = 24
|
||||
}MMC_HOST_TEST_FUNC;
|
||||
|
||||
typedef enum _RESPONSE_TYPE_ {
|
||||
No_Response, // 00b
|
||||
Response_136, // 01b
|
||||
Response_48, // 10b
|
||||
Response_48_Busy // 11b
|
||||
}RESPONSE_TYPE;
|
||||
|
||||
typedef enum _COMMAND_TYPE_ {
|
||||
Normal, // 00b
|
||||
Suspend, // 01b
|
||||
Resume, // 10b
|
||||
Abort // 11b
|
||||
}COMMAND_TYPE;
|
||||
|
||||
typedef enum _DATA_PRESENT_ {
|
||||
No_Data_Present, // 00b
|
||||
Data_Present, // 01b
|
||||
}DATA_PRESENT;
|
||||
|
||||
typedef enum _SUPPLY_VOLTAGE_ {
|
||||
MMC_VDD_27_28 = BIT15,
|
||||
MMC_VDD_28_29 = BIT16,
|
||||
MMC_VDD_29_30 = BIT17,
|
||||
MMC_VDD_30_31 = BIT18,
|
||||
MMC_VDD_31_32 = BIT19,
|
||||
MMC_VDD_32_33 = BIT20,
|
||||
MMC_VDD_33_34 = BIT21,
|
||||
MMC_VDD_34_35 = BIT22,
|
||||
MMC_VDD_35_36 = BIT23,
|
||||
}SUPPLY_VOLTAGE;
|
||||
|
||||
typedef enum _COMMAND_INDEX_ {
|
||||
GO_IDLE_STATE = 0,
|
||||
ALL_SEND_CID = 2,
|
||||
SEND_RELATIVE_ADDR = 3,
|
||||
SET_BUS_WIDTH = 6,
|
||||
SELECT_CARD = 7,
|
||||
SEND_IF_COND = 8,
|
||||
SEND_CSD = 9,
|
||||
STOP_TRANSMISSION = 12,
|
||||
SEND_STATUS = 13,
|
||||
READ_SINGLE_BLOCK = 17,
|
||||
READ_MULTIPLE_BLOCK = 18,
|
||||
WRITE_BLOCK = 24,
|
||||
WRITE_MULTIPLE_BLOCK = 25,
|
||||
SD_SEND_OP_COND = 41,
|
||||
APP_CMD = 55,
|
||||
}COMMAND_INDEX;
|
||||
|
||||
typedef enum _TRANSFER_CONFIG_ {
|
||||
Read_Data = 0,
|
||||
Write_Data = 1,
|
||||
Single_Block = 0,
|
||||
Multiple_Block = 1,
|
||||
}TRANSFER_CONFIG;
|
||||
|
||||
typedef enum _ERROR_STATUS_ {
|
||||
General_Error, // 0
|
||||
CRC_Error, // 1
|
||||
TIME_OUT_ERROR, // 2
|
||||
CRC_Error_NeedCMD12, // 3
|
||||
Transfer_OK // 4
|
||||
}ERROR_STATUS;
|
||||
|
||||
typedef enum _CARD_CURRENT_STATE_ {
|
||||
IDLE_STATE,
|
||||
READY_STATE,
|
||||
IDENT_STATE,
|
||||
STBY_STATE,
|
||||
TRAN_STATE,
|
||||
DATA_STATE,
|
||||
RCV_STATE,
|
||||
PRG_STATE,
|
||||
DIS_STATE,
|
||||
UNKNOWN_STATE
|
||||
}CARD_CURRENT_STATE;
|
||||
|
||||
typedef struct _COMMAND_FORMAT_
|
||||
{
|
||||
u16 Resp_Type:2;
|
||||
u16 Rsvd0:1;
|
||||
u16 CMD_CRC_Chk:1;
|
||||
u16 CMD_Idx_Chk:1;
|
||||
u16 Data_Present:1;
|
||||
u16 CMD_Type:2;
|
||||
u16 CMD_Idx:6;
|
||||
u16 Rsvd1:2;
|
||||
}COMMAND_FORMAT, *PCOMMAND_FPRMAT;
|
||||
|
||||
typedef struct _MMC_COMMAND
|
||||
{
|
||||
COMMAND_FORMAT Cmd_Format;
|
||||
u32 Arg;
|
||||
}MMC_COMMAND;
|
||||
|
||||
typedef struct _MMC_HOST_
|
||||
{
|
||||
u32 OCR_Avail;
|
||||
u32 Resp[4];
|
||||
u32 CID[4];
|
||||
u32 RCA;
|
||||
}MMC_HOST, *PMMC_HOST;
|
||||
|
||||
typedef struct _ADMA_ATTR_
|
||||
{
|
||||
u16 Valid:1;
|
||||
u16 End:1;
|
||||
u16 Int:1;
|
||||
u16 Rsvd1:1;
|
||||
u16 Act1:1;
|
||||
u16 Act2:1;
|
||||
u16 Rsvd2:10;
|
||||
}ADMA_ATTR, *PADMA_ATTR;
|
||||
// 24 bytes
|
||||
typedef struct _ADMA_DESC_TABLE_
|
||||
{
|
||||
// 1st buffer desc
|
||||
ADMA_ATTR Attribute1;
|
||||
u16 Length1;
|
||||
u32 Address1;
|
||||
// 2nd buffer desc
|
||||
ADMA_ATTR Attribute2;
|
||||
u16 Length2;
|
||||
u32 Address2;
|
||||
// 3rd buffer desc
|
||||
ADMA_ATTR Attribute3;
|
||||
u16 Length3;
|
||||
u32 Address3;
|
||||
}ADMA_DESC_TABLE, *PADMA_DESC_TABLE;
|
||||
// 1024 bytes
|
||||
typedef struct _ADMA_BUFFER_
|
||||
{
|
||||
u8 Data1[512]; /* 1st buffer */
|
||||
u8 Data2[512]; /* 2nd buffer */
|
||||
}ADMA_BUFFER, *PADMA_BUFFER;
|
||||
|
||||
|
||||
VOID
|
||||
SdHostTestApp(
|
||||
IN u8 *argv[]
|
||||
);
|
||||
#endif // end of "#ifdef CONFIG_SDIO_HOST_VERIFY"
|
||||
|
||||
#endif /* #ifndef _RTL8195A_SDIO_HOST_H_ */
|
||||
|
|
@ -0,0 +1,379 @@
|
|||
#ifndef _RTL8195A_SDR_H
|
||||
#define _RTL8195A_SDR_H
|
||||
|
||||
#define MS_0_CTRL_BASE BSP_MS_I_DRAMC_0_BASE
|
||||
#define MS_0_CTRL_PHY_BASE (BSP_MS_I_DRAMC_0_BASE)
|
||||
#define MS_0_WRAP_BASE (MS_0_CTRL_BASE + 0x200)
|
||||
|
||||
#define MS_1_CTRL_BASE BSP_MS_I_DRAMC_1_BASE
|
||||
#define MS_1_CTRL_PHY_BASE (BSP_MS_I_DRAMC_1_BASE)
|
||||
#define MS_1_WRAP_BASE (MS_1_CTRL_BASE + 0x200)
|
||||
|
||||
#define MS_PCTL_CCR_OFFSET 0x000
|
||||
#define MS_PCTL_DCR_OFFSET 0x004
|
||||
#define MS_PCTL_IOCR_OFFSET 0x008
|
||||
#define MS_PCTL_CSR_OFFSET 0x00c
|
||||
#define MS_PCTL_DRR_OFFSET 0x010
|
||||
#define MS_PCTL_TPR0_OFFSET 0x014
|
||||
#define MS_PCTL_TPR1_OFFSET 0x018
|
||||
#define MS_PCTL_TPR2_OFFSET 0x01c
|
||||
#define MS_PCTL_MR_OFFSET 0x020
|
||||
#define MS_PCTL_EMR1_OFFSET 0x024
|
||||
#define MS_PCTL_EMR2_OFFSET 0x028
|
||||
#define MS_PCTL_EMR3_OFFSET 0x02c
|
||||
#define MS_PCTL_CSR2_OFFSET 0x030
|
||||
#define MS_PCTL_SRST_OFFSET 0x034
|
||||
#define MS_PCTL_DTR2_OFFSET 0x038
|
||||
#define MS_PCTL_DTR3_OFFSET 0x03c
|
||||
#define MS_PCTL_GDLLCR_OFFSET 0x040
|
||||
#define MS_PCTL_DLLCR0_OFFSET 0x044
|
||||
#define MS_PCTL_DLLCR1_OFFSET 0x048
|
||||
#define MS_PCTL_DLLCR2_OFFSET 0x04c
|
||||
#define MS_PCTL_DLLCR3_OFFSET 0x050
|
||||
#define MS_PCTL_DLLCR4_OFFSET 0x054
|
||||
#define MS_PCTL_DLLCR5_OFFSET 0x058
|
||||
#define MS_PCTL_DLLCR6_OFFSET 0x05c
|
||||
#define MS_PCTL_DLLCR7_OFFSET 0x060
|
||||
#define MS_PCTL_DLLCR8_OFFSET 0x064
|
||||
#define MS_PCTL_DQTR0_OFFSET 0x068
|
||||
#define MS_PCTL_DQTR1_OFFSET 0x06c
|
||||
#define MS_PCTL_DQTR2_OFFSET 0x070
|
||||
#define MS_PCTL_DQTR3_OFFSET 0x074
|
||||
#define MS_PCTL_DQTR4_OFFSET 0x078
|
||||
#define MS_PCTL_DQTR5_OFFSET 0x07c
|
||||
#define MS_PCTL_DQTR6_OFFSET 0x080
|
||||
#define MS_PCTL_DQTR7_OFFSET 0x084
|
||||
#define MS_PCTL_DQSTR_OFFSET 0x088
|
||||
#define MS_PCTL_DQSBTR_OFFSET 0x08c
|
||||
#define MS_PCTL_ODTCR_OFFSET 0x090
|
||||
#define MS_PCTL_DTR0_OFFSET 0x094
|
||||
#define MS_PCTL_DTR1_OFFSET 0x098
|
||||
#define MS_PCTL_DTAR_OFFSET 0x09c
|
||||
#define MS_PCTL_ZQCR0_OFFSET 0x0a0
|
||||
#define MS_PCTL_ZQCR1_OFFSET 0x0a4
|
||||
#define MS_PCTL_ZQSR_OFFSET 0x0a8
|
||||
#define MS_PCTL_RSLR0_OFFSET 0x0ac
|
||||
#define MS_PCTL_RSLR1_OFFSET 0x0b0
|
||||
#define MS_PCTL_RSLR2_OFFSET 0x0b4
|
||||
#define MS_PCTL_RSLR3_OFFSET 0x0b8
|
||||
#define MS_PCTL_RDGR0_OFFSET 0x0bc
|
||||
#define MS_PCTL_RDGR1_OFFSET 0x0c0
|
||||
#define MS_PCTL_RDGR2_OFFSET 0x0c4
|
||||
#define MS_PCTL_RDGR3_OFFSET 0x0c8
|
||||
#define MS_PCTL_MXSL_OFFSET 0x0cc
|
||||
|
||||
#define MS_PCTL_BCR_OFFSET 0x0d0
|
||||
#define MS_PCTL_BALR0_OFFSET 0x0d4
|
||||
#define MS_PCTL_BALR1_OFFSET 0x0d8
|
||||
#define MS_PCTL_BDR0_OFFSET 0x0dc
|
||||
#define MS_PCTL_BDR1_OFFSET 0x0e0
|
||||
#define MS_PCTL_BBR_OFFSET 0x0e4
|
||||
#define MS_PCTL_BSR_OFFSET 0x0e8
|
||||
#define MS_PCTL_BYR_OFFSET 0x0ec
|
||||
#define MS_PCTL_BFA_OFFSET 0x0f0
|
||||
#define MS_PCTL_IDR_OFFSET 0x0f8
|
||||
#define MS_PCTL_ERR_OFFSET 0x0fc
|
||||
|
||||
#define MS_WRAP_SCR_OFFSET 0x224
|
||||
#define MS_WRAP_QCR_OFFSET 0x230
|
||||
#define MS_WRAP_PCR_OFFSET 0x234
|
||||
#define MS_WRAP_QTR0_OFFSET 0x240
|
||||
#define MS_WRAP_QTR1_OFFSET 0x244
|
||||
#define MS_WRAP_QTR2_OFFSET 0x248
|
||||
#define MS_WRAP_QTR3_OFFSET 0x24c
|
||||
#define MS_WRAP_QTR4_OFFSET 0x250
|
||||
#define MS_WRAP_QTR5_OFFSET 0x254
|
||||
#define MS_WRAP_QTR6_OFFSET 0x258
|
||||
#define MS_WRAP_QTR7_OFFSET 0x25c
|
||||
#define MS_WRAP_QTR8_OFFSET 0x260
|
||||
#define MS_WRAP_QTR9_OFFSET 0x264
|
||||
#define MS_WRAP_QTR10_OFFSET 0x268
|
||||
#define MS_WRAP_QTR11_OFFSET 0x26c
|
||||
#define MS_WRAP_QTR12_OFFSET 0x270
|
||||
#define MS_WRAP_QTR13_OFFSET 0x274
|
||||
#define MS_WRAP_QTR14_OFFSET 0x278
|
||||
#define MS_WRAP_QTR15_OFFSET 0x27c
|
||||
|
||||
#define MS_PHY_DLY0 0x100
|
||||
#define MS_PHY_DLY1_RST 0x104
|
||||
#define MS_PHY_DLY_CLK 0x108
|
||||
#define MS_PHY_DLY_ST 0x10c
|
||||
#define MS_PHY_DLY_NUM 0x100
|
||||
|
||||
#define PCTL_CCR_INIT_BFO 0
|
||||
#define PCTL_CCR_INIT_BFW 1
|
||||
#define PCTL_CCR_DTT_BFO 1
|
||||
#define PCTL_CCR_DTT_BFW 1
|
||||
#define PCTL_CCR_BTT_BFO 2
|
||||
#define PCTL_CCR_BTT_BFW 1
|
||||
#define PCTL_CCR_DPIT_BFO 3
|
||||
#define PCTL_CCR_DPIT_BFW 1
|
||||
#define PCTL_CCR_FLUSH_FIFO_BFO 8
|
||||
#define PCTL_CCR_FLUSH_FIFO_BFW 1
|
||||
|
||||
#define PCTL_DCR_DDR3_BFO 0
|
||||
#define PCTL_DCR_DDR3_BFW 1
|
||||
#define PCTL_DCR_SDR_BFO 1
|
||||
#define PCTL_DCR_SDR_BFW 1
|
||||
#define PCTL_DCR_DQ32_BFO 4
|
||||
#define PCTL_DCR_DQ32_BFW 1
|
||||
#define PCTL_DCR_DFI_RATE_BFO 8
|
||||
#define PCTL_DCR_DFI_RATE_BFW 3
|
||||
|
||||
#define PCTL_IOCR_RD_PIPE_BFO 8
|
||||
#define PCTL_IOCR_RD_PIPE_BFW 4
|
||||
#define PCTL_IOCR_TPHY_WD_BFO 12
|
||||
#define PCTL_IOCR_TPHY_WD_BFW 5
|
||||
#define PCTL_IOCR_TPHY_WL_BFO 17
|
||||
#define PCTL_IOCR_TPHY_WL_BFW 3
|
||||
#define PCTL_IOCR_TPHY_RD_EN_BFO 20
|
||||
#define PCTL_IOCR_TPHY_RD_EN_BFW 5
|
||||
|
||||
#define PCTL_CSR_MEM_IDLE_BFO 8
|
||||
#define PCTL_CSR_MEM_IDLE_BFW 1
|
||||
#define PCTL_CSR_DT_IDLE_BFO 9
|
||||
#define PCTL_CSR_DT_IDLE_BFW 1
|
||||
#define PCTL_CSR_BIST_IDLE_BFO 10
|
||||
#define PCTL_CSR_BIST_IDLE_BFW 1
|
||||
#define PCTL_CSR_DT_FAIL_BFO 11
|
||||
#define PCTL_CSR_DT_FAIL_BFW 1
|
||||
#define PCTL_CSR_BT_FAIL_BFO 12
|
||||
#define PCTL_CSR_BT_FAIL_BFW 1
|
||||
|
||||
#define PCTL_DRR_TRFC_BFO 0
|
||||
#define PCTL_DRR_TRFC_BFW 7
|
||||
#define PCTL_DRR_TREF_BFO 8
|
||||
#define PCTL_DRR_TREF_BFW 24
|
||||
#define PCTL_DRR_REF_NUM_BFO 24
|
||||
#define PCTL_DRR_REF_NUM_BFW 4
|
||||
#define PCTL_DRR_REF_DIS_BFO 28
|
||||
#define PCTL_DRR_REF_DIS_BFW 1
|
||||
|
||||
#define PCTL_TPR0_TRP_BFO 0
|
||||
#define PCTL_TPR0_TRP_BFW 4
|
||||
#define PCTL_TPR0_TRAS_BFO 4
|
||||
#define PCTL_TPR0_TRAS_BFW 5
|
||||
#define PCTL_TPR0_TWR_BFO 9
|
||||
#define PCTL_TPR0_TWR_BFW 4
|
||||
#define PCTL_TPR0_TRTP_BFO 13
|
||||
#define PCTL_TPR0_TRTP_BFW 3
|
||||
|
||||
#define PCTL_TPR1_TRRD_BFO 0
|
||||
#define PCTL_TPR1_TRRD_BFW 4
|
||||
#define PCTL_TPR1_TRC_BFO 4
|
||||
#define PCTL_TPR1_TRC_BFW 6
|
||||
#define PCTL_TPR1_TRCD_BFO 10
|
||||
#define PCTL_TPR1_TRCD_BFW 4
|
||||
#define PCTL_TPR1_TCCD_BFO 14
|
||||
#define PCTL_TPR1_TCCD_BFW 3
|
||||
#define PCTL_TPR1_TWTR_BFO 17
|
||||
#define PCTL_TPR1_TWTR_BFW 3
|
||||
#define PCTL_TPR1_TRTW_BFO 20
|
||||
#define PCTL_TPR1_TRTW_BFW 4
|
||||
|
||||
#define PCTL_TPR2_INIT_REF_NUM_BFO 0
|
||||
#define PCTL_TPR2_INIT_REF_NUM_BFW 4
|
||||
#define PCTL_TPR2_INIT_NS_EN_BFO 4
|
||||
#define PCTL_TPR2_INIT_NS_EN_BFW 1
|
||||
#define PCTL_TPR2_TMRD_BFO 5
|
||||
#define PCTL_TPR2_TMRD_BFW 2
|
||||
|
||||
#define PCTL_MR_BL_BFO 0
|
||||
#define PCTL_MR_BL_BFW 3
|
||||
#define PCTL_MR_BT_BFO 3
|
||||
#define PCTL_MR_BT_BFW 1
|
||||
#define PCTL_MR_CAS_BFO 4
|
||||
#define PCTL_MR_CAS_BFW 3
|
||||
#define PCTL_MR_OP_BFO 8
|
||||
#define PCTL_MR_OP_BFW 12
|
||||
|
||||
#define PCTL_EMR1_ADDLAT_BFO 3
|
||||
#define PCTL_EMR1_ADDLAT_BFW 3
|
||||
|
||||
#define PCTL_CMD_DPIN_RSTN_BFO 0
|
||||
#define PCTL_CMD_DPIN_RSTN_BFW 1
|
||||
#define PCTL_CMD_DPIN_CKE_BFO 1
|
||||
#define PCTL_CMD_DPIN_CKE_BFW 1
|
||||
#define PCTL_CMD_DPIN_ODT_BFO 2
|
||||
#define PCTL_CMD_DPIN_ODT_BFW 1
|
||||
|
||||
#define PCTL_BCR_STOP_BFO 0
|
||||
#define PCTL_BCR_STOP_BFW 1
|
||||
#define PCTL_BCR_CMP_BFO 1
|
||||
#define PCTL_BCR_CMP_BFW 1
|
||||
#define PCTL_BCR_LOOP_BFO 2
|
||||
#define PCTL_BCR_LOOP_BFW 1
|
||||
#define PCTL_BCR_DIS_MASK_BFO 3
|
||||
#define PCTL_BCR_DIS_MASK_BFW 1
|
||||
#define PCTL_BCR_AT_STOP_BFO 4
|
||||
#define PCTL_BCR_AT_STOP_BFW 1
|
||||
#define PCTL_BCR_FLUSH_CMD_BFO 8
|
||||
#define PCTL_BCR_FLUSH_CMD_BFW 1
|
||||
#define PCTL_BCR_FLUSH_WD_BFO 9
|
||||
#define PCTL_BCR_FLUSH_WD_BFW 1
|
||||
#define PCTL_BCR_FLUSH_RGD_BFO 10
|
||||
#define PCTL_BCR_FLUSH_RGD_BFW 1
|
||||
#define PCTL_BCR_FLUSH_RD_BFO 11
|
||||
#define PCTL_BCR_FLUSH_RD_BFW 1
|
||||
#define PCTL_BCR_FLUSH_RD_EXPC_BFO 16
|
||||
#define PCTL_BCR_FLUSH_RD_EXPC_BFW 14
|
||||
|
||||
#define PCTL_BST_ERR_FST_TH_BFO 0
|
||||
#define PCTL_BST_ERR_FST_TH_BFW 12
|
||||
#define PCTL_BST_ERR_CNT_BFO 16
|
||||
#define PCTL_BST_ERR_CNT_BFW 14
|
||||
|
||||
#define PCTL_BSRAM0_CMD_LEVEL_BFO 0
|
||||
#define PCTL_BSRAM0_CMD_LEVEL_BFW 12
|
||||
#define PCTL_BSRAM0_WD_LEVEL_BFO 16
|
||||
#define PCTL_BSRAM0_WD_LEVEL_BFW 14
|
||||
|
||||
#define PCTL_BSRAM1_RG_LEVEL_BFO 0
|
||||
#define PCTL_BSRAM1_RG_LEVEL_BFW 14
|
||||
#define PCTL_BSRAM1_RD_LEVEL_BFO 16
|
||||
#define PCTL_BSRAM1_RD_LEVEL_BFW 14
|
||||
|
||||
#define WRAP_MISC_PAGE_SIZE_BFO 0
|
||||
#define WRAP_MISC_PAGE_SIZE_BFW 4
|
||||
#define WRAP_MISC_BANK_SIZE_BFO 4
|
||||
#define WRAP_MISC_BANK_SIZE_BFW 2
|
||||
#define WRAP_MISC_BST_SIZE_BFO 6
|
||||
#define WRAP_MISC_BST_SIZE_BFW 2
|
||||
#define WRAP_MISC_DDR_PARAL_BFO 8
|
||||
#define WRAP_MISC_DDR_PARAL_BFW 1
|
||||
|
||||
struct ms_rxi310_portmap {
|
||||
volatile unsigned int ccr; /* 0x000 */
|
||||
volatile unsigned int dcr; /* 0x004 */
|
||||
volatile unsigned int iocr; /* 0x008 */
|
||||
volatile unsigned int csr; /* 0x00c */
|
||||
volatile unsigned int drr; /* 0x010 */
|
||||
volatile unsigned int tpr0; /* 0x014 */
|
||||
volatile unsigned int tpr1; /* 0x018 */
|
||||
volatile unsigned int tpr2; /* 0x01c */
|
||||
volatile unsigned int mr; /* 0x020 */
|
||||
volatile unsigned int emr1; /* 0x024 */
|
||||
volatile unsigned int emr2; /* 0x028 */
|
||||
volatile unsigned int emr3; /* 0x02c */
|
||||
volatile unsigned int cdpin; /* 0x030 */
|
||||
volatile unsigned int tdpin; /* 0x034 */
|
||||
volatile unsigned int dtr2; /* 0x038 */
|
||||
volatile unsigned int dtr3; /* 0x03c */
|
||||
volatile unsigned int gdllcr; /* 0x040 */
|
||||
volatile unsigned int dllcr0; /* 0x044 */
|
||||
volatile unsigned int dllcr1; /* 0x048 */
|
||||
volatile unsigned int dllcr2; /* 0x04c */
|
||||
volatile unsigned int dllcr3; /* 0x050 */
|
||||
volatile unsigned int dllcr4; /* 0x054 */
|
||||
volatile unsigned int dllcr5; /* 0x058 */
|
||||
volatile unsigned int dllcr6; /* 0x05c */
|
||||
volatile unsigned int dllcr7; /* 0x060 */
|
||||
volatile unsigned int dllcr8; /* 0x064 */
|
||||
volatile unsigned int dqtr0; /* 0x068 */
|
||||
volatile unsigned int dqtr1; /* 0x06c */
|
||||
volatile unsigned int dqtr2; /* 0x070 */
|
||||
volatile unsigned int dqtr3; /* 0x074 */
|
||||
volatile unsigned int dqtr4; /* 0x078 */
|
||||
volatile unsigned int dqtr5; /* 0x07c */
|
||||
volatile unsigned int dqtr6; /* 0x080 */
|
||||
volatile unsigned int dqtr7; /* 0x084 */
|
||||
volatile unsigned int dqstr; /* 0x088 */
|
||||
volatile unsigned int dqsbtr; /* 0x08c */
|
||||
volatile unsigned int odtcr; /* 0x090 */
|
||||
volatile unsigned int dtr0; /* 0x094 */
|
||||
volatile unsigned int dtr1; /* 0x098 */
|
||||
volatile unsigned int dtar; /* 0x09c */
|
||||
volatile unsigned int zqcr0; /* 0x0a0 */
|
||||
volatile unsigned int zqcr1; /* 0x0a4 */
|
||||
volatile unsigned int zqsr; /* 0x0a8 */
|
||||
volatile unsigned int rslr0; /* 0x0ac */
|
||||
volatile unsigned int rslr1; /* 0x0b0 */
|
||||
volatile unsigned int rslr2; /* 0x0b4 */
|
||||
volatile unsigned int rslr3; /* 0x0b8 */
|
||||
volatile unsigned int rdgr0; /* 0x0bc */
|
||||
volatile unsigned int rdgr1; /* 0x0c0 */
|
||||
volatile unsigned int rdgr2; /* 0x0c4 */
|
||||
volatile unsigned int rdgr3; /* 0x0c8 */
|
||||
volatile unsigned int mxsl; /* 0x0cc */
|
||||
volatile unsigned int bcr; /* 0x0d0 */
|
||||
volatile unsigned int bst; /* 0x0d4 */
|
||||
volatile unsigned int bsram0; /* 0x0d8 */
|
||||
volatile unsigned int bsram1; /* 0x0dc */
|
||||
volatile unsigned int bdr1; /* 0x0e0 */
|
||||
volatile unsigned int bbr; /* 0x0e4 */
|
||||
volatile unsigned int bsr; /* 0x0e8 */
|
||||
volatile unsigned int byr; /* 0x0ec */
|
||||
volatile unsigned int bfa; /* 0x0f0 */
|
||||
volatile unsigned int pctl_svn; /* 0x0f4 */
|
||||
volatile unsigned int pctl_idr; /* 0x0f8 */
|
||||
volatile unsigned int err; /* 0x0fc */
|
||||
|
||||
// SDR_PHY CONTROL REGISTER
|
||||
volatile unsigned int phy_dly0; /* 0x100 */
|
||||
volatile unsigned int phy_dly1_rst; /* 0x104 */
|
||||
volatile unsigned int phy_dly_clk; /* 0x108 */
|
||||
volatile unsigned int phy_dly_st; /* 0x10c */
|
||||
volatile unsigned int phy_dly_num; /* 0x110 */
|
||||
volatile unsigned int reserved0[68];
|
||||
|
||||
// WRAP CONTROL REGISTER
|
||||
volatile unsigned int misc; /* 0x224 */
|
||||
volatile unsigned int cq_ver; /* 0x228 */
|
||||
volatile unsigned int cq_mon; /* 0x22c */
|
||||
volatile unsigned int wq_ver; /* 0x230 */
|
||||
volatile unsigned int wq_mon; /* 0x234 */
|
||||
volatile unsigned int rq_ver; /* 0x240 */
|
||||
volatile unsigned int rq_mon; /* 0x244 */
|
||||
volatile unsigned int reserved1[22];
|
||||
volatile unsigned int wwrap_idr; /* 0x2a0 */
|
||||
volatile unsigned int wrap_svn; /* 0x2a4 */
|
||||
|
||||
}; //ms_rxi310_portmap
|
||||
|
||||
#define QFIFO_CMD_BANK_BFO (35 - QFIFO_CMD_WRRD_BFO) // [38:35]
|
||||
#define QFIFO_CMD_BANK_BFW 4
|
||||
#define QFIFO_CMD_PAGE_BFO (20 - QFIFO_CMD_WRRD_BFO) // [34:20]
|
||||
#define QFIFO_CMD_PAGE_BFW 15
|
||||
#define QFIFO_CMD_COLU_BFO (7 - QFIFO_CMD_WRRD_BFO) // [19: 7]
|
||||
#define QFIFO_CMD_COLU_BFW 13 // [19: 7]
|
||||
#define QFIFO_BST_LEN_BFO (3 - QFIFO_CMD_WRRD_BFO) // [6:3]
|
||||
#define QFIFO_BST_LEN_BFW 4 // [6:3]
|
||||
#define QFIFO_CMD_WRRD_BFO 2 // [2], remove bit[1:0]
|
||||
#define QFIFO_CMD_WRRD_BFW 1 // [2], remove bit[1:0]
|
||||
|
||||
//====================================================//
|
||||
|
||||
#define REG_SDR_CCR 0x00
|
||||
#define REG_SDR_DCR 0x04
|
||||
#define REG_SDR_IOCR 0x08
|
||||
#define REG_SDR_CSR 0x0C
|
||||
#define REG_SDR_DRR 0x10
|
||||
#define REG_SDR_TPR0 0x14
|
||||
#define REG_SDR_TPR1 0x18
|
||||
#define REG_SDR_TPR2 0x1C
|
||||
#define REG_SDR_MR 0x20
|
||||
#define REG_SDR_EMR1 0x24
|
||||
#define REG_SDR_EMR2 0x28
|
||||
#define REG_SDR_EMR3 0x2C
|
||||
#define REG_SDR_CMD_DPIN 0x30
|
||||
#define REG_SDR_TIE_DPIN 0x34
|
||||
#define REG_SDR_BCR 0xD0
|
||||
#define REG_SDR_BST 0xD4
|
||||
#define REG_SDR_BSRAM0 0xD8
|
||||
#define REG_SDR_BSRAM1 0xDC
|
||||
#define REG_SDR_PCTL_SVN_ID 0xF4
|
||||
#define REG_SDR_PCTL_IDR 0xF8
|
||||
#define REG_SDR_DLY0 0x100
|
||||
|
||||
#define REG_SDR_DLY1 0x104
|
||||
#define REG_SDR_DCM_RST 0x104
|
||||
|
||||
#define REG_SDR_DLY_CLK_PHA 0x108
|
||||
#define REG_SDR_DLY_ST 0x10C
|
||||
|
||||
#define REG_SDR_MISC 0x224
|
||||
#define REG_SDR_OCP_WRAP_IDR 0x2A0
|
||||
#define REG_SDR_OCP_WRAP_VERSION 0x2A4
|
||||
|
||||
|
||||
#endif // end of "#ifndef _RTL8195A_SDR_H"
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,530 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#ifndef _RTL8195A_SSI_H_
|
||||
#define _RTL8195A_SSI_H_
|
||||
|
||||
#define SSI_DUMMY_DATA 0x00 // for master mode, we need to push a Dummy data to TX FIFO for read
|
||||
|
||||
#define SSI_CLK_SPI1 (PLATFORM_CLOCK/2)
|
||||
#define SSI_CLK_SPI0_2 (PLATFORM_CLOCK/4)
|
||||
|
||||
/* Parameters of DW_apb_ssi for RTL8195A */
|
||||
#define SSI_TX_FIFO_DEPTH 64
|
||||
#define TX_ABW 6 // 1-8, log2(SSI_TX_FIFO_DEPTH)
|
||||
#define SSI_RX_FIFO_DEPTH 64
|
||||
#define RX_ABW 6 // 1-8, log2(SSI_RX_FIFO_DEPTH)
|
||||
|
||||
#define SSI0_REG_BASE 0x40042000
|
||||
#define SSI1_REG_BASE 0x40042400
|
||||
#define SSI2_REG_BASE 0x40042800
|
||||
|
||||
/* Memory Map of DW_apb_ssi */
|
||||
#define REG_DW_SSI_CTRLR0 0x00 // 16 bits
|
||||
#define REG_DW_SSI_CTRLR1 0x04 // 16 bits
|
||||
#define REG_DW_SSI_SSIENR 0x08 // 1 bit
|
||||
#define REG_DW_SSI_MWCR 0x0C // 3 bits
|
||||
#define REG_DW_SSI_SER 0x10 //
|
||||
#define REG_DW_SSI_BAUDR 0x14 // 16 bits
|
||||
#define REG_DW_SSI_TXFTLR 0x18 // TX_ABW
|
||||
#define REG_DW_SSI_RXFTLR 0x1C // RX_ABW
|
||||
#define REG_DW_SSI_TXFLR 0x20 //
|
||||
#define REG_DW_SSI_RXFLR 0x24 //
|
||||
#define REG_DW_SSI_SR 0x28 // 7 bits
|
||||
#define REG_DW_SSI_IMR 0x2C //
|
||||
#define REG_DW_SSI_ISR 0x30 // 6 bits
|
||||
#define REG_DW_SSI_RISR 0x34 // 6 bits
|
||||
#define REG_DW_SSI_TXOICR 0x38 // 1 bits
|
||||
#define REG_DW_SSI_RXOICR 0x3C // 1 bits
|
||||
#define REG_DW_SSI_RXUICR 0x40 // 1 bits
|
||||
#define REG_DW_SSI_MSTICR 0x44 // 1 bits
|
||||
#define REG_DW_SSI_ICR 0x48 // 1 bits
|
||||
#define REG_DW_SSI_DMACR 0x4C // 2 bits
|
||||
#define REG_DW_SSI_DMATDLR 0x50 // TX_ABW
|
||||
#define REG_DW_SSI_DMARDLR 0x54 // RX_ABW
|
||||
#define REG_DW_SSI_IDR 0x58 // 32 bits
|
||||
#define REG_DW_SSI_COMP_VERSION 0x5C // 32 bits
|
||||
#define REG_DW_SSI_DR 0x60 // 16 bits 0x60-0xEC
|
||||
#define REG_DW_SSI_RX_SAMPLE_DLY 0xF0 // 8 bits
|
||||
#define REG_DW_SSI_RSVD_0 0xF4 // 32 bits
|
||||
#define REG_DW_SSI_RSVD_1 0xF8 // 32 bits
|
||||
#define REG_DW_SSI_RSVD_2 0xFC // 32 bits
|
||||
|
||||
// CTRLR0 0x00 // 16 bits, 6.2.1
|
||||
// DFS Reset Value: 0x7
|
||||
#define BIT_SHIFT_CTRLR0_DFS 0
|
||||
#define BIT_MASK_CTRLR0_DFS 0xF
|
||||
#define BIT_CTRLR0_DFS(x)(((x) & BIT_MASK_CTRLR0_DFS) << BIT_SHIFT_CTRLR0_DFS)
|
||||
#define BIT_INVC_CTRLR0_DFS (~(BIT_MASK_CTRLR0_DFS << BIT_SHIFT_CTRLR0_DFS))
|
||||
|
||||
#define BIT_SHIFT_CTRLR0_FRF 4
|
||||
#define BIT_MASK_CTRLR0_FRF 0x3
|
||||
#define BIT_CTRLR0_FRF(x)(((x) & BIT_MASK_CTRLR0_FRF) << BIT_SHIFT_CTRLR0_FRF)
|
||||
#define BIT_INVC_CTRLR0_FRF (~(BIT_MASK_CTRLR0_FRF << BIT_SHIFT_CTRLR0_FRF))
|
||||
|
||||
#define BIT_SHIFT_CTRLR0_SCPH 6
|
||||
#define BIT_MASK_CTRLR0_SCPH 0x1
|
||||
#define BIT_CTRLR0_SCPH(x)(((x) & BIT_MASK_CTRLR0_SCPH) << BIT_SHIFT_CTRLR0_SCPH)
|
||||
#define BIT_INVC_CTRLR0_SCPH (~(BIT_MASK_CTRLR0_SCPH << BIT_SHIFT_CTRLR0_SCPH))
|
||||
|
||||
#define BIT_SHIFT_CTRLR0_SCPOL 7
|
||||
#define BIT_MASK_CTRLR0_SCPOL 0x1
|
||||
#define BIT_CTRLR0_SCPOL(x)(((x) & BIT_MASK_CTRLR0_SCPOL) << BIT_SHIFT_CTRLR0_SCPOL)
|
||||
#define BIT_INVC_CTRLR0_SCPOL (~(BIT_MASK_CTRLR0_SCPOL << BIT_SHIFT_CTRLR0_SCPOL))
|
||||
|
||||
#define BIT_SHIFT_CTRLR0_TMOD 8
|
||||
#define BIT_MASK_CTRLR0_TMOD 0x3
|
||||
#define BIT_CTRLR0_TMOD(x)(((x) & BIT_MASK_CTRLR0_TMOD) << BIT_SHIFT_CTRLR0_TMOD)
|
||||
#define BIT_INVC_CTRLR0_TMOD (~(BIT_MASK_CTRLR0_TMOD << BIT_SHIFT_CTRLR0_TMOD))
|
||||
|
||||
#define BIT_SHIFT_CTRLR0_SLV_OE 10
|
||||
#define BIT_MASK_CTRLR0_SLV_OE 0x1
|
||||
#define BIT_CTRLR0_SLV_OE(x)(((x) & BIT_MASK_CTRLR0_SLV_OE) << BIT_SHIFT_CTRLR0_SLV_OE)
|
||||
#define BIT_INVC_CTRLR0_SLV_OE (~(BIT_MASK_CTRLR0_SLV_OE << BIT_SHIFT_CTRLR0_SLV_OE))
|
||||
|
||||
#define BIT_SHIFT_CTRLR0_SRL 11
|
||||
#define BIT_MASK_CTRLR0_SRL 0x1
|
||||
#define BIT_CTRLR0_SRL(x)(((x) & BIT_MASK_CTRLR0_SRL) << BIT_SHIFT_CTRLR0_SRL)
|
||||
#define BIT_INVC_CTRLR0_SRL (~(BIT_MASK_CTRLR0_SRL << BIT_SHIFT_CTRLR0_SRL))
|
||||
|
||||
#define BIT_SHIFT_CTRLR0_CFS 12
|
||||
#define BIT_MASK_CTRLR0_CFS 0xF
|
||||
#define BIT_CTRLR0_CFS(x)(((x) & BIT_MASK_CTRLR0_CFS) << BIT_SHIFT_CTRLR0_CFS)
|
||||
#define BIT_INVC_CTRLR0_CFS (~(BIT_MASK_CTRLR0_CFS << BIT_SHIFT_CTRLR0_CFS))
|
||||
|
||||
// CTRLR1 0x04 // 16 bits
|
||||
#define BIT_SHIFT_CTRLR1_NDF 0
|
||||
#define BIT_MASK_CTRLR1_NDF 0xFFFF
|
||||
#define BIT_CTRLR1_NDF(x)(((x) & BIT_MASK_CTRLR1_NDF) << BIT_SHIFT_CTRLR1_NDF)
|
||||
#define BIT_INVC_CTRLR1_NDF (~(BIT_MASK_CTRLR1_NDF << BIT_SHIFT_CTRLR1_NDF))
|
||||
|
||||
// SSIENR 0x08 // 1 bit
|
||||
#define BIT_SHIFT_SSIENR_SSI_EN 0
|
||||
#define BIT_MASK_SSIENR_SSI_EN 0x1
|
||||
#define BIT_SSIENR_SSI_EN(x)(((x) & BIT_MASK_SSIENR_SSI_EN) << BIT_SHIFT_SSIENR_SSI_EN)
|
||||
#define BIT_INVC_SSIENR_SSI_EN (~(BIT_MASK_SSIENR_SSI_EN << BIT_SHIFT_SSIENR_SSI_EN))
|
||||
|
||||
// MWCR 0x0c // 3 bits
|
||||
#define BIT_SHIFT_MWCR_MWMOD 0
|
||||
#define BIT_MASK_MWCR_MWMOD 0x1
|
||||
#define BIT_MWCR_MWMOD(x)(((x) & BIT_MASK_MWCR_MWMOD) << BIT_SHIFT_MWCR_MWMOD)
|
||||
#define BIT_INVC_MWCR_MWMOD (~(BIT_MASK_MWCR_MWMOD << BIT_SHIFT_MWCR_MWMOD))
|
||||
|
||||
#define BIT_SHIFT_MWCR_MDD 1
|
||||
#define BIT_MASK_MWCR_MDD 0x1
|
||||
#define BIT_MWCR_MDD(x)(((x) & BIT_MASK_MWCR_MDD) << BIT_SHIFT_MWCR_MDD)
|
||||
#define BIT_INVC_MWCR_MDD (~(BIT_MASK_MWCR_MDD << BIT_SHIFT_MWCR_MDD))
|
||||
|
||||
#define BIT_SHIFT_MWCR_MHS 2
|
||||
#define BIT_MASK_MWCR_MHS 0x1
|
||||
#define BIT_MWCR_MHS(x)(((x) & BIT_MASK_MWCR_MHS) << BIT_SHIFT_MWCR_MHS)
|
||||
#define BIT_INVC_MWCR_MHS (~(BIT_MASK_MWCR_MHS << BIT_SHIFT_MWCR_MHS))
|
||||
|
||||
// SER 0x10 // Variable Length
|
||||
#define BIT_SHIFT_SER_SER 0
|
||||
#define BIT_MASK_SER_SER 0xFF
|
||||
#define BIT_SER_SER(x)(((x) & BIT_MASK_SER_SER) << BIT_SHIFT_SER_SER)
|
||||
#define BIT_INVC_SER_SER (~(BIT_MASK_SER_SER << BIT_SHIFT_SER_SER))
|
||||
|
||||
// BAUDR 0x14 // 16 bits
|
||||
#define BIT_SHIFT_BAUDR_SCKDV 0
|
||||
#define BIT_MASK_BAUDR_SCKDV 0xFFFF
|
||||
#define BIT_BAUDR_SCKDV(x)(((x) & BIT_MASK_BAUDR_SCKDV) << BIT_SHIFT_BAUDR_SCKDV)
|
||||
#define BIT_INVC_BAUDR_SCKDV (~(BIT_MASK_BAUDR_SCKDV << BIT_SHIFT_BAUDR_SCKDV))
|
||||
|
||||
// TXFLTR 0x18 // Variable Length
|
||||
#define BIT_SHIFT_TXFTLR_TFT 0
|
||||
#define BIT_MASK_TXFTLR_TFT 0x3F // (TX_ABW-1):0
|
||||
#define BIT_TXFTLR_TFT(x)(((x) & BIT_MASK_TXFTLR_TFT) << BIT_SHIFT_TXFTLR_TFT)
|
||||
#define BIT_INVC_TXFTLR_TFT (~(BIT_MASK_TXFTLR_TFT << BIT_SHIFT_TXFTLR_TFT))
|
||||
|
||||
// RXFLTR 0x1c // Variable Length
|
||||
#define BIT_SHIFT_RXFTLR_RFT 0
|
||||
#define BIT_MASK_RXFTLR_RFT 0x3F // (RX_ABW-1):0
|
||||
#define BIT_RXFTLR_RFT(x)(((x) & BIT_MASK_RXFTLR_RFT) << BIT_SHIFT_RXFTLR_RFT)
|
||||
#define BIT_INVC_RXFTLR_RFT (~(BIT_MASK_RXFTLR_RFT << BIT_SHIFT_RXFTLR_RFT))
|
||||
|
||||
// TXFLR 0x20 // see [READ ONLY]
|
||||
#define BIT_MASK_TXFLR_TXTFL 0x7F // (TX_ABW):0
|
||||
|
||||
// RXFLR 0x24 // see [READ ONLY]
|
||||
#define BIT_MASK_RXFLR_RXTFL 0x7F // (RX_ABW):0
|
||||
|
||||
// SR 0x28 // 7 bits [READ ONLY]
|
||||
#define BIT_SR_BUSY BIT0
|
||||
#define BIT_SR_TFNF BIT1
|
||||
#define BIT_SR_TFE BIT2
|
||||
#define BIT_SR_RFNE BIT3
|
||||
#define BIT_SR_RFF BIT4
|
||||
#define BIT_SR_TXE BIT5
|
||||
#define BIT_SR_DCOL BIT6
|
||||
|
||||
// IMR 0x2c // see
|
||||
#define BIT_SHIFT_IMR_TXEIM 0
|
||||
#define BIT_MASK_IMR_TXEIM 0x1
|
||||
// #define BIT_IMR_TXEIM(x)(((x) & BIT_MASK_IMR_TXEIM) << BIT_SHIFT_IMR_TXEIM)
|
||||
#define BIT_INVC_IMR_TXEIM (~(BIT_MASK_IMR_TXEIM << BIT_SHIFT_IMR_TXEIM))
|
||||
|
||||
#define BIT_SHIFT_IMR_TXOIM 1
|
||||
#define BIT_MASK_IMR_TXOIM 0x1
|
||||
// #define BIT_IMR_TXOIM(x)(((x) & BIT_MASK_IMR_TXOIM) << BIT_SHIFT_IMR_TXOIM)
|
||||
#define BIT_INVC_IMR_TXOIM (~(BIT_MASK_IMR_TXOIM << BIT_SHIFT_IMR_TXOIM))
|
||||
|
||||
#define BIT_SHIFT_IMR_RXUIM 2
|
||||
#define BIT_MASK_IMR_RXUIM 0x1
|
||||
// #define BIT_IMR_RXUIM(x)(((x) & BIT_MASK_IMR_RXUIM) << BIT_SHIFT_IMR_RXUIM)
|
||||
#define BIT_INVC_IMR_RXUIM (~(BIT_MASK_IMR_RXUIM << BIT_SHIFT_IMR_RXUIM))
|
||||
|
||||
#define BIT_SHIFT_IMR_RXOIM 3
|
||||
#define BIT_MASK_IMR_RXOIM 0x1
|
||||
// #define BIT_IMR_RXOIM(x)(((x) & BIT_MASK_IMR_RXOIM) << BIT_SHIFT_IMR_RXOIM)
|
||||
#define BIT_INVC_IMR_RXOIM (~(BIT_MASK_IMR_RXOIM << BIT_SHIFT_IMR_RXOIM))
|
||||
|
||||
#define BIT_SHIFT_IMR_RXFIM 4
|
||||
#define BIT_MASK_IMR_RXFIM 0x1
|
||||
// #define BIT_IMR_RXFIM(x)(((x) & BIT_MASK_IMR_RXFIM) << BIT_SHIFT_IMR_RXFIM)
|
||||
#define BIT_INVC_IMR_RXFIM (~(BIT_MASK_IMR_RXFIM << BIT_SHIFT_IMR_RXFIM))
|
||||
|
||||
#define BIT_SHIFT_IMR_MSTIM 5
|
||||
#define BIT_MASK_IMR_MSTIM 0x1
|
||||
// #define BIT_IMR_MSTIM(x)(((x) & BIT_MASK_IMR_MSTIM) << BIT_SHIFT_IMR_MSTIM)
|
||||
#define BIT_INVC_IMR_MSTIM (~(BIT_MASK_IMR_MSTIM << BIT_SHIFT_IMR_MSTIM))
|
||||
|
||||
#define BIT_IMR_TXEIM BIT0
|
||||
#define BIT_IMR_TXOIM BIT1
|
||||
#define BIT_IMR_RXUIM BIT2
|
||||
#define BIT_IMR_RXOIM BIT3
|
||||
#define BIT_IMR_RXFIM BIT4
|
||||
#define BIT_IMR_MSTIM BIT5
|
||||
|
||||
// ISR 0x30 // 6 bits [READ ONLY]
|
||||
#define BIT_ISR_TXEIS BIT0
|
||||
#define BIT_ISR_TXOIS BIT1
|
||||
#define BIT_ISR_RXUIS BIT2
|
||||
#define BIT_ISR_RXOIS BIT3
|
||||
#define BIT_ISR_RXFIS BIT4
|
||||
#define BIT_ISR_MSTIS BIT5
|
||||
|
||||
// RISR 0x34 // 6 bits [READ ONLY]
|
||||
#define BIT_RISR_TXEIR BIT0
|
||||
#define BIT_RISR_TXOIR BIT1
|
||||
#define BIT_RISR_RXUIR BIT2
|
||||
#define BIT_RISR_RXOIR BIT3
|
||||
#define BIT_RISR_RXFIR BIT4
|
||||
#define BIT_RISR_MSTIR BIT5
|
||||
|
||||
// TXOICR 0x38 // 1 bits [READ ONLY]
|
||||
// RXOICR 0x3c // 1 bits [READ ONLY]
|
||||
// RXUICR 0x40 // 1 bits [READ ONLY]
|
||||
// MSTICR 0x44 // 1 bits [READ ONLY]
|
||||
// ICR 0x48 // 1 bits [READ ONLY]
|
||||
|
||||
// DMACR 0x4c // 2 bits
|
||||
#define BIT_SHIFT_DMACR_RDMAE 0
|
||||
#define BIT_MASK_DMACR_RDMAE 0x1
|
||||
#define BIT_DMACR_RDMAE(x)(((x) & BIT_MASK_DMACR_RDMAE) << BIT_SHIFT_DMACR_RDMAE)
|
||||
#define BIT_INVC_DMACR_RDMAE (~(BIT_MASK_DMACR_RDMAE << BIT_SHIFT_DMACR_RDMAE))
|
||||
|
||||
#define BIT_SHIFT_DMACR_TDMAE 1
|
||||
#define BIT_MASK_DMACR_TDMAE 0x1
|
||||
#define BIT_DMACR_TDMAE(x)(((x) & BIT_MASK_DMACR_TDMAE) << BIT_SHIFT_DMACR_TDMAE)
|
||||
#define BIT_INVC_DMACR_TDMAE (~(BIT_MASK_DMACR_TDMAE << BIT_SHIFT_DMACR_TDMAE))
|
||||
|
||||
// DMATDLR 0x50
|
||||
#define BIT_SHIFT_DMATDLR_DMATDL 0
|
||||
#define BIT_MASK_DMATDLR_DMATDL 0x3F // (TX_ABW-1):0
|
||||
#define BIT_DMATDLR_DMATDL(x)(((x) & BIT_MASK_DMATDLR_DMATDL) << BIT_SHIFT_DMATDLR_DMATDL)
|
||||
#define BIT_INVC_DMATDLR_DMATDL (~(BIT_MASK_DMATDLR_DMATDL << BIT_SHIFT_DMATDLR_DMATDL))
|
||||
|
||||
// DMARDLR 0x54
|
||||
#define BIT_SHIFT_DMARDLR_DMARDL 0
|
||||
#define BIT_MASK_DMARDLR_DMARDL 0x3F // (RX_ABW-1):0
|
||||
#define BIT_DMARDLR_DMARDL(x)(((x) & BIT_MASK_DMARDLR_DMARDL) << BIT_SHIFT_DMARDLR_DMARDL)
|
||||
#define BIT_INVC_DMARDLR_DMARDL (~(BIT_MASK_DMARDLR_DMARDL << BIT_SHIFT_DMARDLR_DMARDL))
|
||||
|
||||
// IDR 0x58 // 32 bits [READ ONLY]
|
||||
// COMP_VERSION 0x5c // 32 bits [READ ONLY]
|
||||
|
||||
// DR 0x60 // 16 bits 0x60-0xEC
|
||||
#define BIT_SHIFT_DR_DR 0
|
||||
#define BIT_MASK_DR_DR 0xFFFF
|
||||
#define BIT_DR_DR(x)(((x) & BIT_MASK_DR_DR) << BIT_SHIFT_DR_DR)
|
||||
#define BIT_INVC_DR_DR (~(BIT_MASK_DR_DR << BIT_SHIFT_DR_DR))
|
||||
|
||||
// RX_SAMPLE_DLY 0xF0 // 8 bits
|
||||
#define BIT_SHIFT_RX_SAMPLE_DLY_RSD 0
|
||||
#define BIT_MASK_RX_SAMPLE_DLY_RSD 0xFFFF
|
||||
#define BIT_RX_SAMPLE_DLY_RSD(x)(((x) & BIT_MASK_RX_SAMPLE_DLY_RSD) << BIT_SHIFT_RX_SAMPLE_DLY_RSD)
|
||||
#define BIT_INVC_RX_SAMPLE_DLY_RSD (~(BIT_MASK_RX_SAMPLE_DLY_RSD << BIT_SHIFT_RX_SAMPLE_DLY_RSD))
|
||||
|
||||
// RSVD_0 0xF4 // 32 bits
|
||||
// RSVD_1 0xF8 // 32 bits
|
||||
// RSVD_2 0xFC // 32 bits
|
||||
|
||||
// SSI0 Pinmux
|
||||
#define BIT_SHIFT_SSI0_PIN_EN 0
|
||||
#define BIT_MASK_SSI0_PIN_EN 0x1
|
||||
#define BIT_SSI0_PIN_EN(x)(((x) & BIT_MASK_SSI0_PIN_EN) << BIT_SHIFT_SSI0_PIN_EN)
|
||||
#define BIT_INVC_SSI0_PIN_EN (~(BIT_MASK_SSI0_PIN_EN << BIT_SHIFT_SSI0_PIN_EN))
|
||||
|
||||
#define BIT_SHIFT_SSI0_PIN_SEL 1
|
||||
#define BIT_MASK_SSI0_PIN_SEL 0x7
|
||||
#define BIT_SSI0_PIN_SEL(x)(((x) & BIT_MASK_SSI0_PIN_SEL) << BIT_SHIFT_SSI0_PIN_SEL)
|
||||
#define BIT_INVC_SSI0_PIN_SEL (~(BIT_MASK_SSI0_PIN_SEL << BIT_SHIFT_SSI0_PIN_SEL))
|
||||
|
||||
// SSI1 Pinmux
|
||||
#define BIT_SHIFT_SSI1_PIN_EN 4
|
||||
#define BIT_MASK_SSI1_PIN_EN 0x1
|
||||
#define BIT_SSI1_PIN_EN(x)(((x) & BIT_MASK_SSI1_PIN_EN) << BIT_SHIFT_SSI1_PIN_EN)
|
||||
#define BIT_INVC_SSI1_PIN_EN (~(BIT_MASK_SSI1_PIN_EN << BIT_SHIFT_SSI1_PIN_EN))
|
||||
|
||||
#define BIT_SHIFT_SSI1_PIN_SEL 5
|
||||
#define BIT_MASK_SSI1_PIN_SEL 0x7
|
||||
#define BIT_SSI1_PIN_SEL(x)(((x) & BIT_MASK_SSI1_PIN_SEL) << BIT_SHIFT_SSI1_PIN_SEL)
|
||||
#define BIT_INVC_SSI1_PIN_SEL (~(BIT_MASK_SSI1_PIN_SEL << BIT_SHIFT_SSI1_PIN_SEL))
|
||||
|
||||
// SSI2 Pinmux
|
||||
#define BIT_SHIFT_SSI2_PIN_EN 8
|
||||
#define BIT_MASK_SSI2_PIN_EN 0x1
|
||||
#define BIT_SSI2_PIN_EN(x)(((x) & BIT_MASK_SSI2_PIN_EN) << BIT_SHIFT_SSI2_PIN_EN)
|
||||
#define BIT_INVC_SSI2_PIN_EN (~(BIT_MASK_SSI2_PIN_EN << BIT_SHIFT_SSI2_PIN_EN))
|
||||
|
||||
#define BIT_SHIFT_SSI2_PIN_SEL 9
|
||||
#define BIT_MASK_SSI2_PIN_SEL 0x7
|
||||
#define BIT_SSI2_PIN_SEL(x)(((x) & BIT_MASK_SSI2_PIN_SEL) << BIT_SHIFT_SSI2_PIN_SEL)
|
||||
#define BIT_INVC_SSI2_PIN_SEL (~(BIT_MASK_SSI2_PIN_SEL << BIT_SHIFT_SSI2_PIN_SEL))
|
||||
|
||||
// SSI0 Multiple Chip Selection (Pinmux Select is controlled by BIT_SSI0_PIN_SEL)
|
||||
#define BIT_SHIFT_SSI0_MULTI_CS_EN 28
|
||||
#define BIT_MASK_SSI0_MULTI_CS_EN 0x1
|
||||
#define BIT_SSI0_MULTI_CS_EN(x)(((x) & BIT_MASK_SSI0_MULTI_CS_EN) << BIT_SHIFT_SSI0_MULTI_CS_EN)
|
||||
#define BIT_INVC_SSI0_MULTI_CS_EN (~(BIT_MASK_SSI0_MULTI_CS_EN << BIT_SHIFT_SSI0_MULTI_CS_EN))
|
||||
|
||||
|
||||
#define HAL_SSI_READ32(SsiIndex, addr) \
|
||||
HAL_READ32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
|
||||
#define HAL_SSI_WRITE32(SsiIndex, addr, value) \
|
||||
HAL_WRITE32(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
|
||||
#define HAL_SSI_READ16(SsiIndex, addr) \
|
||||
HAL_READ16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
|
||||
#define HAL_SSI_WRITE16(SsiIndex, addr, value) \
|
||||
HAL_WRITE16(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
|
||||
#define HAL_SSI_READ8(SsiIndex, addr) \
|
||||
HAL_READ8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr)
|
||||
#define HAL_SSI_WRITE8(SsiIndex, addr, value) \
|
||||
HAL_WRITE8(SPI0_REG_BASE+ (SsiIndex*SSI_REG_OFF), addr, value)
|
||||
|
||||
|
||||
// SSI Pinmux Select
|
||||
typedef enum _SSI0_PINMUX_SELECT_ {
|
||||
SSI0_MUX_TO_GPIOE = S0,
|
||||
SSI0_MUX_TO_GPIOC = S1
|
||||
}SSI0_PINMUX_SELECT, *PSSI0_PINMUX_SELECT;
|
||||
|
||||
typedef enum _SSI1_PINMUX_SELECT_ {
|
||||
SSI1_MUX_TO_GPIOA = S0,
|
||||
SSI1_MUX_TO_GPIOB = S1,
|
||||
SSI1_MUX_TO_GPIOD = S2
|
||||
}SSI1_PINMUX_SELECT, *PSSI1_PINMUX_SELECT;
|
||||
|
||||
typedef enum _SSI2_PINMUX_SELECT_ {
|
||||
SSI2_MUX_TO_GPIOG = S0,
|
||||
SSI2_MUX_TO_GPIOE = S1,
|
||||
SSI2_MUX_TO_GPIOD = S2
|
||||
}SSI2_PINMUX_SELECT, *PSSI2_PINMUX_SELECT;
|
||||
|
||||
typedef enum _SSI0_MULTI_CS_PINMUX_SELECT_ {
|
||||
SSI0_CS_MUX_TO_GPIOE = S0,
|
||||
SSI0_CS_MUX_TO_GPIOC = S1
|
||||
}SSI0_MULTI_CS_PINMUX_SELECT, *PSSI0_MULTI_CS_PINMUX_SELECT;
|
||||
|
||||
typedef enum _SSI_CTRLR0_TMOD_ {
|
||||
TMOD_TR = 0,
|
||||
TMOD_TO = 1,
|
||||
TMOD_RO = 2,
|
||||
TMOD_EEPROM_R = 3
|
||||
}SSI_CTRLR0_TMOD, *PSSI_CTRLR0_TMOD;
|
||||
|
||||
typedef enum _SSI_CTRLR0_SCPOL_ {
|
||||
SCPOL_INACTIVE_IS_LOW = 0,
|
||||
SCPOL_INACTIVE_IS_HIGH = 1
|
||||
}SSI_CTRLR0_SCPOL, *PSSI_CTRLR0_SCPOL;
|
||||
|
||||
typedef enum _SSI_CTRLR0_SCPH_ {
|
||||
SCPH_TOGGLES_IN_MIDDLE = 0,
|
||||
SCPH_TOGGLES_AT_START = 1
|
||||
}SSI_CTRLR0_SCPH, *PSSI_CTRLR0_SCPH;
|
||||
|
||||
typedef enum _SSI_CTRLR0_DFS_ {
|
||||
DFS_4_BITS = 3,
|
||||
DFS_5_BITS = 4,
|
||||
DFS_6_BITS = 5,
|
||||
DFS_7_BITS = 6,
|
||||
DFS_8_BITS = 7,
|
||||
DFS_9_BITS = 8,
|
||||
DFS_10_BITS = 9,
|
||||
DFS_11_BITS = 10,
|
||||
DFS_12_BITS = 11,
|
||||
DFS_13_BITS = 12,
|
||||
DFS_14_BITS = 13,
|
||||
DFS_15_BITS = 14,
|
||||
DFS_16_BITS = 15,
|
||||
}SSI_CTRLR0_DFS, *PSSI_CTRLR0_DFS;
|
||||
|
||||
typedef enum _SSI_CTRLR0_CFS_ {
|
||||
CFS_1_BIT = 0,
|
||||
CFS_2_BITS = 1,
|
||||
CFS_3_BITS = 2,
|
||||
CFS_4_BITS = 3,
|
||||
CFS_5_BITS = 4,
|
||||
CFS_6_BITS = 5,
|
||||
CFS_7_BITS = 6,
|
||||
CFS_8_BITS = 7,
|
||||
CFS_9_BITS = 8,
|
||||
CFS_10_BITS = 9,
|
||||
CFS_11_BITS = 10,
|
||||
CFS_12_BITS = 11,
|
||||
CFS_13_BITS = 12,
|
||||
CFS_14_BITS = 13,
|
||||
CFS_15_BITS = 14,
|
||||
CFS_16_BITS = 15
|
||||
}SSI_CTRLR0_CFS, *PSSI_CTRLR0_CFS;
|
||||
|
||||
typedef enum _SSI_CTRLR0_SLV_OE_ {
|
||||
SLV_TXD_ENABLE = 0,
|
||||
SLV_TXD_DISABLE = 1
|
||||
}SSI_CTRLR0_SLV_OE, *PSSI_CTRLR0_SLV_OE;
|
||||
|
||||
typedef enum _SSI_ROLE_SELECT_ {
|
||||
SSI_SLAVE = 0,
|
||||
SSI_MASTER = 1
|
||||
}SSI_ROLE_SELECT, *PSSI_ROLE_SELECT;
|
||||
|
||||
typedef enum _SSI_FRAME_FORMAT_ {
|
||||
FRF_MOTOROLA_SPI = 0,
|
||||
FRF_TI_SSP = 1,
|
||||
FRF_NS_MICROWIRE = 2,
|
||||
FRF_RSVD = 3
|
||||
}SSI_FRAME_FORMAT, *PSSI_FRAME_FORMAT;
|
||||
|
||||
typedef enum _SSI_DMACR_ENABLE_ {
|
||||
SSI_NODMA = 0,
|
||||
SSI_RXDMA_ENABLE = 1,
|
||||
SSI_TXDMA_ENABLE = 2,
|
||||
SSI_TRDMA_ENABLE = 3
|
||||
}SSI_DMACR_ENABLE, *PSSI_DMACR_ENABLE;
|
||||
|
||||
typedef enum _SSI_MWCR_HANDSHAKE_ {
|
||||
MW_HANDSHAKE_DISABLE = 0,
|
||||
MW_HANDSHAKE_ENABLE = 1
|
||||
}SSI_MWCR_HANDSHAKE, *PSSI_MWCR_HANDSHAKE;
|
||||
|
||||
typedef enum _SSI_MWCR_DIRECTION_ {
|
||||
MW_DIRECTION_SLAVE_TO_MASTER = 0,
|
||||
MW_DIRECTION_MASTER_TO_SLAVE = 1
|
||||
}SSI_MWCR_DIRECTION, *PSSI_MWCR_DIRECTION;
|
||||
|
||||
typedef enum _SSI_MWCR_TMOD_ {
|
||||
MW_TMOD_NONSEQUENTIAL = 0,
|
||||
MW_TMOD_SEQUENTIAL = 1
|
||||
}SSI_MWCR_TMOD, *PSSI_MWCR_TMOD;
|
||||
|
||||
typedef enum _SSI_DATA_TRANSFER_MECHANISM_ {
|
||||
SSI_DTM_BASIC,
|
||||
SSI_DTM_INTERRUPT,
|
||||
SSI_DTM_DMA
|
||||
}SSI_DATA_TRANSFER_MECHANISM, *PSSI_DATA_TRANSFER_MECHANISM;
|
||||
|
||||
|
||||
_LONG_CALL_ HAL_Status HalSsiPinmuxEnableRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ROM_ HAL_Status HalSsiEnableRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ROM_ HAL_Status HalSsiDisableRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ HAL_Status HalSsiSetSclkPolarityRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ HAL_Status HalSsiSetSclkPhaseRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ HAL_Status HalSsiWriteRtl8195a(VOID *Adaptor, u32 value);
|
||||
_LONG_CALL_ HAL_Status HalSsiLoadSettingRtl8195a(VOID *Adaptor, VOID *Setting);
|
||||
_LONG_CALL_ROM_ HAL_Status HalSsiSetInterruptMaskRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ HAL_Status HalSsiSetDeviceRoleRtl8195a(VOID *Adaptor, u32 Role);
|
||||
_LONG_CALL_ HAL_Status HalSsiInterruptEnableRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ HAL_Status HalSsiInterruptDisableRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ HAL_Status HalSsiReadInterruptRtl8195a(VOID *Adaptor, VOID *RxData, u32 Length);
|
||||
_LONG_CALL_ROM_ HAL_Status HalSsiSetRxFifoThresholdLevelRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ HAL_Status HalSsiSetTxFifoThresholdLevelRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ HAL_Status HalSsiWriteInterruptRtl8195a(VOID *Adaptor, VOID *TxData, u32 Length);
|
||||
_LONG_CALL_ROM_ HAL_Status HalSsiSetSlaveEnableRegisterRtl8195a(VOID *Adaptor, u32 SlaveIndex);
|
||||
_LONG_CALL_ROM_ u32 HalSsiBusyRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ROM_ u32 HalSsiWriteableRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ROM_ u32 HalSsiReadableRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ROM_ u32 HalSsiGetInterruptMaskRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ROM_ u32 HalSsiGetRxFifoLevelRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ u32 HalSsiGetTxFifoLevelRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ROM_ u32 HalSsiGetStatusRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ROM_ u32 HalSsiGetInterruptStatusRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ u32 HalSsiReadRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ u32 HalSsiGetRawInterruptStatusRtl8195a(VOID *Adaptor);
|
||||
_LONG_CALL_ROM_ u32 HalSsiGetSlaveEnableRegisterRtl8195a(VOID *Adaptor);
|
||||
|
||||
_LONG_CALL_ROM_ VOID _SsiReadInterrupt(VOID *Adaptor);
|
||||
_LONG_CALL_ROM_ VOID _SsiWriteInterrupt(VOID *Adaptor);
|
||||
_LONG_CALL_ u32 _SsiIrqHandle(VOID *Adaptor);
|
||||
|
||||
// ROM code patch
|
||||
VOID _SsiReadInterruptRtl8195a(VOID *Adapter);
|
||||
VOID _SsiWriteInterruptRtl8195a(VOID *Adapter);
|
||||
HAL_Status HalSsiInitRtl8195a_Patch(VOID *Adaptor);
|
||||
HAL_Status HalSsiPinmuxEnableRtl8195a_Patch(VOID *Adaptor);
|
||||
HAL_Status HalSsiPinmuxDisableRtl8195a(VOID *Adaptor);
|
||||
HAL_Status HalSsiDeInitRtl8195a(VOID * Adapter);
|
||||
HAL_Status HalSsiClockOffRtl8195a(VOID * Adapter);
|
||||
HAL_Status HalSsiClockOnRtl8195a(VOID * Adapter);
|
||||
VOID HalSsiSetSclkRtl8195a(VOID *Adapter, u32 ClkRate);
|
||||
HAL_Status HalSsiIntReadRtl8195a(VOID *Adapter, VOID *RxData, u32 Length);
|
||||
HAL_Status HalSsiIntWriteRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
|
||||
VOID HalSsiTxFIFOThresholdRtl8195a(VOID *Adaptor, u32 txftl);
|
||||
HAL_Status HalSsiEnterCriticalRtl8195a(VOID * Data);
|
||||
HAL_Status HalSsiExitCriticalRtl8195a(VOID * Data);
|
||||
HAL_Status HalSsiIsTimeoutRtl8195a(u32 StartCount, u32 TimeoutCnt);
|
||||
HAL_Status HalSsiStopRecvRtl8195a(VOID * Data);
|
||||
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
HAL_Status HalSsiPinmuxEnableRtl8195a_V04(VOID *Adaptor);
|
||||
HAL_Status HalSsiPinmuxDisableRtl8195a_V04(VOID * Adaptor);
|
||||
VOID _SsiReadInterruptRtl8195a_V04(VOID *Adapter);
|
||||
VOID _SsiWriteInterruptRtl8195a_V04(VOID *Adapter);
|
||||
HAL_Status HalSsiInitRtl8195a_V04(VOID *Adaptor);
|
||||
HAL_Status HalSsiSetFormatRtl8195a_V04(VOID * Adaptor);
|
||||
HAL_Status HalSsiDeInitRtl8195a_V04(VOID *Adapter);
|
||||
HAL_Status HalSsiIntReadRtl8195a_V04(VOID *Adapter, VOID *RxData, u32 Length);
|
||||
HAL_Status HalSsiIntWriteRtl8195a_V04(VOID *Adapter, u8 *pTxData, u32 Length);
|
||||
HAL_Status HalSsiClockOffRtl8195a_V04(VOID * Adapter);
|
||||
HAL_Status HalSsiClockOnRtl8195a_V04(VOID * Adapter);
|
||||
VOID HalSsiSetSclkRtl8195a_V04(VOID *Adapter, u32 ClkRate);
|
||||
VOID HalSsiTxGdmaLoadDefRtl8195a_V04(IN VOID * Adapter);
|
||||
VOID HalSsiRxGdmaLoadDefRtl8195a_V04(IN VOID * Adapter);
|
||||
VOID HalSsiDmaInitRtl8195a_V04(VOID *Adapter);
|
||||
HAL_Status HalSsiDmaSendRtl8195a_V04(IN VOID * Adapter, IN u8 * pTxData, IN u32 Length);
|
||||
HAL_Status HalSsiDmaRecvRtl8195a_V04(IN VOID * Adapter, IN u8 * pRxData, IN u32 Length);
|
||||
HAL_Status HalSsiDmaSendMultiBlockRtl8195a_V04(VOID * Adapter, u8 * pTxData, u32 Length);
|
||||
HAL_Status HalSsiDmaRecvMultiBlockRtl8195a_V04(VOID * Adapter, u8 * pRxData, u32 Length);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_GDMA_EN
|
||||
VOID HalSsiTxGdmaLoadDefRtl8195a(VOID *Adapter);
|
||||
VOID HalSsiRxGdmaLoadDefRtl8195a(VOID *Adapter);
|
||||
VOID HalSsiDmaInitRtl8195a(VOID *Adapter);
|
||||
HAL_Status HalSsiDmaSendRtl8195a(VOID *Adapter, u8 *pTxData, u32 Length);
|
||||
HAL_Status HalSsiDmaRecvRtl8195a(VOID *Adapter, u8 *pRxData, u32 Length);
|
||||
HAL_Status HalSsiDmaSendMultiBlockRtl8195a(VOID * Adapter, u8 * pRxData, u32 Length);
|
||||
HAL_Status HalSsiDmaRecvMultiBlockRtl8195a(VOID * Adapter, u8 * pRxData, u32 Length);
|
||||
|
||||
#endif // end of "#ifdef CONFIG_GDMA_EN"
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,257 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#ifndef _RTL8195A_TIMER_H_
|
||||
#define _RTL8195A_TIMER_H_
|
||||
|
||||
|
||||
#define TIMER_TICK_US 31
|
||||
|
||||
#define TIMER_LOAD_COUNT_OFF 0x00
|
||||
#define TIMER_CURRENT_VAL_OFF 0x04
|
||||
#define TIMER_CTL_REG_OFF 0x08
|
||||
#define TIMER_EOI_OFF 0x0c
|
||||
#define TIMER_INT_STATUS_OFF 0x10
|
||||
#define TIMER_INTERVAL 0x14
|
||||
#define TIMERS_INT_STATUS_OFF 0xa0
|
||||
#define TIMERS_EOI_OFF 0xa4
|
||||
#define TIMERS_RAW_INT_STATUS_OFF 0xa8
|
||||
#define TIMERS_COMP_VER_OFF 0xac
|
||||
|
||||
#define MAX_TIMER_VECTOR_TABLE_NUM 6
|
||||
|
||||
#define HAL_TIMER_READ32(addr) (*((volatile u32*)(TIMER_REG_BASE + addr)))//HAL_READ32(TIMER_REG_BASE, addr)
|
||||
#define HAL_TIMER_WRITE32(addr, value) ((*((volatile u32*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE32(TIMER_REG_BASE, addr, value)
|
||||
#define HAL_TIMER_READ16(addr) (*((volatile u16*)(TIMER_REG_BASE + addr)))//HAL_READ16(TIMER_REG_BASE, addr)
|
||||
#define HAL_TIMER_WRITE16(addr, value) ((*((volatile u16*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE16(TIMER_REG_BASE, addr, value)
|
||||
#define HAL_TIMER_READ8(addr) (*((volatile u8*)(TIMER_REG_BASE + addr)))//HAL_READ8(TIMER_REG_BASE, addr)
|
||||
#define HAL_TIMER_WRITE8(addr, value) ((*((volatile u8*)(TIMER_REG_BASE + addr))) = value)//HAL_WRITE8(TIMER_REG_BASE, addr, value)
|
||||
|
||||
_LONG_CALL_ u32
|
||||
HalGetTimerIdRtl8195a(
|
||||
IN u32 *TimerID
|
||||
);
|
||||
|
||||
_LONG_CALL_ BOOL
|
||||
HalTimerInitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ u32
|
||||
HalTimerReadCountRtl8195a(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
HalTimerIrqClearRtl8195a(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
HalTimerDisRtl8195a(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
HalTimerEnRtl8195a(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
HalTimerDumpRegRtl8195a(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
// ROM Code patch
|
||||
HAL_Status
|
||||
HalTimerInitRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u32
|
||||
HalTimerReadCountRtl8195a_Patch(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTimerReLoadRtl8195a_Patch(
|
||||
IN u32 TimerId,
|
||||
IN u32 LoadUs
|
||||
);
|
||||
|
||||
u32
|
||||
HalTimerReadCountRtl8195a_Patch(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTimerIrqEnRtl8195a(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTimerIrqDisRtl8195a(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTimerClearIsrRtl8195a(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTimerEnRtl8195a_Patch(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTimerDisRtl8195a_Patch(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
VOID
|
||||
HalTimerDeInitRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
|
||||
|
||||
__weak _LONG_CALL_
|
||||
VOID
|
||||
HalTimerIrq2To7HandleV02(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
__weak _LONG_CALL_ROM_
|
||||
HAL_Status
|
||||
HalTimerIrqRegisterRtl8195aV02(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
__weak _LONG_CALL_
|
||||
HAL_Status
|
||||
HalTimerInitRtl8195aV02(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
__weak _LONG_CALL_
|
||||
u32
|
||||
HalTimerReadCountRtl8195aV02(
|
||||
IN u32 TimerId
|
||||
);
|
||||
|
||||
__weak _LONG_CALL_
|
||||
VOID
|
||||
HalTimerReLoadRtl8195aV02(
|
||||
IN u32 TimerId,
|
||||
IN u32 LoadUs
|
||||
);
|
||||
|
||||
__weak _LONG_CALL_ROM_
|
||||
HAL_Status
|
||||
HalTimerIrqUnRegisterRtl8195aV02(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
__weak _LONG_CALL_
|
||||
VOID
|
||||
HalTimerDeInitRtl8195aV02(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#endif // end of "#ifdef CONFIG_CHIP_C_CUT"
|
||||
|
||||
#ifdef CONFIG_CHIP_E_CUT
|
||||
_LONG_CALL_ VOID
|
||||
HalTimerReLoadRtl8195a_V04(
|
||||
IN u32 TimerId,
|
||||
IN u32 LoadUs
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalTimerInitRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
#endif // #ifdef CONFIG_CHIP_E_CUT
|
||||
|
||||
// HAL functions wrapper
|
||||
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
|
||||
static __inline HAL_Status
|
||||
HalTimerInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
#ifdef CONFIG_CHIP_E_CUT
|
||||
return (HalTimerInitRtl8195a_V04(Data));
|
||||
#else
|
||||
return (HalTimerInitRtl8195a_Patch(Data));
|
||||
#endif
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalTimerEnable(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
HalTimerIrqEnRtl8195a(TimerId);
|
||||
HalTimerEnRtl8195a_Patch(TimerId);
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalTimerDisable(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
HalTimerDisRtl8195a_Patch(TimerId);
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalTimerClearIsr(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
HalTimerClearIsrRtl8195a(TimerId);
|
||||
}
|
||||
|
||||
static __inline VOID
|
||||
HalTimerReLoad(
|
||||
IN u32 TimerId,
|
||||
IN u32 LoadUs
|
||||
)
|
||||
{
|
||||
#ifdef CONFIG_CHIP_E_CUT
|
||||
HalTimerReLoadRtl8195a_V04(TimerId, LoadUs);
|
||||
#else
|
||||
HalTimerReLoadRtl8195a_Patch(TimerId, LoadUs);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
|
||||
|
||||
static __inline VOID
|
||||
HalTimerDeInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
HalTimerDeInitRtl8195a_Patch(Data);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
static __inline VOID
|
||||
HalTimerDeInit(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
HalTimerDeInitRtl8195aV02(Data);
|
||||
}
|
||||
|
||||
#endif // end of "#ifndef CONFIG_CHIP_C_CUT"
|
||||
#endif // #ifndef CONFIG_RELEASE_BUILD_LIBRARIES
|
||||
#endif //_RTL8195A_TIMER_H_
|
||||
|
|
@ -0,0 +1,716 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _RTL8195A_UART_H_
|
||||
#define _RTL8195A_UART_H_
|
||||
|
||||
#define MAX_UART_INDEX 2
|
||||
|
||||
#define RUART_DLL_OFF 0x00
|
||||
#define RUART_DLM_OFF 0x04 //RW, DLAB = 1
|
||||
#define RUART_INTERRUPT_EN_REG_OFF 0x04 //RW, DLAB = 0
|
||||
// Define Interrupt Enable Bit
|
||||
typedef enum {
|
||||
RU_IER_ERBFI = BIT0, // Enable Received Data Available Interrupt
|
||||
RU_IER_ETBEI = BIT1, // Enable Transmit Holding Register Empty Interrupt
|
||||
RU_IER_ELSI = BIT2, // Enable Receiver Line Status Interrupt
|
||||
RU_IER_EDSSI = BIT3, // Enable Modem Status Interrupt
|
||||
RU_IER_PTIME = BIT7 // Programmable THRE Interrupt Mode Enable
|
||||
} RUART_INT_EN;
|
||||
#define RUART_IER_ERBI BIT0 //BIT0, Enable Received Data Available Interrupt (rx trigger)
|
||||
#define RUART_IER_ETBEI BIT1 //BIT1, Enable Transmitter FIFO Empty Interrupt (tx fifo empty)
|
||||
#define RUART_IER_ELSI BIT2 //BIT2, Enable Receiver Line Status Interrupt (receiver line status)
|
||||
#define RUART_IER_EDSSI BIT3 //BIT3, Enable Modem Status Interrupt (modem status transition)
|
||||
#define RUART_IER_PTIME BIT7 //*BIT7 PTIME, Programmable THRE Interrupt Mode Enable
|
||||
|
||||
#define RUART_INT_ID_REG_OFF 0x08 //[R]
|
||||
// define Log UART Interrupt Indication ID
|
||||
/*
|
||||
IIR[3:0]:
|
||||
0000 = modem status
|
||||
0001 = no interrupt pending
|
||||
0010 = THR empty
|
||||
0100 = received data available
|
||||
0110 = receiver line status
|
||||
0111 = busy detect
|
||||
1100 = character timeout
|
||||
*/
|
||||
typedef enum {
|
||||
RU_IIR_MODEM_STATUS = 0, //Clear to send or data set ready or ring indicator or data carrier detect.
|
||||
RU_IIR_NO_PENDING = 1,
|
||||
RU_IIR_THR_EMPTY = 2, // TX FIFO level lower than threshold or FIFO empty
|
||||
RU_IIR_RX_RDY = 4, // RX data ready
|
||||
RU_IIR_RX_LINE_STATUS = 6, // Overrun/parity/framing errors or break interrupt
|
||||
RU_IIR_BUSY = 7,
|
||||
RU_IIR_CHAR_TIMEOUT = 12 // timeout: Rx data ready but no read
|
||||
} RUART_INT_ID;
|
||||
#define RUART_IIR_INT_PEND 0x01
|
||||
#define RUART_IIR_INT_ID (0x07<<1) //011(3), 010(2), 110(6), 001(1), 000(0)
|
||||
|
||||
#define RUART_FIFO_CTL_REG_OFF 0x08 //[W]
|
||||
// Define FIFO Control Register Bits
|
||||
typedef enum {
|
||||
RU_FCR_FIFO_EN = BIT0, // FIFO Enable.
|
||||
RU_FCR_RST_RX = BIT1, // RCVR FIFO Reset, self clear
|
||||
RU_FCR_RST_TX = BIT2, // XMIT FIFO Reset, self clear
|
||||
RU_FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty
|
||||
RU_FCR_TX_TRIG_2CH = BIT4, // TX Empty Trigger: 2 characters in the FIFO
|
||||
RU_FCR_TX_TRIG_QF = BIT5, // TX Empty Trigger: FIFO 1/4 full
|
||||
RU_FCR_TX_TRIG_HF = (BIT5|BIT4), // TX Empty Trigger: FIFO 1/2 full
|
||||
RU_FCR_TX_TRIG_MASK = (BIT5|BIT4), // TX Empty Trigger Bit Mask
|
||||
RU_FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO
|
||||
RU_FCR_RX_TRIG_QF = BIT6, // RCVR Trigger: FIFO 1/4 full
|
||||
RU_FCR_RX_TRIG_HF = BIT7, // RCVR Trigger: FIFO 1/2 full
|
||||
RU_FCR_RX_TRIG_AF = (BIT7|BIT6), // RCVR Trigger: FIFO 2 less than full
|
||||
RU_FCR_RX_TRIG_MASK = (BIT7|BIT6) // RCVR Trigger bits Mask
|
||||
} RUART_FIFO_CTRL;
|
||||
#define RUART_FIFO_CTL_REG_FIFO_ENABLE BIT0 //BIT0, FIFO Enable
|
||||
#define RUART_FIFO_CTL_REG_CLEAR_RXFIFO BIT1 //BIT1, Write 1 clear
|
||||
#define RUART_FIFO_CTL_REG_CLEAR_TXFIFO BIT2 //BIT2, Write 1 clear
|
||||
#define RUART_FIFO_CTL_REG_DMA_ENABLE BIT3 //BIT3 DMAM, DMA Mode
|
||||
#define RUART_FIFO_CTL_REG_TET (0x03<<4) //BIT4..5 TET, TX Empty Trigger: 00 = FIFO empty, 01 = 2 characters in the FIFO, 10 = FIFO 1/4 full, 11 = FIFO 1/2 full
|
||||
#define RUART_FIFO_CTL_REG_RT (0x03<<6) //BIT6..7 RT, RCVR Trigger: 00 = FIFO empty, 01 = 2 characters in the FIFO, 10 = FIFO 1/4 full, 11 = FIFO 1/2 full
|
||||
#define FIFO_CTL_DEFAULT_WITH_FIFO_DMA 0xC9
|
||||
#define FIFO_CTL_DEFAULT_WITH_FIFO 0xC1
|
||||
|
||||
#define RUART_MODEM_CTL_REG_OFF 0x10
|
||||
#define RUART_MCR_DTR BIT0 //BIT0, Data Terminal Ready (DTR)
|
||||
#define RUART_MCR_RTS BIT1 //*BIT1 Request to Send (RTS)
|
||||
#define RUART_MCR_OUT1 BIT2 //*BIT2 User designated Output 1 (OUT1)
|
||||
#define RUART_MCR_OUT2 BIT3 //*BIT3 User designated Output 2 (OUT2)
|
||||
#define RUART_MCR_LOOPBACK BIT4 //*BIT4, LoopBack Bit (LOOPBACK)
|
||||
#define RUART_MCL_AUTOFLOW_ENABLE BIT5 //BIT5, 0x20
|
||||
|
||||
|
||||
#define RUART_LINE_CTL_REG_OFF 0x0C
|
||||
// Define Line Control Register Bits
|
||||
typedef enum {
|
||||
RU_LCR_DLS_5B = 0, // Data Length: 5 bits
|
||||
RU_LCR_DLS_6B = BIT0, // Data Length: 6 bits
|
||||
RU_LCR_DLS_7B = BIT1, // Data Length: 7 bits
|
||||
RU_LCR_DLS_8B = (BIT1|BIT0), // Data Length: 7 bits
|
||||
|
||||
RU_LCR_STOP_1B = 0, // Number of stop bits: 1
|
||||
RU_LCR_STOP_2B = BIT2, // Number of stop bits: 1.5(data len=5) or 2
|
||||
|
||||
RU_LCR_PARITY_NONE = 0, // Parity Enable: 0
|
||||
RU_LCR_PARITY_ODD = BIT3, // Parity Enable: 1, Even Parity: 0
|
||||
RU_LCR_PARITY_EVEN = (BIT4|BIT3), // Parity Enable: 1, Even Parity: 1
|
||||
|
||||
RU_LCR_BC = BIT6, // Break Control Bit
|
||||
RU_LCR_DLAB = BIT7 // Divisor Latch Access Bit
|
||||
} RUART_LINE_CTRL;
|
||||
//*BIT6 Break Control Bit (BC)
|
||||
//*BIT4 Even Parity Select (EPS)
|
||||
//*BIT3 Parity Enable (PEN)
|
||||
//*BIT2 Number of stop bits (STOP)
|
||||
//*BIT1..0 Data Length Select (DLS)
|
||||
#define RUART_LINE_CTL_REG_DLAB_ENABLE BIT7 //BIT7, 0x80
|
||||
|
||||
#define RUART_LINE_STATUS_REG_OFF 0x14
|
||||
// Define Line Status Bit
|
||||
typedef enum {
|
||||
RU_LSR_DR = BIT0, // Data Ready bit
|
||||
RU_LSR_OE = BIT1, // Overrun error bit
|
||||
RU_LSR_PE = BIT2, // Parity Error bit
|
||||
RU_LSR_FE = BIT3, // Framing Error bit
|
||||
RU_LSR_BI = BIT4, // Break Interrupt bit
|
||||
RU_LSR_THRE = BIT5, // Transmit Holding Register Empty bit(IER_PTIME=0)
|
||||
RU_LSR_FIFOF = BIT5, // Transmit FIFO Full bit(IER_PTIME=1)
|
||||
RU_LSR_TEMT = BIT6, // Transmitter Empty bit
|
||||
RU_LSR_RFE = BIT7 // Receiver FIFO Error bit
|
||||
} RUART_LINE_STATUS;
|
||||
#define RUART_LINE_STATUS_REG_DR BIT0 //BIT0, Data Ready indicator
|
||||
#define RUART_LINE_STATUS_ERR_OVERRUN BIT1 //BIT1, Over Run
|
||||
#define RUART_LINE_STATUS_ERR_PARITY BIT2 //BIT2, Parity error
|
||||
#define RUART_LINE_STATUS_ERR_FRAMING BIT3 //BIT3, Framing error
|
||||
#define RUART_LINE_STATUS_ERR_BREAK BIT4 //BIT4, Break interrupt error
|
||||
#define RUART_LINE_STATUS_REG_THRE BIT5 //BIT5, 0x20, Transmit Holding Register Empty Interrupt enable
|
||||
#define RUART_LINE_STATUS_REG_TEMT BIT6 //BIT6, 0x40, Transmitter Empty indicator(bit)
|
||||
#define RUART_LINE_STATUS_ERR_RXFIFO BIT7 //BIT7, RX FIFO error
|
||||
#define RUART_LINE_STATUS_ERR (RUART_LINE_STATUS_ERR_OVERRUN|RUART_LINE_STATUS_ERR_PARITY| \
|
||||
RUART_LINE_STATUS_ERR_FRAMING|RUART_LINE_STATUS_ERR_BREAK| \
|
||||
RUART_LINE_STATUS_ERR_RXFIFO) //Line status error
|
||||
|
||||
#define RUART_MODEM_STATUS_REG_OFF 0x18 //Modem Status Register
|
||||
//* BIT7 Data Carrier Detect (DCD)
|
||||
//* BIT6 Ring Indicator (RI)
|
||||
//* BIT5 Data Set Ready (DSR)
|
||||
//* BIT4 Clear to Send (CTS)
|
||||
//* BIT3 Delta Data Carrier Detect (DDCD)
|
||||
//* BIT2 Trailing Edge of Ring Indicator (TERI)
|
||||
//* BIT1 Delta Data Set Ready (DDSR)
|
||||
//* BIT0 Delta Clear to Send (DCTS)
|
||||
#define RUART_SCRATCH_PAD_REG_OFF 0x1C //Scratch Pad Register
|
||||
#define RUART_SP_REG_RXBREAK_INT_STATUS BIT7 //BIT7, 0x80, Write 1 clear
|
||||
#define RUART_SP_REG_DBG_SEL (0x0F<<8) //[11:8], Debug port selection
|
||||
#define RUART_SP_REG_XFACTOR_ADJ (0x7FF<<16) //[26:16]
|
||||
|
||||
#define RUART_STS_REG_OFF 0x20
|
||||
#define RUART_STS_REG_RESET_RCV BIT3 //BIT3, 0x08, Reset Uart Receiver
|
||||
#define RUART_STS_REG_XFACTOR 0xF<<4
|
||||
|
||||
#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register
|
||||
#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register
|
||||
|
||||
#define RUART_MISC_CTL_REG_OFF 0x28
|
||||
#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3
|
||||
#define RUART_RXDMA_BURSTSIZE_MASK 0x1F00 //12:8
|
||||
|
||||
#define RUART_DEBUG_REG_OFF 0x3C
|
||||
|
||||
// RUART_LINE_CTL_REG_OFF (0x0C)
|
||||
#define BIT_SHIFT_LCR_WLS 0 // word length select: 0: 7 bits, 1: 8bits
|
||||
#define BIT_MASK_LCR_WLS_8BITS 0x1
|
||||
#define BIT_LCR_WLS(x)(((x) & BIT_MASK_LCR_WLS_8BITS) << BIT_SHIFT_LCR_WLS)
|
||||
#define BIT_CLR_LCR_WLS (~(BIT_MASK_LCR_WLS_8BITS << BIT_SHIFT_LCR_WLS))
|
||||
|
||||
#define BIT_SHIFT_LCR_STB 2 // Stop bit select: 0: no stop bit, 1: 1 stop bit
|
||||
#define BIT_MASK_LCR_STB_EN 0x1
|
||||
#define BIT_LCR_STB_EN(x)(((x) & BIT_MASK_LCR_STB_EN) << BIT_SHIFT_LCR_STB)
|
||||
#define BIT_INVC_LCR_STB_EN (~(BIT_MASK_LCR_STB_EN << BIT_SHIFT_LCR_STB))
|
||||
|
||||
#define BIT_SHIFT_LCR_PARITY_EN 3
|
||||
#define BIT_MASK_LCR_PARITY_EN 0x1
|
||||
#define BIT_LCR_PARITY_EN(x)(((x) & BIT_MASK_LCR_PARITY_EN) << BIT_SHIFT_LCR_PARITY_EN)
|
||||
#define BIT_INVC_LCR_PARITY_EN (~(BIT_MASK_LCR_PARITY_EN << BIT_SHIFT_LCR_PARITY_EN))
|
||||
|
||||
#define BIT_SHIFT_LCR_PARITY_TYPE 4
|
||||
#define BIT_MASK_LCR_PARITY_TYPE 0x1
|
||||
#define BIT_LCR_PARITY_TYPE(x)(((x) & BIT_MASK_LCR_PARITY_TYPE) << BIT_SHIFT_LCR_PARITY_TYPE)
|
||||
#define BIT_INVC_LCR_PARITY_TYPE (~(BIT_MASK_LCR_PARITY_TYPE << BIT_SHIFT_LCR_PARITY_TYPE))
|
||||
|
||||
#define BIT_SHIFT_LCR_STICK_PARITY_EN 5
|
||||
#define BIT_MASK_LCR_STICK_PARITY_EN 0x1
|
||||
#define BIT_LCR_STICK_PARITY_EN(x)(((x) & BIT_MASK_LCR_STICK_PARITY_EN) << BIT_SHIFT_LCR_STICK_PARITY_EN)
|
||||
#define BIT_INVC_LCR_STICK_PARITY_EN (~(BIT_MASK_LCR_STICK_PARITY_EN << BIT_SHIFT_LCR_STICK_PARITY_EN))
|
||||
|
||||
#define BIT_SHIFT_LCR_BREAK_CTRL 6
|
||||
#define BIT_MASK_LCR_BREAK_CTRL 0x1
|
||||
#define BIT_UART_LCR_BREAK_CTRL ((BIT_MASK_LCR_BREAK_CTRL) << BIT_SHIFT_LCR_BREAK_CTRL)
|
||||
|
||||
#define RUART_BAUD_RATE_2400 2400
|
||||
#define RUART_BAUD_RATE_4800 4800
|
||||
#define RUART_BAUD_RATE_9600 9600
|
||||
#define RUART_BAUD_RATE_19200 19200
|
||||
#define RUART_BAUD_RATE_38400 38400
|
||||
#define RUART_BAUD_RATE_57600 57600
|
||||
#define RUART_BAUD_RATE_115200 115200
|
||||
#define RUART_BAUD_RATE_921600 921600
|
||||
#define RUART_BAUD_RATE_1152000 1152000
|
||||
|
||||
#define HAL_RUART_READ32(UartIndex, addr) \
|
||||
HAL_READ32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
|
||||
#define HAL_RUART_WRITE32(UartIndex, addr, value) \
|
||||
HAL_WRITE32(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
|
||||
#define HAL_RUART_READ16(UartIndex, addr) \
|
||||
HAL_READ16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
|
||||
#define HAL_RUART_WRITE16(UartIndex, addr, value) \
|
||||
HAL_WRITE16(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
|
||||
#define HAL_RUART_READ8(UartIndex, addr) \
|
||||
HAL_READ8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr)
|
||||
#define HAL_RUART_WRITE8(UartIndex, addr, value) \
|
||||
HAL_WRITE8(UART0_REG_BASE+ (UartIndex*RUART_REG_OFF), addr, value)
|
||||
|
||||
#define UART_OVSR_POOL_MIN 1000
|
||||
#define UART_OVSR_POOL_MAX 2090
|
||||
#define DIVISOR_RESOLUTION 10
|
||||
#define JITTER_LIMIT 100
|
||||
#define UART_SCLK (200000000*5/12)
|
||||
|
||||
typedef struct _RUART_SPEED_SETTING_ {
|
||||
u32 BaudRate;
|
||||
u32 Ovsr;
|
||||
u32 Div;
|
||||
u32 Ovsr_adj;
|
||||
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
|
||||
u8 Ovsr_adj_max_bits; // 9: No parity, 10: with Parity
|
||||
u8 Ovsr_adj_bits;
|
||||
u16 *Ovsr_adj_map;
|
||||
u32 max_err; // 10 ~ 100: 30
|
||||
u32 Ovsr_min; // 10 ~ 20: 1000
|
||||
u32 Ovsr_max; // 10 ~ 20: 2000
|
||||
u32 divisor_resolution; // 1 ~ 20: 10
|
||||
u32 jitter_lim; // 50 ~ 100: 100
|
||||
u32 sclk; // 83.33333 MHz
|
||||
#endif
|
||||
}RUART_SPEED_SETTING, *PRUART_SPEED_SETTING;
|
||||
|
||||
typedef enum _UART_RXFIFO_TRIGGER_LEVEL_ {
|
||||
OneByte = 0x00, // 1
|
||||
FourBytes = 0x01, // 4
|
||||
EightBytes = 0x10, // 8
|
||||
FourteenBytes = 0x11 // 14
|
||||
}UART_RXFIFO_TRIGGER_LEVEL, *PUART_RXFIFO_TRIGGER_LEVEL;
|
||||
|
||||
typedef enum _RUART0_PINMUX_SELECT_ {
|
||||
RUART0_MUX_TO_GPIOC = S0,
|
||||
RUART0_MUX_TO_GPIOE = S1,
|
||||
RUART0_MUX_TO_GPIOA = S2
|
||||
}RUART0_PINMUX_SELECT, *PRUART0_PINMUX_SELECT;
|
||||
|
||||
typedef enum _RUART1_PINMUX_SELECT_ {
|
||||
RUART1_MUX_TO_GPIOD = S0,
|
||||
RUART1_MUX_TO_GPIOE = S1,
|
||||
RUART1_MUX_TO_GPIOB = S2
|
||||
}RUART1_PINMUX_SELECT, *PRUART1_PINMUX_SELECT;
|
||||
|
||||
typedef enum _RUART2_PINMUX_SELECT_ {
|
||||
RUART2_MUX_TO_GPIOA = S0,
|
||||
RUART2_MUX_TO_GPIOC = S1,
|
||||
RUART2_MUX_TO_GPIOD = S2
|
||||
}RUART2_PINMUX_SELECT, *PRUART2_PINMUX_SELECT;
|
||||
|
||||
typedef enum _RUART_FLOW_CONTROL_ {
|
||||
AUTOFLOW_DISABLE = 0,
|
||||
AUTOFLOW_ENABLE = 1
|
||||
}RUART_FLOW_CONTROL, *PRUART_FLOW_CONTROL;
|
||||
|
||||
typedef enum _RUART_WORD_LEN_SEL_ {
|
||||
RUART_WLS_7BITS = 0,
|
||||
RUART_WLS_8BITS = 1
|
||||
}RUART_WORD_LEN_SEL, *PRUART_WORD_LEN_SEL;
|
||||
|
||||
typedef enum _RUART_STOP_BITS_ {
|
||||
RUART_STOP_BIT_1 = 0,
|
||||
RUART_STOP_BIT_2 = 1
|
||||
}RUART_STOP_BITS, *PRUART_STOP_BITS;
|
||||
|
||||
typedef enum _RUART_PARITY_CONTROL_ {
|
||||
RUART_PARITY_DISABLE = 0,
|
||||
RUART_PARITY_ENABLE = 1
|
||||
}RUART_PARITY_CONTROL, *PRUART_PARITY_CONTROL;
|
||||
|
||||
typedef enum _RUART_PARITY_TYPE_ {
|
||||
RUART_ODD_PARITY = 0,
|
||||
RUART_EVEN_PARITY = 1
|
||||
}RUART_PARITY_TYPE, *PRUART_PARITY_TYPE;
|
||||
|
||||
typedef enum _RUART_STICK_PARITY_CONTROL_ {
|
||||
RUART_STICK_PARITY_DISABLE = 0,
|
||||
RUART_STICK_PARITY_ENABLE = 1
|
||||
}RUART_STICK_PARITY_CONTROL, *PRUART_STICK_PARITY_CONTROL;
|
||||
|
||||
typedef enum _UART_INT_ID_ {
|
||||
ModemStatus = 0,
|
||||
TxFifoEmpty = 1,
|
||||
ReceiverDataAvailable = 2,
|
||||
ReceivLineStatus = 3,
|
||||
TimeoutIndication = 6
|
||||
}UART_INT_ID, *PUART_INT_ID;
|
||||
|
||||
typedef enum _HAL_UART_State_
|
||||
{
|
||||
HAL_UART_STATE_NULL = 0x00, // UART hardware not been initial yet
|
||||
HAL_UART_STATE_READY = 0x10, // UART is initialed, ready to use
|
||||
HAL_UART_STATE_BUSY = 0x20, // UART hardware is busy on configuration
|
||||
HAL_UART_STATE_BUSY_TX = 0x21, // UART is buzy on TX
|
||||
HAL_UART_STATE_BUSY_RX = 0x22, // UART is busy on RX
|
||||
HAL_UART_STATE_BUSY_TX_RX = 0x23, // UART is busy on TX an RX
|
||||
HAL_UART_STATE_TIMEOUT = 0x30, // Transfer timeout
|
||||
HAL_UART_STATE_ERROR = 0x40 // UART Error
|
||||
}HAL_UART_State, *PHAL_UART_State;
|
||||
|
||||
typedef enum _HAL_UART_Status_
|
||||
{
|
||||
HAL_UART_STATUS_OK = 0x00, // Transfer OK
|
||||
HAL_UART_STATUS_TIMEOUT = 0x01, // Transfer Timeout
|
||||
HAL_UART_STATUS_ERR_OVERRUN = 0x02, // RX Over run
|
||||
HAL_UART_STATUS_ERR_PARITY = 0x04, // Parity error
|
||||
HAL_UART_STATUS_ERR_FRAM = 0x08, // Framing Error
|
||||
HAL_UART_STATUS_ERR_BREAK = 0x10, // Break Interrupt
|
||||
HAL_UART_STATUS_ERR_PARA = 0x20, // Parameter error
|
||||
HAL_UART_STATUS_ERR_RXFIFO = 0x80, // RX FIFO error
|
||||
}HAL_UART_Status, *PHAL_UART_Status;
|
||||
|
||||
u32
|
||||
HalRuartGetDebugValueRtl8195a(
|
||||
IN VOID* Data,
|
||||
IN u32 DbgSel
|
||||
);
|
||||
|
||||
#if 0
|
||||
u32
|
||||
FindElementIndex(
|
||||
u32 Element,
|
||||
u32* Array
|
||||
);
|
||||
#endif
|
||||
|
||||
VOID
|
||||
RuartResetRxFifoRtl8195a(
|
||||
IN u8 UartIndex
|
||||
);
|
||||
#if 0
|
||||
VOID
|
||||
RuartBusDomainEnableRtl8195a(
|
||||
IN u8 UartIndex
|
||||
);
|
||||
#endif
|
||||
|
||||
HAL_Status
|
||||
HalRuartResetRxFifoRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartInitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartDeInitRtl8195a(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartPutCRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 TxData
|
||||
);
|
||||
|
||||
u32
|
||||
HalRuartSendRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 *pTxData,
|
||||
IN u32 Length,
|
||||
IN u32 Timeout
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartIntSendRtl8195a(
|
||||
IN VOID *Data, // PHAL_RUART_ADAPTER
|
||||
IN u8 *pTxData, // the Buffer to be send
|
||||
IN u32 Length // the length of data to be send
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartDmaSendRtl8195a(
|
||||
IN VOID *Data, // PHAL_RUART_ADAPTER
|
||||
IN u8 *pTxData, // the Buffer to be send
|
||||
IN u32 Length // the length of data to be send
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartStopSendRtl8195a(
|
||||
IN VOID *Data // PHAL_RUART_ADAPTER
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartGetCRtl8195a(
|
||||
IN VOID *Data,
|
||||
OUT u8 *pRxByte
|
||||
);
|
||||
|
||||
u32
|
||||
HalRuartRecvRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 *pRxData,
|
||||
IN u32 Length,
|
||||
IN u32 Timeout
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartIntRecvRtl8195a(
|
||||
IN VOID *Data, ///< RUART Adapter
|
||||
IN u8 *pRxData, ///< Rx buffer
|
||||
IN u32 Length // buffer length
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartDmaRecvRtl8195a(
|
||||
IN VOID *Data, ///< RUART Adapter
|
||||
IN u8 *pRxData, ///< Rx buffer
|
||||
IN u32 Length // buffer length
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartStopRecvRtl8195a(
|
||||
IN VOID *Data // PHAL_RUART_ADAPTER
|
||||
);
|
||||
|
||||
u8
|
||||
HalRuartGetIMRRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ROM_ VOID
|
||||
HalRuartSetIMRRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartDmaInitRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartRTSCtrlRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN BOOLEAN RtsCtrl
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartRegIrqRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartIntEnableRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartIntDisableRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartAdapterLoadDefRtl8195a(
|
||||
IN VOID *pAdp,
|
||||
IN u8 UartIdx
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartTxGdmaLoadDefRtl8195a(
|
||||
IN VOID *pAdp,
|
||||
IN VOID *pCfg
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartRxGdmaLoadDefRtl8195a(
|
||||
IN VOID *pAdp,
|
||||
IN VOID *pCfg
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status HalRuartIntSendRtl8195aV02(
|
||||
IN VOID *Data, // PHAL_RUART_ADAPTER
|
||||
IN u8 *pTxData, // the Buffer to be send
|
||||
IN u32 Length // the length of data to be send
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartIntRecvRtl8195aV02(
|
||||
IN VOID *Data, ///< RUART Adapter
|
||||
IN u8 *pRxData, ///< Rx buffer
|
||||
IN u32 Length // buffer length
|
||||
);
|
||||
|
||||
_LONG_CALL_ s32
|
||||
FindElementIndex_v02(
|
||||
u32 Element, ///< RUART Baudrate
|
||||
u32* Array, ///< Pre-defined Baudrate Array
|
||||
u32 ElementNo
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status HalRuartInitRtl8195a_v02(IN VOID *Data);
|
||||
|
||||
// New added function 2015/04/20
|
||||
HAL_Status
|
||||
HalRuartResetTxFifoRtl8195a(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartResetRxFifoRtl8195a_Patch(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartResetTRxFifoRtl8195a(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartSetBaudRateRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartEnableRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartDisableRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartFlowCtrlRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u32
|
||||
_UartTxDmaIrqHandle_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
u32
|
||||
_UartRxDmaIrqHandle_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartDmaSendRtl8195a_Patch(
|
||||
IN VOID *Data,
|
||||
IN u8 *pTxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartDmaRecvRtl8195a_Patch(
|
||||
IN VOID *Data,
|
||||
IN u8 *pRxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartMultiBlkDmaSendRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 *pTxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartMultiBlkDmaRecvRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 *pRxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
RuartIsTimeout (
|
||||
u32 StartCount,
|
||||
u32 TimeoutCnt
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartStopRecvRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
HAL_Status
|
||||
HalRuartStopSendRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartEnterCriticalRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
VOID
|
||||
HalRuartExitCriticalRtl8195a(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#if CONFIG_CHIP_E_CUT
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartResetTxFifoRtl8195a_V04(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartResetRxFifoRtl8195a_V04(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartResetTRxFifoRtl8195a_V04(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartSetBaudRateRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartInitRtl8195a_V04(
|
||||
IN VOID *Data ///< RUART Adapter
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartEnableRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartDisableRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartFlowCtrlRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ u32
|
||||
_UartTxDmaIrqHandle_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ u32
|
||||
_UartRxDmaIrqHandle_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartDmaSendRtl8195a_V04(
|
||||
IN VOID *Data,
|
||||
IN u8 *pTxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartDmaRecvRtl8195a_V04(
|
||||
IN VOID *Data,
|
||||
IN u8 *pRxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartMultiBlkDmaSendRtl8195a_V04(
|
||||
IN VOID *Data,
|
||||
IN u8 *pTxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartMultiBlkDmaRecvRtl8195a_V04(
|
||||
IN VOID *Data,
|
||||
IN u8 *pRxData,
|
||||
IN u32 Length
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartStopRecvRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ HAL_Status
|
||||
HalRuartStopSendRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
HalRuartEnterCriticalRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
_LONG_CALL_ VOID
|
||||
HalRuartExitCriticalRtl8195a_V04(
|
||||
IN VOID *Data
|
||||
);
|
||||
|
||||
#endif // #if CONFIG_CHIP_E_CUT
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,432 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#ifndef _RTL8195A_USB_H_
|
||||
#define _RTL8195A_USB_H_
|
||||
|
||||
|
||||
// common command for USB
|
||||
#define USB_CMD_TX_ETH 0x83 // request to TX a 802.3 packet
|
||||
#define USB_CMD_TX_WLN 0x81 // request to TX a 802.11 packet
|
||||
#define USB_CMD_H2C 0x11 // H2C(host to device) command packet
|
||||
#define USB_CMD_MEMRD 0x51 // request to read a block of memory data
|
||||
#define USB_CMD_MEMWR 0x53 // request to write a block of memory
|
||||
#define USB_CMD_MEMST 0x55 // request to set a block of memory with a value
|
||||
#define USB_CMD_STARTUP 0x61 // request to jump to the start up function
|
||||
|
||||
#define USB_CMD_RX_ETH 0x82 // indicate a RX 802.3 packet
|
||||
#define USB_CMD_RX_WLN 0x80 // indicate a RX 802.11 packet
|
||||
#define USB_CMD_C2H 0x10 // C2H(device to host) command packet
|
||||
#define USB_CMD_MEMRD_RSP 0x50 // response to memory block read command
|
||||
#define USB_CMD_MEMWR_RSP 0x52 // response to memory write command
|
||||
#define USB_CMD_MEMST_RSP 0x54 // response to memory set command
|
||||
#define USB_CMD_STARTED 0x60 // indicate the program has jumped to the given function
|
||||
|
||||
|
||||
// TODO: This data structer just for test, we should modify it for the normal driver
|
||||
typedef struct _USB_TX_DESC{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
#else
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
u32 rsvd0:24;
|
||||
#else
|
||||
u32 rsvd0:24;
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 rsvd1;
|
||||
|
||||
// u4Byte 3
|
||||
u32 rsvd2;
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} USB_TX_DESC, *PUSB_TX_DESC;
|
||||
|
||||
#define SIZE_USB_TX_DESC sizeof(USB_TX_DESC)
|
||||
|
||||
// TX Desc for Memory Write command
|
||||
typedef struct _USB_TX_DESC_MW{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
#else
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
u32 reply:1; // bit[8], request to send a reply message
|
||||
u32 rsvd0:23;
|
||||
#else
|
||||
u32 rsvd0:23;
|
||||
u32 reply:1; // bit[8], request to send a reply message
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_addr; // memory write start address
|
||||
|
||||
// u4Byte 3
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 write_len:16; // bit[15:0], the length to write
|
||||
u32 rsvd2:16; // bit[31:16]
|
||||
#else
|
||||
u32 rsvd2:16; // bit[31:16]
|
||||
u32 write_len:16; // bit[15:0], the length to write
|
||||
#endif
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} USB_TX_DESC_MW, *PUSB_TX_DESC_MW;
|
||||
|
||||
// TX Desc for Memory Read command
|
||||
typedef struct _USB_TX_DESC_MR{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
#else
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
u32 rsvd0:24;
|
||||
#else
|
||||
u32 rsvd0:24;
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_addr; // memory write start address
|
||||
|
||||
// u4Byte 3
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 read_len:16; // bit[15:0], the length to read
|
||||
u32 rsvd2:16; // bit[31:16]
|
||||
#else
|
||||
u32 rsvd2:16; // bit[31:16]
|
||||
u32 read_len:16; // bit[15:0], the length to read
|
||||
#endif
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} USB_TX_DESC_MR, *PUSB_TX_DESC_MR;
|
||||
|
||||
// TX Desc for Memory Set command
|
||||
typedef struct _USB_TX_DESC_MS{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
#else
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
u32 data:8; // bit[8:15], the value to be written to the memory
|
||||
u32 reply:1; // bit[16], request to send a reply message
|
||||
u32 rsvd0:15;
|
||||
#else
|
||||
u32 rsvd0:15;
|
||||
u32 reply:1; // bit[16], request to send a reply message
|
||||
u32 data:8; // bit[8:15], the value to be written to the memory
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_addr; // memory write start address
|
||||
|
||||
// u4Byte 3
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 write_len:16; // bit[15:0], the length to write
|
||||
u32 rsvd2:16; // bit[31:16]
|
||||
#else
|
||||
u32 rsvd2:16; // bit[31:16]
|
||||
u32 write_len:16; // bit[15:0], the length to write
|
||||
#endif
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} USB_TX_DESC_MS, *PUSB_TX_DESC_MS;
|
||||
|
||||
// TX Desc for Jump to Start command
|
||||
typedef struct _USB_TX_DESC_JS{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
#else
|
||||
u32 bus_agg_num:8; // bit[31:24], the bus aggregation number
|
||||
u32 offset:8; // bit[23:16], store the sizeof(SDIO_TX_DESC)
|
||||
u32 txpktsize:16; // bit[15:0]
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
u32 rsvd0:24;
|
||||
#else
|
||||
u32 rsvd0:24;
|
||||
u32 type:8; // bit[7:0], the packet type
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_fun; // the pointer of the startup function
|
||||
|
||||
// u4Byte 3
|
||||
u32 rsvd2;
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} USB_TX_DESC_JS, *PUSB_TX_DESC_JS;
|
||||
|
||||
typedef struct _USB_RX_DESC{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 rsvd0:6; // bit[29:24]
|
||||
u32 icv:1; // bit[30], ICV error
|
||||
u32 crc:1; // bit[31], CRC error
|
||||
#else
|
||||
u32 crc:1; // bit[31], CRC error
|
||||
u32 icv:1; // bit[30], ICV error
|
||||
u32 rsvd0:6; // bit[29:24]
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
#else
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 rsvd2;
|
||||
|
||||
// u4Byte 3
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd4;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd5;
|
||||
} USB_RX_DESC, *PUSB_RX_DESC;
|
||||
|
||||
|
||||
// For memory read command
|
||||
typedef struct _USB_RX_DESC_MR{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 rsvd0:8; // bit[31:24]
|
||||
#else
|
||||
u32 rsvd0:8; // bit[31:24]
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
#else
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_addr;
|
||||
|
||||
// u4Byte 3
|
||||
u32 rsvd2;
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} USB_RX_DESC_MR, *PUSB_RX_DESC_MR;
|
||||
|
||||
// For memory write reply command
|
||||
typedef struct _USB_RX_DESC_MW{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 rsvd0:8; // bit[31:24]
|
||||
#else
|
||||
u32 rsvd0:8; // bit[31:24]
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
#else
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_addr;
|
||||
|
||||
// u4Byte 3
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 write_len:16; // bit[15:0], the type of this packet
|
||||
u32 result:8; // bit[23:16], the result of memory write command
|
||||
u32 rsvd2:8; // bit[31:24]
|
||||
#else
|
||||
u32 rsvd2:8; // bit[31:24]
|
||||
u32 result:8; // bit[23:16], the result of memory write command
|
||||
u32 write_len:16; // bit[15:0], the type of this packet
|
||||
#endif
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} USB_RX_DESC_MW, *PUSB_RX_DESC_MW;
|
||||
|
||||
// For memory set reply command
|
||||
typedef struct _USB_RX_DESC_MS{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 rsvd0:8; // bit[31:24]
|
||||
#else
|
||||
u32 rsvd0:8; // bit[31:24]
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
#else
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 start_addr;
|
||||
|
||||
// u4Byte 3
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 write_len:16; // bit[15:0], the type of this packet
|
||||
u32 result:8; // bit[23:16], the result of memory write command
|
||||
u32 rsvd2:8; // bit[31:24]
|
||||
#else
|
||||
u32 rsvd2:8; // bit[31:24]
|
||||
u32 result:8; // bit[23:16], the result of memory write command
|
||||
u32 write_len:16; // bit[15:0], the type of this packet
|
||||
#endif
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd4;
|
||||
} USB_RX_DESC_MS, *PUSB_RX_DESC_MS;
|
||||
|
||||
// For firmware ready reply command
|
||||
typedef struct _USB_RX_DESC_FS{
|
||||
// u4Byte 0
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 rsvd0:8; // bit[31:24]
|
||||
#else
|
||||
u32 rsvd0:8; // bit[31:24]
|
||||
u32 offset:8; // bit[23:16], the offset from the packet start to the buf start, also means the size of RX Desc
|
||||
u32 pkt_len:16; // bit[15:0], the packet size
|
||||
#endif
|
||||
|
||||
// u4Byte 1
|
||||
#if (SYSTEM_ENDIAN==PLATFORM_LITTLE_ENDIAN)
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
#else
|
||||
u32 rsvd1:24; // bit[31:8]
|
||||
u32 type:8; // bit[7:0], the type of this packet
|
||||
#endif
|
||||
|
||||
// u4Byte 2
|
||||
u32 rsvd2;
|
||||
|
||||
// u4Byte 3
|
||||
u32 rsvd3;
|
||||
|
||||
// u4Byte 4
|
||||
u32 rsvd4;
|
||||
|
||||
// u4Byte 5
|
||||
u32 rsvd5;
|
||||
} USB_RX_DESC_FS, *PUSB_RX_DESC_FS;
|
||||
|
||||
|
||||
#define SIZE_USB_RX_DESC sizeof(USB_RX_DESC)
|
||||
|
||||
#endif // #ifndef _RTL8195A_USB_H_
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2014 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#ifndef _RTL8195A_WDT_H_
|
||||
#define _RTL8195A_WDT_H_
|
||||
|
||||
#define WDGTIMERELY (10*1024) //us
|
||||
|
||||
typedef struct _WDG_REG_ {
|
||||
u16 WdgScalar;
|
||||
u8 WdgEnByte;
|
||||
u8 WdgClear:1;
|
||||
u8 WdgCunLimit:4;
|
||||
u8 Rsvd:1;
|
||||
u8 WdgMode:1;
|
||||
u8 WdgToISR:1;
|
||||
}WDG_REG, *PWDG_REG;
|
||||
|
||||
typedef struct _WDG_ADAPTER_ {
|
||||
|
||||
WDG_REG Ctrl;
|
||||
IRQ_HANDLE IrqHandle;
|
||||
TIMER_ADAPTER WdgGTimer;
|
||||
VOID (*UserCallback)(u32 callback_id); // User callback function
|
||||
u32 callback_id;
|
||||
}WDG_ADAPTER, *PWDG_ADAPTER;
|
||||
|
||||
typedef enum _WDG_CNTLMT_ {
|
||||
CNT1H = 0,
|
||||
CNT3H = 1,
|
||||
CNT7H = 2,
|
||||
CNTFH = 3,
|
||||
CNT1FH = 4,
|
||||
CNT3FH = 5,
|
||||
CNT7FH = 6,
|
||||
CNTFFH = 7,
|
||||
CNT1FFH = 8,
|
||||
CNT3FFH = 9,
|
||||
CNT7FFH = 10,
|
||||
CNTFFFH = 11
|
||||
}WDG_CNTLMT, *PWDG_CNTLMT;
|
||||
|
||||
|
||||
typedef enum _WDG_MODE_ {
|
||||
INT_MODE = 0,
|
||||
RESET_MODE = 1
|
||||
}WDG_MODE, *PWDG_MODE;
|
||||
|
||||
extern VOID
|
||||
WDGInitial(
|
||||
IN u32 Period
|
||||
);
|
||||
|
||||
extern VOID
|
||||
WDGIrqInitial(
|
||||
VOID
|
||||
);
|
||||
|
||||
extern VOID
|
||||
WDGIrqInitial(
|
||||
VOID
|
||||
);
|
||||
|
||||
extern VOID
|
||||
WDGStop(
|
||||
VOID
|
||||
);
|
||||
|
||||
extern VOID
|
||||
WDGRefresh(
|
||||
VOID
|
||||
);
|
||||
|
||||
extern VOID
|
||||
WDGIrqCallBackReg(
|
||||
IN VOID *CallBack,
|
||||
IN u32 Id
|
||||
);
|
||||
|
||||
#endif //_RTL8195A_WDT_H_
|
||||
|
|
@ -0,0 +1,389 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "platform_autoconf.h"
|
||||
#include "diag.h"
|
||||
#include "rtl8195a_adc.h"
|
||||
#include "hal_adc.h"
|
||||
|
||||
#ifdef CONFIG_ADC_EN
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CInit8195a
|
||||
//
|
||||
// Description:
|
||||
// To initialize I2C module by using the given data.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the DeInit process.
|
||||
// _EXIT_SUCCESS if the initialization succeeded.
|
||||
// _EXIT_FAILURE if the initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-04-02.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalADCInit8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
|
||||
u32 AdcTempDat;
|
||||
u8 AdcTempIdx = pHalAdcInitData->ADCIdx;
|
||||
|
||||
/* Enable ADC power cut */
|
||||
/*
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
|
||||
AdcTempDat |= BIT_ADC_PWR_AUTO;
|
||||
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
|
||||
*/
|
||||
|
||||
/* ADC Control register set-up*/
|
||||
AdcTempDat = 0;
|
||||
AdcTempDat |= (BIT_CTRL_ADC_COMP_ONLY(pHalAdcInitData->ADCCompOnly) |
|
||||
BIT_CTRL_ADC_ONESHOT(pHalAdcInitData->ADCOneShotEn) |
|
||||
BIT_CTRL_ADC_OVERWRITE(pHalAdcInitData->ADCOverWREn) |
|
||||
BIT_CTRL_ADC_ENDIAN(pHalAdcInitData->ADCEndian) |
|
||||
BIT_CTRL_ADC_BURST_SIZE(pHalAdcInitData->ADCBurstSz) |
|
||||
BIT_CTRL_ADC_THRESHOLD(pHalAdcInitData->ADCOneShotTD) |
|
||||
BIT_CTRL_ADC_DBG_SEL(pHalAdcInitData->ADCDbgSel));
|
||||
HAL_ADC_WRITE32(REG_ADC_CONTROL,AdcTempDat);
|
||||
|
||||
DBG_8195A_ADC_LVL(HAL_ADC_LVL,"REG_ADC_CONTROL:%x\n", HAL_ADC_READ32(REG_ADC_CONTROL));
|
||||
|
||||
/* ADC compare value and compare method setting*/
|
||||
switch (AdcTempIdx) {
|
||||
case ADC0_SEL:
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
|
||||
AdcTempDat &= ~(BIT_ADC_COMP_TH_0(0xFFFF));
|
||||
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_0(pHalAdcInitData->ADCCompTD);
|
||||
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
|
||||
break;
|
||||
|
||||
case ADC1_SEL:
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_L);
|
||||
AdcTempDat &= ~(BIT_ADC_COMP_TH_1(0xFFFF));
|
||||
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_1(pHalAdcInitData->ADCCompTD);
|
||||
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_L, AdcTempDat);
|
||||
break;
|
||||
|
||||
case ADC2_SEL:
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
|
||||
AdcTempDat &= ~(BIT_ADC_COMP_TH_2(0xFFFF));
|
||||
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_2(pHalAdcInitData->ADCCompTD);
|
||||
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
|
||||
break;
|
||||
|
||||
case ADC3_SEL:
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_VALUE_H);
|
||||
AdcTempDat &= ~(BIT_ADC_COMP_TH_3(0xFFFF));
|
||||
AdcTempDat |= BIT_CTRL_ADC_COMP_TH_3(pHalAdcInitData->ADCCompTD);
|
||||
HAL_ADC_WRITE32(REG_ADC_COMP_VALUE_H, AdcTempDat);
|
||||
break;
|
||||
default:
|
||||
return _EXIT_FAILURE;
|
||||
}
|
||||
|
||||
/* ADC compare mode setting */
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_COMP_SET);
|
||||
AdcTempDat &= (~(0x01 << pHalAdcInitData->ADCIdx));
|
||||
AdcTempDat |= (BIT_CTRL_ADC_COMP_0_EN(pHalAdcInitData->ADCCompCtrl) <<
|
||||
pHalAdcInitData->ADCIdx);
|
||||
HAL_ADC_WRITE32(REG_ADC_COMP_SET, AdcTempDat);
|
||||
|
||||
/* ADC audio mode set-up */
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
|
||||
AdcTempDat &= ~(BIT_ADC_AUDIO_EN);
|
||||
AdcTempDat |= BIT_CTRL_ADC_AUDIO_EN(pHalAdcInitData->ADCAudioEn);
|
||||
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
|
||||
|
||||
/* ADC enable manually setting */
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
|
||||
AdcTempDat &= ~(BIT_ADC_EN_MANUAL);
|
||||
AdcTempDat |= BIT_CTRL_ADC_EN_MANUAL(pHalAdcInitData->ADCEnManul);
|
||||
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
|
||||
|
||||
|
||||
/* ADC analog parameter 0 */
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
|
||||
DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
|
||||
//AdcTempDat |= (BIT0);
|
||||
if (pHalAdcInitData->ADCInInput == 1){
|
||||
AdcTempDat &= (~BIT14);
|
||||
}
|
||||
else {
|
||||
AdcTempDat |= (BIT14);
|
||||
}
|
||||
AdcTempDat &= (~(BIT3|BIT2));
|
||||
|
||||
/* Adjust VCM for C-Cut*/
|
||||
#ifdef CONFIG_CHIP_C_CUT
|
||||
AdcTempDat |= (BIT22);
|
||||
#endif
|
||||
|
||||
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD0, AdcTempDat);
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD0);
|
||||
DBG_ADC_INFO("AD0:%x\n", AdcTempDat);
|
||||
|
||||
/* ADC analog parameter 1 */
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
|
||||
AdcTempDat &= (~BIT1);
|
||||
AdcTempDat |= (BIT2|BIT0);
|
||||
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD1, AdcTempDat);
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD1);
|
||||
DBG_ADC_INFO("AD1:%x\n", AdcTempDat);
|
||||
|
||||
/* ADC analog parameter 2 */
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
|
||||
DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
|
||||
AdcTempDat = 0x67884400;
|
||||
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD2, AdcTempDat);
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD2);
|
||||
DBG_ADC_INFO("AD2:%x\n", AdcTempDat);
|
||||
|
||||
/* ADC analog parameter 3 */
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
|
||||
DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
|
||||
AdcTempDat = 0x77780039;
|
||||
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD3, AdcTempDat);
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD3);
|
||||
DBG_ADC_INFO("AD3:%x\n", AdcTempDat);
|
||||
|
||||
/* ADC analog parameter 4 */
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
|
||||
DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
|
||||
AdcTempDat = 0x0004d501;
|
||||
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD4, AdcTempDat);
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD4);
|
||||
DBG_ADC_INFO("AD4:%x\n", AdcTempDat);
|
||||
|
||||
/* ADC analog parameter 5 */
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
|
||||
DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
|
||||
AdcTempDat = 0x1E010800;
|
||||
HAL_ADC_WRITE32(REG_ADC_ANAPAR_AD5, AdcTempDat);
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_ANAPAR_AD5);
|
||||
DBG_ADC_INFO("AD5:%x\n", AdcTempDat);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CInit8195a
|
||||
//
|
||||
// Description:
|
||||
// To initialize I2C module by using the given data.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the DeInit process.
|
||||
// _EXIT_SUCCESS if the initialization succeeded.
|
||||
// _EXIT_FAILURE if the initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-04-02.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalADCDeInit8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
u32 AdcTempDat;
|
||||
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
|
||||
AdcTempDat &= ~(BIT_ADC_PWR_AUTO);
|
||||
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CIntrCtrl8195a
|
||||
//
|
||||
// Description:
|
||||
// Modify the I2C interrupt mask according to the given value
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the enable process.
|
||||
// _EXIT_SUCCESS if the de-initialization succeeded.
|
||||
// _EXIT_FAILURE if the de-initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalADCEnableRtl8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
//PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
|
||||
u32 AdcTempDat;
|
||||
DBG_ADC_INFO("HalADCEnableRtl8195a\n");
|
||||
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_POWER);
|
||||
|
||||
AdcTempDat &= (~BIT_ADC_PWR_AUTO);
|
||||
AdcTempDat |= 0x02;
|
||||
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
|
||||
AdcTempDat |= 0x04;
|
||||
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
|
||||
AdcTempDat &= (~0x08);
|
||||
HAL_ADC_WRITE32(REG_ADC_POWER, AdcTempDat);
|
||||
|
||||
AdcTempDat = (u32)HAL_ADC_READ32(REG_ADC_POWER);
|
||||
DBG_ADC_INFO("HalADCEnableRtl8195a, power reg:%x\n",AdcTempDat);
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CIntrCtrl8195a
|
||||
//
|
||||
// Description:
|
||||
// Modify the I2C interrupt mask according to the given value
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the enable process.
|
||||
// _EXIT_SUCCESS if the de-initialization succeeded.
|
||||
// _EXIT_FAILURE if the de-initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalADCIntrCtrl8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_ADC_INIT_DAT pHalAdcInitData = (PHAL_ADC_INIT_DAT)Data;
|
||||
|
||||
HAL_ADC_WRITE32(REG_ADC_INTR_EN, pHalAdcInitData->ADCIntrMSK);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CReceiveRtl8195a
|
||||
//
|
||||
// Description:
|
||||
// Directly read one data byte a I2C data fifo.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The first data fifo content.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
u32
|
||||
HalADCReceiveRtl8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
u32 AdcTempDat;
|
||||
|
||||
AdcTempDat = HAL_ADC_READ32(REG_ADC_FIFO_READ);
|
||||
|
||||
return (AdcTempDat);
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CReadRegRtl8195a
|
||||
//
|
||||
// Description:
|
||||
// Directly read a I2C register according to the register offset.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
// [in] I2CReg -
|
||||
// The I2C register offset.
|
||||
//
|
||||
// Return:
|
||||
// The register content in u32 format.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
u32
|
||||
HalADCReadRegRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 I2CReg
|
||||
){
|
||||
u32 AdcTempDat;
|
||||
|
||||
AdcTempDat = HAL_ADC_READ32(I2CReg);
|
||||
return (AdcTempDat);
|
||||
}
|
||||
|
||||
#endif // CONFIG_ADC_EN
|
||||
|
|
@ -0,0 +1,269 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_dac.h"
|
||||
#include "hal_dac.h"
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalDACInit8195a
|
||||
//
|
||||
// Description:
|
||||
// To initialize DAC module by using the given data.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The DAC parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the DeInit process.
|
||||
// _EXIT_SUCCESS if the initialization succeeded.
|
||||
// _EXIT_FAILURE if the initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-04-15.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalDACInit8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
|
||||
u32 DacTempDat;
|
||||
u8 DacTempIdx = pHalDacInitData->DACIdx;
|
||||
|
||||
/* Enable DAC power cut */
|
||||
DacTempDat = HAL_DAC_READ32(0, REG_DAC_PWR_CTRL);
|
||||
DacTempDat |= BIT_DAC_PWR_AUTO;
|
||||
|
||||
HAL_DAC_WRITE32(0, REG_DAC_PWR_CTRL, DacTempDat);
|
||||
|
||||
/* Disable DAC module first */
|
||||
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, 0);
|
||||
|
||||
/* Setup DAC module */
|
||||
DacTempDat = 0;
|
||||
DacTempDat |= (BIT_CTRL_DAC_SPEED(pHalDacInitData->DACDataRate) |
|
||||
BIT_CTRL_DAC_ENDIAN(pHalDacInitData->DACEndian) |
|
||||
BIT_CTRL_DAC_FILTER_SETTLE(pHalDacInitData->DACFilterSet) |
|
||||
BIT_CTRL_DAC_BURST_SIZE(pHalDacInitData->DACBurstSz) |
|
||||
BIT_CTRL_DAC_DBG_SEL(pHalDacInitData->DACDbgSel) |
|
||||
BIT_CTRL_DAC_DSC_DBG_SEL(pHalDacInitData->DACDscDbgSel) |
|
||||
BIT_CTRL_DAC_BYPASS_DSC(pHalDacInitData->DACBPDsc) |
|
||||
BIT_CTRL_DAC_DELTA_SIGMA(pHalDacInitData->DACDeltaSig));
|
||||
|
||||
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CInit8195a
|
||||
//
|
||||
// Description:
|
||||
// To initialize I2C module by using the given data.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the DeInit process.
|
||||
// _EXIT_SUCCESS if the initialization succeeded.
|
||||
// _EXIT_FAILURE if the initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-04-02.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalDACDeInit8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
|
||||
u32 DacTempDat;
|
||||
|
||||
DacTempDat = HAL_DAC_READ32(pHalDacInitData->DACIdx, REG_DAC_CTRL);
|
||||
DacTempDat &= (~BIT_DAC_FIFO_EN);
|
||||
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_CTRL ,DacTempDat);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CIntrCtrl8195a
|
||||
//
|
||||
// Description:
|
||||
// Modify the I2C interrupt mask according to the given value
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the enable process.
|
||||
// _EXIT_SUCCESS if the de-initialization succeeded.
|
||||
// _EXIT_FAILURE if the de-initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalDACEnableRtl8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
|
||||
u32 DacTempDat;
|
||||
u8 DacTempIdx = pHalDacInitData->DACIdx;
|
||||
|
||||
DacTempDat = HAL_DAC_READ32(DacTempIdx, REG_DAC_CTRL);
|
||||
DacTempDat &= (~BIT_DAC_FIFO_EN);
|
||||
|
||||
DacTempDat |= BIT_CTRL_DAC_FIFO_EN(pHalDacInitData->DACEn);
|
||||
HAL_DAC_WRITE32(DacTempIdx, REG_DAC_CTRL, DacTempDat);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CIntrCtrl8195a
|
||||
//
|
||||
// Description:
|
||||
// Modify the I2C interrupt mask according to the given value
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the enable process.
|
||||
// _EXIT_SUCCESS if the de-initialization succeeded.
|
||||
// _EXIT_FAILURE if the de-initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
RTK_STATUS
|
||||
HalDACIntrCtrl8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
|
||||
|
||||
HAL_DAC_WRITE32(pHalDacInitData->DACIdx, REG_DAC_INTR_CTRL, pHalDacInitData->DACIntrMSK);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CReceiveRtl8195a
|
||||
//
|
||||
// Description:
|
||||
// Directly read one data byte a I2C data fifo.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The first data fifo content.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
u8
|
||||
HalDACSendRtl8195a(
|
||||
IN VOID *Data
|
||||
){
|
||||
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalDACReadRegRtl8195a
|
||||
//
|
||||
// Description:
|
||||
//
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The DAC parameter data struct.
|
||||
// [in] I2CReg -
|
||||
// The DAC register offset.
|
||||
//
|
||||
// Return:
|
||||
// The DAC register content in u32 format.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-04-15.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
u32
|
||||
HalDACReadRegRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 I2CReg
|
||||
){
|
||||
PHAL_DAC_INIT_DAT pHalDacInitData = (PHAL_DAC_INIT_DAT)Data;
|
||||
|
||||
//DBG_8195A_DAC("dac read reg idx:%x\n",pHalDacInitData->DACIdx);
|
||||
//DBG_8195A_DAC("dac read reg offset:%x\n",I2CReg);
|
||||
|
||||
return (u32)HAL_DAC_READ32(pHalDacInitData->DACIdx, I2CReg);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,295 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_gdma.h"
|
||||
#include "hal_gdma.h"
|
||||
|
||||
#ifdef CONFIG_GDMA_EN
|
||||
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
BOOL
|
||||
HalGdmaChBlockSetingRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
PGDMA_CH_LLI_ELE pLliEle;
|
||||
struct GDMA_CH_LLI *pGdmaChLli;
|
||||
struct BLOCK_SIZE_LIST *pGdmaChBkLi;
|
||||
u32 MultiBlockCount = pHalGdmaAdapter->MaxMuliBlock;
|
||||
u32 CtlxLow, CtlxUp, CfgxLow, CfgxUp;
|
||||
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
|
||||
u8 ChNum = pHalGdmaAdapter->ChNum;
|
||||
u32 ChEn = pHalGdmaAdapter->ChEn;
|
||||
u8 GdmaChIsrBitmap = (ChEn & 0xFF);
|
||||
u8 PendingIsrIndex;
|
||||
|
||||
|
||||
pLliEle = pHalGdmaAdapter->pLlix->pLliEle;
|
||||
pGdmaChLli = pHalGdmaAdapter->pLlix->pNextLli;
|
||||
pGdmaChBkLi = pHalGdmaAdapter->pBlockSizeList;
|
||||
|
||||
|
||||
//4 1) Check chanel is avaliable
|
||||
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
|
||||
//4 Disable Channel
|
||||
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
|
||||
|
||||
HalGdmaChDisRtl8195a(Data);
|
||||
|
||||
}
|
||||
|
||||
//4 2) Check if there are the pending isr; TFR, Block, Src Tran, Dst Tran, Error
|
||||
for (PendingIsrIndex=0; PendingIsrIndex<5;PendingIsrIndex++) {
|
||||
|
||||
u32 PendRaw, PendStstus;
|
||||
PendRaw = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_RAW_INT_BASE + PendingIsrIndex*8));
|
||||
PendStstus = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_STATUS_INT_BASE + PendingIsrIndex*8));
|
||||
|
||||
if ((PendRaw & GdmaChIsrBitmap) || (PendStstus & GdmaChIsrBitmap)) {
|
||||
//4 Clear Pending Isr
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CLEAR_INT_BASE + PendingIsrIndex*8),
|
||||
(PendStstus & (GdmaChIsrBitmap))
|
||||
);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
//4 Fill in SARx register
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF),
|
||||
(pHalGdmaAdapter->ChSar)
|
||||
);
|
||||
|
||||
|
||||
//4 Fill in DARx register
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF),
|
||||
(pHalGdmaAdapter->ChDar)
|
||||
);
|
||||
|
||||
|
||||
|
||||
//4 3) Process CTLx
|
||||
CtlxLow = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF));
|
||||
|
||||
//4 Clear Config low register bits
|
||||
CtlxLow &= (BIT_INVC_CTLX_LO_INT_EN &
|
||||
BIT_INVC_CTLX_LO_DST_TR_WIDTH &
|
||||
BIT_INVC_CTLX_LO_SRC_TR_WIDTH &
|
||||
BIT_INVC_CTLX_LO_DINC &
|
||||
BIT_INVC_CTLX_LO_SINC &
|
||||
BIT_INVC_CTLX_LO_DEST_MSIZE &
|
||||
BIT_INVC_CTLX_LO_SRC_MSIZE &
|
||||
BIT_INVC_CTLX_LO_TT_FC &
|
||||
BIT_INVC_CTLX_LO_LLP_DST_EN &
|
||||
BIT_INVC_CTLX_LO_LLP_SRC_EN);
|
||||
|
||||
CtlxUp = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF + 4));
|
||||
|
||||
//4 Clear Config upper register bits
|
||||
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS &
|
||||
BIT_INVC_CTLX_UP_DONE);
|
||||
|
||||
|
||||
CtlxLow = BIT_CTLX_LO_INT_EN(pHalGdmaAdapter->GdmaCtl.IntEn) |
|
||||
BIT_CTLX_LO_DST_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.DstTrWidth) |
|
||||
BIT_CTLX_LO_SRC_TR_WIDTH(pHalGdmaAdapter->GdmaCtl.SrcTrWidth) |
|
||||
BIT_CTLX_LO_DINC(pHalGdmaAdapter->GdmaCtl.Dinc) |
|
||||
BIT_CTLX_LO_SINC(pHalGdmaAdapter->GdmaCtl.Sinc) |
|
||||
BIT_CTLX_LO_DEST_MSIZE(pHalGdmaAdapter->GdmaCtl.DestMsize) |
|
||||
BIT_CTLX_LO_SRC_MSIZE(pHalGdmaAdapter->GdmaCtl.SrcMsize) |
|
||||
BIT_CTLX_LO_TT_FC(pHalGdmaAdapter->GdmaCtl.TtFc) |
|
||||
BIT_CTLX_LO_LLP_DST_EN(pHalGdmaAdapter->GdmaCtl.LlpDstEn) |
|
||||
BIT_CTLX_LO_LLP_SRC_EN(pHalGdmaAdapter->GdmaCtl.LlpSrcEn) |
|
||||
CtlxLow;
|
||||
|
||||
CtlxUp = BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize) |
|
||||
BIT_CTLX_UP_DONE(pHalGdmaAdapter->GdmaCtl.Done) |
|
||||
CtlxUp;
|
||||
|
||||
//4 Fill in CTLx register
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF),
|
||||
CtlxLow
|
||||
);
|
||||
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_CTL + ChNum*REG_GDMA_CH_OFF +4),
|
||||
CtlxUp
|
||||
);
|
||||
|
||||
//4 4) Program CFGx
|
||||
|
||||
CfgxLow = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF));
|
||||
|
||||
CfgxLow &= (BIT_INVC_CFGX_LO_CH_PRIOR &
|
||||
BIT_INVC_CFGX_LO_CH_SUSP &
|
||||
BIT_INVC_CFGX_LO_HS_SEL_DST &
|
||||
BIT_INVC_CFGX_LO_HS_SEL_SRC &
|
||||
BIT_INVC_CFGX_LO_LOCK_CH_L &
|
||||
BIT_INVC_CFGX_LO_LOCK_B_L &
|
||||
BIT_INVC_CFGX_LO_LOCK_CH &
|
||||
BIT_INVC_CFGX_LO_LOCK_B &
|
||||
BIT_INVC_CFGX_LO_RELOAD_SRC &
|
||||
BIT_INVC_CFGX_LO_RELOAD_DST);
|
||||
|
||||
CfgxUp = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF + 4));
|
||||
|
||||
CfgxUp &= (BIT_INVC_CFGX_UP_FIFO_MODE &
|
||||
BIT_INVC_CFGX_UP_DS_UPD_EN &
|
||||
BIT_INVC_CFGX_UP_SS_UPD_EN &
|
||||
BIT_INVC_CFGX_UP_SRC_PER &
|
||||
BIT_INVC_CFGX_UP_DEST_PER);
|
||||
|
||||
CfgxLow = BIT_CFGX_LO_CH_PRIOR(pHalGdmaAdapter->GdmaCfg.ChPrior) |
|
||||
BIT_CFGX_LO_CH_SUSP(pHalGdmaAdapter->GdmaCfg.ChSusp) |
|
||||
BIT_CFGX_LO_HS_SEL_DST(pHalGdmaAdapter->GdmaCfg.HsSelDst) |
|
||||
BIT_CFGX_LO_HS_SEL_SRC(pHalGdmaAdapter->GdmaCfg.HsSelSrc) |
|
||||
BIT_CFGX_LO_LOCK_CH_L(pHalGdmaAdapter->GdmaCfg.LockChL) |
|
||||
BIT_CFGX_LO_LOCK_B_L(pHalGdmaAdapter->GdmaCfg.LockBL) |
|
||||
BIT_CFGX_LO_LOCK_CH(pHalGdmaAdapter->GdmaCfg.LockCh) |
|
||||
BIT_CFGX_LO_LOCK_B(pHalGdmaAdapter->GdmaCfg.LockB) |
|
||||
BIT_CFGX_LO_RELOAD_SRC(pHalGdmaAdapter->GdmaCfg.ReloadSrc) |
|
||||
BIT_CFGX_LO_RELOAD_DST(pHalGdmaAdapter->GdmaCfg.ReloadDst) |
|
||||
CfgxLow;
|
||||
|
||||
CfgxUp = BIT_CFGX_UP_FIFO_MODE(pHalGdmaAdapter->GdmaCfg.FifoMode) |
|
||||
BIT_CFGX_UP_DS_UPD_EN(pHalGdmaAdapter->GdmaCfg.DsUpdEn) |
|
||||
BIT_CFGX_UP_SS_UPD_EN(pHalGdmaAdapter->GdmaCfg.SsUpdEn) |
|
||||
BIT_CFGX_UP_SRC_PER(pHalGdmaAdapter->GdmaCfg.SrcPer) |
|
||||
BIT_CFGX_UP_DEST_PER(pHalGdmaAdapter->GdmaCfg.DestPer) |
|
||||
CfgxUp;
|
||||
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF),
|
||||
CfgxLow
|
||||
);
|
||||
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + ChNum*REG_GDMA_CH_OFF +4),
|
||||
CfgxUp
|
||||
);
|
||||
|
||||
|
||||
|
||||
//4 Check 4 Bytes Alignment
|
||||
if ((u32)(pLliEle) & 0x3) {
|
||||
DBG_GDMA_WARN("LLi Addr: 0x%x not 4 bytes alignment!!!!\n",
|
||||
pHalGdmaAdapter->pLli);
|
||||
return _FALSE;
|
||||
}
|
||||
|
||||
HAL_GDMAX_WRITE32(GdmaIndex,
|
||||
(REG_GDMA_CH_LLP + ChNum*REG_GDMA_CH_OFF),
|
||||
pLliEle
|
||||
);
|
||||
|
||||
//4 Update the first llp0
|
||||
pLliEle->CtlxLow = CtlxLow;
|
||||
pLliEle->CtlxUp = CtlxUp;
|
||||
pLliEle->Llpx = (u32)pGdmaChLli->pLliEle;
|
||||
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
|
||||
|
||||
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
|
||||
|
||||
while (MultiBlockCount > 1) {
|
||||
MultiBlockCount--;
|
||||
DBG_GDMA_INFO("Block Count %d\n", MultiBlockCount);
|
||||
pLliEle = pGdmaChLli->pLliEle;
|
||||
|
||||
if (NULL == pLliEle) {
|
||||
DBG_GDMA_ERR("pLliEle Null Point!!!!!\n");
|
||||
return _FALSE;
|
||||
}
|
||||
|
||||
//4 Clear the last element llp enable bit
|
||||
if (1 == MultiBlockCount) {
|
||||
if (((pHalGdmaAdapter->Rsvd4to7) & 0x01) == 1){
|
||||
CtlxLow &= (BIT_INVC_CTLX_LO_LLP_DST_EN &
|
||||
BIT_INVC_CTLX_LO_LLP_SRC_EN);
|
||||
}
|
||||
}
|
||||
//4 Update block size for transfer
|
||||
CtlxUp &= (BIT_INVC_CTLX_UP_BLOCK_BS);
|
||||
CtlxUp |= BIT_CTLX_UP_BLOCK_BS(pGdmaChBkLi->BlockSize);
|
||||
|
||||
//4 Update tje Lli and Block size list point to next llp
|
||||
pGdmaChLli = pGdmaChLli->pNextLli;
|
||||
pGdmaChBkLi = pGdmaChBkLi->pNextBlockSiz;
|
||||
|
||||
//4 Updatethe Llpx context
|
||||
pLliEle->CtlxLow = CtlxLow;
|
||||
pLliEle->CtlxUp = CtlxUp;
|
||||
pLliEle->Llpx = (u32)(pGdmaChLli->pLliEle);
|
||||
|
||||
}
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
u32
|
||||
HalGdmaQueryDArRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
|
||||
u8 ChNum = pHalGdmaAdapter->ChNum;
|
||||
u32 dar;
|
||||
|
||||
dar = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_CH_DAR + ChNum*REG_GDMA_CH_OFF));
|
||||
|
||||
return dar;
|
||||
}
|
||||
|
||||
u32
|
||||
HalGdmaQuerySArRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
u8 GdmaIndex = pHalGdmaAdapter->GdmaIndex;
|
||||
u8 ChNum = pHalGdmaAdapter->ChNum;
|
||||
u32 dar;
|
||||
|
||||
dar = HAL_GDMAX_READ32(GdmaIndex,
|
||||
(REG_GDMA_CH_SAR + ChNum*REG_GDMA_CH_OFF));
|
||||
|
||||
return dar;
|
||||
}
|
||||
|
||||
BOOL
|
||||
HalGdmaQueryChEnRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
|
||||
|
||||
if (HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN) & (pHalGdmaAdapter->ChEn)) {
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif // CONFIG_GDMA_EN
|
||||
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "hal_gpio.h"
|
||||
#include "rtl8195a_gpio.h"
|
||||
#include "gpio_irq_api.h"
|
||||
|
||||
#ifdef CONFIG_GPIO_EN
|
||||
|
||||
extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
|
||||
|
||||
/**
|
||||
* @brief Clear the pending interrupt of a specified pin
|
||||
*
|
||||
* @param GPIO_Pin: The data structer which contains the parameters for the GPIO Pin.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
HAL_Status
|
||||
HAL_GPIO_ClearISR_8195a(
|
||||
HAL_GPIO_PIN *GPIO_Pin
|
||||
)
|
||||
{
|
||||
u8 port_num;
|
||||
u8 pin_num;
|
||||
HAL_GPIO_PIN_MODE pin_mode;
|
||||
|
||||
port_num = HAL_GPIO_GET_PORT_BY_NAME(GPIO_Pin->pin_name);
|
||||
pin_num = HAL_GPIO_GET_PIN_BY_NAME(GPIO_Pin->pin_name);
|
||||
pin_mode = GPIO_Pin->pin_mode;
|
||||
|
||||
if ((pin_mode & HAL_GPIO_PIN_INT_MODE)==0 || (port_num != GPIO_PORT_A)) {
|
||||
DBG_GPIO_WARN("HAL_GPIO_ClearISR_8195a: This pin(%x:%x) is'nt an interrupt pin\n", GPIO_Pin->pin_name, GPIO_Pin->pin_mode);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
|
||||
if (GPIO_Lock() != HAL_OK) {
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
// Clear pending interrupt before unmask it
|
||||
HAL_WRITE32(GPIO_REG_BASE, GPIO_PORTA_EOI, (1<<pin_num));
|
||||
|
||||
GPIO_UnLock();
|
||||
return HAL_OK;
|
||||
|
||||
}
|
||||
|
||||
#endif // CONFIG_GPIO_EN
|
||||
|
|
@ -0,0 +1,543 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
#include "rtl8195a.h"
|
||||
|
||||
#ifdef CONFIG_I2C_EN
|
||||
|
||||
/* Used only for A~C Version */
|
||||
#ifndef CONFIG_CHIP_E_CUT
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CSendRtl8195a
|
||||
//
|
||||
// Description:
|
||||
// Send one byte to the I2C internal fifo, it will generate START and STOP bit
|
||||
// automatically.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// _EXIT_SUCCESS if the sending succeeded.
|
||||
// _EXIT_FAILURE if the sending failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
HAL_Status
|
||||
HalI2CSendRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
|
||||
u8 I2CIdx = pHalI2CInitData->I2CIdx;
|
||||
u8 *pDat = pHalI2CInitData->I2CRWData;
|
||||
u8 I2CCmd = pHalI2CInitData->I2CCmd;
|
||||
u8 I2CStop = pHalI2CInitData->I2CStop;
|
||||
u8 I2CReSTR= pHalI2CInitData->I2CReSTR;
|
||||
|
||||
DBG_I2C_INFO("HalI2CSendRtl8195a\n");
|
||||
DBG_I2C_INFO("I2C Index: %x\n",I2CIdx);
|
||||
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DATA_CMD,
|
||||
*(pDat) |
|
||||
BIT_CTRL_IC_DATA_CMD_RESTART(I2CReSTR)|
|
||||
BIT_CTRL_IC_DATA_CMD_CMD(I2CCmd) |
|
||||
BIT_CTRL_IC_DATA_CMD_STOP(I2CStop));
|
||||
|
||||
return (HAL_OK);
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CInit8195a
|
||||
//
|
||||
// Description:
|
||||
// To initialize I2C module by using the given data.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the DeInit process.
|
||||
// _EXIT_SUCCESS if the initialization succeeded.
|
||||
// _EXIT_FAILURE if the initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-04-02.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
HAL_Status
|
||||
HalI2CMassSendRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
|
||||
|
||||
u8 I2CIdx = pHalI2CInitData->I2CIdx;
|
||||
u8 I2CCmd = pHalI2CInitData->I2CCmd;
|
||||
u8 I2CDatLen = pHalI2CInitData->I2CDataLen;
|
||||
u8 *pDat = pHalI2CInitData->I2CRWData;
|
||||
u8 I2CStopSet = pHalI2CInitData->I2CStop;
|
||||
u8 I2CSTP;
|
||||
u8 I2CReSRT = 0;
|
||||
u8 DatCnt = 0;
|
||||
|
||||
/* Send I2C data one by one. The STOP bit is only used for the last byte.*/
|
||||
for (DatCnt = 0; DatCnt < I2CDatLen; DatCnt++)
|
||||
{
|
||||
I2CSTP = 0;
|
||||
if ((DatCnt == (I2CDatLen - 1)) && (I2CStopSet != 0)) {
|
||||
I2CSTP = 1;
|
||||
}
|
||||
|
||||
if ((DatCnt == 0) && ((pHalI2CInitData->RSVD0 & BIT0) != 0)) {
|
||||
I2CReSRT = 1;
|
||||
}
|
||||
else {
|
||||
I2CReSRT = 0;
|
||||
}
|
||||
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DATA_CMD,
|
||||
*(pDat+DatCnt) |
|
||||
BIT_CTRL_IC_DATA_CMD_CMD(I2CCmd) |
|
||||
BIT_CTRL_IC_DATA_CMD_RESTART(I2CReSRT) |
|
||||
BIT_CTRL_IC_DATA_CMD_STOP(I2CSTP));
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CInit8195a
|
||||
//
|
||||
// Description:
|
||||
// To initialize I2C module by using the given data.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the DeInit process.
|
||||
// _EXIT_SUCCESS if the initialization succeeded.
|
||||
// _EXIT_FAILURE if the initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-04-02.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
HAL_Status
|
||||
HalI2CInit8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
|
||||
|
||||
u8 Master;
|
||||
u8 I2CIdx;
|
||||
u8 SpdMd;
|
||||
u8 AddrMd;
|
||||
u8 ReSTR;
|
||||
u8 StartByte;
|
||||
u8 Specical;
|
||||
u8 GC;
|
||||
u16 I2CAckAddr;
|
||||
u16 SdaHd;
|
||||
u8 SdaSetup;
|
||||
u8 RXTL;
|
||||
u8 TXTL;
|
||||
u8 SlvNoAck;
|
||||
u32 INTRMsk;
|
||||
u8 TxDMARqLv;
|
||||
u8 RxDMARqLv;
|
||||
u32 I2CTmp;
|
||||
|
||||
/* Get the I2C parameters*/
|
||||
I2CIdx = pHalI2CInitData->I2CIdx;
|
||||
SpdMd = pHalI2CInitData->I2CSpdMod;
|
||||
AddrMd = pHalI2CInitData->I2CAddrMod;
|
||||
I2CAckAddr = pHalI2CInitData->I2CAckAddr;
|
||||
Master = pHalI2CInitData->I2CMaster;
|
||||
SdaHd = pHalI2CInitData->I2CSdaHd;
|
||||
SdaSetup = pHalI2CInitData->I2CSetup;
|
||||
|
||||
ReSTR = pHalI2CInitData->I2CReSTR;
|
||||
GC = pHalI2CInitData->I2CGC;
|
||||
StartByte = pHalI2CInitData->I2CStartB;
|
||||
SlvNoAck = pHalI2CInitData->I2CSlvNoAck;
|
||||
|
||||
RXTL = pHalI2CInitData->I2CRXTL;
|
||||
TXTL = pHalI2CInitData->I2CTXTL;
|
||||
|
||||
TxDMARqLv = pHalI2CInitData->I2CTxDMARqLv;
|
||||
RxDMARqLv = pHalI2CInitData->I2CRxDMARqLv;
|
||||
|
||||
/* Disable the IC first */
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_ENABLE,BIT_CTRL_IC_ENABLE(0));
|
||||
|
||||
/* Master case*/
|
||||
if (Master) {
|
||||
/*RESTART MUST be set in these condition in Master mode.
|
||||
But it might be NOT compatible in old slaves.*/
|
||||
if ((AddrMd == I2C_ADDR_10BIT) || (SpdMd == I2C_HS_MODE))
|
||||
ReSTR = 1;
|
||||
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_CON,
|
||||
(BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(1) |
|
||||
BIT_CTRL_IC_CON_IC_RESTART_EN(ReSTR) |
|
||||
BIT_CTRL_IC_CON_IC_10BITADDR_MASTER(AddrMd) |
|
||||
BIT_CTRL_IC_CON_SPEED(SpdMd) |
|
||||
BIT_CTRL_IC_CON_MASTER_MODE(Master)));
|
||||
|
||||
DBG_I2C_INFO("Init master, IC_CON%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_CON, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON));
|
||||
|
||||
|
||||
/* To set target addr.*/
|
||||
Specical = 0;
|
||||
if ((GC!=0) || (StartByte!=0))
|
||||
Specical = 1;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_TAR,
|
||||
(BIT_CTRL_IC_TAR_IC_10BITADDR_MASTER(AddrMd) |
|
||||
BIT_CTRL_IC_TAR_SPECIAL(Specical) |
|
||||
BIT_CTRL_IC_TAR_GC_OR_START(StartByte) |
|
||||
BIT_CTRL_IC_TAR(I2CAckAddr)));
|
||||
|
||||
/* To Set I2C clock*/
|
||||
HalI2CSetCLKRtl8195a_Patch(pHalI2CInitData);
|
||||
|
||||
|
||||
DBG_I2C_INFO("Init master, IC_TAR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_TAR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_TAR));
|
||||
|
||||
} /*if (Master)*/
|
||||
else {
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_CON,
|
||||
BIT_CTRL_IC_CON_IC_10BITADDR_SLAVE(AddrMd) |
|
||||
BIT_CTRL_IC_CON_IC_SLAVE_DISABLE(Master) |
|
||||
BIT_CTRL_IC_CON_SPEED(SpdMd)|
|
||||
BIT_CTRL_IC_CON_MASTER_MODE(Master));
|
||||
|
||||
DBG_I2C_INFO("Init slave, IC_CON%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_CON, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON));
|
||||
|
||||
|
||||
/* To set slave addr. */
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SAR,BIT_CTRL_IC_SAR(I2CAckAddr));
|
||||
|
||||
DBG_I2C_INFO("Init slave, IC_SAR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_SAR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SAR));
|
||||
|
||||
|
||||
/* To set slave no ack */
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SLV_DATA_NACK_ONLY,BIT_CTRL_IC_SLV_DATA_NACK_ONLY(SlvNoAck));
|
||||
|
||||
/* Set ack general call. */
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_ACK_GENERAL_CALL,BIT_CTRL_IC_ACK_GENERAL_CALL(pHalI2CInitData->I2CSlvAckGC));
|
||||
|
||||
|
||||
|
||||
DBG_I2C_INFO("Init slave, I2C_IC_ACK_GC%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_ACK_GENERAL_CALL, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_ACK_GENERAL_CALL));
|
||||
|
||||
/* to set SDA hold time */
|
||||
//HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd));
|
||||
//4
|
||||
/* to set SDA setup time */
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_SETUP,BIT_CTRL_IC_SDA_SETUP(SdaSetup));
|
||||
}
|
||||
|
||||
/* to set SDA hold time */
|
||||
INTRMsk = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_CON);
|
||||
if (BIT_GET_IC_CON_SPEED(INTRMsk) == I2C_SS_MODE) {
|
||||
I2CTmp = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT);
|
||||
} else if (BIT_GET_IC_CON_SPEED(INTRMsk) == I2C_FS_MODE) {
|
||||
I2CTmp = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT);
|
||||
} else {
|
||||
I2CTmp = HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT);
|
||||
}
|
||||
|
||||
if (Master) {
|
||||
if (SdaHd > (I2CTmp -2)) {
|
||||
I2CTmp = I2CTmp -2;
|
||||
if (I2CTmp < 1) {
|
||||
I2CTmp = 1 + 1;
|
||||
}
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(I2CTmp));
|
||||
} else {
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd));
|
||||
}
|
||||
} else {
|
||||
if (SdaHd > (I2CTmp -2)) {
|
||||
I2CTmp = I2CTmp -2;
|
||||
if (I2CTmp < 7) {
|
||||
I2CTmp = 7 + 1;
|
||||
}
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(I2CTmp));
|
||||
} else {
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD,BIT_CTRL_IC_SDA_HOLD(SdaHd));
|
||||
}
|
||||
}
|
||||
//DBG_8195A("SDA:%x\n", HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SDA_HOLD));
|
||||
|
||||
/* To set TX_Empty Level */
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_TX_TL,TXTL);
|
||||
|
||||
/* To set RX_Full Level */
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_RX_TL,RXTL);
|
||||
|
||||
/* To set TX/RX FIFO level */
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DMA_TDLR,TxDMARqLv);
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_DMA_RDLR,RxDMARqLv);
|
||||
|
||||
|
||||
DBG_I2C_INFO("Init i2c dev, I2C_IC_DMA_TDLR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_DMA_TDLR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_DMA_TDLR));
|
||||
DBG_I2C_INFO("Init i2c dev, I2C_IC_DMA_RDLR%d[%2x]: %x\n", I2CIdx, REG_DW_I2C_IC_DMA_RDLR, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_DMA_RDLR));
|
||||
|
||||
|
||||
/*I2C Clear all interrupts first*/
|
||||
HalI2CClrAllIntrRtl8195a(pHalI2CInitData);
|
||||
|
||||
/*I2C Disable all interrupts first*/
|
||||
INTRMsk = pHalI2CInitData->I2CIntrMSK;
|
||||
pHalI2CInitData->I2CIntrMSK = 0;
|
||||
HalI2CIntrCtrl8195a(pHalI2CInitData);
|
||||
pHalI2CInitData->I2CIntrMSK = INTRMsk;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
//Function Name:
|
||||
// HalI2CSetCLKRtl8195a
|
||||
//
|
||||
// Description:
|
||||
// To set I2C bus clock rate.
|
||||
//
|
||||
// Arguments:
|
||||
// [in] VOID *Data -
|
||||
// The I2C parameter data struct.
|
||||
//
|
||||
// Return:
|
||||
// The status of the enable process.
|
||||
// _EXIT_SUCCESS if the de-initialization succeeded.
|
||||
// _EXIT_FAILURE if the de-initialization failed.
|
||||
//
|
||||
// Note:
|
||||
// None
|
||||
//
|
||||
// See Also:
|
||||
// NA
|
||||
//
|
||||
// Author:
|
||||
// By Jason Deng, 2014-02-18.
|
||||
//
|
||||
//---------------------------------------------------------------------------------------------------
|
||||
HAL_Status
|
||||
HalI2CSetCLKRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
|
||||
u8 SpdMd = pHalI2CInitData->I2CSpdMod;
|
||||
u32 I2CClk = pHalI2CInitData->I2CClk;
|
||||
u8 I2CIdx = pHalI2CInitData->I2CIdx;
|
||||
u32 ICHLcnt;
|
||||
u32 ICHtime;
|
||||
u32 ICLtime;
|
||||
|
||||
/* Get the IC-Clk setting first for the following process*/
|
||||
#ifdef CONFIG_FPGA
|
||||
u32 IcClk = SYSTEM_CLK/1000000;
|
||||
#else
|
||||
u32 IcClk;
|
||||
u32 ClkSELTmp = 0;
|
||||
u32 CpuClkTmp = 0;
|
||||
|
||||
#if defined(CONFIG_CHIP_A_CUT)
|
||||
CpuClkTmp = StartupHalGetCpuClk();
|
||||
#elif (defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT))
|
||||
CpuClkTmp = HalGetCpuClk();
|
||||
#endif
|
||||
|
||||
DBG_I2C_INFO("%s, CPU Clk:%x\n",__func__, CpuClkTmp);
|
||||
|
||||
ClkSELTmp = HAL_READ32(PERI_ON_BASE, REG_PESOC_CLK_SEL);
|
||||
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
|
||||
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
|
||||
IcClk = (CpuClkTmp/1000000)>>1;
|
||||
|
||||
#if 0
|
||||
if ((I2CClk > 0) && (I2CClk <= 400)) {
|
||||
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
|
||||
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
|
||||
IcClk = ClkSELTmp/1000000; /*actually it's 12.5MHz*/
|
||||
}
|
||||
else {
|
||||
ClkSELTmp &= (~(BIT_PESOC_PERI_SCLK_SEL(3)));
|
||||
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_CLK_SEL,ClkSELTmp);
|
||||
IcClk = 100;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
switch (SpdMd)
|
||||
{
|
||||
case I2C_SS_MODE:
|
||||
{
|
||||
ICHtime = ((1000000/I2CClk)*I2C_SS_MIN_SCL_HTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
|
||||
ICLtime = ((1000000/I2CClk)*I2C_SS_MIN_SCL_LTIME)/(I2C_SS_MIN_SCL_HTIME+I2C_SS_MIN_SCL_LTIME);
|
||||
|
||||
ICHLcnt = (ICHtime * IcClk)/1000;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT,ICHLcnt);
|
||||
|
||||
|
||||
DBG_I2C_INFO("IC_SS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
|
||||
REG_DW_I2C_IC_SS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT));
|
||||
|
||||
|
||||
ICHLcnt = (ICLtime * IcClk)/1000;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT,ICHLcnt);
|
||||
|
||||
|
||||
DBG_I2C_INFO("IC_SS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
|
||||
REG_DW_I2C_IC_SS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT));
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case I2C_FS_MODE:
|
||||
{
|
||||
ICHtime = ((1000000/I2CClk)*I2C_FS_MIN_SCL_HTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
|
||||
ICLtime = ((1000000/I2CClk)*I2C_FS_MIN_SCL_LTIME)/(I2C_FS_MIN_SCL_HTIME+I2C_FS_MIN_SCL_LTIME);
|
||||
|
||||
ICHLcnt = (ICHtime * IcClk)/1000;
|
||||
if (ICHLcnt>4)/*this part is according to the fine-tune result*/
|
||||
ICHLcnt -= 4;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT,ICHLcnt);
|
||||
|
||||
|
||||
DBG_I2C_INFO("IC_FS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
|
||||
REG_DW_I2C_IC_FS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT));
|
||||
|
||||
|
||||
ICHLcnt = (ICLtime * IcClk)/1000;
|
||||
if (ICHLcnt>3)/*this part is according to the fine-tune result*/
|
||||
ICHLcnt -= 3;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT,ICHLcnt);
|
||||
|
||||
|
||||
DBG_I2C_INFO("IC_FS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
|
||||
REG_DW_I2C_IC_FS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT));
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case I2C_HS_MODE:
|
||||
{
|
||||
ICHLcnt = 400;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_HCNT,ICHLcnt);
|
||||
|
||||
ICHLcnt = 470;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_SS_SCL_LCNT,ICHLcnt);
|
||||
|
||||
ICHLcnt = 60;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_HCNT,ICHLcnt);
|
||||
|
||||
ICHLcnt = 130;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_FS_SCL_LCNT,ICHLcnt);
|
||||
|
||||
ICHtime = ((1000000/I2CClk)*I2C_HS_MIN_SCL_HTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
|
||||
ICLtime = ((1000000/I2CClk)*I2C_HS_MIN_SCL_LTIME_100)/(I2C_HS_MIN_SCL_HTIME_100+I2C_HS_MIN_SCL_LTIME_100);
|
||||
|
||||
|
||||
DBG_I2C_INFO("ICHtime:%x\n",ICHtime);
|
||||
DBG_I2C_INFO("ICLtime:%x\n",ICLtime);
|
||||
|
||||
|
||||
ICHLcnt = (ICHtime * IcClk)/1000;
|
||||
if (ICHLcnt>8)/*this part is according to the fine-tune result*/
|
||||
ICHLcnt -= 3;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_HS_SCL_HCNT,ICHLcnt);
|
||||
|
||||
|
||||
DBG_I2C_INFO("IC_HS_SCL_HCNT%d[%2x]: %x\n", I2CIdx,
|
||||
REG_DW_I2C_IC_HS_SCL_HCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_HCNT));
|
||||
|
||||
|
||||
ICHLcnt = (ICLtime * IcClk)/1000;
|
||||
if (ICHLcnt>6)/*this part is according to the fine-tune result*/
|
||||
ICHLcnt -= 6;
|
||||
HAL_I2C_WRITE32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT,ICHLcnt);
|
||||
|
||||
|
||||
DBG_I2C_INFO("IC_HS_SCL_LCNT%d[%2x]: %x\n", I2CIdx,
|
||||
REG_DW_I2C_IC_HS_SCL_LCNT, HAL_I2C_READ32(I2CIdx,REG_DW_I2C_IC_HS_SCL_LCNT));
|
||||
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalI2CEnableRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
){
|
||||
PHAL_I2C_INIT_DAT pHalI2CInitData = (PHAL_I2C_INIT_DAT)Data;
|
||||
u8 I2CIdx = pHalI2CInitData->I2CIdx;
|
||||
u8 I2CICEn = pHalI2CInitData->I2CEn;
|
||||
u32 I2CTimeoutCount;
|
||||
u32 I2CStartCount;
|
||||
/* Enable I2C module */
|
||||
HAL_I2C_WRITE32(I2CIdx, REG_DW_I2C_IC_ENABLE, BIT_CTRL_IC_ENABLE(I2CICEn));
|
||||
|
||||
I2CTimeoutCount = ((10000/pHalI2CInitData->I2CClk) /TIMER_TICK_US) +1;
|
||||
I2CStartCount = HalTimerOp.HalTimerReadCount(1);
|
||||
|
||||
if (!I2CICEn) {
|
||||
while (HAL_I2C_READ32(I2CIdx, REG_DW_I2C_IC_ENABLE_STATUS) & BIT_IC_ENABLE_STATUS_IC_EN) {
|
||||
if (HAL_TIMEOUT == I2CIsTimeout(I2CStartCount, I2CTimeoutCount)) {
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
while (!(HAL_I2C_READ32(I2CIdx, REG_DW_I2C_IC_ENABLE_STATUS) & BIT_IC_ENABLE_STATUS_IC_EN)) {
|
||||
if (HAL_TIMEOUT == I2CIsTimeout(I2CStartCount, I2CTimeoutCount)) {
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // CONFIG_I2C_EN
|
||||
|
|
@ -0,0 +1,398 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_i2s.h"
|
||||
#include "hal_i2s.h"
|
||||
|
||||
#ifdef CONFIG_I2S_EN
|
||||
|
||||
extern void *
|
||||
_memset( void *s, int c, SIZE_T n );
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SInitRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
|
||||
u8 I2SIdx;
|
||||
//u8 I2SEn;
|
||||
u8 I2SMaster;
|
||||
u8 I2SWordLen;
|
||||
u8 I2SChNum;
|
||||
u8 I2SPageNum;
|
||||
u16 I2SPageSize;
|
||||
u16 I2SRate;
|
||||
u32 I2STxIntrMSK;
|
||||
u32 I2SRxIntrMSK;
|
||||
u8 I2STRxAct;
|
||||
u8 *I2STxData;
|
||||
u8 *I2SRxData;
|
||||
|
||||
u32 Tmp;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
//I2SEn = pHalI2SInitData->I2SEn;
|
||||
I2SMaster = pHalI2SInitData->I2SMaster;
|
||||
I2SWordLen = pHalI2SInitData->I2SWordLen;
|
||||
I2SChNum = pHalI2SInitData->I2SChNum;
|
||||
I2SPageNum = pHalI2SInitData->I2SPageNum;
|
||||
I2SPageSize = pHalI2SInitData->I2SPageSize;
|
||||
I2SRate = pHalI2SInitData->I2SRate;
|
||||
I2STRxAct = pHalI2SInitData->I2STRxAct;
|
||||
I2STxData = pHalI2SInitData->I2STxData;
|
||||
I2SRxData = pHalI2SInitData->I2SRxData;
|
||||
|
||||
|
||||
/* Disable the I2S first, and reset to default */
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
|
||||
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
|
||||
BIT_CTRL_CTLX_I2S_SW_RSTN(0));
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, BIT_CTRL_CTLX_I2S_EN(0) |
|
||||
BIT_CTRL_CTLX_I2S_SW_RSTN(1));
|
||||
|
||||
Tmp = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
|
||||
Tmp |= BIT_CTRL_CTLX_I2S_ENDIAN_SWAP(1);
|
||||
|
||||
if (I2SRate & 0x10)
|
||||
{
|
||||
Tmp |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
|
||||
}
|
||||
|
||||
Tmp |= (BIT_CTRL_CTLX_I2S_WL(I2SWordLen) | BIT_CTRL_CTLX_I2S_CH_NUM(I2SChNum) |
|
||||
BIT_CTRL_CTLX_I2S_SLAVE_MODE(I2SMaster) | BIT_CTRL_CTLX_I2S_TRX_ACT(I2STRxAct));
|
||||
/* set 44.1khz clock source, word length, channel number, master or slave, trx act */
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, Tmp);
|
||||
|
||||
Tmp = BIT_CTRL_SETTING_I2S_PAGE_SZ(I2SPageSize) | BIT_CTRL_SETTING_I2S_PAGE_NUM(I2SPageNum) |
|
||||
BIT_CTRL_SETTING_I2S_SAMPLE_RATE(I2SRate);
|
||||
/* set page size, page number, sample rate */
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, Tmp);
|
||||
|
||||
/* need tx rx buffer? need rx page own bit */
|
||||
if (I2STxData != NULL) {
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (u32)I2STxData);
|
||||
}
|
||||
|
||||
if (I2SRxData != NULL) {
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (u32)I2SRxData);
|
||||
}
|
||||
|
||||
pHalI2SInitData->I2STxIdx = 0;
|
||||
pHalI2SInitData->I2SRxIdx = 0;
|
||||
pHalI2SInitData->I2SHWTxIdx = 0;
|
||||
pHalI2SInitData->I2SHWRxIdx = 0;
|
||||
/* I2S Clear all interrupts first */
|
||||
HalI2SClrAllIntrRtl8195a(pHalI2SInitData);
|
||||
|
||||
/* I2S Disable all interrupts first */
|
||||
I2STxIntrMSK = pHalI2SInitData->I2STxIntrMSK;
|
||||
I2SRxIntrMSK = pHalI2SInitData->I2SRxIntrMSK;
|
||||
pHalI2SInitData->I2STxIntrMSK = 0;
|
||||
pHalI2SInitData->I2SRxIntrMSK = 0;
|
||||
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
|
||||
pHalI2SInitData->I2STxIntrMSK = I2STxIntrMSK;
|
||||
pHalI2SInitData->I2SRxIntrMSK = I2SRxIntrMSK;
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetRateRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
|
||||
reg_value &= ~(BIT_MASK_CTLX_I2S_CLK_SRC << BIT_SHIFT_CTLX_I2S_CLK_SRC);
|
||||
if (pHalI2SInitData->I2SRate & 0x10)
|
||||
{
|
||||
reg_value |= BIT_CTRL_CTLX_I2S_CLK_SRC(1);
|
||||
}
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
|
||||
reg_value &= ~(BIT_MASK_SETTING_I2S_SAMPLE_RATE << BIT_SHIFT_SETTING_I2S_SAMPLE_RATE);
|
||||
reg_value |= BIT_CTRL_SETTING_I2S_SAMPLE_RATE(pHalI2SInitData->I2SRate);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetWordLenRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
|
||||
reg_value &= ~(BIT_MASK_CTLX_I2S_WL << BIT_SHIFT_CTLX_I2S_WL);
|
||||
reg_value |= BIT_CTRL_CTLX_I2S_WL(pHalI2SInitData->I2SWordLen);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetChNumRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
|
||||
reg_value &= ~(BIT_MASK_CTLX_I2S_CH_NUM << BIT_SHIFT_CTLX_I2S_CH_NUM);
|
||||
reg_value |= BIT_CTRL_CTLX_I2S_CH_NUM(pHalI2SInitData->I2SChNum);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetPageNumRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
|
||||
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
|
||||
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetPageSizeRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
|
||||
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
|
||||
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetDirectionRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_CTL);
|
||||
reg_value &= ~(BIT_MASK_CTLX_I2S_TRX_ACT << BIT_SHIFT_CTLX_I2S_TRX_ACT);
|
||||
reg_value |= BIT_CTRL_CTLX_I2S_TRX_ACT(pHalI2SInitData->I2STRxAct);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_CTL, reg_value);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SSetDMABufRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 reg_value;
|
||||
u32 page_num;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg_value = HAL_I2S_READ32(I2SIdx, REG_I2S_SETTING);
|
||||
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_SZ << BIT_SHIFT_SETTING_I2S_PAGE_SZ);
|
||||
reg_value &= ~(BIT_MASK_SETTING_I2S_PAGE_NUM << BIT_SHIFT_SETTING_I2S_PAGE_NUM);
|
||||
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_SZ(pHalI2SInitData->I2SPageSize);
|
||||
reg_value |= BIT_CTRL_SETTING_I2S_PAGE_NUM(pHalI2SInitData->I2SPageNum);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_SETTING, reg_value);
|
||||
|
||||
page_num = pHalI2SInitData->I2SPageNum + 1;
|
||||
if (pHalI2SInitData->I2STxData) {
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2STxData);
|
||||
pHalI2SInitData->I2STxIntrMSK = (1<<page_num) - 1;
|
||||
} else {
|
||||
pHalI2SInitData->I2STxIntrMSK = 0;
|
||||
}
|
||||
|
||||
if (pHalI2SInitData->I2SRxData) {
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE_PTR, (uint32_t)pHalI2SInitData->I2SRxData);
|
||||
pHalI2SInitData->I2SRxIntrMSK = (1<<page_num) - 1;
|
||||
} else {
|
||||
pHalI2SInitData->I2SRxIntrMSK = 0;
|
||||
|
||||
}
|
||||
|
||||
// According to the page number to modify the ISR mask
|
||||
HalI2SIntrCtrlRtl8195a(pHalI2SInitData);
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
u8
|
||||
HalI2SGetTxPageRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
|
||||
u8 I2SIdx;
|
||||
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
|
||||
u32 reg;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(I2STxIdx<<2));
|
||||
if ((reg & (1<<31)) == 0) {
|
||||
return I2STxIdx;
|
||||
} else {
|
||||
return 0xFF;
|
||||
}
|
||||
}
|
||||
|
||||
u8
|
||||
HalI2SGetRxPageRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
|
||||
u8 I2SIdx;
|
||||
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
|
||||
u32 reg;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
|
||||
if ((reg & (1<<31)) == 0) {
|
||||
return I2SRxIdx;
|
||||
} else {
|
||||
return 0xFF;
|
||||
}
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SPageSendRtl8195a(
|
||||
IN VOID *Data,
|
||||
IN u8 PageIdx
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u16 I2STxIdx = pHalI2SInitData->I2STxIdx;
|
||||
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
|
||||
u8 I2SIdx;
|
||||
|
||||
if (I2STxIdx != PageIdx) {
|
||||
DBG_I2S_ERR("HalI2SPageSendRtl8195a: UnExpected Page Index. TxPage=%d, Expected:%d\r\n",
|
||||
PageIdx, I2STxIdx);
|
||||
}
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN + 4 * PageIdx, BIT_PAGE_I2S_OWN_BIT);
|
||||
I2STxIdx = PageIdx + 1;
|
||||
if (I2STxIdx > I2SPageNum) {
|
||||
I2STxIdx = 0;
|
||||
}
|
||||
pHalI2SInitData->I2STxIdx = I2STxIdx;
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SPageRecvRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u16 I2SRxIdx = pHalI2SInitData->I2SRxIdx;
|
||||
u8 I2SPageNum = pHalI2SInitData->I2SPageNum;
|
||||
u32 reg;
|
||||
u8 I2SIdx;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
reg = HAL_I2S_READ32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx << 2));
|
||||
if ((reg & (1<<31)) != 0) {
|
||||
DBG_I2S_ERR("HalI2SPageRecvRtl8195a: No Idle Rx Page\r\n");
|
||||
return _EXIT_FAILURE;
|
||||
}
|
||||
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(I2SRxIdx<<2), 1<<31);
|
||||
I2SRxIdx += 1;
|
||||
if (I2SRxIdx > I2SPageNum) {
|
||||
I2SRxIdx = 0;
|
||||
}
|
||||
pHalI2SInitData->I2SRxIdx = I2SRxIdx;
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SClearAllOwnBitRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_I2S_INIT_DAT pHalI2SInitData = (PHAL_I2S_INIT_DAT)Data;
|
||||
u8 I2SIdx;
|
||||
u32 i;
|
||||
|
||||
I2SIdx = pHalI2SInitData->I2SIdx;
|
||||
|
||||
for (i=0;i<4;i++) {
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_TX_PAGE0_OWN+(i<<2), 0);
|
||||
HAL_I2S_WRITE32(I2SIdx, REG_I2S_RX_PAGE0_OWN+(i<<2), 0);
|
||||
}
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
RTK_STATUS
|
||||
HalI2SDMACtrlRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
return _EXIT_SUCCESS;
|
||||
}
|
||||
|
||||
#endif // CONFIG_I2S_EN
|
||||
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,359 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_pcm.h"
|
||||
#include "hal_pcm.h"
|
||||
|
||||
extern void *
|
||||
_memset( void *s, int c, SIZE_T n );
|
||||
|
||||
VOID
|
||||
HalPcmOnOffRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
|
||||
//todo on off pcm
|
||||
|
||||
}
|
||||
|
||||
//default sampling rate 8khz, linear, 10ms frame size, time slot 0 , tx+rx
|
||||
// master mode, enable endian swap
|
||||
// Question: need local tx/rx page?
|
||||
BOOL
|
||||
HalPcmInitRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
|
||||
_memset((void *)pHalPcmAdapter, 0, sizeof(HAL_PCM_ADAPTER));
|
||||
|
||||
//4 1) Initial PcmChCNR03 Register
|
||||
pHalPcmAdapter->PcmChCNR03.CH0MuA = 0;
|
||||
pHalPcmAdapter->PcmChCNR03.CH0Band = 0;
|
||||
|
||||
|
||||
//4 1) Initial PcmTSR03 Register
|
||||
pHalPcmAdapter->PcmTSR03.CH0TSA = 0;
|
||||
|
||||
//4 1) Initial PcmBSize03 Register
|
||||
pHalPcmAdapter->PcmBSize03.CH0BSize = 39; // 40word= 8khz*0.01s*1ch*2byte/4byte
|
||||
|
||||
|
||||
//4 2) Initial Ctl Register
|
||||
|
||||
pHalPcmAdapter->PcmCtl.Pcm_En = 1;
|
||||
pHalPcmAdapter->PcmCtl.SlaveMode = 0;
|
||||
pHalPcmAdapter->PcmCtl.FsInv = 0;
|
||||
pHalPcmAdapter->PcmCtl.LinearMode = 0;
|
||||
pHalPcmAdapter->PcmCtl.LoopBack = 0;
|
||||
pHalPcmAdapter->PcmCtl.EndianSwap = 1;
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
BOOL
|
||||
HalPcmSettingRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
|
||||
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
|
||||
u8 PcmCh = pHalPcmAdapter->PcmCh;
|
||||
u32 RegCtl, RegChCNR03, RegTSR03, RegBSize03;
|
||||
u32 Isr03;
|
||||
|
||||
PcmCh=0;
|
||||
//4 1) Check Pcm index is avaliable
|
||||
if (HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03) & (BIT24|BIT25)) {
|
||||
//4 Pcm index is running, stop first
|
||||
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
|
||||
|
||||
return _FALSE;
|
||||
}
|
||||
|
||||
//4 2) Check if there are the pending isr
|
||||
|
||||
|
||||
Isr03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_ISR03);
|
||||
Isr03 &= 0xff000000;
|
||||
//4 Clear Pending Isr
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_ISR03, Isr03);
|
||||
//}
|
||||
|
||||
|
||||
//4 3) Process RegCtl
|
||||
RegCtl = HAL_PCMX_READ32(PcmIndex, REG_PCM_CTL);
|
||||
|
||||
//4 Clear Ctl register bits
|
||||
RegCtl &= ( BIT_INV_CTLX_SLAVE_SEL &
|
||||
BIT_INV_CTLX_FSINV &
|
||||
BIT_INV_CTLX_PCM_EN &
|
||||
BIT_INV_CTLX_LINEARMODE &
|
||||
BIT_INV_CTLX_LOOP_BACK &
|
||||
BIT_INV_CTLX_ENDIAN_SWAP);
|
||||
|
||||
RegCtl = BIT_CTLX_SLAVE_SEL(pHalPcmAdapter->PcmCtl.SlaveMode) |
|
||||
BIT_CTLX_FSINV(pHalPcmAdapter->PcmCtl.FsInv) |
|
||||
BIT_CTLX_PCM_EN(pHalPcmAdapter->PcmCtl.Pcm_En) |
|
||||
BIT_CTLX_LINEARMODE(pHalPcmAdapter->PcmCtl.LinearMode) |
|
||||
BIT_CTLX_LOOP_BACK(pHalPcmAdapter->PcmCtl.LoopBack) |
|
||||
BIT_CTLX_ENDIAN_SWAP(pHalPcmAdapter->PcmCtl.EndianSwap) |
|
||||
RegCtl;
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CTL, RegCtl);
|
||||
//4 4) Program ChCNR03 Register
|
||||
|
||||
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
|
||||
|
||||
RegChCNR03 &= (BIT_INV_CHCNR03_CH0RE &
|
||||
BIT_INV_CHCNR03_CH0TE &
|
||||
BIT_INV_CHCNR03_CH0MUA &
|
||||
BIT_INV_CHCNR03_CH0BAND);
|
||||
|
||||
RegChCNR03 = BIT_CHCNR03_CH0RE(pHalPcmAdapter->PcmChCNR03.CH0RE) |
|
||||
BIT_CHCNR03_CH0TE(pHalPcmAdapter->PcmChCNR03.CH0TE) |
|
||||
BIT_CHCNR03_CH0MUA(pHalPcmAdapter->PcmChCNR03.CH0MuA) |
|
||||
BIT_CHCNR03_CH0BAND(pHalPcmAdapter->PcmChCNR03.CH0Band) |
|
||||
RegChCNR03;
|
||||
|
||||
DBG_8195A_DMA("RegChCNR03 data:0x%x\n", RegChCNR03);
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03);
|
||||
// time slot
|
||||
RegTSR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_TSR03);
|
||||
|
||||
RegTSR03 &= (BIT_INV_TSR03_CH0TSA);
|
||||
RegTSR03 = BIT_TSR03_CH0TSA(pHalPcmAdapter->PcmTSR03.CH0TSA) |
|
||||
RegTSR03;
|
||||
|
||||
DBG_8195A_DMA("RegTSR03 data:0x%x\n", RegTSR03);
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_TSR03, RegTSR03);
|
||||
|
||||
// buffer size
|
||||
RegBSize03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_BSIZE03);
|
||||
|
||||
RegBSize03 &= (BIT_INV_BSIZE03_CH0BSIZE);
|
||||
RegBSize03 = BIT_BSIZE03_CH0BSIZE(pHalPcmAdapter->PcmBSize03.CH0BSize) |
|
||||
RegBSize03;
|
||||
|
||||
DBG_8195A_DMA("RegBSize03 data:0x%x\n", RegBSize03);
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_BSIZE03, RegBSize03);
|
||||
|
||||
|
||||
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
BOOL
|
||||
HalPcmEnRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
|
||||
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
|
||||
u8 PcmCh = pHalPcmAdapter->PcmCh;
|
||||
u32 RegChCNR03;
|
||||
|
||||
PcmCh=0;
|
||||
pHalPcmAdapter->Enable = 1;
|
||||
|
||||
|
||||
//4 1) Check Pcm index is avaliable
|
||||
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
|
||||
if (RegChCNR03 & (BIT24|BIT25)) {
|
||||
//4 Pcm index is running, stop first
|
||||
DBG_8195A_DMA("Error, PCM %d ch%d is running; stop first!\n", PcmIndex, PcmCh);
|
||||
|
||||
return _FALSE;
|
||||
}
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03|BIT24|BIT25);
|
||||
pHalPcmAdapter->PcmChCNR03.CH0RE = 1;
|
||||
pHalPcmAdapter->PcmChCNR03.CH0TE = 1;
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
BOOL
|
||||
HalPcmDisRtl8195a(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
|
||||
PHAL_PCM_ADAPTER pHalPcmAdapter = (PHAL_PCM_ADAPTER) Data;
|
||||
u8 PcmIndex = pHalPcmAdapter->PcmIndex;
|
||||
u8 PcmCh = pHalPcmAdapter->PcmCh;
|
||||
u32 RegChCNR03;
|
||||
|
||||
PcmCh=0;
|
||||
pHalPcmAdapter->Enable = 0;
|
||||
|
||||
|
||||
RegChCNR03 = HAL_PCMX_READ32(PcmIndex, REG_PCM_CHCNR03);
|
||||
|
||||
HAL_PCMX_WRITE32(PcmIndex, REG_PCM_CHCNR03, RegChCNR03&(~(BIT24|BIT25)));
|
||||
pHalPcmAdapter->PcmChCNR03.CH0RE = 0;
|
||||
pHalPcmAdapter->PcmChCNR03.CH0TE = 0;
|
||||
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
BOOL
|
||||
HalPcmIsrEnAndDisRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
/*
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
u32 IsrMask, Addr, IsrCtrl;
|
||||
u8 IsrTypeIndex = 0;
|
||||
|
||||
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
|
||||
|
||||
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
|
||||
Addr = (REG_GDMA_MASK_INT_BASE + IsrTypeIndex*8);
|
||||
|
||||
IsrMask = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, Addr);
|
||||
|
||||
IsrCtrl = ((pHalGdmaAdapter->IsrCtrl)?(pHalGdmaAdapter->ChEn | IsrMask):
|
||||
((~pHalGdmaAdapter->ChEn) & IsrMask));
|
||||
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
Addr,
|
||||
IsrCtrl
|
||||
);
|
||||
|
||||
}
|
||||
}
|
||||
*/
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
|
||||
|
||||
BOOL
|
||||
HalPcmDumpRegRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
/*
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
REG_GDMA_CH_EN,
|
||||
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
|
||||
(pHalGdmaAdapter->ChEn))
|
||||
);
|
||||
*/
|
||||
return _TRUE;
|
||||
}
|
||||
|
||||
BOOL
|
||||
HalPcmRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
REG_GDMA_CH_EN,
|
||||
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
|
||||
~(pHalGdmaAdapter->ChEn))
|
||||
);
|
||||
*/
|
||||
return _TRUE;
|
||||
}
|
||||
/*
|
||||
u8
|
||||
HalGdmaChIsrCleanRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
u32 IsrStatus;
|
||||
u8 IsrTypeIndex = 0, IsrActBitMap = 0;
|
||||
|
||||
for (IsrTypeIndex=0; IsrTypeIndex<5; IsrTypeIndex++) {
|
||||
|
||||
IsrStatus = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_RAW_INT_BASE + IsrTypeIndex*8));
|
||||
|
||||
// DBG_8195A_DMA("Isr Type %d: Isr Status 0x%x\n", IsrTypeIndex, IsrStatus);
|
||||
|
||||
IsrStatus = (IsrStatus & (pHalGdmaAdapter->ChEn & 0xFF));
|
||||
|
||||
if (BIT_(IsrTypeIndex) & pHalGdmaAdapter->GdmaIsrType) {
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_CLEAR_INT_BASE+ (IsrTypeIndex*8)),
|
||||
(IsrStatus)// & (pHalGdmaAdapter->ChEn & 0xFF))
|
||||
);
|
||||
IsrActBitMap |= BIT_(IsrTypeIndex);
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
return IsrActBitMap;
|
||||
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalGdmaChCleanAutoSrcRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
u32 CfgxLow;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
|
||||
|
||||
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_SRC;
|
||||
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
|
||||
CfgxLow
|
||||
);
|
||||
|
||||
DBG_8195A_DMA("CFG Low data:0x%x\n",
|
||||
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
|
||||
}
|
||||
|
||||
VOID
|
||||
HalGdmaChCleanAutoDstRtl8195a (
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
u32 CfgxLow;
|
||||
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
|
||||
CfgxLow = HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF));
|
||||
|
||||
CfgxLow &= BIT_INVC_CFGX_LO_RELOAD_DST;
|
||||
|
||||
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
|
||||
(REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF),
|
||||
CfgxLow
|
||||
);
|
||||
DBG_8195A_DMA("CFG Low data:0x%x\n",
|
||||
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
|
||||
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
|
||||
|
||||
#include "rtl8195a.h"
|
||||
#include "hal_peri_on.h"
|
||||
|
||||
#ifdef CONFIG_PWM_EN
|
||||
#include "rtl8195a_pwm.h"
|
||||
#include "hal_pwm.h"
|
||||
|
||||
extern HAL_PWM_ADAPTER PWMPin[];
|
||||
|
||||
extern HAL_TIMER_OP HalTimerOp;
|
||||
|
||||
/**
|
||||
* @brief Configure a G-Timer to generate a tick with certain time.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
* @param tick_time: the time (micro-second) of a tick
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
Pwm_SetTimerTick_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt,
|
||||
u32 tick_time
|
||||
)
|
||||
{
|
||||
TIMER_ADAPTER TimerAdapter;
|
||||
|
||||
|
||||
if (tick_time <= MIN_GTIMER_TIMEOUT) {
|
||||
tick_time = MIN_GTIMER_TIMEOUT;
|
||||
}
|
||||
else {
|
||||
tick_time = (((tick_time-1)/TIMER_TICK_US)+1) * TIMER_TICK_US;
|
||||
}
|
||||
|
||||
// Initial a G-Timer for the PWM pin
|
||||
if (pPwmAdapt->tick_time != tick_time) {
|
||||
TimerAdapter.IrqDis = 1; // Disable Irq
|
||||
TimerAdapter.IrqHandle.IrqFun = (IRQ_FUN) NULL;
|
||||
TimerAdapter.IrqHandle.IrqNum = TIMER2_7_IRQ;
|
||||
TimerAdapter.IrqHandle.Priority = 10;
|
||||
TimerAdapter.IrqHandle.Data = (u32)NULL;
|
||||
TimerAdapter.TimerId = pPwmAdapt->gtimer_id;
|
||||
TimerAdapter.TimerIrqPriority = 0;
|
||||
TimerAdapter.TimerLoadValueUs = tick_time-1;
|
||||
TimerAdapter.TimerMode = 1; // auto-reload with user defined value
|
||||
|
||||
HalTimerOp.HalTimerInit((VOID*) &TimerAdapter);
|
||||
pPwmAdapt->tick_time = tick_time;
|
||||
DBG_PWM_INFO("%s: Timer_Id=%d Count=%d\n", __FUNCTION__, pPwmAdapt->gtimer_id, tick_time);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the duty ratio of the PWM pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
* @param period: the period time, in micro-second.
|
||||
* @param pulse_width: the pulse width time, in micro-second.
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
HAL_Pwm_SetDuty_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt,
|
||||
u32 period,
|
||||
u32 pulse_width
|
||||
)
|
||||
{
|
||||
u32 RegAddr;
|
||||
u32 RegValue;
|
||||
u32 period_tick;
|
||||
u32 pulsewidth_tick;
|
||||
u32 tick_time;
|
||||
u8 timer_id;
|
||||
u8 pwm_id;
|
||||
|
||||
pwm_id = pPwmAdapt->pwm_id;
|
||||
// Adjust the tick time to a proper value
|
||||
if (period < (MIN_GTIMER_TIMEOUT*2)) {
|
||||
DBG_PWM_ERR ("HAL_Pwm_SetDuty_8195a: Invalid PWM period(%d), too short!!\n", period);
|
||||
tick_time = MIN_GTIMER_TIMEOUT;
|
||||
period = MIN_GTIMER_TIMEOUT*2;
|
||||
}
|
||||
else {
|
||||
tick_time = period / 0x3fc; // a duty cycle be devided into 1020 ticks
|
||||
if (tick_time < MIN_GTIMER_TIMEOUT) {
|
||||
tick_time = MIN_GTIMER_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
Pwm_SetTimerTick_8195a(pPwmAdapt, tick_time);
|
||||
tick_time = pPwmAdapt->tick_time;
|
||||
#if 0
|
||||
// Check if current tick time needs adjustment
|
||||
if ((pPwmAdapt->tick_time << 12) <= period) {
|
||||
// need a longger tick time
|
||||
}
|
||||
else if ((pPwmAdapt->tick_time >> 2) >= period) {
|
||||
// need a shorter tick time
|
||||
}
|
||||
#endif
|
||||
period_tick = period/tick_time;
|
||||
if (period_tick == 0) {
|
||||
period_tick = 1;
|
||||
}
|
||||
|
||||
if (pulse_width >= period) {
|
||||
// pulse_width = period-1;
|
||||
pulse_width = period;
|
||||
}
|
||||
pulsewidth_tick = pulse_width/tick_time;
|
||||
if (pulsewidth_tick == 0) {
|
||||
// pulsewidth_tick = 1;
|
||||
}
|
||||
|
||||
timer_id = pPwmAdapt->gtimer_id;
|
||||
|
||||
pPwmAdapt->period = period_tick & 0x3ff;
|
||||
pPwmAdapt->pulsewidth = pulsewidth_tick & 0x3ff;
|
||||
|
||||
RegAddr = REG_PERI_PWM0_CTRL + (pwm_id*4);
|
||||
RegValue = BIT31 | (timer_id<<24) | (pulsewidth_tick<<12) | period_tick;
|
||||
|
||||
HAL_WRITE32(PERI_ON_BASE, RegAddr, RegValue);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes and enable a PWM control pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
* @param sel: pin mux selection
|
||||
* @param timer_id: the G-timer index assigned to this PWM
|
||||
*
|
||||
* @retval HAL_Status
|
||||
*/
|
||||
HAL_Status
|
||||
HAL_Pwm_Init_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
)
|
||||
{
|
||||
u32 pwm_id;
|
||||
u32 pin_sel;
|
||||
|
||||
pwm_id = pPwmAdapt->pwm_id;
|
||||
pin_sel = pPwmAdapt->sel;
|
||||
// Initial a G-Timer for the PWM pin
|
||||
Pwm_SetTimerTick_8195a(pPwmAdapt, MIN_GTIMER_TIMEOUT);
|
||||
|
||||
// Set default duty ration
|
||||
HAL_Pwm_SetDuty_8195a(pPwmAdapt, 20000, 10000);
|
||||
|
||||
// Configure the Pin Mux
|
||||
PinCtrl((PWM0+pwm_id), pin_sel, 1);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable a PWM control pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
HAL_Pwm_Enable_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
)
|
||||
{
|
||||
u32 pwm_id;
|
||||
|
||||
pwm_id = pPwmAdapt->pwm_id;
|
||||
// Configure the Pin Mux
|
||||
if (!pPwmAdapt->enable) {
|
||||
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 1);
|
||||
HalTimerOp.HalTimerEn(pPwmAdapt->gtimer_id);
|
||||
pPwmAdapt->enable = 1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable a PWM control pin.
|
||||
*
|
||||
* @param pwm_id: the PWM pin index
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void
|
||||
HAL_Pwm_Disable_8195a(
|
||||
HAL_PWM_ADAPTER *pPwmAdapt
|
||||
)
|
||||
{
|
||||
u32 pwm_id;
|
||||
|
||||
pwm_id = pPwmAdapt->pwm_id;
|
||||
// Configure the Pin Mux
|
||||
if (pPwmAdapt->enable) {
|
||||
PinCtrl((PWM0+pwm_id), pPwmAdapt->sel, 0);
|
||||
HalTimerOp.HalTimerDis(pPwmAdapt->gtimer_id);
|
||||
pPwmAdapt->enable = 0;
|
||||
}
|
||||
}
|
||||
|
||||
#endif //CONFIG_PWM_EN
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,342 @@
|
|||
/*
|
||||
* Routines to access hardware
|
||||
*
|
||||
* Copyright (c) 2013 Realtek Semiconductor Corp.
|
||||
*
|
||||
* This module is a confidential and proprietary property of RealTek and
|
||||
* possession or use of this module requires written permission of RealTek.
|
||||
*/
|
||||
#include "rtl8195a.h"
|
||||
#include "rtl8195a_timer.h"
|
||||
|
||||
#ifdef CONFIG_TIMER_EN
|
||||
extern u32 gTimerRecord;
|
||||
extern IRQ_FUN Timer2To7VectorTable[MAX_TIMER_VECTOR_TABLE_NUM];
|
||||
|
||||
#ifdef CONFIG_CHIP_A_CUT
|
||||
HAL_RAM_BSS_SECTION u32 gTimerRecord;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CHIP_C_CUT) || defined(CONFIG_CHIP_E_CUT)
|
||||
extern u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
|
||||
#else
|
||||
u32 Timer2To7HandlerData[MAX_TIMER_VECTOR_TABLE_NUM];
|
||||
#endif
|
||||
|
||||
VOID
|
||||
HalTimerIrq2To7Handle_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
u32 TimerIrqStatus = 0, CheckIndex;
|
||||
IRQ_FUN pHandler;
|
||||
|
||||
TimerIrqStatus = HAL_TIMER_READ32(TIMERS_INT_STATUS_OFF);
|
||||
|
||||
DBG_TIMER_INFO("%s:TimerIrqStatus: 0x%x\n",__FUNCTION__, TimerIrqStatus);
|
||||
|
||||
for (CheckIndex = 2; CheckIndex<8; CheckIndex++) {
|
||||
|
||||
//3 Check IRQ status bit and Timer X IRQ enable bit
|
||||
if ((TimerIrqStatus & BIT_(CheckIndex)) &&
|
||||
(HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_CTL_REG_OFF) & BIT0)) {
|
||||
//3 Execute Timer callback function
|
||||
pHandler = Timer2To7VectorTable[CheckIndex-2];
|
||||
if (pHandler != NULL) {
|
||||
pHandler((void*)Timer2To7HandlerData[CheckIndex-2]);
|
||||
}
|
||||
//3 Clear Timer ISR
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*CheckIndex + TIMER_EOI_OFF);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
HAL_Status
|
||||
HalTimerIrqRegisterRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
|
||||
IRQ_HANDLE TimerIrqHandle;
|
||||
//IRQ_FUN BackUpIrqFun = NULL;
|
||||
|
||||
if (pHalTimerAdap->TimerId > 7) {
|
||||
DBG_TIMER_ERR("%s: No Support Timer ID %d!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
else {
|
||||
if (pHalTimerAdap->TimerId > 1) {
|
||||
|
||||
TimerIrqHandle.IrqNum = TIMER2_7_IRQ;
|
||||
TimerIrqHandle.IrqFun = (IRQ_FUN) HalTimerIrq2To7Handle_Patch;
|
||||
|
||||
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] =
|
||||
(IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
|
||||
Timer2To7HandlerData[pHalTimerAdap->TimerId-2] =
|
||||
(uint32_t) pHalTimerAdap->IrqHandle.Data;
|
||||
}
|
||||
else {
|
||||
TimerIrqHandle.IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
|
||||
TimerIrqHandle.IrqFun = (IRQ_FUN) pHalTimerAdap->IrqHandle.IrqFun;
|
||||
}
|
||||
TimerIrqHandle.Data = (u32)pHalTimerAdap;
|
||||
InterruptRegister(&TimerIrqHandle);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
|
||||
// Patch for A/B Cut
|
||||
HAL_Status
|
||||
HalTimerInitRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
|
||||
HAL_Status ret=HAL_OK;
|
||||
u32 ControlReg;
|
||||
|
||||
if ((gTimerRecord & (1<<pHalTimerAdap->TimerId)) != 0) {
|
||||
DBG_TIMER_ERR ("%s:Error! Timer %d is occupied!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
|
||||
return HAL_BUSY;
|
||||
}
|
||||
|
||||
//4 1) Config Timer Setting
|
||||
ControlReg = ((u32)pHalTimerAdap->TimerMode<<1)|((u32)pHalTimerAdap->IrqDis<<2);
|
||||
/*
|
||||
set TimerControlReg
|
||||
0: Timer enable (0,disable; 1,enable)
|
||||
1: Timer Mode (0, free-running mode; 1, user-defined count mode)
|
||||
2: Timer Interrupt Mask (0, not masked; 1,masked)
|
||||
*/
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
|
||||
ControlReg);
|
||||
|
||||
if (pHalTimerAdap->TimerMode) {
|
||||
//User-defined Mode
|
||||
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
|
||||
}
|
||||
else {
|
||||
// set TimerLoadCount Register
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_LOAD_COUNT_OFF),
|
||||
0xFFFFFFFF);
|
||||
}
|
||||
|
||||
//4 2) Setting Timer IRQ
|
||||
if (!pHalTimerAdap->IrqDis) {
|
||||
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
|
||||
//4 2.1) Initial TimerIRQHandle
|
||||
ret = HalTimerIrqRegisterRtl8195a_Patch(pHalTimerAdap);
|
||||
if (HAL_OK != ret) {
|
||||
DBG_TIMER_ERR ("%s: Timer %d Register IRQ Err!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
|
||||
return ret;
|
||||
}
|
||||
//4 2.2) Enable TimerIRQ for Platform
|
||||
InterruptEn((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
|
||||
}
|
||||
else {
|
||||
DBG_TIMER_ERR ("%s: Timer %d ISR Handler is NULL!\r\n", __FUNCTION__, pHalTimerAdap->TimerId);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
}
|
||||
|
||||
//4 4) Enable Timer
|
||||
// HAL_TIMER_WRITE32((TIMER_INTERVAL*pHalTimerAdap->TimerId + TIMER_CTL_REG_OFF),
|
||||
// (ControlReg|0x1));
|
||||
|
||||
gTimerRecord |= (1<<pHalTimerAdap->TimerId);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#elif defined(CONFIG_CHIP_C_CUT)
|
||||
// Patch for C Cut
|
||||
HAL_Status
|
||||
HalTimerInitRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
|
||||
HAL_Status ret=HAL_OK;
|
||||
|
||||
ret = HalTimerInitRtl8195aV02(Data);
|
||||
|
||||
// Patch the Rom code to load the correct count value
|
||||
if (pHalTimerAdap->TimerMode) {
|
||||
//User-defined Mode
|
||||
HalTimerReLoadRtl8195a_Patch(pHalTimerAdap->TimerId ,pHalTimerAdap->TimerLoadValueUs);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
|
||||
|
||||
HAL_Status
|
||||
HalTimerIrqUnRegisterRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
|
||||
PIRQ_HANDLE pTimerIrqHandle;
|
||||
u32 i;
|
||||
|
||||
pTimerIrqHandle = &pHalTimerAdap->IrqHandle;
|
||||
|
||||
if (pHalTimerAdap->TimerId > 7) {
|
||||
DBG_TIMER_ERR("%s:Error: No Support Timer ID!\n", __FUNCTION__);
|
||||
return HAL_ERR_PARA;
|
||||
}
|
||||
else {
|
||||
if (pHalTimerAdap->TimerId > 1) {
|
||||
pTimerIrqHandle->IrqNum = TIMER2_7_IRQ;
|
||||
Timer2To7VectorTable[pHalTimerAdap->TimerId-2] = NULL;
|
||||
for (i=0;i<MAX_TIMER_VECTOR_TABLE_NUM;i++) {
|
||||
if (Timer2To7VectorTable[i] != NULL) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i == MAX_TIMER_VECTOR_TABLE_NUM) {
|
||||
// All timer UnRegister Interrupt
|
||||
InterruptDis((PIRQ_HANDLE)&pHalTimerAdap->IrqHandle);
|
||||
InterruptUnRegister(pTimerIrqHandle);
|
||||
}
|
||||
}
|
||||
else {
|
||||
pTimerIrqHandle->IrqNum = (pHalTimerAdap->TimerId ? TIMER1_IRQ : TIMER0_IRQ);
|
||||
InterruptUnRegister(pTimerIrqHandle);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
VOID
|
||||
HalTimerDeInitRtl8195a_Patch(
|
||||
IN VOID *Data
|
||||
)
|
||||
{
|
||||
PTIMER_ADAPTER pHalTimerAdap = (PTIMER_ADAPTER) Data;
|
||||
u32 timer_id;
|
||||
|
||||
timer_id = pHalTimerAdap->TimerId;
|
||||
HalTimerDisRtl8195a (timer_id);
|
||||
if (!pHalTimerAdap->IrqDis) {
|
||||
if (pHalTimerAdap->IrqHandle.IrqFun != NULL) {
|
||||
HalTimerIrqUnRegisterRtl8195a_Patch(pHalTimerAdap);
|
||||
}
|
||||
}
|
||||
|
||||
gTimerRecord &= ~(1<<pHalTimerAdap->TimerId);
|
||||
}
|
||||
|
||||
u32
|
||||
HalTimerReadCountRtl8195a_Patch(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
u32 TimerCountOld;
|
||||
u32 TimerCountNew;
|
||||
u32 TimerRDCnt;
|
||||
|
||||
TimerRDCnt = 0;
|
||||
TimerCountOld = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
|
||||
while(1) {
|
||||
TimerCountNew = HAL_TIMER_READ32(TimerId*TIMER_INTERVAL + TIMER_CURRENT_VAL_OFF);
|
||||
|
||||
if (TimerCountOld == TimerCountNew) {
|
||||
return (u32)TimerCountOld;
|
||||
}
|
||||
else {
|
||||
TimerRDCnt++;
|
||||
TimerCountOld = TimerCountNew;
|
||||
|
||||
if (TimerRDCnt >= 2){
|
||||
return (u32)TimerCountOld;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT)
|
||||
|
||||
#if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
|
||||
|
||||
VOID
|
||||
HalTimerReLoadRtl8195a_Patch(
|
||||
IN u32 TimerId,
|
||||
IN u32 LoadUs
|
||||
)
|
||||
{
|
||||
u32 LoadCount = 0;
|
||||
u32 ms125; // how many 125ms
|
||||
u32 remain_us;
|
||||
|
||||
ms125 = LoadUs/125000;
|
||||
remain_us = LoadUs - (ms125*125000);
|
||||
LoadCount = ms125 * (GTIMER_CLK_HZ/8);
|
||||
LoadCount += (remain_us*GTIMER_CLK_HZ)/1000000;
|
||||
if (LoadCount == 0) {
|
||||
LoadCount = 1;
|
||||
}
|
||||
|
||||
// DBG_TIMER_INFO("%s: Load Count=0x%x\r\n", __FUNCTION__, LoadCount);
|
||||
// set TimerLoadCount Register
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_LOAD_COUNT_OFF),
|
||||
LoadCount);
|
||||
}
|
||||
|
||||
#endif // #if defined(CONFIG_CHIP_A_CUT) || defined(CONFIG_CHIP_B_CUT) || defined(CONFIG_CHIP_C_CUT)
|
||||
|
||||
VOID
|
||||
HalTimerIrqEnRtl8195a(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~(BIT2)));
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTimerIrqDisRtl8195a(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT2));
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTimerClearIsrRtl8195a(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_EOI_OFF);
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTimerEnRtl8195a_Patch(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) | (BIT0));
|
||||
}
|
||||
|
||||
VOID
|
||||
HalTimerDisRtl8195a_Patch(
|
||||
IN u32 TimerId
|
||||
)
|
||||
{
|
||||
// Disable Timer will alos disable the IRQ, so need to re-enable the IRQ when re-enable the timer
|
||||
HAL_TIMER_WRITE32((TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF),
|
||||
HAL_TIMER_READ32(TIMER_INTERVAL*TimerId + TIMER_CTL_REG_OFF) & (~BIT0));
|
||||
}
|
||||
|
||||
#endif // CONFIG_TIMER_EN
|
||||
File diff suppressed because it is too large
Load diff
Loading…
Add table
Add a link
Reference in a new issue