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RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmFunc.h

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+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.20
+ * @date     25. February 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  __ASM volatile ("");
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  /* Empty asm statement works as a scheduling barrier */
+  __ASM volatile ("");
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+  __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmInstr.h

@@ -0,0 +1,688 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V3.20
+ * @date     05. March 2013
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2013 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
+ * Otherwise, use general registers, specified by constrant "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
+    so that all instructions following the ISB are fetched from cache or
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier.
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (short)__builtin_bswap16(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+#endif
+}
+
+
+/** \brief  Rotate Right in unsigned value (32 bit)
+
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+
+    \param [in]    value  Value to rotate
+    \param [in]    value  Number of Bits to rotate
+    \return               Rotated value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  return (op1 >> op2) | (op1 << (32 - op2)); 
+}
+
+
+/** \brief  Breakpoint
+
+    This function causes the processor to enter Debug state.
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+
+    \param [in]    value  is ignored by the processor.
+                   If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+{
+   uint32_t result;
+
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/Descript.ion

@@ -0,0 +1 @@
+app_start.c +

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/app_start.c

@@ -0,0 +1,235 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+//#include "build_info.h"
+#include "rtl8195a.h"
+#ifdef PLATFORM_FREERTOS
+#include "FreeRTOS.h"
+#include "task.h"
+#include "platform_stdlib.h"
+// #include "rtl_lib.h"
+#endif
+
+#if defined (CONFIG_USB_EN) && defined(CONFIG_USB_HOST_ONLY)
+	extern void _usb_init(void);
+#endif
+
+#if defined(CONFIG_SDIO_DEVICE_EN) && defined(CONFIG_SDIO_DEVICE_NORMAL)
+extern VOID HalSdioInit(VOID);
+#endif
+
+#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)
+extern void init_rom_wlan_ram_map(void);
+extern VOID wlan_network(VOID);
+#endif
+
+//3 Monitor App Function
+extern VOID RtlConsolInitRam(u32 Boot, u32 TBLSz, VOID *pTBL);
+#ifndef CONFIG_KERNEL
+extern VOID RtlConsolTaskRom(VOID *Data);
+#endif
+
+#ifndef CONFIG_WITHOUT_MONITOR
+extern COMMAND_TABLE    UartLogRamCmdTable[];
+extern u32 GetRamCmdNum(VOID);
+extern VOID UartLogIrqHandleRam(VOID * Data);
+#endif
+
+#ifdef CONFIG_APP_DEMO
+#define MAIN_APP_DEFAULT_STACK_SIZE         2048
+#define MAIN_APP_DEFAULT_PRIORITY           (tskIDLE_PRIORITY + 1)
+#endif
+
+#ifdef CONFIG_MBED_ENABLED
+extern void __libc_fini_array (void);
+extern void __libc_init_array (void);
+extern  void SVC_Handler (void);
+extern  void PendSV_Handler (void);
+extern  void SysTick_Handler (void);
+#endif
+
+#ifndef CONFIG_WITHOUT_MONITOR
+static 
+VOID
+ReRegisterPlatformLogUart(
+    VOID
+)
+{
+    IRQ_HANDLE          UartIrqHandle;
+    
+    //4 Register Log Uart Callback function
+    UartIrqHandle.Data = (u32)NULL;//(u32)&UartAdapter;
+    UartIrqHandle.IrqNum = UART_LOG_IRQ;
+    UartIrqHandle.IrqFun = (IRQ_FUN) UartLogIrqHandleRam;
+    UartIrqHandle.Priority = 5;
+
+    
+    //4 Register Isr handle
+    InterruptUnRegister(&UartIrqHandle); 
+    InterruptRegister(&UartIrqHandle); 
+#if !TASK_SCHEDULER_DISABLED    
+    RtlConsolInitRam((u32)RAM_STAGE,(u32)GetRamCmdNum(),(VOID*)&UartLogRamCmdTable);
+#else
+    //RtlConsolInit(ROM_STAGE,GetRomCmdNum(),(VOID*)&UartLogRomCmdTable);// executing boot seq., 
+    //pUartLogCtl->TaskRdy = 1;
+    RtlConsolInitRam((u32)ROM_STAGE,(u32)GetRamCmdNum(),(VOID*)&UartLogRamCmdTable);
+#endif
+}
+#endif  // end of "#ifndef CONFIG_WITHOUT_MONITOR"
+
+
+VOID ShowRamBuildInfo(VOID)
+{
+    /*
+    DBG_8195A("=========================================================\n\n");
+    //DBG_8195A("Build Time: "UTS_VERSION"\n");
+    DBG_8195A("Build Time: "RTL8195AFW_COMPILE_TIME"\n");
+    DBG_8195A("Build Author: "RTL8195AFW_COMPILE_BY"\n");    
+    DBG_8195A("Build Host: "RTL8195AFW_COMPILE_HOST"\n");    
+    DBG_8195A("Build ToolChain Version: "RTL195AFW_COMPILER"\n\n");    
+    DBG_8195A("=========================================================\n");
+    */
+}
+
+#ifdef CONFIG_APP_DEMO
+#include "device.h"
+#include "gpio_api.h"   // mbed
+
+_WEAK int main(void)
+{
+    gpio_t gpio_led;
+    
+#ifndef CONFIG_WITHOUT_MONITOR
+    ReRegisterPlatformLogUart();
+#endif
+
+    // Init LED control pin
+    gpio_init(&gpio_led, PC_5);
+    gpio_dir(&gpio_led, PIN_OUTPUT);    // Direction: Output
+    gpio_mode(&gpio_led, PullNone);     // No pull
+    while(1){
+        gpio_write(&gpio_led, !gpio_read(&gpio_led));
+        RtlMsleepOS(1000);
+    }
+
+    return 0;
+}
+#else
+//default main
+_WEAK int main(void)
+{
+    // Init SDIO
+#if defined(CONFIG_SDIO_DEVICE_EN) && defined(CONFIG_SDIO_DEVICE_NORMAL)
+    HalSdioInit();
+#endif
+
+#ifndef CONFIG_WITHOUT_MONITOR
+    ReRegisterPlatformLogUart();
+#endif
+                
+#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)
+	wlan_network();
+#else
+
+#if defined (CONFIG_USB_EN) && defined(CONFIG_USB_HOST_ONLY)
+	_usb_init();
+#endif
+
+#endif  // end of else of "#if defined(CONFIG_WIFI_NORMAL) && defined(CONFIG_NETWORK)"
+
+	//3 4)Enable Schedule
+#if defined(CONFIG_KERNEL) && !TASK_SCHEDULER_DISABLED
+    #ifdef PLATFORM_FREERTOS
+		vTaskStartScheduler();
+    #endif
+#else
+		RtlConsolTaskRom(NULL);
+#endif
+    return 0;
+}
+#endif // end of #if CONFIG_APP_DEMO
+
+__weak void __low_level_init(void)   
+{
+	// weak function
+}
+
+#if defined ( __ICCARM__ )
+#pragma section="SDRAM.bss"
+#pragma section="SDRAM.bss"
+#endif
+// The Main App entry point
+void _AppStart(void)
+{
+#ifdef CONFIG_MBED_ENABLED
+    InterruptForOSInit((VOID*)SVC_Handler,
+                       (VOID*)PendSV_Handler,
+                       (VOID*)SysTick_Handler);
+    __asm (
+        "ldr   r0, =SystemInit\n"
+        "blx   r0\n"
+        "ldr   r0, =_start\n"
+        "bx    r0\n"
+    );
+
+    for(;;);
+#else
+    // It's Not Mbed BSP
+#ifdef CONFIG_KERNEL
+#endif
+
+    // Disable debug info log of spiflash
+    DBG_INFO_MSG_OFF(_DBG_SPI_FLASH_);
+        
+#ifdef CONFIG_APP_DEMO
+#ifdef PLATFORM_FREERTOS
+    xTaskCreate( (TaskFunction_t)main, "MAIN_APP__TASK", (MAIN_APP_DEFAULT_STACK_SIZE/4), (void *)NULL, MAIN_APP_DEFAULT_PRIORITY, NULL);
+    vTaskStartScheduler();
+#endif
+#else
+	
+	__low_level_init();		
+#if defined ( __ICCARM__ )
+	// __iar_data_init3 replaced by __iar_cstart_call_ctors, just do c++ constructor,
+	__iar_cstart_call_ctors(NULL);
+#ifdef CONFIG_SDR_EN
+	// clear SDRAM bss
+	u8* __sdram_bss_start__		= (u8*)__section_begin("SDRAM.bss");
+	u8* __sdram_bss_end__			= (u8*)__section_end("SDRAM.bss");
+	//DiagPrintf("clean sdram bss %8x to %8x\n\r", __sdram_bss_start__, __sdram_bss_end__);
+	if((int)__sdram_bss_end__-(int)__sdram_bss_start__ > 0)
+		memset(__sdram_bss_start__, 0, (int)__sdram_bss_end__-(int)__sdram_bss_start__);
+#endif
+#elif defined ( __GNUC__ )
+#ifdef CONFIG_SDR_EN
+	// clear SDRAM bss	
+	extern u8 __sdram_bss_start__[];
+	extern u8 __sdram_bss_end__[];
+	//DiagPrintf("clean sdram bss %8x to %8x\n\r", __sdram_bss_start__, __sdram_bss_end__);
+	if((int)__sdram_bss_end__-(int)__sdram_bss_start__ > 0)
+		memset(__sdram_bss_start__, 0, (int)__sdram_bss_end__-(int)__sdram_bss_start__);
+#endif
+#else
+	#error !!!!!!NOT Support this compiler!!!!!!
+#endif
+	// force SP align to 8 byte not 4 byte (initial SP is 4 byte align)
+	__asm( 
+		  "mov r0, sp\n"
+		  "bic r0, r0, #7\n" 
+		  "mov sp, r0\n"
+	);
+	
+    main();
+#if defined ( __ICCARM__ )	
+	// for compile issue, If user never call this function, Liking fail 
+	__iar_data_init3();
+#endif
+#endif // end of #if CONFIG_APP_DEMO
+    
+#endif  // end of else of "#ifdef CONFIG_MBED_ENABLED"
+}

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/cmsis.h

@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "rtl8195a.h"
+#include "cmsis_nvic.h"
+
+#endif

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/cmsis_nvic.c

@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Vectors positioned at start of RAM
+#define NVIC_ROM_VECTOR_ADDRESS   (0x00000000)  // Initial vector position at start of ROM
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t *)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/cmsis_nvic.h

@@ -0,0 +1,54 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// CORE: 64 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ...
+// Total: 128 vectors = 512 bytes (0x200) to be reserved in RAM
+#define NVIC_NUM_VECTORS      128
+#define NVIC_USER_IRQ_OFFSET  64
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/diag.h

@@ -0,0 +1,829 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _DIAG_H_
+#define _DIAG_H_
+
+#include "basic_types.h"
+#include "platform_autoconf.h"
+
+#include <stddef.h> /* for size_t */
+
+extern u32 ConfigDebugErr;
+extern u32 ConfigDebugInfo;
+extern u32 ConfigDebugWarn;
+
+extern u32 CfgSysDebugErr;
+extern u32 CfgSysDebugInfo;
+extern u32 CfgSysDebugWarn;
+
+#define DBG_ERR_MSG_ON(x)       (ConfigDebugErr |= (x))
+#define DBG_WARN_MSG_ON(x)      (ConfigDebugWarn |= (x))
+#define DBG_INFO_MSG_ON(x)      (ConfigDebugInfo |= (x))
+
+#define DBG_ERR_MSG_OFF(x)      (ConfigDebugErr &= ~(x))
+#define DBG_WARN_MSG_OFF(x)     (ConfigDebugWarn &= ~(x))
+#define DBG_INFO_MSG_OFF(x)     (ConfigDebugInfo &= ~(x))
+
+// Define debug group
+#define	_DBG_BOOT_          	0x00000001
+#define	_DBG_GDMA_          	0x00000002
+#define	_DBG_GPIO_			    0x00000004
+#define	_DBG_TIMER_         	0x00000008
+#define	_DBG_I2C_           	0x00000010
+#define	_DBG_I2S_           	0x00000020
+#define	_DBG_MII_           	0x00000040
+#define	_DBG_NFC_           	0x00000080
+#define	_DBG_PCM_           	0x00000100
+#define	_DBG_PWM_           	0x00000200
+#define	_DBG_SDIO_          	0x00000400
+#define	_DBG_SSI_           	0x00000800
+#define	_DBG_SPI_FLASH_         0x00001000
+#define	_DBG_SDR_           	0x00002000
+#define	_DBG_UART_          	0x00004000
+#define	_DBG_USB_OTG_           0x00008000
+#define	_DBG_USB_CORE_          0x00010000
+#define	_DBG_CRYPTO_        	0x00020000
+#define	_DBG_ADC_           	0x00040000
+#define	_DBG_DAC_               0x00080000
+#define	_DBG_TCM_HEAP_          0x00100000
+#define	_DBG_RAM_HEAP_          0x00200000
+#define	_DBG_FEEP_          	0x00400000
+
+#define _DBG_MISC_              0x40000000
+#define	_DBG_FAULT_        	    0x80000000
+
+typedef enum _SYSTEM_DBG_DEFINE_ {
+    _SYSDBG_MISC_       = 1<<0,
+    _SYSDBG_MAILBOX_    = 1<<1,
+    _SYSDBG_TIMER_      = 1<<2
+
+} SYSTEM_DBG;
+
+extern
+_LONG_CALL_ROM_ u32
+DiagPrintf(
+    IN  const char *fmt, ...
+);
+
+u32
+DiagSPrintf(
+    IN  u8 *buf,
+    IN  const char *fmt, ...
+);
+
+int
+prvDiagPrintf(
+    IN  const char *fmt, ...
+);
+
+int
+prvDiagSPrintf(
+    IN char *buf,
+    IN  const char *fmt, ...
+);
+
+
+#define _DbgDump  DiagPrintf
+
+#define DRIVER_PREFIX	"RTL8195A[Driver]: "
+#define HAL_PREFIX      "RTL8195A[HAL]: "
+#define DMA_PREFIX      "RTL8195A[DMA]: "
+#define SDIO_PREFIX     "RTL8195A[SDIO]"
+#define MBOX_PREFIX		"[OS-MBOX]"
+#define TIMER_PREFIX	"[OS-TMR]"
+
+#define BOOT_ERR_PREFIX         "[BOOT Err]"
+#define BOOT_WARN_PREFIX        "[BOOT Wrn]"
+#define BOOT_INFO_PREFIX        "[BOOT Inf]"
+
+#define GDMA_ERR_PREFIX         "[GDMA Err]"
+#define GDMA_WARN_PREFIX        "[GDMA Wrn]"
+#define GDMA_INFO_PREFIX        "[GDMA Inf]"
+
+#define GPIO_ERR_PREFIX         "[GPIO Err]"
+#define GPIO_WARN_PREFIX        "[GPIO Wrn]"
+#define GPIO_INFO_PREFIX        "[GPIO Inf]"
+
+#define TIMER_ERR_PREFIX        "[TIMR Err]"
+#define TIMER_WARN_PREFIX       "[TIMR Wrn]"
+#define TIMER_INFO_PREFIX       "[TIMR Inf]"
+
+#define I2C_ERR_PREFIX          "[I2C  Err]"
+#define I2C_WARN_PREFIX         "[I2C  Wrn]"
+#define I2C_INFO_PREFIX         "[I2C  Inf]"
+
+#define I2S_ERR_PREFIX          "[I2S  Err]"
+#define I2S_WARN_PREFIX         "[I2S  Wrn]"
+#define I2S_INFO_PREFIX         "[I2S  Inf]"
+
+#define MII_ERR_PREFIX          "[MII  Err]"
+#define MII_WARN_PREFIX         "[MII  Wrn]"
+#define MII_INFO_PREFIX         "[MII  Inf]"
+
+#define NFC_ERR_PREFIX          "[NFC  Err]"
+#define NFC_WARN_PREFIX         "[NFC  Wrn]"
+#define NFC_INFO_PREFIX         "[NFC  Inf]"
+
+#define PCM_ERR_PREFIX          "[PCM  Err]"
+#define PCM_WARN_PREFIX         "[PCM  Wrn]"
+#define PCM_INFO_PREFIX         "[PCM  Inf]"
+
+#define PWM_ERR_PREFIX          "[PWM  Err]"
+#define PWM_WARN_PREFIX         "[PWM  Wrn]"
+#define PWM_INFO_PREFIX         "[PWM  Inf]"
+
+#define SSI_ERR_PREFIX          "[SSI  Err]"
+#define SSI_WARN_PREFIX         "[SSI  Wrn]"
+#define SSI_INFO_PREFIX         "[SSI  Inf]"
+
+#define SDIO_ERR_PREFIX         "[SDIO Err]"
+#define SDIO_WARN_PREFIX        "[SDIO Wrn]"
+#define SDIO_INFO_PREFIX        "[SDIO Inf]"
+
+#define SPIF_ERR_PREFIX         "[SPIF Err]"
+#define SPIF_WARN_PREFIX        "[SPIF Wrn]"
+#define SPIF_INFO_PREFIX        "[SPIF Inf]"
+
+#define SDR_ERR_PREFIX          "[SDR  Err]"
+#define SDR_WARN_PREFIX         "[SDR  Wrn]"
+#define SDR_INFO_PREFIX         "[SDR  Inf]"
+
+#define UART_ERR_PREFIX         "[UART Err]"
+#define UART_WARN_PREFIX        "[UART Wrn]"
+#define UART_INFO_PREFIX        "[UART Inf]"
+
+#define USB_ERR_PREFIX          "[USB  Err]"
+#define USB_WARN_PREFIX         "[USB  Wrn]"
+#define USB_INFO_PREFIX         "[USB  Inf]"
+
+#define IPSEC_ERR_PREFIX        "[CRYP Err]"
+#define IPSEC_WARN_PREFIX       "[CRYP Wrn]"
+#define IPSEC_INFO_PREFIX       "[CRYP Inf]"
+
+#define ADC_ERR_PREFIX          "[ADC  Err]"
+#define ADC_WARN_PREFIX         "[ADC  Wrn]"
+#define ADC_INFO_PREFIX         "[ADC  Inf]"
+
+#define DAC_ERR_PREFIX          "[DAC  Err]"
+#define DAC_WARN_PREFIX         "[DAC  Wrn]"
+#define DAC_INFO_PREFIX         "[DAC  Inf]"
+
+#define MISC_ERR_PREFIX         "[MISC Err]"
+#define MISC_WARN_PREFIX        "[MISC Wrn]"
+#define MISC_INFO_PREFIX        "[MISC Inf]"
+
+#define OTG_ERR_PREFIX         "[OTG Err]"
+#define OTG_WARN_PREFIX        "[OTG Wrn]"
+#define OTG_INFO_PREFIX        "[OTG Inf]"
+
+#define TCM_ERR_PREFIX         "[TCM Err]"
+#define TCM_WARN_PREFIX        "[TCM Wrn]"
+#define TCM_INFO_PREFIX        "[TCM Inf]"
+
+#define FEEP_ERR_PREFIX         "[FEEP Err]"
+#define FEEP_WARN_PREFIX        "[FEEP Wrn]"
+#define FEEP_INFO_PREFIX        "[FEEP Inf]"
+
+#define OTG_PREFIX      "RTL8195A[OTG]: "
+#define OTG_PREFIX_LVL  "RTL8195A[OTG_LVL_%2x]: "
+
+#ifdef CONFIG_DEBUG_LOG
+ #if CONFIG_DEBUG_LOG > 2
+	#define CONFIG_DEBUG_ERROR      1
+	#define CONFIG_DEBUG_WARN       1
+	#define CONFIG_DEBUG_INFO       1
+ #elif CONFIG_DEBUG_LOG > 1
+	#define CONFIG_DEBUG_ERROR      1
+	#define CONFIG_DEBUG_WARN       1
+ #elif CONFIG_DEBUG_LOG > 0
+	#define CONFIG_DEBUG_ERROR      1
+ #endif
+#endif
+
+#ifndef likely
+#define likely(x)               (x)
+#define unlikely(x)             (x)
+#endif
+
+
+#if CONFIG_DEBUG_ERROR      // if Build-In Debug Error Message
+
+#define DBG_BOOT_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_BOOT_)) \
+        _DbgDump(BOOT_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GDMA_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_GDMA_)) \
+        _DbgDump(GDMA_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GPIO_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_GPIO_)) \
+        _DbgDump(GPIO_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TIMER_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_TIMER_)) \
+        _DbgDump(TIMER_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2C_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_I2C_)) \
+        _DbgDump(I2C_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2S_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_I2S_)) \
+        _DbgDump(I2S_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MII_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_MII_)) \
+        _DbgDump(MII_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_NFC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_NFC_)) \
+        _DbgDump(NFC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PCM_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_PCM_)) \
+        _DbgDump(PCM_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PWM_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_PWM_)) \
+        _DbgDump(PWM_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SSI_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SSI_)) \
+        _DbgDump(SSI_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDIO_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SDIO_)) \
+        _DbgDump(SDIO_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SPIF_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SPI_FLASH_)) \
+        _DbgDump(SPIF_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDR_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_SDR_)) \
+        _DbgDump(SDR_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_UART_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_UART_)) \
+        _DbgDump(UART_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBOTG_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_USB_OTG_)) \
+        _DbgDump( __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBCOR_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_USB_CORE_)) \
+        _DbgDump(USB_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_CRYPTO_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_CRYPTO_)) \
+        _DbgDump(IPSEC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_ADC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_ADC_)) \
+        _DbgDump(ADC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_DAC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_DAC_)) \
+        _DbgDump(DAC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_MBOX_ERR(...)     do {\
+    if (likely(CfgSysDebugErr & _SYSDBG_MAILBOX_)) \
+        _DbgDump(MBOX_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_TIMER_ERR(...)     do {\
+    if (likely(CfgSysDebugErr & _SYSDBG_TIMER_)) \
+        _DbgDump(TIMER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_OTG(...)  do{\
+                if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
+                    _DbgDump(OTG_PREFIX __VA_ARGS__);\
+            }while(0)
+
+#define DBG_8195A_OTG_INFO(...)  do{\
+                if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
+                    _DbgDump(OTG_PREFIX __VA_ARGS__);\
+            }while(0)
+
+#define DBG_8195A_OTG_WARN(...)  do{\
+                if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \
+                    _DbgDump(OTG_PREFIX __VA_ARGS__);\
+            }while(0)
+
+#define DBG_8195A_OTG_ERR(...)  do{\
+                if (unlikely(ConfigDebugErr & _DBG_USB_OTG_)) \
+                    _DbgDump(OTG_PREFIX __VA_ARGS__);\
+            }while(0)
+            
+#define DBG_8195A_OTG_LVL(LVL,...)  do{\
+    if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)){ \
+        _DbgDump(OTG_PREFIX_LVL,LVL);\
+        _DbgDump(__VA_ARGS__);\
+    }\
+}while(0)
+
+#define DBG_TCM_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_TCM_HEAP_)) \
+        _DbgDump(TCM_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MISC_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_MISC_)) \
+        _DbgDump(MISC_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_FEEP_ERR(...)     do {\
+    if (likely(ConfigDebugErr & _DBG_FEEP_)) \
+        _DbgDump(FEEP_ERR_PREFIX __VA_ARGS__);\
+}while(0)
+
+
+#else   // else of "#if CONFIG_DEBUG_ERROR"
+
+#define DBG_BOOT_ERR(...)
+#define DBG_GDMA_ERR(...)
+#define DBG_GPIO_ERR(...)
+#define DBG_TIMER_ERR(...)
+#define DBG_I2C_ERR(...)
+#define DBG_I2S_ERR(...)
+#define DBG_MII_ERR(...)
+#define DBG_NFC_ERR(...)
+#define DBG_PCM_ERR(...)
+#define DBG_PWM_ERR(...)
+#define DBG_SSI_ERR(...)
+#define DBG_SDIO_ERR(...)
+#define DBG_SPIF_ERR(...)
+#define DBG_SDR_ERR(...)
+#define DBG_UART_ERR(...)
+#define DBG_USBOTG_ERR(...)
+#define DBG_USBCOR_ERR(...)
+#define DBG_CRYPTO_ERR(...)
+#define DBG_ADC_ERR(...)
+#define DBG_DAC_ERR(...)
+
+#define MSG_MBOX_ERR(...)
+#define MSG_TIMER_ERR(...)
+#define DBG_8195A_OTG(...)
+#define DBG_8195A_OTG_LVL(LVL,...)
+#define DBG_8195A_OTG_INFO(...)
+#define DBG_8195A_OTG_WARN(...)
+#define DBG_8195A_OTG_ERR(...)
+
+#define DBG_TCM_ERR(...)
+#define DBG_FEEP_ERR(...)
+
+#endif  // end of else of "#if CONFIG_DEBUG_ERROR"
+
+// =============================================================
+
+#if CONFIG_DEBUG_WARN     // if Build-In Debug Warring Message
+
+#define DBG_BOOT_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn& _DBG_BOOT_)) \
+        _DbgDump(BOOT_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GDMA_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_GDMA_)) \
+        _DbgDump(GDMA_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GPIO_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_GPIO_)) \
+        _DbgDump(GPIO_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TIMER_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_TIMER_)) \
+        _DbgDump(TIMER_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2C_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_I2C_)) \
+        _DbgDump(I2C_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2S_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_I2S_)) \
+        _DbgDump(I2S_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MII_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_MII_)) \
+        _DbgDump(MII_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_NFC_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_NFC_)) \
+        _DbgDump(NFC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PCM_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_PCM_)) \
+        _DbgDump(PCM_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PWM_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_PWM_)) \
+        _DbgDump(PWM_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SSI_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SSI_)) \
+        _DbgDump(SSI_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDIO_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SDIO_)) \
+        _DbgDump(SDIO_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SPIF_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SPI_FLASH_)) \
+        _DbgDump(SPIF_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDR_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_SDR_)) \
+        _DbgDump(SDR_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_UART_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_UART_)) \
+        _DbgDump(UART_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBOTG_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_USB_OTG_)) \
+        _DbgDump( __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBCOR_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_USB_CORE_)) \
+        _DbgDump(USB_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_CRYPTO_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_CRYPTO_)) \
+        _DbgDump(IPSEC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_ADC_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_ADC_)) \
+        _DbgDump(ADC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_DAC_WARN(...)     do {\
+    if (unlikely(ConfigDebugWarn & _DBG_DAC_)) \
+        _DbgDump(DAC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_MBOX_WARN(...)     do {\
+    if (unlikely(CfgSysDebugWarn& _SYSDBG_MAILBOX_)) \
+        _DbgDump(MBOX_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_TIMER_WARN(...)     do {\
+    if (unlikely(CfgSysDebugWarn & _SYSDBG_TIMER_)) \
+        _DbgDump(TIMER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TCM_WARN(...)     do {\
+    if (likely(ConfigDebugWarn & _DBG_TCM_HEAP_)) \
+        _DbgDump(TCM_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_FEEP_WARN(...)     do {\
+    if (likely(ConfigDebugWarn & _DBG_FEEP_)) \
+        _DbgDump(FEEP_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MISC_WARN(...)     do {\
+    if (likely(ConfigDebugWarn & _DBG_MISC_)) \
+        _DbgDump(MISC_WARN_PREFIX __VA_ARGS__);\
+}while(0)
+
+#else   // else of "#if CONFIG_DEBUG_WARN"
+
+#define DBG_BOOT_WARN(...)
+#define DBG_GDMA_WARN(...)
+#define DBG_GPIO_WARN(...)
+#define DBG_TIMER_WARN(...)
+#define DBG_I2C_WARN(...)
+#define DBG_I2S_WARN(...)
+#define DBG_MII_WARN(...)
+#define DBG_NFC_WARN(...)
+#define DBG_PCM_WARN(...)
+#define DBG_PWM_WARN(...)
+#define DBG_SSI_WARN(...)
+#define DBG_SDIO_WARN(...)
+#define DBG_SPIF_WARN(...)
+#define DBG_SDR_WARN(...)
+#define DBG_UART_WARN(...)
+#define DBG_USBOTG_WARN(...)
+#define DBG_USBCOR_WARN(...)
+#define DBG_CRYPTO_WARN(...)
+#define DBG_ADC_WARN(...)
+#define DBG_DAC_WARN(...)
+#define DBG_TCM_WARN(...)
+#define DBG_FEEP_WARN(...)
+#define DBG_MISC_WARN(...)
+
+#define MSG_MBOX_WARN(...)
+#define MSG_TIMER_WARN(...)
+
+#endif  // end of else of "#if CONFIG_DEBUG_WARN"
+
+// =============================================================
+
+#if CONFIG_DEBUG_INFO     // if Build-In Debug Information Message
+
+#define DBG_BOOT_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_BOOT_)) \
+        _DbgDump(BOOT_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GDMA_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_GDMA_)) \
+        _DbgDump(GDMA_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_GPIO_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_GPIO_)) \
+        _DbgDump(GPIO_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TIMER_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_TIMER_)) \
+        _DbgDump(TIMER_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2C_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_I2C_)) \
+        _DbgDump(I2C_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_I2S_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_I2S_)) \
+        _DbgDump(I2S_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MII_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_MII_)) \
+        _DbgDump(MII_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_NFC_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_NFC_)) \
+        _DbgDump(NFC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PCM_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_PCM_)) \
+        _DbgDump(PCM_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_PWM_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_PWM_)) \
+        _DbgDump(PWM_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SSI_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SSI_)) \
+        _DbgDump(SSI_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDIO_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SDIO_)) \
+        _DbgDump(SDIO_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SPIF_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SPI_FLASH_)) \
+        _DbgDump(SPIF_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_SDR_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_SDR_)) \
+        _DbgDump(SDR_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_UART_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_UART_)) \
+        _DbgDump(UART_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBOTG_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_USB_OTG_)) \
+        _DbgDump( __VA_ARGS__);\
+}while(0)
+
+#define DBG_USBCOR_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_USB_CORE_)) \
+        _DbgDump(USB_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_CRYPTO_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_CRYPTO_)) \
+        _DbgDump(IPSEC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_ADC_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_ADC_)) \
+        _DbgDump(ADC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_DAC_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_DAC_)) \
+        _DbgDump(DAC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_MBOX_INFO(...)     do {\
+    if (unlikely(CfgSysDebugInfo & _SYSDBG_MAILBOX_)) \
+        _DbgDump(MBOX_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define MSG_TIMER_INFO(...)     do {\
+    if (unlikely(CfgSysDebugInfo & _SYSDBG_TIMER_)) \
+        _DbgDump(TIMER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_TCM_INFO(...)     do {\
+    if (likely(ConfigDebugInfo & _DBG_TCM_HEAP_)) \
+        _DbgDump(TCM_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_FEEP_INFO(...)     do {\
+    if (unlikely(ConfigDebugInfo & _DBG_FEEP_)) \
+        _DbgDump(FEEP_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_MISC_INFO(...)     do {\
+    if (likely(ConfigDebugInfo & _DBG_MISC_)) \
+        _DbgDump(MISC_INFO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#else   // else of "#if CONFIG_DEBUG_INFO"
+
+#define DBG_BOOT_INFO(...)
+#define DBG_GDMA_INFO(...)
+#define DBG_GPIO_INFO(...)
+#define DBG_TIMER_INFO(...)
+#define DBG_I2C_INFO(...)
+#define DBG_I2S_INFO(...)
+#define DBG_MII_INFO(...)
+#define DBG_NFC_INFO(...)
+#define DBG_PCM_INFO(...)
+#define DBG_PWM_INFO(...)
+#define DBG_SSI_INFO(...)
+#define DBG_SDIO_INFO(...)
+#define DBG_SPIF_INFO(...)
+#define DBG_SDR_INFO(...)
+#define DBG_UART_INFO(...)
+#define DBG_USBOTG_INFO(...)
+#define DBG_USBCOR_INFO(...)
+#define DBG_CRYPTO_INFO(...)
+#define DBG_ADC_INFO(...)
+#define DBG_DAC_INFO(...)
+#define DBG_TCM_INFO(...)
+#define DBG_FEEP_INFO(...)
+#define DBG_MISC_INFO(...)
+
+#define MSG_MBOX_INFO(...)
+#define MSG_TIMER_INFO(...)
+
+#endif  // end of else of "#if CONFIG_DEBUG_INFO"
+
+// =============================================================
+
+#ifdef CONFIG_DEBUG_LOG
+
+#define DBG_8195A_DRIVER(...)     do {\
+    if (unlikely(ConfigDebugErr & (_DBG_I2S_|_DBG_PCM_|_DBG_TIMER_))) \
+        _DbgDump(DRIVER_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_HAL(...)     do {\
+    if (unlikely(ConfigDebugErr & (_DBG_SDR_|_DBG_MISC_))) \
+        _DbgDump(HAL_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_DMA(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_GDMA_)) \
+        _DbgDump(DMA_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A_SDIO(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_SDIO_)) \
+        _DbgDump(SDIO_PREFIX __VA_ARGS__);\
+}while(0)
+
+#define DBG_8195A(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_MISC_)) \
+        _DbgDump( __VA_ARGS__);\
+}while(0)
+
+#define MONITOR_LOG(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_MISC_)) \
+        _DbgDump( __VA_ARGS__);\
+}while(0)
+
+#define DBG_ERROR_LOG(...)     do {\
+    if (unlikely(ConfigDebugErr & _DBG_FAULT_)) \
+        _DbgDump( __VA_ARGS__);\
+}while(0)
+
+#ifdef __GNUC__
+#define DBG_ASSERT(x)     do {\
+        if (unlikely(!(x))) \
+            _DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\
+    }while(0)
+#endif
+
+#ifdef __ICCARM__
+#define DBG_ASSERT(x)     do {\
+        if (unlikely(!(x))) \
+            _DbgDump("Assertion: %s:%s, %d\n", __FILE__, __func__, __LINE__);\
+    }while(0)
+#endif
+
+#else // #ifdef CONFIG_DEBUG_LOG
+
+#define DBG_8195A_DRIVER(...)
+#define DBG_8195A_HAL(...)
+#define DBG_8195A_DMA(...)
+#define DBG_8195A_SDIO(...)
+#define DBG_8195A(...)
+#define MONITOR_LOG(...)
+#define DBG_ERROR_LOG(...)
+#define DBG_ASSERT(...)
+
+#endif // #ifdef CONFIG_DEBUG_LOG
+
+// =============================================================
+
+#define ANSI_COLOR_GREEN   "\x1b[32m"
+#define ANSI_COLOR_CYAN    "\x1b[36m"
+#define ANSI_COLOR_YELLOW  "\x1b[33m"
+#define ANSI_COLOR_MAGENTA "\x1b[35m"
+#define ANSI_COLOR_RED     "\x1b[31m"
+#define ANSI_COLOR_BLUE    "\x1b[34m"
+#define ANSI_COLOR_RESET   "\x1b[0m"
+
+#define IDENT_ONE_SPACE    " "
+#define IDENT_TWO_SPACE    "  "
+#define IDENT_FOUR_SPACE   "    "
+#define IDENT_SIX_SPACE    "      "
+#define IDENT_EIGHT_SPACE  "        "
+
+// =============================================================
+
+#ifdef CONFIG_DEBUG_LOG
+typedef enum _DBG_CFG_TYPE_ {
+	DBG_CFG_ERR=0,
+	DBG_CFG_WARN=1,
+	DBG_CFG_INFO=2
+} DBG_CFG_TYPE;
+
+typedef struct _DBG_CFG_CMD_ {
+	u8 cmd_name[16];
+	u32	cmd_type;
+} DBG_CFG_CMD, *PDBG_CFG_CMD;
+#endif // #ifdef CONFIG_DEBUG_LOG
+
+typedef enum _CONSOLE_OP_STAGE_ {
+    ROM_STAGE = 0,
+    RAM_STAGE = 1
+}CONSOLE_OP_STAGE;
+
+#endif //_DIAG_H_

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/rand.h

@@ -0,0 +1,15 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+u32
+Rand (
+ VOID
+);
+
+

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/rtl_stdlib.h

@@ -0,0 +1,41 @@
+/*
+ *  Routines for standard lib access 
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _RTL_STDLIB_H_
+#define _RTL_STDLIB_H_
+
+#include <basic_types.h>
+#include <strproc.h>
+#include <diag.h>
+
+//
+// string operation
+//
+#define strlen(str)						prvStrLen((const u8*)str)
+#define strcmp(str1, str2)				prvStrCmp((const u8*)str1, (const u8*)str2)
+#define sscanf(src, format...)				//TODO
+#define strtok(str, delim)				prvStrTok(str, delim)
+#define strcpy(dst, src)				prvStrCpy((u8 *)dst, (const u8*)src)
+#define atoi(str)						prvAtoi(str)
+#define strstr(str1, str2)				prvStrStr(str1, str2)
+
+//
+// standard i/o
+//
+#define snprintf						DiagSnPrintf
+#define sprintf							prvDiagSPrintf
+#define printf 							prvDiagPrintf
+
+//
+// memory management
+//
+#define malloc 							pvPortMalloc
+#define free							vPortFree
+
+#endif //_RTL_STDLIB_H_

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/rtl_utility.h

@@ -0,0 +1,70 @@
+/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *                                        
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#ifndef __RTL_UTILITY_H_
+#define __RTL_UTILITY_H_
+
+VOID RtlMemcpy(VOID* dec, VOID* sour, u32 sz);
+u32 RtlMemcmp(VOID *dst, VOID *src, u32 sz);
+VOID RtlMemset(VOID *pbuf, u32 c, u32 sz);
+
+s8 *
+RtlStrncpy(
+    IN  s8 *dest, 
+    IN  const s8 *src, 
+    IN  SIZE_T count
+);
+
+s8 *
+RtlStrcpy(
+    IN  s8 *dest, 
+    IN  const s8 *src
+);
+
+
+SIZE_T
+RtlStrlen(
+    IN  const s8 *s
+);
+
+
+SIZE_T
+RtlStrnlen(
+    IN  const s8 *s, 
+    IN  SIZE_T count
+);
+
+
+int 
+RtlStrcmp(
+    IN  const s8 *cs, 
+    IN  const s8 *ct
+
+);
+
+int
+RtlStrncmp(
+    IN  const s8 *cs, 
+    IN  const s8 *ct, 
+    IN  SIZE_T count
+);
+
+#endif
+
+

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/strproc.h

@@ -0,0 +1,104 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _STRPROC_H_
+#define _STRPROC_H_
+
+#include <stddef.h> /* for size_t */
+#include <stdarg.h>
+
+#ifndef isprint
+#define in_range(c, lo, up)  ((u8)c >= lo && (u8)c <= up)
+#define isprint(c)           in_range(c, 0x20, 0x7f)
+#define isdigit(c)           in_range(c, '0', '9')
+#define isxdigit(c)          (isdigit(c) || in_range(c, 'a', 'f') || in_range(c, 'A', 'F'))
+#define islower(c)           in_range(c, 'a', 'z')
+#define isspace(c)           (c == ' ' || c == '\f' || c == '\n' || c == '\r' || c == '\t' || c == '\v' || c == ',')
+#endif  
+
+
+extern _LONG_CALL_ROM_ char *_strncpy(char *dest, const char *src, size_t count);
+extern _LONG_CALL_ROM_ char *_strcpy(char *dest, const char *src);
+extern _LONG_CALL_ROM_ size_t _strlen(const char *s);
+extern _LONG_CALL_ROM_ size_t _strnlen(const char *s, size_t count);
+extern _LONG_CALL_ROM_ int _strcmp(const char *cs, const char *ct);
+extern _LONG_CALL_ROM_ int _strncmp(const char *cs, const char *ct, size_t count);
+extern _LONG_CALL_ROM_ int _sscanf(const char *buf, const char *fmt, ...);
+extern _LONG_CALL_ROM_ char *_strsep(char **s, const char *ct);
+extern _LONG_CALL_ROM_ char *skip_spaces(const char *str);
+extern _LONG_CALL_ROM_ int skip_atoi(const char **s);
+extern _LONG_CALL_ROM_ int _vsscanf(const char *buf, const char *fmt, va_list args);
+extern _LONG_CALL_ROM_ unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base);
+extern _LONG_CALL_ROM_ long simple_strtol(const char *cp, char **endp, unsigned int base);
+extern _LONG_CALL_ROM_ long long simple_strtoll(const char *cp, char **endp, unsigned int base);
+extern _LONG_CALL_ROM_ unsigned long simple_strtoul(const char *cp, char **endp, unsigned int base);
+extern _LONG_CALL_ROM_ const char *_parse_integer_fixup_radix(const char *s, unsigned int *base);
+extern _LONG_CALL_ROM_ unsigned int _parse_integer(const char *s, unsigned int base, unsigned long long *p);
+extern _LONG_CALL_ROM_ u64 div_u64(u64 dividend, u32 divisor);
+extern _LONG_CALL_ROM_ s64 div_s64(s64 dividend, s32 divisor);
+extern _LONG_CALL_ROM_ u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder);
+extern _LONG_CALL_ROM_ s64 div_s64_rem(s64 dividend, s32 divisor, s32 *remainder);
+extern _LONG_CALL_ROM_ char *_strpbrk(const char *cs, const char *ct);
+extern _LONG_CALL_ROM_ char *_strchr(const char *s, int c);
+
+
+extern _LONG_CALL_ROM_ VOID
+prvStrCpy(
+    IN  u8  *pDES,
+    IN  const u8  *pSRC
+);
+
+extern _LONG_CALL_ROM_ u32
+prvStrLen(
+    IN  const   u8  *pSRC
+);
+
+extern _LONG_CALL_ROM_  u8
+prvStrCmp(
+    IN  const   u8  *string1,
+    IN  const   u8  *string2
+);
+
+extern _LONG_CALL_ROM_ u8*
+StrUpr(
+    IN  u8  *string
+);
+
+extern _LONG_CALL_ROM_ int prvAtoi(
+	IN const char * s
+);
+
+extern _LONG_CALL_ROM_ const char * prvStrStr(
+	IN const char * str1, 
+	IN const char * str2
+);
+
+
+/*
+ * Fast implementation of tolower() for internal usage. Do not use in your
+ * code.
+ */
+static inline char _tolower(const char c)
+{
+    return c | 0x20;
+}
+
+/* Fast check for octal digit */
+static inline int isodigit(const char c)
+{
+    return c >= '0' && c <= '7';
+}
+#ifndef strtoul
+#define strtoul(str, endp, base)       simple_strtoul(str, endp, base)
+#endif
+#ifndef strtol
+#define strtol(str, endp, base)        simple_strtol(str, endp, base)
+#endif
+
+#endif

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/system_8195a.c

@@ -0,0 +1,139 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.c
+ * @brief    CMSIS Device System Source File for
+ *           ARMCM3 Device Series
+ * @version  V1.08
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#include "basic_types.h"
+#include "rtl8195a.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+#define __HSI             ( 8000000UL)
+#define __XTAL            ( 5000000UL)    /* Oscillator frequency             */
+
+//#define __SYSTEM_CLOCK    (5*__XTAL)
+#define __SYSTEM_CLOCK    (200000000UL/6*5) // PLATFORM_CLOCK // 
+
+extern unsigned int rand_x;
+extern u32 HalGetCpuClk(VOID);
+
+#ifdef CONFIG_CHIP_A_CUT
+const u32 SysCpkClkTbl[]= {
+    200000000,
+    100000000,
+    50000000,
+    25000000,
+    12500000,
+    4000000
+};
+#endif
+
+u32 Rand2(void)
+{
+    static unsigned int y = 362436;
+    static unsigned int z = 521288629;
+    static unsigned int c = 7654321;
+
+    unsigned long long t, a= 698769069;
+
+    rand_x = 69069 * rand_x + 12345;
+    y ^= (y << 13); y ^= (y >> 17); y ^= (y << 5);
+    t = a * z + c; c = (t >> 32); z = t;
+
+    return rand_x + y + z;
+}
+
+/*----------------------------------------------------------------------------
+  Clock Variable definitions
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
+
+
+u32
+SystemGetCpuClk(void)
+{
+#ifdef CONFIG_CHIP_A_CUT
+
+    u32  CpuType = 0, CpuClk = 0, FreqDown = 0;
+
+    CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4);
+    FreqDown = HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_SYSPLL_CTRL1) & BIT17;
+
+    CpuClk = SysCpkClkTbl[CpuType];
+
+    if ( !FreqDown ) {
+        if ( CpuClk > 4000000 ){
+            CpuClk = (CpuClk*5/6);
+        }
+    }
+
+    return CpuClk;
+#else
+    return HalGetCpuClk();
+#endif
+}
+
+/*----------------------------------------------------------------------------
+  Clock functions
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)            /* Get Core Clock Frequency      */
+{
+//  SystemCoreClock = __SYSTEM_CLOCK;
+  
+    SystemCoreClock = SystemGetCpuClk();
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit (void)
+{
+    // TODO: Hardware initial
+#ifdef UNALIGNED_SUPPORT_DISABLE
+  SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
+#endif
+
+  //SystemCoreClock = __SYSTEM_CLOCK;
+  //SystemCoreClock = HalGetCpuClk();
+    SystemCoreClockUpdate();
+}

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/system_8195a.h

@@ -0,0 +1,77 @@
+/**************************************************************************//**
+ * @file     system_ARMCM3.h
+ * @brief    CMSIS Device System Header File for
+ *           ARMCM3 Device Series
+ * @version  V1.08
+ * @date     23. November 2012
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2011 - 2012 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#ifndef _SYSTEM_8195A_H
+#define _SYSTEM_8195A_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+extern u32 SystemGetCpuClk(void);
+extern u32 Rand2(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_8195A_H */

RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/va_list.h

@@ -0,0 +1,37 @@
+/*
+ *  Routines to access hardware
+ *
+ *  Copyright (c) 2013 Realtek Semiconductor Corp.
+ *
+ *  This module is a confidential and proprietary property of RealTek and
+ *  possession or use of this module requires written permission of RealTek.
+ */
+
+#ifndef _VA_LIST_H_
+#define _VA_LIST_H_
+
+#include "platform_autoconf.h"
+#include "basic_types.h"
+
+#ifndef va_arg //this part is adapted from linux (Linux/include/acpi/platform/acenv.h)
+
+typedef s32 acpi_native_int;//this definition is in (Linux/include/acpi/actypes.h)
+
+#ifndef _VALIST
+#define _VALIST
+    typedef char *va_list;
+#endif                          /* _VALIST */
+
+/* Storage alignment properties */
+#define  _AUPBND                (sizeof (acpi_native_int) - 1)
+#define  _ADNBND                (sizeof (acpi_native_int) - 1)
+
+/* Variable argument list macro definitions */
+#define _bnd(X, bnd)            (((sizeof (X)) + (bnd)) & (~(bnd)))
+#define va_arg(ap, T)           (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND))))
+#define va_end(ap)              (ap = (va_list) NULL)
+#define va_start(ap, A)         (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND))))
+
+#endif                          /* va_arg */
+
+#endif //_VA_LIST_H_