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https://github.com/pvvx/RTL00MP3.git
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add AutoMake Eclipse
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pvvx
parent
a590693719
commit
cf7a2d9683
5 changed files with 326 additions and 166 deletions
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@ -0,0 +1,256 @@
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ENTRY(Reset_Handler)
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ENTRY(main)
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INCLUDE "export-rom_v04.txt"
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MEMORY
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{
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ROM (rx) : ORIGIN = 0x000000, LENGTH = 1M /* end 0x00100000 */
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ROM_USED_RAM (rwx): ORIGIN = 0x10000000, LENGTH = 0x2400 /* end 0x10002400 */
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BOOT_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
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ROM_HEAP (rwx) : ORIGIN = 0x10002400, LENGTH = 3K /* end 0x10003000 */
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RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12K /* end 0x10006000 */
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BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 424K /* end 0x10070000 */
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TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64K /* end 0x20000000 */
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TCM_TAB (rwx) : ORIGIN = 0x1FFFFD00, LENGTH = 768 /* end 0x20000000 */
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SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M /* end 0x30200000 */
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}
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EXTERN(RAM_IMG2_VALID_PATTEN)
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EXTERN(InfraStart)
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SECTIONS
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{
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/* 0x00000000: ROM */
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.rom :
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{
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__rom_image_start__ = .;
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KEEP(*(.rom));
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__rom_image_end__ = .;
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} > ROM
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/* 0x10000000: SRAM */
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.rom_ram : /* use in rom */
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{
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__ram_image_start__ = .;
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KEEP(*(.ram_dedecated_vector_table)) /* 0x10000000: NewVectorTable */
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KEEP(*(.ram_user_define_irq_table)) /* 0x10000100: UserIrqFunTable */
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KEEP(*(.ram_user_define_data_table)) /* 0x10000200: UserIrqDataTable */
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__rom_bss_start__ = .;
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KEEP(*(.hal.ram.bss)) /* 0x10000300: CfgSysDebugWarn .. _pHAL_Gpio_Adapter */
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KEEP(*(.timer2_7_vector_table.data)) /* 0x10000358: Timer2To7VectorTable */
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KEEP(*(.infra.ram.bss)) /* 0x10000370: first .. z4 */
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KEEP(*(.mon.ram.bss)) /* 0x10000384: pUartLogCtl .. ArgvArray */
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KEEP(*(.wlan_ram_map)) /* 0x100006d4: rom_wlan_ram_map, FalseAlmCnt, ROMInfo, DM_CfoTrack */
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KEEP(*(.ram.rom.wlanmap)) /* align(8) */
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KEEP(*(.libc.ram.bss)) /* 0x10000760: rom_libgloss_ram_map __rtl_malloc_av_ __rtl_errno */
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__rom_bss_end__ = .;
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} > ROM_USED_RAM
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/* 0x10000bc8: bootloader */
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.ram_image1.text . : /* use in rom & boot */
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{
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/* __ram_start_table_start__ = .; */
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__ram_image1_text_start__ = .;
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KEEP(*rtl_boot*.o(.start.ram.data*))
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/* __image1_validate_code__ = .; */
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KEEP(*(.image1.validate.rodata))
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KEEP(*(.infra.ram.data*))
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KEEP(*(.timer.ram.data*))
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KEEP(*(.cutb.ram.data*))
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KEEP(*(.cutc.ram.data*))
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KEEP(*(.libc.reent))
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KEEP(*(.rom.unc.data))
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KEEP(*(.sdr.rand2.data))
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PROVIDE (__ram_image_end__ = .); /* 0x100020c0: end */
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/* boot & images data */
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KEEP(*(.hal.ram.data))
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KEEP(*(.hal.flash.data))
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KEEP(*rtl_boot*.o(.rodata*))
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KEEP(*rtl_boot*.o(.text*))
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KEEP(*rtl_boot*.o(.data*))
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__image1_bss_start__ = .;
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KEEP(*rtl_boot*.o(.bss*))
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__image1_bss_end__ = .;
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__ram_image1_text_end__ = .;
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} > BOOT_RAM
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.romheap :
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{
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__rom_heap_start__ = .;
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end = __rom_heap_start__;
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. = ALIGN(0x1000);
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__rom_heap_end__ = .;
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} > ROM_HEAP
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.ram_heap1 :
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{
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__ram_heap1_start__ = .;
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/* *(.heap1*) */
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} > RAM_HEAP1
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.tcm :
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{
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__ram_tcm_start__ = .;
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__tcm_heap_start__ = .;
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*(.tcm.heap)
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} > TCM
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.soc_ps_monitor :
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{
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__tcm_heap_end__ = .;
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} > TCM_TAB
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.image2.start.table :
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{
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__ram_heap1_end__ = .;
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__ram_image2_text_start__ = .;
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__image2_entry_func__ = .;
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.image2.start.table1$$Base = .;
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KEEP(*(SORT(.image2.ram.data*)))
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__image2_validate_code__ = .;
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KEEP(*(.image2.validate.rodata*))
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KEEP(*(.custom.validate.rodata*))
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} > BD_RAM
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.ram_image2.text :
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{
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*(.infra.ram.start*)
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. = ALIGN(4);
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KEEP(*(.init))
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/* init data */
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. = ALIGN(4);
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PROVIDE (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE (__init_array_end = .);
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. = ALIGN(4);
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KEEP(*(.fini))
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. = ALIGN(4);
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PROVIDE (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE (__fini_array_end = .);
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*(.mon.ram.text*)
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*(.hal.flash.text*)
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*(.hal.sdrc.text*)
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*(.hal.gpio.text*)
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*(.fwu.text*)
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*(.otg.rom.text*)
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*(.text*)
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*(.sdram.text*)
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*(.p2p.text*)
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*(.wps.text*)
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*(.websocket.text*)
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} > BD_RAM
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.ram_image2.rodata :
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{
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*(.rodata*)
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*(.fwu.rodata*)
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*(.sdram.rodata*)
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*(.p2p.rodata*)
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*(.wps.rodata*)
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*(.websocket.rodata*)
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. = ALIGN(4);
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xHeapRegions = .;
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LONG(__ram_heap1_start__)
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LONG(__ram_heap1_end__ - __ram_heap1_start__)
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LONG(__ram_heap2_start__)
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LONG(__ram_heap2_end__ - __ram_heap2_start__)
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LONG(__sdram_heap_start__)
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LONG(__sdram_heap_end__ - __sdram_heap_start__)
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LONG(0)
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LONG(0)
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UartLogRamCmdTable = .;
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KEEP(*(SORT(.mon.tab*)))
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UartLogRamCmdTable_end = .;
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LONG(0)
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} > BD_RAM
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PROVIDE(UartLogRamCmdTableSize = UartLogRamCmdTable_end - UartLogRamCmdTable);
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.ram.data :
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{
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__data_start__ = .;
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*(.data*)
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*(.p2p.data*)
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*(.wps.data*)
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*(.websocket.data*)
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*(.sdram.data*)
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__data_end__ = .;
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__ram_image2_text_end__ = .;
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} > BD_RAM
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.ram.bss :
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{
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__bss_start__ = .;
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.ram.bss$$Base = .;
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*(.hal.flash.data*)
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*(.hal.sdrc.data*)
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*(.hal.gpio.data*)
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*(.fwu.data*)
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*(.bdsram.data*)
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*(.bfsram.data*)
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*(COMMON)
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*(.bss*)
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*(.sdram.bss*)
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*(.p2p.bss*)
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*(.wps.bss*)
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*(.websocket.bss*)
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*(.ssl_ram_map*)
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__bss_end__ = .;
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.ram.bss$$Limit = .;
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} > BD_RAM
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.ram_heap2 :
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{
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. = ALIGN(8);
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__ram_heap2_start__ = .;
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*(.heap*) /* ucHeap */
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} > BD_RAM
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__ram_heap2_end__ = 0x10070000;
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.sdr_text :
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{
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__sdram_data_start__ = .;
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} > SDRAM_RAM
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.sdr_rodata :
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{
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} > SDRAM_RAM
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.sdr_data :
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{
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__sdram_data_end__ = .;
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} > SDRAM_RAM
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.sdr_bss :
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{
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__sdram_bss_start__ = .;
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__sdram_bss_end__ = .;
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. = ALIGN(8);
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__sdram_heap_start__ = .;
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} > SDRAM_RAM
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__sdram_heap_end__ = 0x30200000;
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.boot.head :
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{
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KEEP(*(.loader.head*))
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}
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ASSERT(__ram_image_end__ == 0x100020c0, "Error rom-bios-boot code & data!")
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}
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