mirror of
https://github.com/pvvx/RTL00MP3.git
synced 2025-07-31 12:41:06 +00:00
add boot (startup RAM only!)
This commit is contained in:
pvvx
parent
6278f73e47
commit
bf4fb5d560
30 changed files with 905 additions and 1509 deletions
|
|
@ -715,71 +715,19 @@ SECTIONS
|
|||
/* RAM data used in ROM */
|
||||
|
||||
__ram_image_start__ = 0x10000000;
|
||||
NewVectorTable = 0x10000000;
|
||||
UserIrqFunTable = 0x10000100;
|
||||
UserIrqDataTable = 0x10000200;
|
||||
__rom_bss_start__ = 0x10000300;
|
||||
CfgSysDebugWarn = 0x10000300;
|
||||
CfgSysDebugInfo = 0x10000304;
|
||||
CfgSysDebugErr = 0x10000308;
|
||||
ConfigDebugWarn = 0x1000030c;
|
||||
ConfigDebugInfo = 0x10000310;
|
||||
ConfigDebugErr = 0x10000314;
|
||||
HalTimerOp = 0x10000318;
|
||||
GPIOState = 0x10000334; /* HalPinCtrlRtl8195A() */
|
||||
gTimerRecord = 0x1000034c; /* HalGetTimerIdRtl8195a() */
|
||||
SSI_DBG_CONFIG = 0x10000350; /* HalSsiPinmuxEnableRtl8195a() */
|
||||
_pHAL_Gpio_Adapter = 0x10000354; /* GPIO_FuncOn_8195a() */
|
||||
Timer2To7VectorTable = 0x10000358; /* HalTimerIrqUnRegisterRtl8195aV02() */
|
||||
_rand_first = 0x10000370; /* Rand() */
|
||||
_rand_z1 = 0x10000374; /* Rand() */
|
||||
_rand_z2 = 0x10000378; /* Rand() */
|
||||
_rand_z3 = 0x1000037C; /* Rand() */
|
||||
_rand_z4 = 0x10000380; /* Rand() */
|
||||
pUartLogCtl = 0x10000384; /* UartLogIrqHandle() */
|
||||
UartLogBuf = 0x10000388; /* RtlConsolInit() */
|
||||
UartLogCtl = 0x10000408; /* RtlConsolInit() */
|
||||
UartLogHistoryBuf = 0x10000430; /* */
|
||||
ArgvArray = 0x100006ac; /* GetArgv() */
|
||||
rom_wlan_ram_map = 0x100006d4; /* os_zalloc(), WPS_realloc(),.. */
|
||||
FalseAlmCnt = 0x100006e0; /* ROM_odm_FalseAlarmCounterStatistics() */
|
||||
ROMInfo = 0x10000720; /* ROM_odm_GetDefaultCrytaltalCap(), ROM_odm_SetCrystalCap(), ROM_ODM_CfoTrackingReset(),.. */
|
||||
DM_CfoTrack = 0x10000738; /* ROM_odm_CfoTrackingFlow() */
|
||||
rom_libgloss_ram_map = 0x10000760; /* _rtl_fstat_v1_00(), _rtl_lseek_v1_00(),.. */
|
||||
__rtl_malloc_av_ = 0x10000780; /* __rom_mallocr_init_v1_00(), _rtl_free_r_v1_00().. */
|
||||
__rtl_malloc_trim_threshold = 0x10000b88; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_malloc_top_pad = 0x10000b8c; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_malloc_sbrk_base = 0x10000b90; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_malloc_max_sbrked_mem = 0x10000b94; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_malloc_max_total_mem = 0x10000b98; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_malloc_current_mallinfo = 0x10000b9c; /* __rom_mallocr_init_v1_00() */
|
||||
__rtl_errno = 0x10000bc4; /* __rtl_sread_v1_00(), __rtl_write_v1_00(), __rtl_lseek_v1_00(), __rtl_close_v1_00(), __rtl_sbrk_v1_00().. */
|
||||
__ram_start_table_start__ = 0x10000bc8;
|
||||
__rom_bss_end__ = 0x10000bc8;
|
||||
|
||||
/* BOOT-LOADER */
|
||||
|
||||
bootloader = 0x10000bc8; /* = gRamStartFun, HalResetVsr() */
|
||||
gRamStartFun = 0x10000bc8; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamStartFun = 0x10000bc8; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchWAKE = 0x10000bcc; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchFun0 = 0x10000bd0; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchFun1 = 0x10000bd4; /* HalResetVsrV02(), HalResetVsr() */
|
||||
gRamPatchFun2 = 0x10000bd8; /* HalResetVsrV02(), HalResetVsr() */
|
||||
__image1_validate_code__ = 0x10000bdc; /* 8 bytes HalResetVsrV02(), HalResetVsr() */
|
||||
RAM_IMG1_VALID_PATTEN = 0x10000bdc;
|
||||
rand_x = 0x10000be4; /* ChangeRandSeed_rom().. Sdr_Rand2_rom() */
|
||||
AvaWds = 0x10000be8; /* SdrCalibration_rom() */
|
||||
SdrDramInfo = 0x10001be8; /* SdrCalibration_rom() */
|
||||
SdrDramTiming = 0x10001bfc; /* SdrCalibration_rom() */
|
||||
SdrDramModeReg = 0x10001c30; /* SdrCalibration_rom() */
|
||||
SdrDramDev = 0x10001c4c; /* SdrCalibration_rom() */
|
||||
/* 0x10000be8: buf 0x1000+ bytes SdrCalibration_rom() */
|
||||
_rtl_impure_ptr = 0x10001c60; /* struct _reent * _rtl_impure_ptr = { &impure_reent } (for standard library) */
|
||||
impure_reent = 0x10001c68; /* struct _reent */
|
||||
_rom_unc_data = 0x10002090; /* ? u32 _rom_unc_data[9] */
|
||||
_sdr_rnd2_y = 0x100020b4; /* Sdr_Rand2_rom().. ChangeRandSeed_rom() */
|
||||
_sdr_rnd2_z = 0x100020b8; /* Sdr_Rand2_rom().. ChangeRandSeed_rom() */
|
||||
_sdr_rnd2_c = 0x100020bc; /* Sdr_Rand2_rom().. ChangeRandSeed_rom() */
|
||||
|
||||
|
||||
__ram_image_end__ = 0x10002100;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,13 +1,14 @@
|
|||
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
ENTRY(main)
|
||||
|
||||
INCLUDE "export-rom_v04.txt"
|
||||
|
||||
|
||||
MEMORY
|
||||
{
|
||||
ROM_USED_RAM (rwx): ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
|
||||
ROM (rx) : ORIGIN = 0x000000, LENGTH = 1M /* end 0x00100000 */
|
||||
ROM_USED_RAM (rwx): ORIGIN = 0x10000000, LENGTH = 0x2400 /* end 0x10002400 */
|
||||
BOOT_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
|
||||
ROM_HEAP (rwx) : ORIGIN = 0x10002400, LENGTH = 3K /* end 0x10003000 */
|
||||
RAM_HEAP1 (rwx) : ORIGIN = 0x10003000, LENGTH = 12K /* end 0x10006000 */
|
||||
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 424K /* end 0x10070000 */
|
||||
|
|
@ -17,211 +18,232 @@ MEMORY
|
|||
}
|
||||
|
||||
EXTERN(RAM_IMG2_VALID_PATTEN)
|
||||
EXTERN(main)
|
||||
EXTERN(InfraStart)
|
||||
EXTERN(gImage2EntryFun0)
|
||||
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
__rom_bss_start__ = 0x10000300;
|
||||
__rom_bss_end__ = 0x10000bc8;
|
||||
|
||||
.bootloader :
|
||||
{
|
||||
KEEP(*(.loader.data*))
|
||||
} > ROM_USED_RAM
|
||||
/* 0x00000000: ROM */
|
||||
|
||||
.romheap :
|
||||
{
|
||||
__rom_heap_start__ = .;
|
||||
end = __rom_heap_start__;
|
||||
. = ALIGN(0x1000);
|
||||
__rom_heap_end__ = .;
|
||||
} > ROM_HEAP
|
||||
.rom :
|
||||
{
|
||||
__rom_image_start__ = .;
|
||||
KEEP(*(.rom));
|
||||
__rom_image_end__ = .;
|
||||
} > ROM
|
||||
|
||||
.ram_heap1 :
|
||||
{
|
||||
__ram_heap1_start__ = .;
|
||||
/* *(.heap1*) */
|
||||
} > RAM_HEAP1
|
||||
|
||||
OVERLAY 0x1FFF0000:
|
||||
{
|
||||
.valid
|
||||
{
|
||||
__ram_tcm_start__ = .;
|
||||
*mem.o (.bss*)
|
||||
*memp.o (.bss*)
|
||||
__tcm_heap_start__ = .;
|
||||
*(.tcm.heap)
|
||||
}
|
||||
.dummy
|
||||
{
|
||||
__ram_image1_text_start__ = .;
|
||||
__ram_start_table_start__ = .;
|
||||
KEEP(*(SORT(.start.ram.data*)))
|
||||
__ram_start_table_end__ = .;
|
||||
__image1_validate_code__ = .;
|
||||
KEEP(*(.image1.validate.rodata*))
|
||||
/* 0x10000000: SRAM */
|
||||
|
||||
.rom_ram : /* use in rom */
|
||||
{
|
||||
__ram_image_start__ = .;
|
||||
KEEP(*(.ram_dedecated_vector_table)) /* 0x10000000: NewVectorTable */
|
||||
KEEP(*(.ram_user_define_irq_table)) /* 0x10000100: UserIrqFunTable */
|
||||
KEEP(*(.ram_user_define_data_table)) /* 0x10000200: UserIrqDataTable */
|
||||
__rom_bss_start__ = .;
|
||||
KEEP(*(.hal.ram.bss)) /* 0x10000300: CfgSysDebugWarn .. _pHAL_Gpio_Adapter */
|
||||
KEEP(*(.timer2_7_vector_table.data)) /* 0x10000358: Timer2To7VectorTable */
|
||||
KEEP(*(.infra.ram.bss)) /* 0x10000370: first .. z4 */
|
||||
KEEP(*(.mon.ram.bss)) /* 0x10000384: pUartLogCtl .. ArgvArray */
|
||||
KEEP(*(.wlan_ram_map)) /* 0x100006d4: rom_wlan_ram_map, FalseAlmCnt, ROMInfo, DM_CfoTrack */
|
||||
KEEP(*(.ram.rom.wlanmap)) /* align(8) */
|
||||
KEEP(*(.libc.ram.bss)) /* 0x10000760: rom_libgloss_ram_map __rtl_malloc_av_ __rtl_errno */
|
||||
__rom_bss_end__ = .;
|
||||
} > ROM_USED_RAM
|
||||
|
||||
/* 0x10000bc8: bootloader */
|
||||
|
||||
.ram_image1.text . : /* use in rom & boot */
|
||||
{
|
||||
/* __ram_start_table_start__ = .; */
|
||||
__ram_image1_text_start__ = .;
|
||||
KEEP(*(SORT(.start.ram.data*)))
|
||||
/* __image1_validate_code__ = .; */
|
||||
KEEP(*(.image1.validate.rodata))
|
||||
|
||||
KEEP(*(.infra.ram.data*))
|
||||
KEEP(*(.timer.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.hal.ram.data*))
|
||||
KEEP(*(.cutb.ram.data*))
|
||||
KEEP(*(.cutc.ram.data*))
|
||||
KEEP(*(.libc.reent))
|
||||
KEEP(*(.rom.unc.data))
|
||||
KEEP(*(.sdr.rand2.data))
|
||||
__ram_image_end__ = .;
|
||||
/* 0x100020c0: end */
|
||||
/* boot & images data */
|
||||
KEEP(*(.hal.ram.data))
|
||||
KEEP(*(.hal.flash.data))
|
||||
/* KEEP(*(.data)); ? */
|
||||
build/obj/project/src/user/rtl_bios_data.o (.rodata*)
|
||||
KEEP(*(.ram.boot.text))
|
||||
build/obj/project/src/user/rtl_boot.o (.rodata*)
|
||||
__image1_bss_start__ = .;
|
||||
.ram_image1.bss$$Base = .;
|
||||
__image1_bss_end__ = .;
|
||||
.ram_image1.bss$$Limit = .;
|
||||
__ram_image1_data_end__ = .;
|
||||
|
||||
*(.hal.ram.text*)
|
||||
*(.infra.ram.text*)
|
||||
}
|
||||
} > TCM
|
||||
__image1_bss_end__ = .;
|
||||
__ram_image1_text_end__ = .;
|
||||
} > BOOT_RAM
|
||||
|
||||
.soc_ps_monitor :
|
||||
{
|
||||
__tcm_heap_end__ = .;
|
||||
} > TCM_TAB
|
||||
.romheap :
|
||||
{
|
||||
__rom_heap_start__ = .;
|
||||
end = __rom_heap_start__;
|
||||
. = ALIGN(0x1000);
|
||||
__rom_heap_end__ = .;
|
||||
} > ROM_HEAP
|
||||
|
||||
.image2.start.table :
|
||||
{
|
||||
__ram_heap1_end__ = .;
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
.image2.start.table1$$Base = .;
|
||||
KEEP(*(SORT(.image2.ram.data*)))
|
||||
__image2_validate_code__ = .;
|
||||
KEEP(*(.image2.validate.rodata*))
|
||||
KEEP(*(.custom.validate.rodata*))
|
||||
} > BD_RAM
|
||||
.ram_heap1 :
|
||||
{
|
||||
__ram_heap1_start__ = .;
|
||||
/* *(.heap1*) */
|
||||
} > RAM_HEAP1
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
*(.infra.ram.start*)
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
.tcm :
|
||||
{
|
||||
__ram_tcm_start__ = .;
|
||||
__tcm_heap_start__ = .;
|
||||
*(.tcm.heap)
|
||||
} > TCM
|
||||
|
||||
/* init data */
|
||||
. = ALIGN(4);
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
.soc_ps_monitor :
|
||||
{
|
||||
__tcm_heap_end__ = .;
|
||||
} > TCM_TAB
|
||||
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
.image2.start.table :
|
||||
{
|
||||
__ram_heap1_end__ = .;
|
||||
__ram_image2_text_start__ = .;
|
||||
__image2_entry_func__ = .;
|
||||
.image2.start.table1$$Base = .;
|
||||
KEEP(*(SORT(.image2.ram.data*)))
|
||||
__image2_validate_code__ = .;
|
||||
KEEP(*(.image2.validate.rodata*))
|
||||
KEEP(*(.custom.validate.rodata*))
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.text :
|
||||
{
|
||||
*(.infra.ram.start*)
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
|
||||
. = ALIGN(4);
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
/* init data */
|
||||
. = ALIGN(4);
|
||||
PROVIDE (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE (__init_array_end = .);
|
||||
|
||||
*(.mon.ram.text*)
|
||||
*(.hal.flash.text*)
|
||||
*(.hal.sdrc.text*)
|
||||
*(.hal.gpio.text*)
|
||||
*(.fwu.text*)
|
||||
*(.otg.rom.text*)
|
||||
*(.text*)
|
||||
*(.sdram.text*)
|
||||
*(.p2p.text*)
|
||||
*(.wps.text*)
|
||||
*(.websocket.text*)
|
||||
} > BD_RAM
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.fini))
|
||||
|
||||
.ram_image2.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
PROVIDE (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE (__fini_array_end = .);
|
||||
|
||||
*(.mon.ram.text*)
|
||||
*(.hal.flash.text*)
|
||||
*(.hal.sdrc.text*)
|
||||
*(.hal.gpio.text*)
|
||||
*(.fwu.text*)
|
||||
*(.otg.rom.text*)
|
||||
*(.text*)
|
||||
*(.sdram.text*)
|
||||
*(.p2p.text*)
|
||||
*(.wps.text*)
|
||||
*(.websocket.text*)
|
||||
} > BD_RAM
|
||||
|
||||
.ram_image2.rodata :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.fwu.rodata*)
|
||||
*(.sdram.rodata*)
|
||||
*(.p2p.rodata*)
|
||||
*(.wps.rodata*)
|
||||
*(.websocket.rodata*)
|
||||
. = ALIGN(4);
|
||||
xHeapRegions = .;
|
||||
LONG(__ram_heap1_start__)
|
||||
LONG(__ram_heap1_end__ - __ram_heap1_start__)
|
||||
LONG(__ram_heap2_start__)
|
||||
LONG(__ram_heap2_end__ - __ram_heap2_start__)
|
||||
LONG(__sdram_heap_start__)
|
||||
LONG(__sdram_heap_end__ - __sdram_heap_start__)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
UartLogRamCmdTable = .;
|
||||
KEEP(*(SORT(.mon.tab*)))
|
||||
UartLogRamCmdTable_end = .;
|
||||
LONG(0)
|
||||
} > BD_RAM
|
||||
|
||||
PROVIDE(UartLogRamCmdTableSize = UartLogRamCmdTable_end - UartLogRamCmdTable);
|
||||
*(.fwu.rodata*)
|
||||
*(.sdram.rodata*)
|
||||
*(.p2p.rodata*)
|
||||
*(.wps.rodata*)
|
||||
*(.websocket.rodata*)
|
||||
. = ALIGN(4);
|
||||
xHeapRegions = .;
|
||||
LONG(__ram_heap1_start__)
|
||||
LONG(__ram_heap1_end__ - __ram_heap1_start__)
|
||||
LONG(__ram_heap2_start__)
|
||||
LONG(__ram_heap2_end__ - __ram_heap2_start__)
|
||||
LONG(__sdram_heap_start__)
|
||||
LONG(__sdram_heap_end__ - __sdram_heap_start__)
|
||||
LONG(0)
|
||||
LONG(0)
|
||||
UartLogRamCmdTable = .;
|
||||
KEEP(*(SORT(.mon.tab*)))
|
||||
UartLogRamCmdTable_end = .;
|
||||
LONG(0)
|
||||
} > BD_RAM
|
||||
|
||||
PROVIDE(UartLogRamCmdTableSize = UartLogRamCmdTable_end - UartLogRamCmdTable);
|
||||
|
||||
.ram.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
*(.p2p.data*)
|
||||
*(.wps.data*)
|
||||
*(.websocket.data*)
|
||||
*(.sdram.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
.ram.bss$$Base = .;
|
||||
*(.hal.flash.data*)
|
||||
*(.hal.sdrc.data*)
|
||||
*(.hal.gpio.data*)
|
||||
*(.fwu.data*)
|
||||
*(.bdsram.data*)
|
||||
.ram.data :
|
||||
{
|
||||
__data_start__ = .;
|
||||
*(.data*)
|
||||
*(.p2p.data*)
|
||||
*(.wps.data*)
|
||||
*(.websocket.data*)
|
||||
*(.sdram.data*)
|
||||
__data_end__ = .;
|
||||
__ram_image2_text_end__ = .;
|
||||
} > BD_RAM
|
||||
|
||||
.ram.bss :
|
||||
{
|
||||
__bss_start__ = .;
|
||||
.ram.bss$$Base = .;
|
||||
*(.hal.flash.data*)
|
||||
*(.hal.sdrc.data*)
|
||||
*(.hal.gpio.data*)
|
||||
*(.fwu.data*)
|
||||
*(.bdsram.data*)
|
||||
*(.bfsram.data*)
|
||||
*(COMMON)
|
||||
*(.bss*)
|
||||
*(.sdram.bss*)
|
||||
*(.p2p.bss*)
|
||||
*(.wps.bss*)
|
||||
*(.websocket.bss*)
|
||||
*(.ssl_ram_map*)
|
||||
__bss_end__ = .;
|
||||
.ram.bss$$Limit = .;
|
||||
|
||||
} > BD_RAM
|
||||
*(COMMON)
|
||||
*(.bss*)
|
||||
*(.sdram.bss*)
|
||||
*(.p2p.bss*)
|
||||
*(.wps.bss*)
|
||||
*(.websocket.bss*)
|
||||
*(.ssl_ram_map*)
|
||||
__bss_end__ = .;
|
||||
.ram.bss$$Limit = .;
|
||||
|
||||
} > BD_RAM
|
||||
|
||||
.ram_heap2 :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__ram_heap2_start__ = .;
|
||||
KEEP(*(.heap*)) /* ucHeap */
|
||||
} > BD_RAM
|
||||
__ram_heap2_end__ = 0x10070000;
|
||||
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
.ram_heap2 :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__ram_heap2_start__ = .;
|
||||
*(.heap*) /* ucHeap */
|
||||
} > BD_RAM
|
||||
__ram_heap2_end__ = 0x10070000;
|
||||
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_rodata :
|
||||
{
|
||||
} > SDRAM_RAM
|
||||
.sdr_rodata :
|
||||
{
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_data :
|
||||
{
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
.sdr_data :
|
||||
{
|
||||
__sdram_data_end__ = .;
|
||||
} > SDRAM_RAM
|
||||
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
__sdram_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
__sdram_heap_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
__sdram_heap_end__ = 0x30200000;
|
||||
.sdr_bss :
|
||||
{
|
||||
__sdram_bss_start__ = .;
|
||||
__sdram_bss_end__ = .;
|
||||
. = ALIGN(8);
|
||||
__sdram_heap_start__ = .;
|
||||
} > SDRAM_RAM
|
||||
__sdram_heap_end__ = 0x30200000;
|
||||
|
||||
.boot.head :
|
||||
{
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#ifndef _RTL_BIOS_DATA_H_
|
||||
#define _RTL_BIOS_DATA_H_
|
||||
|
||||
#include "platform_autoconf.h"
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include <stdio.h>
|
||||
|
|
@ -54,7 +55,7 @@ extern u32 ConfigDebugErr; // 10000314
|
|||
|
||||
/* ROM + hal_timer.h & .. */
|
||||
extern HAL_TIMER_OP HalTimerOp; // 10000318
|
||||
extern u16 GPIOState[11]; // 10000334 побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию.
|
||||
extern u16 GPIOState[11]; // 10000334
|
||||
extern u32 gTimerRecord; // 1000034C
|
||||
/* ROM + hal_ssi.h */
|
||||
extern u32 SSI_DBG_CONFIG; // 10000350
|
||||
|
|
@ -167,7 +168,7 @@ extern RAM_START_FUNCTION gRamPatchWAKE; // 10000bcc = { RtlBootToSram + 1 };
|
|||
extern RAM_START_FUNCTION gRamPatchFun0; // 10000bd0 = { RtlBootToSram + 1 };
|
||||
extern RAM_START_FUNCTION gRamPatchFun1; // 10000bd4 = { RtlBootToSram + 1 };
|
||||
extern RAM_START_FUNCTION gRamPatchFun2; // 10000bd8 = { RtlBootToSram + 1 };
|
||||
extern uint8 RAM_IMG1_VALID_PATTEN[8]; // 10000bdc = { 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
|
||||
//extern uint8 RAM_IMG1_VALID_PATTEN[8]; // 10000bdc = { 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
|
||||
|
||||
/* ROM + hal_sdr_controller.c */
|
||||
extern u32 rand_x; // 10000be4: ChangeRandSeed_rom(), Sdr_Rand2_rom()
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue