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https://github.com/pvvx/RTL00MP3.git
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add boot (startup RAM only!)
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parent
6278f73e47
commit
bf4fb5d560
30 changed files with 905 additions and 1509 deletions
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@ -8,11 +8,9 @@
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*/
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#include "rtl8195a.h"
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#include "hal_spi_flash.h"
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#include "rtl8195a_spi_flash.h"
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#pragma arm section code = ".hal.flash.text", rodata = ".hal.flash.rodata", rwdata = ".hal.flash.data", zidata = ".hal.flash.bss"
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//#pragma arm section code = ".hal.flash.text", rodata = ".hal.flash.rodata", rwdata = ".hal.flash.data", zidata = ".hal.flash.bss"
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//#define SPI_CTRL_BASE 0x1FFEF000
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#define SPI_DLY_CTRL_ADDR 0x40000300 // [7:0]
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@ -88,11 +86,11 @@ SECTION SPIC_INIT_PARA SpicInitParaAllClk[CPU_CLK_TYPE_NO] = {{0,0,0,0},
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{0,0,0,0},
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{0,0,0,0},};
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#else
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HAL_FLASH_DATA_SECTION
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SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO];
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extern HAL_FLASH_DATA_SECTION
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SPIC_INIT_PARA SpicInitParaAllClk[SpicMaxMode][CPU_CLK_TYPE_NO]; // in rtl_bios_data.c
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#endif
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extern SPIC_INIT_PARA SpicInitCPUCLK[4];
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//extern SPIC_INIT_PARA SpicInitCPUCLK[4];
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/* Send Flash Instruction with Data Phase */
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HAL_FLASH_TEXT_SECTION
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@ -113,7 +111,7 @@ SpicTxCmdWithDataRtl8195A
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HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
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if (DataPhaseLen > 15) {
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DBG_SPIF_WARN("SpicTxInstRtl8195A: Data Phase Leng too Big(%d)\n",DataPhaseLen);
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DBG_SPIF_WARN("%s: Data Phase Leng too Big(%d)\n", __func__, DataPhaseLen);
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DataPhaseLen = 15;
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}
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@ -1355,15 +1353,16 @@ SpicNVMCalLoad(u8 BitMode, u8 CpuClk)
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SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle = pspci_para->RdDummyCyle;
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SpicInitParaAllClk[BitMode][CpuClk].DelayLine = pspci_para->DelayLine;
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SpicInitParaAllClk[BitMode][CpuClk].Valid = pspci_para->Valid;
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DBG_SPIF_INFO("SpicNVMCalLoad: Calibration Loaded(BitMode %d, CPUClk %d): BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n",
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BitMode, CpuClk,
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DBG_SPIF_INFO("%s: Calibration Loaded(BitMode %d, CPUClk %d): BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n",
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__func__, BitMode, CpuClk,
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SpicInitParaAllClk[BitMode][CpuClk].BaudRate,
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SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle,
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SpicInitParaAllClk[BitMode][CpuClk].DelayLine);
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}
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else {
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DBG_SPIF_WARN("SpicNVMCalLoad: Data in Flash(@ 0x%x = 0x%x 0x%x) is Invalid\r\n",
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(FLASH_SPIC_PARA_BASE+flash_offset), spci_para, spci_para_inv);
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DBG_SPIF_WARN("%s: Data in Flash(@ 0x%x = 0x%x 0x%x) is Invalid\r\n",
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__func__,
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(FLASH_SPIC_PARA_BASE+flash_offset), spci_para, spci_para_inv);
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}
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}
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@ -1408,7 +1407,7 @@ SpicNVMCalStore(u8 BitMode, u8 CpuClk)
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SPIC_INIT_PARA SpicInitPara;
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#if CONFIG_DEBUG_LOG > 4
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DBG_SPIF_INFO("SpicNVMCalStore==> BitMode=%d CpuClk=%d\r\n", BitMode, CpuClk);
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DBG_SPIF_INFO("%s ==> BitMode=%d CpuClk=%d\r\n", __func__, BitMode, CpuClk);
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#endif
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/* each Calibration parameters use 8 bytes, first 4-bytes are the calibration data,
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2nd 4-bytes are the validate data: ~(calibration data) */
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@ -1436,7 +1435,8 @@ SpicNVMCalStore(u8 BitMode, u8 CpuClk)
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SpicWaitWipDoneRefinedRtl8195A(SpicInitPara);
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#if CONFIG_DEBUG_LOG > 4
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DBG_SPIF_INFO("SpicNVMCalStore(BitMode %d, CPUClk %d): Calibration Stored: BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n",
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DBG_SPIF_INFO("%s(BitMode %d, CPUClk %d): Calibration Stored: BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n",
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__func__,
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BitMode, CpuClk,
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SpicInitParaAllClk[BitMode][CpuClk].BaudRate,
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SpicInitParaAllClk[BitMode][CpuClk].RdDummyCyle,
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@ -1444,18 +1444,21 @@ SpicNVMCalStore(u8 BitMode, u8 CpuClk)
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#endif
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// Read back to check
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if (HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset)) != spci_para) {
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DBG_SPIF_ERR("SpicNVMCalStore Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n",
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DBG_SPIF_ERR("%s: Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n",
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__func__,
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flash_offset, spci_para, HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset)));
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}
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if (HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset+4)) != ~spci_para) {
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DBG_SPIF_ERR("SpicNVMCalStore Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n",
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DBG_SPIF_ERR("%s: Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n",
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__func__,
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flash_offset+4, ~spci_para, HAL_READ32(SPI_FLASH_BASE, (FLASH_SPIC_PARA_BASE+flash_offset+4)));
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}
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}
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else {
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// There is a parameter on the flash memory already
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DBG_SPIF_ERR("SpicNVMCalStore: The flash memory(@0x%x = 0x%x) is not able to be write, Erase it first!\r\n",
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DBG_SPIF_ERR("%s: The flash memory(@0x%x = 0x%x) is not able to be write, Erase it first!\r\n",
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__func__,
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(FLASH_SPIC_PARA_BASE+flash_offset), spci_para);
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}
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}
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