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https://github.com/pvvx/RTL00MP3.git
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add and update
This commit is contained in:
pvvx
parent
03ed2886cb
commit
bda4d33012
109 changed files with 73065 additions and 85 deletions
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@ -102,21 +102,20 @@ VOID ShowRamBuildInfo(VOID)
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_WEAK int main(void)
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{
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gpio_t gpio_led;
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#ifndef CONFIG_WITHOUT_MONITOR
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ReRegisterPlatformLogUart();
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#endif
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HalPinCtrlRtl8195A(JTAG, 0, 1);
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// Init LED control pin
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gpio_init(&gpio_led, PC_5);
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gpio_dir(&gpio_led, PIN_OUTPUT); // Direction: Output
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gpio_mode(&gpio_led, PullNone); // No pull
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while(1){
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gpio_write(&gpio_led, !gpio_read(&gpio_led));
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RtlMsleepOS(1000);
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DiagPrintf("\r\nRTL Console ROM: Start - press key 'Up', Help '?'\r\n");
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while(pUartLogCtl[5] != 1);
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pUartLogCtl[3] = 0;
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pUartLogCtl[6] = 1;
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DiagPrintf("\r<RTL8710AF>");
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while(1) {
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while(pUartLogCtl[4] != 1 );
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UartLogCmdExecute(pUartLogCtl);
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DiagPrintf("\r<RTL8710AF>");
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pUartLogCtl[4] = 0;
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}
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return 0;
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}
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#else
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170
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/loader.c
Normal file
170
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/loader.c
Normal file
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@ -0,0 +1,170 @@
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/*
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* loader.c
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*
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* Created on: 17 нояб. 2016 г.
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* Author: PVV
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*/
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#include "rtl8195a.h"
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#include "diag.h"
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#include "hal_spi_flash.h"
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#include "hal_api.h"
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#include "hal_platform.h"
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#include "diag.h"
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#include "hal_diag.h"
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#include "rtl8195a_uart.h"
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#include "rtl8195a/rtl8195a_peri_on.h"
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#include "hal_peri_on.h"
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#include "wifi_conf.h"
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//-------------------------------------------------------------------------
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// Data declarations
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extern u32 * NewVectorTable; // LD: NewVectorTable = 0x10000000;
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extern START_FUNC __image2_entry_func__;
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extern u8 __image2_validate_code__;
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extern u8 __image1_bss_start__, __image1_bss_end__;
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extern u8 __rom_bss_start__, __rom_bss_end__;
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extern u8 __bss_start__, __bss_end__;
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typedef struct __RAM_IMG2_VALID_PATTEN__ {
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char rtkwin[7];
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u8 x[13];
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} _RAM_IMG2_VALID_PATTEN, *_PRAM_IMG2_VALID_PATTEN;
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const uint8_t __attribute__((section(".image1.validate.rodata"))) RAM_IMG1_VALID_PATTEN[8] =
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{ 0x23, 0x79, 0x16, 0x88, 0xff, 0xff, 0xff, 0xff };
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PRAM_FUNCTION_START_TABLE __attribute__((section(".data.pRamStartFun"))) pRamStartFun =
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(PRAM_FUNCTION_START_TABLE) 0x10000BC8;
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RAM_START_FUNCTION __attribute__((section(".start.ram.data.a"))) gRamStartFun =
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{ PreProcessForVendor + 1 };
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RAM_START_FUNCTION __attribute__((section(".start.ram.data.b"))) gRamPatchWAKE =
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{ RtlBootToSram + 1 };
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RAM_START_FUNCTION __attribute__((section(".start.ram.data.c"))) gRamPatchFun0 =
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{ RtlBootToSram + 1 };
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RAM_START_FUNCTION __attribute__((section(".start.ram.data.d"))) gRamPatchFun1 =
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{ RtlBootToSram + 1 };
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RAM_START_FUNCTION __attribute__((section(".start.ram.data.e"))) gRamPatchFun2 =
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{ RtlBootToSram + 1 };
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RAM_START_FUNCTION __attribute__((section(".image2.ram.data"))) gImage2EntryFun0 =
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{ InfraStart + 1 };
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_RAM_IMG2_VALID_PATTEN __attribute__((section(".image2.validate.rodata"))) RAM_IMG2_VALID_PATTEN =
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{ { "RTKWin" }, { 0xff, 0, 1, 1, 0, 0x95, 0x81, 1, 1, 0, 0, 0, 0 } };
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HAL_GPIO_ADAPTER __attribute__((section(".hal.ram.data"))) gBoot_Gpio_Adapter;
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void sub_100037EC(void)
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{
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0, (HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) & 0xFFFFF) | 0xE00000);
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HAL_SYS_CTRL_WRITE32(REG_SYS_REGU_CTRL0, HAL_SYS_CTRL_READ32(REG_SYS_REGU_CTRL0) | 2);
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}
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void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
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u8 efuse0xF8_data;
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// memset((void *)0x10000300, 0 , 0x10000BC8-0x10000300); ???
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HalPinCtrlRtl8195A(JTAG, 0, 1);
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HalDelayUs(1000);
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HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8,
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&efuse0xF8_data, L25EOUTVOLTAGE);
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if(efuse0xF8_data == CHIP_ID_8711AF) { // ??
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | 0x200000) ; 1<<21
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sub_100037EC();
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}
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int flash_enable = HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN;
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}
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void sub_1000441A(void)
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{
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ConfigDebugErr = -1;
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ConfigDebugWarn = 0;
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ConfigDebugInfo = 0;
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}
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//----- InfraStart
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void __attribute__((section(".infra.ram.start"))) InfraStart(void) {
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NewVectorTable[2] = HalNMIHandler_Patch;
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sub_100022F0();
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memset((void *)0x10000300, 0 , 0x10000BC8-0x10000300);
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HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_VENDOR_REG_EN);
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HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_SLPCK_VENDOR_REG_EN);
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HalPinCtrlRtl8195A(JTAG, 0, 1);
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HAL_PERI_ON_WRITE32(REG_GPIO_SHTDN_CTRL, 0x7FF);
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HAL_PERI_ON_WRITE32(REG_CPU_PERIPHERAL_CTRL, HAL_PERI_ON_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_SPI_FLSH_PIN_EN);
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HAL_PERI_ON_WRITE32(REG_CPU_PERIPHERAL_CTRL, HAL_SYHAL_PERI_ON_READ32S_CTRL_READ32(REG_CPU_PERIPHERAL_CTRL) | BIT_LOG_UART_PIN_EN);
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VectorTableInitRtl8195A(0x1FFFFFFC); // 0x1FFFFFFC StackP
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_FLASH_EN) ;
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HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_FLASH_EN);
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HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_SLPCK_FLASH_EN);
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HalPinCtrlRtl8195A(SPI_FLASH, 0, 1);
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sub_1000367C();
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HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL1, HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL1) & 0x8F);
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sub_1000441A();
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HAL_UART_READ32(UART_REV_BUF_OFF);
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & (~BIT_SOC_LOG_UART_EN));
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_LOG_UART_EN);
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HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_LOG_UART_EN);
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LOG_UART_ADAPTER UartAdapter;
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UartAdapter.BaudRate = UART_BAUD_RATE_38400;
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UartAdapter.FIFOControl = 0xC1;
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UartAdapter.IntEnReg = 0x00;
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UartAdapter.Parity = UART_PARITY_DISABLE;
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UartAdapter.Stop = UART_STOP_1BIT;
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UartAdapter.DataLength = UART_DATA_LEN_8BIT;
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HalLogUartInit(UartAdapter); // sub_10004434(38400, 193, 0, v14);
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TIMER_ADAPTER tim_adapter;
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tim_adapter.IrqHandle.IrqFun = &UartLogIrqHandle;
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tim_adapter.IrqHandle.IrqNum = UART_LOG_IRQ;
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tim_adapter.IrqHandle.Data = 0;
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tim_adapter.IrqHandle.Priority = 5;
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VectorIrqRegisterRtl8195A(&tim_adapter.IrqHandle);
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UartAdapter.IntEnReg = 0x05;
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HalLogUartInit(UartAdapter);
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HAL_PERI_ON_WRITE32(REG_PON_ISO_CTRL, 3); // ? USB ?
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HAL_PERI_ON_WRITE32(REG_OSC32K_CTRL, HAL_PERI_ON_READ32(REG_OSC32K_CTRL) | BIT_32K_POW_CKGEN_EN);
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HAL_PERI_ON_WRITE32(REG_SOC_FUNC_EN, HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) | BIT_SOC_GTIMER_EN);
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HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_ACTCK_TIMER_EN);
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HAL_PERI_ON_WRITE32(REG_PESOC_CLK_CTRL, HAL_PERI_ON_READ32(REG_PESOC_CLK_CTRL) | BIT_SOC_SLPCK_TIMER_EN);
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tim_adapter.TimerIrqPriority = 0;
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tim_adapter.TimerLoadValueUs = 0;
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tim_adapter.TimerMode = FREE_RUN_MODE;
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tim_adapter.IrqDis = 1;
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tim_adapter.TimerId = 1;
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HalTimerInitRtl8195a((PTIMER_ADAPTER) &tim_adapter);
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SpicInitRtl8195A(1, 1); // InitBaudRate 1, SpicBitMode 1
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SpicFlashInitRtl8195A(1); // SpicBitMode 1
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DBG_8195A("===== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\n",
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&__image2_validate_code__, __image2_entry_func__);
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HAL_SYS_CTRL_WRITE32(REG_SYS_CLK_CTRL0,
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HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0) | BIT4);
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if (HalCommonInit() != HAL_OK) DBG_8195A("Hal Common Init Failed.\n");
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DBG_8195A("===== Enter Image 2 ====\n");
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ShowRamBuildInfo(); // app_start.c: VOID ShowRamBuildInfo(VOID)
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memset(&__bss_start__, 0, &__bss_end__ - &__bss_start__);
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int clk = (HAL_SYS_CTRL_READ32(REG_SYS_CLK_CTRL0)
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>> BIT_SHIFT_PESOC_OCP_CPU_CK_SEL) & 1;
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if (clk) {
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SpicNVMCalLoadAll();
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SpicReadIDRtl8195A();
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}
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SystemCoreClockUpdate();
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SYSPlatformInit();
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En32KCalibration();
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InitSoCPM();
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SDIO_Device_Off();
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VectorTableInitForOSRtl8195A(&vPortSVCHandler, &xPortPendSVHandler,
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&xPortSysTickHandler);
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if (clk) SpicDisableRtl8195A();
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_AppStart();
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}
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@ -1,6 +1,6 @@
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/*
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startup.o sdk-ameba-rtl8710af-v3.5a_without_NDA_GCC_V1.0.0
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pvvx 2016
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* startup.o sdk-ameba-rtl8710af-v3.5a_without_NDA_GCC_V1.0.0
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* pvvx 2016
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*/
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#include "rtl8195a.h"
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@ -41,7 +41,7 @@ void StartupHalInitPlatformLogUart(void);
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void RtlBootToSram(void);
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int IsForceLoadDefaultImg2(void);
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void StartupHalSpicInit(int InitBaudRate);
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void PreProcessForVendor(u32 def_fuse, u32 Img2Addr, int a3);
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void PreProcessForVendor(void);
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void HalHardFaultHandler_Patch_c(u32 HardDefaultArg);
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void VectorTableOverrideRtl8195A(u32 StackP);
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void SYSPlatformInit(void);
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@ -220,7 +220,7 @@ void __attribute__((section(".hal.ram.text"))) SYSCpuClkConfig(int ChipID, int S
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SpicWaitWipRtl8195A(); // extern u32 SpicWaitWipRtl8195A(VOID);
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flg = 1;
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}
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if (ChipID == 0xFC && (!SysCpuClk)) SysCpuClk = 1;
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if (ChipID == CHIP_ID_8710AF && (!SysCpuClk)) SysCpuClk = 1;
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HalCpuClkConfig(SysCpuClk);
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HalDelayUs(1000);
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StartupHalInitPlatformLogUart();
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@ -283,13 +283,12 @@ void __attribute__((section(".hal.ram.text"))) StartupHalSpicInit(
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}
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//----- PreProcessForVendor
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void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(u32 def_fuse,
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u32 Img2Addr, int a3) {
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void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
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START_FUNC entry_func;
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u32 run_image;
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u32 Image2Addr = Img2Addr;
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u32 Image2Addr;
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u32 v16 = 0, v17;
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u8 efuse0xD3_data = def_fuse >> 24;
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u8 efuse0xD3_data;
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HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xD3,
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&efuse0xD3_data, L25EOUTVOLTAGE);
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if (efuse0xD3_data & 1) v16 = HalPinCtrlRtl8195A(JTAG, 0, 1);
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@ -303,7 +302,7 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(u32 def_fuse,
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} else {
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memcpy(&Image2Addr, (const void *) 0x1006FFFC, 4); // ???
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entry_func = Image2Addr;
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if (chip_id != 0xFB) {
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if (chip_id != CHIP_ID_8711AN) { // 0xFB
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StartupHalSpicInit(1); // BaudRate 1
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x_enable = 1;
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}
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@ -319,7 +318,10 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(u32 def_fuse,
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sdr_enable = 1;
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}
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#else
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SdrPowerOff();
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// SdrPowerOff();
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SDR_PIN_FCTRL(OFF);
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LDO25M_CTRL(OFF);
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HAL_WRITE32(PERI_ON_BASE, REG_SOC_FUNC_EN, HAL_READ32(PERI_ON_BASE, REG_SOC_FUNC_EN) | BIT(21));
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#endif
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ConfigDebugErr = -1;
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ConfigDebugWarn = 0;
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@ -331,7 +333,7 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(u32 def_fuse,
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DBG_8195A("===== Enter Image 1 ====\n");
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if (x_enable) {
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SpicReadIDRtl8195A();
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SpicFlashInitRtl8195A(1); // SpicBitMode 1
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SpicFlashInitRtl8195A(SpicDualBitMode); // SpicBitMode 1
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}
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// if (sdr_enable) SdrControllerInit();
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if (flash_enable) {
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@ -362,10 +364,8 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(u32 def_fuse,
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sign1 = *prdflash++;
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sign2 = *prdflash;
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if (sign2 == 0x31313738) {
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if (sign1 == 0x35393138)
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v16 = OTA_addr;
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else if (sign1 == 0x35393130)
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v17 = OTA_addr;
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if (sign1 == 0x35393138) v16 = OTA_addr;
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else if (sign1 == 0x35393130) v17 = OTA_addr;
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}
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LABEL_41: if (IsForceLoadDefaultImg2()) {
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if (v17 != -1) run_image = v17;
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@ -373,8 +373,7 @@ LABEL_41: if (IsForceLoadDefaultImg2()) {
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run_image = v16;
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if (run_image == -1) {
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DiagPrintf("Fatal: no fw\n");
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while (1)
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RtlConsolRom(1000);
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while (1) RtlConsolRom(1000);
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}
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}
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} else {
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@ -383,8 +382,7 @@ LABEL_41: if (IsForceLoadDefaultImg2()) {
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run_image = v17;
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if (run_image == -1) {
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DiagPrintf("Fatal: no fw\n");
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while (1)
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RtlConsolRom(1000);
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while (1) RtlConsolRom(1000);
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}
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}
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}
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@ -0,0 +1,149 @@
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#ifndef _GENERIC_ERRNO_H
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#define _GENERIC_ERRNO_H
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#define EPERM 1 /* Operation not permitted */
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#define ENOENT 2 /* No such file or directory */
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#define ESRCH 3 /* No such process */
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#define EINTR 4 /* Interrupted system call */
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#define EIO 5 /* I/O error */
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#define ENXIO 6 /* No such device or address */
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#define E2BIG 7 /* Argument list too long */
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#define ENOEXEC 8 /* Exec format error */
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#define EBADF 9 /* Bad file number */
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#define ECHILD 10 /* No child processes */
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#define EAGAIN 11 /* Try again */
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#define ENOMEM 12 /* Out of memory */
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#define EACCES 13 /* Permission denied */
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#define EFAULT 14 /* Bad address */
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#define ENOTBLK 15 /* Block device required */
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#define EBUSY 16 /* Device or resource busy */
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#define EEXIST 17 /* File exists */
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#define EXDEV 18 /* Cross-device link */
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#define ENODEV 19 /* No such device */
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#define ENOTDIR 20 /* Not a directory */
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#define EISDIR 21 /* Is a directory */
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#define EINVAL 22 /* Invalid argument */
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#define ENFILE 23 /* File table overflow */
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#define EMFILE 24 /* Too many open files */
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#define ENOTTY 25 /* Not a typewriter */
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#define ETXTBSY 26 /* Text file busy */
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#define EFBIG 27 /* File too large */
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#define ENOSPC 28 /* No space left on device */
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#define ESPIPE 29 /* Illegal seek */
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#define EROFS 30 /* Read-only file system */
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#define EMLINK 31 /* Too many links */
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#define EPIPE 32 /* Broken pipe */
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#define EDOM 33 /* Math argument out of domain of func */
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||||
#define ERANGE 34 /* Math result not representable */
|
||||
|
||||
#define EDEADLK 35 /* Resource deadlock would occur */
|
||||
#define ENAMETOOLONG 36 /* File name too long */
|
||||
#define ENOLCK 37 /* No record locks available */
|
||||
#define ENOSYS 38 /* Function not implemented */
|
||||
#define ENOTEMPTY 39 /* Directory not empty */
|
||||
#define ELOOP 40 /* Too many symbolic links encountered */
|
||||
#define EWOULDBLOCK EAGAIN /* Operation would block */
|
||||
#define ENOMSG 42 /* No message of desired type */
|
||||
#define EIDRM 43 /* Identifier removed */
|
||||
#define ECHRNG 44 /* Channel number out of range */
|
||||
#define EL2NSYNC 45 /* Level 2 not synchronized */
|
||||
#define EL3HLT 46 /* Level 3 halted */
|
||||
#define EL3RST 47 /* Level 3 reset */
|
||||
#define ELNRNG 48 /* Link number out of range */
|
||||
#define EUNATCH 49 /* Protocol driver not attached */
|
||||
#define ENOCSI 50 /* No CSI structure available */
|
||||
#define EL2HLT 51 /* Level 2 halted */
|
||||
#define EBADE 52 /* Invalid exchange */
|
||||
#define EBADR 53 /* Invalid request descriptor */
|
||||
#define EXFULL 54 /* Exchange full */
|
||||
#define ENOANO 55 /* No anode */
|
||||
#define EBADRQC 56 /* Invalid request code */
|
||||
#define EBADSLT 57 /* Invalid slot */
|
||||
|
||||
#define EDEADLOCK EDEADLK
|
||||
|
||||
#define EBFONT 59 /* Bad font file format */
|
||||
#define ENOSTR 60 /* Device not a stream */
|
||||
#define ENODATA 61 /* No data available */
|
||||
#define ETIME 62 /* Timer expired */
|
||||
#define ENOSR 63 /* Out of streams resources */
|
||||
#define ENONET 64 /* Machine is not on the network */
|
||||
#define ENOPKG 65 /* Package not installed */
|
||||
#define EREMOTE 66 /* Object is remote */
|
||||
#define ENOLINK 67 /* Link has been severed */
|
||||
#define EADV 68 /* Advertise error */
|
||||
#define ESRMNT 69 /* Srmount error */
|
||||
#define ECOMM 70 /* Communication error on send */
|
||||
#define EPROTO 71 /* Protocol error */
|
||||
#define EMULTIHOP 72 /* Multihop attempted */
|
||||
#define EDOTDOT 73 /* RFS specific error */
|
||||
#define EBADMSG 74 /* Not a data message */
|
||||
#define EOVERFLOW 75 /* Value too large for defined data type */
|
||||
#define ENOTUNIQ 76 /* Name not unique on network */
|
||||
#define EBADFD 77 /* File descriptor in bad state */
|
||||
#define EREMCHG 78 /* Remote address changed */
|
||||
#define ELIBACC 79 /* Can not access a needed shared library */
|
||||
#define ELIBBAD 80 /* Accessing a corrupted shared library */
|
||||
#define ELIBSCN 81 /* .lib section in a.out corrupted */
|
||||
#define ELIBMAX 82 /* Attempting to link in too many shared libraries */
|
||||
#define ELIBEXEC 83 /* Cannot exec a shared library directly */
|
||||
#define EILSEQ 84 /* Illegal byte sequence */
|
||||
#define ERESTART 85 /* Interrupted system call should be restarted */
|
||||
#define ESTRPIPE 86 /* Streams pipe error */
|
||||
#define EUSERS 87 /* Too many users */
|
||||
#define ENOTSOCK 88 /* Socket operation on non-socket */
|
||||
#define EDESTADDRREQ 89 /* Destination address required */
|
||||
#define EMSGSIZE 90 /* Message too long */
|
||||
#define EPROTOTYPE 91 /* Protocol wrong type for socket */
|
||||
#define ENOPROTOOPT 92 /* Protocol not available */
|
||||
#define EPROTONOSUPPORT 93 /* Protocol not supported */
|
||||
#define ESOCKTNOSUPPORT 94 /* Socket type not supported */
|
||||
#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
|
||||
#define EPFNOSUPPORT 96 /* Protocol family not supported */
|
||||
#define EAFNOSUPPORT 97 /* Address family not supported by protocol */
|
||||
#define EADDRINUSE 98 /* Address already in use */
|
||||
#define EADDRNOTAVAIL 99 /* Cannot assign requested address */
|
||||
#define ENETDOWN 100 /* Network is down */
|
||||
#define ENETUNREACH 101 /* Network is unreachable */
|
||||
#define ENETRESET 102 /* Network dropped connection because of reset */
|
||||
#define ECONNABORTED 103 /* Software caused connection abort */
|
||||
#define ECONNRESET 104 /* Connection reset by peer */
|
||||
#define ENOBUFS 105 /* No buffer space available */
|
||||
#define EISCONN 106 /* Transport endpoint is already connected */
|
||||
#define ENOTCONN 107 /* Transport endpoint is not connected */
|
||||
#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */
|
||||
#define ETOOMANYREFS 109 /* Too many references: cannot splice */
|
||||
#define ETIMEDOUT 110 /* Connection timed out */
|
||||
#define ECONNREFUSED 111 /* Connection refused */
|
||||
#define EHOSTDOWN 112 /* Host is down */
|
||||
#define EHOSTUNREACH 113 /* No route to host */
|
||||
#define EALREADY 114 /* Operation already in progress */
|
||||
#define EINPROGRESS 115 /* Operation now in progress */
|
||||
#define ESTALE 116 /* Stale NFS file handle */
|
||||
#define EUCLEAN 117 /* Structure needs cleaning */
|
||||
#define ENOTNAM 118 /* Not a XENIX named type file */
|
||||
#define ENAVAIL 119 /* No XENIX semaphores available */
|
||||
#define EISNAM 120 /* Is a named type file */
|
||||
#define EREMOTEIO 121 /* Remote I/O error */
|
||||
#define EDQUOT 122 /* Quota exceeded */
|
||||
|
||||
#define ENOMEDIUM 123 /* No medium found */
|
||||
#define EMEDIUMTYPE 124 /* Wrong medium type */
|
||||
#define ECANCELED 125 /* Operation Canceled */
|
||||
#define ENOKEY 126 /* Required key not available */
|
||||
#define EKEYEXPIRED 127 /* Key has expired */
|
||||
#define EKEYREVOKED 128 /* Key has been revoked */
|
||||
#define EKEYREJECTED 129 /* Key was rejected by service */
|
||||
|
||||
/* for robust mutexes */
|
||||
#define EOWNERDEAD 130 /* Owner died */
|
||||
#define ENOTRECOVERABLE 131 /* State not recoverable */
|
||||
|
||||
#define ERFKILL 132 /* Operation not possible due to RF-kill */
|
||||
|
||||
#define EHWPOISON 133 /* Memory page has hardware error */
|
||||
|
||||
|
||||
#define ENOTSUPP 524 /* Operation is not supported */
|
||||
|
||||
#endif
|
||||
|
|
@ -933,11 +933,11 @@ VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk)
|
|||
uint32_t spci_para; // [sp+Ch] [bp-2Ch]@4
|
||||
|
||||
v2 = CpuClk + 6 * BitMode;
|
||||
v3 = 40006120;
|
||||
v4 = 40006014;
|
||||
v3 = 0x40006120;
|
||||
v4 = 0x40006014;
|
||||
v5 = BitMode;
|
||||
v6 = CpuClk;
|
||||
if (40006014 == 1) {
|
||||
if (0x40006014 == 1) {
|
||||
BitMode = HalGetCpuClk(BitMode, CpuClk);
|
||||
if (BitMode == 166666666) {
|
||||
40006120 |= 0x202u;
|
||||
|
|
@ -1012,39 +1012,38 @@ VOID HAL_FLASH_TEXT_SECTION SpicNVMCalStore(u8 BitMode, u8 CpuClk)
|
|||
v4);
|
||||
v5 = v4 + 6 * v3;
|
||||
v6 = v5;
|
||||
if (*(u32 *) (8 * v5 - 1744793472) == -1) {
|
||||
if (*(u32 *) (8 * v5 + 0x98009080) == -1) {
|
||||
LOBYTE (spci_para) = SpicInitParaAllClk[0][v5].BaudRate;
|
||||
BYTE1 (spci_para) = SpicInitParaAllClk[0][v6].RdDummyCyle;
|
||||
BYTE2 (spci_para) = SpicInitParaAllClk[0][v6].DelayLine;
|
||||
BYTE3 (spci_para) = SpicInitParaAllClk[0][v6]._anon_0.Rsvd;
|
||||
*(u32 *) (8 * v5 - 1744793472) = spci_para;
|
||||
*(u32 *) (8 * v5 + 0x98009080) = spci_para;
|
||||
if (SpicInitParaAllClk[0][v6].flashtype == 4)
|
||||
SpicWaitOperationDoneRtl8195A(SpicInitPara, spci_para);
|
||||
else
|
||||
SpicWaitWipDoneRefinedRtl8195A(SpicInitPara, spci_para);
|
||||
*(u32 *) (8 * v5 - 1744793468) = ~spci_para;
|
||||
*(u32 *) (8 * v5 + 0x98009084) = ~spci_para;
|
||||
v7 = SpicInitParaAllClk[0][v4 + 6 * v3].flashtype;
|
||||
if (v7 == 4)
|
||||
SpicWaitOperationDoneRtl8195A(SpicInitPara, 4);
|
||||
else
|
||||
SpicWaitWipDoneRefinedRtl8195A(SpicInitPara, v7);
|
||||
DBG_SPIF_INFO("SpicNVMCalStore(BitMode %d, CPUClk %d): Calibration Stored: BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n",
|
||||
DBG_SPIF_INFO("SpicNVMCalStore(BitMode %d, CPUClk %d): Calibration Stored: BaudRate=0x%x RdDummyCyle=0x%x DelayLine=0x%x\r\n",
|
||||
v3, v4, SpicInitParaAllClk[0][v4 + 6 * v3].BaudRate,
|
||||
SpicInitParaAllClk[0][v4 + 6 * v3].RdDummyCyle,
|
||||
SpicInitParaAllClk[0][v4 + 6 * v3].DelayLine);
|
||||
if (*(u32 *) (8 * v5 - 1744793472) != spci_para) {
|
||||
|
||||
v8 = *(u32 *) (8 * v5 - 1744793472);
|
||||
if (*(u32 *) (8 * v5 + 0x98009080) != spci_para) {
|
||||
v8 = *(u32 *) (8 * v5 + 0x98009080);
|
||||
DBG_SPIF_ERR("SpicNVMCalStore Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n",
|
||||
8 * v5);
|
||||
}
|
||||
if (*(u32 *) (8 * v5 - 1744793468) != ~spci_para) {
|
||||
v9 = *(u32 *) (8 * v5 - 1744793468);
|
||||
if (*(u32 *) (8 * v5 + 0x98009084) != ~spci_para) {
|
||||
v9 = *(u32 *) (8 * v5 + 0x98009084);
|
||||
DBG_SPIF_ERR("SpicNVMCalStore Err(Offset=0x%x), Wr=0x%x Rd=0x%x \r\n",
|
||||
v6 * 8 + 4);
|
||||
}
|
||||
} else DBG_SPIF_ERR("SpicNVMCalStore: The flash memory(@0x%x = 0x%x) is not able to be write, Erase it first!!\r\n",
|
||||
v6 * 8 + 36992);
|
||||
v6 * 8 + 0x9080);
|
||||
}
|
||||
|
||||
//----- SpicCalibrationRtl8195A
|
||||
|
|
@ -1226,7 +1225,7 @@ extern BOOLEAN HAL_FLASH_TEXT_SECTION SpicFlashInitRtl8195A(u8 SpicBitMode)
|
|||
DefRdDummyCycle = 8;
|
||||
break;
|
||||
default:
|
||||
DBG_MISC_ERR("No Support SPI Mode!!!!!!!!\n");
|
||||
DBG_MISC_ERR("No Support SPI Mode!\n");
|
||||
SpicConfigAutoModeRtl8195A(SpicOneBitMode);
|
||||
DefRdDummyCycle = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,9 +9,9 @@ MEMORY
|
|||
{
|
||||
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 65536
|
||||
ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560
|
||||
//RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 16128
|
||||
RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 16128
|
||||
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 434176
|
||||
RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 7936
|
||||
// RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 7936
|
||||
//BD_RAM (rwx) : ORIGIN = 0x10004000, LENGTH = 442368
|
||||
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
|
||||
}
|
||||
|
|
@ -165,14 +165,14 @@ SECTIONS
|
|||
__buffer_data_end__ = .;
|
||||
|
||||
} > BD_RAM
|
||||
|
||||
/*
|
||||
.bf_data2 :
|
||||
{
|
||||
__buffer_data_start2__ = .;
|
||||
__buffer_data_end2__ = .;
|
||||
|
||||
} > RECY_RAM
|
||||
|
||||
*/
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
|
|
|
|||
|
|
@ -8,10 +8,10 @@ INCLUDE "export-rom_v03.txt"
|
|||
MEMORY
|
||||
{
|
||||
TCM (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 65536
|
||||
ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560
|
||||
//RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 16128
|
||||
ROM_USED_RAM (rwx) : ORIGIN = 0x10000bc8, LENGTH = 21560 /* end 0x10006000 */
|
||||
RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 16128 /* end 0x10006000 */
|
||||
BD_RAM (rwx) : ORIGIN = 0x10006000, LENGTH = 434176
|
||||
RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 7936
|
||||
//RECY_RAM (rwx) : ORIGIN = 0x10002100, LENGTH = 7936 /* end 0x10004000 */
|
||||
//BD_RAM (rwx) : ORIGIN = 0x10004000, LENGTH = 442368
|
||||
SDRAM_RAM (rwx) : ORIGIN = 0x30000000, LENGTH = 2M
|
||||
}
|
||||
|
|
@ -186,14 +186,14 @@ SECTIONS
|
|||
__buffer_data_end__ = .;
|
||||
|
||||
} > BD_RAM
|
||||
|
||||
/*
|
||||
.bf_data2 :
|
||||
{
|
||||
__buffer_data_start2__ = .;
|
||||
__buffer_data_end2__ = .;
|
||||
|
||||
} > RECY_RAM
|
||||
|
||||
*/
|
||||
.sdr_text :
|
||||
{
|
||||
__sdram_data_start__ = .;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* rom_libc_string.h
|
||||
*
|
||||
* Definitions for standard library - libc functions.
|
||||
*/
|
||||
#ifndef _ROM_LIBC_STRING_H_
|
||||
#define _ROM_LIBC_STRING_H_
|
||||
|
||||
#include <basic_types.h>
|
||||
|
||||
#define __rtl_memchr __rtl_memchr_v1_00
|
||||
#define __rtl_memcmp __rtl_memcmp_v1_00
|
||||
#define __rtl_memcpy __rtl_memcpy_v1_00
|
||||
#define __rtl_memmove __rtl_memmove_v1_00
|
||||
#define __rtl_memset __rtl_memset_v1_00
|
||||
#define __rtl_strcat __rtl_strcat_v1_00
|
||||
#define __rtl_strchr __rtl_strchr_v1_00
|
||||
#define __rtl_strcmp __rtl_strcmp_v1_00
|
||||
#define __rtl_strcpy __rtl_strcpy_v1_00
|
||||
#define __rtl_strlen __rtl_strlen_v1_00
|
||||
#define __rtl_strncat __rtl_strncat_v1_00
|
||||
#define __rtl_strncmp __rtl_strncmp_v1_00
|
||||
#define __rtl_strncpy __rtl_strncpy_v1_00
|
||||
#define __rtl_strstr __rtl_strstr_v1_00
|
||||
#define __rtl_strsep __rtl_strsep_v1_00
|
||||
#define __rtl_strtok __rtl_strtok_v1_00
|
||||
|
||||
#define __rtl_critical_factorization __rtl_critical_factorization_v1_00
|
||||
#define __rtl_two_way_short_needle __rtl_two_way_short_needle_v1_00
|
||||
#define __rtl_two_way_long_needle __rtl_two_way_long_needle_v1_00
|
||||
|
||||
extern _LONG_CALL_ void * __rtl_memchr_v1_00(const void * src_void , int c , size_t length);
|
||||
extern _LONG_CALL_ int __rtl_memcmp_v1_00(const void * m1 , const void * m2 , size_t n);
|
||||
extern _LONG_CALL_ void * __rtl_memcpy_v1_00(void * __restrict dst0 , const void * __restrict src0 , size_t len0);
|
||||
extern _LONG_CALL_ void * __rtl_memmove_v1_00( void * dst_void , const void * src_void , size_t length);
|
||||
extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
|
||||
extern _LONG_CALL_ char * __rtl_strcat_v1_00(char *__restrict s1 , const char *__restrict s2);
|
||||
extern _LONG_CALL_ char * __rtl_strchr_v1_00(const char *s1 , int i);
|
||||
extern _LONG_CALL_ int __rtl_strcmp_v1_00(const char *s1 , const char *s2);
|
||||
extern _LONG_CALL_ char* __rtl_strcpy_v1_00(char *dst0 , const char *src0);
|
||||
extern _LONG_CALL_ size_t __rtl_strlen_v1_00(const char *str);
|
||||
extern _LONG_CALL_ char * __rtl_strncat_v1_00(char *__restrict s1 , const char *__restrict s2 , size_t n);
|
||||
extern _LONG_CALL_ int __rtl_strncmp_v1_00(const char *s1 , const char *s2 , size_t n);
|
||||
extern _LONG_CALL_ char * __rtl_strncpy_v1_00(char *__restrict dst0 , const char *__restrict src0 , size_t count);
|
||||
extern _LONG_CALL_ char * __rtl_strstr_v1_00(const char *searchee , const char *lookfor);
|
||||
extern _LONG_CALL_ char * __rtl_strsep_v1_00(register char **source_ptr , register const char *delim);
|
||||
extern _LONG_CALL_ char * __rtl_strtok_v1_00(register char *__restrict s , register const char *__restrict delim);
|
||||
|
||||
#endif /* _ROM_LIBC_STRING_H_ */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
#ifndef ROM_LIBGLOSS_RETARGET_H
|
||||
#define ROM_LIBGLOSS_RETARGET_H
|
||||
|
||||
#include <sys/stat.h>
|
||||
#include <basic_types.h>
|
||||
|
||||
#define __rtl_close __rtl_close_v1_00
|
||||
#define __rtl_fstat __rtl_fstat_v1_00
|
||||
#define __rtl_isatty __rtl_isatty_v1_00
|
||||
#define __rtl_lseek __rtl_lseek_v1_00
|
||||
#define __rtl_open __rtl_open_v1_00
|
||||
#define __rtl_read __rtl_read_v1_00
|
||||
#define __rtl_write __rtl_write_v1_00
|
||||
#define __rtl_sbrk __rtl_sbrk_v1_00
|
||||
|
||||
extern _LONG_CALL_ int __rtl_close_v1_00(int fildes);
|
||||
extern _LONG_CALL_ int __rtl_fstat_v1_00(int fildes , struct stat *st);
|
||||
extern _LONG_CALL_ int __rtl_isatty_v1_00(int file);
|
||||
extern _LONG_CALL_ int __rtl_lseek_v1_00(int file , int ptr , int dir);
|
||||
extern _LONG_CALL_ int __rtl_open_v1_00(char *file , int flags , int mode);
|
||||
extern _LONG_CALL_ int __rtl_read_v1_00(int file , char *ptr , int len);
|
||||
extern _LONG_CALL_ int __rtl_write_v1_00(int file , const char *ptr , int len);
|
||||
extern _LONG_CALL_ void* __rtl_sbrk_v1_00(int incr);
|
||||
|
||||
|
||||
struct _rom_libgloss_ram_map {
|
||||
int (*libgloss_close)(int fildes);
|
||||
int (*libgloss_fstat)(int fildes , struct stat *st);
|
||||
int (*libgloss_isatty)(int file);
|
||||
int (*libgloss_lseek)(int file , int ptr , int dir);
|
||||
int (*libgloss_open)(char *file , int flags , int mode);
|
||||
int (*libgloss_read)(int file , char *ptr , int len);
|
||||
int (*libgloss_write)(int file , const char *ptr , int len);
|
||||
void* (*libgloss_sbrk)(int incr);
|
||||
};
|
||||
|
||||
#endif /* ROM_LIBGLOSS_RETARGET_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue