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pvvx 2017-02-19 22:35:23 +03:00
parent 629e5fdc28
commit bd42ffa334
212 changed files with 35447 additions and 223 deletions
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28
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
View file

@ -7,13 +7,21 @@
* possession or use of this module requires written permission of RealTek.
*/
#include "rtl8195a.h"
#include "platform_opts.h"
#include "hal_sdr_controller.h"
#include "rtl8195a_sdr.h"
#include "flash_api.h"
#ifdef CONFIG_SDR_EN
#ifndef USE_SRC_ONLY_BOOT
#define USE_SRC_ONLY_BOOT 0
#endif
#if !USE_SRC_ONLY_BOOT
#define SDRAM_INIT_USE_TCM_HEAP
#define SDRAM_INIT_USE_FLASH_API
#endif
#if 0
@ -122,9 +130,11 @@ u32 SdrCalibration(VOID);
//#define Sdr_Rand2 Rand
#ifndef SDRAM_INIT_USE_TCM_HEAP
#if !USE_SRC_ONLY_BOOT
//3 Note: stack overfloat if the arrary is declared in the task
HAL_CUT_B_RAM_DATA_SECTION
u32 AvaWds[2][REC_NUM];
#endif
#else
typedef struct {
u32 m[2][REC_NUM];
@ -138,6 +148,12 @@ unsigned int rand_x = 123456789;
*/
#ifdef CONFIG_SDR_EN
//#pragma arm section code = ".hal.sdrc.text"
#pragma arm section rodata = ".rodata.hal.sdrc"
//, rwdata = ".hal.sdrc.data"
//, zidata = ".hal.sdrc.bss"
//#pragma arm section bss = ".hal.sdrc.bss"
#ifdef CONFIG_SDR_VERIFY
enum{
LLT,
@ -744,8 +760,10 @@ SdrCalibration(
u32 valid;
union { u8 b[4]; u32 l;} value;
////
#ifdef SDRAM_INIT_USE_FLASH_API
flash_turnon();
if(fspic_isinit == 0) flash_init(&flashobj);
#endif
////
u32 CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4);
@ -776,11 +794,16 @@ SdrCalibration(
}
#endif
#if !USE_SRC_ONLY_BOOT
#ifdef SDRAM_INIT_USE_TCM_HEAP
pAvaWds AvaWds = (pAvaWds) tcm_heap_calloc(sizeof(u32)*REC_NUM*2);
#else
_memset((u8*)AvaWds, 0, sizeof(u32)*REC_NUM*2);
#endif
#else
u32 AvaWds[2][REC_NUM];
_memset((u8*)AvaWds, 0, sizeof(u32)*REC_NUM*2);
#endif
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
@ -981,7 +1004,7 @@ SdrCalibration(
return Result;
} // SdrCalibration
HAL_RAM_DATA_SECTION
/*
HAL_SDRC_TEXT_SECTION
@ -1062,7 +1085,7 @@ u8 IsSdrPowerOn(
#else // ifndef CONFIG_SDR_EN
VOID SdrPowerOff(
HAL_SDRC_TEXT_SECTION VOID SdrPowerOff(
VOID
)
{
@ -1072,7 +1095,6 @@ VOID SdrPowerOff(
}
HAL_SDRC_TEXT_SECTION VOID SdrCtrlInit(VOID)
{
DBG_SDR_ERR("No SDRAM!\n");

13
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c
View file

@ -12,8 +12,9 @@
#include "rtl8195a_spi_flash.h"
#pragma arm section code = ".hal.flash.text", rodata = ".hal.flash.rodata", rwdata = ".hal.flash.data", zidata = ".hal.flash.bss"
#define SPI_CTRL_BASE 0x1FFEF000
//#define SPI_CTRL_BASE 0x1FFEF000
#define SPI_DLY_CTRL_ADDR 0x40000300 // [7:0]
#define MIN_BAUDRATE 0x01
#define MAX_BAUDRATE 0x04
@ -633,7 +634,6 @@ SpicReadIDRtl8195A(
}
/* Disable SPI_FLASH User Mode */
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
}
HAL_FLASH_TEXT_SECTION
@ -645,7 +645,7 @@ SpicCalibrationRtl8195A
)
{
u32 rd_data, /*id_no,*/ baudr, autolen, dly_line;
u32 rd_data, baudr, autolen, dly_line;
u32 total_ava_wds=0;
u32 tmp_str_pt, tmp_end_pt, pass, last_pass;
struct ava_window max_wd;
@ -841,9 +841,7 @@ SpicConfigAutoModeRtl8195A
BIT_RD_DUAL_IO |
BIT_RD_DUAL_I))));//Disable all the four and two bit commands.
}
if (SpicDualBitMode == SpicBitMode) {
else if (SpicDualBitMode == SpicBitMode) {
#if FLASH_RD_2IO_EN
HAL_SPI_WRITE32(REG_SPIC_READ_DUAL_ADDR_DATA, FLASH_CMD_2READ);
#endif
@ -856,8 +854,7 @@ SpicConfigAutoModeRtl8195A
(HAL_SPI_READ32(REG_SPIC_VALID_CMD)|(FLASH_VLD_DUAL_CMDS)));
}
if (SpicQuadBitMode == SpicBitMode) {
else if (SpicQuadBitMode == SpicBitMode) {
#if FLASH_WR_4IO_EN
HAL_SPI_WRITE32(REG_SPIC_WRITE_QUAD_ADDR_DATA, FLASH_CMD_4PP);
#endif