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pvvx 2017-02-19 22:35:23 +03:00
parent 629e5fdc28
commit bd42ffa334
212 changed files with 35447 additions and 223 deletions
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88
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_spi_flash.h
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@ -911,30 +911,30 @@
#define BIT_CTRL_FLUSH_FIFO(x) (((x) & BIT_MASK_FLUSH_FIFO) << BIT_SHIFT_FLUSH_FIFO)
//=================== Register Address Definition ============================//
#define REG_SPIC_CTRLR0 0x0000//O
#define REG_SPIC_CTRLR1 0x0004//O
#define REG_SPIC_SSIENR 0x0008//O
#define REG_SPIC_MWCR 0x000C
#define REG_SPIC_SER 0x0010//O
#define REG_SPIC_BAUDR 0x0014//O
#define REG_SPIC_TXFTLR 0x0018
#define REG_SPIC_RXFTLR 0x001C//O
#define REG_SPIC_TXFLR 0x0020//O
#define REG_SPIC_RXFLR 0x0024
#define REG_SPIC_SR 0x0028
#define REG_SPIC_IMR 0x002C//O
#define REG_SPIC_ISR 0x0030
#define REG_SPIC_RISR 0x0034
#define REG_SPIC_TXOICR 0x0038
#define REG_SPIC_RXOICR 0x003C
#define REG_SPC_RXUICR 0x0040
#define REG_SPIC_MSTICR 0x0044
#define REG_SPIC_ICR 0x0048
#define REG_SPIC_DMACR 0x004C
#define REG_SPIC_DMATDLR0 0x0050
#define REG_SPIC_DMATDLR1 0x0054
#define REG_SPIC_IDR 0x0058
#define REG_SPIC_VERSION 0x005C
#define REG_SPIC_CTRLR0 0x0000 //O 0x1040300
#define REG_SPIC_CTRLR1 0x0004 //O 0x10
#define REG_SPIC_SSIENR 0x0008 //O 0
#define REG_SPIC_MWCR 0x000C // 0
#define REG_SPIC_SER 0x0010 //O 1
#define REG_SPIC_BAUDR 0x0014 //O 1
#define REG_SPIC_TXFTLR 0x0018 // 0
#define REG_SPIC_RXFTLR 0x001C //O 0x1F
#define REG_SPIC_TXFLR 0x0020 //O 0
#define REG_SPIC_RXFLR 0x0024 // 0
#define REG_SPIC_SR 0x0028 // 6
#define REG_SPIC_IMR 0x002C //O 0x1FF
#define REG_SPIC_ISR 0x0030 // 4
#define REG_SPIC_RISR 0x0034 // 4
#define REG_SPIC_TXOICR 0x0038 // 0
#define REG_SPIC_RXOICR 0x003C // 0
#define REG_SPC_RXUICR 0x0040 // 0
#define REG_SPIC_MSTICR 0x0044 // 0
#define REG_SPIC_ICR 0x0048 // 0
#define REG_SPIC_DMACR 0x004C // 0
#define REG_SPIC_DMATDLR0 0x0050 // 0
#define REG_SPIC_DMATDLR1 0x0054 // 0
#define REG_SPIC_IDR 0x0058 // 0x10001
#define REG_SPIC_VERSION 0x005C // 0x40470603
#define REG_SPIC_DR0 0x0060
#define REG_SPIC_DR1 0x0064
#define REG_SPIC_DR2 0x0068
@ -966,26 +966,26 @@
#define REG_SPIC_DR28 0x00D0
#define REG_SPIC_DR29 0x00D4
#define REG_SPIC_DR30 0x00D8
#define REG_SPIC_DR31 0x00DC
#define REG_SPIC_READ_FAST_SINGLE 0x00E0//O
#define REG_SPIC_READ_DUAL_DATA 0x00E4//O
#define REG_SPIC_READ_DUAL_ADDR_DATA 0x00E8//O
#define REG_SPIC_READ_QUAD_DATA 0x00EC//O
#define REG_SPIC_READ_QUAD_ADDR_DATA 0x00F0//O
#define REG_SPIC_WRITE_SIGNLE 0x00F4//O
#define REG_SPIC_WRITE_DUAL_DATA 0x00F8//O
#define REG_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC//O
#define REG_SPIC_WRITE_QUAD_DATA 0x0100//O
#define REG_SPIC_WRITE_QUAD_ADDR_DATA 0x0104//O
#define REG_SPIC_WRITE_ENABLE 0x0108//O
#define REG_SPIC_READ_STATUS 0x010C//O
#define REG_SPIC_CTRLR2 0x0110//O
#define REG_SPIC_FBAUDR 0x0114//O
#define REG_SPIC_ADDR_LENGTH 0x0118//O
#define REG_SPIC_AUTO_LENGTH 0x011C//O
#define REG_SPIC_VALID_CMD 0x0120//O
#define REG_SPIC_FLASE_SIZE 0x0124//O
#define REG_SPIC_FLUSH_FIFO 0x0128//O
#define REG_SPIC_DR31 0x00DC // MXIC (DeviceID: FC, Flash Size: 1048576 bytes, FlashID: C22014/1, SpicMode: DIO)
#define REG_SPIC_READ_FAST_SINGLE 0x00E0 //O 0x0B
#define REG_SPIC_READ_DUAL_DATA 0x00E4 //O 0x3B
#define REG_SPIC_READ_DUAL_ADDR_DATA 0x00E8 //O 0x3B
#define REG_SPIC_READ_QUAD_DATA 0x00EC //O 0x6B
#define REG_SPIC_READ_QUAD_ADDR_DATA 0x00F0 //O 0xEB
#define REG_SPIC_WRITE_SIGNLE 0x00F4 //O 0x02
#define REG_SPIC_WRITE_DUAL_DATA 0x00F8 //O 0xA2
#define REG_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC//O 0xA2
#define REG_SPIC_WRITE_QUAD_DATA 0x0100 //O 0x32
#define REG_SPIC_WRITE_QUAD_ADDR_DATA 0x0104//O 0x38
#define REG_SPIC_WRITE_ENABLE 0x0108 //O 0x06
#define REG_SPIC_READ_STATUS 0x010C //O 0x05
#define REG_SPIC_CTRLR2 0x0110 //O 0x51
#define REG_SPIC_FBAUDR 0x0114 //O 0x1
#define REG_SPIC_ADDR_LENGTH 0x0118 //O 0x3
#define REG_SPIC_AUTO_LENGTH 0x011C //O 0x20030011/0x20030021
#define REG_SPIC_VALID_CMD 0x0120 //O 0x202
#define REG_SPIC_FLASE_SIZE 0x0124 //O 0x0E
#define REG_SPIC_FLUSH_FIFO 0x0128 //O 0
VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); // spi-flash controller initialization
VOID SpicRxCmdRtl8195A(u8 cmd); // recieve command

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RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_sdio_host.zip Normal file
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