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https://github.com/pvvx/RTL00MP3.git
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update
This commit is contained in:
pvvx
parent
629e5fdc28
commit
bd42ffa334
212 changed files with 35447 additions and 223 deletions
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@ -244,7 +244,7 @@ HAL_GPIO_IP_DeInit(
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//extern u16 GPIOState[_PORT_MAX-1]; // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию.
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extern u16 GPIOState[_PORT_MAX]; // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию.
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#endif // end of "#define _HAL_GPIO_H_"
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@ -16,12 +16,6 @@
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#define SYSTEM_CLK PLATFORM_CLOCK
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#define SDR_SDRAM_BASE 0x30000000
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#define SYSTEM_CTRL_BASE 0x40000000
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#define PERI_ON_BASE 0x40000000
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#define VENDOR_REG_BASE 0x40002800
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#define SPI_FLASH_BASE 0x98000000
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#define SDR_CTRL_BASE 0x40005000
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#define PERIPHERAL_IRQ_STATUS 0x04
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#define PERIPHERAL_IRQ_MODE 0x08
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@ -34,13 +28,21 @@
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#define TIMER_CLK 32*1000
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#define SDR_SDRAM_BASE 0x30000000
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#define SYSTEM_CTRL_BASE 0x40000000
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#define PERI_ON_BASE 0x40000000
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#define SPI_FLASH_BASE 0x98000000
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//3 Peripheral IP Base Address
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#define GPIO_REG_BASE 0x40001000
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#define TIMER_REG_BASE 0x40002000
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#define VENDOR_REG_BASE 0x40002800
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#define NFC_INTERFACE_BASE 0x40002400
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#define LOG_UART_REG_BASE 0x40003000
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#define I2C2_REG_BASE 0x40003400
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#define I2C3_REG_BASE 0x40003800
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#define SDR_CTRL_BASE 0x40005000
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#define SPI_FLASH_CTRL_BASE 0x40006000
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#define ADC_REG_BASE 0x40010000
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#define DAC_REG_BASE 0x40011000
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@ -10,7 +10,7 @@
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#ifndef _HAL_SDR_CONTROLLER_H_
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#define _HAL_SDR_CONTROLLER_H_
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#if 1 // def CONFIG_SDR_EN
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#if 1 //def CONFIG_SDR_EN
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typedef enum _DRAM_TYPE_ {
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DRAM_DDR_1 = 1,
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@ -187,5 +187,5 @@ typedef struct _DRAM_DEVICE_INFO_ {
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#define HAL_SDRAM_READ8(addr) HAL_READ8(SDR_SDRAM_BASE, addr)
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#endif // CONFIG_SDR_EN
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// extern unsigned int rand_x; // in rtl_bios_data.h
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//extern unsigned int rand_x;
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#endif // end of "#ifndef _HAL_SDR_CONTROLLER_H_"
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@ -68,7 +68,7 @@ enum _SPIC_BIT_MODE_ {
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#define FLASH_EON 5
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//#define FLASH_MXIC_MX25L4006E 0
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//#define FLASH_MXIC_MX25L8073E 0
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//#define FLASH_MXIC_MX25L8073E 1
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//#define FLASH_MICRON_N25Q512A 1
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// The below parts are based on the flash characteristics
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//====== Flash Command Definition ======
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@ -244,6 +244,7 @@ enum _SPIC_BIT_MODE_ {
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//#endif
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#if 0
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#if FLASH_MXIC_MX25L4006E
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#define FLASH_RD_2IO_EN 1
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@ -0,0 +1,130 @@
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2015 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "rtl8195a.h"
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#include "build_info.h"
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#include "PinNames.h"
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#include "serial_api.h"
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extern void serial_init (serial_t *obj, PinName tx, PinName rx);
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extern void serial_free (serial_t *obj);
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extern void serial_baud (serial_t *obj, int baudrate);
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extern void serial_format (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
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extern int main(void);
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void iar_data_init_fw_loader(void);
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void fw_loader_main(void);// __attribute__ ((weak));
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#pragma section=".image2.start.table1"
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#pragma section=".fwloader_ram.bss"
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FW_LOADER_START_RAM_FUN_SECTION
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RAM_START_FUNCTION gFWLoaderEntryFun0 = {fw_loader_main};
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u8* __image4_entry_func__;
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u8* __image4_validate_code__;
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u8* __fwloader_bss_start__;
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u8* __fwloader_bss_end__;
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FW_LOADER_VALID_PATTEN_SECTION const u8 RAM_FW_LOADER_VALID_PATTEN[20] = {
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'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
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(FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
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(FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
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(FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff),
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(FW_CHIP_VER),
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(FW_BUS_TYPE),
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(FW_INFO_RSV1),
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(FW_INFO_RSV2),
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(FW_INFO_RSV3),
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(FW_INFO_RSV4)
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};
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/**
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* @brief Main program.
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* @param None
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* @retval None
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*/
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void fw_loader_main(void)
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{
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#if defined ( __ICCARM__ )
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iar_data_init_fw_loader();
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#endif
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u32 Image2Len, Image2Addr, ImageIndex, SpicBitMode, SpicImageIndex;
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u32 Image2LoadAddr = 0x13000;
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DBG_8195A("===== Enter FW Loader Image ====\n");
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#ifdef BOOTLOADER
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main();
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#endif
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IGMAE4:
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PRAM_START_FUNCTION Image4EntryFun=(PRAM_START_FUNCTION)__image4_entry_func__;
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Image2Len = HAL_READ32(SPI_FLASH_BASE, Image2LoadAddr);
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Image2Addr = HAL_READ32(SPI_FLASH_BASE, (Image2LoadAddr+0x4));
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DBG_8195A("Flash FW Loader:Addr 0x%x, Len %d, Load to SRAM 0x%x\n", Image2LoadAddr, Image2Len, Image2Addr);
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SpicImageIndex = 0;
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for (ImageIndex = 0x10 + Image2LoadAddr; ImageIndex < (Image2Len + Image2LoadAddr + 0x10); ImageIndex = ImageIndex + 4) {
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HAL_WRITE32(Image2Addr, SpicImageIndex,
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HAL_READ32(SPI_FLASH_BASE, ImageIndex));
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SpicImageIndex += 4;
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}
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#ifdef CONFIG_SDR_EN
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u32 Image3LoadAddr;
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u32 Image3Len;
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u32 Image3Addr;
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Image3LoadAddr = Image2LoadAddr + Image2Len+0x10;
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Image3Len = HAL_READ32(SPI_FLASH_BASE, Image3LoadAddr);
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Image3Addr = HAL_READ32(SPI_FLASH_BASE, Image3LoadAddr + 0x4);
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if( (Image3Len==0xFFFFFFFF) || (Image3Len==0) || (Image3Addr!=0x30000000)){
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DBG_8195A("No Image3\n\r");
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}else{
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DBG_8195A("Image3 length: 0x%x, Image3 Addr: 0x%x\n",Image3Len, Image3Addr);
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SpicImageIndex = 0;
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for (ImageIndex = 0x10 + Image3LoadAddr;
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ImageIndex < (Image3Len + Image3LoadAddr + 0x10);
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ImageIndex = ImageIndex + 4) {
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HAL_WRITE32(Image3Addr, SpicImageIndex,
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HAL_READ32(SPI_FLASH_BASE, ImageIndex));
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SpicImageIndex += 4;
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}
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}
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#endif
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//3 3) Jump to image 4
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DBG_8195A("InfraStart: %p, Img2 Sign %s \n", __image4_entry_func__, (char*)__image4_validate_code__);
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if (_strcmp((char *)__image4_validate_code__, "RTKWin")) {
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while (1) {
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DBG_8195A("Invalid Image4 Signature\n");
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RtlConsolRom(1000);//each delay is 100us
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}
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}
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#ifdef BOOTLOADER
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deinit_platform_bootloader();
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#endif
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Image4EntryFun->RamStartFun();
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}
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void iar_data_init_fw_loader(void)
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{
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__image4_entry_func__ = (u8*)__section_begin(".image2.start.table1");
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__image4_validate_code__ = __image4_entry_func__+4;//(u8*)__section_begin(".image2.start.table2");
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__fwloader_bss_start__ = (u8*)__section_begin(".fwloader_ram.bss");
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__fwloader_bss_end__ = (u8*)__section_end(".fwloader_ram.bss");
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}
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@ -0,0 +1,82 @@
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/*
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decompiled low_level_io.o
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*/
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#include ......
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//-------------------------------------------------------------------------
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// Function declarations
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void mode_init();
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void HalSerialPutcRtl8195a(int c, int a2, char a3);
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signed int DiagPrintf(const char *fmt, ...);
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void log_uart_enable_printf();
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void log_uart_disable_printf();
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//-------------------------------------------------------------------------
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// Data declarations
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uint32_t backupWarn;
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uint32_t backupErr;
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uint32_t backupInfo;
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int disablePrintf;
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// extern _UNKNOWN use_mode;
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// extern _UNKNOWN ConfigDebugErr;
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// extern _UNKNOWN ConfigDebugInfo;
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// extern _UNKNOWN ConfigDebugWarn;
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//-----
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void mode_init()
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{
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use_mode = 1;
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}
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//-----
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void HalSerialPutcRtl8195a(int c)
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{
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signed int v3; // r3@2
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if ( disablePrintf != 1 )
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{
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v3 = 6540;
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do
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{
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if ( !--v3 )
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break;
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a3 = v40003014;
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}
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while ( !(v40003014 & 0x60) );
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if ( c == 10 ) a3 = 13;
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v40003000 = c;
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if ( c == 10 ) v40003000 = a3;
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}
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}
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//-----
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signed int DiagPrintf(const char *fmt, ...)
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{
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va_list va;
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va_start(va, fmt);
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if ( disablePrintf != 1 )
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VSprintf(0, fmt, va);
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return 1;
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}
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//-----
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void log_uart_enable_printf()
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{
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disablePrintf = 0;
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ConfigDebugErr = backupErr;
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ConfigDebugInfo = backupInfo;
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ConfigDebugWarn = backupWarn;
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}
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//-----
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void log_uart_disable_printf()
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{
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disablePrintf = 1;
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backupErr = ConfigDebugErr;
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backupInfo = ConfigDebugInfo;
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backupWarn = ConfigDebugWarn;
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ConfigDebugErr = 0;
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ConfigDebugInfo = 0;
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ConfigDebugWarn = 0;
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}
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@ -911,30 +911,30 @@
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#define BIT_CTRL_FLUSH_FIFO(x) (((x) & BIT_MASK_FLUSH_FIFO) << BIT_SHIFT_FLUSH_FIFO)
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//=================== Register Address Definition ============================//
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#define REG_SPIC_CTRLR0 0x0000//O
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#define REG_SPIC_CTRLR1 0x0004//O
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#define REG_SPIC_SSIENR 0x0008//O
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#define REG_SPIC_MWCR 0x000C
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#define REG_SPIC_SER 0x0010//O
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#define REG_SPIC_BAUDR 0x0014//O
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#define REG_SPIC_TXFTLR 0x0018
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#define REG_SPIC_RXFTLR 0x001C//O
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#define REG_SPIC_TXFLR 0x0020//O
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#define REG_SPIC_RXFLR 0x0024
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#define REG_SPIC_SR 0x0028
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#define REG_SPIC_IMR 0x002C//O
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#define REG_SPIC_ISR 0x0030
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#define REG_SPIC_RISR 0x0034
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#define REG_SPIC_TXOICR 0x0038
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#define REG_SPIC_RXOICR 0x003C
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#define REG_SPC_RXUICR 0x0040
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#define REG_SPIC_MSTICR 0x0044
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#define REG_SPIC_ICR 0x0048
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#define REG_SPIC_DMACR 0x004C
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#define REG_SPIC_DMATDLR0 0x0050
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#define REG_SPIC_DMATDLR1 0x0054
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#define REG_SPIC_IDR 0x0058
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#define REG_SPIC_VERSION 0x005C
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#define REG_SPIC_CTRLR0 0x0000 //O 0x1040300
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#define REG_SPIC_CTRLR1 0x0004 //O 0x10
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#define REG_SPIC_SSIENR 0x0008 //O 0
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#define REG_SPIC_MWCR 0x000C // 0
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#define REG_SPIC_SER 0x0010 //O 1
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#define REG_SPIC_BAUDR 0x0014 //O 1
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#define REG_SPIC_TXFTLR 0x0018 // 0
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#define REG_SPIC_RXFTLR 0x001C //O 0x1F
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#define REG_SPIC_TXFLR 0x0020 //O 0
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#define REG_SPIC_RXFLR 0x0024 // 0
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#define REG_SPIC_SR 0x0028 // 6
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#define REG_SPIC_IMR 0x002C //O 0x1FF
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#define REG_SPIC_ISR 0x0030 // 4
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#define REG_SPIC_RISR 0x0034 // 4
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#define REG_SPIC_TXOICR 0x0038 // 0
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#define REG_SPIC_RXOICR 0x003C // 0
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#define REG_SPC_RXUICR 0x0040 // 0
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#define REG_SPIC_MSTICR 0x0044 // 0
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#define REG_SPIC_ICR 0x0048 // 0
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#define REG_SPIC_DMACR 0x004C // 0
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#define REG_SPIC_DMATDLR0 0x0050 // 0
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#define REG_SPIC_DMATDLR1 0x0054 // 0
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#define REG_SPIC_IDR 0x0058 // 0x10001
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#define REG_SPIC_VERSION 0x005C // 0x40470603
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#define REG_SPIC_DR0 0x0060
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#define REG_SPIC_DR1 0x0064
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#define REG_SPIC_DR2 0x0068
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@ -966,26 +966,26 @@
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#define REG_SPIC_DR28 0x00D0
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#define REG_SPIC_DR29 0x00D4
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#define REG_SPIC_DR30 0x00D8
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#define REG_SPIC_DR31 0x00DC
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#define REG_SPIC_READ_FAST_SINGLE 0x00E0//O
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#define REG_SPIC_READ_DUAL_DATA 0x00E4//O
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#define REG_SPIC_READ_DUAL_ADDR_DATA 0x00E8//O
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#define REG_SPIC_READ_QUAD_DATA 0x00EC//O
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#define REG_SPIC_READ_QUAD_ADDR_DATA 0x00F0//O
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#define REG_SPIC_WRITE_SIGNLE 0x00F4//O
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#define REG_SPIC_WRITE_DUAL_DATA 0x00F8//O
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#define REG_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC//O
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#define REG_SPIC_WRITE_QUAD_DATA 0x0100//O
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#define REG_SPIC_WRITE_QUAD_ADDR_DATA 0x0104//O
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#define REG_SPIC_WRITE_ENABLE 0x0108//O
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#define REG_SPIC_READ_STATUS 0x010C//O
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#define REG_SPIC_CTRLR2 0x0110//O
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#define REG_SPIC_FBAUDR 0x0114//O
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#define REG_SPIC_ADDR_LENGTH 0x0118//O
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#define REG_SPIC_AUTO_LENGTH 0x011C//O
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#define REG_SPIC_VALID_CMD 0x0120//O
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#define REG_SPIC_FLASE_SIZE 0x0124//O
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#define REG_SPIC_FLUSH_FIFO 0x0128//O
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#define REG_SPIC_DR31 0x00DC // MXIC (DeviceID: FC, Flash Size: 1048576 bytes, FlashID: C22014/1, SpicMode: DIO)
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#define REG_SPIC_READ_FAST_SINGLE 0x00E0 //O 0x0B
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#define REG_SPIC_READ_DUAL_DATA 0x00E4 //O 0x3B
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#define REG_SPIC_READ_DUAL_ADDR_DATA 0x00E8 //O 0x3B
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#define REG_SPIC_READ_QUAD_DATA 0x00EC //O 0x6B
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#define REG_SPIC_READ_QUAD_ADDR_DATA 0x00F0 //O 0xEB
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#define REG_SPIC_WRITE_SIGNLE 0x00F4 //O 0x02
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#define REG_SPIC_WRITE_DUAL_DATA 0x00F8 //O 0xA2
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#define REG_SPIC_WRITE_DUAL_ADDR_DATA 0x00FC//O 0xA2
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#define REG_SPIC_WRITE_QUAD_DATA 0x0100 //O 0x32
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#define REG_SPIC_WRITE_QUAD_ADDR_DATA 0x0104//O 0x38
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#define REG_SPIC_WRITE_ENABLE 0x0108 //O 0x06
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#define REG_SPIC_READ_STATUS 0x010C //O 0x05
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#define REG_SPIC_CTRLR2 0x0110 //O 0x51
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#define REG_SPIC_FBAUDR 0x0114 //O 0x1
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#define REG_SPIC_ADDR_LENGTH 0x0118 //O 0x3
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#define REG_SPIC_AUTO_LENGTH 0x011C //O 0x20030011/0x20030021
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#define REG_SPIC_VALID_CMD 0x0120 //O 0x202
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#define REG_SPIC_FLASE_SIZE 0x0124 //O 0x0E
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#define REG_SPIC_FLUSH_FIFO 0x0128 //O 0
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VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode); // spi-flash controller initialization
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VOID SpicRxCmdRtl8195A(u8 cmd); // recieve command
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Binary file not shown.
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@ -7,13 +7,21 @@
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "rtl8195a.h"
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#include "platform_opts.h"
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#include "hal_sdr_controller.h"
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#include "rtl8195a_sdr.h"
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#include "flash_api.h"
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||||
|
||||
#ifdef CONFIG_SDR_EN
|
||||
|
||||
#ifndef USE_SRC_ONLY_BOOT
|
||||
#define USE_SRC_ONLY_BOOT 0
|
||||
#endif
|
||||
|
||||
#if !USE_SRC_ONLY_BOOT
|
||||
#define SDRAM_INIT_USE_TCM_HEAP
|
||||
#define SDRAM_INIT_USE_FLASH_API
|
||||
#endif
|
||||
|
||||
|
||||
#if 0
|
||||
|
|
@ -122,9 +130,11 @@ u32 SdrCalibration(VOID);
|
|||
//#define Sdr_Rand2 Rand
|
||||
|
||||
#ifndef SDRAM_INIT_USE_TCM_HEAP
|
||||
#if !USE_SRC_ONLY_BOOT
|
||||
//3 Note: stack overfloat if the arrary is declared in the task
|
||||
HAL_CUT_B_RAM_DATA_SECTION
|
||||
u32 AvaWds[2][REC_NUM];
|
||||
#endif
|
||||
#else
|
||||
typedef struct {
|
||||
u32 m[2][REC_NUM];
|
||||
|
|
@ -138,6 +148,12 @@ unsigned int rand_x = 123456789;
|
|||
*/
|
||||
#ifdef CONFIG_SDR_EN
|
||||
|
||||
//#pragma arm section code = ".hal.sdrc.text"
|
||||
#pragma arm section rodata = ".rodata.hal.sdrc"
|
||||
//, rwdata = ".hal.sdrc.data"
|
||||
//, zidata = ".hal.sdrc.bss"
|
||||
//#pragma arm section bss = ".hal.sdrc.bss"
|
||||
|
||||
#ifdef CONFIG_SDR_VERIFY
|
||||
enum{
|
||||
LLT,
|
||||
|
|
@ -744,8 +760,10 @@ SdrCalibration(
|
|||
u32 valid;
|
||||
union { u8 b[4]; u32 l;} value;
|
||||
////
|
||||
#ifdef SDRAM_INIT_USE_FLASH_API
|
||||
flash_turnon();
|
||||
if(fspic_isinit == 0) flash_init(&flashobj);
|
||||
#endif
|
||||
////
|
||||
|
||||
u32 CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4);
|
||||
|
|
@ -776,11 +794,16 @@ SdrCalibration(
|
|||
}
|
||||
#endif
|
||||
|
||||
#if !USE_SRC_ONLY_BOOT
|
||||
#ifdef SDRAM_INIT_USE_TCM_HEAP
|
||||
pAvaWds AvaWds = (pAvaWds) tcm_heap_calloc(sizeof(u32)*REC_NUM*2);
|
||||
#else
|
||||
_memset((u8*)AvaWds, 0, sizeof(u32)*REC_NUM*2);
|
||||
#endif
|
||||
#else
|
||||
u32 AvaWds[2][REC_NUM];
|
||||
_memset((u8*)AvaWds, 0, sizeof(u32)*REC_NUM*2);
|
||||
#endif
|
||||
|
||||
volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
|
||||
ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
|
||||
|
|
@ -981,7 +1004,7 @@ SdrCalibration(
|
|||
return Result;
|
||||
} // SdrCalibration
|
||||
|
||||
|
||||
HAL_RAM_DATA_SECTION
|
||||
/*
|
||||
|
||||
HAL_SDRC_TEXT_SECTION
|
||||
|
|
@ -1062,7 +1085,7 @@ u8 IsSdrPowerOn(
|
|||
|
||||
#else // ifndef CONFIG_SDR_EN
|
||||
|
||||
VOID SdrPowerOff(
|
||||
HAL_SDRC_TEXT_SECTION VOID SdrPowerOff(
|
||||
VOID
|
||||
)
|
||||
{
|
||||
|
|
@ -1072,7 +1095,6 @@ VOID SdrPowerOff(
|
|||
}
|
||||
|
||||
|
||||
|
||||
HAL_SDRC_TEXT_SECTION VOID SdrCtrlInit(VOID)
|
||||
{
|
||||
DBG_SDR_ERR("No SDRAM!\n");
|
||||
|
|
|
|||
|
|
@ -12,8 +12,9 @@
|
|||
|
||||
#include "rtl8195a_spi_flash.h"
|
||||
|
||||
#pragma arm section code = ".hal.flash.text", rodata = ".hal.flash.rodata", rwdata = ".hal.flash.data", zidata = ".hal.flash.bss"
|
||||
|
||||
#define SPI_CTRL_BASE 0x1FFEF000
|
||||
//#define SPI_CTRL_BASE 0x1FFEF000
|
||||
#define SPI_DLY_CTRL_ADDR 0x40000300 // [7:0]
|
||||
#define MIN_BAUDRATE 0x01
|
||||
#define MAX_BAUDRATE 0x04
|
||||
|
|
@ -633,7 +634,6 @@ SpicReadIDRtl8195A(
|
|||
}
|
||||
/* Disable SPI_FLASH User Mode */
|
||||
HAL_SPI_WRITE32(REG_SPIC_SSIENR, 0);
|
||||
|
||||
}
|
||||
|
||||
HAL_FLASH_TEXT_SECTION
|
||||
|
|
@ -645,7 +645,7 @@ SpicCalibrationRtl8195A
|
|||
)
|
||||
{
|
||||
|
||||
u32 rd_data, /*id_no,*/ baudr, autolen, dly_line;
|
||||
u32 rd_data, baudr, autolen, dly_line;
|
||||
u32 total_ava_wds=0;
|
||||
u32 tmp_str_pt, tmp_end_pt, pass, last_pass;
|
||||
struct ava_window max_wd;
|
||||
|
|
@ -841,9 +841,7 @@ SpicConfigAutoModeRtl8195A
|
|||
BIT_RD_DUAL_IO |
|
||||
BIT_RD_DUAL_I))));//Disable all the four and two bit commands.
|
||||
}
|
||||
|
||||
|
||||
if (SpicDualBitMode == SpicBitMode) {
|
||||
else if (SpicDualBitMode == SpicBitMode) {
|
||||
#if FLASH_RD_2IO_EN
|
||||
HAL_SPI_WRITE32(REG_SPIC_READ_DUAL_ADDR_DATA, FLASH_CMD_2READ);
|
||||
#endif
|
||||
|
|
@ -856,8 +854,7 @@ SpicConfigAutoModeRtl8195A
|
|||
(HAL_SPI_READ32(REG_SPIC_VALID_CMD)|(FLASH_VLD_DUAL_CMDS)));
|
||||
|
||||
}
|
||||
|
||||
if (SpicQuadBitMode == SpicBitMode) {
|
||||
else if (SpicQuadBitMode == SpicBitMode) {
|
||||
#if FLASH_WR_4IO_EN
|
||||
HAL_SPI_WRITE32(REG_SPIC_WRITE_QUAD_ADDR_DATA, FLASH_CMD_4PP);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue