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https://github.com/pvvx/RTL00MP3.git
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pvvx
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5e30f12891
commit
ad9b495d7e
10 changed files with 120 additions and 36 deletions
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@ -35,6 +35,18 @@ typedef struct _HAL_SDIO_HOST_OP_ {
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HAL_Status (*HalSdioHostSetWriteProtect) (VOID *Data, u8 Setting);
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}HAL_SDIO_HOST_OP, *PHAL_SDIO_HOST_OP;
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// SDIO error type
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typedef enum _SDIO_ERR_TYPE_ {
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SDIO_ERR_DAT_CRC = 0x01,
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SDIO_ERR_CMD_TIMEOUT = 0x02,
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}SDIO_ERR_TYPE;
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typedef enum _SDIO_XFER_TYPE_{
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SDIO_XFER_NOR = 0x00, // normal
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SDIO_XFER_R = 0x01, // read and write block
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SDIO_XFER_W = 0x02, // read and write block
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}SDIO_XFER_TYPE;
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typedef struct _HAL_SDIO_HOST_ADAPTER_{
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IRQ_HANDLE IrqHandle; // Irq Handler
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ADMA2_DESC_FMT *AdmaDescTbl;
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@ -46,15 +58,21 @@ typedef struct _HAL_SDIO_HOST_ADAPTER_{
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u8 Csd[CSD_REG_LEN];
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volatile u8 CmdCompleteFlg;
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volatile u8 XferCompleteFlg;
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volatile u8 ErrIntFlg;
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volatile u8 ErrIntFlg;
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volatile u8 CardCurState;
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u8 IsSdhc;
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u8 CurrSdClk;
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u16 RCA;
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u16 SdSpecVer;
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SDIO_ERR_TYPE errType;
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SDIO_XFER_TYPE XferType;
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VOID (*XferCompCallback)(VOID *pAdapter);
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VOID *XferCompCbPara;
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VOID (*ErrorCallback)(VOID *pAdapter);
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VOID *ErrorCbPara;
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VOID (*CardInsertCallBack)(VOID *pAdapter);
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VOID (*CardRemoveCallBack)(VOID *pAdapter);
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VOID *CardInsertCbPara;
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VOID (*CardRemoveCallBack)(VOID *pAdapter);
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VOID *CardRemoveCbPara;
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}HAL_SDIO_HOST_ADAPTER, *PHAL_SDIO_HOST_ADAPTER;
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@ -9,9 +9,13 @@
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#include "rtl8195a.h"
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#include "hal_sdr_controller.h"
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#include "rtl8195a_sdr.h"
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#include "flash_api.h"
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#ifdef CONFIG_SDR_EN
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#define SDRAM_INIT_USE_TCM_HEAP
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#if 0
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#define HAL_SDR_WRITE32(addr, value32) HAL_WRITE32(SDR_CTRL_BASE, addr, value32)
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#define HAL_SDR_WRITE16(addr, value16) HAL_WRITE16(SDR_CTRL_BASE, addr, value16)
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@ -28,6 +32,9 @@
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#define HAL_SDRAM_READ8(addr) HAL_READ8(SDR_SDRAM_BASE, addr)
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#endif
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#define DEBUG_SDRAM 2
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//#define CONFIG_SDR_VERIFY
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extern SPIC_INIT_PARA SpicInitParaAllClk[3][CPU_CLK_TYPE_NO];
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HAL_CUT_B_RAM_DATA_SECTION
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@ -111,17 +118,24 @@ u32 SdrControllerInit(VOID);
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VOID DramInit(DRAM_DEVICE_INFO *);
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s32 MemTest(u32 loop_cnt);
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u32 SdrCalibration(VOID);
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u32 Sdr_Rand2(VOID);
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//u32 Sdr_Rand2(VOID);
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//#define Sdr_Rand2 Rand
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#ifndef SDRAM_INIT_USE_TCM_HEAP
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//3 Note: stack overfloat if the arrary is declared in the task
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HAL_CUT_B_RAM_DATA_SECTION
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u32 AvaWds[2][REC_NUM];
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#else
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typedef struct {
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u32 m[2][REC_NUM];
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} sAvaWds, * pAvaWds;
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#endif
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#endif // CONFIG_SDR_EN
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/*
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HAL_CUT_B_RAM_DATA_SECTION
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unsigned int rand_x = 123456789;
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*/
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#ifdef CONFIG_SDR_EN
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#ifdef CONFIG_SDR_VERIFY
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@ -350,8 +364,9 @@ VOID
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SdrCtrlInit(
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VOID
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){
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HAL_WRITE32(0x40000000, 0x40,
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((HAL_READ32(0x40000000, 0x40)&0xfffff)|0xe00000));
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// ConfigDebugErr |= _DBG_MISC_;
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// DBG_8195A("SDR Ctrl Init\n");
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HAL_WRITE32(0x40000000, 0x40, ((HAL_READ32(0x40000000, 0x40)&0xfffff)|0xe00000));
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LDO25M_CTRL(ON);
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}
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@ -361,6 +376,7 @@ SdrControllerInit(
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VOID
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)
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{
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// ConfigDebugErr |= _DBG_MISC_;
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DBG_8195A("SDR Controller Init\n");
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HAL_WRITE32(0x40000000, 0x40,
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@ -424,7 +440,7 @@ DramInit (
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// In PHY, write latency == 3
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DramMaxWr= (DramInfo->Timing->WrMaxTck)/(DfiRate) +1;
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DramWr = ((DramInfo->Timing->TwrPs) / DrmaPeriod)+1;
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DramWr = ((DramInfo->Timing->TwrPs) / DrmaPeriod) +1;
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CrTwr = ((DramInfo->Timing->TwrPs) / DrmaPeriod) + 3;
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if (CrTwr < DramMaxWr) {
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@ -727,20 +743,28 @@ SdrCalibration(
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SPIC_INIT_PARA SpicInitPara;
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u32 valid;
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union { u8 b[4]; u32 l;} value;
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////
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flash_turnon();
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if(fspic_isinit == 0) flash_init(&flashobj);
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////
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u32 CpuType = ((HAL_READ32(SYSTEM_CTRL_BASE, REG_SYS_CLK_CTRL1) & (0x70)) >> 4);
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valid = RdPipe = TapCnt = 0xFFFFFFFF;
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value.l = HAL_READ32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType);
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if((value.b[0]^value.b[1])==0xFF)
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valid = value.b[0];
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//DiagPrintf("dump1 %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
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#if DEBUG_SDRAM > 1
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DiagPrintf("dump1 %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
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#endif
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value.l = HAL_READ32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType+4);
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if((value.b[0]^value.b[1])==0xFF)
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RdPipe = value.b[0];
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if((value.b[2]^value.b[3])==0xFF)
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TapCnt = value.b[2];
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//DiagPrintf("dump2 %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
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#if DEBUG_SDRAM > 1
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DiagPrintf("dump2 %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
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#endif
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if((valid==1)&&(RdPipe!=0xFFFFFFFF)&&(TapCnt!=0xFFFFFFFF)){
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// wait DRAM settle down
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HalDelayUs(10);
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@ -752,7 +776,11 @@ SdrCalibration(
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}
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#endif
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#ifdef SDRAM_INIT_USE_TCM_HEAP
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pAvaWds AvaWds = (pAvaWds) tcm_heap_calloc(sizeof(u32)*REC_NUM*2);
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#else
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_memset((u8*)AvaWds, 0, sizeof(u32)*REC_NUM*2);
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#endif
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volatile struct ms_rxi310_portmap *ms_ctrl_0_map;
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ms_ctrl_0_map = (struct ms_rxi310_portmap*) SDR_CTRL_BASE;
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@ -766,8 +794,10 @@ SdrCalibration(
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// ms_ctrl_0_map->iocr = (ms_ctrl_0_map->iocr & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO);
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HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RdPipe << PCTL_IOCR_RD_PIPE_BFO)));
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DBG_SDR_INFO("IOCR: 0x%x; Write: 0x%x\n",HAL_SDR_READ32(REG_SDR_IOCR), (RdPipe << PCTL_IOCR_RD_PIPE_BFO));
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// DBG_8195A("IOCR: 0x%x; Write: 0x%x\n",ms_ctrl_0_map->iocr, (RdPipe << PCTL_IOCR_RD_PIPE_BFO));
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DBG_SDR_INFO("IOCR: 0x%x; Write: 0x%x\n", HAL_SDR_READ32(REG_SDR_IOCR), (RdPipe << PCTL_IOCR_RD_PIPE_BFO));
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#if DEBUG_SDRAM > 1
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DBG_8195A("IOCR: 0x%x; Write: 0x%x\n",ms_ctrl_0_map->iocr, (RdPipe << PCTL_IOCR_RD_PIPE_BFO));
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#endif
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RdPipeFlag = _FALSE;
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PassFlag = _FALSE;
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@ -785,7 +815,7 @@ SdrCalibration(
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HAL_SDR_WRITE32(REG_SDR_DLY0, TapCnt);
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// ms_ctrl_0_map->phy_dly0 = TapCnt;
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#endif
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DBG_SDR_INFO("DLY: 0x%x; Write: 0x%x\n",HAL_PERI_ON_READ32(REG_PESOC_MEM_CTRL), TapCnt);
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DBG_SDR_INFO("DLY: 0x%x; Write: 0x%x\n", HAL_PERI_ON_READ32(REG_PESOC_MEM_CTRL), TapCnt);
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#else
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SDR_DDL_FCTRL(TapCnt);
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// Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF);
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@ -804,8 +834,11 @@ SdrCalibration(
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RdPipeFlag = _TRUE;
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RecRdPipe[RdPipeCounter - 1] = RdPipe;
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}
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#ifdef SDRAM_INIT_USE_TCM_HEAP
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AvaWds->m[RdPipeCounter-1][AvaWdsCnt] = TapCnt;
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#else
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AvaWds[RdPipeCounter-1][AvaWdsCnt] = TapCnt;
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#endif
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AvaWdsCnt++;
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RecNum[RdPipeCounter-1] = AvaWdsCnt;
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@ -834,13 +867,13 @@ SdrCalibration(
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}
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// }
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}
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}
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} // for TapCnt
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if (RdPipeCounter > 2) {
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u8 BestRangeIndex, BestIndex;
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#ifdef CONFIG_SDR_VERIFY //to reduce log
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#ifdef CONFIG_SDR_VERIFY //to reduce log
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u32 i;
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DBG_SDR_INFO("Avaliable RdPipe 0\n");
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@ -851,7 +884,7 @@ SdrCalibration(
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for (i=0;i<256;i++) {
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DBG_SDR_INFO("%d\n", AvaWds[1][i]);
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}
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#endif
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#endif
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DBG_SDR_INFO("Rec 0 => total counter %d; RdPipe:%d;\n", RecNum[0], RecRdPipe[0]);
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DBG_SDR_INFO("Rec 1 => total counter %d; RdPipe:%d;\n", RecNum[1], RecRdPipe[1]);
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@ -859,16 +892,22 @@ SdrCalibration(
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BestRangeIndex = (RecNum[0] > RecNum[1]) ? 0 : 1;
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BestIndex = RecNum[BestRangeIndex]>>1;
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#ifdef SDRAM_INIT_USE_TCM_HEAP
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DBG_SDR_INFO("The Finial RdPipe: %d; TpCnt: 0x%x\n", RecRdPipe[BestRangeIndex], AvaWds->m[BestRangeIndex][BestIndex]);
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#else
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DBG_SDR_INFO("The Finial RdPipe: %d; TpCnt: 0x%x\n", RecRdPipe[BestRangeIndex], AvaWds[BestRangeIndex][BestIndex]);
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#endif
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// set RdPipe and tap_dly
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// ms_ctrl_0_map->iocr = (ms_ctrl_0_map->iocr & 0xff) | (RecRdPipe[BestRangeIndex] << PCTL_IOCR_RD_PIPE_BFO);
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HAL_SDR_WRITE32(REG_SDR_IOCR, ((HAL_SDR_READ32(REG_SDR_IOCR) & 0xff) | (RecRdPipe[BestRangeIndex] << PCTL_IOCR_RD_PIPE_BFO)));
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#ifdef FPGA
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#ifdef FPGA_TEMP
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#ifdef SDRAM_INIT_USE_TCM_HEAP
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SDR_DDL_FCTRL(AvaWds->m[BestRangeIndex][BestIndex]);
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#else
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SDR_DDL_FCTRL(AvaWds[BestRangeIndex][BestIndex]);
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#endif
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// Value32 = (RD_DATA(SDR_CLK_DLY_CTRL) & 0xFF00FFFF);
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// Value32 = Value32 | (AvaWds[BestRangeIndex][BestIndex] << 16);
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@ -885,13 +924,19 @@ SdrCalibration(
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#endif
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#if DRAM_CALIBRATION_IN_NVM
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RdPipe = RecRdPipe[BestRangeIndex];
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#ifdef SDRAM_INIT_USE_TCM_HEAP
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TapCnt = AvaWds->m[BestRangeIndex][BestIndex];
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#else
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TapCnt = AvaWds[BestRangeIndex][BestIndex];
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#endif
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value.b[0] = (u8)RdPipe;
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value.b[1] = ~value.b[0];
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value.b[2] = (u8)TapCnt;
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value.b[3] = ~value.b[2];
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//DiagPrintf("dump1w %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
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#if DEBUG_SDRAM > 1
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DiagPrintf("dump1w %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
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#endif
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if( HAL_READ32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType+4) == 0xFFFFFFFF)
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{
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HAL_WRITE32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType+4, value.l);
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@ -907,7 +952,9 @@ SdrCalibration(
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value.b[1] = ~value.b[0];
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value.b[2] = 0xFF;
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value.b[3] = 0xFF;
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//DiagPrintf("dump1w %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
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#if DEBUG_SDRAM > 1
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DiagPrintf("dump1w %x, %x %x %x %x \n\r", value.l, value.b[0], value.b[1], value.b[2], value.b[3]);
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#endif
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if( HAL_READ32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType) == 0xFFFFFFFF )
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{
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HAL_WRITE32(SPI_FLASH_BASE, FLASH_SDRC_PARA_BASE+8*CpuType, value.l);
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@ -928,11 +975,14 @@ SdrCalibration(
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}
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}
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#ifdef SDRAM_INIT_USE_TCM_HEAP
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tcm_heap_free(AvaWds);
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#endif
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return Result;
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} // SdrCalibration
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/*
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HAL_SDRC_TEXT_SECTION
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VOID
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@ -963,7 +1013,9 @@ Sdr_Rand2(
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return rand_x + y + z;
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}
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*/
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HAL_SDRC_TEXT_SECTION
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s32
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MemTest(
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@ -973,8 +1025,10 @@ MemTest(
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u32 LoopIndex = 0;
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u32 Value32, Addr;
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for (LoopIndex = 0; LoopIndex<LoopCnt; LoopIndex++) {
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Value32 = Sdr_Rand2();
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Addr = Sdr_Rand2();
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// Value32 = Sdr_Rand2();
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// Addr = Sdr_Rand2();
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Value32 = Rand();
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Addr = Rand();
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Addr &= 0x1FFFFF;
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Addr &= (~0x3);
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