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Merge remote-tracking branch 'upstream/master'

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This commit is contained in:
Tido Klaassen 2017-05-14 16:41:21 +02:00
commit aafc2a508f
197 changed files with 52917 additions and 3054 deletions
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6
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_i2c.h
View file

@ -17,9 +17,9 @@
// I2C SAL User Configuration Flags
// I2C SAL operation types
#define I2C_POLL_OP_TYPE 1
#define I2C_INTR_OP_TYPE 1
#define I2C_DMA_OP_TYPE 1
#define I2C_POLL_OP_TYPE 1 //1
#define I2C_INTR_OP_TYPE 1 //1
#define I2C_DMA_OP_TYPE 1 //1
// I2C supports user register address
#define I2C_USER_REG_ADDR 1 //I2C User specific register address by using

86
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_i2c.h
View file

@ -739,49 +739,49 @@
#define BIT_GET_IC_COMP_TYPE(x) (((x) >> BIT_SHIFT_IC_COMP_TYPE) & BIT_MASK_IC_COMP_TYPE)
//======================== Register Address Definition ========================
#define REG_DW_I2C_IC_CON 0x0000
#define REG_DW_I2C_IC_TAR 0x0004
#define REG_DW_I2C_IC_SAR 0x0008
#define REG_DW_I2C_IC_HS_MADDR 0x000C
#define REG_DW_I2C_IC_DATA_CMD 0x0010
#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014
#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018
#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C
#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020
#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024
#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028
#define REG_DW_I2C_IC_INTR_STAT 0x002C
#define REG_DW_I2C_IC_INTR_MASK 0x0030
#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034
#define REG_DW_I2C_IC_RX_TL 0x0038
#define REG_DW_I2C_IC_TX_TL 0x003C
#define REG_DW_I2C_IC_CLR_INTR 0x0040
#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044
#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048
#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C
#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050
#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054
#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058
#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C
#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060
#define REG_DW_I2C_IC_CLR_START_DET 0x0064
#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068
#define REG_DW_I2C_IC_ENABLE 0x006C
#define REG_DW_I2C_IC_STATUS 0x0070
#define REG_DW_I2C_IC_TXFLR 0x0074
#define REG_DW_I2C_IC_RXFLR 0x0078
#define REG_DW_I2C_IC_SDA_HOLD 0x007C
#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080
#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084
#define REG_DW_I2C_IC_DMA_CR 0x0088
#define REG_DW_I2C_IC_DMA_TDLR 0x008C
#define REG_DW_I2C_IC_DMA_RDLR 0x0090
#define REG_DW_I2C_IC_SDA_SETUP 0x0094
#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098
#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C
#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4
#define REG_DW_I2C_IC_COMP_VERSION 0x00F8
#define REG_DW_I2C_IC_COMP_TYPE 0x00FC
#define REG_DW_I2C_IC_CON 0x0000 // Control Register
#define REG_DW_I2C_IC_TAR 0x0004 // Master Target Address
#define REG_DW_I2C_IC_SAR 0x0008 // Slave Address
#define REG_DW_I2C_IC_HS_MADDR 0x000C // High Speed Master ID
#define REG_DW_I2C_IC_DATA_CMD 0x0010 // Data Buffer and Command
#define REG_DW_I2C_IC_SS_SCL_HCNT 0x0014 // Standard Speed Clock SCL High Count
#define REG_DW_I2C_IC_SS_SCL_LCNT 0x0018 // Standard Speed Clock SCL Low Count
#define REG_DW_I2C_IC_FS_SCL_HCNT 0x001C // Fast Speed Clock SCL High Count
#define REG_DW_I2C_IC_FS_SCL_LCNT 0x0020 // Fast Speed I2C Clock SCL Low Count
#define REG_DW_I2C_IC_HS_SCL_HCNT 0x0024 // High Speed I2C Clock SCL High Count
#define REG_DW_I2C_IC_HS_SCL_LCNT 0x0028 // High Speed I2C Clock SCL Low Count
#define REG_DW_I2C_IC_INTR_STAT 0x002C // Interrupt Status
#define REG_DW_I2C_IC_INTR_MASK 0x0030 // Interrupt Mask
#define REG_DW_I2C_IC_RAW_INTR_STAT 0x0034 // Raw Interrupt Status
#define REG_DW_I2C_IC_RX_TL 0x0038 // Receive FIFO Threshold Level
#define REG_DW_I2C_IC_TX_TL 0x003C // Transmit FIFO Threshold Level
#define REG_DW_I2C_IC_CLR_INTR 0x0040 // Clear Combined and Individual Interrupt
#define REG_DW_I2C_IC_CLR_RX_UNDER 0x0044 // Clear RX_UNDER Interrupt
#define REG_DW_I2C_IC_CLR_RX_OVER 0x0048 // Clear RX_OVER Interrupt
#define REG_DW_I2C_IC_CLR_TX_OVER 0x004C // Clear TX_OVER Interrupt
#define REG_DW_I2C_IC_CLR_RD_REQ 0x0050 // Clear RD_REQ Interrupt
#define REG_DW_I2C_IC_CLR_TX_ABRT 0x0054 // Clear TX_ABRT Interrupt
#define REG_DW_I2C_IC_CLR_RX_DONE 0x0058 // Clear RX_DONE Interrupt
#define REG_DW_I2C_IC_CLR_ACTIVITY 0x005C // Clear ACTIVITY Interrupt
#define REG_DW_I2C_IC_CLR_STOP_DET 0x0060 // Clear STOP_DET Interrupt
#define REG_DW_I2C_IC_CLR_START_DET 0x0064 // Clear START_DET Interrupt
#define REG_DW_I2C_IC_CLR_GEN_CALL 0x0068 // Clear GEN_CALL Interrupt
#define REG_DW_I2C_IC_ENABLE 0x006C // Enable
#define REG_DW_I2C_IC_STATUS 0x0070 // Status
#define REG_DW_I2C_IC_TXFLR 0x0074 // Transmit FIFO Level
#define REG_DW_I2C_IC_RXFLR 0x0078 // Receive FIFO Level
#define REG_DW_I2C_IC_SDA_HOLD 0x007C // SDA Hold
#define REG_DW_I2C_IC_TX_ABRT_SOURCE 0x0080 // Transmit Abort Source
#define REG_DW_I2C_IC_SLV_DATA_NACK_ONLY 0x0084 //
#define REG_DW_I2C_IC_DMA_CR 0x0088 //
#define REG_DW_I2C_IC_DMA_TDLR 0x008C // DMA Transmit Data Level Register
#define REG_DW_I2C_IC_DMA_RDLR 0x0090 // I2C Receive Data Level Register
#define REG_DW_I2C_IC_SDA_SETUP 0x0094 // SDA Setup
#define REG_DW_I2C_IC_ACK_GENERAL_CALL 0x0098 // General Call Ack
#define REG_DW_I2C_IC_ENABLE_STATUS 0x009C // Enable Status
#define REG_DW_I2C_IC_COMP_PARAM_1 0x00F4 // Configuration Parameters
#define REG_DW_I2C_IC_COMP_VERSION 0x00F8 // Component Version
#define REG_DW_I2C_IC_COMP_TYPE 0x00FC // Component Type
//======================================================
// I2C related enumeration

2
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_peri_on.h
View file

@ -168,7 +168,7 @@
#define BIT_PESOC_SPI1_SCLK_SEL BIT(18)
#define BIT_SHIFT_PESOC_PERI_SCLK_SEL 16
#define BIT_MASK_PESOC_PERI_SCLK_SEL 0x3
#define BIT_MASK_PESOC_PERI_SCLK_SEL 0x3 // 0 - CLK, 1 - CLK/2, 2 - CLK/4, 3 - CLK/8
#define BIT_PESOC_PERI_SCLK_SEL(x) (((x) & BIT_MASK_PESOC_PERI_SCLK_SEL) << BIT_SHIFT_PESOC_PERI_SCLK_SEL)

212
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c
View file

@ -2630,14 +2630,14 @@ SoCPWRIdleTaskHandleTest(
DiagPrintf("0x2009F408 : 0x%x\n", HAL_READ32(0x2009F400,8));
DiagPrintf("\n");
HAL_WRITE32(0x40000000,0x330,0x55559555);//0x55552a2a
HAL_WRITE32(PERI_ON_BASE,0x330,0x55559555);//0x55552a2a
//slp pg GPIOD GPIOE
HAL_WRITE32(0x40000000,0x334,0x55555555);
HAL_WRITE32(0x40000000,0x338,0x05555555);
HAL_WRITE32(0x40000000,0x33c,0x55555555);
HAL_WRITE32(0x40000000,0x340,0x55555555);
HAL_WRITE32(0x40000000,0x344,0x55555555);
HAL_WRITE32(0x40000000,0x320,0x0);
HAL_WRITE32(PERI_ON_BASE,0x334,0x55555555);
HAL_WRITE32(PERI_ON_BASE,0x338,0x05555555);
HAL_WRITE32(PERI_ON_BASE,0x33c,0x55555555);
HAL_WRITE32(PERI_ON_BASE,0x340,0x55555555);
HAL_WRITE32(PERI_ON_BASE,0x344,0x55555555);
HAL_WRITE32(PERI_ON_BASE,0x320,0x0);
HAL_WRITE32(0x20080000, 0, (HAL_READ32(0x20080000,0)+1));
HAL_WRITE32(0x20080000, 4, (HAL_READ32(0x20080000,4)+1));
@ -2648,22 +2648,22 @@ SoCPWRIdleTaskHandleTest(
}
}
//mem test
if (HAL_READ8(0x40000000,0xf1) == 0xaa) {
if (HAL_READ8(SYSTEM_CTRL_BASE,0xf1) == 0xaa) {
CMDTemp[0] = 8;
SOCPSTestApp((VOID*)CMDTemp);
Rtemp = HAL_READ32(0x40080000,0x824);
Rtemp = HAL_READ32(WIFI_REG_BASE,0x824);
Rtemp2 = Rtemp;
Rtemp2 = ((Rtemp2 & 0x807fffff) | 0x80000000);
HAL_WRITE32(0x40080000,0x824,Rtemp&0x7fffffff);
HAL_WRITE32(0x40080000,0x824,Rtemp2);
HAL_WRITE32(0x40080000,0x824,(Rtemp|0x80000000));
Rtemp1 = HAL_READ32(0x40080000,0x820)&BIT8;
HAL_WRITE32(WIFI_REG_BASE,0x824,Rtemp&0x7fffffff);
HAL_WRITE32(WIFI_REG_BASE,0x824,Rtemp2);
HAL_WRITE32(WIFI_REG_BASE,0x824,(Rtemp|0x80000000));
Rtemp1 = HAL_READ32(WIFI_REG_BASE,0x820)&BIT8;
if (Rtemp1) {
Rtemp = HAL_READ32(0x40080000,0x8b8)&0xfffff;
Rtemp = HAL_READ32(WIFI_REG_BASE,0x8b8)&0xfffff;
}
else {
Rtemp = HAL_READ32(0x40080000,0x8a0)&0xfffff;
Rtemp = HAL_READ32(WIFI_REG_BASE,0x8a0)&0xfffff;
}
if(Rtemp== 0x00045678){
Chktemp = 1;
@ -2673,16 +2673,16 @@ SoCPWRIdleTaskHandleTest(
&SoCPSMEMTestChk(0x1FFF4000,0x5000,0x12345678);
if (Chktemp) {
HAL_WRITE32(0x40080000,0x4,(HAL_READ32(0x40080000,0x4)&0xFFFFFFF0));
HAL_WRITE32(0x40000000,0xfc,(HAL_READ32(0x40000000,0xfc)+1));
DiagPrintf("run %d times\n", HAL_READ32(0x40000000,0xfc));
HAL_WRITE32(WIFI_REG_BASE,0x4,(HAL_READ32(WIFI_REG_BASE,0x4)&0xFFFFFFF0));
HAL_WRITE32(SYSTEM_CTRL_BASE,0xfc,(HAL_READ32(SYSTEM_CTRL_BASE,0xfc)+1));
DiagPrintf("run %d times\n", HAL_READ32(SYSTEM_CTRL_BASE,0xfc));
CMDTemp[0] = 1;
CMDTemp[1] = 5;
CMDTemp[2] = 0xff;
SOCPSTestApp((VOID*)CMDTemp);
}
else {
HAL_WRITE32(0x40000000,0xf0,0);
HAL_WRITE32(SYSTEM_CTRL_BASE,0xf0,0);
}
}
@ -2973,14 +2973,14 @@ SOCPSTestApp(
case 0:
DiagPrintf("SoC PWR Init wlan\n");
Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,0x214)|BIT16;
HAL_WRITE32(SYSTEM_CTRL_BASE,0x214,Rtemp);
Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_HCI_COM_FUNC_EN)|BIT_SOC_HCI_WL_MACON_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SOC_HCI_COM_FUNC_EN,Rtemp);
Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,0x244)|BIT0;
HAL_WRITE32(SYSTEM_CTRL_BASE,0x244,Rtemp);
Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_PESOC_COM_CLK_CTRL1)|BIT_SOC_ACTCK_WL_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_PESOC_COM_CLK_CTRL1,Rtemp);
Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,0x210)|BIT2;
HAL_WRITE32(SYSTEM_CTRL_BASE,0x210,Rtemp);
Rtemp = HAL_READ32(SYSTEM_CTRL_BASE,REG_SOC_FUNC_EN)|BIT_SOC_LXBUS_EN;
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SOC_FUNC_EN,Rtemp);
HalDelayUs(100);
@ -2989,10 +2989,10 @@ SOCPSTestApp(
#if 0
DiagPrintf("SoC PWR debug setting\n");
Rtemp = 0;
HAL_WRITE32(SYSTEM_CTRL_BASE,0x33c,Rtemp);
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_GPIO_PULL_CTRL3,Rtemp);
Rtemp = 0;
HAL_WRITE32(SYSTEM_CTRL_BASE,0x334,Rtemp);
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_GPIO_PULL_CTRL1,Rtemp);
#if 0
//en debug
@ -3027,8 +3027,8 @@ SOCPSTestApp(
//HAL_WRITE32(0x40001000,0x4,0x4000000);
//SIC EN
//HAL_WRITE32(0x40000000,0x8,0x81000010);
//HAL_WRITE32(0x40000000,0xA4,0x00000001);
//HAL_WRITE32(SYSTEM_CTRL_BASE,0x8,0x81000010);
//HAL_WRITE32(SYSTEM_CTRL_BASE,0xA4,0x00000001);
//Wait for LogUart print out
while(1) {
@ -3040,14 +3040,14 @@ SOCPSTestApp(
#if 0
HAL_WRITE32(0x40000000,0x330,0x55559555);//0x55552a2a
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL0,0x55559555);//0x55552a2a
//slp pg GPIOD GPIOE
HAL_WRITE32(0x40000000,0x334,0x55555555);
HAL_WRITE32(0x40000000,0x338,0x05555555);
HAL_WRITE32(0x40000000,0x33c,0x55555555);
HAL_WRITE32(0x40000000,0x340,0x55555555);
HAL_WRITE32(0x40000000,0x344,0x55555555);
HAL_WRITE32(0x40000000,0x320,0x0);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL1,0x55555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL2,0x05555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL3,0x55555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL4,0x55555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL5,0x55555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_SHTDN_CTRL,0x0);
#endif
ChangeSoCPwrState(TestParameter[1], TestParameter[2]);
@ -3062,27 +3062,27 @@ SOCPSTestApp(
case 2:
#if 1
HAL_WRITE32(0x40000000,0x320,0x7ff);
HAL_WRITE32(0x40000000,0x330,0x5565A555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_SHTDN_CTRL,0x7ff);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL0,0x5565A555);
//slp pg GPIOD GPIOE
HAL_WRITE32(0x40000000,0x334,0x55555555);
HAL_WRITE32(0x40000000,0x338,0x05555555);
HAL_WRITE32(0x40000000,0x33c,0x55555555);
HAL_WRITE32(0x40000000,0x340,0x55555555);
HAL_WRITE32(0x40000000,0x344,0x55555555);
HAL_WRITE32(0x40000000,0x348,0x55555555);
HAL_WRITE32(0x40000000,0x320,0x0);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL1,0x55555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL2,0x05555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL3,0x55555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL4,0x55555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL5,0x55555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_PULL_CTRL6,0x55555555);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_SHTDN_CTRL,0x0);
HAL_WRITE32(0x40000000,0x8,0x80000011);
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_FUNC_EN,0x80000011);
#endif
HAL_WRITE32(SYSTEM_CTRL_BASE, 0X120, TestParameter[1]);
HAL_WRITE32(SYSTEM_CTRL_BASE, 0X124, TestParameter[2]);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, TestParameter[1]);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT, TestParameter[2]);
if (TestParameter[4] == 0xff) {
//SIC EN
HAL_WRITE32(0x40000000,0x320,0x4);
HAL_WRITE32(0x40000000,0x8,0xC1000010);
HAL_WRITE32(0x40000000,0xA4,0x00000001);
HAL_WRITE32(PERI_ON_BASE,REG_GPIO_SHTDN_CTRL,0x4);
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_FUNC_EN,0xC1000010);
HAL_WRITE32(SYSTEM_CTRL_BASE,REG_SYS_PINMUX_CTRL,0x00000001);
}
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, TestParameter[3]);
@ -3097,8 +3097,8 @@ SOCPSTestApp(
break;
case 3:
HAL_WRITE32(SYSTEM_CTRL_BASE, 0X120, 0x74000e00);
HAL_WRITE32(SYSTEM_CTRL_BASE, 0X124, 2);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION, 0x74000e00);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_OPTION_EXT, 2);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, TestParameter[1]);
#if 0
{
@ -3182,27 +3182,27 @@ SOCPSTestApp(
Rtemp = 0x00000001;
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_SLP_WAKE_EVENT_MSK0, Rtemp);
#if 0
HAL_WRITE32(0x40000000,0x330,0x55559555);//0x55552a2a
HAL_WRITE32(0x40000000,0x2C0,0x100001);
HAL_WRITE32(PERI_ON_BASE,0x330,0x55559555);//0x55552a2a
HAL_WRITE32(PERI_ON_BASE,0x2C0,0x100001);
//slp pg GPIOD GPIOE
HAL_WRITE32(0x40000000,0x334,0x55555555);
HAL_WRITE32(0x40000000,0x338,0x05555555);
HAL_WRITE32(0x40000000,0x33c,0x55555555);
HAL_WRITE32(0x40000000,0x340,0x55555555);
HAL_WRITE32(0x40000000,0x344,0x55555555);
HAL_WRITE32(0x40000000,0x320,0x0);
HAL_WRITE32(PERI_ON_BASE,0x334,0x55555555);
HAL_WRITE32(PERI_ON_BASE,0x338,0x05555555);
HAL_WRITE32(PERI_ON_BASE,0x33c,0x55555555);
HAL_WRITE32(PERI_ON_BASE,0x340,0x55555555);
HAL_WRITE32(PERI_ON_BASE,0x344,0x55555555);
HAL_WRITE32(PERI_ON_BASE,0x320,0x0);
#endif
HAL_WRITE32(SYSTEM_CTRL_BASE, 0X120, TestParameter[1]);
HAL_WRITE32(SYSTEM_CTRL_BASE, 0X124, TestParameter[2]);
if (HAL_READ32(0x40000000,0xf4) == 0x11) {
HAL_WRITE32(0x40000000,0x8,0x80000011);
if (HAL_READ32(SYSTEM_CTRL_BASE,0xf4) == 0x11) {
HAL_WRITE32(SYSTEM_CTRL_BASE,0x8,0x80000011);
}
if (TestParameter[4] == 0xff) {
//SIC EN
HAL_WRITE32(0x40000000,0x8,0x81000010);
HAL_WRITE32(0x40000000,0xA4,0x00000001);
HAL_WRITE32(SYSTEM_CTRL_BASE,0x8,0x81000010);
HAL_WRITE32(SYSTEM_CTRL_BASE,0xA4,0x00000001);
}
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_SYS_PWRMGT_CTRL, TestParameter[3]);
@ -3267,27 +3267,27 @@ SOCPSTestApp(
case 8:
DiagPrintf("enable wifi\n");
Rtemp = HAL_READ32(0x40000000,0x214)|0x10000;
HAL_WRITE32(0x40000000,0x214,Rtemp);
Rtemp = HAL_READ32(0x40000000,0x244)|0x1;
HAL_WRITE32(0x40000000,0x244,Rtemp);
Rtemp = HAL_READ32(0x40000000,0x210)|0x4;
HAL_WRITE32(0x40000000,0x210,Rtemp);
Rtemp = HAL_READ32(PERI_ON_BASE,REG_SOC_HCI_COM_FUNC_EN)|BIT_SOC_HCI_WL_MACON_EN;
HAL_WRITE32PERI_ON_BASE,REG_SOC_HCI_COM_FUNC_EN,Rtemp);
Rtemp = HAL_READ32(PERI_ON_BASE,REG_PESOC_COM_CLK_CTRL1)|BIT_SOC_ACTCK_WL_EN;
HAL_WRITE32(PERI_ON_BASE,REG_PESOC_COM_CLK_CTRL1,Rtemp);
Rtemp = HAL_READ32(PERI_ON_BASE,REG_SOC_FUNC_EN)|BIT_SOC_LXBUS_EN;
HAL_WRITE32(PERI_ON_BASE,REG_SOC_FUNC_EN,Rtemp);
Rtemp = HAL_READ32(0x40080000,0x0)&0xFFFFFFDF;
HAL_WRITE32(0x40080000,0x0,Rtemp);
Rtemp = HAL_READ32(0x40080000,0x4)|0x1;
HAL_WRITE32(0x40080000,0x4,Rtemp);
Rtemp = HAL_READ32(0x40080000,0x20)|0x1;
HAL_WRITE32(0x40080000,0x20,Rtemp);
while( (HAL_READ32(0x40080000,0x20)&BIT0)!=0);
Rtemp = HAL_READ32(WIFI_REG_BASE,0x0)&0xFFFFFFDF;
HAL_WRITE32(WIFI_REG_BASE,0x0,Rtemp);
Rtemp = HAL_READ32(WIFI_REG_BASE,0x4)|0x1;
HAL_WRITE32(WIFI_REG_BASE,0x4,Rtemp);
Rtemp = HAL_READ32(WIFI_REG_BASE,0x20)|0x1;
HAL_WRITE32(WIFI_REG_BASE,0x20,Rtemp);
while( (HAL_READ32(WIFI_REG_BASE,0x20)&BIT0)!=0);
Rtemp = HAL_READ32(0x40080000,0x4)|0x30000;
HAL_WRITE32(0x40080000,0x4,Rtemp);
Rtemp = HAL_READ32(0x40080000,0x4)|0x7000000;
HAL_WRITE32(0x40080000,0x4,Rtemp);
Rtemp = HAL_READ32(0x40080000,0x50)&0xFFFFFF00;
HAL_WRITE32(0x40080000,0x50,Rtemp);
Rtemp = HAL_READ32(WIFI_REG_BASE,0x4)|0x30000;
HAL_WRITE32(WIFI_REG_BASE,0x4,Rtemp);
Rtemp = HAL_READ32(WIFI_REG_BASE,0x4)|0x7000000;
HAL_WRITE32(WIFI_REG_BASE,0x4,Rtemp);
Rtemp = HAL_READ32(WIFI_REG_BASE,0x50)&0xFFFFFF00;
HAL_WRITE32(WIFI_REG_BASE,0x50,Rtemp);
break;
case 9:
@ -3315,18 +3315,18 @@ SOCPSTestApp(
break;
case 10:
Rtemp = HAL_READ32(0x40080000,0x824);
Rtemp = HAL_READ32(WIFI_REG_BASE,0x824);
Rtemp2 = Rtemp;
Rtemp2 = Rtemp2 & 0x807fffff | (TestParameter[1]<<23) | 0x80000000;
HAL_WRITE32(0x40080000,0x824,Rtemp&0x7fffffff);
HAL_WRITE32(0x40080000,0x824,Rtemp2);
HAL_WRITE32(0x40080000,0x824,Rtemp|0x80000000);
Rtemp1 = HAL_READ32(0x40080000,0x820)&BIT8;
HAL_WRITE32(WIFI_REG_BASE,0x824,Rtemp&0x7fffffff);
HAL_WRITE32(WIFI_REG_BASE,0x824,Rtemp2);
HAL_WRITE32(WIFI_REG_BASE,0x824,Rtemp|0x80000000);
Rtemp1 = HAL_READ32(WIFI_REG_BASE,0x820)&BIT8;
if (Rtemp1) {
Rtemp = HAL_READ32(0x40080000,0x8b8)&0xfffff;
Rtemp = HAL_READ32(WIFI_REG_BASE,0x8b8)&0xfffff;
}
else {
Rtemp = HAL_READ32(0x40080000,0x8a0)&0xfffff;
Rtemp = HAL_READ32(WIFI_REG_BASE,0x8a0)&0xfffff;
}
DiagPrintf("rf offset: 0x%x, 0x%x\n", TestParameter[1], Rtemp);
break;
@ -3334,7 +3334,7 @@ SOCPSTestApp(
case 11://addr [1]; date [2]
TestParameter[1] &= 0x3f;
Rtemp = (TestParameter[1]<<20)|(TestParameter[2]&0x000fffff)&0x0fffffff;
HAL_WRITE32(0x40080000,0x840,Rtemp);
HAL_WRITE32(WIFI_REG_BASE,0x840,Rtemp);
//SoCPWRIdleTaskHandle();
break;
@ -3348,19 +3348,19 @@ SOCPSTestApp(
break;
case 14:
HAL_WRITE32(0x40000000,TestParameter[1],0x12345678);
DiagPrintf("w32: 0x%x\n", HAL_READ32(0x40000000,TestParameter[1]));
HAL_WRITE32(0x40000000,TestParameter[1],0);
HAL_WRITE16(0x40000000,TestParameter[1],0x1234);
DiagPrintf("w16: 0x%x\n", HAL_READ32(0x40000000,TestParameter[1]));
HAL_WRITE32(0x40000000,TestParameter[1],0);
HAL_WRITE8(0x40000000,TestParameter[1],0x12);
DiagPrintf("w8: 0x%x\n", HAL_READ32(0x40000000,TestParameter[1]));
HAL_WRITE32(0x40000000,TestParameter[1],0x12345678);
DiagPrintf("R32: 0x%x\n", HAL_READ32(0x40000000,TestParameter[1]));
DiagPrintf("R16: 0x%x\n", HAL_READ16(0x40000000,TestParameter[1]));
DiagPrintf("R8: 0x%x\n", HAL_READ8(0x40000000,TestParameter[1]));
Rtemp = ((HAL_READ32(0x40000000,0xf4))?1:0);
HAL_WRITE32(SYSTEM_CTRL_BASE,TestParameter[1],0x12345678);
DiagPrintf("w32: 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE,TestParameter[1]));
HAL_WRITE32(SYSTEM_CTRL_BASE,TestParameter[1],0);
HAL_WRITE16(SYSTEM_CTRL_BASE,TestParameter[1],0x1234);
DiagPrintf("w16: 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE,TestParameter[1]));
HAL_WRITE32(SYSTEM_CTRL_BASE,TestParameter[1],0);
HAL_WRITE8(SYSTEM_CTRL_BASE,TestParameter[1],0x12);
DiagPrintf("w8: 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE,TestParameter[1]));
HAL_WRITE32(SYSTEM_CTRL_BASE,TestParameter[1],0x12345678);
DiagPrintf("R32: 0x%x\n", HAL_READ32(SYSTEM_CTRL_BASE,TestParameter[1]));
DiagPrintf("R16: 0x%x\n", HAL_READ16(SYSTEM_CTRL_BASE,TestParameter[1]));
DiagPrintf("R8: 0x%x\n", HAL_READ8(SYSTEM_CTRL_BASE,TestParameter[1]));
Rtemp = ((HAL_READ32(SYSTEM_CTRL_BASE,0xf4))?1:0);
DiagPrintf("R: 0x%x\n", Rtemp);
break;
@ -3463,7 +3463,7 @@ SOCPSTestApp(
break;
}
}
HAL_WRITE32(SYSTEM_CTRL_BASE, 0X2c0, 0x0);
HAL_WRITE32(SYSTEM_CTRL_BASE, REG_CPU_PERIPHERAL_CTRL, 0x0);
GpioPsPullCtrl();

1
RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/export-rom_v04.txt
View file

@ -240,6 +240,7 @@ SECTIONS
RtkI2CDeInit = 0xbe4d;
RtkI2CSendUserAddr = 0xbee5;
RtkI2CSend = 0xc07d;
_RtkI2CReceive = 0x0c6dd;
RtkI2CLoadDefault = 0xce51;
RtkSalI2COpInit = 0xcf21;
HalI2SWrite32 = 0xcf65;

7
RTL00_SDKV35a/component/soc/realtek/8195a/misc/rtl_std_lib/lib_rtlstd/ram_pvvx_libc.c
View file

@ -534,10 +534,3 @@ int __aeabi_fcmpgt(float a, float b)
{
return __rtl_fcmpgt_v1_00(a, b);
}