mirror of
https://github.com/pvvx/RTL00MP3.git
synced 2025-07-31 12:41:06 +00:00
update
This commit is contained in:
pvvx
parent
8a03c98d0a
commit
95b8017e95
20 changed files with 3315 additions and 2732 deletions
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@ -88,11 +88,11 @@ typedef struct _feep_element {
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} FEEP_ELEMENT, *PFEEP_ELEMENT;
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FEEP_ELEMENT feep_tab[] = {
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{ FEEP_ID_WIFI_AP_CFG, sizeof(wifi_ap_cfg), &wifi_ap_cfg }, // Bit0
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{ FEEP_ID_WIFI_ST_CFG, sizeof(wifi_st_cfg), &wifi_st_cfg }, // Bit1
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{ FEEP_ID_AP_DHCP_CFG, sizeof(wifi_ap_dhcp), &wifi_ap_dhcp }, // Bit2
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{ FEEP_ID_ST_DHCP_CFG, sizeof(wifi_st_dhcp), &wifi_st_dhcp }, // Bit3
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{ FEEP_ID_WIFI_CFG, sizeof(wifi_cfg), &wifi_cfg }, // Bit4
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{ FEEP_ID_WIFI_AP_CFG, sizeof(wifi_ap_cfg), &wifi_ap_cfg }, // Bit0 BID_WIFI_AP_CFG
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{ FEEP_ID_WIFI_ST_CFG, sizeof(wifi_st_cfg), &wifi_st_cfg }, // Bit1 BID_WIFI_ST_CFG
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{ FEEP_ID_AP_DHCP_CFG, sizeof(wifi_ap_dhcp), &wifi_ap_dhcp }, // Bit2 BID_AP_DHCP_CFG
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{ FEEP_ID_ST_DHCP_CFG, sizeof(wifi_st_dhcp), &wifi_st_dhcp }, // Bit3 BID_ST_DHCP_CFG
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{ FEEP_ID_WIFI_CFG, sizeof(wifi_cfg), &wifi_cfg }, // Bit4 BID_WIFI_CFG
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// { FEEP_ID_LWIP_CFG, sizeof(lwip_conn_info), &lwip_conn_info }, // Bit5
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{ 0, 0, NULL }
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};
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@ -144,11 +144,6 @@ _WEAK void connect_close(void)
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info_printf("\%s: Time at start %d ms.\n", __func__, xTaskGetTickCount());
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}
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_WEAK void user_start(void)
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{
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info_printf("\%s: Time at start %d ms.\n", __func__, xTaskGetTickCount());
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}
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int wlan_init_done_callback(void) {
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info_printf("WiFi Init after %d ms\n", xTaskGetTickCount());
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return 0;
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@ -479,9 +474,9 @@ error_end:
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return ret;
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}
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void wifi_init_thrd(void) {
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void wifi_init(void) {
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debug_printf("\nLoad Config\n");
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read_wifi_cfg(DEF_LOAD_CFG);
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read_wifi_cfg(wifi_cfg.load_flg); // DEF_LOAD_CFG
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// Call back from wlan driver after wlan init done
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p_wlan_init_done_callback = wlan_init_done_callback;
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// Call back from application layer after wifi_connection success
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@ -493,12 +488,7 @@ void wifi_init_thrd(void) {
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wifi_manager_init();
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#endif
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wifi_run(wifi_cfg.mode);
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user_start();
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}
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/* Initilaize the console stack */
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console_init();
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/* Kill init thread after all init tasks done */
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vTaskDelete(NULL);
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}
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rtw_security_t translate_rtw_security(u8 security_type)
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@ -563,274 +553,3 @@ void show_wifi_cfg(void) {
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printf("\tSave flags: %p\n", wifi_cfg.save_flg);
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}
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//==========================================================
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//--- CONSOLE --------------------------
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#include "section_config.h"
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#include "hal_diag.h"
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// ATPN=<SSID>[,password[,encryption[,auto reconnect[,reconnect pause]]]: WIFI Connect to AP
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void fATPN(int argc, char *argv[]){
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if(argc > 1) {
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if(argv[1][0] == '?') {
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show_wifi_st_cfg();
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}
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else {
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strncpy(wifi_st_cfg.ssid, argv[1], NDIS_802_11_LENGTH_SSID);
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if(argc > 2) {
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strncpy(wifi_st_cfg.password, argv[2], NDIS_802_11_LENGTH_SSID);
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int i = strlen(wifi_st_cfg.password);
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if(i > 7) {
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wifi_st_cfg.security_type = RTW_SECURITY_WPA2_AES_PSK;
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}
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else if(!i) {
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wifi_st_cfg.security_type = RTW_SECURITY_OPEN;
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}
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else {
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printf("password len < 8!\n");
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wifi_st_cfg.security_type = RTW_SECURITY_OPEN;
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}
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}
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else {
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wifi_st_cfg.password[0] = 0;
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wifi_st_cfg.security_type = RTW_SECURITY_OPEN;
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}
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if(argc > 3) {
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wifi_st_cfg.security_type = translate_rtw_security(atoi(argv[3]));
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}
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if(argc > 4) {
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wifi_st_cfg.autoreconnect = atoi(argv[3]);
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}
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else wifi_st_cfg.autoreconnect = 0;
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if(argc > 5) {
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wifi_st_cfg.reconnect_pause = atoi(argv[3]);
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}
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else wifi_st_cfg.reconnect_pause = 5;
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show_wifi_st_cfg();
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wifi_run(wifi_run_mode | RTW_MODE_STA);
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}
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}
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}
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// ATPA=<SSID>[,password[,encryption[,channel[,hidden[,max connections]]]]]: Start WIFI AP
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void fATPA(int argc, char *argv[]){
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if(argc > 1) {
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if(argv[1][0] == '?') {
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show_wifi_ap_cfg();
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}
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else {
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strncpy(wifi_ap_cfg.ssid, argv[1], NDIS_802_11_LENGTH_SSID);
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if(argc > 2) {
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strncpy(wifi_ap_cfg.password, argv[2], NDIS_802_11_LENGTH_SSID);
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int i = strlen(wifi_ap_cfg.password);
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if(i > 7) {
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wifi_ap_cfg.security_type = RTW_SECURITY_WPA2_AES_PSK;
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}
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else if(i == 0) {
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wifi_ap_cfg.security_type = RTW_SECURITY_OPEN;
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}
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else {
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printf("password len < 8!\n");
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wifi_ap_cfg.security_type = RTW_SECURITY_OPEN;
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}
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}
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else {
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wifi_ap_cfg.password[0] = 0;
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wifi_ap_cfg.security_type = RTW_SECURITY_OPEN;
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}
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if(argc > 3) {
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wifi_ap_cfg.security_type = translate_rtw_security(atoi(argv[3]));
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}
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if(argc > 4) {
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wifi_ap_cfg.channel = atoi(argv[4]);
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}
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else wifi_ap_cfg.channel = 1;
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if(argc > 5) {
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wifi_ap_cfg.ssid_hidden = atoi(argv[5]);
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}
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else wifi_ap_cfg.ssid_hidden = 0;
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if(argc > 6) {
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wifi_ap_cfg.max_sta = atoi(argv[6]);
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}
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else wifi_ap_cfg.max_sta = 3;
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show_wifi_ap_cfg();
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wifi_run(wifi_run_mode | RTW_MODE_AP);
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}
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}
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}
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// WIFI Connect, Disconnect
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void fATWR(int argc, char *argv[]){
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rtw_mode_t mode = RTW_MODE_NONE;
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if(argc > 1) mode = atoi(argv[1]);
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wifi_run(mode);
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}
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// Close connections
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void fATOF(int argc, char *argv[]){
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connect_close();
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}
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// Open connections
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void fATON(int argc, char *argv[]){
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connect_start();
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}
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void fATWI(int argc, char *argv[]) {
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rtw_wifi_setting_t Setting;
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if((wifi_run_mode & RTW_MODE_AP)
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&& wifi_get_setting(wlan_ap_name, &Setting) == 0) {
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wifi_show_setting(wlan_ap_name, &Setting);
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// show_wifi_ap_ip();
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printf("\tIP: " IPSTR "\n", IP2STR(&xnetif[WLAN_AP_NETIF_NUM].ip_addr));
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}
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if((wifi_run_mode & RTW_MODE_STA)
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&& wifi_get_setting(wlan_st_name, &Setting) == 0) {
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wifi_show_setting(wlan_st_name, &Setting);
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// show_wifi_st_ip();
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printf("\tIP: " IPSTR "\n", IP2STR(&xnetif[WLAN_ST_NETIF_NUM].ip_addr));
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}
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printf("\nWIFI config:\n");
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printf(&str_rom_57ch3Dch0A[25]); // "================================\n"
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show_wifi_cfg();
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printf("\nWIFI AP config:\n");
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printf(&str_rom_57ch3Dch0A[25]); // "================================\n"
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show_wifi_ap_cfg();
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printf("\nWIFI ST config:\n");
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printf(&str_rom_57ch3Dch0A[25]); // "================================\n"
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show_wifi_st_cfg();
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printf("\n");
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if(argc > 2
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&& (argv[1][0] == 's'
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|| argv[1][0] == 'S')) {
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int i = atoi(argv[2]);
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printf("Save configs(%d)..\n", i);
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write_wifi_cfg(atoi(argv[2]));
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}
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}
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void fATWT(int argc, char *argv[]) {
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if(argc > 1) {
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int txpwr = atoi(argv[1]);
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debug_printf("set tx power (%d)...\n", txpwr);
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if(rltk_set_tx_power_percentage(txpwr) != RTW_SUCCESS) {
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error_printf("Error set tx power (%d)!", wifi_cfg.tx_pwr);
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}
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}
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printf("TX power = %d\n", rtw_power_percentage_idx);
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}
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//-- Test tsf (64-bits counts, 1 us step) ---
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#include "hal_com_reg.h"
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#define ReadTSF_Lo32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR)))
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#define ReadTSF_Hi32() (*((volatile unsigned int *)(WIFI_REG_BASE + REG_TSFTR1)))
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LOCAL uint64_t get_tsf(void)
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{
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return *((uint64_t *)(WIFI_REG_BASE + REG_TSFTR));
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}
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void fATSF(int argc, char *argv[])
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{
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uint64_t tsf = get_tsf();
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printf("\nTSF: %08x%08x\n", (uint32_t)(tsf>>32), (uint32_t)(tsf));
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}
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/* -------- WiFi Scan ------------------------------- */
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unsigned char *tab_txt_rtw_secyrity[] = {
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"OPEN ",
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"WEP ",
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"WPA TKIP",
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"WPA AES",
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"WPA2 AES",
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"WPA2 TKIP",
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"WPA2 Mixed",
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"WPA/WPA2 AES",
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"Unknown"
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};
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unsigned int *tab_code_rtw_secyrity[] = {
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RTW_SECURITY_OPEN,
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RTW_SECURITY_WEP_PSK,
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RTW_SECURITY_WPA_TKIP_PSK,
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RTW_SECURITY_WPA_AES_PSK,
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RTW_SECURITY_WPA2_AES_PSK,
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RTW_SECURITY_WPA2_TKIP_PSK,
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RTW_SECURITY_WPA2_MIXED_PSK,
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RTW_SECURITY_WPA_WPA2_MIXED,
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RTW_SECURITY_UNKNOWN
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};
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volatile uint8_t scan_end;
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/* -------- WiFi Scan ------------------------------- */
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static rtw_result_t _scan_result_handler( rtw_scan_handler_result_t* malloced_scan_result )
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{
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if (malloced_scan_result->scan_complete != RTW_TRUE) {
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rtw_scan_result_t* record = &malloced_scan_result->ap_details;
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record->SSID.val[record->SSID.len] = 0; /* Ensure the SSID is null terminated */
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if(scan_end == 1) {
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printf("\nScan networks:\n\n");
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printf("N\tType\tMAC\t\t\tSignal\tCh\tWPS\tSecyrity\tSSID\n\n");
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};
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printf("%d\t", scan_end++);
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printf("%s\t", (record->bss_type == RTW_BSS_TYPE_ADHOC)? "Adhoc": "Infra");
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printf(MAC_FMT, MAC_ARG(record->BSSID.octet));
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printf("\t%d\t", record->signal_strength);
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printf("%d\t", record->channel);
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printf("%d\t", record->wps_type);
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int i = 0;
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for(; record->security != tab_code_rtw_secyrity[i] && tab_code_rtw_secyrity[i] != RTW_SECURITY_UNKNOWN; i++);
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printf("%s \t", tab_txt_rtw_secyrity[i]);
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printf("%s\n", record->SSID.val);
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} else {
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scan_end = 0;
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printf("\n");
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}
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return RTW_SUCCESS;
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}
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/* -------- WiFi Scan ------------------------------- */
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#define scan_channels 14
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void fATSN(int argc, char *argv[])
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{
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int i;
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u8 *channel_list = (u8*)pvPortMalloc(scan_channels*2);
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if(channel_list) {
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scan_end = 1;
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u8 * pscan_config = &channel_list[scan_channels];
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//parse command channel list
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for(i = 1; i <= scan_channels; i++){
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*(channel_list + i - 1) = i;
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*(pscan_config + i - 1) = PSCAN_ENABLE;
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};
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if(wifi_set_pscan_chan(channel_list, pscan_config, scan_channels) < 0){
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printf("ERROR: wifi set partial scan channel fail\n");
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} else if(wifi_scan_networks(_scan_result_handler, NULL ) != RTW_SUCCESS){
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printf("ERROR: wifi scan failed\n");
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} else {
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i = 300;
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while(i-- && scan_end) {
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vTaskDelay(10);
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};
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};
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vPortFree(channel_list);
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} else {
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printf("ERROR: Can't malloc memory for channel list\n");
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};
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}
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MON_RAM_TAB_SECTION COMMAND_TABLE console_cmd_wifi_api[] = {
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{"ATPN", 1, fATPN, "=<SSID>[,password[,encryption[,auto-reconnect[,reconnect pause]]]: WIFI Connect to AP"},
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{"ATPA", 1, fATPA, "=<SSID>[,password[,encryption[,channel[,hidden[,max connections]]]]]: Start WIFI AP"},
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{"ATWR", 0, fATWR, ": WIFI Connect, Disconnect"},
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{"ATON", 0, fATON, ": Open connections"},
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{"ATOF", 0, fATOF, ": Close connections"},
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{"ATWI", 0, fATWI, ": WiFi Info"},
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#if CONFIG_DEBUG_LOG > 3
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{"ATWT", 1, fATWT, "=<tx_power>: WiFi tx power: 0 - 100%, 1 - 75%, 2 - 50%, 3 - 25%, 4 - 12.5%"},
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{"ATSF", 0, fATSF, ": Test TSF value"},
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#endif
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{"ATSN", 0, fATSN, ": Scan networks"}
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};
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@ -7,11 +7,13 @@
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#ifndef _WIFI_API_H_
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#define _WIFI_API_H_
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#include "wifi_constants.h"
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#include "wifi_conf.h"
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#define ip4_addr1(ipaddr) (((u8_t*)(ipaddr))[0])
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#define ip4_addr2(ipaddr) (((u8_t*)(ipaddr))[1])
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#define ip4_addr3(ipaddr) (((u8_t*)(ipaddr))[2])
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#define ip4_addr4(ipaddr) (((u8_t*)(ipaddr))[3])
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#define ip4_addr1(ipaddr) (((uint8_t*)(ipaddr))[0])
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#define ip4_addr2(ipaddr) (((uint8_t*)(ipaddr))[1])
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#define ip4_addr3(ipaddr) (((uint8_t*)(ipaddr))[2])
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#define ip4_addr4(ipaddr) (((uint8_t*)(ipaddr))[3])
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#define IPSTR "%d.%d.%d.%d"
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@ -97,6 +99,19 @@ typedef struct _dhcp_config {
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unsigned char mode; // =0 dhcp off, =1 - dhcp on, =2 Static ip, =3 - auto
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} DHCP_CONFIG, *PDHCP_CONFIG;
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extern WIFI_CONFIG wifi_cfg;
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extern SOFTAP_CONFIG wifi_ap_cfg;
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extern DHCP_CONFIG wifi_ap_dhcp;
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extern STATION_CONFIG wifi_st_cfg;
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extern DHCP_CONFIG wifi_st_dhcp;
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extern rtw_mode_t wifi_run_mode;
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extern char wlan_st_name[];
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extern char wlan_ap_name[];
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extern char wlan_st_netifn;
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extern char wlan_ap_netifn;
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void show_wifi_ap_ip(void);
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void show_wifi_st_ip(void);
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void show_wifi_cfg(void);
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@ -105,6 +120,8 @@ void show_wifi_ap_cfg(void);
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uint32 read_wifi_cfg(uint32 flg);
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uint32 write_wifi_cfg(uint32 flg);
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int wifi_run(rtw_mode_t mode);
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void wifi_init_thrd(void);
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void wifi_init(void);
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void _LwIP_Init(void);
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#endif // _WIFI_API_H_
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@ -374,8 +374,8 @@ void NETBIOS_CODE_ATTR netbios_init(void) {
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for(int i = 0; i < NET_IF_NUM; i++) {
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os_printf("%d: '%s' ", i, netbios_name[i]);
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}
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os_printf("\n");
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#endif
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pcb = udp_new();
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if (pcb != NULL) {
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/* we have to be allowed to send broadcast packets! */
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@ -12,27 +12,27 @@
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/*
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* in hal_platform.h
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#define GPIO_REG_BASE 0x40001000
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#define BITBAND_REG_BASE 0x40001000
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*/
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/*
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* in rtl8195a_gpio.h
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*
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#define GPIO_PORTA_DR 0x00 // data register
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#define GPIO_PORTA_DDR 0x04 // data direction
|
||||
#define GPIO_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
|
||||
#define BITBAND_PORTA_DR 0x00 // data register
|
||||
#define BITBAND_PORTA_DDR 0x04 // data direction
|
||||
#define BITBAND_PORTA_CTRL 0x08 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define GPIO_PORTB_DR 0x0c // data register
|
||||
#define GPIO_PORTB_DDR 0x10 // data direction
|
||||
#define GPIO_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
|
||||
#define BITBAND_PORTB_DR 0x0c // data register
|
||||
#define BITBAND_PORTB_DDR 0x10 // data direction
|
||||
#define BITBAND_PORTB_CTRL 0x14 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define GPIO_PORTC_DR 0x18 // data register
|
||||
#define GPIO_PORTC_DDR 0x1c // data direction
|
||||
#define GPIO_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
|
||||
#define BITBAND_PORTC_DR 0x18 // data register
|
||||
#define BITBAND_PORTC_DDR 0x1c // data direction
|
||||
#define BITBAND_PORTC_CTRL 0x20 // data source control, we should keep it as default: data source from software
|
||||
|
||||
#define GPIO_EXT_PORTA 0x50 // GPIO IN read or OUT read back
|
||||
#define GPIO_EXT_PORTB 0x54 // GPIO IN read or OUT read back
|
||||
#define GPIO_EXT_PORTC 0x58 // GPIO IN read or OUT read back
|
||||
#define BITBAND_EXT_PORTA 0x50 // GPIO IN read or OUT read back
|
||||
#define BITBAND_EXT_PORTB 0x54 // GPIO IN read or OUT read back
|
||||
#define BITBAND_EXT_PORTC 0x58 // GPIO IN read or OUT read back
|
||||
*/
|
||||
|
||||
#define BITBAND_PERI_REF 0x40000000
|
||||
|
|
@ -41,106 +41,106 @@
|
|||
#define ucBITBAND_PERI(a,b) *((volatile unsigned char *)BITBAND_PERI(a,b))
|
||||
#define uiBITBAND_PERI(a,b) *((volatile unsigned int *)BITBAND_PERI(a,b))
|
||||
|
||||
#define GPIO_A0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,0) //Port = 0, bit = 0, A0
|
||||
#define GPIO_A1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,1) //Port = 0, bit = 1, A1
|
||||
#define GPIO_A2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,0) //Port = 1, bit = 0, A2
|
||||
#define GPIO_A3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,1) //Port = 1, bit = 1, A3
|
||||
#define GPIO_A4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,2) //Port = 1, bit = 2, A4
|
||||
#define GPIO_A5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,3) //Port = 1, bit = 3, A5
|
||||
#define GPIO_A6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,4) //Port = 1, bit = 4, A6
|
||||
#define GPIO_A7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,5) //Port = 1, bit = 5, A7
|
||||
#define BITBAND_A0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,0) //Port = 0, bit = 0, A0
|
||||
#define BITBAND_A1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,1) //Port = 0, bit = 1, A1
|
||||
#define BITBAND_A2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,0) //Port = 1, bit = 0, A2
|
||||
#define BITBAND_A3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,1) //Port = 1, bit = 1, A3
|
||||
#define BITBAND_A4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,2) //Port = 1, bit = 2, A4
|
||||
#define BITBAND_A5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,3) //Port = 1, bit = 3, A5
|
||||
#define BITBAND_A6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,4) //Port = 1, bit = 4, A6
|
||||
#define BITBAND_A7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,5) //Port = 1, bit = 5, A7
|
||||
|
||||
#define GPIO_B0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,6) //Port = 1, bit = 6, B0
|
||||
#define GPIO_B1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,7) //Port = 1, bit = 7, B1
|
||||
#define GPIO_B2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,8) //Port = 1, bit = 8, B2
|
||||
#define GPIO_B3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,2) //Port = 0, bit = 2, B3
|
||||
#define GPIO_B4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,3) //Port = 0, bit = 3, B4
|
||||
#define GPIO_B5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,9) //Port = 1, bit = 9, B5
|
||||
#define GPIO_B6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 0, bit = 4, B6
|
||||
#define GPIO_B7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,5) //Port = 0, bit = 5, B7
|
||||
#define BITBAND_B0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,6) //Port = 1, bit = 6, B0
|
||||
#define BITBAND_B1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,7) //Port = 1, bit = 7, B1
|
||||
#define BITBAND_B2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,8) //Port = 1, bit = 8, B2
|
||||
#define BITBAND_B3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,2) //Port = 0, bit = 2, B3
|
||||
#define BITBAND_B4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,3) //Port = 0, bit = 3, B4
|
||||
#define BITBAND_B5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,9) //Port = 1, bit = 9, B5
|
||||
#define BITBAND_B6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 0, bit = 4, B6
|
||||
#define BITBAND_B7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,5) //Port = 0, bit = 5, B7
|
||||
|
||||
#define GPIO_C0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,10) //Port = 1, bit = 10, C0
|
||||
#define GPIO_C1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,6) //Port = 0, bit = 6, C1
|
||||
#define GPIO_C2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,11) //Port = 1, bit = 11, C2
|
||||
#define GPIO_C3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,7) //Port = 0, bit = 7, C3
|
||||
#define GPIO_C4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,8) //Port = 0, bit = 8, C4
|
||||
#define GPIO_C5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,9) //Port = 0, bit = 9, C5
|
||||
#define GPIO_C6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,10) //Port = 0, bit = 10, C6
|
||||
#define GPIO_C7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,11) //Port = 0, bit = 11, C7
|
||||
#define GPIO_C8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,12) //Port = 0, bit = 12, C8
|
||||
#define GPIO_C9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,13) //Port = 0, bit = 13, C9
|
||||
#define BITBAND_C0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,10) //Port = 1, bit = 10, C0
|
||||
#define BITBAND_C1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,6) //Port = 0, bit = 6, C1
|
||||
#define BITBAND_C2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,11) //Port = 1, bit = 11, C2
|
||||
#define BITBAND_C3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,7) //Port = 0, bit = 7, C3
|
||||
#define BITBAND_C4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,8) //Port = 0, bit = 8, C4
|
||||
#define BITBAND_C5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,9) //Port = 0, bit = 9, C5
|
||||
#define BITBAND_C6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,10) //Port = 0, bit = 10, C6
|
||||
#define BITBAND_C7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,11) //Port = 0, bit = 11, C7
|
||||
#define BITBAND_C8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,12) //Port = 0, bit = 12, C8
|
||||
#define BITBAND_C9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,13) //Port = 0, bit = 13, C9
|
||||
|
||||
#define GPIO_D0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,12) //Port = 1, bit = 12, D0
|
||||
#define GPIO_D1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,14) //Port = 0, bit = 14, D1
|
||||
#define GPIO_D2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,13) //Port = 1, bit = 13, D2
|
||||
#define GPIO_D3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,15) //Port = 0, bit = 15, D3
|
||||
#define GPIO_D4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,16) //Port = 0, bit = 16, D4
|
||||
#define GPIO_D5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,17) //Port = 0, bit = 17, D5
|
||||
#define GPIO_D6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,18) //Port = 0, bit = 18, D6
|
||||
#define GPIO_D7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,19) //Port = 0, bit = 19, D7
|
||||
#define GPIO_D8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,14) //Port = 1, bit = 14, D8
|
||||
#define GPIO_D9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,20) //Port = 0, bit = 20, D9
|
||||
#define BITBAND_D0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,12) //Port = 1, bit = 12, D0
|
||||
#define BITBAND_D1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,14) //Port = 0, bit = 14, D1
|
||||
#define BITBAND_D2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,13) //Port = 1, bit = 13, D2
|
||||
#define BITBAND_D3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,15) //Port = 0, bit = 15, D3
|
||||
#define BITBAND_D4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,16) //Port = 0, bit = 16, D4
|
||||
#define BITBAND_D5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,17) //Port = 0, bit = 17, D5
|
||||
#define BITBAND_D6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,18) //Port = 0, bit = 18, D6
|
||||
#define BITBAND_D7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,19) //Port = 0, bit = 19, D7
|
||||
#define BITBAND_D8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,14) //Port = 1, bit = 14, D8
|
||||
#define BITBAND_D9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,20) //Port = 0, bit = 20, D9
|
||||
|
||||
#define GPIO_E0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, E0
|
||||
#define GPIO_E1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,21) //Port = 0, bit = 21, E1
|
||||
#define GPIO_E2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,22) //Port = 0, bit = 22, E2
|
||||
#define GPIO_E3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,23) //Port = 0, bit = 23, E3
|
||||
#define GPIO_E4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,16) //Port = 1, bit = 16, E4
|
||||
#define GPIO_E5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,24) //Port = 0, bit = 24, E5
|
||||
#define GPIO_E6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,25) //Port = 0, bit = 25, E6
|
||||
#define GPIO_E7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,26) //Port = 0, bit = 26, E7
|
||||
#define GPIO_E8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,27) //Port = 0, bit = 27, E8
|
||||
#define GPIO_E9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,17) //Port = 1, bit = 17, E9
|
||||
#define GPIO_E10 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,18) //Port = 1, bit = 17, E10
|
||||
#define BITBAND_E0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, E0
|
||||
#define BITBAND_E1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,21) //Port = 0, bit = 21, E1
|
||||
#define BITBAND_E2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,22) //Port = 0, bit = 22, E2
|
||||
#define BITBAND_E3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,23) //Port = 0, bit = 23, E3
|
||||
#define BITBAND_E4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,16) //Port = 1, bit = 16, E4
|
||||
#define BITBAND_E5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,24) //Port = 0, bit = 24, E5
|
||||
#define BITBAND_E6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,25) //Port = 0, bit = 25, E6
|
||||
#define BITBAND_E7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,26) //Port = 0, bit = 26, E7
|
||||
#define BITBAND_E8 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,27) //Port = 0, bit = 27, E8
|
||||
#define BITBAND_E9 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,17) //Port = 1, bit = 17, E9
|
||||
#define BITBAND_E10 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,18) //Port = 1, bit = 17, E10
|
||||
|
||||
#define GPIO_F0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,19) //Port = 1, bit = 19, F0
|
||||
#define GPIO_F1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,20) //Port = 1, bit = 20, F1
|
||||
#define GPIO_F2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,21) //Port = 1, bit = 21, F2
|
||||
#define GPIO_F3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,22) //Port = 1, bit = 22, F3
|
||||
#define GPIO_F4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,23) //Port = 1, bit = 23, F4
|
||||
#define GPIO_F5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,24) //Port = 1, bit = 24, F5
|
||||
#define BITBAND_F0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,19) //Port = 1, bit = 19, F0
|
||||
#define BITBAND_F1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,20) //Port = 1, bit = 20, F1
|
||||
#define BITBAND_F2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,21) //Port = 1, bit = 21, F2
|
||||
#define BITBAND_F3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,22) //Port = 1, bit = 22, F3
|
||||
#define BITBAND_F4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,23) //Port = 1, bit = 23, F4
|
||||
#define BITBAND_F5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,24) //Port = 1, bit = 24, F5
|
||||
|
||||
#define GPIO_G0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,25) //Port = 1, bit = 25, G0
|
||||
#define GPIO_G1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,26) //Port = 1, bit = 26, G1
|
||||
#define GPIO_G2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,27) //Port = 1, bit = 27, G2
|
||||
#define GPIO_G3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,28) //Port = 0, bit = 28, G3
|
||||
#define GPIO_G4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,28) //Port = 1, bit = 28, G4
|
||||
#define GPIO_G5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,29) //Port = 1, bit = 29, G5
|
||||
#define GPIO_G6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,30) //Port = 1, bit = 30, G6
|
||||
#define GPIO_G7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,31) //Port = 1, bit = 31, G7
|
||||
#define BITBAND_G0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,25) //Port = 1, bit = 25, G0
|
||||
#define BITBAND_G1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,26) //Port = 1, bit = 26, G1
|
||||
#define BITBAND_G2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,27) //Port = 1, bit = 27, G2
|
||||
#define BITBAND_G3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,28) //Port = 0, bit = 28, G3
|
||||
#define BITBAND_G4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,28) //Port = 1, bit = 28, G4
|
||||
#define BITBAND_G5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,29) //Port = 1, bit = 29, G5
|
||||
#define BITBAND_G6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,30) //Port = 1, bit = 30, G6
|
||||
#define BITBAND_G7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTB_DR,31) //Port = 1, bit = 31, G7
|
||||
|
||||
#define GPIO_H0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,0) //Port = 2, bit = 0, H0
|
||||
#define GPIO_H1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,29) //Port = 0, bit = 29, H1
|
||||
#define GPIO_H2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,1) //Port = 2, bit = 1, H2
|
||||
#define GPIO_H3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,30) //Port = 0, bit = 30, H3
|
||||
#define GPIO_H4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,2) //Port = 2, bit = 2, H4
|
||||
#define GPIO_H5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,31) //Port = 0, bit = 31, H5
|
||||
#define GPIO_H6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,3) //Port = 2, bit = 3, H6
|
||||
#define GPIO_H7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 2, bit = 4, H7
|
||||
#define BITBAND_H0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,0) //Port = 2, bit = 0, H0
|
||||
#define BITBAND_H1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,29) //Port = 0, bit = 29, H1
|
||||
#define BITBAND_H2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,1) //Port = 2, bit = 1, H2
|
||||
#define BITBAND_H3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,30) //Port = 0, bit = 30, H3
|
||||
#define BITBAND_H4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,2) //Port = 2, bit = 2, H4
|
||||
#define BITBAND_H5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,31) //Port = 0, bit = 31, H5
|
||||
#define BITBAND_H6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,3) //Port = 2, bit = 3, H6
|
||||
#define BITBAND_H7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTA_DR,4) //Port = 2, bit = 4, H7
|
||||
|
||||
#define GPIO_I0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,5) //Port = 2, bit = 5, I0
|
||||
#define GPIO_I1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,6) //Port = 2, bit = 6, I1
|
||||
#define GPIO_I2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,7) //Port = 2, bit = 7, I2
|
||||
#define GPIO_I3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,8) //Port = 2, bit = 8, I3
|
||||
#define GPIO_I4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,9) //Port = 2, bit = 9, I4
|
||||
#define GPIO_I5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,10) //Port = 2, bit = 10, I5
|
||||
#define GPIO_I6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,11) //Port = 2, bit = 11, I6
|
||||
#define GPIO_I7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,12) //Port = 2, bit = 12, I7
|
||||
#define BITBAND_I0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,5) //Port = 2, bit = 5, I0
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#define BITBAND_I1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,6) //Port = 2, bit = 6, I1
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#define BITBAND_I2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,7) //Port = 2, bit = 7, I2
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#define BITBAND_I3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,8) //Port = 2, bit = 8, I3
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#define BITBAND_I4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,9) //Port = 2, bit = 9, I4
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#define BITBAND_I5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,10) //Port = 2, bit = 10, I5
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#define BITBAND_I6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,11) //Port = 2, bit = 11, I6
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#define BITBAND_I7 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,12) //Port = 2, bit = 12, I7
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#define GPIO_J0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,13) //Port = 2, bit = 13, J0
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#define GPIO_J1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,14) //Port = 2, bit = 14, J1
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#define GPIO_J2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, J2
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#define GPIO_J3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,16) //Port = 2, bit = 16, J3
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#define GPIO_J4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,17) //Port = 2, bit = 17, J4
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#define GPIO_J5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,18) //Port = 2, bit = 18, J5
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#define GPIO_J6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,19) //Port = 2, bit = 19, J6
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#define BITBAND_J0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,13) //Port = 2, bit = 13, J0
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#define BITBAND_J1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,14) //Port = 2, bit = 14, J1
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#define BITBAND_J2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,15) //Port = 2, bit = 15, J2
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#define BITBAND_J3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,16) //Port = 2, bit = 16, J3
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#define BITBAND_J4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,17) //Port = 2, bit = 17, J4
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#define BITBAND_J5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,18) //Port = 2, bit = 18, J5
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#define BITBAND_J6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,19) //Port = 2, bit = 19, J6
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#define GPIO_K0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,20) //Port = 2, bit = 20, K0
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#define GPIO_K1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,21) //Port = 2, bit = 21, K1
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#define GPIO_K2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,22) //Port = 2, bit = 22, K2
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#define GPIO_K3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,23) //Port = 2, bit = 23, K3
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#define GPIO_K4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,24) //Port = 2, bit = 24, K4
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#define GPIO_K5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,25) //Port = 2, bit = 25, K5
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#define GPIO_K6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,26) //Port = 2, bit = 26, K6
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#define BITBAND_K0 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,20) //Port = 2, bit = 20, K0
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#define BITBAND_K1 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,21) //Port = 2, bit = 21, K1
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#define BITBAND_K2 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,22) //Port = 2, bit = 22, K2
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#define BITBAND_K3 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,23) //Port = 2, bit = 23, K3
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#define BITBAND_K4 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,24) //Port = 2, bit = 24, K4
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#define BITBAND_K5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,25) //Port = 2, bit = 25, K5
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#define BITBAND_K6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,26) //Port = 2, bit = 26, K6
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|
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#endif // _BITBAND_IO_H_
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|
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Loading…
Add table
Add a link
Reference in a new issue