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fix & update

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pvvx 2017-02-01 14:57:01 +03:00
parent 0557a41f1a
commit 741520fa66
58 changed files with 6620 additions and 6810 deletions
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2
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h
View file

@ -945,7 +945,7 @@ enum SDIO_RPWM2_BITS {
RPWM2_PIN_C7_LV_BIT = BIT8, // GPIO C7 wakeup level
RPWM2_PIN_D5_LV_BIT = BIT9, // GPIO D5 wakeup level
RPWM2_PIN_E3_LV_BIT = BIT10, // GPIO E3 wakeup level
RPWM2_CG_BIT = BIT11, // Clock Gated
RPWM2_CG_BIT = BIT11, // Clock Gated
RPWM2_ACK_BIT = BIT14, // Acknowledge
RPWM2_TOGGLE_BIT = BIT15, // Toggle bit
};

18
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio_host.h
View file

@ -273,15 +273,15 @@ typedef enum
/* 0x2C */
typedef enum
{
BASE_CLK = 0x00,
BASE_CLK_DIVIDED_BY_2 = 0x01,
BASE_CLK_DIVIDED_BY_4 = 0x02,
BASE_CLK_DIVIDED_BY_8 = 0x04,
BASE_CLK_DIVIDED_BY_16 = 0x08,
BASE_CLK_DIVIDED_BY_32 = 0x10,
BASE_CLK_DIVIDED_BY_64 = 0x20,
BASE_CLK_DIVIDED_BY_128 = 0x40,
BASE_CLK_DIVIDED_BY_256 = 0x80
BASE_CLK = 0x00, // 41.6 MHz
BASE_CLK_DIVIDED_BY_2 = 0x01, // 20.8 MHz
BASE_CLK_DIVIDED_BY_4 = 0x02, // 10.4 MHz
BASE_CLK_DIVIDED_BY_8 = 0x04, // 5.2 MHZ
BASE_CLK_DIVIDED_BY_16 = 0x08, // 2.6 MHz
BASE_CLK_DIVIDED_BY_32 = 0x10, // 1.3 MHz
BASE_CLK_DIVIDED_BY_64 = 0x20, // 650 kHz
BASE_CLK_DIVIDED_BY_128 = 0x40, // 325 kHz
BASE_CLK_DIVIDED_BY_256 = 0x80 // 162 kHz
}SD_CLK_DIVISOR;
typedef enum

2
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c
View file

@ -41,7 +41,7 @@ HalGdmaChBlockSetingRtl8195a_Patch(
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
DBG_GDMA_WARN("Channel had used; Disable Channel!\n");
HalGdmaChDisRtl8195a(Data);

18
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c
View file

@ -221,7 +221,7 @@ HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
#ifdef CONFIG_PCM_EN
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
@ -243,7 +243,7 @@ HalPcmIsrEnAndDisRtl8195a (
}
}
*/
#endif
return _TRUE;
}
@ -254,14 +254,14 @@ HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
#ifdef CONFIG_PCM_EN
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
#endif
return _TRUE;
}
@ -270,16 +270,18 @@ HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
#ifdef CONFIG_PCM_EN
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
#endif
return _TRUE;
}
/*
#ifdef CONFIG_PCM_EN
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
@ -354,6 +356,6 @@ HalGdmaChCleanAutoDstRtl8195a (
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/
#endif // CONFIG_PCM_EN

3821
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_sdio_host.c
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File diff suppressed because it is too large Load diff

3
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
View file

@ -14,8 +14,7 @@
extern _LONG_CALL_
HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
extern _LONG_CALL_
u32 HalGetCpuClk(VOID);
//extern _LONG_CALL_ u32 HalGetCpuClk(VOID);
VOID _SsiReadInterruptRtl8195a(VOID *Adapter)