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fix & update

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This commit is contained in:
pvvx 2017-02-01 14:57:01 +03:00
parent 0557a41f1a
commit 741520fa66
58 changed files with 6620 additions and 6810 deletions
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2
RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmFunc.h
View file

@ -309,7 +309,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
// #include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

2
RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/core_cmInstr.h
View file

@ -295,7 +295,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
// #include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/

6
RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/rtl_stdlib.h
View file

@ -21,14 +21,14 @@
#define strcmp(str1, str2) prvStrCmp((const u8*)str1, (const u8*)str2)
#define sscanf(src, format...) //TODO
#define strtok(str, delim) prvStrTok(str, delim)
#define strcpy(dst, src) prvStrCpy((u8 *)dst, (const u8*)src)
#define strcpy(dst, src) prvStrCpy((u8 *)dst, (const u8*)src)
#define atoi(str) prvAtoi(str)
#define strstr(str1, str2) prvStrStr(str1, str2)
#define strstr(str1, str2) prvStrStr(str1, str2)
//
// standard i/o
//
#define snprintf DiagSnPrintf
#define snprintf DiagSnPrintf
#define sprintf prvDiagSPrintf
#define printf prvDiagPrintf

3
RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/strproc.h
View file

@ -79,7 +79,7 @@ extern _LONG_CALL_ROM_ const char * prvStrStr(
IN const char * str2
);
#ifndef __GNUC__
/*
* Fast implementation of tolower() for internal usage. Do not use in your
* code.
@ -88,6 +88,7 @@ static inline char _tolower(const char c)
{
return c | 0x20;
}
#endif
/* Fast check for octal digit */
static inline int isodigit(const char c)

2
RTL00_SDKV35a/component/soc/realtek/8195a/cmsis/device/system_8195a.c
View file

@ -49,7 +49,7 @@
#define __SYSTEM_CLOCK (200000000UL/6*5) // PLATFORM_CLOCK //
extern unsigned int rand_x;
extern u32 HalGetCpuClk(VOID);
//extern u32 HalGetCpuClk(VOID);
#ifdef CONFIG_CHIP_A_CUT
const u32 SysCpkClkTbl[]= {

20
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gdma.h
View file

@ -58,17 +58,17 @@ typedef struct _HAL_GDMA_ADAPTER_ {
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
typedef struct _HAL_GDMA_CHNL_ {

2
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gpio.h
View file

@ -244,7 +244,7 @@ HAL_GPIO_IP_DeInit(
extern u16 GPIOState[_PORT_MAX-1]; // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на переферию.
extern u16 GPIOState[_PORT_MAX-1]; // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию.
#endif // end of "#define _HAL_GPIO_H_"

7
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_misc.h
View file

@ -31,11 +31,12 @@ enum _HAL_RESET_REASON{
typedef u32 HAL_RESET_REASON;
#ifdef CONFIG_TIMER_MODULE
extern _LONG_CALL_ u32 HalDelayUs(u32 us);
extern _LONG_CALL_ unsigned int HalDelayUs(unsigned int us);
#endif
extern _LONG_CALL_ u32 HalGetCpuClk(VOID);
extern _LONG_CALL_ u8 HalGetRomInfo(VOID);
extern _LONG_CALL_ unsigned int HalGetCpuClk(VOID);
extern _LONG_CALL_ unsigned char HalGetRomInfo(VOID);
extern u8 HalGetChipId(void);
extern _LONG_CALL_ROM_ void *_memset( void *s, int c, SIZE_T n );
extern _LONG_CALL_ROM_ void *_memcpy( void *s1, const void *s2, SIZE_T n );

22
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_sdio_host.h
View file

@ -14,11 +14,9 @@
#include "rtl8195a_sdio_host.h"
#define SDIO_HOST_WAIT_FOREVER 0xFFFFFFFF
typedef struct _HAL_SDIO_HOST_OP_ {
HAL_Status (*HalSdioHostInitHost) (VOID *Data);
HAL_Status (*HalSdioHostInitCard) (VOID *Data);
@ -48,20 +46,20 @@ typedef enum _SDIO_XFER_TYPE_{
}SDIO_XFER_TYPE;
typedef struct _HAL_SDIO_HOST_ADAPTER_{
IRQ_HANDLE IrqHandle; // Irq Handler
ADMA2_DESC_FMT *AdmaDescTbl;
u32 Response[4];
u32 CardOCR;
u32 CardStatus;
u32 IsWriteProtect;
u8 SdStatus[SD_STATUS_LEN];
u8 Csd[CSD_REG_LEN];
IRQ_HANDLE IrqHandle; //+0..6(u32) Irq Handler
ADMA2_DESC_FMT *AdmaDescTbl; //+7(u32)
u32 Response[4]; //+8..11(u32)
u32 CardOCR; //+12
u32 CardStatus; //+13
u32 IsWriteProtect; //+14
u8 SdStatus[SD_STATUS_LEN]; //+15..
u8 Csd[CSD_REG_LEN]; //+31
volatile u8 CmdCompleteFlg;
volatile u8 XferCompleteFlg;
volatile u8 ErrIntFlg;
volatile u8 CardCurState;
u8 IsSdhc;
u8 CurrSdClk;
u8 CurrSdClk; //+133?
u16 RCA;
u16 SdSpecVer;
SDIO_ERR_TYPE errType;
@ -76,6 +74,7 @@ typedef struct _HAL_SDIO_HOST_ADAPTER_{
VOID *CardRemoveCbPara;
}HAL_SDIO_HOST_ADAPTER, *PHAL_SDIO_HOST_ADAPTER;
extern HAL_SDIO_HOST_ADAPTER SdioHostAdapter;
extern HAL_Status
HalSdioHostInit(
@ -102,6 +101,5 @@ HalSdioHostOpInit(
IN VOID *Data
);
#endif

36
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_spi_flash.h
View file

@ -55,6 +55,7 @@ enum _SPIC_BIT_MODE_ {
SpicOneBitMode = 0,
SpicDualBitMode = 1,
SpicQuadBitMode = 2,
SpicMaxMode = 3
};
//======================================================
@ -98,20 +99,22 @@ enum _SPIC_BIT_MODE_ {
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
/*Micron Special command*/
#define FLASH_CMD_DE 0xC4
#define FLASH_CMD_4PP2 0x12
#define FLASH_CMD_RFSR 0x70
#define FLASH_CMD_CFSR 0x50
#define FLASH_CMD_RNCR 0xB5
#define FLASH_CMD_WNCR 0xB1
#define FLASH_CMD_RVCR 0x85
#define FLASH_CMD_WVCR 0x81
#define FLASH_CMD_REVCR 0x65
#define FLASH_CMD_WEVCR 0x61
#define FLASH_CMD_REAR 0xC8
#define FLASH_CMD_WEAR 0xC5
#define FLASH_CMD_ENQUAD 0x35
#define FLASH_CMD_EXQUAD 0xF5
#define FLASH_CMD_DE 0xC4 // DIE ERASE
#define FLASH_CMD_4PP2 0x12 // 4-BYTE PAGE PROGRAM
#define FLASH_CMD_RFSR 0x70 // READ FLAG STATUS REGISTER
#define FLASH_CMD_CFSR 0x50 // CLEAR FLAG STATUS REGISTER
#define FLASH_CMD_RNCR 0xB5 // READ NONVOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_WNCR 0xB1 // WRITE NONVOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_RVCR 0x85 // READ VOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_WVCR 0x81 // WRITE VOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_REVCR 0x65 // READ ENHANCED VOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_WEVCR 0x61 // WRITE ENHANCED VOLATILE CONFIGURATION REGISTER
#define FLASH_CMD_REAR 0xC8 // READ EXTENDED ADDRESS REGISTER
#define FLASH_CMD_WEAR 0xC5 // WRITE EXTENDED ADDRESS REGISTER
#define FLASH_CMD_ENQUAD 0x35 // ENTER QUAD
#define FLASH_CMD_EXQUAD 0xF5 // EXIT QUAD
#define FLASH_CMD_ROTPA 0x4B // READ OTP ARRAY
#define FLASH_CMD_POTPA 0x42 // PROGRAM OTP ARRAY
/*MXIC Special command*/
#define FLASH_CMD_RDCR 0x15 //read configurate register
@ -120,7 +123,10 @@ enum _SPIC_BIT_MODE_ {
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
/* EON Special command*/
#define FLASH_CMD_EOTPM 0x3A // Enter OTP Mode (3Ah)
//#endif
#if 0

7
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/ram_lib/startup.c
View file

@ -202,7 +202,6 @@ void __attribute__((section(".hal.ram.text"))) RtlBootToSram(void) {
SpicInitRtl8195A(1, 1); // InitBaudRate 1, SpicBitMode 1
SpicFlashInitRtl8195A(1); // SpicBitMode 1
DBG_8195A("===== Enter Image 1.5 ====\nImg2 Sign: %s, InfaStart @ 0x%08x\n",
&__image2_validate_code__, __image2_entry_func__);
if (strcmp((const char * )&__image2_validate_code__, "RTKWin")) {
@ -313,7 +312,7 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
HalDelayUs(1000);
int sdr_enable = 0;
#ifdef CONFIG_SDR_EN
if ((chip_id + 5) > 2) {
if (chip_id > CHIP_ID_8711AF) {
SdrCtrlInit();
sdr_enable = 1;
}
@ -335,7 +334,9 @@ void __attribute__((section(".hal.ram.text"))) PreProcessForVendor(void) {
SpicReadIDRtl8195A();
SpicFlashInitRtl8195A(SpicDualBitMode); // SpicBitMode 1
}
// if (sdr_enable) SdrControllerInit();
#ifdef CONFIG_SDR_EN
if (sdr_enable) SdrControllerInit();
#endif
if (flash_enable) {
u32 img1size = (*(u16 *) (SPI_FLASH_BASE + 0x18)) << 10; // size in 1024 bytes
if (img1size == 0 || img1size >= 0x3FFFC00)

2
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio.h
View file

@ -945,7 +945,7 @@ enum SDIO_RPWM2_BITS {
RPWM2_PIN_C7_LV_BIT = BIT8, // GPIO C7 wakeup level
RPWM2_PIN_D5_LV_BIT = BIT9, // GPIO D5 wakeup level
RPWM2_PIN_E3_LV_BIT = BIT10, // GPIO E3 wakeup level
RPWM2_CG_BIT = BIT11, // Clock Gated
RPWM2_CG_BIT = BIT11, // Clock Gated
RPWM2_ACK_BIT = BIT14, // Acknowledge
RPWM2_TOGGLE_BIT = BIT15, // Toggle bit
};

18
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_sdio_host.h
View file

@ -273,15 +273,15 @@ typedef enum
/* 0x2C */
typedef enum
{
BASE_CLK = 0x00,
BASE_CLK_DIVIDED_BY_2 = 0x01,
BASE_CLK_DIVIDED_BY_4 = 0x02,
BASE_CLK_DIVIDED_BY_8 = 0x04,
BASE_CLK_DIVIDED_BY_16 = 0x08,
BASE_CLK_DIVIDED_BY_32 = 0x10,
BASE_CLK_DIVIDED_BY_64 = 0x20,
BASE_CLK_DIVIDED_BY_128 = 0x40,
BASE_CLK_DIVIDED_BY_256 = 0x80
BASE_CLK = 0x00, // 41.6 MHz
BASE_CLK_DIVIDED_BY_2 = 0x01, // 20.8 MHz
BASE_CLK_DIVIDED_BY_4 = 0x02, // 10.4 MHz
BASE_CLK_DIVIDED_BY_8 = 0x04, // 5.2 MHZ
BASE_CLK_DIVIDED_BY_16 = 0x08, // 2.6 MHz
BASE_CLK_DIVIDED_BY_32 = 0x10, // 1.3 MHz
BASE_CLK_DIVIDED_BY_64 = 0x20, // 650 kHz
BASE_CLK_DIVIDED_BY_128 = 0x40, // 325 kHz
BASE_CLK_DIVIDED_BY_256 = 0x80 // 162 kHz
}SD_CLK_DIVISOR;
typedef enum

2
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_gdma.c
View file

@ -41,7 +41,7 @@ HalGdmaChBlockSetingRtl8195a_Patch(
//4 1) Check chanel is avaliable
if (HAL_GDMAX_READ32(GdmaIndex, REG_GDMA_CH_EN) & ChEn) {
//4 Disable Channel
DBG_GDMA_WARN("Channel had used; Disable Channel!!!!\n");
DBG_GDMA_WARN("Channel had used; Disable Channel!\n");
HalGdmaChDisRtl8195a(Data);

18
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_pcm.c
View file

@ -221,7 +221,7 @@ HalPcmIsrEnAndDisRtl8195a (
IN VOID *Data
)
{
/*
#ifdef CONFIG_PCM_EN
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
u32 IsrMask, Addr, IsrCtrl;
u8 IsrTypeIndex = 0;
@ -243,7 +243,7 @@ HalPcmIsrEnAndDisRtl8195a (
}
}
*/
#endif
return _TRUE;
}
@ -254,14 +254,14 @@ HalPcmDumpRegRtl8195a (
IN VOID *Data
)
{
/*
#ifdef CONFIG_PCM_EN
PHAL_GDMA_ADAPTER pHalGdmaAdapter = Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)|
(pHalGdmaAdapter->ChEn))
);
*/
#endif
return _TRUE;
}
@ -270,16 +270,18 @@ HalPcmRtl8195a (
IN VOID *Data
)
{
/* PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
#ifdef CONFIG_PCM_EN
PHAL_GDMA_ADAPTER pHalGdmaAdapter = (PHAL_GDMA_ADAPTER) Data;
HAL_GDMAX_WRITE32(pHalGdmaAdapter->GdmaIndex,
REG_GDMA_CH_EN,
(HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, REG_GDMA_CH_EN)&
~(pHalGdmaAdapter->ChEn))
);
*/
#endif
return _TRUE;
}
/*
#ifdef CONFIG_PCM_EN
u8
HalGdmaChIsrCleanRtl8195a (
IN VOID *Data
@ -354,6 +356,6 @@ HalGdmaChCleanAutoDstRtl8195a (
HAL_GDMAX_READ32(pHalGdmaAdapter->GdmaIndex, (REG_GDMA_CH_CFG + pHalGdmaAdapter->ChNum*REG_GDMA_CH_OFF)));
}
*/
#endif // CONFIG_PCM_EN

3821
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_sdio_host.c
View file

File diff suppressed because it is too large Load diff

3
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_ssi.c
View file

@ -14,8 +14,7 @@
extern _LONG_CALL_
HAL_Status HalSsiInitRtl8195a(VOID *Adaptor);
extern _LONG_CALL_
u32 HalGetCpuClk(VOID);
//extern _LONG_CALL_ u32 HalGetCpuClk(VOID);
VOID _SsiReadInterruptRtl8195a(VOID *Adapter)

5
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_adc.c
View file

@ -1228,10 +1228,7 @@ RtkADCReceive(
return _EXIT_FAILURE;
}
extern u32
HalDelayUs(
IN u32 us
);
//extern u32 HalDelayUs(IN u32 us);
u32
RtkADCReceiveBuf(

10
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_misc.c
View file

@ -56,4 +56,14 @@ HAL_RESET_REASON HalGetResetCause(void)
return HAL_PERI_ON_READ32(REG_SYS_DSLP_TIM_CTRL);
}
u8 HalGetChipId(void) {
u8 chip_id = CHIP_ID_8195AM;
#if CONFIG_DEBUG_LOG > 3
if (HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8, &chip_id, L25EOUTVOLTAGE) != 1)
DBG_MISC_INFO("Get Chip ID Failed\r");
#else
HALEFUSEOneByteReadROM(HAL_SYS_CTRL_READ32(REG_SYS_EFUSE_CTRL), 0xF8, &chip_id, L25EOUTVOLTAGE);
#endif
return chip_id;
}

1
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pcm.c
View file

@ -8,6 +8,7 @@
*/
#include "platform_autoconf.h"
#include "hal_pcm.h"
#ifdef CONFIG_PCM_EN

3
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_pinmux.c
View file

@ -30,6 +30,7 @@ void HalJtagPinOff(void)
HalPinCtrlRtl8195A(JTAG, 0, 0);
}
#if RTL8710_DEF_PIN_ON
//----- GpioIcFunChk
@ -45,7 +46,7 @@ u8 GpioIcFunChk(IN u32 chip_pin, IN u8 Operation)
if (tst & 0xEF) result = 1;
else {
result = tst & 0x10;
if(tst & 0x10) { // RTL8710AF ?
if(result) { // RTL8710AF ?
if (chip_pin - 1 <= 2) result = 0; // PA_1, PA_2, PA_3
else {
result = chip_pin - PC_5; // PC_5

20
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdio_host.c
View file

@ -4,12 +4,17 @@
* RTL8710/11 pvvx 12/2016
*/
#include "rtl8195a.h"
#ifdef CONFIG_SDIO_HOST_EN
#include "sd.h"
#include "sdio_host.h"
#include "hal_sdio_host.h"
#include "rtl8195a_sdio_host.h"
#include "hal_pinmux.h"
//#ifdef RTL8710AF
#include "hal_gpio.h"
#include "PinNames.h"
#include "hal_gpio.h"
//#endif
//-------------------------------------------------------------------------
// Function declarations
@ -107,4 +112,17 @@ void HalSdioHostOpInit(void *Data) {
phsha->HalSdioHostErase = &HalSdioHostEraseRtl8195a;
phsha->HalSdioHostGetWriteProtect = &HalSdioHostGetWriteProtectRtl8195a;
phsha->HalSdioHostSetWriteProtect = &HalSdioHostSetWriteProtectRtl8195a;
//#ifdef RTL8710AF
if(HalGetChipId() != CHIP_ID_8195AM) {
GPIOState[0] &= ~((1 << 8) - 1);
{
for (int i = 0; i <= 6; i++)
HAL_GPIO_PullCtrl(i, PullNone);
HAL_GPIO_PullCtrl(PA_6, PullDown);
HAL_GPIO_PullCtrl(PA_7, PullDown);
}
}
//#endif
}
#endif // CONFIG_SDIO_HOST_EN

4
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_sdr_controller.c
View file

@ -1047,7 +1047,7 @@ MemTest(
} // MemTest
#if defined ( __ICCARM__ )
//#if defined ( __ICCARM__ )
u8 IsSdrPowerOn(
VOID
)
@ -1058,7 +1058,7 @@ u8 IsSdrPowerOn(
return 1;
}
}
#endif
//#endif
#else // ifndef CONFIG_SDR_EN

4
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_soc_ps_monitor.c
View file

@ -22,8 +22,8 @@ extern void xPortPendSVHandler( void ) __attribute__ (( naked ));
#endif
extern void xPortSysTickHandler( void );
extern void vPortSVCHandler( void );
extern u32 HalGetCpuClk(VOID);
extern _LONG_CALL_ u32 HalDelayUs(u32 us);
//extern unsigned int HalGetCpuClk(void);
//extern _LONG_CALL_ u32 HalDelayUs(u32 us);
extern COMMAND_TABLE UartLogRomCmdTable[];
extern HAL_TIMER_OP HalTimerOp;

2158
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_spi_flash_ram.c
View file

File diff suppressed because it is too large Load diff

BIN
RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/lib_platform_new.a
View file

Binary file not shown.

1
RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/lib_platform_new.bat
View file

@ -13,6 +13,7 @@ del hal_log_uart.o
del hal_pinmux.o
del hal_misc.o
del startup.o
rem del hal_spi_flash_ram.o
arm-none-eabi-ar.exe ru ..\%libname%_new.a *.o
cd ..
rd /q /s %libname%.lib

2
RTL00_SDKV35a/component/soc/realtek/8195a/misc/bsp/lib/common/GCC/rlx8195A-symbol-v03-img2.ld
View file

@ -27,7 +27,7 @@ SECTIONS
{
__rom_bss_start__ = 0x10000300;
__rom_bss_end__ = 0x10000bc8;
/*
.ram.start.table :
{