update

RTL00_SDKV35a/component/common/example/example_entry.c

@@ -303,7 +303,7 @@ void example_entry(void)
 #endif   
 
 #if CONFIG_EXAMPLE_MEDIA_AUDIO_FROM_RTP
-        example_media_audio_from_rtp();
+    example_media_audio_from_rtp();
 #endif     
         
 #if CONFIG_EXAMPLE_AUDIO_MP3

RTL00_SDKV35a/component/common/mbed/hal_ext/serial_ex_api.h

@@ -46,8 +46,8 @@ int32_t serial_send_stream_abort (serial_t *obj);
 int32_t serial_recv_stream_abort (serial_t *obj);
 void serial_disable (serial_t *obj);
 void serial_enable (serial_t *obj);
-int32_t serial_recv_stream_timeout (serial_t *obj, char *prxbuf, uint32_t \
+int32_t serial_recv_stream_timeout (serial_t *obj, char *prxbuf, \
-    len, uint32_t timeout_ms, void *force_cs);
+	uint32_t len, uint32_t timeout_ms, void *force_cs);
 int32_t serial_recv_stream_dma_timeout (serial_t *obj, char *prxbuf, \
     uint32_t len, uint32_t timeout_ms, void *force_cs);
 

RTL00_SDKV35a/component/common/utilities/uart_socket.c

@@ -150,8 +150,8 @@ Exit:
 
 uart_socket_t* uart_open(uart_set_str *puartpara)
 {
-	PinName uart_tx = PA_7;//PA_4; //PA_7
+	PinName uart_tx = PA_7; //PA_4; //PA_7
-	PinName uart_rx = PA_6;//PA_0; //PA_6
+	PinName uart_rx = PA_6; //PA_0; //PA_6
 	uart_socket_t *u;
 
 	u = (uart_socket_t *)RtlZmalloc(sizeof(uart_socket_t));

RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/bitband_io.h

@@ -10,34 +10,12 @@
 #define BITBAND_SRAM_BASE 0x12000000
 #define BITBAND_SRAM(a,b) (BITBAND_SRAM_BASE + (a-BITBAND_SRAM_REF)*32 + (b*4)) // Convert SRAM address
 
-/*
+#define BITBAND_ADDR(a,b)	(0x02000000 + (a & 0xF0000000) + (a - (a & 0xF0000000)) * 32 + ((b) * 4))	// Convert address ?
- * in hal_platform.h
-#define BITBAND_REG_BASE		0x40001000
- */
-
-/*
- * in rtl8195a_gpio.h
- *
-#define BITBAND_PORTA_DR           0x00        // data register
-#define BITBAND_PORTA_DDR          0x04        // data direction
-#define BITBAND_PORTA_CTRL         0x08        // data source control, we should keep it as default: data source from software
-
-#define BITBAND_PORTB_DR           0x0c        // data register
-#define BITBAND_PORTB_DDR          0x10        // data direction
-#define BITBAND_PORTB_CTRL         0x14        // data source control, we should keep it as default: data source from software
-
-#define BITBAND_PORTC_DR           0x18        // data register
-#define BITBAND_PORTC_DDR          0x1c        // data direction
-#define BITBAND_PORTC_CTRL         0x20        // data source control, we should keep it as default: data source from software
-
-#define BITBAND_EXT_PORTA          0x50        // GPIO IN read or OUT read back
-#define BITBAND_EXT_PORTB          0x54        // GPIO IN read or OUT read back
-#define BITBAND_EXT_PORTC          0x58        // GPIO IN read or OUT read back
-*/
 
 #define BITBAND_PERI_REF	0x40000000
 #define BITBAND_PERI_BASE	0x42000000
-#define BITBAND_PERI(a,b)	(BITBAND_PERI_BASE + (a-BITBAND_PERI_REF)*32 + (b*4))	// Convert PERI address
+#define BITBAND_PERI(a,b)	(BITBAND_PERI_BASE + (a - BITBAND_PERI_REF) * 32 + ((b) * 4))	// Convert PERI address
+
 #define ucBITBAND_PERI(a,b)	*((volatile unsigned char *)BITBAND_PERI(a,b))
 #define uiBITBAND_PERI(a,b) *((volatile unsigned int *)BITBAND_PERI(a,b))
 
@@ -143,4 +121,10 @@
 #define BITBAND_K5 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,25)  //Port = 2, bit = 25, K5
 #define BITBAND_K6 ucBITBAND_PERI(GPIO_REG_BASE+GPIO_PORTC_DR,26)  //Port = 2, bit = 26, K6
 
+volatile u8 * BitBandAddr(void *addr, u8 bit);
+volatile u8 * BitBandPeriAddr(void *addr, u8 bit);
+volatile u8 * GetOutPinBitBandAddr(PinName pin);
+volatile u8 * GetInpPinBitBandAddr(PinName pin);
+volatile u8 * HardSetPin(PinName pin, PinDirection pdir, PinMode pmode, u8 val);
+
 #endif // _BITBAND_IO_H_

RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_gpio.h

@@ -242,8 +242,6 @@ HAL_GPIO_IP_DeInit(
     VOID
 );
 
-
-
 extern u16 GPIOState[_PORT_MAX]; // побитно 16 бит для каждого порта (A..K), бит=номер задействованного пина в порту на периферию.
 
 #endif  // end of "#define _HAL_GPIO_H_"

RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/hal_uart.h

@@ -45,35 +45,35 @@ typedef struct _UART_DMA_CONFIG_ {
 }UART_DMA_CONFIG, *PUART_DMA_CONFIG;
 
 typedef struct _HAL_RUART_ADAPTER_ {
-    u32 BaudRate;
+    u32 BaudRate;		//+0
-    u32 FlowControl;
+    u32 FlowControl;	//+4
-    u32 FifoControl;
+    u32 FifoControl;	//+8
-    u32 Interrupts;
+    u32 Interrupts;		//+12
-    u32 TxCount;     // how many byte to TX
+    u32 TxCount;     //+16 how many byte to TX
-    u32 RxCount;     // how many bytes to RX
+    u32 RxCount;     //+20 how many bytes to RX
-    u8 *pTxBuf;
+    u8 *pTxBuf;		//+24
-    u8 *pRxBuf;
+    u8 *pRxBuf;		//+28
-    HAL_UART_State State;       // UART state
+    HAL_UART_State State;       //+32 UART state
-    u8 Status;      // Transfer Status
+    u8 Status;      //+36 Transfer Status
-    u8 Locked;      // is UART locked for operation
+    u8 Locked;      //+37 is UART locked for operation
-    u8 UartIndex;
+    u8 UartIndex;	//+38
-    u8 WordLen;     // word length select: 0 -> 7 bits, 1 -> 8 bits
+    u8 WordLen;     //+39 word length select: 0 -> 7 bits, 1 -> 8 bits
-    u8 StopBit;     // word length select: 0 -> 1 stop bit, 1 -> 2 stop bit
+    u8 StopBit;     //+40 word length select: 0 -> 1 stop bit, 1 -> 2 stop bit
-    u8 Parity;      // parity check enable
+    u8 Parity;      //+41 parity check enable
-    u8 ParityType;  // parity check type
+    u8 ParityType;  //+42 parity check type
-    u8 StickParity;
+    u8 StickParity;	//+43
-    u8 ModemStatus; // the modem status
+    u8 ModemStatus; //+44 the modem status
     u8 DmaEnable;
     u8 TestCaseNumber;
     u8 PinmuxSelect;
     BOOL PullMode;
     IRQ_HANDLE IrqHandle;
     PUART_DMA_CONFIG DmaConfig;
-    VOID (*ModemStatusInd)(VOID *pAdapter);    // modem status indication interrupt handler
+    VOID (*ModemStatusInd)(VOID *pAdapter);    //+72 modem status indication interrupt handler
-    VOID (*TxTDCallback)(VOID *pAdapter);      // User Tx Done callback function
+    VOID (*TxTDCallback)(VOID *pAdapter);      //+76 User Tx Done callback function
-    VOID (*RxDRCallback)(VOID *pAdapter);      // User Rx Data ready callback function
+    VOID (*RxDRCallback)(VOID *pAdapter);      //+80 User Rx Data ready callback function
-    VOID (*TxCompCallback)(VOID *para);    // User Tx complete callback function
+    VOID (*TxCompCallback)(VOID *para);    	//+84 User Tx complete callback function
-    VOID (*RxCompCallback)(VOID *para);    // User Rx complete callback function
+    VOID (*RxCompCallback)(VOID *para);    	//+88 User Rx complete callback function
     VOID *TxTDCbPara;   // the pointer agrument for TxTDCallback
     VOID *RxDRCbPara;   // the pointer agrument for RxDRCallback
     VOID *TxCompCbPara; // the pointer argument for TxCompCbPara

RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h

@@ -261,6 +261,14 @@ GPIO_Int_SetType_8195a(
     u8 int_mode
 );
 
+_LONG_CALL_ VOID
+GPIO_Int_Mask_8195a(
+		u8 pin_num,
+		u8 En
+);
+
+_LONG_CALL_ u32 GPIO_FuncOn_8195a(VOID);
+_LONG_CALL_ u32 GPIO_FuncOff_8195a(VOID);
 
 _LONG_CALL_  HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN  *GPIO_Pin, u32 En);
 _LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr);

RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h

@@ -57,17 +57,17 @@ typedef enum {
 #define RUART_FIFO_CTL_REG_OFF          0x08    //[W]
 // Define FIFO Control Register Bits
 typedef enum {
-	RU_FCR_FIFO_EN      = BIT0,   // FIFO Enable.
+	RU_FCR_FIFO_EN      = BIT0,   		// FIFO Enable.
-	RU_FCR_RST_RX       = BIT1,   // RCVR FIFO Reset, self clear
+	RU_FCR_RST_RX       = BIT1,   		// RCVR FIFO Reset, self clear
-	RU_FCR_RST_TX       = BIT2,   // XMIT FIFO Reset, self clear
+	RU_FCR_RST_TX       = BIT2,   		// XMIT FIFO Reset, self clear
-	RU_FCR_TX_TRIG_EMP  = 0,        // TX Empty Trigger: FIFO empty
+	RU_FCR_TX_TRIG_EMP  = 0,        	// TX Empty Trigger: FIFO empty
-	RU_FCR_TX_TRIG_2CH  = BIT4,   // TX Empty Trigger: 2 characters in the FIFO
+	RU_FCR_TX_TRIG_2CH  = BIT4,   		// TX Empty Trigger: 2 characters in the FIFO
-	RU_FCR_TX_TRIG_QF   = BIT5,   // TX Empty Trigger: FIFO 1/4 full
+	RU_FCR_TX_TRIG_QF   = BIT5,   		// TX Empty Trigger: FIFO 1/4 full
-	RU_FCR_TX_TRIG_HF   = (BIT5|BIT4),   // TX Empty Trigger: FIFO 1/2 full
+	RU_FCR_TX_TRIG_HF   = (BIT5|BIT4),  // TX Empty Trigger: FIFO 1/2 full
-	RU_FCR_TX_TRIG_MASK = (BIT5|BIT4),   // TX Empty Trigger Bit Mask
+	RU_FCR_TX_TRIG_MASK = (BIT5|BIT4),  // TX Empty Trigger Bit Mask
-	RU_FCR_RX_TRIG_1CH  = 0,        // RCVR Trigger: 1 character in the FIFO
+	RU_FCR_RX_TRIG_1CH  = 0,        	// RCVR Trigger: 1 character in the FIFO
-	RU_FCR_RX_TRIG_QF   = BIT6,   // RCVR Trigger: FIFO 1/4 full
+	RU_FCR_RX_TRIG_QF   = BIT6,   		// RCVR Trigger: FIFO 1/4 full
-	RU_FCR_RX_TRIG_HF   = BIT7,   // RCVR Trigger: FIFO 1/2 full
+	RU_FCR_RX_TRIG_HF   = BIT7,   		// RCVR Trigger: FIFO 1/2 full
 	RU_FCR_RX_TRIG_AF   = (BIT7|BIT6),  // RCVR Trigger: FIFO 2 less than full
 	RU_FCR_RX_TRIG_MASK = (BIT7|BIT6)   // RCVR Trigger bits Mask
 } RUART_FIFO_CTRL;
@@ -92,7 +92,7 @@ typedef enum {
 #define RUART_LINE_CTL_REG_OFF          0x0C
 // Define Line Control Register Bits
 typedef enum {
-	RU_LCR_DLS_5B = 0,      			// Data Length: 5 bits
+	RU_LCR_DLS_5B = 0,      		// Data Length: 5 bits
 	RU_LCR_DLS_6B = BIT0,      		// Data Length: 6 bits
 	RU_LCR_DLS_7B = BIT1,      		// Data Length: 7 bits
 	RU_LCR_DLS_8B = (BIT1|BIT0),   	// Data Length: 7 bits
@@ -101,11 +101,11 @@ typedef enum {
 	RU_LCR_STOP_2B = BIT2,		// Number of stop bits: 1.5(data len=5) or 2
 
 	RU_LCR_PARITY_NONE = 0,     		// Parity Enable: 0
-	RU_LCR_PARITY_ODD = BIT3,      	// Parity Enable: 1, Even Parity: 0
+	RU_LCR_PARITY_ODD = BIT3,      		// Parity Enable: 1, Even Parity: 0
 	RU_LCR_PARITY_EVEN = (BIT4|BIT3),	// Parity Enable: 1, Even Parity: 1
 
 	RU_LCR_BC = BIT6, 	    	// Break Control Bit
-	RU_LCR_DLAB = BIT7     	// Divisor Latch Access Bit
+	RU_LCR_DLAB = BIT7     		// Divisor Latch Access Bit
 } RUART_LINE_CTRL;
 //*BIT6 Break Control Bit (BC)
 //*BIT4 Even Parity Select (EPS)
@@ -154,11 +154,11 @@ typedef enum {
 #define RUART_SP_REG_XFACTOR_ADJ        (0x7FF<<16)  //[26:16]
 
 #define RUART_STS_REG_OFF               0x20
-#define RUART_STS_REG_RESET_RCV         BIT3  //BIT3, 0x08, Reset Uart Receiver
+#define RUART_STS_REG_RESET_RCV         BIT3  // BIT3, 0x08, Reset Uart Receiver
 #define RUART_STS_REG_XFACTOR           0xF<<4
 
-#define RUART_REV_BUF_REG_OFF           0x24  //Receiver Buffer Register
+#define RUART_REV_BUF_REG_OFF           0x24  // Receiver Buffer Register
-#define RUART_TRAN_HOLD_REG_OFF         0x24  //Transmitter Holding Register
+#define RUART_TRAN_HOLD_REG_OFF         0x24  // Transmitter Holding Register
 
 #define RUART_MISC_CTL_REG_OFF          0x28
 #define RUART_TXDMA_BURSTSIZE_MASK      0xF8    //7:3

RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c

@@ -1248,7 +1248,7 @@ HalRuartMultiBlkDmaRecvRtl8195a(
 }
 
 /**
- * Stop non-blocking UART TX
+ * Stop non-blocking UART RX
  *
  *
  * @return VOID

RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/Descript.ion

@@ -1,7 +0,0 @@
-hal_common.c +
-hal_efuse.c +
-hal_misc.c +
-hal_pinmux.c +
-hal_sdio_host.c +
-hal_soc_ps_monitor.c +
-hal_spi_flash_ram.c +

RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/bitband_io.c

@@ -0,0 +1,55 @@
+
+#include "PinNames.h"
+#include "bitband_io.h"
+
+volatile u8 * BitBandAddr(void *addr, u8 bit) {
+	return (volatile u8 *)(BITBAND_ADDR((u32)addr, bit));
+}
+
+volatile u8 * BitBandPeriAddr(void *addr, u8 bit) {
+	return (volatile u8 *)(BITBAND_PERI((u32)addr, bit));
+}
+
+volatile u8 * GetOutPinBitBandAddr(PinName pin) {
+	u32 paddr = NULL;
+	u32 ippin = HAL_GPIO_GetIPPinName_8195a(pin);
+	if(ippin != 0xff) {
+		// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
+		paddr =  BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)),  ippin & 0x1f);
+	}
+	return paddr;
+}
+
+volatile u8 * GetInPinBitBandAddr(PinName pin) {
+	volatile u8 * paddr = NULL;
+	u32 ippin = HAL_GPIO_GetIPPinName_8195a(pin);
+	if(ippin != 0xff) {
+		// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
+		paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_EXT_PORTA + (ippin >> 5) * 4),  ippin & 0x1f);
+	}
+	return paddr;
+}
+
+volatile u8 * HardSetPin(PinName pin, PinDirection pdir, PinMode pmode, u8 val)
+{
+	volatile u8 *paddr = NULL;
+	u32 ippin = HAL_GPIO_GetIPPinName_8195a(pin);
+	if(ippin != 0xff) {
+		// paddr = 0x42000000 + (0x40001000 + 0x0c * (ippin >> 5) - 0x40000000) * 32 + ((ippin & 0x1f) * 4);
+		paddr = BitBandPeriAddr((void *)(GPIO_REG_BASE + GPIO_PORTB_DR * (ippin >> 5)),  ippin & 0x1f);
+	}
+	if(paddr && _pHAL_Gpio_Adapter) {
+		if (_pHAL_Gpio_Adapter->Gpio_Func_En == 0)  GPIO_FuncOn_8195a();
+		paddr[0] = val;						// data register
+		paddr[(GPIO_PORTB_DDR - GPIO_PORTB_DR) * 32] = pdir;	// data direction
+#if 1 // if use HAL_Gpio_Adapter
+		uint32 * p = &_pHAL_Gpio_Adapter->Local_Gpio_Dir[ippin >> 5];
+		if(pdir) *p |= 1 << (ippin & 0x1f);
+		else *p &= ~(1 << (ippin & 0x1f));
+#endif
+		paddr[(GPIO_PORTB_CTRL - GPIO_PORTB_DR) * 32] = 0;		// data source control, we should keep it as default: data source from software
+		HAL_GPIO_PullCtrl_8195a(pin, pmode);				// set GPIO_PULL_CTRLx
+	}
+	return paddr;
+}
+

RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/src/hal_gpio.c

@@ -14,8 +14,6 @@
 HAL_GPIO_ADAPTER gHAL_Gpio_Adapter;
 extern PHAL_GPIO_ADAPTER _pHAL_Gpio_Adapter;
 
-extern VOID GPIO_PullCtrl_8195a(u32 chip_pin, u8 pull_type);
-
 /**
   * @brief  To get the GPIO IP Pin name for the given chip pin name
   *
@@ -203,5 +201,4 @@ HAL_GPIO_DeInit(
     GpioFunctionChk(chip_pin, DISABLE);
 }
 
-
 #endif // CONFIG_GPIO_EN

RTL00_SDKV35a/sdkset.mk

@@ -232,6 +232,7 @@ SRC_C += sdk/component/common/mbed/targets/hal/rtl8195a/flash_eep.c
 endif
 
 #peripheral - hal
+SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/bitband_io.c
 SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_32k.c
 SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_adc.c
 SRC_C += sdk/component/soc/realtek/8195a/fwlib/src/hal_gdma.c