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pvvx 2017-06-14 10:21:20 +03:00
parent fd4c492ea4
commit 5cbdd7eea5
19 changed files with 2308 additions and 2272 deletions
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8
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_gpio.h
View file

@ -261,6 +261,14 @@ GPIO_Int_SetType_8195a(
u8 int_mode
);
_LONG_CALL_ VOID
GPIO_Int_Mask_8195a(
u8 pin_num,
u8 En
);
_LONG_CALL_ u32 GPIO_FuncOn_8195a(VOID);
_LONG_CALL_ u32 GPIO_FuncOff_8195a(VOID);
_LONG_CALL_ HAL_Status HAL_GPIO_IntCtrl_8195aV02(HAL_GPIO_PIN *GPIO_Pin, u32 En);
_LONG_CALL_ u32 GPIO_Int_Clear_8195aV02(u32 irq_clr);

34
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/rtl8195a_uart.h
View file

@ -57,17 +57,17 @@ typedef enum {
#define RUART_FIFO_CTL_REG_OFF 0x08 //[W]
// Define FIFO Control Register Bits
typedef enum {
RU_FCR_FIFO_EN = BIT0, // FIFO Enable.
RU_FCR_RST_RX = BIT1, // RCVR FIFO Reset, self clear
RU_FCR_RST_TX = BIT2, // XMIT FIFO Reset, self clear
RU_FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty
RU_FCR_TX_TRIG_2CH = BIT4, // TX Empty Trigger: 2 characters in the FIFO
RU_FCR_TX_TRIG_QF = BIT5, // TX Empty Trigger: FIFO 1/4 full
RU_FCR_TX_TRIG_HF = (BIT5|BIT4), // TX Empty Trigger: FIFO 1/2 full
RU_FCR_TX_TRIG_MASK = (BIT5|BIT4), // TX Empty Trigger Bit Mask
RU_FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO
RU_FCR_RX_TRIG_QF = BIT6, // RCVR Trigger: FIFO 1/4 full
RU_FCR_RX_TRIG_HF = BIT7, // RCVR Trigger: FIFO 1/2 full
RU_FCR_FIFO_EN = BIT0, // FIFO Enable.
RU_FCR_RST_RX = BIT1, // RCVR FIFO Reset, self clear
RU_FCR_RST_TX = BIT2, // XMIT FIFO Reset, self clear
RU_FCR_TX_TRIG_EMP = 0, // TX Empty Trigger: FIFO empty
RU_FCR_TX_TRIG_2CH = BIT4, // TX Empty Trigger: 2 characters in the FIFO
RU_FCR_TX_TRIG_QF = BIT5, // TX Empty Trigger: FIFO 1/4 full
RU_FCR_TX_TRIG_HF = (BIT5|BIT4), // TX Empty Trigger: FIFO 1/2 full
RU_FCR_TX_TRIG_MASK = (BIT5|BIT4), // TX Empty Trigger Bit Mask
RU_FCR_RX_TRIG_1CH = 0, // RCVR Trigger: 1 character in the FIFO
RU_FCR_RX_TRIG_QF = BIT6, // RCVR Trigger: FIFO 1/4 full
RU_FCR_RX_TRIG_HF = BIT7, // RCVR Trigger: FIFO 1/2 full
RU_FCR_RX_TRIG_AF = (BIT7|BIT6), // RCVR Trigger: FIFO 2 less than full
RU_FCR_RX_TRIG_MASK = (BIT7|BIT6) // RCVR Trigger bits Mask
} RUART_FIFO_CTRL;
@ -92,7 +92,7 @@ typedef enum {
#define RUART_LINE_CTL_REG_OFF 0x0C
// Define Line Control Register Bits
typedef enum {
RU_LCR_DLS_5B = 0, // Data Length: 5 bits
RU_LCR_DLS_5B = 0, // Data Length: 5 bits
RU_LCR_DLS_6B = BIT0, // Data Length: 6 bits
RU_LCR_DLS_7B = BIT1, // Data Length: 7 bits
RU_LCR_DLS_8B = (BIT1|BIT0), // Data Length: 7 bits
@ -101,11 +101,11 @@ typedef enum {
RU_LCR_STOP_2B = BIT2, // Number of stop bits: 1.5(data len=5) or 2
RU_LCR_PARITY_NONE = 0, // Parity Enable: 0
RU_LCR_PARITY_ODD = BIT3, // Parity Enable: 1, Even Parity: 0
RU_LCR_PARITY_ODD = BIT3, // Parity Enable: 1, Even Parity: 0
RU_LCR_PARITY_EVEN = (BIT4|BIT3), // Parity Enable: 1, Even Parity: 1
RU_LCR_BC = BIT6, // Break Control Bit
RU_LCR_DLAB = BIT7 // Divisor Latch Access Bit
RU_LCR_DLAB = BIT7 // Divisor Latch Access Bit
} RUART_LINE_CTRL;
//*BIT6 Break Control Bit (BC)
//*BIT4 Even Parity Select (EPS)
@ -154,11 +154,11 @@ typedef enum {
#define RUART_SP_REG_XFACTOR_ADJ (0x7FF<<16) //[26:16]
#define RUART_STS_REG_OFF 0x20
#define RUART_STS_REG_RESET_RCV BIT3 //BIT3, 0x08, Reset Uart Receiver
#define RUART_STS_REG_RESET_RCV BIT3 // BIT3, 0x08, Reset Uart Receiver
#define RUART_STS_REG_XFACTOR 0xF<<4
#define RUART_REV_BUF_REG_OFF 0x24 //Receiver Buffer Register
#define RUART_TRAN_HOLD_REG_OFF 0x24 //Transmitter Holding Register
#define RUART_REV_BUF_REG_OFF 0x24 // Receiver Buffer Register
#define RUART_TRAN_HOLD_REG_OFF 0x24 // Transmitter Holding Register
#define RUART_MISC_CTL_REG_OFF 0x28
#define RUART_TXDMA_BURSTSIZE_MASK 0xF8 //7:3

2
RTL00_SDKV35a/component/soc/realtek/8195a/fwlib/rtl8195a/src/rtl8195a_uart.c
View file

@ -1248,7 +1248,7 @@ HalRuartMultiBlkDmaRecvRtl8195a(
}
/**
* Stop non-blocking UART TX
* Stop non-blocking UART RX
*
*
* @return VOID