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add examples
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25
RTL00_SDKV35a/example_sources/spi_stream_twoboard/readme.txt
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25
RTL00_SDKV35a/example_sources/spi_stream_twoboard/readme.txt
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Example Description
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This example describes how to use SPI stream read/write by mbed api.
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The SPI Interface provides a "Serial Peripheral Interface" Master.
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This interface can be used for communication with SPI slave devices,
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such as FLASH memory, LCD screens and other modules or integrated circuits.
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In this example, we use config SPI_IS_AS_MASTER to decide if device is master or slave.
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If SPI_IS_AS_MASTER is 1, then device is master.
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If SPI_IS_AS_MASTER is 0, then device is slave.
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We connect wires as below:
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master's MOSI (PC_2) connect to slave's MOSI (PC_2)
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master's MISO (PC_3) connect to slave's MISO (PC_3)
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master's SCLK (PC_1) connect to slave's SCLK (PC_1)
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master's CS (PC_0) connect to slave's CS (PC_0)
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This example shows master sends data to slave.
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We bootup slave first, and then bootup master.
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Then log will presents that master sending data to slave.
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To ensure the order is correct, we use a GPIO pin to notify the master that the slave device is ready to write or read data.
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211
RTL00_SDKV35a/example_sources/spi_stream_twoboard/src/main.c
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RTL00_SDKV35a/example_sources/spi_stream_twoboard/src/main.c
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2014 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#include "device.h"
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#include "main.h"
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#include "spi_api.h"
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#include "spi_ex_api.h"
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#define SPI_IS_AS_MASTER 1
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#define TEST_BUF_SIZE 2048
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#define SCLK_FREQ 1000000
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#define SPI_DMA_DEMO 0
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#define TEST_LOOP 100
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#define GPIO_SYNC_PIN PA_1
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// SPI0
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#define SPI0_MOSI PC_2
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#define SPI0_MISO PC_3
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#define SPI0_SCLK PC_1
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#define SPI0_CS PC_0
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_LONG_CALL_ extern
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void __rtl_memDump_v1_00(const u8 *start, u32 size, char * strHeader);
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extern void wait_ms(u32);
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char TestBuf[TEST_BUF_SIZE];
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volatile int MasterTxDone;
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volatile int MasterRxDone;
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volatile int SlaveTxDone;
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volatile int SlaveRxDone;
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gpio_t GPIO_Syc;
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void master_tr_done_callback(void *pdata, SpiIrq event)
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{
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switch(event){
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case SpiRxIrq:
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DBG_8195A("Master RX done!\n");
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MasterRxDone = 1;
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gpio_write(&GPIO_Syc, 0);
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break;
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case SpiTxIrq:
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DBG_8195A("Master TX done!\n");
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MasterTxDone = 1;
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break;
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default:
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DBG_8195A("unknown interrput evnent!\n");
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}
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}
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void slave_tr_done_callback(void *pdata, SpiIrq event)
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{
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switch(event){
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case SpiRxIrq:
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DBG_8195A("Slave RX done!\n");
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SlaveRxDone = 1;
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gpio_write(&GPIO_Syc, 0);
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break;
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case SpiTxIrq:
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DBG_8195A("Slave TX done!\n");
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SlaveTxDone = 1;
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break;
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default:
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DBG_8195A("unknown interrput evnent!\n");
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}
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}
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#if SPI_IS_AS_MASTER
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spi_t spi_master;
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#else
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spi_t spi_slave;
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#endif
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/**
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* @brief Main program.
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* @param None
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* @retval None
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*/
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void main(void)
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{
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int Counter = 0;
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int i;
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gpio_init(&GPIO_Syc, GPIO_SYNC_PIN);
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gpio_write(&GPIO_Syc, 0);//Initialize GPIO Pin to low
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gpio_dir(&GPIO_Syc, PIN_OUTPUT); // Direction: Output
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gpio_mode(&GPIO_Syc, PullNone); // No pull
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#if SPI_IS_AS_MASTER
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spi_init(&spi_master, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
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spi_frequency(&spi_master, SCLK_FREQ);
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spi_format(&spi_master, 16, (SPI_SCLK_IDLE_LOW|SPI_SCLK_TOGGLE_MIDDLE) , 0);
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// wait Slave ready
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while (Counter < TEST_LOOP) {
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DBG_8195A("======= Test Loop %d =======\r\n", Counter);
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for (i=0;i<TEST_BUF_SIZE;i++) {
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TestBuf[i] = i;
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}
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spi_irq_hook(&spi_master, master_tr_done_callback, (uint32_t)&spi_master);
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DBG_8195A("SPI Master Write Test==>\r\n");
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MasterTxDone = 0;
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while(gpio_read(&GPIO_Syc) == 0);
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#if SPI_DMA_DEMO
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spi_master_write_stream_dma(&spi_master, TestBuf, TEST_BUF_SIZE);
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#else
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spi_master_write_stream(&spi_master, TestBuf, TEST_BUF_SIZE);
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#endif
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i=0;
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DBG_8195A("SPI Master Wait Write Done...\r\n");
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while(MasterTxDone == 0) {
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wait_ms(10);
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i++;
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}
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DBG_8195A("SPI Master Write Done!!\r\n");
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DBG_8195A("SPI Master Read Test==>\r\n");
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_memset(TestBuf, 0, TEST_BUF_SIZE);
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spi_flush_rx_fifo(&spi_master);
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MasterRxDone = 0;
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while(gpio_read(&GPIO_Syc) == 0);
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#if SPI_DMA_DEMO
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spi_master_read_stream_dma(&spi_master, TestBuf, TEST_BUF_SIZE);
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#else
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spi_master_read_stream(&spi_master, TestBuf, TEST_BUF_SIZE);
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#endif
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i=0;
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DBG_8195A("SPI Master Wait Read Done...\r\n");
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while(MasterRxDone == 0) {
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wait_ms(10);
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i++;
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}
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DBG_8195A("SPI Master Read Done!!\r\n");
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__rtl_memDump_v1_00(TestBuf, TEST_BUF_SIZE, "SPI Master Read Data:");
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Counter++;
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}
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spi_free(&spi_master);
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DBG_8195A("SPI Master Test <==\r\n");
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#else
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spi_init(&spi_slave, SPI0_MOSI, SPI0_MISO, SPI0_SCLK, SPI0_CS);
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spi_format(&spi_slave, 16, (SPI_SCLK_IDLE_LOW|SPI_SCLK_TOGGLE_MIDDLE) , 1);
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while (spi_busy(&spi_slave)) {
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DBG_8195A("Wait SPI Bus Ready...\r\n");
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wait_ms(1000);
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}
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while (Counter < TEST_LOOP) {
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DBG_8195A("======= Test Loop %d =======\r\n", Counter);
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_memset(TestBuf, 0, TEST_BUF_SIZE);
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DBG_8195A("SPI Slave Read Test ==>\r\n");
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spi_irq_hook(&spi_slave, slave_tr_done_callback, (uint32_t)&spi_slave);
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SlaveRxDone = 0;
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spi_flush_rx_fifo(&spi_slave);
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#if SPI_DMA_DEMO
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spi_slave_read_stream_dma(&spi_slave, TestBuf, TEST_BUF_SIZE);
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#else
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spi_slave_read_stream(&spi_slave, TestBuf, TEST_BUF_SIZE);
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#endif
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gpio_write(&GPIO_Syc, 1);
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i=0;
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DBG_8195A("SPI Slave Wait Read Done...\r\n");
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while(SlaveRxDone == 0) {
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wait_ms(100);
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i++;
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if (i>150) {
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DBG_8195A("SPI Slave Wait Timeout\r\n");
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break;
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}
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}
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__rtl_memDump_v1_00(TestBuf, TEST_BUF_SIZE, "SPI Slave Read Data:");
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// Slave Write Test
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DBG_8195A("SPI Slave Write Test ==>\r\n");
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SlaveTxDone = 0;
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#if SPI_DMA_DEMO
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spi_slave_write_stream_dma(&spi_slave, TestBuf, TEST_BUF_SIZE);
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#else
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spi_slave_write_stream(&spi_slave, TestBuf, TEST_BUF_SIZE);
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#endif
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gpio_write(&GPIO_Syc, 1);
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i=0;
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DBG_8195A("SPI Slave Wait Write Done...\r\n");
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while(SlaveTxDone == 0) {
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wait_ms(100);
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i++;
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if (i> 200) {
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DBG_8195A("SPI Slave Write Timeout...\r\n");
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break;
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}
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}
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DBG_8195A("SPI Slave Write Done!!\r\n");
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Counter++;
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}
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spi_free(&spi_slave);
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#endif
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DBG_8195A("SPI Demo finished.\n");
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for(;;);
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}
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