mirror of
https://github.com/pvvx/RTL00ConsoleROM.git
synced 2024-11-22 10:04:17 +00:00
295 lines
7.1 KiB
C
295 lines
7.1 KiB
C
/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _RTL8195A_SDIO_HOST_H_
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#define _RTL8195A_SDIO_HOST_H_
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#include "hal_api.h"
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#include "osdep_api.h"
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#ifdef CONFIG_SDIO_HOST_VERIFY
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#define HAL_MMC_HOST_READ32(addr) HAL_READ32(SDIO_HOST_REG_BASE, addr)
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#define HAL_MMC_HOST_WRITE32(addr, value) HAL_WRITE32(SDIO_HOST_REG_BASE, addr, value)
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#define HAL_MMC_HOST_READ16(addr) HAL_READ16(SDIO_HOST_REG_BASE, addr)
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#define HAL_MMC_HOST_WRITE16(addr, value) HAL_WRITE16(SDIO_HOST_REG_BASE, addr, value)
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#define HAL_MMC_HOST_READ8(addr) HAL_READ8(SDIO_HOST_REG_BASE, addr)
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#define HAL_MMC_HOST_WRITE8(addr, value) HAL_WRITE8(SDIO_HOST_REG_BASE, addr, value)
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/* RTL8195A Register */
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// REG_SOC_HCI_COM_FUNC_EN (0x214)
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#define SD_DEVICE_IP_ON_BLK BIT0
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#define SD_DEVICE_IP_OFF_BLK BIT1
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#define SD_HOST_IP_BLK BIT2
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// REG_PESOC_HCI_CLK_CTRL0 (0x240)
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#define SD_HOST_CLKEN_IN_CPU_RUN_MODE BIT2
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// REG_HCI_PINMUX_CTRL (0x2A0)
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#define SD_DEVICE_MODE_PINMUX_EN BIT0
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#define SD_HOST_MODE_PINMUX_EN BIT1
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// 0x40059000
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#define SD_HOST_CARD_DETECT_CIRCUIT BIT10
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/* SD Host Register */
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#define REG_SDMA_SYS_ADDR_ARG 0x00 // 4byte
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#define REG_BLOCK_SIZE 0x04 // 2byte
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#define REG_BLOCK_COUNT 0x06 // 2byte
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#define REG_ARGUMENT1 0x08 // 4byte
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#define REG_TRANSFER_MODE 0x0C // 2byte
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#define REG_COMMAND 0x0E // 2byte
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#define REG_RESPONSE0 0x10 // 4byte
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#define REG_RESPONSE2 0x14 // 4byte
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#define REG_RESPONSE4 0x18 // 4byte
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#define REG_RESPONSE6 0x1C // 4byte
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#define REG_BUFFER_DATA_PORT 0x20 // 4byte
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#define REG_PRESENT_STATE 0x24 // 4byte
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#define REG_HOST_CONTROL1 0x28 // 1byte
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#define REG_POWER_CONTROL 0x29 // 1byte
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#define REG_BLOCK_GAP_CONTROL 0x2A // 1byte
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#define REG_WAKEUP_CONTROL 0x2B // 1byte
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#define REG_CLOCK_CONTROL 0x2C // 2byte
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#define REG_TIMEOUT_CONTROL 0x2E // 1byte
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#define REG_SW_RESET 0x2F // 1byte
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#define REG_NORMAL_INT_STATUS 0x30 // 2byte
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#define REG_ERROR_INT_STATUS 0x32 // 2byte
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#define REG_NORMAL_INT_STATUS_ENABLE 0x34 // 2byte
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#define REG_ERROR_INT_STATUS_ENABLE 0x36 // 2byte
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#define REG_NORMAL_INT_SIGNAL_ENABLE 0x38 // 2byte
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#define REG_ERROR_INT_SIGNAL_ENABLE 0x3A // 2byte
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#define REG_CAPABILITIES 0x40 // 8byte
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#define REG_ADMA_ADDRESS 0x58 // 8byte
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// Transfer Mode (0x0C)
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#define BIT_DMA_EN BIT0
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#define BIT_BLK_CNT_EN BIT1
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#define BIT_AUTO_CMD12_EN BIT2
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#define BIT_AUTO_CMD23_EN BIT3
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#define BIT_READ_TRANS BIT4
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#define BIT_MULTI_BLK BIT5
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// Present State (0x24)
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#define BIT_CMD_INHIBIT_CMD BIT0
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#define BIT_CMD_INHIBIT_DAT BIT1
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#define BIT_CARD_INSERTED BIT16
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#define BIT_WRITE_PROTECT_SWITCH_PIN BIT19
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// Power Control (0x29)
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#define BIT_POWER_33 0xE
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#define BIT_POWER_30 0xC
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#define BIT_POWER_18 0xA
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// Clock Control (0x2C)
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#define BIT_INTERNAL_CLK_EN BIT0
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#define BIT_INTERNAL_CLK_STABLE BIT1
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#define BIT_SD_CLK_EN BIT2
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// Software Reset (0x2F)
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#define BIT_SW_RESET_ALL BIT0
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#define BIT_SW_RESET_CMD_LINE BIT1
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#define BIT_SW_RESET_DAT_LINE BIT2
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// Norma Interrupt Status (0x30)
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#define BIT_COMMAND_COMPLETE BIT0
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#define BIT_TRANSFER_COMPLETE BIT1
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#define BIT_BLOCK_GAP_EVENT BIT2
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#define BIT_DMA_INT BIT3
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#define BIT_BUFFER_WRITE_RDY BIT4
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#define BIT_BUFFER_READ_RDY BIT5
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#define BIT_CARD_INSERTION BIT6
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#define BIT_CARD_REMOVAL BIT7
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#define BIT_CARD_INT BIT8
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#define BIT_ERROR_INT BIT15
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// Error Interrupt Status (0x32)
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#define BIT_DATA_TIME_OUT_ERROR BIT4
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#define BIT_DATA_CRC_ERROR BIT5
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#define BIT_ADMA_ERROR BIT9
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// Capabilities (0x40)
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#define BIT_VDD_33 BIT24
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#define BIT_VDD_30 BIT25
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#define BIT_VDD_18 BIT26
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#define ENABLE 1
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#define DISABLE 0
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#define ADMA_DESC_NUM 50
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#define BUFFER_UNIT_SIZE 512
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typedef enum _MMC_HOST_TEST_FUNC_ {
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MMC_HOST_TEST_HW_INIT, // 0
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MMC_HOST_TEST_CARD_INIT, // 1
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MMC_HOST_TEST_SEND_CMD, // 2
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MMC_HOST_TEST_DEBUG, // 3
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MMC_HOST_TEST_SW_RESET, // 4
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MMC_HOST_TEST_READ_SINGLE, // 5
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MMC_HOST_TEST_WRITE_SINGLE, // 6
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MMC_HOST_TEST_READ_MULTI, // 7
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MMC_HOST_TEST_WRITE_MULTI, // 8
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MMC_HOST_TEST_SINGLE_LONGRUN, // 9
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MMC_HOST_TEST_MULTI_LONGRUN, // 10
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MMC_HOST_TEST_CARD_DETECTION, // 11
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MMC_HOST_TEST_WRITE_PROTECT, // 12
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MMC_HOST_TEST_REGISTER_RW // 13
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}MMC_HOST_TEST_FUNC;
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typedef enum _RESPONSE_TYPE_ {
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No_Response, // 00b
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Response_136, // 01b
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Response_48, // 10b
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Response_48_Busy // 11b
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}RESPONSE_TYPE;
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typedef enum _COMMAND_TYPE_ {
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Normal, // 00b
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Suspend, // 01b
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Resume, // 10b
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Abort // 11b
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}COMMAND_TYPE;
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typedef enum _DATA_PRESENT_ {
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No_Data_Present, // 00b
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Data_Present, // 01b
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}DATA_PRESENT;
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typedef enum _SUPPLY_VOLTAGE_ {
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MMC_VDD_27_28 = BIT15,
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MMC_VDD_28_29 = BIT16,
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MMC_VDD_29_30 = BIT17,
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MMC_VDD_30_31 = BIT18,
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MMC_VDD_31_32 = BIT19,
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MMC_VDD_32_33 = BIT20,
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MMC_VDD_33_34 = BIT21,
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MMC_VDD_34_35 = BIT22,
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MMC_VDD_35_36 = BIT23,
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}SUPPLY_VOLTAGE;
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typedef enum _COMMAND_INDEX_ {
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GO_IDLE_STATE = 0,
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ALL_SEND_CID = 2,
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SEND_RELATIVE_ADDR = 3,
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SET_BUS_WIDTH = 6,
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SELECT_CARD = 7,
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SEND_IF_COND = 8,
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SEND_CSD = 9,
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STOP_TRANSMISSION = 12,
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SEND_STATUS = 13,
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READ_SINGLE_BLOCK = 17,
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READ_MULTIPLE_BLOCK = 18,
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WRITE_BLOCK = 24,
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WRITE_MULTIPLE_BLOCK = 25,
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SD_SEND_OP_COND = 41,
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APP_CMD = 55,
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}COMMAND_INDEX;
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typedef enum _TRANSFER_CONFIG_ {
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Read_Data = 0,
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Write_Data = 1,
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Single_Block = 0,
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Multiple_Block = 1,
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}TRANSFER_CONFIG;
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typedef enum _ERROR_STATUS_ {
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General_Error, // 0
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CRC_Error, // 1
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TIME_OUT_ERROR, // 2
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CRC_Error_NeedCMD12, // 3
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Transfer_OK // 4
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}ERROR_STATUS;
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typedef enum _CARD_CURRENT_STATE_ {
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IDLE_STATE,
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READY_STATE,
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IDENT_STATE,
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STBY_STATE,
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TRAN_STATE,
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DATA_STATE,
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RCV_STATE,
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PRG_STATE,
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DIS_STATE,
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UNKNOWN_STATE
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}CARD_CURRENT_STATE;
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typedef struct _COMMAND_FORMAT_
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{
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u16 Resp_Type:2;
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u16 Rsvd0:1;
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u16 CMD_CRC_Chk:1;
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u16 CMD_Idx_Chk:1;
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u16 Data_Present:1;
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u16 CMD_Type:2;
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u16 CMD_Idx:6;
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u16 Rsvd1:2;
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}COMMAND_FORMAT, *PCOMMAND_FPRMAT;
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typedef struct _MMC_COMMAND
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{
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COMMAND_FORMAT Cmd_Format;
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u32 Arg;
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}MMC_COMMAND;
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typedef struct _MMC_HOST_
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{
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u32 OCR_Avail;
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u32 Resp[4];
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u32 CID[4];
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u32 RCA;
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}MMC_HOST, *PMMC_HOST;
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typedef struct _ADMA_ATTR_
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{
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u16 Valid:1;
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u16 End:1;
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u16 Int:1;
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u16 Rsvd1:1;
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u16 Act1:1;
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u16 Act2:1;
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u16 Rsvd2:10;
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}ADMA_ATTR, *PADMA_ATTR;
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// 24 bytes
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typedef struct _ADMA_DESC_TABLE_
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{
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// 1st buffer desc
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ADMA_ATTR Attribute1;
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u16 Length1;
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u32 Address1;
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// 2nd buffer desc
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ADMA_ATTR Attribute2;
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u16 Length2;
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u32 Address2;
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// 3rd buffer desc
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ADMA_ATTR Attribute3;
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u16 Length3;
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u32 Address3;
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}ADMA_DESC_TABLE, *PADMA_DESC_TABLE;
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// 1024 bytes
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typedef struct _ADMA_BUFFER_
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{
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u8 Data1[512]; /* 1st buffer */
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u8 Data2[512]; /* 2nd buffer */
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}ADMA_BUFFER, *PADMA_BUFFER;
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VOID
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SdHostTestApp(
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IN u8 *argv[]
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);
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#endif // end of "#ifdef CONFIG_SDIO_HOST_VERIFY"
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#endif /* #ifndef _RTL8195A_SDIO_HOST_H_ */
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