mirror of
https://github.com/pvvx/RTL00ConsoleROM.git
synced 2024-11-21 17:54:16 +00:00
319 lines
11 KiB
C
319 lines
11 KiB
C
/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _HAL_ADC_H_
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#define _HAL_ADC_H_
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#include "rtl8195a.h"
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#include "rtl8195a_adc.h"
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#include "hal_gdma.h"
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//================ ADC Configuration =========================
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#define ADC_INTR_OP_TYPE 1
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#define ADC_DMA_OP_TYPE 1
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// ADC SAL management macros
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#define SAL_ADC_USER_CB_NUM (sizeof(SAL_ADC_USER_CB) / sizeof(PSAL_ADC_USERCB_ADPT))
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// ADC used module.
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// Please set the ADC module flag to 1 to enable the related
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#define ADC0_USED 1
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#define ADC1_USED 1
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#define ADC2_USED 1
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#define ADC3_USED 1
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//================ Debug MSG Definition =======================
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#define ADC_PREFIX "RTL8195A[adc]: "
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#define ADC_PREFIX_LVL " [ADC_DBG]: "
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typedef enum _ADC_DBG_LVL_ {
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HAL_ADC_LVL = 0x01,
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SAL_ADC_LVL = 0x02,
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VERI_ADC_LVL = 0x04,
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}ADC_DBG_LVL,*PADC_DBG_LVL;
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#ifdef CONFIG_DEBUG_LOG
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#ifdef CONFIG_DEBUG_LOG_ADC_HAL
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#define DBG_8195A_ADC(...) do{ \
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_DbgDump("\r"ADC_PREFIX __VA_ARGS__);\
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}while(0)
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#define ADCDBGLVL 0xFF
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#define DBG_8195A_ADC_LVL(LVL,...) do{\
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if (LVL&ADCDBGLVL){\
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_DbgDump("\r"ADC_PREFIX_LVL __VA_ARGS__);\
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}\
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}while(0)
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#else
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#define DBG_ADC_LOG_PERD 100
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#define DBG_8195A_ADC(...)
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#define DBG_8195A_ADC_LVL(...)
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#endif
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#endif
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//================ ADC HAL Related Enumeration ==================
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// ADC Module Selection
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typedef enum _ADC_MODULE_SEL_ {
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ADC0_SEL = 0x0,
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ADC1_SEL = 0x1,
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ADC2_SEL = 0x2,
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ADC3_SEL = 0x3,
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}ADC_MODULE_SEL,*PADC_MODULE_SEL;
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// ADC module status
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typedef enum _ADC_MODULE_STATUS_ {
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ADC_DISABLE = 0x0,
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ADC_ENABLE = 0x1,
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}ADC_MODULE_STATUS, *PADC_MODULE_STATUS;
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// ADC Data Endian
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typedef enum _ADC_DATA_ENDIAN_ {
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ADC_DATA_ENDIAN_LITTLE = 0x0,
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ADC_DATA_ENDIAN_BIG = 0x1,
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}ADC_DATA_ENDIAN,*PADC_DATA_ENDIAN;
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// ADC Debug Select
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typedef enum _ADC_DEBUG_SEL_ {
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ADC_DBG_SEL_DISABLE = 0x0,
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ADC_DBG_SEL_ENABLE = 0x1,
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}ADC_DEBUG_SEL,*PADC_DEBUG_SEL;
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typedef enum _ADC_COMPARE_SET_ {
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ADC_COMP_SMALLER_THAN = 0x0,
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ADC_COMP_GREATER_THAN = 0x1,
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}ADC_COMPARE_SET, *PADC_COMPARE_SET;
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// ADC feature status
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typedef enum _ADC_FEATURE_STATUS_{
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ADC_FEATURE_DISABLED = 0,
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ADC_FEATURE_ENABLED = 1,
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}ADC_FEATURE_STATUS,*PADC_FEATURE_STATUS;
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// ADC operation type
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typedef enum _ADC_OP_TYPE_ {
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ADC_RDREG_TYPE = 0x0,
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ADC_DMA_TYPE = 0x1,
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ADC_INTR_TYPE = 0x2,
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}ADC_OP_TYPE, *PADC_OP_TYPE;
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// ADC device status
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typedef enum _ADC_DEVICE_STATUS_ {
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ADC_STS_UNINITIAL = 0x00,
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ADC_STS_INITIALIZED = 0x01,
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ADC_STS_IDLE = 0x02,
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ADC_STS_TX_READY = 0x03,
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ADC_STS_TX_ING = 0x04,
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ADC_STS_RX_READY = 0x05,
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ADC_STS_RX_ING = 0x06,
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ADC_STS_ERROR = 0x07,
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ADC_STS_FULL = 0x08,
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}ADC_DEVICE_STATUS, *PADC_DEVICE_STATUS;
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// ADC error type
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typedef enum _ADC_ERR_TYPE_ {
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ADC_ERR_FIFO_RD_ERROR = 0x40, //ADC FIFO read error
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}ADC_ERR_TYPE, *PADC_ERR_TYPE;
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// ADC initial status
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typedef enum _ADC_INITAIL_STATUS_ {
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ADC0_INITED = 0x1,
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ADC1_INITED = 0x2,
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ADC2_INITED = 0x4,
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ADC3_INITED = 0x8,
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}ADC_INITAIL_STATUS, *PADC_INITAIL_STATUS;
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//================ ADC HAL Data Structure ======================
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// ADC HAL initial data structure
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typedef struct _HAL_ADC_INIT_DAT_ {
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u8 ADCIdx; //ADC index used
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u8 ADCEn; //ADC module enable
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u8 ADCEndian; //ADC endian selection,
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//but actually it's for 32-bit ADC data swap control
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//1'b0: no swap,
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//1'b1: swap the upper 16-bit and the lower 16-bit
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u8 ADCBurstSz; //ADC DMA operation threshold
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u8 ADCCompOnly; //ADC compare mode only enable (without FIFO enable)
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u8 ADCOneShotEn; //ADC one-shot mode enable
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u8 ADCOverWREn; //ADC overwrite mode enable
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u8 ADCOneShotTD; //ADC one shot mode threshold
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u16 ADCCompCtrl; //ADC compare mode control,
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//1'b0:less than the compare threshold
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//1'b1:greater than the compare threshod
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u16 ADCCompTD; //ADC compare mode threshold
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u8 ADCDataRate; //ADC down sample data rate,
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u8 ADCAudioEn; //ADC audio mode enable
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u8 ADCEnManul; //ADC enable manually
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u8 ADCDbgSel;
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u32 RSVD0;
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u32 *ADCData; //ADC data pointer
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u32 ADCPWCtrl; //ADC0 power control
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u32 ADCIntrMSK; //ADC Interrupt Mask
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u32 ADCAnaParAd3; //ADC analog parameter 3
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u32 ADCInInput; //ADC Input is internal?
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}HAL_ADC_INIT_DAT,*PHAL_ADC_INIT_DAT;
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// ADC HAL Operations
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typedef struct _HAL_ADC_OP_ {
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RTK_STATUS (*HalADCInit) (VOID *Data); //HAL ADC initialization
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RTK_STATUS (*HalADCDeInit) (VOID *Data); //HAL ADC de-initialization
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RTK_STATUS (*HalADCEnable) (VOID *Data); //HAL ADC de-initialization
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u32 (*HalADCReceive) (VOID *Data); //HAL ADC receive
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RTK_STATUS (*HalADCIntrCtrl) (VOID *Data); //HAL ADC interrupt control
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u32 (*HalADCReadReg) (VOID *Data, u8 ADCReg);//HAL ADC read register
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}HAL_ADC_OP, *PHAL_ADC_OP;
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// ADC user callback adapter
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typedef struct _SAL_ADC_USERCB_ADPT_ {
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VOID (*USERCB) (VOID *Data);
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u32 USERData;
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}SAL_ADC_USERCB_ADPT, *PSAL_ADC_USERCB_ADPT;
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// ADC user callback structure
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typedef struct _SAL_ADC_USER_CB_ {
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PSAL_ADC_USERCB_ADPT pTXCB; //ADC Transmit Callback
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PSAL_ADC_USERCB_ADPT pTXCCB; //ADC Transmit Complete Callback
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PSAL_ADC_USERCB_ADPT pRXCB; //ADC Receive Callback
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PSAL_ADC_USERCB_ADPT pRXCCB; //ADC Receive Complete Callback
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PSAL_ADC_USERCB_ADPT pRDREQCB; //ADC Read Request Callback
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PSAL_ADC_USERCB_ADPT pERRCB; //ADC Error Callback
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PSAL_ADC_USERCB_ADPT pDMATXCB; //ADC DMA Transmit Callback
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PSAL_ADC_USERCB_ADPT pDMATXCCB; //ADC DMA Transmit Complete Callback
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PSAL_ADC_USERCB_ADPT pDMARXCB; //ADC DMA Receive Callback
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PSAL_ADC_USERCB_ADPT pDMARXCCB; //ADC DMA Receive Complete Callback
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}SAL_ADC_USER_CB, *PSAL_ADC_USER_CB;
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// ADC Transmit Buffer
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typedef struct _SAL_ADC_TRANSFER_BUF_ {
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u32 DataLen; //ADC Transmfer Length
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u32 *pDataBuf; //ADC Transfer Buffer Pointer
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u32 RSVD; //
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}SAL_ADC_TRANSFER_BUF,*PSAL_ADC_TRANSFER_BUF;
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typedef struct _SAL_ADC_DMA_USER_DEF_ {
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u8 TxDatSrcWdth;
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u8 TxDatDstWdth;
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u8 TxDatSrcBstSz;
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u8 TxDatDstBstSz;
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u8 TxChNo;
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u8 LlpCtrl;
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u16 RSVD0;
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u32 MaxMultiBlk;
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u32 pLlix;
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u32 pBlockSizeList;
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}SAL_ADC_DMA_USER_DEF, *PSAL_ADC_DMA_USER_DEF;
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// Software API Level ADC Handler
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typedef struct _SAL_ADC_HND_ {
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u8 DevNum; //ADC device number
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u8 PinMux; //ADC pin mux seletion
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u8 OpType; //ADC operation type selection
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volatile u8 DevSts; //ADC device status
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u32 ADCExd; //ADC extended options:
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//bit 0: example
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//bit 31~bit 1: Reserved
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u32 ErrType; //
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u32 TimeOut; //ADC IO Timeout count
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PHAL_ADC_INIT_DAT pInitDat; //Pointer to ADC initial data struct
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PSAL_ADC_TRANSFER_BUF pRXBuf; //Pointer to ADC TX buffer
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PSAL_ADC_USER_CB pUserCB; //Pointer to ADC User Callback
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}SAL_ADC_HND, *PSAL_ADC_HND;
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// ADC SAL handle private
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typedef struct _SAL_ADC_HND_PRIV_ {
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VOID **ppSalADCHnd; //Pointer to SAL_ADC_HND pointer
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SAL_ADC_HND SalADCHndPriv; //Private SAL_ADC_HND
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}SAL_ADC_HND_PRIV, *PSAL_ADC_HND_PRIV;
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//ADC SAL management adapter
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typedef struct _SAL_ADC_MNGT_ADPT_ {
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PSAL_ADC_HND_PRIV pSalHndPriv; //Pointer to SAL_ADC_HND
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PHAL_ADC_INIT_DAT pHalInitDat; //Pointer to HAL ADC initial data( HAL_ADC_INIT_DAT )
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PHAL_ADC_OP pHalOp; //Pointer to HAL ADC operation( HAL_ADC_OP )
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VOID (*pHalOpInit)(VOID*);//Pointer to HAL ADC initialize function
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PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
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VOID (*pSalIrqFunc)(VOID*); //Used for SAL ADC interrupt function
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PSAL_ADC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config
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PHAL_GDMA_ADAPTER pHalGdmaAdp;
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PHAL_GDMA_OP pHalGdmaOp;
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PIRQ_HANDLE pIrqGdmaHnd;
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VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function
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PSAL_ADC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_ADC_USER_CB )
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VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function
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}SAL_ADC_MNGT_ADPT, *PSAL_ADC_MNGT_ADPT;
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//================ ADC HAL Function Prototype ===================
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// ADC HAL inline function
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// For checking I2C input index valid or not
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static inline RTK_STATUS
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RtkADCIdxChk(
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IN u8 ADCIdx
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)
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{
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#if !ADC0_USED
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if (ADCIdx == ADC0_SEL)
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return _EXIT_FAILURE;
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#endif
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#if !ADC1_USED
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if (ADCIdx == ADC1_SEL)
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return _EXIT_FAILURE;
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#endif
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#if !ADC2_USED
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if (ADCIdx == ADC2_SEL)
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return _EXIT_FAILURE;
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#endif
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#if !ADC3_USED
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if (ADCIdx == ADC3_SEL)
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return _EXIT_FAILURE;
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#endif
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return _EXIT_SUCCESS;
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}
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VOID HalADCOpInit(IN VOID *Data);
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PSAL_ADC_HND RtkADCGetSalHnd(IN u8 DACIdx);
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RTK_STATUS RtkADCFreeSalHnd(IN PSAL_ADC_HND pSalADCHND);
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RTK_STATUS RtkADCLoadDefault(IN VOID *Data);
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RTK_STATUS RtkADCInit(IN VOID *Data);
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RTK_STATUS RtkADCDeInit(IN VOID *Data);
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//RTK_STATUS RtkADCReceive(IN VOID *Data);
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u32 RtkADCReceive(IN VOID *Data);
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u32 RtkADCReceiveBuf(IN VOID *Data,IN u32 *pBuf);
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PSAL_ADC_MNGT_ADPT RtkADCGetMngtAdpt(IN u8 ADCIdx);
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RTK_STATUS RtkADCFreeMngtAdpt(IN PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt);
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VOID ADCISRHandle(IN VOID *Data);
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VOID ADCGDMAISRHandle(IN VOID *Data);
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HAL_Status RtkADCDisablePS(IN VOID *Data);
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HAL_Status RtkADCEnablePS(IN VOID *Data);
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#endif
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