mirror of
https://github.com/pvvx/RTL00ConsoleROM.git
synced 2024-11-22 02:04:14 +00:00
100 lines
3 KiB
C
100 lines
3 KiB
C
#ifndef _RTL8710_SPI_H_
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#define _RTL8710_SPI_H_
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#include <stdint.h>
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typedef struct{
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volatile uint32_t CTRLR0;
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volatile uint32_t CTRLR1;
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volatile uint32_t SSIENR;
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volatile uint32_t MWCR;
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volatile uint32_t SER;
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volatile uint32_t BAUDR;
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volatile uint32_t TXFTLR;
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volatile uint32_t RXFTLR;
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volatile uint32_t TXFLR;
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volatile uint32_t RXFLR;
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volatile uint32_t SR;
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volatile uint32_t IMR;
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volatile uint32_t ISR;
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volatile uint32_t RISR;
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volatile uint32_t TXOICR;
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volatile uint32_t RXOICR;
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volatile uint32_t RXUICR;
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volatile uint32_t MSTICR;
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volatile uint32_t ICR;
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volatile uint32_t DMACR;
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volatile uint32_t DMATDLR;
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volatile uint32_t DMARDLR;
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volatile uint32_t IDR;
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volatile uint32_t SSI_COMP_VERSION;
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union{
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struct{
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union{
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volatile uint8_t DR;
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volatile uint8_t DR8;
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};
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uint8_t RESERVED1[3];
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}__attribute__((packed));
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struct{
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volatile uint16_t DR16;
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uint16_t RESERVED2[1];
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}__attribute__((packed));
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volatile uint32_t DR32;
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};
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uint32_t RESERVED3[31];
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volatile uint32_t READ_FAST_SINGLE;
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volatile uint32_t READ_DUAL_DATA;
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volatile uint32_t READ_DUAL_ADDR_DATA;
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volatile uint32_t READ_QUAD_DATA;
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union{
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volatile uint32_t READ_QUAD_ADDR_DATA;
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volatile uint32_t RX_SAMPLE_DLY;
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};
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volatile uint32_t WRITE_SIGNLE;
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volatile uint32_t WRITE_DUAL_DATA;
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volatile uint32_t WRITE_DUAL_ADDR_DATA;
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volatile uint32_t WRITE_QUAD_DATA;
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volatile uint32_t WRITE_QUAD_ADDR_DATA;
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volatile uint32_t WRITE_ENABLE;
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volatile uint32_t READ_STATUS;
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volatile uint32_t CTRLR2;
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volatile uint32_t FBAUDR;
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volatile uint32_t ADDR_LENGTH;
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volatile uint32_t AUTO_LENGTH;
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volatile uint32_t VALID_CMD;
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volatile uint32_t FLASE_SIZE;
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volatile uint32_t FLUSH_FIFO;
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}__attribute__((packed)) SPI_TypeDef;
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#define SPI_FLASH ((SPI_TypeDef *)0x40006000)
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// SPI_CTRLR0
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#define SPI_CTRLR0_FRF (((uint32_t)0x03) << 4)
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#define SPI_CTRLR0_SCPH (((uint32_t)0x01) << 6)
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#define SPI_CTRLR0_SCPOL (((uint32_t)0x01) << 7)
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#define SPI_CTRLR0_TMOD (((uint32_t)0x03) << 8)
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#define SPI_CTRLR0_SLV_OE (((uint32_t)0x01) << 10)
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#define SPI_CTRLR0_SRL (((uint32_t)0x01) << 11)
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#define SPI_CTRLR0_CFS (((uint32_t)0x0F) << 12)
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#define SPI_CTRLR0_ADDR_CH (((uint32_t)0x03) << 16)
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#define SPI_CTRLR0_DATA_CH (((uint32_t)0x03) << 18)
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#define SPI_CTRLR0_CMD_CH (((uint32_t)0x03) << 20)
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#define SPI_CTRLR0_FAST_RD (((uint32_t)0x01) << 22)
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#define SPI_CTRLR0_SHIFT_CK_MTIMES (((uint32_t)0x1F) << 23)
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// SPI_SER
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#define SPI_SER_SS0 (((uint32_t)0x01) << 0)
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#define SPI_SER_SS1 (((uint32_t)0x01) << 1)
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#define SPI_SER_SS2 (((uint32_t)0x01) << 2)
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// SPI_SR
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#define SPI_SR_SSI (((uint32_t)0x01) << 0)
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#define SPI_SR_TFNF (((uint32_t)0x01) << 1)
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#define SPI_SR_TFE (((uint32_t)0x01) << 2)
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#define SPI_SR_RFNE (((uint32_t)0x01) << 3)
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#define SPI_SR_RFF (((uint32_t)0x01) << 4)
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#define SPI_SR_TXE (((uint32_t)0x01) << 5)
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#endif
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