mirror of
https://github.com/pvvx/RTL00ConsoleROM.git
synced 2024-11-28 09:10:37 +00:00
79 lines
2.8 KiB
C
79 lines
2.8 KiB
C
#ifndef _CORTEX_H_
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#define _CORTEX_H_
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#include <stdint.h>
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typedef struct{
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volatile uint32_t ISER[8];
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uint32_t RESERVED1[24];
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volatile uint32_t ICER[8];
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uint32_t RESERVED2[24];
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volatile uint32_t ISPR[8];
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uint32_t RESERVED3[24];
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volatile uint32_t ICPR[8];
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uint32_t RESERVED4[24];
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volatile uint32_t IABR[8];
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uint32_t RESERVED5[56];
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volatile uint32_t IPR[32];
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}NVIC_TypeDef;
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typedef struct{
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uint32_t RESERVED1[2];
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volatile uint32_t ACTLR;
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uint32_t RESERVED2[829];
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volatile const uint32_t CPUID;
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volatile uint32_t ICSR;
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volatile uint32_t VTOR;
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volatile uint32_t AIRCR;
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volatile uint32_t SCR;
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volatile uint32_t CCR;
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volatile uint32_t SHPR[3];
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volatile uint32_t SHCSR;
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volatile uint32_t CFSR;
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volatile uint32_t HFSR;
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volatile uint32_t DFSR;
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volatile uint32_t MMFAR;
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volatile uint32_t BFAR;
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volatile uint32_t AFSR;
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volatile const uint32_t PFR[2];
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volatile const uint32_t DFR;
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volatile const uint32_t AFR;
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volatile const uint32_t MMFR[4];
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volatile const uint32_t ISAR[5];
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uint32_t RESERVED3[5];
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volatile uint32_t CPACR;
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}SCB_TypeDef;
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#define NVIC ((NVIC_TypeDef *)0xE000E100)
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#define SCB ((SCB_TypeDef *)0xE000E000)
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// SCB_AIRCR
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#define SCB_AIRCR_VECTRESET (((uint32_t)0x0001) << 0)
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#define SCB_AIRCR_VECTCLRACTIVE (((uint32_t)0x0001) << 1)
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#define SCB_AIRCR_SYSRESETREQ (((uint32_t)0x0001) << 2)
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#define SCB_AIRCR_PRIGROUP (((uint32_t)0x0007) << 8)
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#define SCB_AIRCR_VECTKEY (((uint32_t)0xFFFF) << 16)
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#define SCB_AIRCR_VECTKEYSTAT (((uint32_t)0xFFFF) << 16)
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// SCB_CPACR
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#define SCB_CPACR_CP10 (((uint32_t)0x03) << 20)
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#define SCB_CPACR_CP11 (((uint32_t)0x03) << 22)
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#define cortex_interrupt_set_priority(i, p) (NVIC->IPR[(i) >> 2] = ((NVIC->IPR[(i) >> 2] & ~(((uint32_t)0xFF) << (((i) & 0x03) << 3))) | (((uint32_t)p) << (((i) & 0x03) << 3))))
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#define cortex_interrupt_enable(i) (NVIC->ISER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
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#define cortex_interrupt_disable(i) (NVIC->ICER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
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#define cortex_interrupt_clear(i) (NVIC->ICPR[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
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#define cortex_interrupts_disable() __asm__("cpsid f")
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#define cortex_interrupts_enable() __asm__("cpsie f")
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#define interrupts_disable() __asm__("cpsid f")
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#define interrupts_enable() __asm__("cpsie f")
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#define CORTEX_ISR(n) _CORTEX_ISR(n)
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#define _CORTEX_ISR(n) void __attribute__((interrupt)) CORTEX_INTERRUPT_##n##_Handler()
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void cortex_bootstrap(void *start) __attribute__ ((noreturn));
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void cortex_reboot() __attribute__ ((noreturn));
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#endif
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