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pvvx 2016-09-26 17:55:41 +03:00
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test.elf
test.bin
flash.bin
ram.bin

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>RTL00ConsoleROM</name>
<comment></comment>
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<natures>
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<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
</natures>
</projectDescription>

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buildTools.path=D\:\\MCU\\GNU_Tools_ARM_Embedded\\5.4_2016q2\\bin
eclipse.preferences.version=1
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25
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
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<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-68325830061" id="ilg.gnuarmeclipse.managedbuild.cross.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT GCC Built-in Compiler Settings Cross ARM" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
<language-scope id="org.eclipse.cdt.core.gcc"/>
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</provider>
</extension>
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<configuration id="cdt.managedbuild.config.gnu.mingw.exe.release.601511714" name="Release">
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<language-scope id="org.eclipse.cdt.core.gcc"/>
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</provider>
</extension>
</configuration>
</project>

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eclipse.preferences.version=1
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org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
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29
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environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/PATH/delimiter=;
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/PATH/operation=replace
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/PATH/value=${TL_PATH}\\bin;${MINGW_HOME}\\mingw64\\bin;${MINGW_HOME}\\bin;${MSYS_HOME}\\bin;${OCD_PATH};C\:/Program Files (x86)/Java/jre1.8.0_101/bin/client;C\:/Program Files (x86)/Java/jre1.8.0_101/bin;C\:/Program Files (x86)/Java/jre1.8.0_101/lib/i386;C\:\\MinGW\\mingw64\\bin;C\:\\MinGW\\msys\\1.0\\bin;C\:\\MinGW\\bin;D\:\\MCU\\STMicroelectronics\\st_toolset\\asm;C\:\\Python27;C\:\\Utils\\FarUtils;C\:\\Utils\\FarUtils\\HIEW810;C\:\\Windows;C\:\\Windows\\system32;C\:\\Windows\\System32\\Wbem;C\:\\Windows\\System32\\WindowsPowerShell\\v1.0;D\:\\MCU\\Microchip\\xc32\\v1.42\\bin;D\:\\MCU\\Microchip\\mplabc30\\v3.31\\bin;D\:\\MCU\\Microchip\\MPLAB C32 Suite\\bin;D\:\\MCU\\Microchip\\mplabc32\\v1.12\\bin;D\:\\MCU\\Microchip\\mcc18\\mpasm;D\:\\MCU\\Microchip\\mcc18\\bin;D\:\\WRK\\TortoiseGit\\bin;C\:\\Utils\\TortoiseSVN\\binC\:\\Program Files (x86)\\Git\\cmd;C\:\\Program Files (x86)\\Borland\\Delphi7\\Bin;C\:\\Program Files (x86)\\Borland\\Delphi7\\Projects\\Bpl\\;C\:\\Program Files (x86)\\Common Files\\Microsoft Shared\\Windows Live;C\:\\Program Files (x86)\\ATI Technologies\\ATI.ACE\\Core-Static;C\:\\Program Files (x86)\\Common Files\\Acronis\\SnapAPI;C\:\\Program Files (x86)\\Windows Live\\Shared;C\:\\Program Files (x86)\\IVI Foundation\\VISA\\WinNT\\Bin;C\:\\Program Files (x86)\\Windows Kits\\8.1\\Windows Performance Toolkit;C\:\\Program Files (x86)\\Microsoft SDKs\\TypeScript\\1.0;C\:\\Program Files (x86)\\IVI Foundation\\VISA\\WinNT\\Bin;C\:\\Program Files\\Microsoft SQL Server\\110\\Tools\\Binn;C\:\\Program Files\\Common Files\\Microsoft Shared\\Windows Live;C\:\\Program Files\\Microsoft SQL Server\\120\\Tools\\Binn;C\:\\Program Files\\Microsoft DNX\\Dnvm;C\:\\Program Files\\IVI Foundation\\VISA\\Win64\\Bin;D\:\\Automation\\Samcoon\\SKWorkshop\\Marco\\HMI\\bin;D\:\\Automation\\Samcoon\\SKWorkshop\\Marco\\X86\\bin;D\:\\Automation\\Samcoon\\SK035AE\\SKWorkshop\\Marco\\HMI\\bin;D\:\\Automation\\Samcoon\\SK035AE\\SKWorkshop\\Marco\\X86\\bin;C\:\\Users\\PVV\\.dnx\\bin;C\:\\ProgramData\\chocolatey\\bin;C\:\\ProgramData\\Oracle\\Java\\javapath;C\:\\Program Files (x86)\\QuickTime\\QTSystem;C\:\\Program Files\\nodejs;D\:\\WRK\\TortoiseGit\\bin;C\:\\Utils\\TortoiseSVN\\bin;C\:\\Program Files (x86)\\Git\\cmd;D\:\\MentorGraphics\\Sourcery_CodeBench_Lite_for_MIPS_ELF\\bin;C\:\\Eclipse
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/TL_PATH/delimiter=;
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/TL_PATH/operation=replace
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/TL_PATH/value=D\:\\MCU\\GNU_Tools_ARM_Embedded\\5.4_2016q2\\bin
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/append=true
environment/project/cdt.managedbuild.config.gnu.mingw.exe.release.601511714/appendContributed=true

2
.settings/org.eclipse.core.resources.prefs Normal file
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eclipse.preferences.version=1
encoding/<project>=UTF-8

3
JLink-RTL00ConsoleROM.bat Normal file
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@ -0,0 +1,3 @@
@echo off
PATH=D:\MCU\SEGGER\JLink_V610a;%PATH%
start JLink.exe -Device CORTEX-M3 -If SWD -Speed 4000 flasher\RTL00ConsoleROM.JLinkScript

3
JLink-RdFullFlash.bat Normal file
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@ -0,0 +1,3 @@
@echo off
PATH=D:\MCU\SEGGER\JLink_V610a;%PATH%
JLink.exe -Device CORTEX-M3 -If SWD -Speed 4000 flasher/RTL_FFlash.JLinkScript

3
JLink-Reset.bat Normal file
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@ -0,0 +1,3 @@
@echo off
PATH=D:\MCU\SEGGER\JLink_V610a;%PATH%
start JLink.exe -Device CORTEX-M3 -If SWD -Speed 1000 flasher\RTL_Reset.JLinkScript

3
JLink-RunRAM.bat Normal file
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@ -0,0 +1,3 @@
@echo off
PATH=D:\MCU\SEGGER\JLink_V610a;%PATH%
start JLink.exe -Device CORTEX-M3 -If SWD -Speed 4000 flasher\RTL_RunRAM.JLinkScript

6
JLinkGDB-RdFullFlash.bat Normal file
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@ -0,0 +1,6 @@
@echo off
PATH=D:\MCU\GNU_Tools_ARM_Embedded\5.2_2015q4\bin;D:\MCU\SEGGER\JLink_V610a;%PATH%
start JLinkGDBServer.exe -device Cortex-M3 -if SWD -ir -endian little -speed 1000
arm-none-eabi-gdb.exe -x flasher/gdb_rdflash.jlink
taskkill /F /IM JLinkGDBServer.exe

16
JLinkGDB-RunRAM.bat Normal file
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@echo off
PATH=D:\MCU\GNU_Tools_ARM_Embedded\5.2_2015q4\bin;D:\MCU\SEGGER\JLink_V610a;%PATH%
@if exist test.elf goto run
echo File 'build\obj\build.axf' not found!
echo Build project...
mingw32-make.exe -f Makefile all
@if not exist test.elf goto err
:run
start JLinkGDBServer.exe -device Cortex-M3 -if SWD -ir -endian little -speed 1000
arm-none-eabi-gdb.exe --help >xxx.txt
arm-none-eabi-gdb.exe -x flasher/gdb_run_ram.jlink
taskkill /F /IM JLinkGDBServer.exe
goto end
:err
echo Error!
:end

6
JLinkGDB-WrFlash.bat Normal file
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@ -0,0 +1,6 @@
@echo off
PATH=D:\MCU\GNU_Tools_ARM_Embedded\5.2_2015q4\bin;D:\MCU\SEGGER\JLink_V610a;%PATH%
start JLinkGDBServer.exe -device Cortex-M3 -if SWD -ir -endian little -speed 3500
arm-none-eabi-gdb.exe -x flasher/gdb_wrflash.jlink
taskkill /F /IM JLinkGDBServer.exe

36
LICENSE Normal file
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THE BEER-WARE LICENSE
As long as you retain this notice you can do whatever you want
with this stuff. If we meet some day, and you think this stuff
is worth it, you can buy me a beer in return.
Rebane, rebane@alkohol.ee
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
This is free and unencumbered software released into the public domain.
Anyone is free to copy, modify, publish, use, compile, sell, or
distribute this software, either in source code form or as a compiled
binary, for any purpose, commercial or non-commercial, and by any
means.
In jurisdictions that recognize copyright laws, the author or authors
of this software dedicate any and all copyright interest in the
software to the public domain. We make this dedication for the benefit
of the public at large and to the detriment of our heirs and
successors. We intend this dedication to be an overt act of
relinquishment in perpetuity of all present and future rights to this
software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
For more information, please refer to <http://unlicense.org/>

78
Makefile Normal file
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LIBDIR = lib
FILENAME_PREFIX = test
ADDRESS = 0x10001000
tmp?=/tmp
#ADDRESS = 0x10000BC8
#FLASHER = stlink-v2-1
#FLASHER = stlink-v2
FLASHER = Jlink
ifeq ($(FLASHER), Jlink)
# Jlink FLASHER_SPEED ..4000 kHz
FLASHER_SPEED = 3500
else
ifeq ($(FLASHER),stlink-v2)
# stlink-v2 FLASHER_SPEED ..1800 kHz
FLASHER_SPEED = 1800
else
# ? FLASHER_SPEED ..500 kHz ?
FLASHER_SPEED = 500
endif
endif
#FLASH_TOOLDIR = tools/openocd
CC_PARAMS = -Wall -g3 -Os -mlittle-endian -mlong-calls -mthumb -mcpu=cortex-m3 -mfloat-abi=soft -mthumb-interwork -ffunction-sections -ffreestanding -fsingle-precision-constant -fshort-wchar -fno-short-enums -Ddouble=float -nostartfiles -nostdlib
LINK_PARAMS = -Wstrict-aliasing=0 -Wl,--gc-sections -Wl,-Map=$(FILENAME_PREFIX).map -Wl,-Trtl8710.ld -Wl,-defsym -Wl,seg0_size_1k=0x002c
#-Wl,--entry=start_init -Wl,--section-start=.text=$(ADDRESS)
BASE_PARAMS = -DCORTEX_INTERRUPT_MAX=32 -I$(LIBDIR) -I$(LIBDIR)/cpu/rtl8710 -I$(LIBDIR)/cpu/cortex -I$(LIBDIR)/fwlib
LIBC_PARAMS = -L$(LIBDIR)/cpu/rtl8710 -I$(LIBDIR)/libc $(LIBDIR)/libc/libc.c -DLIBC_PRINTF $(LIBDIR)/cpu/cortex/cortex.c
#-lgcc
#$(LIBDIR)/libc/libc.c -DLIBC_PRINTF $(LIBDIR)/cpu/cortex/cortex.c
FIRMWARE_PARAMS = main.c
#---------------------------
# User defined
#---------------------------
# + or set in PATH D:\MCU\GNU_Tools_ARM_Embedded\5.4_2016q2\bin;
GCC_PATH=d:/MCU/GNU_Tools_ARM_Embedded/5.4_2016q2/bin/
#---------------------------
# Default
#---------------------------
# Compilation tools
CROSS_COMPILE = $(GCC_PATH)arm-none-eabi-
AR = $(CROSS_COMPILE)ar
CC = $(CROSS_COMPILE)gcc
AS = $(CROSS_COMPILE)as
NM = $(CROSS_COMPILE)nm
LD = $(CROSS_COMPILE)ld
GDB = $(CROSS_COMPILE)gdb
SIZE = $(CROSS_COMPILE)size
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
STRIP = $(CROSS_COMPILE)strip
all: firmware
firmware:
$(CC) $(CC_PARAMS) $(BASE_PARAMS) $(LIBC_PARAMS) $(LINK_PARAMS) $(FIRMWARE_PARAMS) -o $(FILENAME_PREFIX).elf
$(OBJCOPY) -j .header -j .text -j .data -Obinary $(FILENAME_PREFIX).elf $(RAM1_IMAGE) ram.bin
$(OBJCOPY) -j .fheader -j .header -j .text -j .data -Obinary $(FILENAME_PREFIX).elf $(RAM1_IMAGE) flash.bin
$(OBJDUMP) -S $(FILENAME_PREFIX).elf >$(FILENAME_PREFIX).asm
size:
$(SIZE) -A -x $(FILENAME_PREFIX).elf
clean:
rm -rf *.bin test.elf test.asm flash.bin ram.bin test.map
test:
#openocd -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(LIBDIR)/cpu/rtl8710/rtl8710.ocd -f $(LIBDIR)/cpu/cortex/cortex.ocd -c "init" -c "reset halt" -c "load_image $(FILENAME_PREFIX).bin $(ADDRESS) bin" -c "cortex_bootstrap $(ADDRESS)" -c "shutdown"
flash:
#openocd -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(LIBDIR)/cpu/rtl8710/rtl8710.ocd -c "init" -c "reset halt" -c "rtl8710_flash_auto_erase 1" -c "rtl8710_flash_auto_verify 1" -c "rtl8710_flash_write flash.bin 0" -c "rtl8710_reboot" -c "reset run" -c shutdown
reset:
#openocd -f interface/$(FLASHER).cfg -c "adapter_khz $(FLASHER_SPEED)" -f $(LIBDIR)/cpu/rtl8710/rtl8710.ocd -c "init" -c "reset halt" -c "rtl8710_reboot" -c shutdown

42
README.md Normal file
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# RTL-00 Test Load to RAM + RTL Console ROM
Testing RTL8710 + J-Link/STlink
## pins:
* UART RX: GB0
* UART TX: GB1
* LED: GC4
* SWDIO: GE3
* SWCLK: GE4
## building:
```
make
```
## flashing:
```
JLinkGDB-WrFlash.bat
```
## reset:
```
JLink-Reset.bat
```
```
## Runing in ram:
```
JLink-RunRAM.bat
JLinkGDB-RunRAM.bat
```
## Read FullFlash
```
JLink-RdFullFlash.bat
```
## Debug RAM
```
export project to Eclipse...
```
## RTL00 Console ROM
```
JLink-RTL00ConsoleROM.bat
```

6
flasher/RTL00ConsoleROM.JLinkScript Normal file
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h
loadbin flasher/RTL00Console_ROM.bin 0x10000ba8
r
w4 0x40000210,0x4011117
g
q

BIN
flasher/RTL00Console_ROM.bin Normal file
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Binary file not shown.

17
flasher/RTL_FFlash.JLinkScript Normal file
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h
r
w4 0x40000230,0x0000D3C4
w4 0x40000210,0x00200113
w4 0x400002C0,0x00110001
w4 0x40006008,0
w4 0x4000602C,0
w4 0x40006010,1
w4 0x40006014,2
w4 0x40006018,0
w4 0x4000601C,0
w4 0x4000604C,0
savebin fullflash.bin 0x98000000 0x100000
w4 0x40000210,0x211157
r
g
q

5
flasher/RTL_Reset.JLinkScript Normal file
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h
r
w4 0x40000210,0x00211157
g
q

6
flasher/RTL_RunRAM.JLinkScript Normal file
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h
loadbin ram.bin 0x10000bc8
r
w4 0x40000210,0x4011117
g
q

124
flasher/ameba1.cfg Normal file
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# Main file for Ameba1 series Cortex-M3 parts
#
# !!!!!!
#
set CHIPNAME rtl8195a
set CHIPSERIES ameba1
# Adapt based on what transport is active.
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
error "CHIPNAME not set. Please do not include ameba1.cfg directly."
}
if { [info exists CHIPSERIES] } {
# Validate chip series is supported
if { $CHIPSERIES != "ameba1" } {
error "Unsupported chip series specified."
}
set _CHIPSERIES $CHIPSERIES
} else {
error "CHIPSERIES not set. Please do not include ameba1.cfg directly."
}
if { [info exists CPUTAPID] } {
# Allow user override
set _CPUTAPID $CPUTAPID
} else {
# Ameba1 use a Cortex M3 core.
if { $_CHIPSERIES == "ameba1" } {
if { [using_jtag] } {
set _CPUTAPID 0x4ba00477
} {
set _CPUTAPID 0x2ba01477
}
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
# Run with *real slow* clock by default since the
# boot rom could have been playing with the PLL, so
# we have no idea what clock the target is running at.
adapter_khz 1000
# delays on reset lines
adapter_nsrst_delay 200
if {[using_jtag]} {
jtag_ntrst_delay 200
}
# Ameba1 (Cortex M3 core) support SYSRESETREQ
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
$_TARGETNAME configure -event reset-init {ameba1_init}
# Ameba1 SDRAM enable
proc ameba1_init { } {
# init System
mww 0x40000014 0x00000021
sleep 10
mww 0x40000304 0x1fc00002
sleep 10
mww 0x40000250 0x00000400
sleep 10
mww 0x40000340 0x00000000
sleep 10
mww 0x40000230 0x0000dcc4
sleep 10
mww 0x40000210 0x00011117
sleep 10
mww 0x40000210 0x00011157
sleep 10
mww 0x400002c0 0x00110011
sleep 10
mww 0x40000320 0xffffffff
sleep 10
# init SDRAM
mww 0x40000040 0x00fcc702
sleep 10
mdw 0x40000040
mww 0x40005224 0x00000001
sleep 10
mww 0x40005004 0x00000208
sleep 10
mww 0x40005008 0xffffd000
sleep 13
mww 0x40005020 0x00000022
sleep 13
mww 0x40005010 0x09006201
sleep 13
mww 0x40005014 0x00002611
sleep 13
mww 0x40005018 0x00068413
sleep 13
mww 0x4000501c 0x00000042
sleep 13
mww 0x4000500c 0x700 ;# set Idle
sleep 20
mww 0x40005000 0x1 ;# start init
sleep 100
mdw 0x40005000
mww 0x4000500c 0x600 ;# enter memory mode
sleep 30
mww 0x40005008 0x00000000 ;# 0xf00
;# mww 0x40005008 0x00000f00
sleep 3
mww 0x40000300 0x0006005e ;# 0x5e
;# mww 0x40000300 0x0000005e
sleep 3
}

89
flasher/cortex.ocd Normal file
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proc cortex_bootstrap {start} {
# disable interrupts
reg faultmask 0x01
set vectors ""
mem2array vectors 32 $start 2
reg sp $vectors(0)
reg pc $vectors(1)
resume
}
proc cortex_reboot {} {
set ddd [ format "0x%08x" [ rtl8710_flasher_mrw [ expr 0x40000210 ] ] ]
# set aaa [ format "0x%08x" [ expr 0x40000210 ] ]
echo "CLK_CTRL1 = $ddd"
# echo "# Set processor clock to default before system reset"
set ddd [ format "0x%08x" [ rtl8710_flasher_mrw [ expr 0x40000014 ] ] ]
# set aaa [ format "0x%08x" [ expr 0x40000014 ] ]
echo "SOC_FUNC_EN = $ddd"
# mww 0x40000014 0x00000021
sleep 10
echo "# Reboot (system reset)"
mww 0xE000ED0C 0x05FA0007
}
proc init_system {} {
# Set processor clock to default before system reset
# CLK_CTRL1
# mww 0x40000014 0x00000011
mww 0x40000014 0x00000021
sleep 10
# PESOC_SOC_CTRL
# mww 0x40000304 0x1fc00001
mww 0x40000304 0x1fc00002
sleep 10
# PESOC_CLK_SEL
mww 0x40000250 0x00000400
sleep 10
# GPIO_PULL_CTRL4
mww 0x40000340 0x00000000
sleep 10
# PESOC_CLK_CTRL
# mww 0x40000230 0x0000d3c4
mww 0x40000230 0x0000dcc4
sleep 10
# SOC_FUNC_EN: FUN|OCP|LXBUS|FLASH|CPU|LOG_UART|GTIMER|SECURITY_ENGINE
# mww 0x40000210 0x00211117
mww 0x40000210 0x00011117
sleep 10
# SOC_FUNC_EN: FUN|OCP|LXBUS|FLASH|CPU|LOG_UART|GTIMER|SECURITY_ENGINE + MEM_CTRL
mww 0x40000210 0x00011157
sleep 10
# CPU_PERIPHERAL_CTRL SPI_FLASH_PIN_EN|SDR_PIN_EN|SWD_PIN_EN|LOG_UART_PIN_EN ?
# mww 0x400002c0 0x00110000
mww 0x400002c0 0x00110011
sleep 10
# GPIO_SHTDN_CTRL
# mww 0x40000320 0x00000033
mww 0x40000320 0xffffffff
sleep 10
mww 0x40005008 0x00000000
sleep 10
# PESOC_MEM_CTRL
mww 0x40000300 0x0006005e
sleep 10
# set baudrate to 38400
# mww 0x40003010 0x00000080
# mww 0x40003008 0x00000022
# mww 0x4000300C 0x00000000
# mww 0x40003010 0x00000000
}
proc boot_from_flash {} {
echo "# skip sdram init, it has been init in openocd config"
mww 0x40000210 0x211157
}
proc boot_from_ram {} {
echo "# boot from ram, igonore loading flash"
mww 0x40000210 0x8011157
}
proc restart_from_falsh {} {
init
init_system
boot_from_flash
cortex_reboot
}

200
flasher/gdb_flasher.jlink Normal file
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####################################
# J-LINK GDB SERVER initialization #
####################################
define InitJlink
printf "Jlink Init:\n"
set verbose off
set complaints 0
set confirm off
set exec-done-display off
show exec-done-display
set trace-commands off
#set debug aix-thread off
#set debug dwarf2-die 0
set debug displaced off
set debug expression 0
set debug frame 0
set debug infrun 0
set debug observer 0
set debug overload 0
#set debugvarobj 0
set pagination off
set print address off
set print symbol-filename off
set print symbol off
set print pretty off
set print object off
#set debug notification off
set debug parser off
set debug remote 0
target remote localhost:2331
set remotetimeout 10000
monitor device Cortex-M3
monitor endian little
monitor reset
# Set max speed
monitor speed 4000
set mem inaccessible-by-default off
# Setup GDB FOR FASTER DOWNLOADS
set remote memory-write-packet-size 8192
set remote memory-write-packet-size fixed
end
#############
# Boot_Flash
define SetBootFlash
printf "SetBoot = Flash:\n"
monitor long 0x40000210 = 0x211157
end
# Boot RAM start_addr0() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x80000000 )
define SetBootCall0
printf "SetBoot = Call0:\n"
monitor long 0x40000210 = 0x80011117
end
# Boot RAM start_addr1() Run if ( v40000210 & 0x20000000 )
define SetBootCall1
printf "SetBoot = Call1:\n"
monitor long 0x40000210 = 0x20011117
end
# Boot RAM start_addr2() Run if ( v40000210 & 0x10000000 )
define SetBootCall2
printf "SetBoot = Call2:\n"
monitor long 0x40000210 = 0x10011117
end
# Boot RAM start_addr3() Run if ( v400001F4 & 0x8000000 ) && ( v40000210 & 0x8000000 )
define SetBootCall3
printf "SetBoot = Call3:\n"
monitor long 0x40000210 = 0x8011117
end
# Boot RAM start_addr4() Init console, Run if ( v40000210 & 0x4000000 )
define SetBootCall4
printf "SetBoot = Call4:\n"
monitor long 0x40000210 = 0x4011117
end
# CPU CLK 166 MHz?
define SetClk166MHz
printf "SetCLK 166.66MHz:\n"
monitor long 0x40000014 = 0x00000011
end
# CPU CLK 83 MHz?
define SetClk83MHz
printf "SetCLK 83.33MHz:\n"
monitor long 0x40000014 = 0x00000021
end
###############
# System Init #
###############
define SystemInit
printf "System Init:\n"
monitor long 0x40000304 = 0x1FC00002
monitor long 0x40000250 = 0x400
monitor long 0x40000340 = 0x0
monitor long 0x40000230 = 0xdcc4
monitor long 0x40000210 = 0x11117
monitor long 0x40000210 = 0x11157
monitor long 0x400002c0 = 0x110011
monitor long 0x40000320 = 0xffffffff
end
############
# SPI Init #
############
define SPI_Init
printf "Init SPI:\n"
#enable spi flash peripheral clock
set $Temp = {int}(0x40000230)
set $Temp = ($Temp | 0x300)
set {int}(0x40000230) = $Temp
#enable spi flash peripheral
set $Temp = {int}(0x40000210)
set $Temp = ($Temp | 0x10)
set {int}(0x40000210) = $Temp
#select spi flash pinout (0 - internal), enable spi flash pins
set $Temp = {int}(0x400002C0)
set $Temp = (($Temp & 0xFFFFFFF8) | 1)
set {int}(0x400002C0) = $Temp
#disable SPI FLASH operation
monitor long 0x40006008 = 0
#disable all interrupts
monitor long 0x4000602C = 0
#use first "slave select" pin
monitor long 0x40006010 = 1
#baud rate, default value
monitor long 0x40006014 = 2
#tx fifo threshold
monitor long 0x40006018 = 0
#rx fifo threshold
monitor long 0x4000601C = 0
#disable DMA
monitor long 0x4000604C = 0
set $SPI_FLASH_BASE = 0x98000000
end
###################
# SetFirwareSize #
###################
define SetFirwareSize
set $rambuffer = 0x10000300
set $Image2Addr = 0
set $Image2Size = 0
printf "Get ImagesSize:\n"
restore $arg0 binary $rambuffer 0 0x20
set $Image1Size = {int}($rambuffer+0x10) + 32
set $Image1LoadAddr = {int}($rambuffer+0x14)
#set $Image2Addr = {short}($rambuffer+0x18) * 1024
if $Image1Size != 0 && $Image1Size < 0x1000000
if $Image2Addr == 0
set $Image2Addr = $Image1Size
end
# printf "Image1Size = %d\n", $Image1Size
# printf "Image1LoadAddr = 0x%08x\n", $Image1LoadAddr
# printf "Image2FlashAddr = 0x%08x\n", $Image2Addr
# set $parms1 = $rambuffer - $Image2Addr
# set $parms3 = $Image2Addr + 0x08
# restore $arg0 binary $parms1 $Image2Addr $parms3
# set $Image2Size = {int}($rambuffer)
# set $Image2LoadAddr = {int}($rambuffer+0x4)
if $Image2Size != 0xFFFFFFFF && $Image2Size != 0
set $Image2Size = $Image2Size + 16
printf "Image2Size = %d\n", $Image2Size
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
set $FirmwareSize = $Image2Addr + $Image2Size
printf "FirmwareSize = %d\n", $FirmwareSize
else
set $Image2Size = 0
printf "Image2 - None\n"
set $FirmwareSize = $Image1Size
printf "FirmwareSize = %d\n", $FirmwareSize
end
else
set $Image1Size = 0
set $Image2Size = 0
set $Image2Addr = 0
set $FirmwareSize = 0
printf "Image not format Firmware!\n"
end
end
#####################
# Flash Images Info #
#####################
define FlashImagesInfo
printf "Flash Info:\n"
set $Image1Size = {int}($SPI_FLASH_BASE + 0x10) + 32
set $Image1LoadAddr = {int}($SPI_FLASH_BASE + 0x14)
if $Image1LoadAddr == 0xFFFFFFFF
printf "Image1 - None\n"
else
set $Image2FlashAddr = {short}($SPI_FLASH_BASE + 0x18) * 1024
if $Image2FlashAddr == 0
$Image2FlashAddr = $Image1Size
end
set $Image2Size = {int}($Image2FlashAddr + $SPI_FLASH_BASE)
set $Image2LoadAddr = {int}($Image2FlashAddr + $SPI_FLASH_BASE + 0x4)
printf "Image1Size = %d\n", $Image1Size
printf "Image1LoadAddr = 0x%08x\n", $Image1LoadAddr
printf "Image2FlashAddr = 0x%08x\n", $Image2FlashAddr
if $Image2Size != 0xFFFFFFFF
printf "Image2Size = %d\n", $Image2Size
printf "Image2LoadAddr = 0x%08x\n", $Image2LoadAddr
else
printf "Image2 - None\n"
end
end
end

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#
# J-LINK GDB SERVER initialization
#
source -v flasher/gdb_flasher.jlink
InitJlink
SetBootFlash
monitor reset
monitor go
quit

16
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# GDB Jlink read fullflash
# Init
source -v flasher/gdb_flasher.jlink
InitJlink
SystemInit
SPI_Init
FlashImagesInfo
# Read FullFlash
printf "Read FullFlash:\n"
set $dumpstartaddr = $SPI_FLASH_BASE
set $dumpendaddr = $SPI_FLASH_BASE + 0x100000
printf "Start addr of dumping = 0x%08x\n", $dumpstartaddr
printf "End addr of dumping = 0x%08x\n", $dumpendaddr
dump binary memory fullflash.bin $dumpstartaddr $dumpendaddr
printf "FullFlash saved in 'fullflash.bin' - OK.\n"
quit

11
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#
# J-LINK GDB SERVER initialization
#
source -v flasher/gdb_flasher.jlink
InitJlink
SetBootCall4
load test.elf
monitor reset
monitor go
quit

160
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###############
# FlasherInit #
###############
define FlasherInit
set $rtl8710_flasher_capacity = 0
set $rtl8710_flasher_auto_erase = 1
set $rtl8710_flasher_auto_verify = 1
set $rtl8710_flasher_firmware_ptr = 0x10001000
set $rtl8710_flasher_buffer = 0x10008000
#262144
set $rtl8710_flasher_buffer_size = 425984
set $rtl8710_flasher_sector_size = 4096
set $rtl8710_flasher_auto_erase_sector = 0xFFFFFFFF
end
###############
# FlasherWait #
###############
define FlasherWait
set $fresult = {int}($rtl8710_flasher_buffer)
while ($fresult != 0)
set $fresult = {int}($rtl8710_flasher_buffer)
end
end
###############
# FlasherLoad #
###############
define FlasherLoad
if $rtl8710_flasher_capacity == 0
printf "initializing RTL8710 flasher\n"
restore $arg0 binary $rtl8710_flasher_firmware_ptr 0 968
monitor reset
set $pc = $rtl8710_flasher_firmware_ptr
set $sp = 0x1ffffffc
set {int}($rtl8710_flasher_buffer + 0x08) = 0
set {int}($rtl8710_flasher_buffer + 0x00) = 1
#continue
monitor go
FlasherWait
set $id = {int}($rtl8710_flasher_buffer + 0x0C)
if ($id == 0x1420c2)
set $rtl8710_flasher_capacity = 1 << (($id >> 16) & 0x0ff)
printf "Flash ID = 0x%08x : MX25L8006E (%d kbytes)\n", $id, $rtl8710_flasher_capacity>>10
else
set $rtl8710_flasher_capacity = 1024*1024)
error "Flash ID = 0x%08x : ?\n", $id
end
printf "RTL8710 flasher initialized\n"
else
printf "reinitializing RTL8710 flasher\n"
end
end
##################
# FlasherWrBlock #
##################
define FlasherWrBlock
#printf "FlashWrBlock 0x%08x, 0x%08x\n", $arg0, $arg1
set {int}($rtl8710_flasher_buffer + 0x04) = 4
set {int}($rtl8710_flasher_buffer + 0x08) = 0
set {int}($rtl8710_flasher_buffer + 0x10) = $arg0
set {int}($rtl8710_flasher_buffer + 0x14) = $arg1
set {int}($rtl8710_flasher_buffer + 0x00) = 1
FlasherWait
set $status = {int}($rtl8710_flasher_buffer + 0x08)
if $status > 0
error "write error, offset 0x%08x", $arg0
end
end
##################
# FlasherVrBlock #
##################
define FlasherVrBlock
#printf "FlashVrBlock 0x%08x, 0x%08x\n", $arg0, $arg1
set {int}($rtl8710_flasher_buffer + 0x04) = 5
set {int}($rtl8710_flasher_buffer + 0x08) = 0
set {int}($rtl8710_flasher_buffer + 0x10) = $arg0
set {int}($rtl8710_flasher_buffer + 0x14) = $arg1
set {int}($rtl8710_flasher_buffer + 0x00) = 1
FlasherWait
set $status = {int}($rtl8710_flasher_buffer + 0x08)
if $status > 0
set $status = {int}($rtl8710_flasher_buffer + 0x0C)
set $status = {int}($status + $arg0)
error "verify error, offset 0x%08x", $status
end
end
#################
# FlashSecErase #
#################
define FlashSecErase
#printf "FlashSecErase 0x%08x, 0x%08x\n", $rtl8710_flasher_buffer, $arg0
set {int}($rtl8710_flasher_buffer + 0x04) = 2
set {int}($rtl8710_flasher_buffer + 0x08) = 0
set {int}($rtl8710_flasher_buffer + 0x10) = $arg0
set {int}($rtl8710_flasher_buffer + 0x00) = 1
FlasherWait
end
################
# FlasherWrite #
################
define FlasherWrite
set $sector = 0
set $offset = 0
set $size = $arg2
while $offset < $size
set $len = $size - $offset
if $len > $rtl8710_flasher_buffer_size
set $len = $rtl8710_flasher_buffer_size
end
set $flash_offset = $arg1 + $offset
printf "write offset 0x%08x\n", $flash_offset
set $parms1 = $rtl8710_flasher_buffer + 0x20 - $offset - $arg1
set $parms2 = $offset + $arg1
set $parms3 = $offset + $len + $arg1
restore $arg0 binary $parms1 $parms2 $parms3
if $rtl8710_flasher_auto_erase != 0
set $count_i = $flash_offset
while $count_i < ($flash_offset + $len)
set $sector = $count_i/$rtl8710_flasher_sector_size
if $rtl8710_flasher_auto_erase_sector != $sector
set $parms1 = $sector * $rtl8710_flasher_sector_size
printf "erase sector %d at 0x%08x\n", $sector, $parms1
FlashSecErase $parms1
set $rtl8710_flasher_auto_erase_sector = $sector
end
set $count_i = $count_i + 1
end
end
FlasherWrBlock $flash_offset $len
printf "wrote %d bytes at 0x%08x\n", $len, $flash_offset
if $rtl8710_flasher_auto_verify != 0
printf "verify offset 0x%08x len %d\n", $flash_offset, $len
FlasherVrBlock $flash_offset $len
end
set $offset = $offset + $rtl8710_flasher_buffer_size
end
end
#########################################
source -v flasher/gdb_flasher.jlink
InitJlink
SystemInit
SetClk166MHz
SPI_Init
FlashImagesInfo
SetFirwareSize flash.bin
if $FirmwareSize == 0
error "FirmwareSize = 0!"
end
FlasherInit
FlasherLoad flasher/rtl8710_flasher.bin
if $Image1Size != 0
printf "Write Image1 size %d to Flash addr 0x00000000:\n", $Image1Size
FlasherWrite flash.bin 0 $Image1Size
if $Image2Size != 0 && $Image2Addr >= $Image1Size
printf "Write Image2 size %d to Flash addr 0x%08x:\n", $Image2Size, $Image2Addr
FlasherWrite flash.bin $Image2Addr $Image2Size
end
end
FlashImagesInfo
quit

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#!/bin/sh
#===============================================================================
CURRENT_UTILITY_DIR=$(pwd)
GDBSCPTFILE="../../../component/soc/realtek/8195a/misc/gcc_utility/rtl_gdb_flash_write.txt"
#===============================================================================
RLXSTS=$(ps -W | grep "rlx_probe_driver.exe" | grep -v "grep" | wc -l)
echo $RLXSTS
JLKSTS=$(ps -W | grep "JLinkGDBServer.exe" | grep -v "grep" | wc -l)
echo $JLKSTS
echo $CURRENT_UTILITY_DIR
#===============================================================================
#make the new string for being written
if [ $RLXSTS = 1 ]
then
echo "probe get"
#-------------------------------------------
LINE_NUMBER=$(grep -n "monitor reset " $GDBSCPTFILE | awk -F":" '{print $1}')
DEFAULT_STR=$(grep -n "monitor reset " $GDBSCPTFILE | awk -F":" '{print $2}')
#echo $LINE_NUMBER
echo $DEFAULT_STR
STRLEN_DFT=$(expr length "$DEFAULT_STR")
DEFAULT_STR="#monitor reset 1"
echo $DEFAULT_STR
#-------------------------------------------
SED_PARA="$LINE_NUMBER""c""$DEFAULT_STR"
sed -i "$SED_PARA" $GDBSCPTFILE
#===========================================
LINE_NUMBER=$(grep -n "monitor sleep " $GDBSCPTFILE | awk -F":" '{print $1}')
DEFAULT_STR=$(grep -n "monitor sleep " $GDBSCPTFILE | awk -F":" '{print $2}')
#echo $LINE_NUMBER
echo $DEFAULT_STR
STRLEN_DFT=$(expr length "$DEFAULT_STR")
DEFAULT_STR="#monitor sleep 20"
echo $DEFAULT_STR
#-------------------------------------------
SED_PARA="$LINE_NUMBER""c""$DEFAULT_STR"
sed -i "$SED_PARA" $GDBSCPTFILE
else
if [ $JLKSTS = 1 ]
then
echo "jlink get"
#-------------------------------------------
LINE_NUMBER=$(grep -n "monitor reset " $GDBSCPTFILE | awk -F":" '{print $1}')
DEFAULT_STR=$(grep -n "monitor reset " $GDBSCPTFILE | awk -F":" '{print $2}')
#echo $LINE_NUMBER
echo $DEFAULT_STR
STRLEN_DFT=$(expr length "$DEFAULT_STR")
DEFAULT_STR="monitor reset 1"
echo $DEFAULT_STR
#-------------------------------------------
SED_PARA="$LINE_NUMBER""c""$DEFAULT_STR"
sed -i "$SED_PARA" $GDBSCPTFILE
#===========================================
LINE_NUMBER=$(grep -n "monitor sleep " $GDBSCPTFILE | awk -F":" '{print $1}')
DEFAULT_STR=$(grep -n "monitor sleep " $GDBSCPTFILE | awk -F":" '{print $2}')
#echo $LINE_NUMBER
echo $DEFAULT_STR
STRLEN_DFT=$(expr length "$DEFAULT_STR")
DEFAULT_STR="monitor sleep 20"
echo $DEFAULT_STR
#-------------------------------------------
SED_PARA="$LINE_NUMBER""c""$DEFAULT_STR"
sed -i "$SED_PARA" $GDBSCPTFILE
fi
fi
#===============================================================================

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flasher/openocd/SetupGDB_NORMAL.sh Normal file
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#!/bin/sh
#===============================================================================
CURRENT_UTILITY_DIR=$(pwd)
echo "..."
echo $CURRENT_UTILITY_DIR
RAMFILENAME="./application/Debug/bin/ram_all.bin"
echo $RAMFILENAME
#RAMFILENAME="ram_2.bin"
GDBSCPTFILE="../../../component/soc/realtek/8195a/misc/gcc_utility/rtl_gdb_flash_write.txt"
#===============================================================================
#get file size
RAM_FILE_SIZE=$(stat -c %s $RAMFILENAME)
RAM_FILE_SIZE_HEX=`echo "obase=16; $RAM_FILE_SIZE"|bc`
echo "size "$RAM_FILE_SIZE" --> 0x"$RAM_FILE_SIZE_HEX
echo "set \$RamFileSize = 0x$RAM_FILE_SIZE_HEX" > fwsize.gdb
exit

BIN
flasher/openocd/ram_all.bin Normal file
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Binary file not shown.

57
flasher/openocd/rtl_gdb_debug.txt Normal file
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# GDB script for loading ram.bin process
#===============================================================================
#set GDB connection
set remotetimeout 100000
target remote :2331
#===============================================================================
#Message display setting
#disable all messages
set verbose off
set complaints 0
set confirm off
set exec-done-display off
show exec-done-display
set trace-commands off
#set debug aix-thread off
#set debug dwarf2-die 0
set debug displaced off
set debug expression 0
set debug frame 0
set debug infrun 0
set debug observer 0
set debug overload 0
set debugvarobj 0
set pagination off
set print address off
set print symbol-filename off
set print symbol off
set print pretty off
set print object off
#set debug notification off
set debug parser off
set debug remote 0
#===============================================================================
monitor reset 1
monitor sleep 20
monitor clrbp
#===============================================================================
#Load flash download file
file ./build/obj/application.axf
#skip sdram init, it has been init in openocd config
set {int}0x40000210=0x211157
#x /1xw 0x40000210
b main
continue
clear main
#Load the file
#lo

58
flasher/openocd/rtl_gdb_debug_jlink.txt Normal file
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# GDB script for loading ram.bin process
#===============================================================================
#set GDB connection
set remotetimeout 100000
target remote :2331
#===============================================================================
#Message display setting
#disable all messages
set verbose off
set complaints 0
set confirm off
set exec-done-display off
show exec-done-display
set trace-commands off
#set debug aix-thread off
#set debug dwarf2-die 0
set debug displaced off
set debug expression 0
set debug frame 0
set debug infrun 0
set debug observer 0
set debug overload 0
set debugvarobj 0
set pagination off
set print address off
set print symbol-filename off
set print symbol off
set print pretty off
set print object off
#set debug notification off
set debug parser off
set debug remote 0
#===============================================================================
monitor reset 1
monitor sleep 20
monitor clrbp
#===============================================================================
#Load flash download file
file ./build/obj/application.axf
#file ./application/Debug/bin/application.axf
#skip sdram init, it has been init in openocd config
set {int}0x40000210=0x211157
#x /1xw 0x40000210
b main
continue
clear main
#Load the file
#lo

57
flasher/openocd/rtl_gdb_debug_openocd.txt Normal file
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# GDB script for loading ram.bin process
#===============================================================================
#set GDB connection
set remotetimeout 100000
target remote :3333
#===============================================================================
#Message display setting
#disable all messages
set verbose off
set complaints 0
set confirm off
set exec-done-display off
show exec-done-display
set trace-commands off
#set debug aix-thread off
#set debug dwarf2-die 0
set debug displaced off
set debug expression 0
set debug frame 0
set debug infrun 0
set debug observer 0
set debug overload 0
set debugvarobj 0
set pagination off
set print address off
set print symbol-filename off
set print symbol off
set print pretty off
set print object off
#set debug notification off
set debug parser off
set debug remote 0
#===============================================================================
monitor reset init
monitor sleep 20
monitor halt
#===============================================================================
#Load flash download file
file ./application/Debug/bin/application.axf
#skip sdram init, it has been init in openocd config
set {int}0x40000210=0x211157
#x /1xw 0x40000210
b main
continue
clear main
#Load the file
#lo

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flasher/openocd/rtl_gdb_flash_write.txt Normal file
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# GDB script for loading ram.bin process
#===============================================================================
#set GDB connection
set remotetimeout 100000
target remote :2331
#===============================================================================
#set file path
set $BINFILE = "./application/Debug/bin/ram_all.bin"
#===============================================================================
#Message display setting
#disable all messages
set verbose off
set complaints 0
set confirm off
set exec-done-display off
show exec-done-display
set trace-commands off
#set debug aix-thread off
#set debug dwarf2-die 0
set debug displaced off
set debug expression 0
set debug frame 0
set debug infrun 0
set debug observer 0
set debug overload 0
set debugvarobj 0
set pagination off
set print address off
set print symbol-filename off
set print symbol off
set print pretty off
set print object off
#set debug notification off
set debug parser off
set debug remote 0
#===============================================================================
#set JTAG and external SRAM
monitor reset 1
monitor sleep 20
monitor clrbp
#===============================================================================
#Variables declaration (1)
#binary file size
set $RamFileSize = 0x0000
source fwsize.gdb
printf "-------------------------------\n"
printf "RamFileSize: %x\n",$RamFileSize
printf "-------------------------------\n"
#===============================================================================
set $FLASHDATBUFSIZE = 0x800
#===============================================================================
#define PERI_ON_BASE 0x40000000
set $PERI_ON_BASE = 0x40000000
#define REG_SOC_PERI_FUNC0_EN 0x0218
set $REG_SOC_PERI_FUNC0_EN = 0x0210
#define SPI_FLASH_BASE 0x4000000
set $SPI_FLASH_BASE = 0x98000000
#------------------------------------------------------------------
set $Temp = 0x0
#===============================================================================
#Load flash download file
file ../../../component/soc/realtek/8195a/misc/gcc_utility/target_NORMAL.axf
#Load the file
lo
printf "Load flash controller.\n"
#===============================================================================
#Set for executing flash controller funciton
set $Temp = {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
p /x $Temp
set $Temp = ($Temp | (0x01 << 27))
p /x $Temp
set {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN) = $Temp
printf "....\n"
printf "wakeup bit(%x):%x\n", ($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN), {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
#===============================================================================
#Direct the startup wake function to flash program function
#the function pointer address
#set $testpointer = 0x200006b4
#set $testpointer2 = 0x200006b8
#set $FuntionPointer = 0x200006c4
#set $FPTemp = 0x200a08e9
#set {int}($FuntionPointer) = $FPTemp
#printf "testpointer(%x):%x\n", $testpointer, {int}$testpointer
#printf "testpointer2(%x):%x\n", $testpointer2, {int}$testpointer2
#printf "FuntionPointer(%x):%x\n", $FuntionPointer, {int}$FuntionPointer
#===============================================================================
#Load file
# restore filename [binary] bias start end
# Restore the contents of file filename into memory.
# The restore command can automatically recognize any known bfd file format, except for raw binary.
# To restore a raw binary file you must specify the optional keyword binary after the filename.
#===============================================================================
set $LoopNum = ($RamFileSize / $FLASHDATBUFSIZE)
printf "LoopNum = %x\n", $LoopNum
set $TailSize = ($RamFileSize % $FLASHDATBUFSIZE)
printf "TailSize = %x\n", $TailSize
printf "global variables\n"
set $FLASHDATSRC = 0x0
set $FILESTARTADDR = 0X0
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
#b RtlFlashProgram:StartOfFlashBlockWrite
b rtl_flash_download.c:489
b rtl_flash_download.c:524
#b Rtl_flash_control.c:RtlFlashProgram
#continue to 489
c
# Mode 0: erase full chip, Mode 1: skip calibration section and erase to firmware size
set EraseMode=1
print EraseMode
set FirmwareSize=$RamFileSize
print FirmwareSize
#continue to 524
c
#printf "...\n"
set $FLASHDATSRC = FlashDatSrc
printf "FlashDatSrc:%x\n", $FLASHDATSRC
printf "FlashBlockWriteSize "
set FlashBlockWriteSize = $FLASHDATBUFSIZE
#p /x FlashBlockWriteSize
printf "FlashBlockWriteSize:%x\n", FlashBlockWriteSize
printf "FlashAddrForWrite"
set FlashAddrForWrite = 0x0
printf "Flash write start...\n"
set $LoopCnt = 0
while ($LoopCnt < $LoopNum)
p /x FlashAddrForWrite
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
c
printf "FILEENDADDR"
p /x $FILEENDADDR
set FlashBlockWriteSize = $FLASHDATBUFSIZE
set FlashAddrForWrite = $FILEENDADDR
set $FILESTARTADDR = $FILEENDADDR
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
set $LoopCnt = $LoopCnt + 0x01
end
#set FlashBlockWriteSize = $FLASHDATBUFSIZE
#set FlashAddrForWrite = $FILEENDADDR
#set $FILESTARTADDR = $FILEENDADDR
set $FILEENDADDR = $FILESTARTADDR + $TailSize
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
c
#Set complete flas
set FlashWriteComplete = 0x1
printf "dump for check\n"
set $LoopCnt = 0
set $dumpaddr = 0
set $dumpstartaddr = $SPI_FLASH_BASE
set $dumpendaddr = $SPI_FLASH_BASE + $RamFileSize
printf "start addr of dumping"
p /x $dumpstartaddr
printf "end addr of dumping"
p /x $dumpendaddr
dump binary memory ./application/Debug/bin/dump.bin $dumpstartaddr $dumpendaddr
delete
b rtl_flash_download.c:556
c
quit
#===============================================================================

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flasher/openocd/rtl_gdb_flash_write_jlink.txt Normal file
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# GDB script for loading ram.bin process
#===============================================================================
#set GDB connection
set remotetimeout 100000
target remote :2331
#===============================================================================
#set file path
set $BINFILE = "./application/Debug/bin/ram_all.bin"
#===============================================================================
#Message display setting
#disable all messages
set verbose off
set complaints 0
set confirm off
set exec-done-display off
show exec-done-display
set trace-commands off
#set debug aix-thread off
#set debug dwarf2-die 0
set debug displaced off
set debug expression 0
set debug frame 0
set debug infrun 0
set debug observer 0
set debug overload 0
set debugvarobj 0
set pagination off
set print address off
set print symbol-filename off
set print symbol off
set print pretty off
set print object off
#set debug notification off
set debug parser off
set debug remote 0
#===============================================================================
#set JTAG and external SRAM
monitor reset 1
monitor sleep 20
monitor clrbp
#===============================================================================
#Variables declaration (1)
#binary file size
set $RamFileSize = 0x0000
source fwsize.gdb
printf "-------------------------------\n"
printf "RamFileSize: %x\n",$RamFileSize
printf "-------------------------------\n"
#===============================================================================
set $FLASHDATBUFSIZE = 0x800
#===============================================================================
#define PERI_ON_BASE 0x40000000
set $PERI_ON_BASE = 0x40000000
#define REG_SOC_PERI_FUNC0_EN 0x0218
set $REG_SOC_PERI_FUNC0_EN = 0x0210
#define SPI_FLASH_BASE 0x4000000
set $SPI_FLASH_BASE = 0x98000000
#------------------------------------------------------------------
set $Temp = 0x0
#===============================================================================
#Load flash download file
file ../../../component/soc/realtek/8195a/misc/gcc_utility/target_NORMAL.axf
#Load the file
lo
printf "Load flash controller.\n"
#===============================================================================
#Set for executing flash controller funciton
set $Temp = {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
p /x $Temp
set $Temp = ($Temp | (0x01 << 27))
p /x $Temp
set {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN) = $Temp
printf "....\n"
printf "wakeup bit(%x):%x\n", ($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN), {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
#===============================================================================
#Direct the startup wake function to flash program function
#the function pointer address
#set $testpointer = 0x200006b4
#set $testpointer2 = 0x200006b8
#set $FuntionPointer = 0x200006c4
#set $FPTemp = 0x200a08e9
#set {int}($FuntionPointer) = $FPTemp
#printf "testpointer(%x):%x\n", $testpointer, {int}$testpointer
#printf "testpointer2(%x):%x\n", $testpointer2, {int}$testpointer2
#printf "FuntionPointer(%x):%x\n", $FuntionPointer, {int}$FuntionPointer
#===============================================================================
#Load file
# restore filename [binary] bias start end
# Restore the contents of file filename into memory.
# The restore command can automatically recognize any known bfd file format, except for raw binary.
# To restore a raw binary file you must specify the optional keyword binary after the filename.
#===============================================================================
set $LoopNum = ($RamFileSize / $FLASHDATBUFSIZE)
printf "LoopNum = %x\n", $LoopNum
set $TailSize = ($RamFileSize % $FLASHDATBUFSIZE)
printf "TailSize = %x\n", $TailSize
printf "global variables\n"
set $FLASHDATSRC = 0x0
set $FILESTARTADDR = 0X0
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
#b RtlFlashProgram:StartOfFlashBlockWrite
b rtl_flash_download.c:489
b rtl_flash_download.c:524
#b Rtl_flash_control.c:RtlFlashProgram
#continue to 489
c
# Mode 0: erase full chip, Mode 1: skip calibration section and erase to firmware size
set EraseMode=1
print EraseMode
set FirmwareSize=$RamFileSize
print FirmwareSize
#continue to 524
c
#printf "...\n"
set $FLASHDATSRC = FlashDatSrc
printf "FlashDatSrc:%x\n", $FLASHDATSRC
printf "FlashBlockWriteSize "
set FlashBlockWriteSize = $FLASHDATBUFSIZE
#p /x FlashBlockWriteSize
printf "FlashBlockWriteSize:%x\n", FlashBlockWriteSize
printf "FlashAddrForWrite"
set FlashAddrForWrite = 0x0
printf "Flash write start...\n"
set $LoopCnt = 0
while ($LoopCnt < $LoopNum)
p /x FlashAddrForWrite
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
c
printf "FILEENDADDR"
p /x $FILEENDADDR
set FlashBlockWriteSize = $FLASHDATBUFSIZE
set FlashAddrForWrite = $FILEENDADDR
set $FILESTARTADDR = $FILEENDADDR
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
set $LoopCnt = $LoopCnt + 0x01
end
#set FlashBlockWriteSize = $FLASHDATBUFSIZE
#set FlashAddrForWrite = $FILEENDADDR
#set $FILESTARTADDR = $FILEENDADDR
set $FILEENDADDR = $FILESTARTADDR + $TailSize
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
c
#Set complete flas
set FlashWriteComplete = 0x1
printf "dump for check\n"
set $LoopCnt = 0
set $dumpaddr = 0
set $dumpstartaddr = $SPI_FLASH_BASE
set $dumpendaddr = $SPI_FLASH_BASE + $RamFileSize
printf "start addr of dumping"
p /x $dumpstartaddr
printf "end addr of dumping"
p /x $dumpendaddr
dump binary memory ./application/Debug/bin/dump.bin $dumpstartaddr $dumpendaddr
delete
b rtl_flash_download.c:556
c
quit
#===============================================================================

198
flasher/openocd/rtl_gdb_flash_write_openocd.txt Normal file
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# GDB script for loading ram.bin process
#===============================================================================
#set GDB connection
set remotetimeout 100000
target remote :3333
#===============================================================================
#set file path
set $BINFILE = "./application/Debug/bin/ram_all.bin"
#===============================================================================
#Message display setting
#disable all messages
set verbose off
set complaints 0
set confirm off
set exec-done-display off
show exec-done-display
set trace-commands off
#set debug aix-thread off
#set debug dwarf2-die 0
set debug displaced off
set debug expression 0
set debug frame 0
set debug infrun 0
set debug observer 0
set debug overload 0
set debugvarobj 0
set pagination off
set print address off
set print symbol-filename off
set print symbol off
set print pretty off
set print object off
#set debug notification off
set debug parser off
set debug remote 0
#===============================================================================
#set JTAG and external SRAM
monitor reset init
monitor halt
monitor sleep 20
#===============================================================================
#Variables declaration (1)
#binary file size
set $RamFileSize = 0x0000
source fwsize.gdb
printf "-------------------------------\n"
printf "RamFileSize: %x\n",$RamFileSize
printf "-------------------------------\n"
#===============================================================================
set $FLASHDATBUFSIZE = 0x800
#===============================================================================
#define PERI_ON_BASE 0x40000000
set $PERI_ON_BASE = 0x40000000
#define REG_SOC_PERI_FUNC0_EN 0x0218
set $REG_SOC_PERI_FUNC0_EN = 0x0210
#define SPI_FLASH_BASE 0x4000000
set $SPI_FLASH_BASE = 0x98000000
#------------------------------------------------------------------
set $Temp = 0x0
#===============================================================================
#Load flash download file
file ../../../component/soc/realtek/8195a/misc/gcc_utility/target_NORMAL.axf
#Load the file
lo
printf "Load flash controller.\n"
#===============================================================================
#Set for executing flash controller funciton
set $Temp = {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
p /x $Temp
set $Temp = ($Temp | (0x01 << 27))
p /x $Temp
set {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN) = $Temp
printf "....\n"
printf "wakeup bit(%x):%x\n", ($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN), {int}($PERI_ON_BASE+$REG_SOC_PERI_FUNC0_EN)
#===============================================================================
#Direct the startup wake function to flash program function
#the function pointer address
#set $testpointer = 0x200006b4
#set $testpointer2 = 0x200006b8
#set $FuntionPointer = 0x200006c4
#set $FPTemp = 0x200a08e9
#set {int}($FuntionPointer) = $FPTemp
#printf "testpointer(%x):%x\n", $testpointer, {int}$testpointer
#printf "testpointer2(%x):%x\n", $testpointer2, {int}$testpointer2
#printf "FuntionPointer(%x):%x\n", $FuntionPointer, {int}$FuntionPointer
#===============================================================================
#Load file
# restore filename [binary] bias start end
# Restore the contents of file filename into memory.
# The restore command can automatically recognize any known bfd file format, except for raw binary.
# To restore a raw binary file you must specify the optional keyword binary after the filename.
#===============================================================================
set $LoopNum = ($RamFileSize / $FLASHDATBUFSIZE)
printf "LoopNum = %x\n", $LoopNum
set $TailSize = ($RamFileSize % $FLASHDATBUFSIZE)
printf "TailSize = %x\n", $TailSize
printf "global variables\n"
set $FLASHDATSRC = 0x0
set $FILESTARTADDR = 0X0
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
#b RtlFlashProgram:StartOfFlashBlockWrite
b rtl_flash_download.c:489
b rtl_flash_download.c:524
#b Rtl_flash_control.c:RtlFlashProgram
#continue to 489
c
# Mode 0: erase full chip, Mode 1: skip calibration section and erase to firmware size
set EraseMode=1
print EraseMode
set FirmwareSize=$RamFileSize
print FirmwareSize
#continue to 524
c
#printf "...\n"
set $FLASHDATSRC = FlashDatSrc
printf "FlashDatSrc:%x\n", $FLASHDATSRC
printf "FlashBlockWriteSize "
set FlashBlockWriteSize = $FLASHDATBUFSIZE
#p /x FlashBlockWriteSize
printf "FlashBlockWriteSize:%x\n", FlashBlockWriteSize
printf "FlashAddrForWrite"
set FlashAddrForWrite = 0x0
printf "Flash write start...\n"
set $LoopCnt = 0
while ($LoopCnt < $LoopNum)
p /x FlashAddrForWrite
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
c
printf "FILEENDADDR"
p /x $FILEENDADDR
set FlashBlockWriteSize = $FLASHDATBUFSIZE
set FlashAddrForWrite = $FILEENDADDR
set $FILESTARTADDR = $FILEENDADDR
set $FILEENDADDR = $FILESTARTADDR + $FLASHDATBUFSIZE
set $LoopCnt = $LoopCnt + 0x01
end
#set FlashBlockWriteSize = $FLASHDATBUFSIZE
#set FlashAddrForWrite = $FILEENDADDR
#set $FILESTARTADDR = $FILEENDADDR
set $FILEENDADDR = $FILESTARTADDR + $TailSize
restore ./application/Debug/bin/ram_all.bin binary ($FLASHDATSRC-$FILESTARTADDR) $FILESTARTADDR $FILEENDADDR
c
#Set complete flas
set FlashWriteComplete = 0x1
printf "dump for check\n"
set $LoopCnt = 0
set $dumpaddr = 0
set $dumpstartaddr = $SPI_FLASH_BASE
set $dumpendaddr = $SPI_FLASH_BASE + $RamFileSize
printf "start addr of dumping"
p /x $dumpstartaddr
printf "end addr of dumping"
p /x $dumpendaddr
dump binary memory ./application/Debug/bin/dump.bin $dumpstartaddr $dumpendaddr
delete
b rtl_flash_download.c:556
c
quit
#===============================================================================

113
flasher/openocd/rtl_gdb_ramdebug.txt Normal file
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# GDB script for loading ram.bin process
#===============================================================================
#set GDB connection
set remotetimeout 100000
target remote :2331
#===============================================================================
#Message display setting
#disable all messages
set verbose off
set complaints 0
set confirm off
set exec-done-display off
show exec-done-display
set trace-commands off
#set debug aix-thread off
#set debug dwarf2-die 0
set debug displaced off
set debug expression 0
set debug frame 0
set debug infrun 0
set debug observer 0
set debug overload 0
set debugvarobj 0
set pagination off
set print address off
set print symbol-filename off
set print symbol off
set print pretty off
set print object off
#set debug notification off
set debug parser off
set debug remote 0
#===============================================================================
monitor reset 1
monitor sleep 20
monitor clrbp
#===============================================================================
#Init SDRAM here
# init System
monitor MemU32 0x40000014=0x00000021
monitor sleep 10
monitor MemU32 0x40000304=0x1fc00002
monitor sleep 10
monitor MemU32 0x40000250=0x00000400
monitor sleep 10
monitor MemU32 0x40000340=0x00000000
monitor sleep 10
monitor MemU32 0x40000230=0x0000dcc4
monitor sleep 10
monitor MemU32 0x40000210=0x00011117
monitor sleep 10
monitor MemU32 0x40000210=0x00011157
monitor sleep 10
monitor MemU32 0x400002c0=0x00110011
monitor sleep 10
monitor MemU32 0x40000320=0xffffffff
monitor sleep 10
# init SDRAM
monitor MemU32 0x40000040=0x00fcc702
monitor sleep 10
monitor MemU32 0x40000040
monitor MemU32 0x40005224=0x00000001
monitor sleep 10
monitor MemU32 0x40005004=0x00000208
monitor sleep 10
monitor MemU32 0x40005008=0xffffd000
monitor sleep 13
monitor MemU32 0x40005020=0x00000022
monitor sleep 13
monitor MemU32 0x40005010=0x09006201
monitor sleep 13
monitor MemU32 0x40005014=0x00002611
monitor sleep 13
monitor MemU32 0x40005018=0x00068413
monitor sleep 13
monitor MemU32 0x4000501c=0x00000042
monitor sleep 13
monitor MemU32 0x4000500c=0x700
monitor sleep 20
monitor MemU32 0x40005000=0x1
monitor sleep 100
monitor MemU32 0x40005000
monitor MemU32 0x4000500c=0x600
monitor sleep 30
monitor MemU32 0x40005008=0x00000000
monitor sleep 3
monitor MemU32 0x40000300=0x0006005e
monitor sleep 3
#===============================================================================
#Load flash download file
#file ./application/Debug/bin/application.axf
file ./build/obj/application.axf
#boot from ram, igonore loading flash
monitor MemU32 0x40000210=0x8011157
#Load the file
lo
#Run to main
b main
continue
clear main

112
flasher/openocd/rtl_gdb_ramdebug_jlink.txt Normal file
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# GDB script for loading ram.bin process
#===============================================================================
#set GDB connection
set remotetimeout 100000
target remote :2331
#===============================================================================
#Message display setting
#disable all messages
set verbose off
set complaints 0
set confirm off
set exec-done-display off
show exec-done-display
set trace-commands off
#set debug aix-thread off
#set debug dwarf2-die 0
set debug displaced off
set debug expression 0
set debug frame 0
set debug infrun 0
set debug observer 0
set debug overload 0
set debugvarobj 0
set pagination off
set print address off
set print symbol-filename off
set print symbol off
set print pretty off
set print object off
#set debug notification off
set debug parser off
set debug remote 0
#===============================================================================
monitor reset 1
monitor sleep 20
monitor clrbp
#===============================================================================
#Init SDRAM here
# init System
monitor MemU32 0x40000014=0x00000021
monitor sleep 10
monitor MemU32 0x40000304=0x1fc00002
monitor sleep 10
monitor MemU32 0x40000250=0x00000400
monitor sleep 10
monitor MemU32 0x40000340=0x00000000
monitor sleep 10
monitor MemU32 0x40000230=0x0000dcc4
monitor sleep 10
monitor MemU32 0x40000210=0x00011117
monitor sleep 10
monitor MemU32 0x40000210=0x00011157
monitor sleep 10
monitor MemU32 0x400002c0=0x00110011
monitor sleep 10
monitor MemU32 0x40000320=0xffffffff
monitor sleep 10
# init SDRAM
monitor MemU32 0x40000040=0x00fcc702
monitor sleep 10
monitor MemU32 0x40000040
monitor MemU32 0x40005224=0x00000001
monitor sleep 10
monitor MemU32 0x40005004=0x00000208
monitor sleep 10
monitor MemU32 0x40005008=0xffffd000
monitor sleep 13
monitor MemU32 0x40005020=0x00000022
monitor sleep 13
monitor MemU32 0x40005010=0x09006201
monitor sleep 13
monitor MemU32 0x40005014=0x00002611
monitor sleep 13
monitor MemU32 0x40005018=0x00068413
monitor sleep 13
monitor MemU32 0x4000501c=0x00000042
monitor sleep 13
monitor MemU32 0x4000500c=0x700
monitor sleep 20
monitor MemU32 0x40005000=0x1
monitor sleep 100
monitor MemU32 0x40005000
monitor MemU32 0x4000500c=0x600
monitor sleep 30
monitor MemU32 0x40005008=0x00000000
monitor sleep 3
monitor MemU32 0x40000300=0x0006005e
monitor sleep 3
#===============================================================================
#Load flash download file
file ./application/Debug/bin/application.axf
#boot from ram, igonore loading flash
monitor MemU32 0x40000210=0x8011157
#Load the file
lo
#Run to main
b main
continue
clear main

59
flasher/openocd/rtl_gdb_ramdebug_openocd.txt Normal file
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# GDB script for loading ram.bin process
#===============================================================================
#set GDB connection
set remotetimeout 100000
target remote :3333
#===============================================================================
#Message display setting
#disable all messages
set verbose off
set complaints 0
set confirm off
set exec-done-display off
show exec-done-display
set trace-commands off
#set debug aix-thread off
#set debug dwarf2-die 0
set debug displaced off
set debug expression 0
set debug frame 0
set debug infrun 0
set debug observer 0
set debug overload 0
set debugvarobj 0
set pagination off
set print address off
set print symbol-filename off
set print symbol off
set print pretty off
set print object off
#set debug notification off
set debug parser off
set debug remote 0
#===============================================================================
monitor reset init
monitor sleep 20
monitor halt
#===============================================================================
#Load flash download file
file ./application/Debug/bin/application.axf
#boot from ram, igonore loading flash
set {int}0x40000210=0x8011157
#Load the file
lo
#Run to main
b main
continue
clear main

BIN
flasher/openocd/target_NORMAL.axf Normal file
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Binary file not shown.

BIN
flasher/openocd/target_NORMALB.axf Normal file
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Binary file not shown.

BIN
flasher/openocd/target_NORMALC.axf Normal file
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336
flasher/rtl8710.ocd Normal file
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#
# OpenOCD script for RTL8710
# Copyright (C) 2016 Rebane, rebane@alkohol.ee
#
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME rtl8710
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x800
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x2ba01477
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x10001000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# adapter_khz 500
adapter_nsrst_delay 100
if {![using_hla]} {
cortex_m reset_config sysresetreq
}
set rtl8710_flasher_firmware_ptr 0x10001000
set rtl8710_flasher_buffer 0x10008000
set rtl8710_flasher_buffer_size 262144
set rtl8710_flasher_sector_size 4096
array set rtl8710_flasher_code {
0 0xB671B57F 1 0x25FF4B58 2 0x6B196B1A 3 0x7040F042 4 0x69D96318 5 0xF4414E55
6 0x69D97480 7 0xF8D361DC 8 0xF8C32120 9 0xF8D35120 10 0xF8C31124 11 0x47B05124
12 0x47B04E4F 13 0x47984B4F 14 0x60104A4F 15 0x484F47B0 16 0x60012100 17 0x2C006804
18 0x4D4DD0FC 19 0xB93E682E 20 0x60264C49 21 0x47B04E46 22 0x47984B46 23 0xE7ED6020
24 0x2B01682B 25 0x4E42D109 26 0x4C4647B0 27 0x47A02006 28 0x47904A45 29 0x47A020C7
30 0x682AE00D 31 0xD10E2A02 32 0x47B04E3B 33 0x20064C3F 34 0x483F47A0 35 0x493F4780
36 0x68084D3F 37 0x47B047A8 38 0x47A02004 39 0x6828E7CE 40 0xD1132803 41 0x47A04C32
42 0x24004838 43 0x4E396805 44 0x68311960 45 0xD206428C 46 0x4B384A37 47 0x221018A1
48 0x34104798 49 0x4D2AE7F3 50 0xE7B847A8 51 0x29046829 52 0x2400D11B 53 0x6806482F
54 0xD2B042B4 55 0x47A84D24 56 0x20064E28 57 0x4B2847B0 58 0x49284798 59 0x680A4B2A
60 0x18A018E1 61 0xF44F4B2A 62 0x47987280 63 0x200447A8 64 0xF50447B0 65 0x47A87480
66 0x682CE7E4 67 0xD1232C05 68 0x47984B17 69 0x4D1F2400 70 0x4294682A 71 0x481BD28F
72 0x68012210 73 0x18604E1D 74 0x47B04669 75 0x1B19682B 76 0xBF282910 77 0x23002110
78 0xD011428B 79 0xF81D4A16 80 0x18A05003 81 0x42B55CC6 82 0x3301D101 83 0x4A15E7F4
84 0x60112101 85 0xE7726054 86 0x25014E12 87 0xE76E6035 88 0x47A84D03 89 0xE7D63410
90 0x40000200 91 0x100011BD 92 0x100013DD 93 0x10001289 94 0x1000800C 95 0x10008000
96 0x10008004 97 0x1000130D 98 0x100013ED 99 0x10008010 100 0x10001335 101 0x10008014
102 0x10008020 103 0x10001221 104 0x10001375 105 0x10008008 106 0x6A5A4B03 107 0xD0FB0512
108 0x0060F893 109 0xBF004770 110 0x40006000 111 0x6B194B17 112 0xF4416B1A 113 0x63187040
114 0x69186919 115 0x0110F041 116 0xF8D36119 117 0x220000C0 118 0x0106F020 119 0x00C0F8D3
120 0x10C0F8C3 121 0x00C0F8D3 122 0x0101F040 123 0x00C0F8D3 124 0x10C0F8C3 125 0x43BCF503
126 0x609A6899 127 0x20016AD9 128 0x691962DA 129 0x69596118 130 0x61592102 131 0x619A6999
132 0x61DA69D9 133 0x64DA6CD9 134 0xBF004770 135 0x40000200 136 0x460EB570 137 0xB34A4614
138 0xF3C04B15 139 0x681A4507 140 0x7240F44F 141 0x685A601A 142 0xF3C02103 143 0x2C102207
144 0x2410BF28 145 0x605CB2C0 146 0x1060F883 147 0x5060F883 148 0xF8832101 149 0xF8832060
150 0x689A0060 151 0x60992500 152 0x47984B08 153 0x35015570 154 0x42A2B2AA 155 0x4804D3F8
156 0xF0116A81 157 0xD1FA0301 158 0x60836881 159 0xBD704620 160 0x40006000 161 0x100011A9
162 0x4C10B5F8 163 0x68232003 164 0x7340F44F 165 0x68636023 166 0x60602101 167 0x68A3229F
168 0x60A14D0B 169 0x2060F884 170 0x460647A8 171 0x460747A8 172 0x040347A8 173 0x2707EA43
174 0x0006EA47 175 0x4B036AA1 176 0x0201F011 177 0x6899D1FA 178 0xBDF8609A 179 0x40006000
180 0x100011A9 181 0x4C0BB510 182 0x68232001 183 0x7340F44F 184 0x68636023 185 0x60602105
186 0x60A068A2 187 0xF8844A06 188 0x47901060 189 0x4B036AA1 190 0x0201F011 191 0x6899D1FA
192 0xBD10609A 193 0x40006000 194 0x100011A9 195 0x21014B08 196 0xF44F681A 197 0x601A7280
198 0x6099689A 199 0x0060F883 200 0x48036A9A 201 0x0101F012 202 0x6883D1FA 203 0x47706081
204 0x40006000 205 0x21014B0E 206 0xF44F681A 207 0x601A7280 208 0x2220689A 209 0xF8836099
210 0xF3C02060 211 0xF3C04107 212 0xB2C02207 213 0x1060F883 214 0x2060F883 215 0x0060F883
216 0x4A036A99 217 0x0001F011 218 0x6893D1FA 219 0x47706090 220 0x40006000 221 0xB36AB530
222 0x25014B17 223 0xF44F681C 224 0x601C7480 225 0x2402689C 226 0xF883609D 227 0xF3C04060
228 0xF3C04507 229 0xB2C02407 230 0x5060F883 231 0x7F80F5B2 232 0xF44FBF28 233 0xF8837280
234 0xF8834060 235 0x20000060 236 0x4C095C0D 237 0xF8843001 238 0xB2855060 239 0xD3F74295
240 0x07496A99 241 0x6AA0D5FC 242 0xF0104B03 243 0xD1FA0101 244 0x60996898 245 0xBD304610
246 0x40006000 247 0x4B02B508 248 0x07C04798 249 0xBD08D4FB 250 0x100012D5 251 0x4B04B508
252 0xF0004798 253 0xB2C10002 254 0xD0F82900 255 0xBF00BD08 256 0x100012D5
}
set rtl8710_flasher_command_read_id 0
set rtl8710_flasher_command_mass_erase 1
set rtl8710_flasher_command_sector_erase 2
set rtl8710_flasher_command_read 3
set rtl8710_flasher_command_write 4
set rtl8710_flasher_command_verify 5
set rtl8710_flasher_ready 0
set rtl8710_flasher_capacity 0
set rtl8710_flasher_auto_erase 0
set rtl8710_flasher_auto_verify 0
set rtl8710_flasher_auto_erase_sector 0xFFFFFFFF
proc rtl8710_flasher_init {} {
global rtl8710_flasher_firmware_ptr
global rtl8710_flasher_buffer
global rtl8710_flasher_capacity
global rtl8710_flasher_ready
global rtl8710_flasher_code
if {[expr {$rtl8710_flasher_ready == 0}]} {
echo "initializing RTL8710 flasher"
halt
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
array2mem rtl8710_flasher_code 32 $rtl8710_flasher_firmware_ptr [array size rtl8710_flasher_code]
reg faultmask 0x01
reg sp 0x20000000
reg pc $rtl8710_flasher_firmware_ptr
resume
rtl8710_flasher_wait
set id [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set rtl8710_flasher_capacity [expr {2 ** [expr {($id >> 16) & 0xFF}]}]
set rtl8710_flasher_ready 1
echo "RTL8710 flasher initialized"
}
return ""
}
proc rtl8710_flasher_mrw {reg} {
set value ""
mem2array value 32 $reg 1
return $value(0)
}
proc rtl8710_flasher_wait {} {
global rtl8710_flasher_buffer
while {[rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x00}]]} { }
}
proc rtl8710_flasher_load_block {local_filename offset len} {
global rtl8710_flasher_buffer
load_image $local_filename [expr {$rtl8710_flasher_buffer + 0x20 - $offset}] bin [expr {$rtl8710_flasher_buffer + 0x20}] $len
}
proc rtl8710_flasher_read_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_read
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_read
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
error "read error, offset $offset"
}
}
proc rtl8710_flasher_write_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_write
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_write
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
error "write error, offset $offset"
}
}
proc rtl8710_flasher_verify_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_verify
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_verify
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set status [expr {$status + $offset}]
error "verify error, offset $status"
}
}
proc rtl8710_flash_read_id {} {
global rtl8710_flasher_buffer
global rtl8710_flasher_capacity
global rtl8710_flasher_command_read_id
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_read_id
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set id [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set manufacturer_id [format "0x%02X" [expr {$id & 0xFF}]]
set memory_type [format "0x%02X" [expr {($id >> 8) & 0xFF}]]
set memory_capacity [expr {2 ** [expr {($id >> 16) & 0xFF}]}]
echo "manufacturer ID: $manufacturer_id, memory type: $memory_type, memory capacity: $memory_capacity bytes"
}
proc rtl8710_flash_mass_erase {} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_mass_erase
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_mass_erase
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
}
proc rtl8710_flash_sector_erase {offset} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_sector_erase
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_sector_erase
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
}
proc rtl8710_flash_read {local_filename loc size} {
global rtl8710_flasher_buffer
global rtl8710_flasher_buffer_size
rtl8710_flasher_init
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "read offset $flash_offset"
rtl8710_flasher_read_block $flash_offset $len
dump_image _rtl8710_flasher.bin [expr {$rtl8710_flasher_buffer + 0x20}] $len
exec dd conv=notrunc if=_rtl8710_flasher.bin "of=$local_filename" bs=1 "seek=$offset"
echo "read $len bytes"
}
}
proc rtl8710_flash_write {local_filename loc} {
global rtl8710_flasher_buffer_size
global rtl8710_flasher_sector_size
global rtl8710_flasher_auto_erase
global rtl8710_flasher_auto_verify
global rtl8710_flasher_auto_erase_sector
rtl8710_flasher_init
set sector 0
set size [file size $local_filename]
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "write offset $flash_offset"
rtl8710_flasher_load_block $local_filename $offset $len
if {[expr {$rtl8710_flasher_auto_erase != 0}]} {
for {set i $flash_offset} {$i < [expr {$flash_offset + $len}]} {incr i} {
set sector [expr {$i / $rtl8710_flasher_sector_size}]
if {[expr {$rtl8710_flasher_auto_erase_sector != $sector}]} {
echo "erase sector $sector"
rtl8710_flash_sector_erase [expr {$sector * $rtl8710_flasher_sector_size}]
set rtl8710_flasher_auto_erase_sector $sector
}
}
}
rtl8710_flasher_write_block $flash_offset $len
echo "wrote $len bytes"
if {[expr {$rtl8710_flasher_auto_verify != 0}]} {
echo "verify offset $flash_offset"
rtl8710_flasher_verify_block $flash_offset $len
}
}
}
proc rtl8710_flash_verify {local_filename loc} {
global rtl8710_flasher_buffer_size
rtl8710_flasher_init
set size [file size $local_filename]
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "read offset $flash_offset"
rtl8710_flasher_load_block $local_filename $offset $len
echo "verify offset $flash_offset"
rtl8710_flasher_verify_block $flash_offset $len
}
}
proc rtl8710_flash_auto_erase {on} {
global rtl8710_flasher_auto_erase
if {[expr {$on != 0}]} {
set rtl8710_flasher_auto_erase 1
echo "auto erase on"
} else {
set rtl8710_flasher_auto_erase 0
echo "auto erase off"
}
}
proc rtl8710_flash_auto_verify {on} {
global rtl8710_flasher_auto_verify
if {[expr {$on != 0}]} {
set rtl8710_flasher_auto_verify 1
echo "auto verify on"
} else {
set rtl8710_flasher_auto_verify 0
echo "auto verify off"
}
}
proc rtl8710_reboot {} {
echo "# Set processor clock to default before system reset"
mww 0x40000014 0x00000021
sleep 10
echo "# Reboot (system reset)"
mww 0xE000ED0C 0x05FA0007
}

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/******************************************************************************
*
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of version 2 of the GNU General Public License as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
*
*
******************************************************************************/
#ifndef __BASIC_TYPES_H__
#define __BASIC_TYPES_H__
//#define PLATFORM_FREERTOS
#include <stdint.h>
#define PLATFORM_LITTLE_ENDIAN 0
#define PLATFORM_BIG_ENDIAN 1
#define SYSTEM_ENDIAN PLATFORM_LITTLE_ENDIAN
#define SUCCESS 0
#define FAIL (-1)
#undef _SUCCESS
#define _SUCCESS 1
#undef _FAIL
#define _FAIL 0
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE (!FALSE)
#endif
#define _TRUE TRUE
#define _FALSE FALSE
#ifndef NULL
#define NULL 0
#endif
#ifdef __GNUC__
#define __weak __attribute__((weak))
#define likely(x) __builtin_expect ((x), 1)
#define unlikely(x) __builtin_expect ((x), 0)
#endif
typedef unsigned int uint;
typedef signed int sint;
#ifdef __ICCARM__
typedef signed long long __int64_t;
typedef unsigned long long __uint64_t;
#endif
#define s8 int8_t
#define u8 uint8_t
#define s16 int16_t
#define u16 uint16_t
#define s32 int32_t
#define u32 uint32_t
#define s64 int64_t
#define u64 uint64_t
#ifdef CONFIG_MBED_ENABLED
typedef unsigned int BOOL;
#else
#ifndef BOOL
typedef unsigned char BOOL;
#endif
#ifndef bool
#ifndef __cplusplus
typedef unsigned char bool;
#endif
#endif
#endif
#define UCHAR uint8_t
#define USHORT uint16_t
#define UINT uint32_t
#define ULONG uint32_t
typedef struct { volatile int counter; } atomic_t;
typedef enum _RTK_STATUS_ {
_EXIT_SUCCESS = 0,
_EXIT_FAILURE = 1
}RTK_STATUS, *PRTK_STATUS;
#define IN
#define OUT
#define VOID void
#define INOUT
#define NDIS_OID uint
#define NDIS_STATUS uint
#ifndef PVOID
typedef void * PVOID;
#endif
typedef u32 dma_addr_t;
typedef void (*proc_t)(void*);
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef __kernel_size_t SIZE_T;
typedef __kernel_ssize_t SSIZE_T;
#define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field)
#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T))
#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1)
#define SIZE_PTR SIZE_T
#define SSIZE_PTR SSIZE_T
#ifndef ON
#define ON 1
#endif
#ifndef OFF
#define OFF 0
#endif
#ifndef ENABLE
#define ENABLE 1
#endif
#ifndef DISABLE
#define DISABLE 0
#endif
#define BIT0 0x0001
#define BIT1 0x0002
#define BIT2 0x0004
#define BIT3 0x0008
#define BIT4 0x0010
#define BIT5 0x0020
#define BIT6 0x0040
#define BIT7 0x0080
#define BIT8 0x0100
#define BIT9 0x0200
#define BIT10 0x0400
#define BIT11 0x0800
#define BIT12 0x1000
#define BIT13 0x2000
#define BIT14 0x4000
#define BIT15 0x8000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define BIT_(__n) (1<<(__n))
#ifndef BIT
#define BIT(__n) (1<<(__n))
#endif
#if defined (__ICCARM__)
#define STRINGIFY(s) #s
#define SECTION(_name) _Pragma( STRINGIFY(location=_name))
#define ALIGNMTO(_bound) _Pragma( STRINGIFY(data_alignment=##_bound##))
#define _PACKED_ __packed
#define _LONG_CALL_
#define _LONG_CALL_ROM_
#define _WEAK __weak
#else
#define SECTION(_name) __attribute__ ((__section__(_name)))
#define ALIGNMTO(_bound) __attribute__ ((aligned (_bound)))
#define _PACKED_ __attribute__ ((packed))
#define _LONG_CALL_ __attribute__ ((long_call))
#define _LONG_CALL_ROM_ _LONG_CALL_
#define _WEAK __attribute__ ((weak))
#endif
//port from fw by thomas
// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness
#define SWAP32(x) ((u32)( \
(((u32)(x) & (u32)0x000000ff) << 24) | \
(((u32)(x) & (u32)0x0000ff00) << 8) | \
(((u32)(x) & (u32)0x00ff0000) >> 8) | \
(((u32)(x) & (u32)0xff000000) >> 24)))
#define WAP16(x) ((u16)( \
(((u16)(x) & (u16)0x00ff) << 8) | \
(((u16)(x) & (u16)0xff00) >> 8)))
#if SYSTEM_ENDIAN == PLATFORM_LITTLE_ENDIAN
#ifndef rtk_le16_to_cpu
#define rtk_cpu_to_le32(x) ((u32)(x))
#define rtk_le32_to_cpu(x) ((u32)(x))
#define rtk_cpu_to_le16(x) ((u16)(x))
#define rtk_le16_to_cpu(x) ((u16)(x))
#define rtk_cpu_to_be32(x) SWAP32((x))
#define rtk_be32_to_cpu(x) SWAP32((x))
#define rtk_cpu_to_be16(x) WAP16((x))
#define rtk_be16_to_cpu(x) WAP16((x))
#endif
#elif SYSTEM_ENDIAN == PLATFORM_BIG_ENDIAN
#ifndef rtk_le16_to_cpu
#define rtk_cpu_to_le32(x) SWAP32((x))
#define rtk_le32_to_cpu(x) SWAP32((x))
#define rtk_cpu_to_le16(x) WAP16((x))
#define rtk_le16_to_cpu(x) WAP16((x))
#define rtk_cpu_to_be32(x) ((__u32)(x))
#define rtk_be32_to_cpu(x) ((__u32)(x))
#define rtk_cpu_to_be16(x) ((__u16)(x))
#define rtk_be16_to_cpu(x) ((__u16)(x))
#endif
#endif
/*
* Call endian free function when
* 1. Read/write packet content.
* 2. Before write integer to IO.
* 3. After read integer from IO.
*/
//
// Byte Swapping routine.
//
#define EF1Byte (u8)
#define EF2Byte le16_to_cpu
#define EF4Byte le32_to_cpu
//
// Read LE format data from memory
//
#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr)))
#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr)))
#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr)))
//
// Write LE data to memory
//
#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val)
#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val)
#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val)
//
// Example:
// BIT_LEN_MASK_32(0) => 0x00000000
// BIT_LEN_MASK_32(1) => 0x00000001
// BIT_LEN_MASK_32(2) => 0x00000003
// BIT_LEN_MASK_32(32) => 0xFFFFFFFF
//
#define BIT_LEN_MASK_32(__BitLen) \
(0xFFFFFFFF >> (32 - (__BitLen)))
//
// Example:
// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
//
#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \
(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))
//
// Description:
// Return 4-byte value in host byte ordering from
// 4-byte pointer in litten-endian system.
//
#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
(EF4Byte(*((u32 *)(__pStart))))
//
// Description:
// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to
// 4-byte value in host byte ordering.
//
#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_32(__BitLen) \
)
//
// Description:
// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering
// and return the result in 4-byte value in host byte ordering.
//
#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P4BYTE_TO_HOST_4BYTE(__pStart) \
& \
( ~ BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \
)
//
// Description:
// Set subfield of little-endian 4-byte value to specified value.
//
#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u32 *)(__pStart)) = \
EF4Byte( \
LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_16(__BitLen) \
(0xFFFF >> (16 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \
(BIT_LEN_MASK_16(__BitLen) << (__BitOffset))
#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
(EF2Byte(*((u16 *)(__pStart))))
#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_16(__BitLen) \
)
#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P2BYTE_TO_HOST_2BYTE(__pStart) \
& \
( ~ BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \
)
#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u16 *)(__pStart)) = \
EF2Byte( \
LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \
);
#define BIT_LEN_MASK_8(__BitLen) \
(0xFF >> (8 - (__BitLen)))
#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \
(BIT_LEN_MASK_8(__BitLen) << (__BitOffset))
#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
(EF1Byte(*((u8 *)(__pStart))))
#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
( \
( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \
& \
BIT_LEN_MASK_8(__BitLen) \
)
#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
( \
LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
& \
( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \
)
#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \
*((u8 *)(__pStart)) = \
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \
| \
( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \
);
//pclint
#define LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
( \
LE_P1BYTE_TO_HOST_1BYTE(__pStart) \
)
//pclint
#define SET_BITS_TO_LE_1BYTE_8BIT(__pStart, __BitOffset, __BitLen, __Value) \
{ \
*((pu1Byte)(__pStart)) = \
EF1Byte( \
LE_BITS_CLEARED_TO_1BYTE_8BIT(__pStart, __BitOffset, __BitLen) \
| \
((u1Byte)__Value) \
); \
}
// Get the N-bytes aligment offset from the current length
#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment))
typedef unsigned char BOOLEAN,*PBOOLEAN;
#define TEST_FLAG(__Flag,__testFlag) (((__Flag) & (__testFlag)) != 0)
#define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag)
#define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag))
#define CLEAR_FLAGS(__Flag) ((__Flag) = 0)
#define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags))
/* Define compilor specific symbol */
//
// inline function
//
#if defined ( __ICCARM__ )
#define __inline__ inline
#define __inline inline
#define __inline_definition //In dialect C99, inline means that a function's definition is provided
//only for inlining, and that there is another definition
//(without inline) somewhere else in the program.
//That means that this program is incomplete, because if
//add isn't inlined (for example, when compiling without optimization),
//then main will have an unresolved reference to that other definition.
// Do not inline function is the function body is defined .c file and this
// function will be called somewhere else, otherwise there is compile error
#elif defined ( __CC_ARM )
#define __inline__ __inline //__linine__ is not supported in keil compilor, use __inline instead
#define inline __inline
#define __inline_definition // for dialect C99
#elif defined ( __GNUC__ )
#define __inline__ inline
#define __inline inline
#define __inline_definition inline
#endif
//
// pack
//
#if defined (__ICCARM__)
#define RTW_PACK_STRUCT_BEGIN _Pragma( STRINGIFY(pack(1)))
#define RTW_PACK_STRUCT_STRUCT
#define RTW_PACK_STRUCT_END _Pragma( STRINGIFY(pack()))
//#define RTW_PACK_STRUCT_USE_INCLUDES
#elif defined (__CC_ARM)
#define RTW_PACK_STRUCT_BEGIN __packed
#define RTW_PACK_STRUCT_STRUCT
#define RTW_PACK_STRUCT_END
#elif defined (__GNUC__)
#define RTW_PACK_STRUCT_BEGIN
#define RTW_PACK_STRUCT_STRUCT __attribute__ ((__packed__))
#define RTW_PACK_STRUCT_END
#elif defined(PLATFORM_WINDOWS)
#define RTW_PACK_STRUCT_BEGIN
#define RTW_PACK_STRUCT_STRUCT
#define RTW_PACK_STRUCT_END
#define RTW_PACK_STRUCT_USE_INCLUDES
#endif
// for standard library
#ifdef __ICCARM__
#define __extension__ /* Ignore */
#define __restrict /* Ignore */
#endif
typedef struct _RAM_START_FUNCTION_ {
VOID (*RamStartFun) (VOID);
}RAM_START_FUNCTION, *PRAM_START_FUNCTION;
typedef struct _RAM_FUNCTION_START_TABLE_ {
VOID (*RamStartFun) (VOID);
VOID (*RamWakeupFun) (VOID);
VOID (*RamPatchFun0) (VOID);
VOID (*RamPatchFun1) (VOID);
VOID (*RamPatchFun2) (VOID);
}RAM_FUNCTION_START_TABLE, *PRAM_FUNCTION_START_TABLE;
#endif// __BASIC_TYPES_H__

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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#ifndef _CORTEX_H_
#define _CORTEX_H_
#include <stdint.h>
typedef struct{
volatile uint32_t ISER[8];
uint32_t RESERVED1[24];
volatile uint32_t ICER[8];
uint32_t RESERVED2[24];
volatile uint32_t ISPR[8];
uint32_t RESERVED3[24];
volatile uint32_t ICPR[8];
uint32_t RESERVED4[24];
volatile uint32_t IABR[8];
uint32_t RESERVED5[56];
volatile uint32_t IPR[32];
}NVIC_TypeDef;
typedef struct{
uint32_t RESERVED1[2];
volatile uint32_t ACTLR;
uint32_t RESERVED2[829];
volatile const uint32_t CPUID;
volatile uint32_t ICSR;
volatile uint32_t VTOR;
volatile uint32_t AIRCR;
volatile uint32_t SCR;
volatile uint32_t CCR;
volatile uint32_t SHPR[3];
volatile uint32_t SHCSR;
volatile uint32_t CFSR;
volatile uint32_t HFSR;
volatile uint32_t DFSR;
volatile uint32_t MMFAR;
volatile uint32_t BFAR;
volatile uint32_t AFSR;
volatile const uint32_t PFR[2];
volatile const uint32_t DFR;
volatile const uint32_t AFR;
volatile const uint32_t MMFR[4];
volatile const uint32_t ISAR[5];
uint32_t RESERVED3[5];
volatile uint32_t CPACR;
}SCB_TypeDef;
#define NVIC ((NVIC_TypeDef *)0xE000E100)
#define SCB ((SCB_TypeDef *)0xE000E000)
// SCB_AIRCR
#define SCB_AIRCR_VECTRESET (((uint32_t)0x0001) << 0)
#define SCB_AIRCR_VECTCLRACTIVE (((uint32_t)0x0001) << 1)
#define SCB_AIRCR_SYSRESETREQ (((uint32_t)0x0001) << 2)
#define SCB_AIRCR_PRIGROUP (((uint32_t)0x0007) << 8)
#define SCB_AIRCR_VECTKEY (((uint32_t)0xFFFF) << 16)
#define SCB_AIRCR_VECTKEYSTAT (((uint32_t)0xFFFF) << 16)
// SCB_CPACR
#define SCB_CPACR_CP10 (((uint32_t)0x03) << 20)
#define SCB_CPACR_CP11 (((uint32_t)0x03) << 22)
#define cortex_interrupt_set_priority(i, p) (NVIC->IPR[(i) >> 2] = ((NVIC->IPR[(i) >> 2] & ~(((uint32_t)0xFF) << (((i) & 0x03) << 3))) | (((uint32_t)p) << (((i) & 0x03) << 3))))
#define cortex_interrupt_enable(i) (NVIC->ISER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
#define cortex_interrupt_disable(i) (NVIC->ICER[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
#define cortex_interrupt_clear(i) (NVIC->ICPR[(i) >> 5] = (((uint32_t)0x01) << ((i) & 0x1F)))
#define cortex_interrupts_disable() __asm__("cpsid f")
#define cortex_interrupts_enable() __asm__("cpsie f")
#define interrupts_disable() __asm__("cpsid f")
#define interrupts_enable() __asm__("cpsie f")
#define CORTEX_ISR(n) _CORTEX_ISR(n)
#define _CORTEX_ISR(n) void __attribute__((interrupt)) CORTEX_INTERRUPT_##n##_Handler()
void cortex_bootstrap(void *start) __attribute__ ((noreturn));
void cortex_reboot() __attribute__ ((noreturn));
#endif

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proc cortex_bootstrap {start} {
# disable interrupts
reg faultmask 0x01
set vectors ""
mem2array vectors 32 $start 2
reg sp $vectors(0)
reg pc $vectors(1)
resume
}
proc cortex_reboot {} {
mww 0xE000ED0C 0x05FA0007
}

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SECTIONS
{
__vectors_table = 0x0;
Reset_Handler = 0x101;
NMI_Handler = 0x109;
HardFault_Handler = 0x10d;
MemManage_Handler = 0x121;
BusFault_Handler = 0x125;
UsageFault_Handler = 0x129;
HalLogUartInit = 0x201;
HalSerialPutcRtl8195a = 0x2d9;
HalSerialGetcRtl8195a = 0x309;
HalSerialGetIsrEnRegRtl8195a = 0x329;
HalSerialSetIrqEnRegRtl8195a = 0x335;
HalCpuClkConfig = 0x341;
HalGetCpuClk = 0x355;
HalRomInfo = 0x39d;
HalGetRomInfo = 0x3b5;
HalResetVsr = 0x3c5;
HalDelayUs = 0x899;
HalNMIHandler = 0x8e1;
HalHardFaultHandler = 0x911;
HalMemManageHandler = 0xc09;
HalBusFaultHandler = 0xc39;
HalUsageFaultHandler = 0xc69;
HalUart0PinCtrlRtl8195A = 0xcfd;
HalUart1PinCtrlRtl8195A = 0xdc9;
HalUart2PinCtrlRtl8195A = 0xe9d;
HalSPI0PinCtrlRtl8195A = 0xf75;
HalSPI1PinCtrlRtl8195A = 0x1015;
HalSPI2PinCtrlRtl8195A = 0x10e5;
HalSPI0MCSPinCtrlRtl8195A = 0x11b5;
HalI2C0PinCtrlRtl8195A = 0x1275;
HalI2C1PinCtrlRtl8195A = 0x1381;
HalI2C2PinCtrlRtl8195A = 0x1459;
HalI2C3PinCtrlRtl8195A = 0x1529;
HalI2S0PinCtrlRtl8195A = 0x1639;
HalI2S1PinCtrlRtl8195A = 0x176d;
HalPCM0PinCtrlRtl8195A = 0x1845;
HalPCM1PinCtrlRtl8195A = 0x1949;
HalSDIODPinCtrlRtl8195A = 0x1a1d;
HalSDIOHPinCtrlRtl8195A = 0x1a6d;
HalMIIPinCtrlRtl8195A = 0x1ab9;
HalWLLEDPinCtrlRtl8195A = 0x1b51;
HalWLANT0PinCtrlRtl8195A = 0x1c0d;
HalWLANT1PinCtrlRtl8195A = 0x1c61;
HalWLBTCOEXPinCtrlRtl8195A = 0x1cb5;
HalWLBTCMDPinCtrlRtl8195A = 0x1d05;
HalNFCPinCtrlRtl8195A = 0x1d59;
HalPWM0PinCtrlRtl8195A = 0x1da9;
HalPWM1PinCtrlRtl8195A = 0x1ead;
HalPWM2PinCtrlRtl8195A = 0x1fb5;
HalPWM3PinCtrlRtl8195A = 0x20b1;
HalETE0PinCtrlRtl8195A = 0x21b9;
HalETE1PinCtrlRtl8195A = 0x22c1;
HalETE2PinCtrlRtl8195A = 0x23c9;
HalETE3PinCtrlRtl8195A = 0x24d1;
HalEGTIMPinCtrlRtl8195A = 0x25d9;
HalSPIFlashPinCtrlRtl8195A = 0x2679;
HalSDRPinCtrlRtl8195A = 0x2725;
HalJTAGPinCtrlRtl8195A = 0x280d;
HalTRACEPinCtrlRtl8195A = 0x2861;
HalLOGUartPinCtrlRtl8195A = 0x28b9;
HalLOGUartIRPinCtrlRtl8195A = 0x291d;
HalSICPinCtrlRtl8195A = 0x2981;
HalEEPROMPinCtrlRtl8195A = 0x29d9;
HalDEBUGPinCtrlRtl8195A = 0x2a31;
HalPinCtrlRtl8195A = 0x2b39;
SpicRxCmdRtl8195A = 0x2e5d;
SpicWaitBusyDoneRtl8195A = 0x2ea5;
SpicGetFlashStatusRtl8195A = 0x2eb5;
SpicWaitWipDoneRtl8195A = 0x2f55;
SpicTxCmdRtl8195A = 0x2f6d;
SpicSetFlashStatusRtl8195A = 0x2fc1;
SpicCmpDataForCalibrationRtl8195A = 0x3049;
SpicLoadInitParaFromClockRtl8195A = 0x3081;
SpicInitRtl8195A = 0x30e5;
SpicEraseFlashRtl8195A = 0x31bd;
SpiFlashApp = 0x3279;
HalPeripheralIntrHandle = 0x33b5;
HalSysOnIntrHandle = 0x3439;
HalWdgIntrHandle = 0x3485;
HalTimer0IntrHandle = 0x34d5;
HalTimer1IntrHandle = 0x3525;
HalI2C3IntrHandle = 0x3575;
HalTimer2To7IntrHandle = 0x35c5;
HalSpi0IntrHandle = 0x3615;
HalGpioIntrHandle = 0x3665;
HalUart0IntrHandle = 0x36b5;
HalSpiFlashIntrHandle = 0x3705;
HalUsbOtgIntrHandle = 0x3755;
HalSdioHostIntrHandle = 0x37a5;
HalI2s0OrPcm0IntrHandle = 0x37f5;
HalI2s1OrPcm1IntrHandle = 0x3845;
HalWlDmaIntrHandle = 0x3895;
HalWlProtocolIntrHandle = 0x38e5;
HalCryptoIntrHandle = 0x3935;
HalGmacIntrHandle = 0x3985;
HalGdma0Ch0IntrHandle = 0x39d5;
HalGdma0Ch1IntrHandle = 0x3a25;
HalGdma0Ch2IntrHandle = 0x3a75;
HalGdma0Ch3IntrHandle = 0x3ac5;
HalGdma0Ch4IntrHandle = 0x3b15;
HalGdma0Ch5IntrHandle = 0x3b65;
HalGdma1Ch0IntrHandle = 0x3bb5;
HalGdma1Ch1IntrHandle = 0x3c05;
HalGdma1Ch2IntrHandle = 0x3c55;
HalGdma1Ch3IntrHandle = 0x3ca5;
HalGdma1Ch4IntrHandle = 0x3cf5;
HalGdma1Ch5IntrHandle = 0x3d45;
HalSdioDeviceIntrHandle = 0x3d95;
VectorTableInitRtl8195A = 0x3de5;
VectorTableInitForOSRtl8195A = 0x4019;
VectorIrqRegisterRtl8195A = 0x4029;
VectorIrqUnRegisterRtl8195A = 0x4091;
VectorIrqEnRtl8195A = 0x40f1;
VectorIrqDisRtl8195A = 0x418d;
_UartRxDmaIrqHandle = 0x422d;
HalRuartPutCRtl8195a = 0x4281;
HalRuartGetCRtl8195a = 0x429d;
HalRuartRTSCtrlRtl8195a = 0x42bd;
HalRuartGetDebugValueRtl8195a = 0x42e1;
HalRuartGetIMRRtl8195a = 0x43e1;
HalRuartSetIMRRtl8195a = 0x442d;
_UartIrqHandle = 0x4465;
HalRuartDmaInitRtl8195a = 0x4681;
HalRuartIntDisableRtl8195a = 0x4845;
HalRuartDeInitRtl8195a = 0x4855;
HalRuartIntEnableRtl8195a = 0x4985;
_UartTxDmaIrqHandle = 0x4995;
HalRuartRegIrqRtl8195a = 0x49d1;
HalRuartAdapterLoadDefRtl8195a = 0x4a4d;
HalRuartTxGdmaLoadDefRtl8195a = 0x4add;
HalRuartRxGdmaLoadDefRtl8195a = 0x4bc9;
RuartLock = 0x4cc9;
RuartUnLock = 0x4ced;
HalRuartIntSendRtl8195a = 0x4d09;
HalRuartDmaSendRtl8195a = 0x4e35;
HalRuartStopSendRtl8195a = 0x4f89;
HalRuartIntRecvRtl8195a = 0x504d;
HalRuartDmaRecvRtl8195a = 0x51ad;
HalRuartStopRecvRtl8195a = 0x52cd;
RuartIsTimeout = 0x5385;
HalRuartSendRtl8195a = 0x53b1;
HalRuartRecvRtl8195a = 0x5599;
RuartResetRxFifoRtl8195a = 0x5751;
HalRuartResetRxFifoRtl8195a = 0x5775;
HalRuartInitRtl8195a = 0x5829;
HalGdmaOnOffRtl8195a = 0x5df1;
HalGdmaChIsrEnAndDisRtl8195a = 0x5e0d;
HalGdmaChEnRtl8195a = 0x5e51;
HalGdmaChDisRtl8195a = 0x5e6d;
HalGdamChInitRtl8195a = 0x5e91;
HalGdmaChSetingRtl8195a = 0x5ebd;
HalGdmaChIsrCleanRtl8195a = 0x6419;
HalGdmaChCleanAutoSrcRtl8195a = 0x64a1;
HalGdmaChCleanAutoDstRtl8195a = 0x6501;
HalEFUSEPowerSwitch8195AROM = 0x6561;
HALEFUSEOneByteReadROM = 0x65f9;
HALEFUSEOneByteWriteROM = 0x6699;
rtl_memcmpb_v1_00 = 0x681d;
rtl_random_v1_00 = 0x6861;
rtl_align_to_be32_v1_00 = 0x6881;
rtl_memsetw_v1_00 = 0x6899;
rtl_memsetb_v1_00 = 0x68ad;
rtl_memcpyw_v1_00 = 0x68bd;
rtl_memcpyb_v1_00 = 0x68dd;
rtl_memDump_v1_00 = 0x68f5;
rtl_AES_set_encrypt_key = 0x6901;
rtl_cryptoEngine_AES_set_decrypt_key = 0x6c11;
rtl_cryptoEngine_set_security_mode_v1_00 = 0x6c95;
rtl_cryptoEngine_init_v1_00 = 0x6ea9;
rtl_cryptoEngine_exit_v1_00 = 0x7055;
rtl_cryptoEngine_reset_v1_00 = 0x70b1;
rtl_cryptoEngine_v1_00 = 0x70ed;
rtl_crypto_cipher_init_v1_00 = 0x7c69;
rtl_crypto_cipher_encrypt_v1_00 = 0x7c89;
rtl_crypto_cipher_decrypt_v1_00 = 0x7cad;
HalSsiPinmuxEnableRtl8195a = 0x7cd5;
HalSsiEnableRtl8195a = 0x7e45;
HalSsiDisableRtl8195a = 0x7ef9;
HalSsiLoadSettingRtl8195a = 0x7fad;
HalSsiSetInterruptMaskRtl8195a = 0x8521;
HalSsiGetInterruptMaskRtl8195a = 0x85c9;
HalSsiSetSclkPolarityRtl8195a = 0x863d;
HalSsiSetSclkPhaseRtl8195a = 0x8715;
HalSsiWriteRtl8195a = 0x87e9;
HalSsiSetDeviceRoleRtl8195a = 0x8861;
HalSsiSetRxFifoThresholdLevelRtl8195a = 0x88c9;
HalSsiSetTxFifoThresholdLevelRtl8195a = 0x8941;
HalSsiReadRtl8195a = 0x89b9;
HalSsiGetRxFifoLevelRtl8195a = 0x8a2d;
HalSsiGetTxFifoLevelRtl8195a = 0x8aa5;
HalSsiGetStatusRtl8195a = 0x8b1d;
HalSsiWriteableRtl8195a = 0x8b91;
HalSsiReadableRtl8195a = 0x8c09;
HalSsiBusyRtl8195a = 0x8c81;
HalSsiReadInterruptRtl8195a = 0x8cf9;
HalSsiWriteInterruptRtl8195a = 0x8efd;
HalSsiSetSlaveEnableRegisterRtl8195a = 0x9009;
HalSsiGetInterruptStatusRtl8195a = 0x90d9;
HalSsiInterruptEnableRtl8195a = 0x914d;
HalSsiInterruptDisableRtl8195a = 0x9299;
HalSsiGetRawInterruptStatusRtl8195a = 0x93e9;
HalSsiGetSlaveEnableRegisterRtl8195a = 0x945d;
HalSsiInitRtl8195a = 0x94d1;
_SsiReadInterrupt = 0x9ba5;
_SsiWriteInterrupt = 0x9db1;
_SsiIrqHandle = 0x9eb1;
HalI2CWrite32 = 0xa061;
HalI2CRead32 = 0xa09d;
HalI2CDeInit8195a = 0xa0dd;
HalI2CSendRtl8195a = 0xa1f1;
HalI2CReceiveRtl8195a = 0xa25d;
HalI2CEnableRtl8195a = 0xa271;
HalI2CIntrCtrl8195a = 0xa389;
HalI2CReadRegRtl8195a = 0xa3a1;
HalI2CWriteRegRtl8195a = 0xa3b1;
HalI2CSetCLKRtl8195a = 0xa3c5;
HalI2CMassSendRtl8195a = 0xa6e9;
HalI2CClrIntrRtl8195a = 0xa749;
HalI2CClrAllIntrRtl8195a = 0xa761;
HalI2CInit8195a = 0xa775;
HalI2CDMACtrl8195a = 0xaa31;
RtkI2CIoCtrl = 0xaa61;
RtkI2CPowerCtrl = 0xaa65;
HalI2COpInit = 0xaa69;
I2CIsTimeout = 0xac65;
I2CTXGDMAISRHandle = 0xb435;
I2CRXGDMAISRHandle = 0xb4c1;
RtkI2CIrqInit = 0xb54d;
RtkI2CIrqDeInit = 0xb611;
RtkI2CPinMuxInit = 0xb675;
RtkI2CPinMuxDeInit = 0xb7c9;
RtkI2CDMAInit = 0xb955;
RtkI2CInit = 0xbc95;
RtkI2CDMADeInit = 0xbdad;
RtkI2CDeInit = 0xbe4d;
RtkI2CSendUserAddr = 0xbee5;
RtkI2CSend = 0xc07d;
RtkI2CLoadDefault = 0xce51;
RtkSalI2COpInit = 0xcf21;
HalI2SWrite32 = 0xcf65;
HalI2SRead32 = 0xcf85;
HalI2SDeInitRtl8195a = 0xcfa9;
HalI2STxRtl8195a = 0xcfc9;
HalI2SRxRtl8195a = 0xd011;
HalI2SEnableRtl8195a = 0xd05d;
HalI2SIntrCtrlRtl8195a = 0xd0b1;
HalI2SReadRegRtl8195a = 0xd0d1;
HalI2SClrIntrRtl8195a = 0xd0dd;
HalI2SClrAllIntrRtl8195a = 0xd0fd;
HalI2SInitRtl8195a = 0xd11d;
GPIO_GetIPPinName_8195a = 0xd2e5;
GPIO_GetChipPinName_8195a = 0xd331;
GPIO_PullCtrl_8195a = 0xd39d;
GPIO_FuncOn_8195a = 0xd421;
GPIO_FuncOff_8195a = 0xd481;
GPIO_Int_Mask_8195a = 0xd4e9;
GPIO_Int_SetType_8195a = 0xd511;
HAL_GPIO_IrqHandler_8195a = 0xd5fd;
HAL_GPIO_MbedIrqHandler_8195a = 0xd645;
HAL_GPIO_UserIrqHandler_8195a = 0xd6a1;
HAL_GPIO_IntCtrl_8195a = 0xd6cd;
HAL_GPIO_Init_8195a = 0xd805;
HAL_GPIO_DeInit_8195a = 0xdac1;
HAL_GPIO_ReadPin_8195a = 0xdbd1;
HAL_GPIO_WritePin_8195a = 0xdc91;
HAL_GPIO_RegIrq_8195a = 0xddad;
HAL_GPIO_UnRegIrq_8195a = 0xddf5;
HAL_GPIO_UserRegIrq_8195a = 0xde15;
HAL_GPIO_UserUnRegIrq_8195a = 0xdef9;
HAL_GPIO_MaskIrq_8195a = 0xdfc1;
HAL_GPIO_UnMaskIrq_8195a = 0xe061;
HAL_GPIO_IntDebounce_8195a = 0xe101;
HAL_GPIO_GetIPPinName_8195a = 0xe1c1;
HAL_GPIO_PullCtrl_8195a = 0xe1c9;
DumpForOneBytes = 0xe259;
CmdRomHelp = 0xe419;
CmdWriteWord = 0xe491;
CmdDumpHelfWord = 0xe505;
CmdDumpWord = 0xe5f1;
CmdDumpByte = 0xe6f5;
CmdSpiFlashTool = 0xe751;
GetRomCmdNum = 0xe7a9;
CmdWriteByte = 0xe7ad;
Isspace = 0xe7ed;
Strtoul = 0xe801;
ArrayInitialize = 0xe8b1;
GetArgc = 0xe8c9;
GetArgv = 0xe8f9;
UartLogCmdExecute = 0xe95d;
UartLogShowBackSpace = 0xe9fd;
UartLogRecallOldCmd = 0xea39;
UartLogHistoryCmd = 0xea71;
UartLogCmdChk = 0xeadd;
UartLogIrqHandle = 0xebf5;
RtlConsolInit = 0xecc5;
RtlConsolTaskRom = 0xed49;
RtlExitConsol = 0xed79;
RtlConsolRom = 0xedcd;
HalTimerOpInit = 0xee0d;
HalTimerIrq2To7Handle = 0xee59;
HalGetTimerIdRtl8195a = 0xef09;
HalTimerInitRtl8195a = 0xef3d;
HalTimerDisRtl8195a = 0xf069;
HalTimerEnRtl8195a = 0xf089;
HalTimerReadCountRtl8195a = 0xf0a9;
HalTimerIrqClearRtl8195a = 0xf0bd;
HalTimerDumpRegRtl8195a = 0xf0d1;
VSprintf = 0xf129;
DiagPrintf = 0xf39d;
DiagSPrintf = 0xf3b9;
DiagSnPrintf = 0xf3d1;
prvDiagPrintf = 0xf3ed;
prvDiagSPrintf = 0xf40d;
_memcmp = 0xf429;
_memcpy = 0xf465;
_memset = 0xf511;
Rand = 0xf585;
_strncpy = 0xf60d;
_strcpy = 0xf629;
prvStrCpy = 0xf639;
_strlen = 0xf651;
_strnlen = 0xf669;
prvStrLen = 0xf699;
_strcmp = 0xf6b1;
_strncmp = 0xf6d1;
prvStrCmp = 0xf719;
StrUpr = 0xf749;
prvAtoi = 0xf769;
prvStrStr = 0xf7bd;
_strsep = 0xf7d5;
skip_spaces = 0xf815;
skip_atoi = 0xf831;
_parse_integer_fixup_radix = 0xf869;
_parse_integer = 0xf8bd;
simple_strtoull = 0xf915;
simple_strtoll = 0xf945;
simple_strtoul = 0xf965;
simple_strtol = 0xf96d;
_vsscanf = 0xf985;
_sscanf = 0xff71;
div_u64 = 0xff91;
div_s64 = 0xff99;
div_u64_rem = 0xffa1;
div_s64_rem = 0xffb1;
_strpbrk = 0xffc1;
_strchr = 0xffed;
aes_set_key = 0x10005;
aes_encrypt = 0x103d1;
aes_decrypt = 0x114a5;
AES_WRAP = 0x125c9;
AES_UnWRAP = 0x12701;
crc32_get = 0x12861;
arc4_byte = 0x12895;
rt_arc4_init = 0x128bd;
rt_arc4_crypt = 0x12901;
rt_md5_init = 0x131c1;
rt_md5_append = 0x131f5;
rt_md5_final = 0x1327d;
rt_md5_hmac = 0x132d5;
rtw_get_bit_value_from_ieee_value = 0x13449;
rtw_is_cckrates_included = 0x13475;
rtw_is_cckratesonly_included = 0x134b5;
rtw_check_network_type = 0x134dd;
rtw_set_fixed_ie = 0x1350d;
rtw_set_ie = 0x1352d;
rtw_get_ie = 0x1355d;
rtw_set_supported_rate = 0x13591;
rtw_get_rateset_len = 0x13611;
rtw_get_wpa_ie = 0x1362d;
rtw_get_wpa2_ie = 0x136c9;
rtw_get_wpa_cipher_suite = 0x13701;
rtw_get_wpa2_cipher_suite = 0x13769;
rtw_parse_wpa_ie = 0x137d1;
rtw_parse_wpa2_ie = 0x138ad;
rtw_get_sec_ie = 0x13965;
rtw_get_wps_ie = 0x13a15;
rtw_get_wps_attr = 0x13a99;
rtw_get_wps_attr_content = 0x13b49;
rtw_ieee802_11_parse_elems = 0x13b91;
str_2char2num = 0x13d9d;
key_2char2num = 0x13db9;
convert_ip_addr = 0x13dd1;
rom_psk_PasswordHash = 0x13e9d;
rom_psk_CalcGTK = 0x13ed5;
rom_psk_CalcPTK = 0x13f69;
wep_80211_encrypt = 0x14295;
wep_80211_decrypt = 0x142f5;
tkip_micappendbyte = 0x14389;
rtw_secmicsetkey = 0x143d9;
rtw_secmicappend = 0x14419;
rtw_secgetmic = 0x14435;
rtw_seccalctkipmic = 0x1449d;
tkip_phase1 = 0x145a5;
tkip_phase2 = 0x14725;
tkip_80211_encrypt = 0x14941;
tkip_80211_decrypt = 0x149d5;
aes1_encrypt = 0x14a8d;
aesccmp_construct_mic_iv = 0x14c65;
aesccmp_construct_mic_header1 = 0x14ccd;
aesccmp_construct_mic_header2 = 0x14d21;
aesccmp_construct_ctr_preload = 0x14db5;
aes_80211_encrypt = 0x14e29;
aes_80211_decrypt = 0x151ad;
_sha1_process_message_block = 0x155b9;
_sha1_pad_message = 0x15749;
rt_sha1_init = 0x157e5;
rt_sha1_update = 0x15831;
rt_sha1_finish = 0x158a9;
rt_hmac_sha1 = 0x15909;
rom_aes_128_cbc_encrypt = 0x15a65;
rom_aes_128_cbc_decrypt = 0x15ae1;
rom_rijndaelKeySetupEnc = 0x15b5d;
rom_aes_decrypt_init = 0x15c39;
rom_aes_internal_decrypt = 0x15d15;
rom_aes_decrypt_deinit = 0x16071;
rom_aes_encrypt_init = 0x16085;
rom_aes_internal_encrypt = 0x1609d;
rom_aes_encrypt_deinit = 0x16451;
bignum_init = 0x17b35;
bignum_deinit = 0x17b61;
bignum_get_unsigned_bin_len = 0x17b81;
bignum_get_unsigned_bin = 0x17b85;
bignum_set_unsigned_bin = 0x17c21;
bignum_cmp = 0x17cd1;
bignum_cmp_d = 0x17cd5;
bignum_add = 0x17cfd;
bignum_sub = 0x17d0d;
bignum_mul = 0x17d1d;
bignum_exptmod = 0x17d2d;
WPS_realloc = 0x17d51;
os_zalloc = 0x17d99;
rom_hmac_sha256_vector = 0x17dc1;
rom_hmac_sha256 = 0x17ebd;
rom_sha256_vector = 0x18009;
phy_CalculateBitShift = 0x18221;
PHY_SetBBReg_8195A = 0x18239;
PHY_QueryBBReg_8195A = 0x18279;
ROM_odm_QueryRxPwrPercentage = 0x1829d;
ROM_odm_EVMdbToPercentage = 0x182bd;
ROM_odm_SignalScaleMapping_8195A = 0x182e5;
ROM_odm_FalseAlarmCounterStatistics = 0x183cd;
ROM_odm_SetEDCCAThreshold = 0x18721;
ROM_odm_SetTRxMux = 0x18749;
ROM_odm_SetCrystalCap = 0x18771;
ROM_odm_GetDefaultCrytaltalCap = 0x187d5;
ROM_ODM_CfoTrackingReset = 0x187e9;
ROM_odm_CfoTrackingFlow = 0x18811;
curve25519_donna = 0x1965d;
aes_test_alignment_detection = 0x1a391;
aes_mode_reset = 0x1a3ed;
aes_ecb_encrypt = 0x1a3f9;
aes_ecb_decrypt = 0x1a431;
aes_cbc_encrypt = 0x1a469;
aes_cbc_decrypt = 0x1a579;
aes_cfb_encrypt = 0x1a701;
aes_cfb_decrypt = 0x1a9e5;
aes_ofb_crypt = 0x1acc9;
aes_ctr_crypt = 0x1af7d;
aes_encrypt_key128 = 0x1b289;
aes_encrypt_key192 = 0x1b2a5;
aes_encrypt_key256 = 0x1b2c1;
aes_encrypt_key = 0x1b2e1;
aes_decrypt_key128 = 0x1b351;
aes_decrypt_key192 = 0x1b36d;
aes_decrypt_key256 = 0x1b389;
aes_decrypt_key = 0x1b3a9;
aes_init = 0x1b419;
CRYPTO_chacha_20 = 0x1b41d;
CRYPTO_poly1305_init = 0x1bc25;
CRYPTO_poly1305_update = 0x1bd09;
CRYPTO_poly1305_finish = 0x1bd8d;
rom_sha512_starts = 0x1ceb5;
rom_sha512_update = 0x1d009;
rom_sha512_finish = 0x1d011;
rom_sha512 = 0x1d261;
rom_sha512_hmac_starts = 0x1d299;
rom_sha512_hmac_update = 0x1d35d;
rom_sha512_hmac_finish = 0x1d365;
rom_sha512_hmac_reset = 0x1d3b5;
rom_sha512_hmac = 0x1d3d1;
rom_sha512_hkdf = 0x1d40d;
rom_ed25519_gen_keypair = 0x1d501;
rom_ed25519_gen_signature = 0x1d505;
rom_ed25519_verify_signature = 0x1d51d;
rom_ed25519_crypto_sign_seed_keypair = 0x1d521;
rom_ed25519_crypto_sign_detached = 0x1d579;
rom_ed25519_crypto_sign_verify_detached = 0x1d655;
rom_ed25519_ge_double_scalarmult_vartime = 0x1f86d;
rom_ed25519_ge_frombytes_negate_vartime = 0x1fc35;
rom_ed25519_ge_p3_tobytes = 0x207d5;
rom_ed25519_ge_scalarmult_base = 0x20821;
rom_ed25519_ge_tobytes = 0x209e1;
rom_ed25519_sc_muladd = 0x20a2d;
rom_ed25519_sc_reduce = 0x2603d;
rtl_memchr_v1_00 = 0x28a4d;
rtl_memcmp_v1_00 = 0x28ae1;
rtl_memcpy_v1_00 = 0x28b49;
__aeabi_memcpy = 0x28b49;
__aeabi_memcpy4 = 0x28b49;
rtl_memmove_v1_00 = 0x28bed;
rtl_memset_v1_00 = 0x28cb5;
__aeabi_memset = 0x28cb5;
rtl_strcat_v1_00 = 0x28d49;
rtl_strchr_v1_00 = 0x28d91;
rtl_strcmp_v1_00 = 0x28e55;
rtl_strcpy_v1_00 = 0x28ec9;
rtl_strlen_v1_00 = 0x28f15;
rtl_strncat_v1_00 = 0x28f69;
rtl_strncmp_v1_00 = 0x28fc5;
rtl_strncpy_v1_00 = 0x2907d;
rtl_strstr_v1_00 = 0x293cd;
rtl_strsep_v1_00 = 0x2960d;
rtl_strtok_v1_00 = 0x29619;
rtl__strtok_r_v1_00 = 0x2962d;
rtl_strtok_r_v1_00 = 0x29691;
rtl_close_v1_00 = 0x29699;
rtl_fstat_v1_00 = 0x296ad;
rtl_isatty_v1_00 = 0x296c1;
rtl_lseek_v1_00 = 0x296d5;
rtl_open_v1_00 = 0x296e9;
rtl_read_v1_00 = 0x296fd;
rtl_write_v1_00 = 0x29711;
rtl_sbrk_v1_00 = 0x29725;
rtl_ltoa_v1_00 = 0x297bd;
rtl_ultoa_v1_00 = 0x29855;
rtl_dtoi_v1_00 = 0x298c5;
rtl_dtoi64_v1_00 = 0x29945;
rtl_dtoui_v1_00 = 0x299dd;
rtl_ftol_v1_00 = 0x299e5;
rtl_itof_v1_00 = 0x29a51;
rtl_itod_v1_00 = 0x29ae9;
rtl_i64tod_v1_00 = 0x29b79;
rtl_uitod_v1_00 = 0x29c55;
rtl_ftod_v1_00 = 0x29d2d;
rtl_dtof_v1_00 = 0x29de9;
rtl_uitof_v1_00 = 0x29e89;
rtl_fadd_v1_00 = 0x29f65;
rtl_fsub_v1_00 = 0x2a261;
rtl_fmul_v1_00 = 0x2a559;
rtl_fdiv_v1_00 = 0x2a695;
rtl_dadd_v1_00 = 0x2a825;
rtl_dsub_v1_00 = 0x2aed9;
rtl_dmul_v1_00 = 0x2b555;
rtl_ddiv_v1_00 = 0x2b8ad;
rtl_dcmpeq_v1_00 = 0x2be4d;
rtl_dcmplt_v1_00 = 0x2bebd;
rtl_dcmpgt_v1_00 = 0x2bf51;
rtl_dcmple_v1_00 = 0x2c049;
rtl_fcmplt_v1_00 = 0x2c139;
rtl_fcmpgt_v1_00 = 0x2c195;
rtl_cos_f32_v1_00 = 0x2c229;
rtl_sin_f32_v1_00 = 0x2c435;
rtl_fabs_v1_00 = 0x2c639;
rtl_fabsf_v1_00 = 0x2c641;
rtl_dtoa_r_v1_00 = 0x2c77d;
__rom_mallocr_init_v1_00 = 0x2d7d1;
rtl_free_r_v1_00 = 0x2d841;
rtl_malloc_r_v1_00 = 0x2da31;
rtl_realloc_r_v1_00 = 0x2df55;
rtl_memalign_r_v1_00 = 0x2e331;
rtl_valloc_r_v1_00 = 0x2e421;
rtl_pvalloc_r_v1_00 = 0x2e42d;
rtl_calloc_r_v1_00 = 0x2e441;
rtl_cfree_r_v1_00 = 0x2e4a9;
rtl_Balloc_v1_00 = 0x2e515;
rtl_Bfree_v1_00 = 0x2e571;
rtl_i2b_v1_00 = 0x2e585;
rtl_multadd_v1_00 = 0x2e599;
rtl_mult_v1_00 = 0x2e629;
rtl_pow5mult_v1_00 = 0x2e769;
rtl_hi0bits_v1_00 = 0x2e809;
rtl_d2b_v1_00 = 0x2e845;
rtl_lshift_v1_00 = 0x2e901;
rtl_cmp_v1_00 = 0x2e9bd;
rtl_diff_v1_00 = 0x2ea01;
rtl_sread_v1_00 = 0x2eae9;
rtl_seofread_v1_00 = 0x2eb39;
rtl_swrite_v1_00 = 0x2eb3d;
rtl_sseek_v1_00 = 0x2ebc1;
rtl_sclose_v1_00 = 0x2ec11;
rtl_sbrk_r_v1_00 = 0x2ec41;
rtl_fflush_r_v1_00 = 0x2ef8d;
rtl_vfprintf_r_v1_00 = 0x2f661;
rtl_fpclassifyd = 0x30c15;
CpkClkTbl = 0x30c68;
ROM_IMG1_VALID_PATTEN = 0x30c80;
SpicCalibrationPattern = 0x30c88;
SpicInitCPUCLK = 0x30c98;
BAUDRATE = 0x30ca8;
OVSR = 0x30d1c;
DIV = 0x30d90;
OVSR_ADJ = 0x30e04;
__AES_rcon = 0x30e78;
__AES_Te4 = 0x30ea0;
I2CDmaChNo = 0x312a0;
_GPIO_PinMap_Chip2IP_8195a = 0x312b4;
_GPIO_PinMap_PullCtrl_8195a = 0x3136c;
_GPIO_SWPORT_DDR_TBL = 0x31594;
_GPIO_EXT_PORT_TBL = 0x31598;
_GPIO_SWPORT_DR_TBL = 0x3159c;
UartLogRomCmdTable = 0x316a0;
_HalRuartOp = 0x31700;
_HalGdmaOp = 0x31760;
RTW_WPA_OUI_TYPE = 0x3540c;
WPA_CIPHER_SUITE_NONE = 0x35410;
WPA_CIPHER_SUITE_WEP40 = 0x35414;
WPA_CIPHER_SUITE_TKIP = 0x35418;
WPA_CIPHER_SUITE_CCMP = 0x3541c;
WPA_CIPHER_SUITE_WEP104 = 0x35420;
RSN_CIPHER_SUITE_NONE = 0x35424;
RSN_CIPHER_SUITE_WEP40 = 0x35428;
RSN_CIPHER_SUITE_TKIP = 0x3542c;
RSN_CIPHER_SUITE_CCMP = 0x35430;
RSN_CIPHER_SUITE_WEP104 = 0x35434;
RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X = 0x35444;
RSN_AUTH_KEY_MGMT_UNSPEC_802_1X = 0x35448;
RSN_VERSION_BSD = 0x3544c;
rom_wps_Te0 = 0x35988;
rom_wps_rcons = 0x35d88;
rom_wps_Td4s = 0x35d94;
rom_wps_Td0 = 0x35e94;
__rom_b_cut_end__ = 0x4467c;
__rom_c_cut_text_start__ = 0x4467c;
HalInitPlatformLogUartV02 = 0x4467d;
HalReInitPlatformLogUartV02 = 0x4471d;
HalInitPlatformTimerV02 = 0x44755;
HalShowBuildInfoV02 = 0x447cd;
SpicReleaseDeepPowerDownFlashRtl8195A = 0x44831;
HalSpiInitV02 = 0x4488d;
HalBootFlowV02 = 0x44a29;
HalInitialROMCodeGlobalVarV02 = 0x44ae5;
HalResetVsrV02 = 0x44b41;
HalI2CSendRtl8195aV02 = 0x44ce1;
HalI2CSetCLKRtl8195aV02 = 0x44d59;
RtkI2CSendV02 = 0x4508d;
RtkI2CReceiveV02 = 0x459a1;
HalI2COpInitV02 = 0x461ed;
I2CISRHandleV02 = 0x463e9;
RtkSalI2COpInitV02 = 0x46be1;
SpicLoadInitParaFromClockRtl8195AV02 = 0x46c25;
SpiFlashAppV02 = 0x46c85;
SpicInitRtl8195AV02 = 0x46dc5;
SpicEraseFlashRtl8195AV02 = 0x46ea1;
HalTimerIrq2To7HandleV02 = 0x46f5d;
HalTimerIrqRegisterRtl8195aV02 = 0x46fe1;
HalTimerInitRtl8195aV02 = 0x4706d;
HalTimerReadCountRtl8195aV02 = 0x471b5;
HalTimerReLoadRtl8195aV02 = 0x471d1;
HalTimerIrqUnRegisterRtl8195aV02 = 0x4722d;
HalTimerDeInitRtl8195aV02 = 0x472c1;
HalTimerOpInitV02 = 0x472f9;
GPIO_LockV02 = 0x47345;
GPIO_UnLockV02 = 0x47379;
GPIO_Int_Clear_8195aV02 = 0x473a5;
HAL_GPIO_IntCtrl_8195aV02 = 0x473b5;
FindElementIndexV02 = 0x47541;
HalRuartInitRtl8195aV02 = 0x4756d;
DramInit_rom = 0x47619;
ChangeRandSeed_rom = 0x47979;
Sdr_Rand2_rom = 0x47985;
MemTest_rom = 0x479dd;
SdrCalibration_rom = 0x47a45;
SdrControllerInit_rom = 0x47d99;
SDIO_EnterCritical = 0x47e39;
SDIO_ExitCritical = 0x47e85;
SDIO_IRQ_Handler_Rom = 0x47ec5;
SDIO_Interrupt_Init_Rom = 0x47f31;
SDIO_Device_Init_Rom = 0x47f81;
SDIO_Interrupt_DeInit_Rom = 0x48215;
SDIO_Device_DeInit_Rom = 0x48255;
SDIO_Enable_Interrupt_Rom = 0x48281;
SDIO_Disable_Interrupt_Rom = 0x482a1;
SDIO_Clear_ISR_Rom = 0x482c1;
SDIO_Alloc_Rx_Pkt_Rom = 0x482d9;
SDIO_Free_Rx_Pkt_Rom = 0x48331;
SDIO_Recycle_Rx_BD_Rom = 0x48355;
SDIO_RX_IRQ_Handler_BH_Rom = 0x484f1;
SDIO_RxTask_Rom = 0x4851d;
SDIO_Process_H2C_IOMsg_Rom = 0x4856d;
SDIO_Send_C2H_IOMsg_Rom = 0x4859d;
SDIO_Process_RPWM_Rom = 0x485b5;
SDIO_Reset_Cmd_Rom = 0x485e9;
SDIO_Rx_Data_Transaction_Rom = 0x48611;
SDIO_Send_C2H_PktMsg_Rom = 0x48829;
SDIO_Register_Tx_Callback_Rom = 0x488f5;
SDIO_ReadMem_Rom = 0x488fd;
SDIO_WriteMem_Rom = 0x489a9;
SDIO_SetMem_Rom = 0x48a69;
SDIO_TX_Pkt_Handle_Rom = 0x48b29;
SDIO_TX_FIFO_DataReady_Rom = 0x48c69;
SDIO_IRQ_Handler_BH_Rom = 0x48d95;
SDIO_TxTask_Rom = 0x48e9d;
SDIO_TaskUp_Rom = 0x48eed;
SDIO_Boot_Up = 0x48f55;
__rom_c_cut_text_end__ = 0x49070;
__rom_c_cut_rodata_start__ = 0x49070;
BAUDRATE_v02 = 0x49070;
OVSR_v02 = 0x490fc;
DIV_v02 = 0x49188;
OVSR_ADJ_v02 = 0x49214;
SdrDramInfo_rom = 0x492a0;
SdrDramTiming_rom = 0x492b4;
SdrDramModeReg_rom = 0x492e8;
SdrDramDev_rom = 0x49304;
__rom_c_cut_rodata_end__ = 0x49314;
NewVectorTable = 0x10000000;
UserIrqFunTable = 0x10000100;
UserIrqDataTable = 0x10000200;
__rom_bss_start__ = 0x10000300;
CfgSysDebugWarn = 0x10000300;
CfgSysDebugInfo = 0x10000304;
CfgSysDebugErr = 0x10000308;
ConfigDebugWarn = 0x1000030c;
ConfigDebugInfo = 0x10000310;
ConfigDebugErr = 0x10000314;
HalTimerOp = 0x10000318;
GPIOState = 0x10000334;
gTimerRecord = 0x1000034c;
SSI_DBG_CONFIG = 0x10000350;
_pHAL_Gpio_Adapter = 0x10000354;
Timer2To7VectorTable = 0x10000358;
pUartLogCtl = 0x10000384;
UartLogBuf = 0x10000388;
UartLogCtl = 0x10000408;
UartLogHistoryBuf = 0x10000430;
ArgvArray = 0x100006ac;
rom_wlan_ram_map = 0x100006d4;
FalseAlmCnt = 0x100006e0;
ROMInfo = 0x10000720;
DM_CfoTrack = 0x10000738;
rom_libgloss_ram_map = 0x10000760;
rtl_errno = 0x10000bc4;
_rtl_impure_ptr = 0x10001c60;
}

13
lib/cpu/rtl8710/rtl8710.h Normal file
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#ifndef _RTL8710_H_
#define _RTL8710_H_
#include "rtl8710_sys.h"
#include "rtl8710_int.h"
#include "rtl8710_peri_on.h"
#include "rtl8710_timer.h"
#include "rtl8710_gpio.h"
//#include "rtl8710_log_uart.h"
//#include "rtl8710_spi.h"
#endif

85
lib/cpu/rtl8710/rtl8710.ld Normal file
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ENTRY(start_init)
MEMORY{
tcm (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 64k
ram (rwx) : ORIGIN = 0x10000ba8, LENGTH = 0x70000 - 0x0ba8
/* flash (rx) : ORIGIN = 0x98000000, LENGTH = 1024k */
}
PROVIDE(STACK_TOP = 0x1FFF0000 + 64k - 4);
SECTIONS{
__rom_bss_start__ = 0x10000300;
__rom_bss_end__ = 0x10000bc8;
.fheader : {
flash_head = ABSOLUTE(.);
LONG(0x96969999)
LONG(0xFC66CC3F)
LONG(0x03CC33C0)
LONG(0x6231DCE5)
FirmvareSize = ABSOLUTE(.);
LONG(__seg0_end__ - __seg0_start__)
LONG(__seg0_start__)
SHORT(seg0_size_1k)
SHORT(0xFFFF)
LONG(0xFFFFFFFF)
/* *(.fheader.data) */
} > ram
.header : {
__seg0_start__ = ABSOLUTE(.);
boot_head = ABSOLUTE(.);
KEEP(*(.header.data*))
. = ALIGN(4);
__seg0_size__ = ABSOLUTE(.);
LONG(__seg0_end__ - __seg0_start__)
. = ALIGN(4);
KEEP(*(.header.code*))
*(.header*)
} > ram
.text : {
. = ALIGN(4);
*(.vector.data*) *(.vector.code*) *(.vector*)
__text_beg__ = ABSOLUTE(.);
*(.text) *(.text*) *(.rodata) *(.rodata*) *(.glue_7) *(.glue_7t) *(.eh_frame) *(.ARM.extab*)
. = ALIGN(4);
__text_end__ = ABSOLUTE(.);
} >ram
.data : {
. = ALIGN(4);
__data_beg__ = ABSOLUTE(.);
*(.ram_vectors) *(.data) *(.data*) *(.ram_func) . = ALIGN(4);
__data_end__ = ABSOLUTE(.);
. = ALIGN(4);
__seg0_end__ = ABSOLUTE(.);
} >ram
.bss : {
. = ALIGN(4);
__bss_beg__ = ABSOLUTE(.);
*(.bss) *(COMMON) . = ALIGN(4);
__bss_end__ = ABSOLUTE(.);
} >ram
.ARM.exidx : {
___exidx_start = ABSOLUTE(.);
*(.ARM.exidx*) ;
___exidx_end = ABSOLUTE(.);
} >ram
.ARM.extab : {
*(.ARM.extab*)
} >ram
. = ALIGN(4);
end = .;
PROVIDE (end = .);
}
INCLUDE "export-rom_v03.txt"

332
lib/cpu/rtl8710/rtl8710.ocd Normal file
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#
# OpenOCD script for RTL8710
# Copyright (C) 2016 Rebane, rebane@alkohol.ee
#
source [find target/swj-dp.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME rtl8710
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x800
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x2ba01477
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x10001000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# adapter_khz 500
adapter_nsrst_delay 100
if {![using_hla]} {
cortex_m reset_config sysresetreq
}
set rtl8710_flasher_firmware_ptr 0x10001000
set rtl8710_flasher_buffer 0x10008000
set rtl8710_flasher_buffer_size 262144
set rtl8710_flasher_sector_size 4096
array set rtl8710_flasher_code {
0 0xB671B57F 1 0x25FF4B58 2 0x6B196B1A 3 0x7040F042 4 0x69D96318 5 0xF4414E55
6 0x69D97480 7 0xF8D361DC 8 0xF8C32120 9 0xF8D35120 10 0xF8C31124 11 0x47B05124
12 0x47B04E4F 13 0x47984B4F 14 0x60104A4F 15 0x484F47B0 16 0x60012100 17 0x2C006804
18 0x4D4DD0FC 19 0xB93E682E 20 0x60264C49 21 0x47B04E46 22 0x47984B46 23 0xE7ED6020
24 0x2B01682B 25 0x4E42D109 26 0x4C4647B0 27 0x47A02006 28 0x47904A45 29 0x47A020C7
30 0x682AE00D 31 0xD10E2A02 32 0x47B04E3B 33 0x20064C3F 34 0x483F47A0 35 0x493F4780
36 0x68084D3F 37 0x47B047A8 38 0x47A02004 39 0x6828E7CE 40 0xD1132803 41 0x47A04C32
42 0x24004838 43 0x4E396805 44 0x68311960 45 0xD206428C 46 0x4B384A37 47 0x221018A1
48 0x34104798 49 0x4D2AE7F3 50 0xE7B847A8 51 0x29046829 52 0x2400D11B 53 0x6806482F
54 0xD2B042B4 55 0x47A84D24 56 0x20064E28 57 0x4B2847B0 58 0x49284798 59 0x680A4B2A
60 0x18A018E1 61 0xF44F4B2A 62 0x47987280 63 0x200447A8 64 0xF50447B0 65 0x47A87480
66 0x682CE7E4 67 0xD1232C05 68 0x47984B17 69 0x4D1F2400 70 0x4294682A 71 0x481BD28F
72 0x68012210 73 0x18604E1D 74 0x47B04669 75 0x1B19682B 76 0xBF282910 77 0x23002110
78 0xD011428B 79 0xF81D4A16 80 0x18A05003 81 0x42B55CC6 82 0x3301D101 83 0x4A15E7F4
84 0x60112101 85 0xE7726054 86 0x25014E12 87 0xE76E6035 88 0x47A84D03 89 0xE7D63410
90 0x40000200 91 0x100011BD 92 0x100013DD 93 0x10001289 94 0x1000800C 95 0x10008000
96 0x10008004 97 0x1000130D 98 0x100013ED 99 0x10008010 100 0x10001335 101 0x10008014
102 0x10008020 103 0x10001221 104 0x10001375 105 0x10008008 106 0x6A5A4B03 107 0xD0FB0512
108 0x0060F893 109 0xBF004770 110 0x40006000 111 0x6B194B17 112 0xF4416B1A 113 0x63187040
114 0x69186919 115 0x0110F041 116 0xF8D36119 117 0x220000C0 118 0x0106F020 119 0x00C0F8D3
120 0x10C0F8C3 121 0x00C0F8D3 122 0x0101F040 123 0x00C0F8D3 124 0x10C0F8C3 125 0x43BCF503
126 0x609A6899 127 0x20016AD9 128 0x691962DA 129 0x69596118 130 0x61592102 131 0x619A6999
132 0x61DA69D9 133 0x64DA6CD9 134 0xBF004770 135 0x40000200 136 0x460EB570 137 0xB34A4614
138 0xF3C04B15 139 0x681A4507 140 0x7240F44F 141 0x685A601A 142 0xF3C02103 143 0x2C102207
144 0x2410BF28 145 0x605CB2C0 146 0x1060F883 147 0x5060F883 148 0xF8832101 149 0xF8832060
150 0x689A0060 151 0x60992500 152 0x47984B08 153 0x35015570 154 0x42A2B2AA 155 0x4804D3F8
156 0xF0116A81 157 0xD1FA0301 158 0x60836881 159 0xBD704620 160 0x40006000 161 0x100011A9
162 0x4C10B5F8 163 0x68232003 164 0x7340F44F 165 0x68636023 166 0x60602101 167 0x68A3229F
168 0x60A14D0B 169 0x2060F884 170 0x460647A8 171 0x460747A8 172 0x040347A8 173 0x2707EA43
174 0x0006EA47 175 0x4B036AA1 176 0x0201F011 177 0x6899D1FA 178 0xBDF8609A 179 0x40006000
180 0x100011A9 181 0x4C0BB510 182 0x68232001 183 0x7340F44F 184 0x68636023 185 0x60602105
186 0x60A068A2 187 0xF8844A06 188 0x47901060 189 0x4B036AA1 190 0x0201F011 191 0x6899D1FA
192 0xBD10609A 193 0x40006000 194 0x100011A9 195 0x21014B08 196 0xF44F681A 197 0x601A7280
198 0x6099689A 199 0x0060F883 200 0x48036A9A 201 0x0101F012 202 0x6883D1FA 203 0x47706081
204 0x40006000 205 0x21014B0E 206 0xF44F681A 207 0x601A7280 208 0x2220689A 209 0xF8836099
210 0xF3C02060 211 0xF3C04107 212 0xB2C02207 213 0x1060F883 214 0x2060F883 215 0x0060F883
216 0x4A036A99 217 0x0001F011 218 0x6893D1FA 219 0x47706090 220 0x40006000 221 0xB36AB530
222 0x25014B17 223 0xF44F681C 224 0x601C7480 225 0x2402689C 226 0xF883609D 227 0xF3C04060
228 0xF3C04507 229 0xB2C02407 230 0x5060F883 231 0x7F80F5B2 232 0xF44FBF28 233 0xF8837280
234 0xF8834060 235 0x20000060 236 0x4C095C0D 237 0xF8843001 238 0xB2855060 239 0xD3F74295
240 0x07496A99 241 0x6AA0D5FC 242 0xF0104B03 243 0xD1FA0101 244 0x60996898 245 0xBD304610
246 0x40006000 247 0x4B02B508 248 0x07C04798 249 0xBD08D4FB 250 0x100012D5 251 0x4B04B508
252 0xF0004798 253 0xB2C10002 254 0xD0F82900 255 0xBF00BD08 256 0x100012D5
}
set rtl8710_flasher_command_read_id 0
set rtl8710_flasher_command_mass_erase 1
set rtl8710_flasher_command_sector_erase 2
set rtl8710_flasher_command_read 3
set rtl8710_flasher_command_write 4
set rtl8710_flasher_command_verify 5
set rtl8710_flasher_ready 0
set rtl8710_flasher_capacity 0
set rtl8710_flasher_auto_erase 0
set rtl8710_flasher_auto_verify 0
set rtl8710_flasher_auto_erase_sector 0xFFFFFFFF
proc rtl8710_flasher_init {} {
global rtl8710_flasher_firmware_ptr
global rtl8710_flasher_buffer
global rtl8710_flasher_capacity
global rtl8710_flasher_ready
global rtl8710_flasher_code
if {[expr {$rtl8710_flasher_ready == 0}]} {
echo "initializing RTL8710 flasher"
halt
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
array2mem rtl8710_flasher_code 32 $rtl8710_flasher_firmware_ptr [array size rtl8710_flasher_code]
reg faultmask 0x01
reg sp 0x20000000
reg pc $rtl8710_flasher_firmware_ptr
resume
rtl8710_flasher_wait
set id [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set rtl8710_flasher_capacity [expr {2 ** [expr {($id >> 16) & 0xFF}]}]
set rtl8710_flasher_ready 1
echo "RTL8710 flasher initialized"
}
return ""
}
proc rtl8710_flasher_mrw {reg} {
set value ""
mem2array value 32 $reg 1
return $value(0)
}
proc rtl8710_flasher_wait {} {
global rtl8710_flasher_buffer
while {[rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x00}]]} { }
}
proc rtl8710_flasher_load_block {local_filename offset len} {
global rtl8710_flasher_buffer
load_image $local_filename [expr {$rtl8710_flasher_buffer + 0x20 - $offset}] bin [expr {$rtl8710_flasher_buffer + 0x20}] $len
}
proc rtl8710_flasher_read_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_read
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_read
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
error "read error, offset $offset"
}
}
proc rtl8710_flasher_write_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_write
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_write
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
error "write error, offset $offset"
}
}
proc rtl8710_flasher_verify_block {offset len} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_verify
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_verify
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x14}] $len
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x08}]]
if {[expr {$status > 0}]} {
set status [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set status [expr {$status + $offset}]
error "verify error, offset $status"
}
}
proc rtl8710_flash_read_id {} {
global rtl8710_flasher_buffer
global rtl8710_flasher_capacity
global rtl8710_flasher_command_read_id
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_read_id
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
set id [rtl8710_flasher_mrw [expr {$rtl8710_flasher_buffer + 0x0C}]]
set manufacturer_id [format "0x%02X" [expr {$id & 0xFF}]]
set memory_type [format "0x%02X" [expr {($id >> 8) & 0xFF}]]
set memory_capacity [expr {2 ** [expr {($id >> 16) & 0xFF}]}]
echo "manufacturer ID: $manufacturer_id, memory type: $memory_type, memory capacity: $memory_capacity bytes"
}
proc rtl8710_flash_mass_erase {} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_mass_erase
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_mass_erase
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
}
proc rtl8710_flash_sector_erase {offset} {
global rtl8710_flasher_buffer
global rtl8710_flasher_command_sector_erase
rtl8710_flasher_init
mww [expr {$rtl8710_flasher_buffer + 0x04}] $rtl8710_flasher_command_sector_erase
mww [expr {$rtl8710_flasher_buffer + 0x08}] 0x00000000
mww [expr {$rtl8710_flasher_buffer + 0x10}] $offset
mww [expr {$rtl8710_flasher_buffer + 0x00}] 0x00000001
rtl8710_flasher_wait
}
proc rtl8710_flash_read {local_filename loc size} {
global rtl8710_flasher_buffer
global rtl8710_flasher_buffer_size
rtl8710_flasher_init
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "read offset $flash_offset"
rtl8710_flasher_read_block $flash_offset $len
dump_image /tmp/_rtl8710_flasher.bin [expr {$rtl8710_flasher_buffer + 0x20}] $len
exec dd conv=notrunc if=/tmp/_rtl8710_flasher.bin "of=$local_filename" bs=1 "seek=$offset"
echo "read $len bytes"
}
}
proc rtl8710_flash_write {local_filename loc} {
global rtl8710_flasher_buffer_size
global rtl8710_flasher_sector_size
global rtl8710_flasher_auto_erase
global rtl8710_flasher_auto_verify
global rtl8710_flasher_auto_erase_sector
rtl8710_flasher_init
set sector 0
set size [file size $local_filename]
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "write offset $flash_offset"
rtl8710_flasher_load_block $local_filename $offset $len
if {[expr {$rtl8710_flasher_auto_erase != 0}]} {
for {set i $flash_offset} {$i < [expr {$flash_offset + $len}]} {incr i} {
set sector [expr {$i / $rtl8710_flasher_sector_size}]
if {[expr {$rtl8710_flasher_auto_erase_sector != $sector}]} {
echo "erase sector $sector"
rtl8710_flash_sector_erase [expr {$sector * $rtl8710_flasher_sector_size}]
set rtl8710_flasher_auto_erase_sector $sector
}
}
}
rtl8710_flasher_write_block $flash_offset $len
echo "wrote $len bytes"
if {[expr {$rtl8710_flasher_auto_verify != 0}]} {
echo "verify offset $flash_offset"
rtl8710_flasher_verify_block $flash_offset $len
}
}
}
proc rtl8710_flash_verify {local_filename loc} {
global rtl8710_flasher_buffer_size
rtl8710_flasher_init
set size [file size $local_filename]
for {set offset 0} {$offset < $size} {set offset [expr {$offset + $rtl8710_flasher_buffer_size}]} {
set len [expr {$size - $offset}]
if {[expr {$len > $rtl8710_flasher_buffer_size}]} {
set len $rtl8710_flasher_buffer_size
}
set flash_offset [expr {$loc + $offset}]
echo "read offset $flash_offset"
rtl8710_flasher_load_block $local_filename $offset $len
echo "verify offset $flash_offset"
rtl8710_flasher_verify_block $flash_offset $len
}
}
proc rtl8710_flash_auto_erase {on} {
global rtl8710_flasher_auto_erase
if {[expr {$on != 0}]} {
set rtl8710_flasher_auto_erase 1
echo "auto erase on"
} else {
set rtl8710_flasher_auto_erase 0
echo "auto erase off"
}
}
proc rtl8710_flash_auto_verify {on} {
global rtl8710_flasher_auto_verify
if {[expr {$on != 0}]} {
set rtl8710_flasher_auto_verify 1
echo "auto verify on"
} else {
set rtl8710_flasher_auto_verify 0
echo "auto verify off"
}
}
proc rtl8710_reboot {} {
mww 0xE000ED0C 0x05FA0007
}

37
lib/cpu/rtl8710/rtl8710_gpio.h Normal file
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#ifndef _RTL8710_GPIO_H_
#define _RTL8710_GPIO_H_
#include <stdint.h>
typedef struct{
volatile uint32_t SWPORTA_DR;
volatile uint32_t SWPORTA_DDR;
volatile uint32_t SWPORTA_CTRL;
volatile uint32_t SWPORTB_DR;
volatile uint32_t SWPORTB_DDR;
volatile uint32_t SWPORTB_CTRL;
volatile uint32_t SWPORTC_DR;
volatile uint32_t SWPORTC_DDR;
volatile uint32_t SWPORTC_CTRL;
uint32_t RESERVED1[3];
volatile uint32_t INTEN;
volatile uint32_t INTMASK;
volatile uint32_t INTTYPE_LEVEL;
volatile uint32_t INT_POLARITY;
volatile uint32_t INTSTATUS;
volatile uint32_t RAW_INTSTATUS;
volatile uint32_t DEBOUNCE;
volatile uint32_t PORTA_EOI;
volatile uint32_t EXT_PORTA;
volatile uint32_t EXT_PORTB;
volatile uint32_t EXT_PORTC;
uint32_t RESERVED2[1];
volatile uint32_t LS_SYNC;
}__attribute__((packed)) GPIO_TypeDef;
#define GPIO ((GPIO_TypeDef *)0x40001000)
#define GPIO_PORTA_GC4 (((uint32_t)1) << 8)
#endif

53
lib/cpu/rtl8710/rtl8710_int.h Normal file
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#ifndef _RTL8710_INT_H_
#define _RTL8710_INT_H_
#define SYSTEM_ON_INT 0
#define WDG_INT 1
#define TIMER0_INT 2
#define TIMER1_INT 3
#define I2C3_INT 4
#define TIMER2_7_INT 5
#define SPI0_INT 6
#define GPIO_INT 7
#define UART0_INT 8
#define SPI_FLASH_INT 9
#define USB_OTG_INT 10
#define SDIO_HOST_INT 11
#define SDIO_DEVICE_INT 12
#define I2S0_PCM0_INT 13
#define I2S1_PCM1_INT 14
#define WL_DMA_INT 15
#define WL_PROTOCOL_INT 16
#define CRYPTO_INT 17
#define GMAC_INT 18
#define PERIPHERAL_INT 19
#define GDMA0_CHANNEL0_INT 20
#define GDMA0_CHANNEL1_INT 21
#define GDMA0_CHANNEL2_INT 22
#define GDMA0_CHANNEL3_INT 23
#define GDMA0_CHANNEL4_INT 24
#define GDMA0_CHANNEL5_INT 25
#define GDMA1_CHANNEL0_INT 26
#define GDMA1_CHANNEL1_INT 27
#define GDMA1_CHANNEL2_INT 28
#define GDMA1_CHANNEL3_INT 29
#define GDMA1_CHANNEL4_INT 30
#define GDMA1_CHANNEL5_INT 31
#define I2C0_INT 64
#define I2C1_INT 65
#define I2C2_INT 66
#define SPI1_INT 72
#define SPI2_INT 73
#define UART1_INT 80
#define UART2_INT 81
#define LOG_UART_INT 88
#define ADC_INT 89
#define DAC0_INT 91
#define DAC1_INT 92
#define LP_EXTENSION_INT 93
#define PTA_TRX_INT 95
#define RXI300_INT 96
#define NFC_INT 97
#endif

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#ifndef _RTL8710_LOG_UART_H_
#define _RTL8710_LOG_UART_H_
#include <stdint.h>
typedef struct{
union{
volatile uint32_t RBR;
volatile uint32_t THR;
volatile uint32_t DLL;
volatile uint32_t RBR_THR_DLL;
};
union{
volatile uint32_t IER;
volatile uint32_t DLH;
volatile uint32_t IER_DLH;
};
union{
volatile uint32_t IIR;
volatile uint32_t FCR;
volatile uint32_t IIR_FCR;
};
volatile uint32_t LCR;
volatile uint32_t MCR;
volatile uint32_t LSR;
volatile uint32_t MSR;
uint32_t RESERVED1[24];
volatile uint32_t USR;
}__attribute__((packed)) LOG_UART_TypeDef;
#define LOG_UART ((LOG_UART_TypeDef *)0x40003000)
// LOG_UART_IER
#define LOG_UART_IER_ERBFI (((uint32_t)0x01) << 0)
#define LOG_UART_IER_ETBEI (((uint32_t)0x01) << 1)
#define LOG_UART_IER_ELSI (((uint32_t)0x01) << 2)
#define LOG_UART_IER_EDSSI (((uint32_t)0x01) << 3)
// LOG_UART_FCR
#define LOG_UART_FCR_FIFOE (((uint32_t)0x01) << 0)
#define LOG_UART_FCR_RFIFOR (((uint32_t)0x01) << 1)
#define LOG_UART_FCR_XFIFOR (((uint32_t)0x01) << 2)
#define LOG_UART_FCR_DMAM (((uint32_t)0x01) << 3)
#define LOG_UART_FCR_TET (((uint32_t)0x03) << 4)
#define LOG_UART_FCR_RT (((uint32_t)0x03) << 6)
// LOG_UART_LCR
#define LOG_UART_LCR_DLS (((uint32_t)0x03) << 0)
#define LOG_UART_LCR_STOP (((uint32_t)0x01) << 2)
#define LOG_UART_LCR_PEN (((uint32_t)0x01) << 3)
#define LOG_UART_LCR_EPS (((uint32_t)0x01) << 4)
#define LOG_UART_LCR_STICK_PAR (((uint32_t)0x01) << 5)
#define LOG_UART_LCR_BC (((uint32_t)0x01) << 6)
#define LOG_UART_LCR_DLAB (((uint32_t)0x01) << 7)
// LOG_UART_MCR
#define LOG_UART_MCR_DTR (((uint32_t)0x01) << 0)
#define LOG_UART_MCR_RTS (((uint32_t)0x01) << 1)
#define LOG_UART_MCR_OUT1 (((uint32_t)0x01) << 2)
#define LOG_UART_MCR_OUT2 (((uint32_t)0x01) << 3)
#define LOG_UART_MCR_LOOPBACK (((uint32_t)0x01) << 4)
#define LOG_UART_MCR_AFCE (((uint32_t)0x01) << 5)
// LOG_UART_LSR
#define LOG_UART_LSR_DR (((uint32_t)0x01) << 0)
#define LOG_UART_LSR_OE (((uint32_t)0x01) << 1)
#define LOG_UART_LSR_PE (((uint32_t)0x01) << 2)
#define LOG_UART_LSR_FE (((uint32_t)0x01) << 3)
#define LOG_UART_LSR_BI (((uint32_t)0x01) << 4)
#define LOG_UART_LSR_THRE (((uint32_t)0x01) << 5)
#define LOG_UART_LSR_TEMT (((uint32_t)0x01) << 6)
#define LOG_UART_LSR_RFE (((uint32_t)0x01) << 7)
#define LOG_UART_LSR_ADDR_RCVD (((uint32_t)0x01) << 8)
#endif

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#ifndef _RTL8710_PERI_ON_H_
#define _RTL8710_PERI_ON_H_
#include <stdint.h>
typedef struct{
volatile uint32_t PEON_PWR_CTRL; // 0x0200
volatile uint32_t PON_ISO_CTRL; // 0x0204
uint32_t RESERVED1[2];
volatile uint32_t SOC_FUNC_EN; // 0x0210
volatile uint32_t SOC_HCI_COM_FUNC_EN; // 0x0214
volatile uint32_t SOC_PERI_FUNC0_EN; // 0x0218
volatile uint32_t SOC_PERI_FUNC1_EN; // 0x021C
volatile uint32_t SOC_PERI_DB_FUNC0_EN; // 0x0220
uint32_t RESERVED2[3];
volatile uint32_t PESOC_CLK_CTRL; // 0x0230
volatile uint32_t PESOC_PERI_CLK_CTRL0; // 0x0234
volatile uint32_t PESOC_PERI_CLK_CTRL1; // 0x0238
volatile uint32_t PESOC_CLK_CTRL3; // 0x023C
volatile uint32_t PESOC_HCI_CLK_CTRL0; // 0x0240
volatile uint32_t PESOC_COM_CLK_CTRL1; // 0x0244
volatile uint32_t PESOC_HW_ENG_CLK_CTRL; // 0x0248
uint32_t RESERVED3[1];
volatile uint32_t PESOC_CLK_SEL; // 0x0250
uint32_t RESERVED4[6];
volatile uint32_t SYS_ANACK_CAL_CTRL; // 0x026C
volatile uint32_t OSC32K_CTRL; // 0x0270
volatile uint32_t OSC32K_REG_CTRL0; // 0x0274
volatile uint32_t OSC32K_REG_CTRL1; // 0x0278
volatile uint32_t THERMAL_METER_CTRL; // 0x027C
volatile uint32_t UART_MUX_CTRL; // 0x0280
volatile uint32_t SPI_MUX_CTRL; // 0x0284
volatile uint32_t I2C_MUX_CTRL; // 0x0288
volatile uint32_t I2S_MUX_CTRL; // 0x028C
uint32_t RESERVED5[4];
volatile uint32_t HCI_PINMUX_CTRL; // 0x02A0
volatile uint32_t WL_PINMUX_CTRL; // 0x02A4
volatile uint32_t BT_PINMUX_CTRL; // 0x02A8
volatile uint32_t PWM_PINMUX_CTRL; // 0x02AC
uint32_t RESERVED6[4];
volatile uint32_t CPU_PERIPHERAL_CTRL; // 0x02C0
uint32_t RESERVED7[7];
volatile uint32_t HCI_CTRL_STATUS_0; // 0x02E0
volatile uint32_t HCI_CTRL_STATUS_1; // 0x02E4
uint32_t RESERVED8[6];
volatile uint32_t PESOC_MEM_CTRL; // 0x0300
volatile uint32_t PESOC_SOC_CTRL; // 0x0304
volatile uint32_t PESOC_PERI_CTRL; // 0x0308
uint32_t RESERVED9[5];
volatile uint32_t GPIO_SHTDN_CTRL; // 0x0320
volatile uint32_t GPIO_DRIVING_CTRL; // 0x0324
uint32_t RESERVED10[2];
volatile uint32_t GPIO_PULL_CTRL0; // 0x0330
volatile uint32_t GPIO_PULL_CTRL1; // 0x0334
volatile uint32_t GPIO_PULL_CTRL2; // 0x0338
volatile uint32_t GPIO_PULL_CTRL3; // 0x033C
volatile uint32_t GPIO_PULL_CTRL4; // 0x0340
volatile uint32_t GPIO_PULL_CTRL5; // 0x0344
volatile uint32_t GPIO_PULL_CTRL6; // 0x0348
uint32_t RESERVED11[5];
volatile uint32_t PERI_PWM0_CTRL; // 0x0360
volatile uint32_t PERI_PWM1_CTRL; // 0x0364
volatile uint32_t PERI_PWM2_CTRL; // 0x0368
volatile uint32_t PERI_PWM3_CTRL; // 0x036C
volatile uint32_t PERI_TIM_EVT_CTRL; // 0x0370
volatile uint32_t PERI_EGTIM_CTRL; // 0x0374
uint32_t RESERVED12[30];
volatile uint32_t PEON_CFG; // 0x03F0
volatile uint32_t PEON_STATUS; // 0x03F4
}__attribute__((packed)) PERI_ON_TypeDef;
#define PERI_ON ((PERI_ON_TypeDef *)0x40000200)
// PERI_ON_SOC_FUNC_EN
#define PERI_ON_SOC_FUNC_EN_FUN (((uint32_t)0x01) << 0)
#define PERI_ON_SOC_FUNC_EN_OCP (((uint32_t)0x01) << 1)
#define PERI_ON_SOC_FUNC_EN_LXBUS (((uint32_t)0x01) << 2)
#define PERI_ON_SOC_FUNC_EN_FLASH (((uint32_t)0x01) << 4)
#define PERI_ON_SOC_FUNC_EN_MEM_CTRL (((uint32_t)0x01) << 6)
#define PERI_ON_SOC_FUNC_EN_CPU (((uint32_t)0x01) << 8)
#define PERI_ON_SOC_FUNC_EN_LOG_UART (((uint32_t)0x01) << 12)
#define PERI_ON_SOC_FUNC_EN_GDMA0 (((uint32_t)0x01) << 13)
#define PERI_ON_SOC_FUNC_EN_GDMA1 (((uint32_t)0x01) << 14)
#define PERI_ON_SOC_FUNC_EN_GTIMER (((uint32_t)0x01) << 16)
#define PERI_ON_SOC_FUNC_EN_SECURITY_ENGINE (((uint32_t)0x01) << 20)
// PERI_ON_SOC_PERI_FUNC1_EN
#define PERI_ON_SOC_PERI_FUNC1_EN_ADC0 (((uint32_t)0x01) << 0)
#define PERI_ON_SOC_PERI_FUNC1_EN_DAC0 (((uint32_t)0x01) << 4)
#define PERI_ON_SOC_PERI_FUNC1_EN_DAC1 (((uint32_t)0x01) << 5)
#define PERI_ON_SOC_PERI_FUNC1_EN_GPIO (((uint32_t)0x01) << 8)
// PERI_ON_PESOC_CLK_CTRL
#define PERI_ON_CLK_CTRL_CKE_OCP (((uint32_t)0x01) << 0)
#define PERI_ON_CLK_CTRL_CKE_PLFM (((uint32_t)0x01) << 2)
#define PERI_ON_CLK_CTRL_ACTCK_TRACE_EN (((uint32_t)0x01) << 4)
#define PERI_ON_CLK_CTRL_SLPCK_TRACE_EN (((uint32_t)0x01) << 5)
#define PERI_ON_CLK_CTRL_ACTCK_VENDOR_REG_EN (((uint32_t)0x01) << 6)
#define PERI_ON_CLK_CTRL_SLPCK_VENDOR_REG_EN (((uint32_t)0x01) << 7)
#define PERI_ON_CLK_CTRL_ACTCK_FLASH_EN (((uint32_t)0x01) << 8)
#define PERI_ON_CLK_CTRL_SLPCK_FLASH_EN (((uint32_t)0x01) << 9)
#define PERI_ON_CLK_CTRL_ACTCK_SDR_EN (((uint32_t)0x01) << 10)
#define PERI_ON_CLK_CTRL_SLPCK_SDR_EN (((uint32_t)0x01) << 11)
#define PERI_ON_CLK_CTRL_ACTCK_LOG_UART_EN (((uint32_t)0x01) << 12)
#define PERI_ON_CLK_CTRL_SLPCK_LOG_UART_EN (((uint32_t)0x01) << 13)
#define PERI_ON_CLK_CTRL_ACTCK_TIMER_EN (((uint32_t)0x01) << 14)
#define PERI_ON_CLK_CTRL_SLPCK_TIMER_EN (((uint32_t)0x01) << 15)
#define PERI_ON_CLK_CTRL_ACTCK_GDMA0_EN (((uint32_t)0x01) << 16)
#define PERI_ON_CLK_CTRL_SLPCK_GDMA0_EN (((uint32_t)0x01) << 17)
#define PERI_ON_CLK_CTRL_ACTCK_GDMA1_EN (((uint32_t)0x01) << 18)
#define PERI_ON_CLK_CTRL_SLPCK_GDMA1_EN (((uint32_t)0x01) << 19)
#define PERI_ON_CLK_CTRL_ACTCK_GPIO_EN (((uint32_t)0x01) << 24)
#define PERI_ON_CLK_CTRL_SLPCK_GPIO_EN (((uint32_t)0x01) << 25)
#define PERI_ON_CLK_CTRL_ACTCK_BTCMD_EN (((uint32_t)0x01) << 28)
#define PERI_ON_CLK_CTRL_SLPCK_BTCMD_EN (((uint32_t)0x01) << 29)
// PERI_ON_CPU_PERIPHERAL_CTRL
#define PERI_ON_CPU_PERIPHERAL_CTRL_SPI_FLASH_PIN_EN (((uint32_t)0x01) << 0)
#define PERI_ON_CPU_PERIPHERAL_CTRL_SPI_FLASH_PIN_SEL (((uint32_t)0x03) << 1)
#define PERI_ON_CPU_PERIPHERAL_CTRL_SDR_PIN_EN (((uint32_t)0x01) << 4)
#define PERI_ON_CPU_PERIPHERAL_CTRL_SWD_PIN_EN (((uint32_t)0x01) << 16)
#define PERI_ON_CPU_PERIPHERAL_CTRL_TRACE_PIN_EN (((uint32_t)0x01) << 17)
#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_PIN_EN (((uint32_t)0x01) << 20)
#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_IR_EN (((uint32_t)0x01) << 21)
#define PERI_ON_CPU_PERIPHERAL_CTRL_LOG_UART_PIN_SEL (((uint32_t)0x03) << 22)
#endif

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#ifndef _RTL8710_SPI_H_
#define _RTL8710_SPI_H_
#include <stdint.h>
typedef struct{
volatile uint32_t CTRLR0;
volatile uint32_t CTRLR1;
volatile uint32_t SSIENR;
volatile uint32_t MWCR;
volatile uint32_t SER;
volatile uint32_t BAUDR;
volatile uint32_t TXFTLR;
volatile uint32_t RXFTLR;
volatile uint32_t TXFLR;
volatile uint32_t RXFLR;
volatile uint32_t SR;
volatile uint32_t IMR;
volatile uint32_t ISR;
volatile uint32_t RISR;
volatile uint32_t TXOICR;
volatile uint32_t RXOICR;
volatile uint32_t RXUICR;
volatile uint32_t MSTICR;
volatile uint32_t ICR;
volatile uint32_t DMACR;
volatile uint32_t DMATDLR;
volatile uint32_t DMARDLR;
volatile uint32_t IDR;
volatile uint32_t SSI_COMP_VERSION;
union{
struct{
union{
volatile uint8_t DR;
volatile uint8_t DR8;
};
uint8_t RESERVED1[3];
}__attribute__((packed));
struct{
volatile uint16_t DR16;
uint16_t RESERVED2[1];
}__attribute__((packed));
volatile uint32_t DR32;
};
uint32_t RESERVED3[31];
volatile uint32_t READ_FAST_SINGLE;
volatile uint32_t READ_DUAL_DATA;
volatile uint32_t READ_DUAL_ADDR_DATA;
volatile uint32_t READ_QUAD_DATA;
union{
volatile uint32_t READ_QUAD_ADDR_DATA;
volatile uint32_t RX_SAMPLE_DLY;
};
volatile uint32_t WRITE_SIGNLE;
volatile uint32_t WRITE_DUAL_DATA;
volatile uint32_t WRITE_DUAL_ADDR_DATA;
volatile uint32_t WRITE_QUAD_DATA;
volatile uint32_t WRITE_QUAD_ADDR_DATA;
volatile uint32_t WRITE_ENABLE;
volatile uint32_t READ_STATUS;
volatile uint32_t CTRLR2;
volatile uint32_t FBAUDR;
volatile uint32_t ADDR_LENGTH;
volatile uint32_t AUTO_LENGTH;
volatile uint32_t VALID_CMD;
volatile uint32_t FLASE_SIZE;
volatile uint32_t FLUSH_FIFO;
}__attribute__((packed)) SPI_TypeDef;
#define SPI_FLASH ((SPI_TypeDef *)0x40006000)
// SPI_CTRLR0
#define SPI_CTRLR0_FRF (((uint32_t)0x03) << 4)
#define SPI_CTRLR0_SCPH (((uint32_t)0x01) << 6)
#define SPI_CTRLR0_SCPOL (((uint32_t)0x01) << 7)
#define SPI_CTRLR0_TMOD (((uint32_t)0x03) << 8)
#define SPI_CTRLR0_SLV_OE (((uint32_t)0x01) << 10)
#define SPI_CTRLR0_SRL (((uint32_t)0x01) << 11)
#define SPI_CTRLR0_CFS (((uint32_t)0x0F) << 12)
#define SPI_CTRLR0_ADDR_CH (((uint32_t)0x03) << 16)
#define SPI_CTRLR0_DATA_CH (((uint32_t)0x03) << 18)
#define SPI_CTRLR0_CMD_CH (((uint32_t)0x03) << 20)
#define SPI_CTRLR0_FAST_RD (((uint32_t)0x01) << 22)
#define SPI_CTRLR0_SHIFT_CK_MTIMES (((uint32_t)0x1F) << 23)
// SPI_SER
#define SPI_SER_SS0 (((uint32_t)0x01) << 0)
#define SPI_SER_SS1 (((uint32_t)0x01) << 1)
#define SPI_SER_SS2 (((uint32_t)0x01) << 2)
// SPI_SR
#define SPI_SR_SSI (((uint32_t)0x01) << 0)
#define SPI_SR_TFNF (((uint32_t)0x01) << 1)
#define SPI_SR_TFE (((uint32_t)0x01) << 2)
#define SPI_SR_RFNE (((uint32_t)0x01) << 3)
#define SPI_SR_RFF (((uint32_t)0x01) << 4)
#define SPI_SR_TXE (((uint32_t)0x01) << 5)
#endif

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#ifndef _RTL8710_SYS_H_
#define _RTL8710_SYS_H_
#include <stdint.h>
// ~/programming/rtl8710/doc/registers/8195a/fwlib/rtl8195a/rtl8195a_sys_on.h
typedef struct{
volatile uint16_t PWR_CTRL; // 0x0000
volatile uint16_t ISO_CTRL; // 0x0002
uint32_t RESERVED1[1];
volatile uint32_t FUNC_EN; // 0x0008
uint32_t RESERVED2[1];
volatile uint32_t CLK_CTRL0; // 0x0010
volatile uint32_t CLK_CTRL1; // 0x0014
uint32_t RESERVED3[2];
volatile uint32_t EFUSE_SYSCFG0; // 0x0020
volatile uint32_t EFUSE_SYSCFG1; // 0x0024
volatile uint32_t EFUSE_SYSCFG2; // 0x0028
volatile uint32_t EFUSE_SYSCFG3; // 0x002C
volatile uint32_t EFUSE_SYSCFG4; // 0x0030
volatile uint32_t EFUSE_SYSCFG5; // 0x0034
volatile uint32_t EFUSE_SYSCFG6; // 0x0038
volatile uint32_t EFUSE_SYSCFG7; // 0x003C
volatile uint32_t REGU_CTRL0; // 0x0040
uint32_t RESERVED4[1];
volatile uint32_t SWR_CTRL0; // 0x0048
volatile uint32_t SWR_CTRL1; // 0x004C
uint32_t RESERVED5[4];
volatile uint32_t XTAL_CTRL0; // 0x0060
volatile uint32_t XTAL_CTRL1; // 0x0064
uint32_t RESERVED6[2];
volatile uint32_t SYSPLL_CTRL0; // 0x0070
volatile uint32_t SYSPLL_CTRL1; // 0x0074
volatile uint32_t SYSPLL_CTRL2; // 0x0078
uint32_t RESERVED7[5];
volatile uint32_t ANA_TIM_CTRL; // 0x0090
volatile uint32_t DSLP_TIM_CTRL; // 0x0094
volatile uint32_t DSLP_TIM_CAL_CTRL; // 0x0098
uint32_t RESERVED8[1];
volatile uint32_t DEBUG_CTRL; // 0x00A0
volatile uint32_t PINMUX_CTRL; // 0x00A4
volatile uint32_t GPIO_DSTBY_WAKE_CTRL0; // 0x00A8
volatile uint32_t GPIO_DSTBY_WAKE_CTRL1; // 0x00AC
uint32_t RESERVED9[3];
volatile uint32_t DEBUG_REG; // 0x00BC
uint32_t RESERVED10[8];
volatile uint32_t EEPROM_CTRL0; // 0x00E0
volatile uint32_t EEPROM_CTRL1; // 0x00E4
volatile uint32_t EFUSE_CTRL; // 0x00E8
volatile uint32_t EFUSE_TEST; // 0x00EC
volatile uint32_t DSTBY_INFO0; // 0x00F0
volatile uint32_t DSTBY_INFO1; // 0x00F4
volatile uint32_t DSTBY_INFO2; // 0x00F8
volatile uint32_t DSTBY_INFO3; // 0x00FC
volatile uint32_t SLP_WAKE_EVENT_MSK0; // 0x0100
volatile uint32_t SLP_WAKE_EVENT_MSK1; // 0x0104
volatile uint32_t SLP_WAKE_EVENT_STATUS0; // 0x0108
volatile uint32_t SLP_WAKE_EVENT_STATUS1; // 0x010C
volatile uint32_t SNF_WAKE_EVENT_MSK0; // 0x0110
volatile uint32_t SNF_WAKE_EVENT_STATUS; // 0x0114
volatile uint32_t PWRMGT_CTRL; // 0x0118
uint32_t RESERVED11[1];
volatile uint32_t PWRMGT_OPTION; // 0x0120
volatile uint32_t PWRMGT_OPTION_EXT; // 0x0124
uint32_t RESERVED12[2];
volatile uint32_t DSLP_WEVENT; // 0x0130
volatile uint32_t PERI_MONITOR; // 0x0134
uint32_t RESERVED13[46];
volatile uint32_t SYSTEM_CFG0; // 0x01F0
volatile uint32_t SYSTEM_CFG1; // 0x01F4
volatile uint32_t SYSTEM_CFG2; // 0x01F8
}__attribute__((packed)) SYS_TypeDef;
#define SYS ((SYS_TypeDef *)0x40000000)
// SYS_PWR_CTRL
#define SYS_PWR_CTRL_PEON_EN (((uint16_t)0x01) << 0)
#define SYS_PWR_CTRL_RET_MEM_EN (((uint16_t)0x01) << 1)
#define SYS_PWR_CTRL_SOC_EN (((uint16_t)0x01) << 2)
// SYS_ISO_CTRL
#define SYS_ISO_CTRL_PEON (((uint16_t)0x01) << 0)
#define SYS_ISO_CTRL_RET_MEM (((uint16_t)0x01) << 1)
#define SYS_ISO_CTRL_SOC (((uint16_t)0x01) << 2)
#define SYS_ISO_CTRL_SYSPLL (((uint16_t)0x01) << 7)
// SYS_FUNC_EN
#define SYS_FUNC_EN_FEN_EELDR (((uint32_t)0x01) << 0)
#define SYS_FUNC_EN_SOC_SYSPEON_EN (((uint32_t)0x01) << 4)
#define SYS_FUNC_EN_FEN_SIC (((uint32_t)0x01) << 24)
#define SYS_FUNC_EN_FEN_SIC_MST (((uint32_t)0x01) << 25)
#define SYS_FUNC_EN_PWRON_TRAP_SHTDN_N (((uint32_t)0x01) << 30)
#define SYS_FUNC_EN_AMACRO_EN (((uint32_t)0x01) << 31)
// SYS_CLK_CTRL0
#define SYS_CLK_CTRL0_CK_SYSREG_EN (((uint32_t)0x01) << 0)
#define SYS_CLK_CTRL0_CK_EELDR_EN (((uint32_t)0x01) << 1)
#define SYS_CLK_CTRL0_SOC_OCP_IOBUS_CK_EN (((uint32_t)0x01) << 2)
// SYS_CLK_CTRL1
#define SYS_CLK_CTRL1_PESOC_EELDR_CK_SEL (((uint32_t)0x01) << 0)
#define SYS_CLK_CTRL1_PESOC_OCP_CPU_CK_SEL (((uint32_t)0x07) << 4)
#endif

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#ifndef _RTL8710_TIMER_H_
#define _RTL8710_TIMER_H_
#include <stdint.h>
typedef struct{
volatile uint32_t TIM0_LOAD_COUNT;
volatile uint32_t TIM0_CURRENT_VALUE;
volatile uint32_t TIM0_CONTROL;
volatile uint32_t TIM0_EOI;
volatile uint32_t TIM0_IS;
volatile uint32_t TIM1_LOAD_COUNT;
volatile uint32_t TIM1_CURRENT_VALUE;
volatile uint32_t TIM1_CONTROL;
volatile uint32_t TIM1_EOI;
volatile uint32_t TIM1_IS;
uint32_t RESERVED1[30];
volatile uint32_t TIMS_IS;
volatile uint32_t TIMS_EOI;
volatile uint32_t TIMS_RAW_IS;
volatile uint32_t TIMS_COMP_VERSION;
volatile uint32_t TIM0_LOAD_COUNT2;
volatile uint32_t TIM1_LOAD_COUNT2;
}__attribute__((packed)) TIMER_TypeDef;
#define TIMER ((TIMER_TypeDef *)0x40002000)
// TIMER_CONTROL
#define TIMER_CONTROL_ENABLE (((uint32_t)0x01) << 0)
#define TIMER_CONTROL_MODE (((uint32_t)0x01) << 1)
#define TIMER_CONTROL_IM (((uint32_t)0x01) << 2)
#define TIMER_CONTROL_PWM (((uint32_t)0x01) << 3)
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_ADC_H_
#define _HAL_ADC_H_
#include "rtl8195a.h"
#include "rtl8195a_adc.h"
#include "hal_gdma.h"
//================ ADC Configuration =========================
#define ADC_INTR_OP_TYPE 1
#define ADC_DMA_OP_TYPE 1
// ADC SAL management macros
#define SAL_ADC_USER_CB_NUM (sizeof(SAL_ADC_USER_CB) / sizeof(PSAL_ADC_USERCB_ADPT))
// ADC used module.
// Please set the ADC module flag to 1 to enable the related
#define ADC0_USED 1
#define ADC1_USED 1
#define ADC2_USED 1
#define ADC3_USED 1
//================ Debug MSG Definition =======================
#define ADC_PREFIX "RTL8195A[adc]: "
#define ADC_PREFIX_LVL " [ADC_DBG]: "
typedef enum _ADC_DBG_LVL_ {
HAL_ADC_LVL = 0x01,
SAL_ADC_LVL = 0x02,
VERI_ADC_LVL = 0x04,
}ADC_DBG_LVL,*PADC_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_ADC_HAL
#define DBG_8195A_ADC(...) do{ \
_DbgDump("\r"ADC_PREFIX __VA_ARGS__);\
}while(0)
#define ADCDBGLVL 0xFF
#define DBG_8195A_ADC_LVL(LVL,...) do{\
if (LVL&ADCDBGLVL){\
_DbgDump("\r"ADC_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_ADC_LOG_PERD 100
#define DBG_8195A_ADC(...)
#define DBG_8195A_ADC_LVL(...)
#endif
#endif
//================ ADC HAL Related Enumeration ==================
// ADC Module Selection
typedef enum _ADC_MODULE_SEL_ {
ADC0_SEL = 0x0,
ADC1_SEL = 0x1,
ADC2_SEL = 0x2,
ADC3_SEL = 0x3,
}ADC_MODULE_SEL,*PADC_MODULE_SEL;
// ADC module status
typedef enum _ADC_MODULE_STATUS_ {
ADC_DISABLE = 0x0,
ADC_ENABLE = 0x1,
}ADC_MODULE_STATUS, *PADC_MODULE_STATUS;
// ADC Data Endian
typedef enum _ADC_DATA_ENDIAN_ {
ADC_DATA_ENDIAN_LITTLE = 0x0,
ADC_DATA_ENDIAN_BIG = 0x1,
}ADC_DATA_ENDIAN,*PADC_DATA_ENDIAN;
// ADC Debug Select
typedef enum _ADC_DEBUG_SEL_ {
ADC_DBG_SEL_DISABLE = 0x0,
ADC_DBG_SEL_ENABLE = 0x1,
}ADC_DEBUG_SEL,*PADC_DEBUG_SEL;
typedef enum _ADC_COMPARE_SET_ {
ADC_COMP_SMALLER_THAN = 0x0,
ADC_COMP_GREATER_THAN = 0x1,
}ADC_COMPARE_SET, *PADC_COMPARE_SET;
// ADC feature status
typedef enum _ADC_FEATURE_STATUS_{
ADC_FEATURE_DISABLED = 0,
ADC_FEATURE_ENABLED = 1,
}ADC_FEATURE_STATUS,*PADC_FEATURE_STATUS;
// ADC operation type
typedef enum _ADC_OP_TYPE_ {
ADC_RDREG_TYPE = 0x0,
ADC_DMA_TYPE = 0x1,
ADC_INTR_TYPE = 0x2,
}ADC_OP_TYPE, *PADC_OP_TYPE;
// ADC device status
typedef enum _ADC_DEVICE_STATUS_ {
ADC_STS_UNINITIAL = 0x00,
ADC_STS_INITIALIZED = 0x01,
ADC_STS_IDLE = 0x02,
ADC_STS_TX_READY = 0x03,
ADC_STS_TX_ING = 0x04,
ADC_STS_RX_READY = 0x05,
ADC_STS_RX_ING = 0x06,
ADC_STS_ERROR = 0x07,
ADC_STS_FULL = 0x08,
}ADC_DEVICE_STATUS, *PADC_DEVICE_STATUS;
// ADC error type
typedef enum _ADC_ERR_TYPE_ {
ADC_ERR_FIFO_RD_ERROR = 0x40, //ADC FIFO read error
}ADC_ERR_TYPE, *PADC_ERR_TYPE;
// ADC initial status
typedef enum _ADC_INITAIL_STATUS_ {
ADC0_INITED = 0x1,
ADC1_INITED = 0x2,
ADC2_INITED = 0x4,
ADC3_INITED = 0x8,
}ADC_INITAIL_STATUS, *PADC_INITAIL_STATUS;
//================ ADC HAL Data Structure ======================
// ADC HAL initial data structure
typedef struct _HAL_ADC_INIT_DAT_ {
u8 ADCIdx; //ADC index used
u8 ADCEn; //ADC module enable
u8 ADCEndian; //ADC endian selection,
//but actually it's for 32-bit ADC data swap control
//1'b0: no swap,
//1'b1: swap the upper 16-bit and the lower 16-bit
u8 ADCBurstSz; //ADC DMA operation threshold
u8 ADCCompOnly; //ADC compare mode only enable (without FIFO enable)
u8 ADCOneShotEn; //ADC one-shot mode enable
u8 ADCOverWREn; //ADC overwrite mode enable
u8 ADCOneShotTD; //ADC one shot mode threshold
u16 ADCCompCtrl; //ADC compare mode control,
//1'b0:less than the compare threshold
//1'b1:greater than the compare threshod
u16 ADCCompTD; //ADC compare mode threshold
u8 ADCDataRate; //ADC down sample data rate,
u8 ADCAudioEn; //ADC audio mode enable
u8 ADCEnManul; //ADC enable manually
u8 ADCDbgSel;
u32 RSVD0;
u32 *ADCData; //ADC data pointer
u32 ADCPWCtrl; //ADC0 power control
u32 ADCIntrMSK; //ADC Interrupt Mask
u32 ADCAnaParAd3; //ADC analog parameter 3
u32 ADCInInput; //ADC Input is internal?
}HAL_ADC_INIT_DAT,*PHAL_ADC_INIT_DAT;
// ADC HAL Operations
typedef struct _HAL_ADC_OP_ {
RTK_STATUS (*HalADCInit) (VOID *Data); //HAL ADC initialization
RTK_STATUS (*HalADCDeInit) (VOID *Data); //HAL ADC de-initialization
RTK_STATUS (*HalADCEnable) (VOID *Data); //HAL ADC de-initialization
u32 (*HalADCReceive) (VOID *Data); //HAL ADC receive
RTK_STATUS (*HalADCIntrCtrl) (VOID *Data); //HAL ADC interrupt control
u32 (*HalADCReadReg) (VOID *Data, u8 ADCReg);//HAL ADC read register
}HAL_ADC_OP, *PHAL_ADC_OP;
// ADC user callback adapter
typedef struct _SAL_ADC_USERCB_ADPT_ {
VOID (*USERCB) (VOID *Data);
u32 USERData;
}SAL_ADC_USERCB_ADPT, *PSAL_ADC_USERCB_ADPT;
// ADC user callback structure
typedef struct _SAL_ADC_USER_CB_ {
PSAL_ADC_USERCB_ADPT pTXCB; //ADC Transmit Callback
PSAL_ADC_USERCB_ADPT pTXCCB; //ADC Transmit Complete Callback
PSAL_ADC_USERCB_ADPT pRXCB; //ADC Receive Callback
PSAL_ADC_USERCB_ADPT pRXCCB; //ADC Receive Complete Callback
PSAL_ADC_USERCB_ADPT pRDREQCB; //ADC Read Request Callback
PSAL_ADC_USERCB_ADPT pERRCB; //ADC Error Callback
PSAL_ADC_USERCB_ADPT pDMATXCB; //ADC DMA Transmit Callback
PSAL_ADC_USERCB_ADPT pDMATXCCB; //ADC DMA Transmit Complete Callback
PSAL_ADC_USERCB_ADPT pDMARXCB; //ADC DMA Receive Callback
PSAL_ADC_USERCB_ADPT pDMARXCCB; //ADC DMA Receive Complete Callback
}SAL_ADC_USER_CB, *PSAL_ADC_USER_CB;
// ADC Transmit Buffer
typedef struct _SAL_ADC_TRANSFER_BUF_ {
u32 DataLen; //ADC Transmfer Length
u32 *pDataBuf; //ADC Transfer Buffer Pointer
u32 RSVD; //
}SAL_ADC_TRANSFER_BUF,*PSAL_ADC_TRANSFER_BUF;
typedef struct _SAL_ADC_DMA_USER_DEF_ {
u8 TxDatSrcWdth;
u8 TxDatDstWdth;
u8 TxDatSrcBstSz;
u8 TxDatDstBstSz;
u8 TxChNo;
u8 LlpCtrl;
u16 RSVD0;
u32 MaxMultiBlk;
u32 pLlix;
u32 pBlockSizeList;
}SAL_ADC_DMA_USER_DEF, *PSAL_ADC_DMA_USER_DEF;
// Software API Level ADC Handler
typedef struct _SAL_ADC_HND_ {
u8 DevNum; //ADC device number
u8 PinMux; //ADC pin mux seletion
u8 OpType; //ADC operation type selection
volatile u8 DevSts; //ADC device status
u32 ADCExd; //ADC extended options:
//bit 0: example
//bit 31~bit 1: Reserved
u32 ErrType; //
u32 TimeOut; //ADC IO Timeout count
PHAL_ADC_INIT_DAT pInitDat; //Pointer to ADC initial data struct
PSAL_ADC_TRANSFER_BUF pRXBuf; //Pointer to ADC TX buffer
PSAL_ADC_USER_CB pUserCB; //Pointer to ADC User Callback
}SAL_ADC_HND, *PSAL_ADC_HND;
// ADC SAL handle private
typedef struct _SAL_ADC_HND_PRIV_ {
VOID **ppSalADCHnd; //Pointer to SAL_ADC_HND pointer
SAL_ADC_HND SalADCHndPriv; //Private SAL_ADC_HND
}SAL_ADC_HND_PRIV, *PSAL_ADC_HND_PRIV;
//ADC SAL management adapter
typedef struct _SAL_ADC_MNGT_ADPT_ {
PSAL_ADC_HND_PRIV pSalHndPriv; //Pointer to SAL_ADC_HND
PHAL_ADC_INIT_DAT pHalInitDat; //Pointer to HAL ADC initial data( HAL_ADC_INIT_DAT )
PHAL_ADC_OP pHalOp; //Pointer to HAL ADC operation( HAL_ADC_OP )
VOID (*pHalOpInit)(VOID*);//Pointer to HAL ADC initialize function
PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
VOID (*pSalIrqFunc)(VOID*); //Used for SAL ADC interrupt function
PSAL_ADC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config
PHAL_GDMA_ADAPTER pHalGdmaAdp;
PHAL_GDMA_OP pHalGdmaOp;
PIRQ_HANDLE pIrqGdmaHnd;
VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function
PSAL_ADC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_ADC_USER_CB )
VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function
}SAL_ADC_MNGT_ADPT, *PSAL_ADC_MNGT_ADPT;
//================ ADC HAL Function Prototype ===================
// ADC HAL inline function
// For checking I2C input index valid or not
static inline RTK_STATUS
RtkADCIdxChk(
IN u8 ADCIdx
)
{
#if !ADC0_USED
if (ADCIdx == ADC0_SEL)
return _EXIT_FAILURE;
#endif
#if !ADC1_USED
if (ADCIdx == ADC1_SEL)
return _EXIT_FAILURE;
#endif
#if !ADC2_USED
if (ADCIdx == ADC2_SEL)
return _EXIT_FAILURE;
#endif
#if !ADC3_USED
if (ADCIdx == ADC3_SEL)
return _EXIT_FAILURE;
#endif
return _EXIT_SUCCESS;
}
VOID HalADCOpInit(IN VOID *Data);
PSAL_ADC_HND RtkADCGetSalHnd(IN u8 DACIdx);
RTK_STATUS RtkADCFreeSalHnd(IN PSAL_ADC_HND pSalADCHND);
RTK_STATUS RtkADCLoadDefault(IN VOID *Data);
RTK_STATUS RtkADCInit(IN VOID *Data);
RTK_STATUS RtkADCDeInit(IN VOID *Data);
//RTK_STATUS RtkADCReceive(IN VOID *Data);
u32 RtkADCReceive(IN VOID *Data);
u32 RtkADCReceiveBuf(IN VOID *Data,IN u32 *pBuf);
PSAL_ADC_MNGT_ADPT RtkADCGetMngtAdpt(IN u8 ADCIdx);
RTK_STATUS RtkADCFreeMngtAdpt(IN PSAL_ADC_MNGT_ADPT pSalADCMngtAdpt);
VOID ADCISRHandle(IN VOID *Data);
VOID ADCGDMAISRHandle(IN VOID *Data);
HAL_Status RtkADCDisablePS(IN VOID *Data);
HAL_Status RtkADCEnablePS(IN VOID *Data);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_API_H_
#define _HAL_API_H_
#include "basic_types.h"
#include "hal_irqn.h"
#define HAL_READ32(base, addr) \
rtk_le32_to_cpu(*((volatile u32*)(base + addr)))
#define HAL_WRITE32(base, addr, value32) \
((*((volatile u32*)(base + addr))) = rtk_cpu_to_le32(value32))
#define HAL_READ16(base, addr) \
rtk_le16_to_cpu(*((volatile u16*)(base + addr)))
#define HAL_WRITE16(base, addr, value) \
((*((volatile u16*)(base + addr))) = rtk_cpu_to_le16(value))
#define HAL_READ8(base, addr) \
(*((volatile u8*)(base + addr)))
#define HAL_WRITE8(base, addr, value) \
((*((volatile u8*)(base + addr))) = value)
#if 0
// These "extern _LONG_CALL_" function declaration are for RAM code building only
// For ROM code building, thses code should be marked off
extern _LONG_CALL_ u8
HalPinCtrlRtl8195A(
IN u32 Function,
IN u32 PinLocation,
IN BOOL Operation
);
extern _LONG_CALL_ VOID
HalSerialPutcRtl8195a(
IN u8 c
);
extern _LONG_CALL_ u8
HalSerialGetcRtl8195a(
IN BOOL PullMode
);
extern _LONG_CALL_ u32
HalSerialGetIsrEnRegRtl8195a(VOID);
extern _LONG_CALL_ VOID
HalSerialSetIrqEnRegRtl8195a (
IN u32 SetValue
);
extern _LONG_CALL_ VOID
VectorTableInitForOSRtl8195A(
IN VOID *PortSVC,
IN VOID *PortPendSVH,
IN VOID *PortSysTick
);
extern _LONG_CALL_ BOOL
VectorIrqRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ BOOL
VectorIrqUnRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ VOID
VectorIrqEnRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ VOID
VectorIrqDisRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
#endif
extern BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
extern VOID InitWDGIRQ(VOID);
#define PinCtrl HalPinCtrlRtl8195A
#define DiagPutChar HalSerialPutcRtl8195a
#define DiagGetChar HalSerialGetcRtl8195a
#define DiagGetIsrEnReg HalSerialGetIsrEnRegRtl8195a
#define DiagSetIsrEnReg HalSerialSetIrqEnRegRtl8195a
#define InterruptForOSInit VectorTableInitForOSRtl8195A
#define InterruptRegister VectorIrqRegisterRtl8195A
#define InterruptUnRegister VectorIrqUnRegisterRtl8195A
#define InterruptEn VectorIrqEnRtl8195A
#define InterruptDis VectorIrqDisRtl8195A
#define SpicFlashInit SpicFlashInitRtl8195A
#define Calibration32k En32KCalibration
#define WDGInit InitWDGIRQ
typedef enum _HAL_Status
{
HAL_OK = 0x00,
HAL_BUSY = 0x01,
HAL_TIMEOUT = 0x02,
HAL_ERR_PARA = 0x03, // error with invaild parameters
HAL_ERR_MEM = 0x04, // error with memory allocation failed
HAL_ERR_HW = 0x05, // error with hardware error
HAL_ERR_UNKNOWN = 0xee // unknown error
} HAL_Status;
#endif //_HAL_API_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_COMMON_H_
#define _HAL_COMMON_H_
//================= Function Prototype START ===================
HAL_Status HalCommonInit(void);
//================= Function Prototype END ===================
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef __HAL_CRYPTO_H__
#define __HAL_CRYPTO_H__
#include "hal_api.h"
#include "basic_types.h"
#define CRYPTO_MAX_MSG_LENGTH 16000
#define CRYPTO_MD5_DIGEST_LENGTH 16
#define CRYPTO_SHA1_DIGEST_LENGTH 20
#define CRYPTO_SHA2_DIGEST_LENGTH 32
typedef enum _SHA2_TYPE_ {
SHA2_NONE = 0,
SHA2_224 = 224/8,
SHA2_256 = 256/8,
SHA2_384 = 384/8,
SHA2_512 = 512/8
} SHA2_TYPE;
#define _ERRNO_CRYPTO_DESC_NUM_SET_OutRange -2
#define _ERRNO_CRYPTO_BURST_NUM_SET_OutRange -3
#define _ERRNO_CRYPTO_NULL_POINTER -4
#define _ERRNO_CRYPTO_ENGINE_NOT_INIT -5
#define _ERRNO_CRYPTO_ADDR_NOT_4Byte_Aligned -6
#define _ERRNO_CRYPTO_KEY_OutRange -7
#define _ERRNO_CRYPTO_MSG_OutRange -8
#define _ERRNO_CRYPTO_IV_OutRange -9
#define _ERRNO_CRYPTO_AUTH_TYPE_NOT_MATCH -10
#define _ERRNO_CRYPTO_CIPHER_TYPE_NOT_MATCH -11
#define _ERRNO_CRYPTO_KEY_IV_LEN_DIFF -12
//
// External API Functions
//
// Crypto Engine
extern int rtl_cryptoEngine_init(void);
extern void rtl_cryptoEngine_info(void);
//
// Authentication
//
// md5
extern int rtl_crypto_md5(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
extern int rtl_crypto_md5_init(void);
extern int rtl_crypto_md5_process(IN const u8* message, const IN u32 msglen, OUT u8* pDigest);
// sha1
extern int rtl_crypto_sha1(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
extern int rtl_crypto_sha1_init(void);
extern int rtl_crypto_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// sha2
extern int rtl_crypto_sha2(IN const SHA2_TYPE sha2type,
IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
extern int rtl_crypto_sha2_init(IN const SHA2_TYPE sha2type);
extern int rtl_crypto_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// HMAC-md5
extern int rtl_crypto_hmac_md5(IN const u8* message, IN const u32 msglen,
IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
extern int rtl_crypto_hmac_md5_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_hmac_md5_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// HMAC-sha1
extern int rtl_crypto_hmac_sha1(IN const u8* message, IN const u32 msglen,
IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
extern int rtl_crypto_hmac_sha1_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_hmac_sha1_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
// HMAC-sha2
extern int rtl_crypto_hmac_sha2(IN const SHA2_TYPE sha2type, IN const u8* message, IN const u32 msglen,
IN const u8* key, IN const u32 keylen, OUT u8* pDigest);
extern int rtl_crypto_hmac_sha2_init(IN const SHA2_TYPE sha2type, IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_hmac_sha2_process(IN const u8* message, IN const u32 msglen, OUT u8* pDigest);
//
// Cipher Functions
//
// AES - CBC
extern int rtl_crypto_aes_cbc_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_aes_cbc_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_aes_cbc_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// AES - ECB
extern int rtl_crypto_aes_ecb_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_aes_ecb_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_aes_ecb_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// AES - CTR
extern int rtl_crypto_aes_ctr_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_aes_ctr_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_aes_ctr_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// 3DES - CBC
extern int rtl_crypto_3des_cbc_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_3des_cbc_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_3des_cbc_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// 3DES - ECB
extern int rtl_crypto_3des_ecb_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_3des_ecb_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_3des_ecb_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// DES - CBC
extern int rtl_crypto_des_cbc_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_des_cbc_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_des_cbc_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
// DES - ECB
extern int rtl_crypto_des_ecb_init(IN const u8* key, IN const u32 keylen);
extern int rtl_crypto_des_ecb_encrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
extern int rtl_crypto_des_ecb_decrypt(
IN const u8* message, IN const u32 msglen,
IN const u8* iv, IN const u32 ivlen, OUT u8* pResult);
//
// C functions in ROM
//
extern int rtl_memcmpb(const u8 *dst, const u8 *src, int bytes);
extern int rtl_memcpyb(u8 *dst, const u8 *src, int bytes);
#endif /* __HAL_CRYPTO_H__ */

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//======================================================
// Routines to access hardware
//
// Copyright (c) 2013 Realtek Semiconductor Corp.
//
// This module is a confidential and proprietary property of RealTek and
// possession or use of this module requires written permission of RealTek.
//======================================================
#ifndef _HAL_DAC_H_
#define _HAL_DAC_H_
#include "rtl8195a.h"
#include "rtl8195a_dac.h"
#include "hal_api.h"
#include "hal_gdma.h"
//================ DAC Configuration =========================
#define DAC_INTR_OP_TYPE 1
#define DAC_DMA_OP_TYPE 1
// DAC SAL management macros
#define SAL_DAC_USER_CB_NUM (sizeof(SAL_DAC_USER_CB) / sizeof(PSAL_DAC_USERCB_ADPT))
// DAC SAL used module.
// Please set the DAC module flag to 1 to enable the related DAC module functions.
#define DAC0_USED 1
#define DAC1_USED 1
//================ Debug MSG Definition =======================
#define DAC_PREFIX "RTL8195A[dac]: "
#define DAC_PREFIX_LVL " [DAC_DBG]: "
typedef enum _DAC_DBG_LVL_ {
HAL_DAC_LVL = 0x00,
SAL_DAC_LVL = 0x02,
VERI_DAC_LVL = 0x04,
}DAC_DBG_LVL,*PDAC_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_DAC_HAL
#define DBG_8195A_DAC(...) do{ \
_DbgDump("\r"DAC_PREFIX __VA_ARGS__);\
}while(0)
#define DACDBGLVL 0xFF
#define DBG_8195A_DAC_LVL(LVL,...) do{\
if (LVL&DACDBGLVL){\
_DbgDump("\r"DAC_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_DAC_LOG_PERD 100
#define DBG_8195A_DAC(...)
#define DBG_8195A_DAC_LVL(...)
#endif
#endif
//================ DAC HAL Related Enumeration ==================
// DAC Module Selection
typedef enum _DAC_MODULE_SEL_ {
DAC0_SEL = 0x0,
DAC1_SEL = 0x1,
}DAC_MODULE_SEL,*PDAC_MODULE_SEL;
// DAC module status
typedef enum _DAC_MODULE_STATUS_ {
DAC_DISABLE = 0x0,
DAC_ENABLE = 0x1,
}DAC_MODULE_STATUS, *PDAC_MODULE_STATUS;
// DAC Data Rate
typedef enum _DAC_DATA_RATE_ {
DAC_DATA_RATE_10K = 0x0,
DAC_DATA_RATE_250K = 0x1,
}DAC_DATA_RATE,*PDAC_DATA_RATE;
// DAC Data Endian
typedef enum _DAC_DATA_ENDIAN_ {
DAC_DATA_ENDIAN_LITTLE = 0x0,
DAC_DATA_ENDIAN_BIG = 0x1,
}DAC_DATA_ENDIAN,*PDAC_DATA_ENDIAN;
// DAC Debug Select
typedef enum _DAC_DEBUG_SEL_ {
DAC_DBG_SEL_DISABLE = 0x0,
DAC_DBG_SEL_ENABLE = 0x1,
}DAC_DEBUG_SEL,*PDAC_DEBUG_SEL;
// DAC Dsc Debug Select
typedef enum _DAC_DSC_DEBUG_SEL_ {
DAC_DSC_DBG_SEL_DISABLE = 0x0,
DAC_DSC_DBG_SEL_ENABLE = 0x1,
}DAC_DSC_DEBUG_SEL,*PDAC_DSC_DEBUG_SEL;
// DAC Bypass Dsc Debug Select
typedef enum _DAC_BYPASS_DSC_SEL_ {
DAC_BYPASS_DSC_SEL_DISABLE = 0x0,
DAC_BYPASS_DSC_SEL_ENABLE = 0x1,
}DAC_BYPASS_DSC_SEL,*PDAC_BYPASS_DSC_SEL;
// DAC feature status
typedef enum _DAC_FEATURE_STATUS_{
DAC_FEATURE_DISABLED = 0,
DAC_FEATURE_ENABLED = 1,
}DAC_FEATURE_STATUS,*PDAC_FEATURE_STATUS;
// DAC operation type
typedef enum _DAC_OP_TYPE_ {
DAC_POLL_TYPE = 0x0,
DAC_DMA_TYPE = 0x1,
DAC_INTR_TYPE = 0x2,
}DAC_OP_TYPE, *PDAC_OP_TYPE;
// DAC device status
typedef enum _DAC_Device_STATUS_ {
DAC_STS_UNINITIAL = 0x00,
DAC_STS_INITIALIZED = 0x01,
DAC_STS_IDLE = 0x02,
DAC_STS_TX_READY = 0x03,
DAC_STS_TX_ING = 0x04,
DAC_STS_RX_READY = 0x05,
DAC_STS_RX_ING = 0x06,
DAC_STS_ERROR = 0x07,
}DAC_Device_STATUS, *PDAC_Device_STATUS;
//DAC device error type
typedef enum _DAC_ERR_TYPE_ {
DAC_ERR_FIFO_OVER = 0x04, //DAC FIFO overflow.
DAC_ERR_FIFO_STOP = 0x08, //DAC FIFO is completely empty, and it will be stopped automatically.
DAC_ERR_FIFO_WRFAIL = 0x10, //When DAC is NOT enabled, a write operation attempts to access DAC register.
DAC_ERR_FIFO_DSC_OVER0 = 0x20,
DAC_ERR_FIFO_DSC_OVER1 = 0x40,
}DAC_ERR_TYPE, *PDAC_ERR_TYPE;
// DAC data input method
typedef enum _DAC_INPUT_TYPE_{
DAC_INPUT_SINGLE_WR = 0x1, //DAC input by using single register write
DAC_INPUT_DMA_ONEBLK = 0x2, //DAC input by using single DMA block
DAC_INPUT_DMA_LLP = 0x3, //DAC input by using DMA linked list mode
}DAC_INPUT_TYPE,*PDAC_INPUT_TYPE;
//======================================================
// DAC HAL initial data structure
typedef struct _HAL_DAC_INIT_DAT_ {
u8 DACIdx; //DAC index used
u8 DACEn; //DAC module enable
u8 DACDataRate; //DAC data rate, 1'b0:10KHz, 1'b1:250KHz
u8 DACEndian; //DAC endian selection,
//but actually it's for 32-bit DAC data swap control
//1'b0: no swap,
//1'b1: swap the upper 16-bit and the lower 16-bit
u8 DACFilterSet; //DAC filter settle
u8 DACBurstSz; //DAC burst size
u8 DACDbgSel; //DAC debug sel
u8 DACDscDbgSel; //DAC debug dsc sel
u8 DACBPDsc; //DAC bypass delta sigma for loopback
u8 DACDeltaSig; //DAC bypass value of delta sigma
u16 RSVD1;
u32 *DACData; //DAC data pointer
u32 DACPWCtrl; //DAC0 and DAC1 power control
u32 DACAnaCtrl0; //DAC anapar_da control 0
u32 DACAnaCtrl1; //DAC anapar_da control 1
u32 DACIntrMSK; //DAC Interrupt Mask
}HAL_DAC_INIT_DAT,*PHAL_DAC_INIT_DAT;
// DAC HAL Operations
typedef struct _HAL_DAC_OP_ {
RTK_STATUS (*HalDACInit) (VOID *Data); //HAL DAC initialization
RTK_STATUS (*HalDACDeInit) (VOID *Data); //HAL DAC de-initialization
RTK_STATUS (*HalDACEnable) (VOID *Data); //HAL DAC de-initialization
u8 (*HalDACSend) (VOID *Data); //HAL DAC receive
RTK_STATUS (*HalDACIntrCtrl) (VOID *Data); //HAL DAC interrupt control
u32 (*HalDACReadReg) (VOID *Data, u8 DACReg);//HAL DAC read register
}HAL_DAC_OP, *PHAL_DAC_OP;
// DAC user callback adapter
typedef struct _SAL_DAC_USERCB_ADPT_ {
VOID (*USERCB) (VOID *Data);
u32 USERData;
}SAL_DAC_USERCB_ADPT, *PSAL_DAC_USERCB_ADPT;
// DAC user callback structure
typedef struct _SAL_DAC_USER_CB_ {
PSAL_DAC_USERCB_ADPT pTXCB; //DAC Transmit Callback
PSAL_DAC_USERCB_ADPT pTXCCB; //DAC Transmit Complete Callback
PSAL_DAC_USERCB_ADPT pRXCB; //DAC Receive Callback
PSAL_DAC_USERCB_ADPT pRXCCB; //DAC Receive Complete Callback
PSAL_DAC_USERCB_ADPT pRDREQCB; //DAC Read Request Callback
PSAL_DAC_USERCB_ADPT pERRCB; //DAC Error Callback
PSAL_DAC_USERCB_ADPT pDMATXCB; //DAC DMA Transmit Callback
PSAL_DAC_USERCB_ADPT pDMATXCCB; //DAC DMA Transmit Complete Callback
PSAL_DAC_USERCB_ADPT pDMARXCB; //DAC DMA Receive Callback
PSAL_DAC_USERCB_ADPT pDMARXCCB; //DAC DMA Receive Complete Callback
}SAL_DAC_USER_CB, *PSAL_DAC_USER_CB;
// DAC Transmit Buffer
typedef struct _SAL_DAC_TRANSFER_BUF_ {
u32 DataLen; //DAC Transmfer Length
u32 *pDataBuf; //DAC Transfer Buffer Pointer
u32 RSVD; //
}SAL_DAC_TRANSFER_BUF,*PSAL_DAC_TRANSFER_BUF;
typedef struct _SAL_DAC_DMA_USER_DEF_ {
u8 TxDatSrcWdth;
u8 TxDatDstWdth;
u8 TxDatSrcBstSz;
u8 TxDatDstBstSz;
u8 TxChNo;
u8 LlpCtrl;
u16 RSVD0;
u32 MaxMultiBlk;
u32 pLlix;
u32 pBlockSizeList;
}SAL_DAC_DMA_USER_DEF, *PSAL_DAC_DMA_USER_DEF;
// Software API Level DAC Handler
typedef struct _SAL_DAC_HND_ {
u8 DevNum; //DAC device number
u8 PinMux; //DAC pin mux seletion
u8 OpType; //DAC operation type selection
volatile u8 DevSts; //DAC device status
u8 DACInType; //DAC input type
u8 RSVD0;
u16 RSVD1;
u32 DACExd; //DAC extended options:
//bit 0: example
//bit 31~bit 1: Reserved
u32 ErrType; //
u32 TimeOut; //DAC IO Timeout count
PHAL_DAC_INIT_DAT pInitDat; //Pointer to DAC initial data struct
PSAL_DAC_TRANSFER_BUF pTXBuf; //Pointer to DAC TX buffer
PSAL_DAC_USER_CB pUserCB; //Pointer to DAC User Callback
PSAL_DAC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA Config
}SAL_DAC_HND, *PSAL_DAC_HND;
// DAC SAL handle private
typedef struct _SAL_DAC_HND_PRIV_ {
VOID **ppSalDACHnd; //Pointer to SAL_DAC_HND pointer
SAL_DAC_HND SalDACHndPriv; //Private SAL_DAC_HND
}SAL_DAC_HND_PRIV, *PSAL_DAC_HND_PRIV;
//DAC SAL management adapter
typedef struct _SAL_DAC_MNGT_ADPT_ {
PSAL_DAC_HND_PRIV pSalHndPriv; //Pointer to SAL_DAC_HND
PHAL_DAC_INIT_DAT pHalInitDat; //Pointer to HAL DAC initial data( HAL_I2C_INIT_DAT )
PHAL_DAC_OP pHalOp; //Pointer to HAL DAC operation( HAL_DAC_OP )
VOID (*pHalOpInit)(VOID*); //Pointer to HAL DAC initialize function
PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
PSAL_DAC_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_DAC_USER_CB )
VOID (*pSalIrqFunc)(VOID*); //Used for SAL DAC interrupt function
PSAL_DAC_DMA_USER_DEF pDMAConf; //Pointer to DAC User Define DMA config
PHAL_GDMA_ADAPTER pHalGdmaAdp;
PHAL_GDMA_OP pHalGdmaOp;
VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL DAC initialize function
PIRQ_HANDLE pIrqGdmaHnd;
VOID (*pSalDMAIrqFunc)(VOID*); //Used for SAL DAC interrupt function
}SAL_DAC_MNGT_ADPT, *PSAL_DAC_MNGT_ADPT;
//================ DAC HAL Function Prototype ===================
// DAC HAL inline function
// For checking DAC input index valid or not
static inline RTK_STATUS
RtkDACIdxChk(
IN u8 DACIdx
)
{
#if !DAC0_USED
if (DACIdx == DAC0_SEL)
return _EXIT_FAILURE;
#endif
#if !DAC1_USED
if (DACIdx == DAC1_SEL)
return _EXIT_FAILURE;
#endif
return _EXIT_SUCCESS;
}
VOID HalDACOpInit(IN VOID *Data);
RTK_STATUS RtkDACLoadDefault(IN VOID *Data);
RTK_STATUS RtkDACInit(IN VOID *Data);
RTK_STATUS RtkDACDeInit(IN VOID *Data);
RTK_STATUS RtkDACSend(IN VOID *Data);
PSAL_DAC_HND RtkDACGetSalHnd(IN u8 DACIdx);
RTK_STATUS RtkDACFreeSalHnd(IN PSAL_DAC_HND pSalDACHND);
PSAL_DAC_MNGT_ADPT RtkDACGetMngtAdpt(IN u8 DACIdx);
RTK_STATUS RtkDACFreeMngtAdpt(IN PSAL_DAC_MNGT_ADPT pSalDACMngtAdpt);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_DIAG_H_
#define _HAL_DIAG_H_
//Register offset
#define UART_REV_BUF_OFF 0x00
#define UART_TRAN_HOLD_OFF 0x00
#define UART_DLH_OFF 0x04
#define UART_DLL_OFF 0x00
#define UART_INTERRUPT_EN_REG_OFF 0x04
#define UART_INTERRUPT_IDEN_REG_OFF 0x08
#define UART_FIFO_CTL_REG_OFF 0x08
#define UART_LINE_CTL_REG_OFF 0x0c
#define UART_MODEM_CTL_REG_OFF 0x10
#define UART_LINE_STATUS_REG_OFF 0x14
#define UART_MODEM_STATUS_REG_OFF 0x18
#define UART_FIFO_ACCESS_REG_OFF 0x70
#define UART_STATUS_REG_OFF 0x7c
#define UART_TFL_OFF 0x80
#define UART_RFL_OFF 0x84
//Buad rate
#define UART_BAUD_RATE_2400 2400
#define UART_BAUD_RATE_4800 4800
#define UART_BAUD_RATE_9600 9600
#define UART_BAUD_RATE_19200 19200
#define UART_BAUD_RATE_38400 38400
#define UART_BAUD_RATE_57600 57600
#define UART_BAUD_RATE_115200 115200
#define UART_BAUD_RATE_921600 921600
#define UART_BAUD_RATE_1152000 1152000
#define UART_PARITY_ENABLE 0x08
#define UART_PARITY_DISABLE 0
#define UART_DATA_LEN_5BIT 0x0
#define UART_DATA_LEN_6BIT 0x1
#define UART_DATA_LEN_7BIT 0x2
#define UART_DATA_LEN_8BIT 0x3
#define UART_STOP_1BIT 0x0
#define UART_STOP_2BIT 0x4
#define HAL_UART_READ32(addr) HAL_READ32(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE32(addr, value) HAL_WRITE32(LOG_UART_REG_BASE, addr, value)
#define HAL_UART_READ16(addr) HAL_READ16(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE16(addr, value) HAL_WRITE16(LOG_UART_REG_BASE, addr, value)
#define HAL_UART_READ8(addr) HAL_READ8(LOG_UART_REG_BASE, addr)
#define HAL_UART_WRITE8(addr, value) HAL_WRITE8(LOG_UART_REG_BASE, addr, value)
typedef struct _LOG_UART_ADAPTER_ {
u32 BaudRate;
u32 FIFOControl;
u32 IntEnReg;
u8 Parity;
u8 Stop;
u8 DataLength;
}LOG_UART_ADAPTER, *PLOG_UART_ADAPTER;
typedef struct _COMMAND_TABLE_ {
const u8* cmd;
u16 ArgvCnt;
u32 (*func)(u16 argc, u8* argv[]);
const u8* msg;
}COMMAND_TABLE, *PCOMMAND_TABLE;
//VOID
//HalLogUartHandle(void);
/*
extern _LONG_CALL_ROM_ u32
HalLogUartInit(
IN LOG_UART_ADAPTER UartAdapter
);
*/
extern _LONG_CALL_ROM_ VOID
HalSerialPutcRtl8195a(
IN u8 c
);
extern _LONG_CALL_ROM_ u8
HalSerialGetcRtl8195a(
IN BOOL PullMode
);
extern _LONG_CALL_ROM_ u32
HalSerialGetIsrEnRegRtl8195a(VOID);
extern _LONG_CALL_ROM_ VOID
HalSerialSetIrqEnRegRtl8195a (
IN u32 SetValue
);
#endif//_HAL_DIAG_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_EFUSE_H_
#define _HAL_EFUSE_H_
_LONG_CALL_ROM_ extern VOID HalEFUSEPowerSwitch8195AROM(IN u8 bWrite, IN u8 PwrState, IN u8 L25OutVoltage);
_LONG_CALL_ extern u32 HALEFUSEOneByteReadROM(IN u32 CtrlSetting, IN u16 Addr, OUT u8 *Data, IN u8 L25OutVoltage);
_LONG_CALL_ extern u32 HALEFUSEOneByteWriteROM(IN u32 CtrlSetting, IN u16 Addr, IN u8 Data, IN u8 L25OutVoltage);
#define EFUSERead8 HALEFUSEOneByteReadROM
#define EFUSEWrite8 HALEFUSEOneByteWriteROM
#define L25EOUTVOLTAGE 7
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_GDMA_H_
#define _HAL_GDMA_H_
#include "rtl8195a_gdma.h"
typedef struct _GDMA_CH_LLI_ELE_ {
u32 Sarx;
u32 Darx;
u32 Llpx;
u32 CtlxLow;
u32 CtlxUp;
u32 Temp;
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
#if 1
#if 0
typedef struct _GDMA_CH_LLI_ {
PGDMA_CH_LLI_ELE pLliEle;
PGDMA_CH_LLI pNextLli;
}GDMA_CH_LLI, *PGDMA_CH_LLI;
typedef struct _BLOCK_SIZE_LIST_ {
u32 BlockSize;
PBLOCK_SIZE_LIST pNextBlockSiz;
}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
#else
struct GDMA_CH_LLI {
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pNextLli;
};
struct BLOCK_SIZE_LIST {
u32 BlockSize;
struct BLOCK_SIZE_LIST *pNextBlockSiz;
};
#endif
#endif
typedef struct _HAL_GDMA_ADAPTER_ {
u32 ChSar;
u32 ChDar;
GDMA_CHANNEL_NUM ChEn;
GDMA_CTL_REG GdmaCtl;
GDMA_CFG_REG GdmaCfg;
u32 PacketLen;
u32 BlockLen;
u32 MuliBlockCunt;
u32 MaxMuliBlock;
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
typedef struct _HAL_GDMA_CHNL_ {
u8 GdmaIndx;
u8 GdmaChnl;
u8 IrqNum;
u8 Reserved;
}HAL_GDMA_CHNL, *PHAL_GDMA_CHNL;
typedef struct _HAL_GDMA_BLOCK_ {
u32 SrcAddr;
u32 DstAddr;
u32 BlockLength;
u32 SrcOffset;
u32 DstOffset;
}HAL_GDMA_BLOCK, *PHAL_GDMA_BLOCK;
typedef struct _HAL_GDMA_OP_ {
VOID (*HalGdmaOnOff)(VOID *Data);
BOOL (*HalGdamChInit)(VOID *Data);
BOOL (*HalGdmaChSeting)(VOID *Data);
BOOL (*HalGdmaChBlockSeting)(VOID *Data);
VOID (*HalGdmaChDis)(VOID *Data);
VOID (*HalGdmaChEn)(VOID *Data);
VOID (*HalGdmaChIsrEnAndDis) (VOID *Data);
u8 (*HalGdmaChIsrClean)(VOID *Data);
VOID (*HalGdmaChCleanAutoSrc)(VOID *Data);
VOID (*HalGdmaChCleanAutoDst)(VOID *Data);
}HAL_GDMA_OP, *PHAL_GDMA_OP;
typedef struct _HAL_GDMA_OBJ_ {
HAL_GDMA_ADAPTER HalGdmaAdapter;
IRQ_HANDLE GdmaIrqHandle;
volatile GDMA_CH_LLI_ELE GdmaChLli[16];
struct GDMA_CH_LLI Lli[16];
struct BLOCK_SIZE_LIST BlockSizeList[16];
u8 Busy; // is transfering
u8 BlockNum;
} HAL_GDMA_OBJ, *PHAL_GDMA_OBJ;
VOID HalGdmaOpInit(IN VOID *Data);
VOID HalGdmaOn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaOff(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChInit(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
BOOL HalGdmaChBlockSeting(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChIsrEn(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChIsrDis(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
u8 HalGdmaChIsrClean(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChCleanAutoSrc(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
VOID HalGdmaChCleanAutoDst(PHAL_GDMA_ADAPTER pHalGdmaAdapter);
extern HAL_Status HalGdmaChnlRegister (u8 GdmaIdx, u8 ChnlNum);
extern VOID HalGdmaChnlUnRegister (u8 GdmaIdx, u8 ChnlNum);
extern PHAL_GDMA_CHNL HalGdmaChnlAlloc (HAL_GDMA_CHNL *pChnlOption);
extern VOID HalGdmaChnlFree (HAL_GDMA_CHNL *pChnl);
extern BOOL HalGdmaMemCpyInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern VOID HalGdmaMemCpyDeInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern VOID* HalGdmaMemCpy(PHAL_GDMA_OBJ pHalGdmaObj, void* pDest, void* pSrc, u32 len);
extern VOID HalGdmaMemAggr(PHAL_GDMA_OBJ pHalGdmaObj, PHAL_GDMA_BLOCK pHalGdmaBlock);
extern BOOL HalGdmaMemCpyAggrInit(PHAL_GDMA_OBJ pHalGdmaObj);
extern const HAL_GDMA_OP _HalGdmaOp;
extern const HAL_GDMA_CHNL GDMA_Chnl_Option[];
extern const HAL_GDMA_CHNL GDMA_Multi_Block_Chnl_Option[];
extern const u16 HalGdmaChnlEn[6];
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_GPIO_H_
#define _HAL_GPIO_H_
#define HAL_GPIO_PIN_INT_MODE 0x80
typedef enum {
_PORT_A = 0,
_PORT_B = 1,
_PORT_C = 2,
_PORT_D = 3,
_PORT_E = 4,
_PORT_F = 5,
_PORT_G = 6,
_PORT_H = 7,
_PORT_I = 8,
_PORT_J = 9,
_PORT_K = 10,
_PORT_MAX
} HAL_GPIO_PORT_NAME;
typedef enum {
_PA_0 = (_PORT_A<<4|0),
_PA_1 = (_PORT_A<<4|1),
_PA_2 = (_PORT_A<<4|2),
_PA_3 = (_PORT_A<<4|3),
_PA_4 = (_PORT_A<<4|4),
_PA_5 = (_PORT_A<<4|5),
_PA_6 = (_PORT_A<<4|6),
_PA_7 = (_PORT_A<<4|7),
_PB_0 = (_PORT_B<<4|0),
_PB_1 = (_PORT_B<<4|1),
_PB_2 = (_PORT_B<<4|2),
_PB_3 = (_PORT_B<<4|3),
_PB_4 = (_PORT_B<<4|4),
_PB_5 = (_PORT_B<<4|5),
_PB_6 = (_PORT_B<<4|6),
_PB_7 = (_PORT_B<<4|7),
_PC_0 = (_PORT_C<<4|0),
_PC_1 = (_PORT_C<<4|1),
_PC_2 = (_PORT_C<<4|2),
_PC_3 = (_PORT_C<<4|3),
_PC_4 = (_PORT_C<<4|4),
_PC_5 = (_PORT_C<<4|5),
_PC_6 = (_PORT_C<<4|6),
_PC_7 = (_PORT_C<<4|7),
_PC_8 = (_PORT_C<<4|8),
_PC_9 = (_PORT_C<<4|9),
_PD_0 = (_PORT_D<<4|0),
_PD_1 = (_PORT_D<<4|1),
_PD_2 = (_PORT_D<<4|2),
_PD_3 = (_PORT_D<<4|3),
_PD_4 = (_PORT_D<<4|4),
_PD_5 = (_PORT_D<<4|5),
_PD_6 = (_PORT_D<<4|6),
_PD_7 = (_PORT_D<<4|7),
_PD_8 = (_PORT_D<<4|8),
_PD_9 = (_PORT_D<<4|9),
_PE_0 = (_PORT_E<<4|0),
_PE_1 = (_PORT_E<<4|1),
_PE_2 = (_PORT_E<<4|2),
_PE_3 = (_PORT_E<<4|3),
_PE_4 = (_PORT_E<<4|4),
_PE_5 = (_PORT_E<<4|5),
_PE_6 = (_PORT_E<<4|6),
_PE_7 = (_PORT_E<<4|7),
_PE_8 = (_PORT_E<<4|8),
_PE_9 = (_PORT_E<<4|9),
_PE_A = (_PORT_E<<4|10),
_PF_0 = (_PORT_F<<4|0),
_PF_1 = (_PORT_F<<4|1),
_PF_2 = (_PORT_F<<4|2),
_PF_3 = (_PORT_F<<4|3),
_PF_4 = (_PORT_F<<4|4),
_PF_5 = (_PORT_F<<4|5),
// _PF_6 = (_PORT_F<<4|6),
// _PF_7 = (_PORT_F<<4|7),
_PG_0 = (_PORT_G<<4|0),
_PG_1 = (_PORT_G<<4|1),
_PG_2 = (_PORT_G<<4|2),
_PG_3 = (_PORT_G<<4|3),
_PG_4 = (_PORT_G<<4|4),
_PG_5 = (_PORT_G<<4|5),
_PG_6 = (_PORT_G<<4|6),
_PG_7 = (_PORT_G<<4|7),
_PH_0 = (_PORT_H<<4|0),
_PH_1 = (_PORT_H<<4|1),
_PH_2 = (_PORT_H<<4|2),
_PH_3 = (_PORT_H<<4|3),
_PH_4 = (_PORT_H<<4|4),
_PH_5 = (_PORT_H<<4|5),
_PH_6 = (_PORT_H<<4|6),
_PH_7 = (_PORT_H<<4|7),
_PI_0 = (_PORT_I<<4|0),
_PI_1 = (_PORT_I<<4|1),
_PI_2 = (_PORT_I<<4|2),
_PI_3 = (_PORT_I<<4|3),
_PI_4 = (_PORT_I<<4|4),
_PI_5 = (_PORT_I<<4|5),
_PI_6 = (_PORT_I<<4|6),
_PI_7 = (_PORT_I<<4|7),
_PJ_0 = (_PORT_J<<4|0),
_PJ_1 = (_PORT_J<<4|1),
_PJ_2 = (_PORT_J<<4|2),
_PJ_3 = (_PORT_J<<4|3),
_PJ_4 = (_PORT_J<<4|4),
_PJ_5 = (_PORT_J<<4|5),
_PJ_6 = (_PORT_J<<4|6),
// _PJ_7 = (_PORT_J<<4|7),
_PK_0 = (_PORT_K<<4|0),
_PK_1 = (_PORT_K<<4|1),
_PK_2 = (_PORT_K<<4|2),
_PK_3 = (_PORT_K<<4|3),
_PK_4 = (_PORT_K<<4|4),
_PK_5 = (_PORT_K<<4|5),
_PK_6 = (_PORT_K<<4|6),
// _PK_7 = (_PORT_K<<4|7),
// Not connected
_PIN_NC = (int)0xFFFFFFFF
} HAL_PIN_NAME;
typedef enum
{
GPIO_PIN_LOW = 0,
GPIO_PIN_HIGH = 1,
GPIO_PIN_ERR = 2 // read Pin error
} HAL_GPIO_PIN_STATE;
typedef enum {
DIN_PULL_NONE = 0, //floating or high impedance ?
DIN_PULL_LOW = 1,
DIN_PULL_HIGH = 2,
DOUT_PUSH_PULL = 3,
DOUT_OPEN_DRAIN = 4,
INT_LOW = (5|HAL_GPIO_PIN_INT_MODE), // Interrupt Low level trigger
INT_HIGH = (6|HAL_GPIO_PIN_INT_MODE), // Interrupt High level trigger
INT_FALLING = (7|HAL_GPIO_PIN_INT_MODE), // Interrupt Falling edge trigger
INT_RISING = (8|HAL_GPIO_PIN_INT_MODE) // Interrupt Rising edge trigger
} HAL_GPIO_PIN_MODE;
enum {
GPIO_PORT_A = 0,
GPIO_PORT_B = 1,
GPIO_PORT_C = 2,
GPIO_PORT_D = 3
};
typedef enum {
hal_PullNone = 0,
hal_PullUp = 1,
hal_PullDown = 2,
hal_OpenDrain = 3,
hal_PullDefault = hal_PullNone
} HAL_PinMode;
typedef struct _HAL_GPIO_PORT_ {
u32 out_data; // to write the GPIO port
u32 in_data; // to read the GPIO port
u32 dir; // config each pin direction
}HAL_GPIO_PORT, *PHAL_GPIO_PORT;
#define HAL_GPIO_PIN_NAME(port,pin) (((port)<<5)|(pin))
#define HAL_GPIO_GET_PORT_BY_NAME(x) ((x>>5) & 0x03)
#define HAL_GPIO_GET_PIN_BY_NAME(x) (x & 0x1f)
typedef struct _HAL_GPIO_PIN_ {
HAL_GPIO_PIN_MODE pin_mode;
u32 pin_name; // Pin: [7:5]: port number, [4:0]: pin number
}HAL_GPIO_PIN, *PHAL_GPIO_PIN;
typedef struct _HAL_GPIO_OP_ {
#if defined(__ICCARM__)
void* dummy;
#endif
}HAL_GPIO_OP, *PHAL_GPIO_OP;
typedef void (*GPIO_IRQ_FUN)(VOID *Data, u32 Id);
typedef void (*GPIO_USER_IRQ_FUN)(u32 Id);
typedef struct _HAL_GPIO_ADAPTER_ {
IRQ_HANDLE IrqHandle; // GPIO HAL IRQ Handle
GPIO_USER_IRQ_FUN UserIrqHandler; // GPIO IRQ Handler
GPIO_IRQ_FUN PortA_IrqHandler[32]; // The interrupt handler triggered by Port A[x]
VOID *PortA_IrqData[32];
VOID (*EnterCritical)(void);
VOID (*ExitCritical)(void);
u32 Local_Gpio_Dir[3]; // to record direction setting: 0- IN, 1- Out
u8 Gpio_Func_En; // Is GPIO HW function enabled ?
u8 Locked;
}HAL_GPIO_ADAPTER, *PHAL_GPIO_ADAPTER;
u32
HAL_GPIO_GetPinName(
u32 chip_pin
);
VOID
HAL_GPIO_PullCtrl(
u32 pin,
u32 mode
);
VOID
HAL_GPIO_Init(
HAL_GPIO_PIN *GPIO_Pin
);
VOID
HAL_GPIO_Irq_Init(
HAL_GPIO_PIN *GPIO_Pin
);
#endif // end of "#define _HAL_GPIO_H_"

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_I2C_H_ //#ifndef _HAL_I2C_H_
#define _HAL_I2C_H_
#include "rtl8195a_i2c.h"
#include "hal_gdma.h"
//================= I2C CONFIGURATION START ==================
// I2C SAL User Configuration Flags
// I2C SAL operation types
#define I2C_POLL_OP_TYPE 1
#define I2C_INTR_OP_TYPE 1
#define I2C_DMA_OP_TYPE 1
// I2C supports user register address
#define I2C_USER_REG_ADDR 1 //I2C User specific register address by using
//the first I2C data as the register
//address
// I2C SAL used module. Please set the I2C module flag to 1 to enable the related
// I2C module functions.
#define I2C0_USED 1
#define I2C1_USED 1
#define I2C2_USED 1
#define I2C3_USED 1
//================= I2C CONFIGURATION END ===================
//================= I2C HAL START ==========================
// I2C debug output
#define I2C_PREFIX "RTL8195A[i2c]: "
#define I2C_PREFIX_LVL " [i2c_DBG]: "
typedef enum _I2C_DBG_LVL_ {
HAL_I2C_LVL = 0x01,
SAL_I2C_LVL = 0x02,
VERI_I2C_LVL = 0x03,
}I2C_DBG_LVL,*PI2C_DBG_LVL;
#ifdef CONFIG_DEBUG_LOG
#ifdef CONFIG_DEBUG_LOG_I2C_HAL
#define DBG_I2C_LOG_PERD 100
#define I2CDBGLVL 0xFF
#define DBG_8195A_I2C(...) do{ \
_DbgDump("\r"I2C_PREFIX __VA_ARGS__);\
}while(0)
#define DBG_8195A_I2C_LVL(LVL,...) do{\
if (LVL&I2CDBGLVL){\
_DbgDump("\r"I2C_PREFIX_LVL __VA_ARGS__);\
}\
}while(0)
#else
#define DBG_I2C_LOG_PERD 100
#define DBG_8195A_I2C(...)
#define DBG_8195A_I2C_LVL(...)
#endif
#else
#define DBG_I2C_LOG_PERD 100
#define DBG_8195A_I2C(...)
#define DBG_8195A_I2C_LVL(...)
#endif
//======================================================
// I2C HAL related enumeration
// I2C Module Selection
typedef enum _I2C_MODULE_SEL_ {
I2C0_SEL = 0x0,
I2C1_SEL = 0x1,
I2C2_SEL = 0x2,
I2C3_SEL = 0x3,
}I2C_MODULE_SEL,*PI2C_MODULE_SEL;
// I2C HAL initial data structure
typedef struct _HAL_I2C_INIT_DAT_ {
u8 I2CIdx; //I2C index used
u8 I2CEn; //I2C module enable
u8 I2CMaster; //Master or Slave mode
u8 I2CAddrMod; //I2C addressing mode(7-bit, 10-bit)
u8 I2CSpdMod; //I2C speed mode(Standard, Fast, High)
u8 I2CSetup; //I2C SDA setup time
u8 I2CRXTL; //I2C RX FIFO Threshold
u8 I2CTXTL; //I2C TX FIFO Threshold
u8 I2CBusLd; //I2C bus load (pf) for high speed mode
u8 I2CReSTR; //I2C restart support
u8 I2CGC; //I2C general support
u8 I2CStartB; //I2C start byte support
u8 I2CSlvNoAck; //I2C slave no ack support
u8 I2CDMACtrl; //I2C DMA feature support
u8 I2CCmd; //I2C Command
u8 I2CDataLen; //I2C Data Length
u8 I2CSlvAckGC; //I2C slave acks to General Call
u8 I2CStop; //I2C issues STOP bit or not
u16 RSVD0;
u8 *I2CRWData; //I2C Read/Write data pointer
u16 I2CIntrMSK; //I2C Interrupt Mask
u16 I2CIntrClr; //I2C Interrupt register to clear
u16 I2CAckAddr; //I2C target address in I2C Master mode,
//ack address in I2C Slave mode
u16 I2CSdaHd; //I2C SDA hold time
u32 I2CClk; //I2C bus clock (in kHz)
u8 I2CTxDMARqLv; //I2C TX DMA Empty Level
u8 I2CRxDMARqLv; //I2C RX DMA Full Level
u16 RSVD1; //Reserved
}HAL_I2C_INIT_DAT,*PHAL_I2C_INIT_DAT;
// I2C HAL Operations
typedef struct _HAL_I2C_OP_ {
HAL_Status (*HalI2CInit) (VOID *Data); //HAL I2C initialization
HAL_Status (*HalI2CDeInit) (VOID *Data); //HAL I2C de-initialization
HAL_Status (*HalI2CSend) (VOID *Data); //HAL I2C send
u8 (*HalI2CReceive) (VOID *Data); //HAL I2C receive
HAL_Status (*HalI2CEnable) (VOID *Data); //HAL I2C enable module
HAL_Status (*HalI2CIntrCtrl) (VOID *Data); //HAL I2C interrupt control
u32 (*HalI2CReadReg) (VOID *Data, u8 I2CReg);//HAL I2C read register
HAL_Status (*HalI2CWriteReg) (VOID *Data, u8 I2CReg, u32 RegVal);//HAL I2C write register
HAL_Status (*HalI2CSetCLK) (VOID *Data); //HAL I2C set bus clock
HAL_Status (*HalI2CMassSend) (VOID *Data); //HAL I2C mass send
HAL_Status (*HalI2CClrIntr) (VOID *Data); //HAL I2C clear interrupts
HAL_Status (*HalI2CClrAllIntr) (VOID *Data); //HAL I2C clear all interrupts
HAL_Status (*HalI2CDMACtrl) (VOID *Data); //HAL I2C DMA control
}HAL_I2C_OP, *PHAL_I2C_OP;
//================= I2C HAL END ===========================
//================= I2C SAL START ==========================
//I2C SAL Macros
//======================================================
// I2C SAL related enumerations
// I2C Extend Features
typedef enum _I2C_EXD_SUPPORT_{
I2C_EXD_RESTART = 0x1, //BIT_0, RESTART bit
I2C_EXD_GENCALL = 0x2, //BIT_1, Master generates General Call. All "send" operations generate General Call addresss
I2C_EXD_STARTB = 0x4, //BIT_2, Using START BYTE, instead of START Bit
I2C_EXD_SLVNOACK = 0x8, //BIT_3, Slave no ack to master
I2C_EXD_BUS400PF = 0x10, //BIT_4, I2C bus loading is 400pf
I2C_EXD_SLVACKGC = 0x20, //BIT_5, Slave acks to a General Call
I2C_EXD_USER_REG = 0x40, //BIT_6, Using User Register Address
I2C_EXD_USER_TWOB = 0x80, //BIT_7, User Register Address is 2-byte
I2C_EXD_MTR_ADDR_RTY= 0x100, //BIT_8, Master retries to send start condition and Slave address when the slave doesn't ack
// the address.
I2C_EXD_MTR_ADDR_UPD= 0x200, //BIT_9, Master dynamically updates slave address
I2C_EXD_MTR_HOLD_BUS= 0x400, //BIT_10, Master doesn't generate STOP when the FIFO is empty. This would make Master hold
// the bus.
}I2C_EXD_SUPPORT,*PI2C_EXD_SUPPORT;
// I2C operation type
typedef enum _I2C_OP_TYPE_ {
I2C_POLL_TYPE = 0x0,
I2C_DMA_TYPE = 0x1,
I2C_INTR_TYPE = 0x2,
}I2C_OP_TYPE, *PI2C_OP_TYPE;
// I2C pinmux selection
typedef enum _I2C_PINMUX_ {
I2C_PIN_S0 = 0x0,
I2C_PIN_S1 = 0x1,
I2C_PIN_S2 = 0x2,
I2C_PIN_S3 = 0x3, //Only valid for I2C0 and I2C3
}I2C_PINMUX, *PI2C_PINMUX;
// I2C module status
typedef enum _I2C_MODULE_STATUS_ {
I2C_DISABLE = 0x0,
I2C_ENABLE = 0x1,
}I2C_MODULE_STATUS, *PI2C_MODULE_STATUS;
// I2C device status
typedef enum _I2C_Device_STATUS_ {
I2C_STS_UNINITIAL = 0x00,
I2C_STS_INITIALIZED = 0x01,
I2C_STS_IDLE = 0x02,
I2C_STS_TX_READY = 0x03,
I2C_STS_TX_ING = 0x04,
I2C_STS_RX_READY = 0x05,
I2C_STS_RX_ING = 0x06,
I2C_STS_ERROR = 0x10,
I2C_STS_TIMEOUT = 0x11,
}I2C_Device_STATUS, *PI2C_Device_STATUS;
// I2C feature status
typedef enum _I2C_FEATURE_STATUS_{
I2C_FEATURE_DISABLED = 0,
I2C_FEATURE_ENABLED = 1,
}I2C_FEATURE_STATUS,*PI2C_FEATURE_STATUS;
// I2C device mode
typedef enum _I2C_DEV_MODE_ {
I2C_SLAVE_MODE = 0x0,
I2C_MASTER_MODE = 0x1,
}I2C_DEV_MODE, *PI2C_DEV_MODE;
// I2C Bus Transmit/Receive
typedef enum _I2C_DIRECTION_ {
I2C_ONLY_TX = 0x1,
I2C_ONLY_RX = 0x2,
I2C_TXRX = 0x3,
}I2C_DIRECTION, *PI2C_DIRECTION;
//I2C DMA module number
typedef enum _I2C_DMA_MODULE_SEL_ {
I2C_DMA_MODULE_0 = 0x0,
I2C_DMA_MODULE_1 = 0x1
}I2C_DMA_MODULE_SEL, *PI2C_DMA_MODULE_SEL;
// I2C0 DMA peripheral number
typedef enum _I2C0_DMA_PERI_NUM_ {
I2C0_DMA_TX_NUM = 0x8,
I2C0_DMA_RX_NUM = 0x9,
}I2C0_DMA_PERI_NUM,*PI2C0_DMA_PERI_NUM;
// I2C1 DMA peripheral number
typedef enum _I2C1_DMA_PERI_NUM_ {
I2C1_DMA_TX_NUM = 0xA,
I2C1_DMA_RX_NUM = 0xB,
}I2C1_DMA_PERI_NUM,*PI2C1_DMA_PERI_NUM;
// I2C0 DMA module used
typedef enum _I2C0_DMA_MODULE_ {
I2C0_DMA0 = 0x0,
I2C0_DMA1 = 0x1,
}I2C0_DMA_MODULE,*PI2C0_DMA_MODULE;
// I2C0 DMA module used
typedef enum _I2C1_DMA_MODULE_ {
I2C1_DMA0 = 0x0,
I2C1_DMA1 = 0x1,
}I2C1_DMA_MODULE,*PI2C1_DMA_MODULE;
// I2C command type
typedef enum _I2C_COMMAND_TYPE_ {
I2C_WRITE_CMD = 0x0,
I2C_READ_CMD = 0x1,
}I2C_COMMAND_TYPE,*PI2C_COMMAND_TYPE;
// I2C STOP BIT
typedef enum _I2C_STOP_TYPE_ {
I2C_STOP_DIS = 0x0,
I2C_STOP_EN = 0x1,
}I2C_STOP_TYPE, *PI2C_STOP_TYPE;
// I2C error type
typedef enum _I2C_ERR_TYPE_ {
I2C_ERR_RX_UNDER = 0x01, //I2C RX FIFO Underflow
I2C_ERR_RX_OVER = 0x02, //I2C RX FIFO Overflow
I2C_ERR_TX_OVER = 0x04, //I2C TX FIFO Overflow
I2C_ERR_TX_ABRT = 0x08, //I2C TX terminated
I2C_ERR_SLV_TX_NACK = 0x10, //I2C slave transmission terminated by master NACK,
//but there are data in slave TX FIFO
I2C_ERR_USER_REG_TO = 0x20,
I2C_ERR_RX_CMD_TO = 0x21,
I2C_ERR_RX_FF_TO = 0x22,
I2C_ERR_TX_CMD_TO = 0x23,
I2C_ERR_TX_FF_TO = 0x24,
I2C_ERR_TX_ADD_TO = 0x25,
I2C_ERR_RX_ADD_TO = 0x26,
}I2C_ERR_TYPE, *PI2C_ERR_TYPE;
// I2C Time Out type
typedef enum _I2C_TIMEOUT_TYPE_ {
I2C_TIMEOOUT_DISABLE = 0x00,
I2C_TIMEOOUT_ENDLESS = 0xFFFFFFFF,
}I2C_TIMEOUT_TYPE, *PI2C_TIMEOUT_TYPE;
//======================================================
// SAL I2C related data structures
// I2C user callback adapter
typedef struct _SAL_I2C_USERCB_ADPT_ {
VOID (*USERCB) (VOID *Data);
u32 USERData;
}SAL_I2C_USERCB_ADPT, *PSAL_I2C_USERCB_ADPT;
// I2C user callback structure
typedef struct _SAL_I2C_USER_CB_ {
PSAL_I2C_USERCB_ADPT pTXCB; //I2C Transmit Callback
PSAL_I2C_USERCB_ADPT pTXCCB; //I2C Transmit Complete Callback
PSAL_I2C_USERCB_ADPT pRXCB; //I2C Receive Callback
PSAL_I2C_USERCB_ADPT pRXCCB; //I2C Receive Complete Callback
PSAL_I2C_USERCB_ADPT pRDREQCB; //I2C Read Request Callback
PSAL_I2C_USERCB_ADPT pERRCB; //I2C Error Callback
PSAL_I2C_USERCB_ADPT pDMATXCB; //I2C DMA Transmit Callback
PSAL_I2C_USERCB_ADPT pDMATXCCB; //I2C DMA Transmit Complete Callback
PSAL_I2C_USERCB_ADPT pDMARXCB; //I2C DMA Receive Callback
PSAL_I2C_USERCB_ADPT pDMARXCCB; //I2C DMA Receive Complete Callback
PSAL_I2C_USERCB_ADPT pGENCALLCB; //I2C General Call Callback
}SAL_I2C_USER_CB, *PSAL_I2C_USER_CB;
// I2C Transmit Buffer
typedef struct _SAL_I2C_TRANSFER_BUF_ {
u16 DataLen; //I2C Transmfer Length
u16 TargetAddr; //I2C Target Address. It's only valid in Master Mode.
u32 RegAddr; //I2C Register Address. It's only valid in Master Mode.
u32 RSVD; //
u8 *pDataBuf; //I2C Transfer Buffer Pointer
}SAL_I2C_TRANSFER_BUF,*PSAL_I2C_TRANSFER_BUF;
typedef struct _SAL_I2C_DMA_USER_DEF_ {
u8 TxDatSrcWdth;
u8 TxDatDstWdth;
u8 TxDatSrcBstSz;
u8 TxDatDstBstSz;
u8 TxChNo;
u8 RSVD0;
u16 RSVD1;
u8 RxDatSrcWdth;
u8 RxDatDstWdth;
u8 RxDatSrcBstSz;
u8 RxDatDstBstSz;
u8 RxChNo;
u8 RSVD2;
u16 RSVD3;
}SAL_I2C_DMA_USER_DEF, *PSAL_I2C_DMA_USER_DEF;
// RTK I2C OP
typedef struct _RTK_I2C_OP_ {
HAL_Status (*Init) (VOID *Data);
HAL_Status (*DeInit) (VOID *Data);
HAL_Status (*Send) (VOID *Data);
HAL_Status (*Receive) (VOID *Data);
HAL_Status (*IoCtrl) (VOID *Data);
HAL_Status (*PowerCtrl) (VOID *Data);
}RTK_I2C_OP, *PRTK_I2C_OP;
// Software API Level I2C Handler
typedef struct _SAL_I2C_HND_ {
u8 DevNum; //I2C device number
u8 PinMux; //I2C pin mux seletion
u8 OpType; //I2C operation type selection
volatile u8 DevSts; //I2C device status
u8 I2CMaster; //I2C Master or Slave mode
u8 I2CAddrMod; //I2C 7-bit or 10-bit mode
u8 I2CSpdMod; //I2C SS/ FS/ HS speed mode
u8 I2CAckAddr; //I2C target address in Master
//mode or ack address in Slave
//mode
u16 I2CClk; //I2C bus clock
u8 MasterRead; //I2C Master Read Supported,
//An Address will be sent before
//read data back.
u8 I2CDmaSel; //I2C DMA module select
// 0 for DMA0,
// 1 for DMA1
u8 I2CTxDMARqLv; //I2C TX DMA Empty Level
u8 I2CRxDMARqLv; //I2C RX DMA Full Level
u16 RSVD0; //Reserved
u32 AddRtyTimeOut; //I2C TimeOut Value for master send address retry
//(Originally Reserved.)
u32 I2CExd; //I2C extended options:
//bit 0: I2C RESTART supported,
// 0 for NOT supported,
// 1 for supported
//bit 1: I2C General Call supported
// 0 for NOT supported,
// 1 for supported
//bit 2: I2C START Byte supported
// 0 for NOT supported,
// 1 for supported
//bit 3: I2C Slave-No-Ack
// supported
// 0 for NOT supported,
// 1 for supported
//bit 4: I2C bus loading,
// 0 for 100pf,
// 1 for 400pf
//bit 5: I2C slave ack to General
// Call
//bit 6: I2C User register address
//bit 7: I2C 2-Byte User register
// address
//bit 8: I2C slave address no ack retry,
// It's only for Master mode,
// when slave doesn't ack the
// address
//bit 31~bit 8: Reserved
u32 ErrType; //
u32 TimeOut; //I2C IO Timeout count, in ms
PHAL_I2C_INIT_DAT pInitDat; //Pointer to I2C initial data struct
PSAL_I2C_TRANSFER_BUF pTXBuf; //Pointer to I2C TX buffer
PSAL_I2C_TRANSFER_BUF pRXBuf; //Pointer to I2C RX buffer
PSAL_I2C_USER_CB pUserCB; //Pointer to I2C User Callback
PSAL_I2C_DMA_USER_DEF pDMAConf; //Pointer to I2C User Define DMA config
}SAL_I2C_HND, *PSAL_I2C_HND;
//======================================================
// I2C SAL Function Prototypes
// For checking I2C input index valid or not
static inline HAL_Status
RtkI2CIdxChk(
IN u8 I2CIdx
)
{
if (I2CIdx > I2C3_SEL)
return HAL_ERR_UNKNOWN;
return HAL_OK;
}
#if 0
//For checking I2C operation type valid or not
static inline HAL_Status
RtkI2COpTypeChk(
IN VOID *Data
)
{
PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data;
if (pSalI2CHND->OpType == I2C_POLL_TYPE)
return HAL_ERR_UNKNOWN;
if (pSalI2CHND->OpType == I2C_DMA_TYPE)
return HAL_ERR_UNKNOWN;
if (pSalI2CHND->OpType == I2C_INTR_TYPE)
return HAL_ERR_UNKNOWN;
pSalI2CHND = pSalI2CHND;
return HAL_OK;
}
#endif
//For checking I2C DMA available or not
static inline HAL_Status
RtkI2CDMAChk(
IN VOID *Data
)
{
PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data;
if (pSalI2CHND->OpType == I2C_DMA_TYPE) {
if (pSalI2CHND->DevNum >= I2C2_SEL)
return HAL_ERR_UNKNOWN;
}
else {
return HAL_ERR_UNKNOWN;
}
return HAL_OK;
}
//For checking I2C DMA available or not
static inline HAL_Status
RtkI2CDMAInitChk(
IN VOID *Data
)
{
PSAL_I2C_HND pSalI2CHND = (PSAL_I2C_HND) Data;
if (pSalI2CHND->OpType != I2C_DMA_TYPE) {
return HAL_ERR_UNKNOWN;
}
else {
return HAL_OK;
}
}
//======================================================
//SAL I2C management function prototype
_LONG_CALL_ROM_ HAL_Status RtkI2CLoadDefault(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CInit(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CDeInit(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CSend(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CReceive(IN VOID *Data);
_LONG_CALL_ROM_ VOID RtkSalI2COpInit(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CSendUserAddr(IN VOID *Data,IN u8 MtrWr);
_LONG_CALL_ROM_ HAL_Status RtkI2CIoCtrl(IN VOID *Data);
_LONG_CALL_ROM_ HAL_Status RtkI2CPowerCtrl(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CInitForPS(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CDeInitForPS(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CDisablePS(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CEnablePS(IN VOID *Data);
//================= I2C SAL END ===========================
//================= I2C SAL MANAGEMENT START =================
// I2C SAL management macros
#define SAL_USER_CB_NUM (sizeof(SAL_I2C_USER_CB) / sizeof(PSAL_I2C_USERCB_ADPT))
//======================================================
// I2C SAL management data structures
// I2C SAL handle private
typedef struct _SAL_I2C_HND_PRIV_ {
VOID **ppSalI2CHnd; //Pointer to SAL_I2C_HND pointer
SAL_I2C_HND SalI2CHndPriv; //Private SAL_I2C_HND
}SAL_I2C_HND_PRIV, *PSAL_I2C_HND_PRIV;
//I2C SAL management adapter
typedef struct _SAL_I2C_MNGT_ADPT_ {
PSAL_I2C_HND_PRIV pSalHndPriv; //Pointer to SAL_I2C_HND
PHAL_I2C_INIT_DAT pHalInitDat; //Pointer to HAL I2C initial data( HAL_I2C_INIT_DAT )
PHAL_I2C_OP pHalOp; //Pointer to HAL I2C operation( HAL_I2C_OP )
VOID (*pHalOpInit)(VOID*); //Pointer to HAL I2C initialize function
PIRQ_HANDLE pIrqHnd; //Pointer to IRQ handler in SAL layer( IRQ_HANDLE )
PSAL_I2C_USER_CB pUserCB; //Pointer to SAL user callbacks (SAL_I2C_USER_CB )
volatile u32 MstRDCmdCnt; //Used for Master Read command count
volatile u32 InnerTimeOut; //Used for SAL internal timeout count
VOID (*pSalIrqFunc)(VOID*); //Used for SAL I2C interrupt function
PSAL_I2C_DMA_USER_DEF pDMAConf; //Pointer to I2C User Define DMA config
PHAL_GDMA_ADAPTER pHalTxGdmaAdp; //Pointer to HAL_GDMA_ADAPTER
PHAL_GDMA_ADAPTER pHalRxGdmaAdp; //Pointer to HAL_GDMA_ADAPTER
PHAL_GDMA_OP pHalGdmaOp; //Pointer to HAL_GDMA_OP
VOID (*pHalGdmaOpInit)(VOID*); //Pointer to HAL I2C initialize function
PIRQ_HANDLE pIrqTxGdmaHnd; //Pointer to IRQ handler for Tx GDMA
PIRQ_HANDLE pIrqRxGdmaHnd; //Pointer to IRQ handler for Rx GDMA
VOID (*pSalDMATxIrqFunc)(VOID*); //Used for SAL I2C interrupt function
VOID (*pSalDMARxIrqFunc)(VOID*); //Used for SAL I2C interrupt function
u32 RSVD; //Reserved
}SAL_I2C_MNGT_ADPT, *PSAL_I2C_MNGT_ADPT;
//======================================================
//SAL I2C management function prototype
PSAL_I2C_MNGT_ADPT RtkI2CGetMngtAdpt(IN u8 I2CIdx);
HAL_Status RtkI2CFreeMngtAdpt(IN PSAL_I2C_MNGT_ADPT pSalI2CMngtAdpt);
PSAL_I2C_HND RtkI2CGetSalHnd(IN u8 I2CIdx);
HAL_Status RtkI2CFreeSalHnd(IN PSAL_I2C_HND pSalI2CHND);
u32 RtkSalI2CSts(IN VOID *Data);
extern _LONG_CALL_ VOID I2CISRHandle(IN VOID *Data);
extern _LONG_CALL_ VOID I2CTXGDMAISRHandle(IN VOID *Data);
extern _LONG_CALL_ VOID I2CRXGDMAISRHandle(IN VOID *Data);
extern HAL_Status I2CIsTimeout (IN u32 StartCount, IN u32 TimeoutCnt);
extern HAL_TIMER_OP HalTimerOp;
//======================================================
// Function Prototypes
_LONG_CALL_ VOID HalI2COpInit(IN VOID *Data);
//================= I2C SAL MANAGEMENT END ==================
//================= Rtl8195a I2C V02 function prototype ============
_LONG_CALL_ VOID HalI2COpInitV02(IN VOID *Data);
_LONG_CALL_ VOID I2CISRHandleV02(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CSendV02(IN VOID *Data);
_LONG_CALL_ HAL_Status RtkI2CReceiveV02(IN VOID *Data);
_LONG_CALL_ VOID RtkSalI2COpInitV02(IN VOID *Data);
//================= Rtl8195a I2C V02 function prototype END==========
//======================================================
//SAL I2C patch function prototype
HAL_Status RtkI2CSend_Patch(IN VOID *Data);
HAL_Status RtkI2CReceive_Patch(IN VOID *Data);
VOID HalI2COpInit_Patch(IN VOID *Data);
VOID I2CISRHandle_Patch(IN VOID *Data);
#ifndef CONFIG_RELEASE_BUILD_LIBRARIES
#define RtkI2CSend RtkI2CSend_Patch
#define RtkI2CReceive RtkI2CReceive_Patch
#endif
HAL_Status RtkI2CSend_Patch(IN VOID *Data);
HAL_Status RtkI2CReceive_Patch(IN VOID *Data);
//================= I2C SAL END ===========================
#endif //#ifndef _HAL_I2C_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_I2S_H_
#define _HAL_I2S_H_
#include "rtl8195a_i2s.h"
/* User Define Flags */
#define I2S_MAX_ID 1 // valid I2S index 0 ~ I2S_MAX_ID
/**********************************************************************/
/* I2S HAL initial data structure */
typedef struct _HAL_I2S_INIT_DAT_ {
u8 I2SIdx; /*I2S index used*/
u8 I2SEn; /*I2S module enable tx/rx/tx+rx*/
u8 I2SMaster; /*I2S Master or Slave mode*/
u8 I2SWordLen; /*I2S Word length 16 or 24bits*/
u8 I2SChNum; /*I2S Channel number mono or stereo*/
u8 I2SPageNum; /*I2S Page Number 2~4*/
u16 I2SPageSize; /*I2S page Size 1~4096 word*/
u8 *I2STxData; /*I2S Tx data pointer*/
u8 *I2SRxData; /*I2S Rx data pointer*/
u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/
u32 I2STxIntrClr; /*I2S Tx Interrupt register to clear */
u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/
u32 I2SRxIntrClr; /*I2S Rx Interrupt register to clear*/
u16 I2STxIdx; /*I2S TX page index */
u16 I2SRxIdx; /*I2S RX page index */
u16 I2SHWTxIdx; /*I2S HW TX page index */
u16 I2SHWRxIdx; /*I2S HW RX page index */
u16 I2SRate; /*I2S sample rate*/
u8 I2STRxAct; /*I2S tx rx act*/
}HAL_I2S_INIT_DAT, *PHAL_I2S_INIT_DAT;
/**********************************************************************/
/* I2S Data Structures */
/* I2S Module Selection */
typedef enum _I2S_MODULE_SEL_ {
I2S0_SEL = 0x0,
I2S1_SEL = 0x1,
}I2S_MODULE_SEL,*PI2S_MODULE_SEL;
/*
typedef struct _HAL_I2S_ADAPTER_ {
u32 Enable:1;
I2S_CTL_REG I2sCtl;
I2S_SETTING_REG I2sSetting;
u32 abc;
u8 I2sIndex;
}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
*/
/* I2S HAL Operations */
typedef struct _HAL_I2S_OP_ {
RTK_STATUS (*HalI2SInit) (VOID *Data);
RTK_STATUS (*HalI2SDeInit) (VOID *Data);
RTK_STATUS (*HalI2STx) (VOID *Data, u8 *pBuff);
RTK_STATUS (*HalI2SRx) (VOID *Data, u8 *pBuff);
RTK_STATUS (*HalI2SEnable) (VOID *Data);
RTK_STATUS (*HalI2SIntrCtrl) (VOID *Data);
u32 (*HalI2SReadReg) (VOID *Data, u8 I2SReg);
RTK_STATUS (*HalI2SSetRate) (VOID *Data);
RTK_STATUS (*HalI2SSetWordLen) (VOID *Data);
RTK_STATUS (*HalI2SSetChNum) (VOID *Data);
RTK_STATUS (*HalI2SSetPageNum) (VOID *Data);
RTK_STATUS (*HalI2SSetPageSize) (VOID *Data);
RTK_STATUS (*HalI2SClrIntr) (VOID *Data);
RTK_STATUS (*HalI2SClrAllIntr) (VOID *Data);
RTK_STATUS (*HalI2SDMACtrl) (VOID *Data);
/*
VOID (*HalI2sOnOff)(VOID *Data);
BOOL (*HalI2sInit)(VOID *Data);
BOOL (*HalI2sSetting)(VOID *Data);
BOOL (*HalI2sEn)(VOID *Data);
BOOL (*HalI2sIsrEnAndDis) (VOID *Data);
BOOL (*HalI2sDumpReg)(VOID *Data);
BOOL (*HalI2s)(VOID *Data);
*/
}HAL_I2S_OP, *PHAL_I2S_OP;
/**********************************************************************/
/* I2S Pinmux Selection */
#if 0
typedef enum _I2S0_PINMUX_ {
I2S0_TO_S0 = 0x0,
I2S0_TO_S1 = 0x1,
I2S0_TO_S2 = 0x2,
}I2S0_PINMUX, *PI2S0_PINMUX;
typedef enum _I2S1_PINMUX_ {
I2S1_TO_S0 = 0x0,
I2S1_TO_S1 = 0x1,
}I2S1_PINMUX, *PI2S1_PINMUX;
#endif
typedef enum _I2S_PINMUX_ {
I2S_S0 = 0,
I2S_S1 = 1,
I2S_S2 = 2,
I2S_S3 = 3
}I2S_PINMUX, *PI2S_PINMUX;
/* I2S Module Status */
typedef enum _I2S_MODULE_STATUS_ {
I2S_DISABLE = 0x0,
I2S_ENABLE = 0x1,
}I2S_MODULE_STATUS, *PI2S_MODULE_STATUS;
/* I2S Device Status */
typedef enum _I2S_Device_STATUS_ {
I2S_STS_UNINITIAL = 0x00,
I2S_STS_INITIALIZED = 0x01,
I2S_STS_IDLE = 0x02,
I2S_STS_TX_READY = 0x03,
I2S_STS_TX_ING = 0x04,
I2S_STS_RX_READY = 0x05,
I2S_STS_RX_ING = 0x06,
I2S_STS_TRX_READY = 0x07,
I2S_STS_TRX_ING = 0x08,
I2S_STS_ERROR = 0x09,
}I2S_Device_STATUS, *PI2S_Device_STATUS;
/* I2S Feature Status */
typedef enum _I2S_FEATURE_STATUS_{
I2S_FEATURE_DISABLED = 0,
I2S_FEATURE_ENABLED = 1,
}I2S_FEATURE_STATUS,*PI2S_FEATURE_STATUS;
/* I2S Device Mode */
typedef enum _I2S_DEV_MODE_ {
I2S_MASTER_MODE = 0x0,
I2S_SLAVE_MODE = 0x1
}I2S_DEV_MODE, *PI2S_DEV_MODE;
/* I2S Word Length */
typedef enum _I2S_WORD_LEN_ {
I2S_WL_16 = 0x0,
I2S_WL_24 = 0x1,
}I2S_WORD_LEN, *PI2S_WORD_LEN;
/* I2S Bus Transmit/Receive */
typedef enum _I2S_DIRECTION_ {
I2S_ONLY_RX = 0x0,
I2S_ONLY_TX = 0x1,
I2S_TXRX = 0x2
}I2S_DIRECTION, *PI2S_DIRECTION;
/* I2S Channel number */
typedef enum _I2S_CH_NUM_ {
I2S_CH_STEREO = 0x0,
I2S_CH_RSVD = 0x1,
I2S_CH_MONO = 0x2
}I2S_CH_NUM, *PI2S_CH_NUM;
/* I2S Page number */
typedef enum _I2S_PAGE_NUM_ {
I2S_1PAGE = 0x0,
I2S_2PAGE = 0x1,
I2S_3PAGE = 0x2,
I2S_4PAGE = 0x3
}I2S_PAGE_NUM, *PI2S_PAGE_NUM;
/* I2S Sample rate*/
typedef enum _I2S_SAMPLE_RATE_ {
I2S_SR_8KHZ = 0x00, // /12
I2S_SR_16KHZ = 0x01, // /6
I2S_SR_24KHZ = 0x02, // /4
I2S_SR_32KHZ = 0x03, // /3
I2S_SR_48KHZ = 0x05, // /2
I2S_SR_96KHZ = 0x06, // x1, base 96kHz
I2S_SR_7p35KHZ = 0x10,
I2S_SR_11p02KHZ = 0x11,
I2S_SR_22p05KHZ = 0x12,
I2S_SR_29p4KHZ = 0x13,
I2S_SR_44p1KHZ = 0x15,
I2S_SR_88p2KHZ = 0x16 // x1, base 88200Hz
}I2S_SAMPLE_RATE, *PI2S_SAMPLE_RATE;
/* I2S TX interrupt mask/status */
typedef enum _I2S_TX_IMR_ {
I2S_TX_INT_PAGE0_OK = (1<<0),
I2S_TX_INT_PAGE1_OK = (1<<1),
I2S_TX_INT_PAGE2_OK = (1<<2),
I2S_TX_INT_PAGE3_OK = (1<<3),
I2S_TX_INT_FULL = (1<<4),
I2S_TX_INT_EMPTY = (1<<5)
} I2S_TX_IMR, *PI2S_TX_IMR;
/* I2S RX interrupt mask/status */
typedef enum _I2S_RX_IMR_ {
I2S_RX_INT_PAGE0_OK = (1<<0),
I2S_RX_INT_PAGE1_OK = (1<<1),
I2S_RX_INT_PAGE2_OK = (1<<2),
I2S_RX_INT_PAGE3_OK = (1<<3),
I2S_RX_INT_EMPTY = (1<<4),
I2S_RX_INT_FULL = (1<<5)
} I2S_RX_IMR, *PI2S_RX_IMR;
/* I2S User Callbacks */
typedef struct _SAL_I2S_USER_CB_{
VOID (*TXCB) (VOID *Data);
VOID (*TXCCB) (VOID *Data);
VOID (*RXCB) (VOID *Data);
VOID (*RXCCB) (VOID *Data);
VOID (*RDREQCB) (VOID *Data);
VOID (*ERRCB) (VOID *Data);
VOID (*GENCALLCB) (VOID *Data);
}SAL_I2S_USER_CB,*PSAL_I2S_USER_CB;
typedef struct _I2S_USER_CB_{
VOID (*TxCCB)(uint32_t id, char *pbuf);
u32 TxCBId;
VOID (*RxCCB)(uint32_t id, char *pbuf);
u32 RxCBId;
}I2S_USER_CB,*PI2S_USER_CB;
/* Software API Level I2S Handler */
typedef struct _HAL_I2S_ADAPTER_{
u8 DevNum; //I2S device number
u8 PinMux; //I2S pin mux seletion
u8 RSVD0; //Reserved
volatile u8 DevSts; //I2S device status
u32 RSVD2; //Reserved
u32 I2SExd; //I2S extended options:
//bit 0: I2C RESTART supported,
// 0 for NOT supported,
// 1 for supported
//bit 1: I2C General Call supported
// 0 for NOT supported,
// 1 for supported
//bit 2: I2C START Byte supported
// 0 for NOT supported,
// 1 for supported
//bit 3: I2C Slave-No-Ack
// supported
// 0 for NOT supported,
// 1 for supported
//bit 4: I2C bus loading,
// 0 for 100pf,
// 1 for 400pf
//bit 5: I2C slave ack to General
// Call
//bit 6: I2C User register address
//bit 7: I2C 2-Byte User register
// address
//bit 31~bit 8: Reserved
u32 ErrType; //
u32 TimeOut; //I2S IO Timeout count
PHAL_I2S_INIT_DAT pInitDat; //Pointer to I2S initial data struct
I2S_USER_CB UserCB; //Pointer to I2S User Callback
IRQ_HANDLE IrqHandle; // Irq Handler
u32* TxPageList[4]; // The Tx DAM buffer: pointer of each page
u32* RxPageList[4]; // The Tx DAM buffer: pointer of each page
}HAL_I2S_ADAPTER, *PHAL_I2S_ADAPTER;
typedef struct _HAL_I2S_DEF_SETTING_{
u8 I2SMaster; // Master or Slave mode
u8 DevSts; //I2S device status
u8 I2SChNum; //I2S Channel number mono or stereo
u8 I2SPageNum; //I2S Page number 2~4
u8 I2STRxAct; //I2S tx rx act, tx only or rx only or tx+rx
u8 I2SWordLen; //I2S Word length 16bit or 24bit
u16 I2SPageSize; //I2S Page size 1~4096 word
u16 I2SRate; //I2S sample rate 8k ~ 96khz
u32 I2STxIntrMSK; /*I2S Tx Interrupt Mask*/
u32 I2SRxIntrMSK; /*I2S Rx Interrupt Mask*/
}HAL_I2S_DEF_SETTING, *PHAL_I2S_DEF_SETTING;
/**********************************************************************/
HAL_Status
RtkI2SLoadDefault(IN VOID *Adapter, IN VOID *Setting);
HAL_Status
RtkI2SInit(IN VOID *Data);
HAL_Status
RtkI2SDeInit(IN VOID *Data);
HAL_Status
RtkI2SEnable(IN VOID *Data);
HAL_Status
RtkI2SDisable(IN VOID *Data);
extern HAL_Status
HalI2SInit( IN VOID *Data);
extern VOID
HalI2SDeInit( IN VOID *Data);
extern HAL_Status
HalI2SDisable( IN VOID *Data);
extern HAL_Status
HalI2SEnable( IN VOID *Data);
/**********************************************************************/
VOID I2S0ISRHandle(VOID *Data);
VOID I2S1ISRHandle(VOID *Data);
/**********************************************************************/
VOID HalI2SOpInit(
IN VOID *Data
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_IRQN_H_
#define _HAL_IRQN_H_
#define PERIPHERAL_IRQ_BASE_NUM 64
typedef enum _IRQn_Type_ {
#if 0
/****** Cortex-M3 Processor Exceptions Numbers ********/
NON_MASKABLE_INT_IRQ = -14,
HARD_FAULT_IRQ = -13,
MEM_MANAGE_FAULT_IRQ = -12,
BUS_FAULT_IRQ = -11,
USAGE_FAULT_IRQ = -10,
SVCALL_IRQ = -5,
DEBUG_MONITOR_IRQ = -4,
PENDSVC_IRQ = -2,
SYSTICK_IRQ = -1,
#else
/****** Cortex-M3 Processor Exceptions Numbers ********/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
#endif
/****** RTL8195A Specific Interrupt Numbers ************/
SYSTEM_ON_IRQ = 0,
WDG_IRQ = 1,
TIMER0_IRQ = 2,
TIMER1_IRQ = 3,
I2C3_IRQ = 4,
TIMER2_7_IRQ = 5,
SPI0_IRQ = 6,
GPIO_IRQ = 7,
UART0_IRQ = 8,
SPI_FLASH_IRQ = 9,
USB_OTG_IRQ = 10,
SDIO_HOST_IRQ = 11,
SDIO_DEVICE_IRQ = 12,
I2S0_PCM0_IRQ = 13,
I2S1_PCM1_IRQ = 14,
WL_DMA_IRQ = 15,
WL_PROTOCOL_IRQ = 16,
CRYPTO_IRQ = 17,
GMAC_IRQ = 18,
PERIPHERAL_IRQ = 19,
GDMA0_CHANNEL0_IRQ = 20,
GDMA0_CHANNEL1_IRQ = 21,
GDMA0_CHANNEL2_IRQ = 22,
GDMA0_CHANNEL3_IRQ = 23,
GDMA0_CHANNEL4_IRQ = 24,
GDMA0_CHANNEL5_IRQ = 25,
GDMA1_CHANNEL0_IRQ = 26,
GDMA1_CHANNEL1_IRQ = 27,
GDMA1_CHANNEL2_IRQ = 28,
GDMA1_CHANNEL3_IRQ = 29,
GDMA1_CHANNEL4_IRQ = 30,
GDMA1_CHANNEL5_IRQ = 31,
/****** RTL8195A Peripheral Interrupt Numbers ************/
I2C0_IRQ = 64,// 0 + 64,
I2C1_IRQ = 65,// 1 + 64,
I2C2_IRQ = 66,// 2 + 64,
SPI1_IRQ = 72,// 8 + 64,
SPI2_IRQ = 73,// 9 + 64,
UART1_IRQ = 80,// 16 + 64,
UART2_IRQ = 81,// 17 + 64,
UART_LOG_IRQ = 88,// 24 + 64,
ADC_IRQ = 89,// 25 + 64,
DAC0_IRQ = 91,// 27 + 64,
DAC1_IRQ = 92,// 28 + 64,
//RXI300_IRQ = 93// 29 + 64
LP_EXTENSION_IRQ = 93,// 29+64
PTA_TRX_IRQ = 95,// 31+64
RXI300_IRQ = 96,// 0+32 + 64
NFC_IRQ = 97// 1+32+64
} IRQn_Type, *PIRQn_Type;
typedef VOID (*HAL_VECTOR_FUN) (VOID);
typedef enum _VECTOR_TABLE_TYPE_{
DEDECATED_VECTRO_TABLE,
PERIPHERAL_VECTOR_TABLE
}VECTOR_TABLE_TYPE, *PVECTOR_TABLE_TYPE;
typedef u32 (*IRQ_FUN)(VOID *Data);
typedef struct _IRQ_HANDLE_ {
IRQ_FUN IrqFun;
IRQn_Type IrqNum;
u32 Data;
u32 Priority;
}IRQ_HANDLE, *PIRQ_HANDLE;
#endif //_HAL_IRQN_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_MII_H_
#define _HAL_MII_H_
#include "rtl8195a_mii.h"
/**
* LOG Configurations
*/
#define NOLOG
#define LOG_TAG "NoTag"
#define LOG_INFO_HEADER "I"
#define LOG_DEBUG_HEADER "D"
#define LOG_ERROR_HEADER "E"
#define LOG_TEST_HEADER "T"
#define IDENT_TWO_SPACE " "
#define IDENT_FOUR_SPACE " "
#define LOG_INFO(...) do {\
DiagPrintf("\r"LOG_INFO_HEADER"/"LOG_TAG": " __VA_ARGS__);\
}while(0)
#define LOG_DEBUG(...) do {\
DiagPrintf("\r"LOG_DEBUG_HEADER"/"LOG_TAG": " __VA_ARGS__);\
}while(0)
#define LOG_ERROR(...) do {\
DiagPrintf("\r"LOG_ERROR_HEADER"/"LOG_TAG": " __VA_ARGS__);\
}while(0)
#ifdef NOLOG
#define LOGI
#define LOGD
#define LOGE
#define LOGI2
#define LOGD2
#define LOGE2
#define LOGI4
#define LOGD4
#define LOGE4
#else
#define LOGI LOG_INFO
#define LOGD LOG_DEBUG
#define LOGE LOG_ERROR
#define LOGI2(...) LOG_INFO(IDENT_TWO_SPACE __VA_ARGS__)
#define LOGD2(...) LOG_DEBUG(IDENT_TWO_SPACE __VA_ARGS__)
#define LOGE2(...) LOG_ERROR(IDENT_TWO_SPACE __VA_ARGS__)
#define LOGI4(...) LOG_INFO(IDENT_FOUR_SPACE __VA_ARGS__)
#define LOGD4(...) LOG_DEBUG(IDENT_FOUR_SPACE __VA_ARGS__)
#define LOGE4(...) LOG_ERROR(IDENT_FOUR_SPACE __VA_ARGS__)
#endif
#define ANSI_COLOR_GREEN "\x1b[32m"
#define ANSI_COLOR_CYAN "\x1b[36m"
#define ANSI_COLOR_YELLOW "\x1b[33m"
#define ANSI_COLOR_MAGENTA "\x1b[35m"
#define ANSI_COLOR_RED "\x1b[31m"
#define ANSI_COLOR_BLUE "\x1b[34m"
#define ANSI_COLOR_RESET "\x1b[0m"
#define DBG_ENTRANCE LOGI(ANSI_COLOR_GREEN "=> %s() <%s>\n" ANSI_COLOR_RESET, \
__func__, __FILE__)
// GMAC MII Configurations
#ifdef LOG_TAG
#undef LOG_TAG
#define LOG_TAG "MII"
#endif
typedef struct _HAL_MII_ADAPTER_ {
u32 InterruptMask;
PPHY_MODE_INFO pPhyModeInfo;
}HAL_MII_ADAPTER, *PHAL_MII_ADAPTER;
typedef struct _HAL_MII_OP_ {
BOOL (*HalMiiGmacInit)(VOID *Data);
BOOL (*HalMiiInit)(VOID *Data);
BOOL (*HalMiiGmacReset)(VOID *Data);
BOOL (*HalMiiGmacEnablePhyMode)(VOID *Data);
u32 (*HalMiiGmacXmit)(VOID *Data);
VOID (*HalMiiGmacCleanTxRing)(VOID *Data);
VOID (*HalMiiGmacFillTxInfo)(VOID *Data);
VOID (*HalMiiGmacFillRxInfo)(VOID *Data);
VOID (*HalMiiGmacTx)(VOID *Data);
VOID (*HalMiiGmacRx)(VOID *Data);
VOID (*HalMiiGmacSetDefaultEthIoCmd)(VOID *Data);
VOID (*HalMiiGmacInitIrq)(VOID *Data);
u32 (*HalMiiGmacGetInterruptStatus)(VOID);
VOID (*HalMiiGmacClearInterruptStatus)(u32 IsrStatus);
}HAL_MII_OP, *PHAL_MII_OP;
VOID HalMiiOpInit(IN VOID *Data);
typedef struct _MII_ADAPTER_ {
PHAL_MII_OP pHalMiiOp;
PHAL_MII_ADAPTER pHalMiiAdapter;
PTX_INFO pTx_Info;
PRX_INFO pRx_Info;
VOID* TxBuffer;
VOID* RxBuffer;
}MII_ADAPTER, *PMII_ADAPTER;
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _MISC_H_
#define _MISC_H_
#include <basic_types.h>
#ifdef CONFIG_TIMER_MODULE
extern _LONG_CALL_ u32 HalDelayUs(u32 us);
#endif
extern _LONG_CALL_ u32 HalGetCpuClk(VOID);
extern _LONG_CALL_ u8 HalGetRomInfo(VOID);
extern _LONG_CALL_ void *_memset( void *s, int c, SIZE_T n );
extern _LONG_CALL_ void *_memcpy( void *s1, const void *s2, SIZE_T n );
extern _LONG_CALL_ int _memcmp( const void *av, const void *bv, SIZE_T len );
extern _LONG_CALL_ SIZE_T _strlen(const char *s);
extern _LONG_CALL_ int _strcmp(const char *cs, const char *ct);
#endif //_MISC_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_NFC_H_
#define _HAL_NFC_H_
#include "rtl8195a_nfc.h"
VOID HalNFCOpInit(
IN VOID *Data
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PCM_H_
#define _HAL_PCM_H_
#include "rtl8195a_pcm.h"
/*
typedef struct _GDMA_CH_LLI_ELE_ {
u32 Sarx;
u32 Darx;
u32 Llpx;
u32 CtlxLow;
u32 CtlxUp;
u32 Temp;
}GDMA_CH_LLI_ELE, *PGDMA_CH_LLI_ELE;
#if 1
#if 0
typedef struct _GDMA_CH_LLI_ {
PGDMA_CH_LLI_ELE pLliEle;
PGDMA_CH_LLI pNextLli;
}GDMA_CH_LLI, *PGDMA_CH_LLI;
typedef struct _BLOCK_SIZE_LIST_ {
u32 BlockSize;
PBLOCK_SIZE_LIST pNextBlockSiz;
}BLOCK_SIZE_LIST, *PBLOCK_SIZE_LIST;
#else
struct GDMA_CH_LLI {
PGDMA_CH_LLI_ELE pLliEle;
struct GDMA_CH_LLI *pNextLli;
};
struct BLOCK_SIZE_LIST {
u32 BlockSize;
struct BLOCK_SIZE_LIST *pNextBlockSiz;
};
#endif
#endif
typedef struct _HAL_GDMA_ADAPTER_ {
u32 ChSar;
u32 ChDar;
GDMA_CHANNEL_NUM ChEn;
GDMA_CTL_REG GdmaCtl;
GDMA_CFG_REG GdmaCfg;
u32 PacketLen;
u32 BlockLen;
u32 MuliBlockCunt;
u32 MaxMuliBlock;
struct GDMA_CH_LLI *pLlix;
struct BLOCK_SIZE_LIST *pBlockSizeList;
PGDMA_CH_LLI_ELE pLli;
u32 NextPlli;
u8 TestItem;
u8 ChNum;
u8 GdmaIndex;
u8 IsrCtrl:1;
u8 GdmaOnOff:1;
u8 Llpctrl:1;
u8 Lli0:1;
u8 Rsvd4to7:4;
u8 GdmaIsrType;
}HAL_GDMA_ADAPTER, *PHAL_GDMA_ADAPTER;
*/
typedef struct _HAL_PCM_ADAPTER_ {
u32 Enable:1;
PCM_CTL_REG PcmCtl;
PCM_CHCNR03_REG PcmChCNR03;
PCM_TSR03_REG PcmTSR03;
PCM_BSIZE03_REG PcmBSize03;
u32 abc;
u8 PcmIndex;
u8 PcmCh;
}HAL_PCM_ADAPTER, *PHAL_PCM_ADAPTER;
typedef struct _HAL_PCM_OP_ {
VOID (*HalPcmOnOff)(VOID *Data);
BOOL (*HalPcmInit)(VOID *Data);
BOOL (*HalPcmSetting)(VOID *Data);
BOOL (*HalPcmEn)(VOID *Data);
BOOL (*HalPcmIsrEnAndDis) (VOID *Data);
BOOL (*HalPcmDumpReg)(VOID *Data);
BOOL (*HalPcm)(VOID *Data);
}HAL_PCM_OP, *PHAL_PCM_OP;
VOID HalPcmOpInit(
IN VOID *Data
);
#endif

451
lib/fwlib/hal_peri_on.h Normal file
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@ -0,0 +1,451 @@
/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PERI_ON_H_
#define _HAL_PERI_ON_H_
#define MASK_ALLON 0xFFFFFFFF
#define HAL_PERI_ON_READ32(addr) HAL_READ32(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE32(addr, value) HAL_WRITE32(PERI_ON_BASE, addr, value)
#define HAL_PERI_ON_READ16(addr) HAL_READ16(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE16(addr, value) HAL_WRITE16(PERI_ON_BASE, addr, value)
#define HAL_PERI_ON_READ8(addr) HAL_READ8(PERI_ON_BASE, addr)
#define HAL_PERI_ON_WRITE8(addr, value) HAL_WRITE8(PERI_ON_BASE, addr, value)
#define HAL_PERL_ON_FUNC_CTRL(addr,value,ctrl) \
HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~value))|((MASK_ALLON - ctrl + 1) & value)))
#define HAL_PERL_ON_PIN_SEL(addr,mask,value) \
HAL_PERI_ON_WRITE32(addr, ((HAL_PERI_ON_READ32(addr) & (~mask)) | value))
//40 REG_SYS_REGU_CTRL0
#define LDO25M_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_REGU_CTRL0, BIT_SYS_REGU_LDO25M_EN, ctrl)
//A0 SYS_DEBUG_CTRL
#define DEBUG_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_DEBUG_CTRL, BIT_SYS_DBG_PIN_EN, ctrl)
//A4 SYS_PINMUX_CTRL
#define SIC_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_SIC_PIN_EN, ctrl)
#define EEPROM_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SYS_PINMUX_CTRL, BIT_EEPROM_PIN_EN, ctrl)
//210 SOV_FUNC_EN
#define LXBUS_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LXBUS_EN, ctrl)
#define FLASH_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI_FLASH_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_FLASH_EN, ctrl);}
#define MEM_CTRL_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDR_SDRAM_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_MEM_CTRL_EN, ctrl);}
#define LOC_UART_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(LOG_UART_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_LOG_UART_EN, ctrl);}
#define GDMA0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GDMA0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA0_EN, ctrl);}
#define GDMA1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GDMA1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GDMA1_EN, ctrl);}
#define GTIMER_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(TIMER_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_GTIMER_EN, ctrl);}
#define SECURITY_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(CRYPTO_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_FUNC_EN, BIT_SOC_SECURITY_ENGINE_EN, ctrl);}
//214 SOC_HCI_COM_FUNC_EN
#define SDIOD_ON_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_EN, ctrl);}
#define SDIOD_OFF_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_DEVICE_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_OFF_EN, ctrl);}
#define SDIOH_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SDIO_HOST_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOH_EN, ctrl);}
#define SDIO_ON_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SDIOD_ON_RST_MUX, ctrl)
#define OTG_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(USB_OTG_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_EN, ctrl);}
#define OTG_RST_MASK(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_OTG_RST_MUX, ctrl)
#define MII_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(MII_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_MII_EN, ctrl);}
#define MII_MUX_SEL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_SM_SEL, ctrl)
#define WL_MACON_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(WIFI_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_HCI_COM_FUNC_EN, BIT_SOC_HCI_WL_MACON_EN, ctrl);}
//218 SOC_PERI_FUNC0_EN
#define UART0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART0_EN, ctrl);}
#define UART1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART1_EN, ctrl);}
#define UART2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_UART2_EN, ctrl);}
#define SPI0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI0_EN, ctrl);}
#define SPI1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI1_EN, ctrl);}
#define SPI2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(SPI2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_SPI2_EN, ctrl);}
#define I2C0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C0_EN, ctrl);}
#define I2C1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C1_EN, ctrl);}
#define I2C2_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C2_EN, ctrl);}
#define I2C3_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2C3_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2C3_EN, ctrl);}
#define I2S0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2S0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S0_EN, ctrl);}
#define I2S1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(I2S1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_I2S1_EN, ctrl);}
#define PCM0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(PCM0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM0_EN, ctrl);}
#define PCM1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(PCM1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC0_EN, BIT_PERI_PCM1_EN, ctrl);}
//21C SOC_PERI_FUNC1_EN
#define ADC0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(ADC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_ADC0_EN, ctrl);}
#define DAC0_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(DAC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC0_EN, ctrl);}
#define DAC1_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(DAC_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_DAC1_EN, ctrl);}
#define GPIO_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(GPIO_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_FUNC1_EN, BIT_PERI_GPIO_EN, ctrl);}
//220 SOC_PERI_BD_FUNC0_EN
#define UART0_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART0_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART0_BD_EN, ctrl);}
#define UART1_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART1_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART1_BD_EN, ctrl);}
#define UART2_BD_FCTRL(ctrl) { \
if (!ctrl) { \
HAL_READ32(UART2_REG_BASE,0);\
}\
HAL_PERL_ON_FUNC_CTRL(REG_SOC_PERI_BD_FUNC0_EN, BIT_PERI_UART2_BD_EN, ctrl);}
//230 PESOC_CLK_CTRL
#define ACTCK_CPU_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_CKE_PLFM, ctrl)
#define ACTCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TRACE_EN, ctrl)
#define SLPCK_TRACE_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TRACE_EN, ctrl)
#define ACTCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_VENDOR_REG_EN, ctrl)
#define SLPCK_VENDOR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_VENDOR_REG_EN, ctrl)
#define ACTCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_FLASH_EN, ctrl)
#define SLPCK_FLASH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_FLASH_EN, ctrl)
#define ACTCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_SDR_EN, ctrl)
#define SLPCK_SDR_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_SDR_EN, ctrl)
#define ACTCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_LOG_UART_EN, ctrl)
#define SLPCK_LOG_UART_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_LOG_UART_EN, ctrl)
#define ACTCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_TIMER_EN, ctrl)
#define SLPCK_TIMER_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_TIMER_EN, ctrl)
#define ACTCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA0_EN, ctrl)
#define SLPCK_GDMA0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA0_EN, ctrl)
#define ACTCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GDMA1_EN, ctrl)
#define SLPCK_GDMA1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GDMA1_EN, ctrl)
#define ACTCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_GPIO_EN, ctrl)
#define SLPCK_GPIO_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_GPIO_EN, ctrl)
#define ACTCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_ACTCK_BTCMD_EN, ctrl)
#define SLPCK_BTCMD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_CLK_CTRL, BIT_SOC_SLPCK_BTCMD_EN, ctrl)
//234 PESOC_PERI_CLK_CTRL0
#define ACTCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART0_EN, ctrl)
#define SLPCK_UART0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART0_EN, ctrl)
#define ACTCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART1_EN, ctrl)
#define SLPCK_UART1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART1_EN, ctrl)
#define ACTCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_UART2_EN, ctrl)
#define SLPCK_UART2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_UART2_EN, ctrl)
#define ACTCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI0_EN, ctrl)
#define SLPCK_SPI0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI0_EN, ctrl)
#define ACTCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI1_EN, ctrl)
#define SLPCK_SPI1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI1_EN, ctrl)
#define ACTCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_ACTCK_SPI2_EN, ctrl)
#define SLPCK_SPI2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL0, BIT_SOC_SLPCK_SPI2_EN, ctrl)
//238 PESOC_PERI_CLK_CTRL1
#define ACTCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C0_EN, ctrl)
#define SLPCK_I2C0_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C0_EN, ctrl)
#define ACTCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C1_EN, ctrl)
#define SLPCK_I2C1_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C1_EN, ctrl)
#define ACTCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C2_EN, ctrl)
#define SLPCK_I2C2_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C2_EN, ctrl)
#define ACTCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2C3_EN, ctrl)
#define SLPCK_I2C3_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2C3_EN, ctrl)
#define ACTCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_I2S_EN, ctrl)
#define SLPCK_I2S_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_I2S_EN, ctrl)
#define ACTCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_PCM_EN, ctrl)
#define SLPCK_PCM_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_PCM_EN, ctrl)
#define ACTCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_ADC_EN, ctrl)
#define SLPCK_ADC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_ADC_EN, ctrl)
#define ACTCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_ACTCK_DAC_EN, ctrl)
#define SLPCK_DAC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CLK_CTRL1, BIT_SOC_SLPCK_DAC_EN, ctrl)
//240 PESOC_HCI_CLK_CTRL0
#define ACTCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_DEV_EN, ctrl)
#define SLPCK_SDIOD_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_DEV_EN, ctrl)
#define ACTCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_SDIO_HST_EN, ctrl)
#define SLPCK_SDIOH_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_SDIO_HST_EN, ctrl)
#define ACTCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_OTG_EN, ctrl)
#define SLPCK_OTG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_OTG_EN, ctrl)
#define ACTCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_ACTCK_MII_MPHY_EN, ctrl)
#define SLPCK_MII_MPHY_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_HCI_CLK_CTRL0, BIT_SOC_SLPCK_MII_MPHY_EN, ctrl)
//244 PESOC_COM_CLK_CTRL1
#define ACTCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_WL_EN, ctrl)
#define SLPCK_WL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_WL_EN, ctrl)
#define ACTCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_SECURITY_ENG_EN, ctrl)
#define SLPCK_SEC_ENG_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_SECURITY_ENG_EN, ctrl)
#define ACTCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_ACTCK_NFC_EN, ctrl)
#define SLPCK_NFC_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_SLPCK_NFC_EN, ctrl)
#define NFC_CAL_CCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_COM_CLK_CTRL1, BIT_SOC_NFC_CAL_EN, ctrl)
//250 REG_PERI_CLK_SEL
#define TRACE_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_TRACE_CK_SEL << BIT_SHIFT_PESOC_TRACE_CK_SEL), BIT_PESOC_TRACE_CK_SEL(num))
#define FLASH_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_FLASH_CK_SEL << BIT_SHIFT_PESOC_FLASH_CK_SEL), BIT_PESOC_FLASH_CK_SEL(num))
#define SDR_CLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_SDR_CK_SEL << BIT_SHIFT_PESOC_SDR_CK_SEL), BIT_PESOC_SDR_CK_SEL(num))
#define I2C_SCLK_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_CLK_SEL, (BIT_MASK_PESOC_PERI_SCLK_SEL << BIT_SHIFT_PESOC_PERI_SCLK_SEL), BIT_PESOC_PERI_SCLK_SEL(num))
//270 REG_OSC32K_CTRL
#define OSC32K_CKGEN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_OSC32K_CTRL, BIT_32K_POW_CKGEN_EN, ctrl)
//280 REG_UART_MUX_CTRL
#define UART0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART0_PIN_EN, ctrl)
#define UART0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART0_PIN_SEL << BIT_SHIFT_UART0_PIN_SEL), BIT_UART0_PIN_SEL(num))
#define UART1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART1_PIN_EN, ctrl)
#define UART1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART1_PIN_SEL << BIT_SHIFT_UART1_PIN_SEL), BIT_UART1_PIN_SEL(num))
#define UART2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_UART_MUX_CTRL, BIT_UART2_PIN_EN, ctrl)
#define UART2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_UART_MUX_CTRL, (BIT_MASK_UART2_PIN_SEL << BIT_SHIFT_UART2_PIN_SEL), BIT_UART2_PIN_SEL(num))
//284 REG_SPI_MUX_CTRL
#define SPI0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_PIN_EN, ctrl)
#define SPI0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI0_PIN_SEL << BIT_SHIFT_SPI0_PIN_SEL), BIT_SPI0_PIN_SEL(num))
#define SPI1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI1_PIN_EN, ctrl)
#define SPI1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI1_PIN_SEL << BIT_SHIFT_SPI1_PIN_SEL), BIT_SPI1_PIN_SEL(num))
#define SPI2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI2_PIN_EN, ctrl)
#define SPI2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_SPI_MUX_CTRL, (BIT_MASK_SPI2_PIN_SEL << BIT_SHIFT_SPI2_PIN_SEL), BIT_SPI2_PIN_SEL(num))
#define SPI0_MULTI_CS_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_SPI_MUX_CTRL, BIT_SPI0_MULTI_CS_EN, ctrl)
//288 REG_I2C_MUX_CTRL
#define I2C0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C0_PIN_EN, ctrl)
#define I2C0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C0_PIN_SEL << BIT_SHIFT_I2C0_PIN_SEL), BIT_I2C0_PIN_SEL(num))
#define I2C1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C1_PIN_EN, ctrl)
#define I2C1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C1_PIN_SEL << BIT_SHIFT_I2C1_PIN_SEL), BIT_I2C1_PIN_SEL(num))
#define I2C2_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C2_PIN_EN, ctrl)
#define I2C2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C2_PIN_SEL << BIT_SHIFT_I2C2_PIN_SEL), BIT_I2C2_PIN_SEL(num))
#define I2C3_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2C_MUX_CTRL, BIT_I2C3_PIN_EN, ctrl)
#define I2C3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2C_MUX_CTRL, (BIT_MASK_I2C3_PIN_SEL << BIT_SHIFT_I2C3_PIN_SEL), BIT_I2C3_PIN_SEL(num))
//28C REG_I2S_MUX_CTRL
#define I2S0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_PIN_EN, ctrl)
#define I2S0_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S0_MCK_EN, ctrl)
#define I2S0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S0_PIN_SEL << BIT_SHIFT_I2S0_PIN_SEL), BIT_I2S0_PIN_SEL(num))
#define I2S1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_PIN_EN, ctrl)
#define I2S1_MCK_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_I2S1_MCK_EN, ctrl)
#define I2S1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_I2S1_PIN_SEL << BIT_SHIFT_I2S1_PIN_SEL), BIT_I2S1_PIN_SEL(num))
#define PCM0_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM0_PIN_EN, ctrl)
#define PCM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM0_PIN_SEL << BIT_SHIFT_PCM0_PIN_SEL), BIT_PCM0_PIN_SEL(num))
#define PCM1_PIN_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_I2S_MUX_CTRL, BIT_PCM1_PIN_EN, ctrl)
#define PCM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_I2S_MUX_CTRL, (BIT_MASK_PCM1_PIN_SEL << BIT_SHIFT_PCM1_PIN_SEL), BIT_PCM1_PIN_SEL(num))
//2A0 HCI_PINMUX_CTRL
#define SDIOD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOD_PIN_EN, ctrl)
#define SDIOH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_SDIOH_PIN_EN, ctrl)
#define MII_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_HCI_PINMUX_CTRL, BIT_HCI_MII_PIN_EN, ctrl)
//2A4 WL_PINMUX_CTRL
#define LED_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_LED_PIN_EN, ctrl)
#define LED_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_WL_PINMUX_CTRL, (BIT_MASK_WL_LED_PIN_SEL << BIT_SHIFT_WL_LED_PIN_SEL), BIT_WL_LED_PIN_SEL(num))
#define ANT0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT0_PIN_EN, ctrl)
#define ANT1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_ANT1_PIN_EN, ctrl)
#define BTCOEX_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCOEX_PIN_EN, ctrl)
#define BTCMD_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_WL_BTCMD_PIN_EN, ctrl)
#define NFC_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_WL_PINMUX_CTRL, BIT_NFC_PIN_EN, ctrl)
//2AC PWM_PINMUX_CTRL
#define PWM0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM0_PIN_EN, ctrl)
#define PWM0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM0_PIN_SEL << BIT_SHIFT_PWM0_PIN_SEL), BIT_PWM0_PIN_SEL(num))
#define PWM1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM1_PIN_EN, ctrl)
#define PWM1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM1_PIN_SEL << BIT_SHIFT_PWM1_PIN_SEL), BIT_PWM1_PIN_SEL(num))
#define PWM2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM2_PIN_EN, ctrl)
#define PWM2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM2_PIN_SEL << BIT_SHIFT_PWM2_PIN_SEL), BIT_PWM2_PIN_SEL(num))
#define PWM3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_PWM3_PIN_EN, ctrl)
#define PWM3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_PWM3_PIN_SEL << BIT_SHIFT_PWM3_PIN_SEL), BIT_PWM3_PIN_SEL(num))
#define ETE0_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE0_PIN_EN, ctrl)
#define ETE0_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE0_PIN_SEL << BIT_SHIFT_ETE0_PIN_SEL), BIT_ETE0_PIN_SEL(num))
#define ETE1_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE1_PIN_EN, ctrl)
#define ETE1_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE1_PIN_SEL << BIT_SHIFT_ETE1_PIN_SEL), BIT_ETE1_PIN_SEL(num))
#define ETE2_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE2_PIN_EN, ctrl)
#define ETE2_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE2_PIN_SEL << BIT_SHIFT_ETE2_PIN_SEL), BIT_ETE2_PIN_SEL(num))
#define ETE3_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PWM_PINMUX_CTRL, BIT_ETE3_PIN_EN, ctrl)
#define ETE3_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PWM_PINMUX_CTRL, (BIT_MASK_ETE3_PIN_SEL << BIT_SHIFT_ETE3_PIN_SEL), BIT_ETE3_PIN_SEL(num))
//2C0 CPU_PERIPHERAL_CTRL
#define SPI_FLASH_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SPI_FLSH_PIN_EN, ctrl)
#define SPI_FLASH_PIN_SEL(num) HAL_PERL_ON_PIN_SEL(REG_CPU_PERIPHERAL_CTRL, (BIT_MASK_SPI_FLSH_PIN_SEL << BIT_SHIFT_SPI_FLSH_PIN_SEL), BIT_SPI_FLSH_PIN_SEL(num))
#define SDR_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_SDR_PIN_EN, ctrl)
#define TRACE_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_TRACE_PIN_EN, ctrl)
#define LOG_UART_PIN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_PIN_EN, ctrl)
#define LOG_UART_IR_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_CPU_PERIPHERAL_CTRL, BIT_LOG_UART_IR_EN, ctrl)
//300 REG_PESOC_MEM_CTRL
#define SDR_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_SDR_DDL_CTRL << BIT_SHIFT_PESOC_SDR_DDL_CTRL), BIT_PESOC_SDR_DDL_CTRL(ctrl))
#define FLASH_DDL_FCTRL(ctrl) HAL_PERL_ON_PIN_SEL(REG_PESOC_MEM_CTRL, (BIT_MASK_PESOC_FLASH_DDL_CTRL << BIT_SHIFT_PESOC_FLASH_DDL_CTRL), BIT_PESOC_FLASH_DDL_CTRL(ctrl))
//304 REG_PESOC_SOC_CTRL
#define SRAM_MUX_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_SRAM_MUX_CFG << BIT_SHIFT_PESOC_SRAM_MUX_CFG), BIT_PESOC_SRAM_MUX_CFG(num))
#define LX_WL_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_WL_SWAP_SEL, ctrl)
#define LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_MST_SWAP_SEL, ctrl)
#define LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_LX_SLV_SWAP_SEL, ctrl)
#define MII_LX_WRAPPER_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_WRAPPER_EN, ctrl)
#define MII_LX_MST_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_MST_SWAP_SEL, ctrl)
#define MII_LX_SLV_SWAP_CTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_SOC_CTRL, BIT_PESOC_MII_LX_SLV_SWAP_SEL, ctrl)
#define GDMA_CFG(num) HAL_PERL_ON_PIN_SEL(REG_PESOC_SOC_CTRL, (BIT_MASK_PESOC_GDMA_CFG << BIT_SHIFT_PESOC_GDMA_CFG), BIT_PESOC_GDMA_CFG(num))
//308 PESOC_PERI_CTRL
#define SPI_RN_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PESOC_PERI_CTRL, BIT_SOC_FUNC_SPI_RN, ctrl)
//320 GPIO_SHTDN_CTRL
#define GPIO_GPA_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPA_SHTDN_N, ctrl)
#define GPIO_GPB_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPB_SHTDN_N, ctrl)
#define GPIO_GPC_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPC_SHTDN_N, ctrl)
#define GPIO_GPD_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPD_SHTDN_N, ctrl)
#define GPIO_GPE_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPE_SHTDN_N, ctrl)
#define GPIO_GPF_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPF_SHTDN_N, ctrl)
#define GPIO_GPG_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPG_SHTDN_N, ctrl)
#define GPIO_GPH_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPH_SHTDN_N, ctrl)
#define GPIO_GPI_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPI_SHTDN_N, ctrl)
#define GPIO_GPJ_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPJ_SHTDN_N, ctrl)
#define GPIO_GPK_SHTDN_N_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_GPIO_SHTDN_CTRL, BIT_GPIO_GPK_SHTDN_N, ctrl)
//374
#define EGTIM_FCTRL(ctrl) HAL_PERL_ON_FUNC_CTRL(REG_PERI_EGTIM_CTRL, BIT_PERI_EGTIM_EN, ctrl)
#define EGTIM_RSIG_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_REF_SIG_SEL << BIT_SHIFT_PERI_EGTIM_REF_SIG_SEL), BIT_PERI_EGTIM_REF_SIG_SEL(num))
#define EGTIME_PIN_G0_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP0_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP0_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP0_OPT_SEL(num))
#define EGTIME_PIN_G1_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP1_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP1_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP1_OPT_SEL(num))
#define EGTIME_PIN_G2_OPT_SEL(num) HAL_PERL_ON_PIN_SEL(REG_PERI_EGTIM_CTRL, (BIT_MASK_PERI_EGTIM_PIN_GROUP2_OPT_SEL << BIT_SHIFT_PERI_EGTIM_PIN_GROUP2_OPT_SEL), BIT_PERI_EGTIM_PIN_GROUP2_OPT_SEL(num))
#endif //_HAL_PERI_ON_H_

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#ifndef _HAL_PINMUX_
#define _HAL_PINMUX_
//Function Index
#define UART0 0
#define UART1 1
#define UART2 2
#define SPI0 8
#define SPI1 9
#define SPI2 10
#define SPI0_MCS 15
#define I2C0 16
#define I2C1 17
#define I2C2 18
#define I2C3 19
#define I2S0 24
#define I2S1 25
#define PCM0 28
#define PCM1 29
#define ADC0 32
#define DAC0 36
#define DAC1 37
#define SDIOD 64
#define SDIOH 65
#define USBOTG 66
#define MII 88
#define WL_LED 96
#define WL_ANT0 104
#define WL_ANT1 105
#define WL_BTCOEX 108
#define WL_BTCMD 109
#define NFC 112
#define PWM0 160
#define PWM1 161
#define PWM2 162
#define PWM3 163
#define ETE0 164
#define ETE1 165
#define ETE2 166
#define ETE3 167
#define EGTIM 168
#define SPI_FLASH 196
#define SDR 200
#define JTAG 216
#define TRACE 217
#define LOG_UART 220
#define LOG_UART_IR 221
#define SIC 224
#define EEPROM 225
#define DEBUG 226
//Location Index(Pin Mux Selection)
#define S0 0
#define S1 1
#define S2 2
#define S3 3
_LONG_CALL_ u8
HalPinCtrlRtl8195A(
IN u32 Function,
IN u32 PinLocation,
IN BOOL Operation);
#endif //_HAL_PINMUX_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PLATFORM_
#define _HAL_PLATFORM_
#define ROMVERSION 0x03
#define ROMINFORMATION (ROMVERSION)
#define SYSTEM_CLK PLATFORM_CLOCK
#define SDR_SDRAM_BASE 0x30000000
#define SYSTEM_CTRL_BASE 0x40000000
#define PERI_ON_BASE 0x40000000
#define VENDOR_REG_BASE 0x40002800
#define SPI_FLASH_BASE 0x98000000
#define SDR_CTRL_BASE 0x40005000
#define PERIPHERAL_IRQ_STATUS 0x04
#define PERIPHERAL_IRQ_MODE 0x08
#define PERIPHERAL_IRQ_EN 0x0C
#define LP_PERI_EXT_IRQ_STATUS 0x24
#define LP_PERI_EXT_IRQ_MODE 0x28
#define LP_PERI_EXT_IRQ_EN 0x2C
#define PERIPHERAL_IRQ_ALL_LEVEL 0
#define TIMER_CLK 32*1000
//3 Peripheral IP Base Address
#define GPIO_REG_BASE 0x40001000
#define TIMER_REG_BASE 0x40002000
#define NFC_INTERFACE_BASE 0x40002400
#define LOG_UART_REG_BASE 0x40003000
#define I2C2_REG_BASE 0x40003400
#define I2C3_REG_BASE 0x40003800
#define SPI_FLASH_CTRL_BASE 0x40006000
#define ADC_REG_BASE 0x40010000
#define DAC_REG_BASE 0x40011000
#define UART0_REG_BASE 0x40040000
#define UART1_REG_BASE 0x40040400
#define UART2_REG_BASE 0x40040800
#define SPI0_REG_BASE 0x40042000
#define SPI1_REG_BASE 0x40042400
#define SPI2_REG_BASE 0x40042800
#define I2C0_REG_BASE 0x40044000
#define I2C1_REG_BASE 0x40044400
#define SDIO_DEVICE_REG_BASE 0x40050000
#define MII_REG_BASE 0x40050000
#define SDIO_HOST_REG_BASE 0x40058000
#define GDMA0_REG_BASE 0x40060000
#define GDMA1_REG_BASE 0x40061000
#define I2S0_REG_BASE 0x40062000
#define I2S1_REG_BASE 0x40063000
#define PCM0_REG_BASE 0x40064000
#define PCM1_REG_BASE 0x40065000
#define CRYPTO_REG_BASE 0x40070000
#define WIFI_REG_BASE 0x40080000
#define USB_OTG_REG_BASE 0x400C0000
#define GDMA1_REG_OFF 0x1000
#define I2S1_REG_OFF 0x1000
#define PCM1_REG_OFF 0x1000
#define SSI_REG_OFF 0x400
#define RUART_REG_OFF 0x400
#define CPU_CLK_TYPE_NO 6
enum _BOOT_TYPE_ {
BOOT_FROM_FLASH = 0,
BOOT_FROM_SDIO = 1,
BOOT_FROM_USB = 2,
BOOT_FROM_RSVD = 3,
};
enum _EFUSE_CPU_CLK_ {
#if 1
CLK_200M = 0,
CLK_100M = 1,
CLK_50M = 2,
CLK_25M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#else
CLK_25M = 0,
CLK_200M = 1,
CLK_100M = 2,
CLK_50M = 3,
CLK_12_5M = 4,
CLK_4M = 5,
#endif
};
#endif //_HAL_PLATFORM_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_PWM_H_
#define _HAL_PWM_H_
#define MAX_PWM_CTRL_PIN 4
// the minimum tick time for G-timer is 61 us (clock source = 32768Hz, reload value=1 and reload takes extra 1T)
//#define GTIMER_TICK_US 31 // micro-second, 1000000/32768 ~= 30.5
#define MIN_GTIMER_TIMEOUT 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
#define PWM_GTIMER_TICK_TIME 61 // in micro-sec, use this value to set the g-timer to generate tick for PWM. 61=(1000000/32768)*2
typedef struct _HAL_PWM_ADAPTER_ {
u8 pwm_id; // the PWM ID, 0~3
u8 sel; // PWM Pin selection, 0~3
u8 gtimer_id; // using G-Timer ID, there are 7 G-timer, but we prefer to use timer 3~6
u8 enable; // is enabled
// u32 timer_value; // the G-Timer auto-reload value, source clock is 32768Hz, reload will takes extra 1 tick. To set the time of a tick of PWM
u32 tick_time; // the tick time for the G-timer
u32 period; // the period of a PWM control cycle, in PWM tick
u32 pulsewidth; // the pulse width in a period of a PWM control cycle, in PWM tick. To control the ratio
// float duty_ratio; // the dyty ratio = pulswidth/period
}HAL_PWM_ADAPTER, *PHAL_PWM_ADAPTER;
extern HAL_Status
HAL_Pwm_Init(
u32 pwm_id,
u32 sel
);
extern void
HAL_Pwm_Enable(
u32 pwm_id
);
extern void
HAL_Pwm_Disable(
u32 pwm_id
);
extern void
HAL_Pwm_SetDuty(
u32 pwm_id,
u32 period,
u32 pulse_width
);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SDIO_H_
#define _HAL_SDIO_H_
#include "rtl8195a_sdio.h"
#if !SDIO_BOOT_DRIVER
#include "mailbox.h"
#endif
#define PURE_SDIO_INIC 0 // is a pure SDIO iNIC device or a SDIO iNIC + peripheral device
#if SDIO_BOOT_DRIVER
typedef struct _HAL_SDIO_ADAPTER_ {
u8 *pTXBDAddr; /* The TX_BD start address */
PSDIO_TX_BD pTXBDAddrAligned; /* The TX_BD start address, it must be 4-bytes aligned */
PSDIO_TX_BD_HANDLE pTXBDHdl; /* point to the allocated memory for TX_BD Handle array */
u16 TXBDWPtr; /* The SDIO TX(Host->Device) BD local write index, different with HW maintained write Index. */
u16 TXBDRPtr; /* The SDIO TX(Host->Device) BD read index */
u16 TXBDRPtrReg; /* The SDIO TX(Host->Device) BD read index has been write to HW register */
u16 reserve1;
u8 *pRXBDAddr; /* The RX_BD start address */
PSDIO_RX_BD pRXBDAddrAligned; /* The RX_BD start address, it must be 8-bytes aligned */
PSDIO_RX_BD_HANDLE pRXBDHdl; /* point to the allocated memory for RX_BD Handle array */
u16 RXBDWPtr; /* The SDIO RX(Device->Host) BD write index */
u16 RXBDRPtr; /* The SDIO RX(Device->Host) BD local read index, different with HW maintained Read Index. */
u16 IntMask; /* The Interrupt Mask */
u16 IntStatus; /* The Interrupt Status */
u32 Events; /* The Event to the SDIO Task */
u32 EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */
u8 CCPWM; /* the value write to register CCPWM, which will sync to Host HCPWM */
u8 reserve2;
u16 CCPWM2; /* the value write to register CCPWM2, which will sync to Host HCPWM2 */
s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); /* to hook the WLan driver TX callback function to handle a Packet TX */
VOID *pTxCb_Adapter; /* a pointer will be used to call the TX Callback function,
which is from the TX CallBack function register */
s8 (*pTxCallback_Backup)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); // Use to back up the registered TX Callback function, for MP/Normal mode switch
VOID *pTxCb_Adapter_Backup; // Backup the pTxCb_Adapter, for MP/Normal mode switch
_LIST FreeTxPktList; /* The list to queue free Tx packets handler */
_LIST RxPktList; /* The list to queue RX packets */
_LIST FreeRxPktList; /* The list to queue free Rx packets handler */
SDIO_TX_PACKET *pTxPktHandler; /* to store allocated TX Packet handler memory address */
SDIO_RX_PACKET *pRxPktHandler; /* to store allocated RX Packet handler memory address */
u32 RxInQCnt; /* The packet count for Rx In Queue */
u32 MemAllocCnt; // Memory allocated count, for debug only
u32 MAllocFailedCnt; // MemAlloc Failed count, for debugging
// VOID *pHalOp; /* point to HAL operation function table */
} HAL_SDIO_ADAPTER, *PHAL_SDIO_ADAPTER;
extern BOOL SDIO_Device_Init_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Device_DeInit_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Send_C2H_IOMsg_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 *C2HMsg
);
extern u8 SDIO_Send_C2H_PktMsg_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u8 *C2HMsg,
IN u16 MsgLen
);
extern VOID SDIO_Register_Tx_Callback_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize),
IN VOID *pAdapter
);
extern s8 SDIO_Rx_Callback_Rom(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN VOID *pData,
IN u16 Offset,
IN u16 Length,
IN u8 CmdType
);
#else // else of "#if SDIO_BOOT_DRIVER"
typedef struct _HAL_SDIO_ADAPTER_ {
// u8 *pTxBuff; /* point to the SDIO TX Buffer */
// u8 *pTxBuffAligned; /* point to the SDIO TX Buffer with 4-bytes aligned */
// u32 TXFifoRPtr; /* The SDIO TX(Host->Device) FIFO buffer read pointer */
u8 *pTXBDAddr; /* The TX_BD start address */
PSDIO_TX_BD pTXBDAddrAligned; /* The TX_BD start address, it must be 4-bytes aligned */
PSDIO_TX_BD_HANDLE pTXBDHdl; /* point to the allocated memory for TX_BD Handle array */
u16 TXBDWPtr; /* The SDIO TX(Host->Device) BD local write index, different with HW maintained write Index. */
u16 TXBDRPtr; /* The SDIO TX(Host->Device) BD read index */
u16 TXBDRPtrReg; /* The SDIO TX(Host->Device) BD read index has been write to HW register */
u8 *pRXBDAddr; /* The RX_BD start address */
PSDIO_RX_BD pRXBDAddrAligned; /* The RX_BD start address, it must be 8-bytes aligned */
PSDIO_RX_BD_HANDLE pRXBDHdl; /* point to the allocated memory for RX_BD Handle array */
u16 RXBDWPtr; /* The SDIO RX(Device->Host) BD write index */
u16 RXBDRPtr; /* The SDIO RX(Device->Host) BD local read index, different with HW maintained Read Index. */
u16 IntMask; /* The Interrupt Mask */
u16 IntStatus; /* The Interrupt Status */
u32 Events; /* The Event to the SDIO Task */
u8 CCPWM; /* the value write to register CCPWM, which will sync to Host HCPWM */
u8 reserve1;
u16 CCPWM2; /* the value write to register CCPWM2, which will sync to Host HCPWM2 */
u8 CRPWM; /* sync from Host HRPWM */
u8 reserve2;
u16 CRPWM2; /* sync from Host HRPWM2 */
#if !TASK_SCHEDULER_DISABLED
_Sema TxSema; /* Semaphore for SDIO TX, use to wakeup the SDIO TX task */
_Sema RxSema; /* Semaphore for SDIO RX, use to wakeup the SDIO RX task */
#else
u32 EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */
#endif
s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); /* to hook the WLan driver TX callback function to handle a Packet TX */
VOID *pTxCb_Adapter; /* a pointer will be used to call the TX Callback function,
which is from the TX CallBack function register */
s8 (*pTxCallback_Backup)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize); // Use to back up the registered TX Callback function, for MP/Normal mode switch
VOID *pTxCb_Adapter_Backup; // Backup the pTxCb_Adapter, for MP/Normal mode switch
#if (CONFIG_INIC_EN == 0)
_LIST FreeTxPktList; /* The list to queue free Tx packets handler */
SDIO_TX_PACKET *pTxPktHandler; /* to store allocated TX Packet handler memory address */
#endif
_LIST RxPktList; /* The list to queue RX packets */
_LIST FreeRxPktList; /* The list to queue free Rx packets handler */
// _LIST RecyclePktList; /* The list to queue packets handler to be recycled */
SDIO_RX_PACKET *pRxPktHandler; /* to store allocated RX Packet handler memory address */
_Mutex RxMutex; /* The Mutex to protect RxPktList */
u32 RxInQCnt; /* The packet count for Rx In Queue */
#if SDIO_DEBUG
_Mutex StatisticMutex; /* The Mutex to protect Statistic data */
u32 MemAllocCnt; // Memory allocated count, for debug only
u32 MAllocFailedCnt; // MemAlloc Failed count, for debugging
#endif
VOID *pHalOp; /* point to HAL operation function table */
RTL_MAILBOX *pMBox; /* the Mail box for other driver module can send message to SDIO driver */
#ifdef PLATFORM_FREERTOS
xTaskHandle xSDIOTxTaskHandle; /* The handle of the SDIO Task for TX, can be used to delte the task */
xTaskHandle xSDIORxTaskHandle; /* The handle of the SDIO Task speical for RX, can be used to delte the task */
#endif
u8 RxFifoBusy; /* is the RX BD fetch hardware busy */
#if SDIO_MP_MODE
#if !TASK_SCHEDULER_DISABLED
u32 MP_Events; /* The Event to the SDIO Task */
_Sema MP_EventSema; /* Semaphore for SDIO events, use to wakeup the SDIO task */
RTL_MAILBOX *pMP_MBox; /* the Mail box for communication with other driver module */
#ifdef PLATFORM_FREERTOS
xTaskHandle MP_TaskHandle; /* The handle of the MP loopback Task, can be used to delte the task */
#endif // end of "#ifdef PLATFORM_FREERTOS"
#endif // end of "#if !TASK_SCHEDULER_DISABLED"
// for MP mode
RTL_TIMER *pPeriodTimer; /* a timer to calculate throughput periodically */
u8 MP_ModeEn; /* is in MP mode */
u8 MP_LoopBackEn; /* is loop-back enabled */
u8 MP_ContinueTx; /* is continue TX test enabled */
u8 MP_ContinueRx; /* is continue RX test enabled */
u8 MP_ContinueRxMode; /* continue RX test mode: static RX Buf, Dyna-Allocate RX Buf, Pre-Allocate RX Buf */
u8 MP_CRxInfinite; /* is non-stop SDIO RX, no packet count limit */
u16 MP_CRxSize; /* SDIO RX test packet size */
u8 *pMP_CRxBuf; // the buffer for continye RX test
u32 MP_CRxPktCnt; /* SDIO RX test packet count */
u32 MP_CRxPktPendingCnt; /* SDIO RX test packet pening count */
u32 MP_TxPktCnt; /* SDIO TX packet count */
u32 MP_RxPktCnt; /* SDIO RX packet count */
u32 MP_TxByteCnt; /* SDIO TX Byte count */
u32 MP_RxByteCnt; /* SDIO RX Byte count */
u32 MP_TxDropCnt; /* SDIO TX Drop packet count */
u32 MP_RxDropCnt; /* SDIO RX Drop packet count */
u32 MP_TxPktCntInPeriod; /* SDIO TX packet count in a period */
u32 MP_RxPktCntInPeriod; /* SDIO RX packet count in a period */
u32 MP_TxByteCntInPeriod; /* SDIO TX Byte count in a period */
u32 MP_RxByteCntInPeriod; /* SDIO RX Byte count in a period */
u32 MP_TxAvgTPWin[SDIO_AVG_TP_WIN_SIZE]; /* a window of SDIO TX byte count history, for average throughput calculation */
u32 MP_RxAvgTPWin[SDIO_AVG_TP_WIN_SIZE]; /* a window of SDIO RX byte count history, for average throughput calculation */
u32 MP_TxAvgTPWinSum; /* The sum of all byte-count in the window */
u32 MP_RxAvgTPWinSum; /* The sum of all byte-count in the window */
u8 OldestTxAvgWinIdx; /* the index of the oldest TX byte count log */
u8 TxAvgWinCnt; /* the number of log in the Window */
u8 OldestRxAvgWinIdx; /* the index of the oldest RX byte count log */
u8 RxAvgWinCnt; /* the number of log in the Window */
_LIST MP_RxPktList; /* The list to queue RX packets, for MP loopback test */
#endif // end of '#if SDIO_MP_MODE'
} HAL_SDIO_ADAPTER, *PHAL_SDIO_ADAPTER;
#endif // end of "#else of "#if SDIO_BOOT_DRIVER""
typedef struct _HAL_SDIO_OP_ {
BOOL (*HalSdioDevInit)(PHAL_SDIO_ADAPTER pSDIODev);
VOID (*HalSdioDevDeInit)(PHAL_SDIO_ADAPTER pSDIODev);
VOID (*HalSdioSendC2HIOMsg)(PHAL_SDIO_ADAPTER pSDIODev, u32 *C2HMsg);
u8 (*HalSdioSendC2HPktMsg)(PHAL_SDIO_ADAPTER pSDIODev, u8 *C2HMsg, u16 MsgLen);
VOID (*HalSdioRegTxCallback)(PHAL_SDIO_ADAPTER pSDIODev,s8 (*CallbackFun)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize), VOID *pAdapter);
s8 (*HalSdioRxCallback)(PHAL_SDIO_ADAPTER pSDIODev, VOID *pData, u16 Offset, u16 PktSize, u8 CmdType);
#if SDIO_MP_MODE
VOID (*HalSdioDevMPApp)(PHAL_SDIO_ADAPTER pSDIODev, u16 argc, u8 *argv[]);
#endif
}HAL_SDIO_OP, *PHAL_SDIO_OP;
extern BOOL SDIO_Device_Init(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Device_DeInit(
IN PHAL_SDIO_ADAPTER pSDIODev
);
extern VOID SDIO_Send_C2H_IOMsg(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u32 *C2HMsg
);
extern u8 SDIO_Send_C2H_PktMsg(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u8 *C2HMsg,
IN u16 MsgLen
);
extern VOID SDIO_Register_Tx_Callback(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN s8 (*Tx_Callback)(VOID *pAdapter, u8 *pPkt, u16 Offset, u16 PktSize),
IN VOID *pAdapter
);
extern s8 SDIO_Rx_Callback(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN VOID *pData,
IN u16 Offset,
IN u16 Length,
IN u8 CmdType
);
#if SDIO_MP_MODE
extern VOID SDIO_DeviceMPApp(
IN PHAL_SDIO_ADAPTER pSDIODev,
IN u16 argc,
IN u8 *argv[]
);
#endif
extern PHAL_SDIO_ADAPTER pgSDIODev;
extern VOID HalSdioInit(VOID);
extern VOID HalSdioDeInit(VOID);
#endif // #ifndef _HAL_SDIO_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SDR_CONTROLLER_H_
#define _HAL_SDR_CONTROLLER_H_
typedef enum _DRAM_TYPE_ {
DRAM_DDR_1 = 1,
DRAM_DDR_2 = 2,
DRAM_DDR_3 = 3,
DRAM_DDR_4 = 4,
DRAM_SDR = 8
}DRAM_TYPE;
typedef enum _DRAM_COLADDR_WTH_ {
DRAM_COLADDR_8B = 0,
DRAM_COLADDR_9B = 1,
DRAM_COLADDR_10B = 2,
DRAM_COLADDR_11B = 3,
DRAM_COLADDR_12B = 4,
DRAM_COLADDR_13B = 5,
DRAM_COLADDR_14B = 6,
DRAM_COLADDR_15B = 7,
DRAM_COLADDR_16B = 8
}DRAM_COLADDR_WTH;
typedef enum _DRAM_BANK_SIZE_ {
DRAM_BANK_2 = 0,
DRAM_BANK_4 = 1,
DRAM_BANK_8 = 2
}DRAM_BANK_SIZE;
typedef enum _DRAM_DQ_WIDTH_ {
DRAM_DQ_16 = 0,
DRAM_DQ_32 = 1,
DRAM_HALF_DQ32 = 2
}DRAM_DQ_WIDTH;
typedef enum _MODE0_BST_LEN_ {
BST_LEN_4 = 0,
BST_LEN_FLY = 1,
BST_LEN_8 = 2
}MODE0_BST_LEN;
typedef enum _MODE0_BST_TYPE_ {
SENQUENTIAL = 0,
INTERLEAVE = 1
}MODE0_BST_TYPE;
typedef enum _DFI_RATIO_TYPE_ {
DFI_RATIO_1 = 0, // DFI= 1:1, or SDR
DFI_RATIO_2 = 1,
DFI_RATIO_4 = 2
}DFI_RATIO_TYPE;
typedef struct _DRAM_INFO_ {
DRAM_TYPE DeviceType;
DRAM_COLADDR_WTH ColAddrWth;
DRAM_BANK_SIZE Bank;
DRAM_DQ_WIDTH DqWidth;
}DRAM_INFO;
typedef struct _DRAM_MODE_REG_INFO_ {
MODE0_BST_LEN BstLen;
MODE0_BST_TYPE BstType;
//enum mode0_cas rd_cas;
u32 Mode0Cas;
u32 Mode0Wr;
u32 Mode1DllEnN;
u32 Mode1AllLat;
u32 Mode2Cwl;
}DRAM_MODE_REG_INFO;
typedef struct _DRAM_TIMING_INFO_ {
u32 TrfcPs;
u32 TrefiPs;
u32 WrMaxTck;
u32 TrcdPs;
u32 TrpPs;
u32 TrasPs;
u32 TrrdTck;
u32 TwrPs;
u32 TwtrTck;
//u32 TrtpPs;
u32 TmrdTck;
u32 TrtpTck;
u32 TccdTck;
u32 TrcPs;
}DRAM_TIMING_INFO;
typedef struct _DRAM_DEVICE_INFO_ {
DRAM_INFO *Dev;
DRAM_MODE_REG_INFO *ModeReg;
DRAM_TIMING_INFO *Timing;
u32 DdrPeriodPs;
DFI_RATIO_TYPE *DfiRate;
}DRAM_DEVICE_INFO;
//======================================================
//DRAM Info
#ifdef CONFIG_FPGA
#define DRAM_INFO_TYPE DRAM_SDR
#define DRAM_INFO_COL_ADDR_WTH DRAM_COLADDR_9B
#define DRAM_INFO_BANK_SZ DRAM_BANK_4
#define DRAM_INFO_DQ_WTH DRAM_DQ_16
#else
#define DRAM_INFO_TYPE DRAM_SDR
#define DRAM_INFO_COL_ADDR_WTH DRAM_COLADDR_8B
#define DRAM_INFO_BANK_SZ DRAM_BANK_2
#define DRAM_INFO_DQ_WTH DRAM_DQ_16
#endif
//======================================================
//DRAM Timing
#ifdef CONFIG_SDR_100MHZ
#define DRAM_TIMING_TCK 10000 //ps
#endif
#ifdef CONFIG_SDR_50MHZ
#define DRAM_TIMING_TCK 20000 //ps
#endif
#ifdef CONFIG_SDR_25MHZ
#define DRAM_TIMING_TCK 40000 //ps
#endif
#ifdef CONFIG_SDR_12_5MHZ
#define DRAM_TIMING_TCK 80000 //ps
#endif
#if 1
#define DRAM_TIMING_TREF 64000 //us
#define DRAM_ROW_NUM 8192 //depends on row bit number
#define DRAM_TIMING_TRFC 60000 //ps
#define DRAM_TIMING_TREFI ((u32)((DRAM_TIMING_TREF*1000)/DRAM_ROW_NUM)*1000) //ps
#define DRAM_TIMING_TWRMAXTCK 2 //tck
#define DRAM_TIMING_TRCD 15000 //ps
#define DRAM_TIMING_TRP 15000 //ps
#define DRAM_TIMING_TRAS 42000 //ps
#define DRAM_TIMING_TRRD 2 //tck
#define DRAM_TIMING_TWR ((u32)(DRAM_TIMING_TCK*2))
#define DRAM_TIMING_TWTR 0 //tck
#define DRAM_TIMING_TMRD 2 //tck
#define DRAM_TIMING_TRTP 0 //tck
#define DRAM_TIMING_TCCD 1 //tck
#define DRAM_TIMING_TRC 60000 //ps
#else
#define DRAM_TIMING_TREF 66000 //us
#define DRAM_ROW_NUM 8192 //depends on row bit number
#define DRAM_TIMING_TRFC 66000 //ps
#define DRAM_TIMING_TREFI 63999800
#define DRAM_TIMING_TWRMAXTCK 2 //tck
#define DRAM_TIMING_TRCD 15000 //ps
#define DRAM_TIMING_TRP 15000 //ps
#define DRAM_TIMING_TRAS 37000 //ps
#define DRAM_TIMING_TRRD 2 //tck
#define DRAM_TIMING_TWR 7000
#define DRAM_TIMING_TWTR 0 //tck
#define DRAM_TIMING_TMRD 2 //tck
#define DRAM_TIMING_TRTP 0 //tck
#define DRAM_TIMING_TCCD 1 //tck
#define DRAM_TIMING_TRC 60000 //ps
#endif
#define HAL_SDR_WRITE32(addr, value32) HAL_WRITE32(SDR_CTRL_BASE, addr, value32)
#define HAL_SDR_WRITE16(addr, value16) HAL_WRITE16(SDR_CTRL_BASE, addr, value16)
#define HAL_SDR_WRITE8(addr, value8) HAL_WRITE8(SDR_CTRL_BASE, addr, value8)
#define HAL_SDR_READ32(addr) HAL_READ32(SDR_CTRL_BASE, addr)
#define HAL_SDR_READ16(addr) HAL_READ16(SDR_CTRL_BASE, addr)
#define HAL_SDR_READ8(addr) HAL_READ8(SDR_CTRL_BASE, addr)
#define HAL_SDRAM_WRITE32(addr, value32) HAL_WRITE32(SDR_SDRAM_BASE, addr, value32)
#define HAL_SDRAM_WRITE16(addr, value16) HAL_WRITE16(SDR_SDRAM_BASE, addr, value16)
#define HAL_SDRAM_WRITE8(addr, value8) HAL_WRITE8(SDR_SDRAM_BASE, addr, value8)
#define HAL_SDRAM_READ32(addr) HAL_READ32(SDR_SDRAM_BASE, addr)
#define HAL_SDRAM_READ16(addr) HAL_READ16(SDR_SDRAM_BASE, addr)
#define HAL_SDRAM_READ8(addr) HAL_READ8(SDR_SDRAM_BASE, addr)
#endif // end of "#ifndef _HAL_SDR_CONTROLLER_H_"

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#ifndef _HAL_SOCPWR_
#define _HAL_SOCPWR_
#define MAX_BACKUP_SIZE 129
#define MAXFUNC 10
#define FSTREG 0xFF
#define REG_VDR_ANACK_CAL_CTRL 0xA0
#define PS_MASK 0xFFFFFFFF
//pwr state
#define HWACT 0
#define HWCG 1
#define HWINACT 2
#define UNDEF 3
#define ALLMET 0xff
//SLP
#define SLP_STIMER BIT0
#define SLP_GTIMER BIT1
#define SLP_GPIO BIT2
#define SLP_WL BIT3
#define SLP_NFC BIT4
#define SLP_SDIO BIT5
#define SLP_USB BIT6
#define SLP_TIMER33 BIT7
//DSTBY
#define DSTBY_STIMER BIT0
#define DSTBY_NFC BIT1
#define DSTBY_TIMER33 BIT2
#define DSTBY_GPIO BIT3
//DS wake event
#define DS_TIMER33 BIT0
#define DS_GPIO BIT1
enum power_state_idx{
ACT = 0,
WFE = 1,
WFI = 2,
SNOOZE = 3,
SLPCG = 4,
SLPPG = 5,
DSTBY = 6,
DSLP = 7,
INACT = 8,
MAXSTATE = 9
};
enum clk_idx{
ANACK = 0,
A33CK = 1,
};
typedef struct _power_state_{
u8 FuncIdx;
u8 PowerState;
}POWER_STATE, *pPOWER_STATE;
typedef struct _reg_power_state_{
u8 FuncIdx;
u8 PwrState;
}REG_POWER_STATE, *pPREG_POWER_STATE;
#if 0
typedef struct _power_state_{
u8 FuncIdx;
u8 PowerState;
u32 ReqDuration;
u32 RegCount;
u32 RemainDuration;
}POWER_STATE, *pPOWER_STATE;
typedef struct _reg_power_state_{
u8 FuncIdx;
u8 PwrState;
u32 ReqDuration;
//u8 StateIdx;
}REG_POWER_STATE, *pPREG_POWER_STATE;
#endif
typedef struct _power_mgn_{
u8 ActFuncCount;
POWER_STATE PwrState[MAXFUNC];
u8 CurrentState;
u8 SDREn;
u32 MSPbackup[MAX_BACKUP_SIZE];
u32 CPURegbackup[25];
u32 CPUPSP;
u32 WakeEventFlag;
BOOL SleepFlag;
//u32 CPUReg[13];
//u32 MSBackUp[128];
}Power_Mgn, *pPower_Mgn;
typedef struct _SYS_ADAPTER_ {
u8 function;
}SYS_ADAPTER, *PSYS_ADAPTER;
extern Power_Mgn PwrAdapter;
u8 ChangeSoCPwrState(
IN u8 RequestState,
IN u32 ReqCount
);
VOID PrintCPU(VOID);
void WakeFromSLPPG(void);
VOID SOCPSTestApp(VOID *Data);
__inline static VOID
CPURegBackUp(
VOID
)
{
#if defined (__ICCARM__)
// TODO: IAR has different way using assembly
#elif defined (__GNUC__)
//backup cpu reg
#if 0
asm volatile
(
"PUSH {PSR, PC, LR, R12,R3,R2,R1,R0}\n"
);
#endif
#if 0
asm volatile
(
"PUSH {r0,r1,r2,r3,r4}\n"
);
#endif
asm volatile
(
"MOV %0, r0\n"
:"=r"(PwrAdapter.CPURegbackup[0])
::"memory"
);
asm volatile
(
"MOV %0, r1\n"
:"=r"(PwrAdapter.CPURegbackup[1])
::"memory"
);
asm volatile
(
"MOV %0, r2\n"
:"=r"(PwrAdapter.CPURegbackup[2])
::"memory"
);
asm volatile
(
"MOV %0, r3\n"
:"=r"(PwrAdapter.CPURegbackup[3])
::"memory"
);
asm volatile
(
"MOV %0, r4\n"
:"=r"(PwrAdapter.CPURegbackup[4])
::"memory"
);
asm volatile
(
"MOV %0, r5\n"
:"=r"(PwrAdapter.CPURegbackup[5])
::"memory"
);
asm volatile
(
"MOV %0, r6\n"
:"=r"(PwrAdapter.CPURegbackup[6])
::"memory"
);
asm volatile
(
"MOV %0, r7\n"
:"=r"(PwrAdapter.CPURegbackup[7])
::"memory"
);
asm volatile
(
"MOV %0, r8\n"
:"=r"(PwrAdapter.CPURegbackup[8])
::"memory"
);
asm volatile
(
"MOV %0, r9\n"
:"=r"(PwrAdapter.CPURegbackup[9])
::"memory"
);
asm volatile
(
"MOV %0, r10\n"
:"=r"(PwrAdapter.CPURegbackup[10])
::"memory"
);
asm volatile
(
"MOV %0, r11\n"
:"=r"(PwrAdapter.CPURegbackup[11])
::"memory"
);
asm volatile
(
"MOV %0, r12\n"
:"=r"(PwrAdapter.CPURegbackup[12])
::"memory"
);
asm volatile
(
"MOV %0, r13\n"
:"=r"(PwrAdapter.CPURegbackup[13])
::"memory"
);
asm volatile
(
//"MOV %0, r14\n"
"LDR %0, =SLPPG_WAKEUP_POINT\n"
"ADD %0, #1\n"
:"=r"(PwrAdapter.CPURegbackup[14])
::"memory"
);
asm volatile
(
"LDR %0, =SLPPG_WAKEUP_POINT\n"
"ADD %0, #1\n"
:"=r"(PwrAdapter.CPURegbackup[15])
::"memory"
);
asm volatile
(
"MRS %0, PSR\n"
:"=r"(PwrAdapter.CPURegbackup[16])
::"memory"
);
#if 1
asm volatile
(
"mov %0, r13\n"
"MOV %1, PC\n"
"MRS %2, CONTROL\n"
"MRS %3, PSP\n"
"MRS %4, MSP\n"
:"=r"(PwrAdapter.CPURegbackup[24]),"=r"(PwrAdapter.CPURegbackup[23]),"=r"(PwrAdapter.CPURegbackup[22]),"=r"(PwrAdapter.CPURegbackup[21]),"=r"(PwrAdapter.CPURegbackup[20])
::"memory"
);
#endif
#ifdef CONFIG_SOC_PS_VERIFY
PrintCPU();
#endif //#ifdef CONFIG_SOC_PS_VERIFY
#endif //#elif defined (__GNUC__)
}
VOID RegPowerState(REG_POWER_STATE RegPwrState);
#endif //_HAL_SOCPWR_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SPIFLASH__
#define _HAL_SPIFLASH__
//======================================================
// Header files
#define SPIC_CALIBRATION_IN_NVM 1 // if store the SPIC calibration data in the NVM
#ifndef CONFIG_IMAGE_SEPARATE // Store SPIC Calibration only for seprated image
#undef SPIC_CALIBRATION_IN_NVM
#define SPIC_CALIBRATION_IN_NVM 0
#endif
//======================================================
// Definition
#define HAL_SPI_WRITE32(addr, value32) HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32)
#define HAL_SPI_WRITE16(addr, value16) HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16)
#define HAL_SPI_WRITE8(addr, value8) HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8)
#define HAL_SPI_READ32(addr) HAL_READ32(SPI_FLASH_CTRL_BASE, addr)
#define HAL_SPI_READ16(addr) HAL_READ16(SPI_FLASH_CTRL_BASE, addr)
#define HAL_SPI_READ8(addr) HAL_READ8(SPI_FLASH_CTRL_BASE, addr)
typedef struct _SPIC_PARA_MODE_ {
u8 Valid:1; // valid
u8 CpuClk:3; // CPU clock
u8 BitMode:2; // Bit mode
u8 Reserved:2; // reserved
} SPIC_PARA_MODE, *PSPIC_PARA_MODE;
typedef struct _SPIC_INIT_PARA_ {
u8 BaudRate;
u8 RdDummyCyle;
u8 DelayLine;
union {
u8 Rsvd;
u8 Valid;
SPIC_PARA_MODE Mode;
};
#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
u8 id[3];
u8 flashtype;
#endif
}SPIC_INIT_PARA, *PSPIC_INIT_PARA;
enum _SPIC_BIT_MODE_ {
SpicOneBitMode = 0,
SpicDualBitMode = 1,
SpicQuadBitMode = 2,
};
//======================================================
// Flash type used
#define FLASH_OTHERS 0
#define FLASH_MXIC 1
#define FLASH_WINBOND 2
#define FLASH_MICRON 3
#define FLASH_MXIC_MX25L4006E 1
#define FLASH_MXIC_MX25L8073E 0
// The below parts are based on the flash characteristics
//====== Flash Command Definition ======
#if FLASH_MXIC_MX25L4006E
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52)
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#elif FLASH_MXIC_MX25L8073E
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0x52 //Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#else
#define FLASH_CMD_WREN 0x06 //write enable
#define FLASH_CMD_WRDI 0x04 //write disable
#define FLASH_CMD_WRSR 0x01 //write status register
#define FLASH_CMD_RDID 0x9F //read idenfication
#define FLASH_CMD_RDSR 0x05 //read status register
#define FLASH_CMD_READ 0x03 //read data
#define FLASH_CMD_FREAD 0x0B //fast read data
#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
#define FLASH_CMD_RES 0xAB //Read Electronic ID
#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
#define FLASH_CMD_SE 0x20 //Sector Erase
#define FLASH_CMD_BE 0x52 //Block Erase
#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
#define FLASH_CMD_PP 0x02 //Page Program
#define FLASH_CMD_DP 0xB9 //Deep Power Down
#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
#define FLASH_CMD_4PP 0x38 //quad page program
#define FLASH_CMD_FF 0xFF //Release Read Enhanced
#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
#define FLASH_CMD_RDSCUR 0x2B // read security register
#define FLASH_CMD_WRSCUR 0x2F // write security register
#endif //#if FLASH_MXIC_MX25L4006E
// ============================
// ===== Flash Parameter Definition =====
#if FLASH_MXIC_MX25L4006E
#define FLASH_RD_2IO_EN 0
#define FLASH_RD_2O_EN 1
#define FLASH_RD_4IO_EN 0
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 0
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 0
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I)
#define FLASH_VLD_QUAD_CMDS (0)
#elif FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it,
//the code MUST be rechecked according to the flash spec.
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x04
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#else
#define FLASH_RD_2IO_EN 1
#define FLASH_RD_2O_EN 0
#define FLASH_RD_4IO_EN 1
#define FLASH_RD_4O_EN 0
#define FLASH_WR_2IO_EN 1
#define FLASH_WR_2O_EN 0
#define FLASH_WR_4IO_EN 1
#define FLASH_WR_4O_EN 0
#define FLASH_DM_CYCLE_2O 0x08
#define FLASH_DM_CYCLE_2IO 0x04
#define FLASH_DM_CYCLE_4O 0x08
#define FLASH_DM_CYCLE_4IO 0x04
#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
#endif
#if 0
//======================================================
// Function prototype
BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
_LONG_CALL_
extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
// spi-flash controller initialization
_LONG_CALL_
extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode);
// wait sr[0] = 0, wait transmission done
_LONG_CALL_
extern VOID SpicWaitBusyDoneRtl8195A(VOID);
// wait spi-flash status register[0] = 0
//_LONG_CALL_
//extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara);
#endif
//======================================================
// ROM Function prototype
_LONG_CALL_ VOID SpiFlashAppV02(IN VOID *Data);
_LONG_CALL_ROM_ VOID SpicInitRtl8195AV02(IN u8 InitBaudRate,IN u8 SpicBitMode);
_LONG_CALL_ROM_ VOID SpicEraseFlashRtl8195AV02(VOID);
_LONG_CALL_ROM_ VOID SpicLoadInitParaFromClockRtl8195AV02(IN u8 CpuClkMode,IN u8 BaudRate,IN PSPIC_INIT_PARA pSpicInitPara);
VOID SpicBlockEraseFlashRtl8195A(IN u32 Address);
VOID SpicSectorEraseFlashRtl8195A(IN u32 Address);
VOID SpicDieEraseFlashRtl8195A(IN u32 Address);
VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect);
VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicWaitOperationDoneRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara);
u8 SpicGetFlashStatusRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate,IN u8 SpicBitMode);
u32 SpicWaitWipRtl8195A(VOID);
u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
VOID SpicDisableRtl8195A(VOID);
VOID SpicDeepPowerDownFlashRtl8195A(VOID);
VOID SpicUserProgramRtl8195A(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo);
#if SPIC_CALIBRATION_IN_NVM
VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk);
VOID SpicNVMCalLoadAll(void);
VOID SpicNVMCalStore(u8 BitMode, u8 CpuClk);
#endif // #if SPIC_CALIBRATION_IN_NVM
#endif //_HAL_SPIFLASH__

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_SSI_H_
#define _HAL_SSI_H_
#include "rtl8195a_ssi.h"
/**
* LOG Configurations
*/
extern u32 SSI_DBG_CONFIG;
extern uint8_t SPI0_IS_AS_SLAVE;
#define SSI_DBG_ENTRANCE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENTRANCE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE ANSI_COLOR_GREEN __VA_ARGS__ ANSI_COLOR_RESET); \
}while(0)
#define SSI_DBG_INIT(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INIT_V(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_V)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INIT_VV(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INIT_VV)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_PINMUX(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_PINMUX)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_ENDIS(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_ENDIS)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_V(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_V)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_HNDLR(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_HNDLR)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_READ(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_READ)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_INT_WRITE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_INT_WRITE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_STATUS(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_STATUS)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_FIFO(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_FIFO)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_READ(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_READ)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_WRITE(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_WRITE)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
#define SSI_DBG_SLV_CTRL(...) do {\
if (unlikely(SSI_DBG_CONFIG & DBG_TYPE_SLV_CTRL)) \
DBG_SSI_INFO(IDENT_FOUR_SPACE __VA_ARGS__); \
}while(0)
typedef enum _SSI_DBG_TYPE_LIST_ {
DBG_TYPE_ENTRANCE = 1 << 0,
DBG_TYPE_INIT = 1 << 1,
DBG_TYPE_INIT_V = 1 << 2,
DBG_TYPE_INIT_VV = 1 << 3,
DBG_TYPE_PINMUX = 1 << 4,
DBG_TYPE_ENDIS = 1 << 5,
DBG_TYPE_INT = 1 << 6,
DBG_TYPE_INT_V = 1 << 7,
DBG_TYPE_INT_HNDLR = 1 << 8,
DBG_TYPE_INT_READ = 1 << 9,
DBG_TYPE_INT_WRITE = 1 << 10,
DBG_TYPE_STATUS = 1 << 11,
DBG_TYPE_FIFO = 1 << 12,
DBG_TYPE_READ = 1 << 13,
DBG_TYPE_WRITE = 1 << 14,
DBG_TYPE_SLV_CTRL = 1 << 15
} SSI_DBG_TYPE_LIST, *PSSI_DBG_TYPE_LIST;
typedef struct _SSI_DMA_CONFIG_ {
VOID *pHalGdmaOp;
VOID *pTxHalGdmaAdapter;
VOID *pRxHalGdmaAdapter;
u8 RxDmaBurstSize;
u8 TxDmaBurstSize;
u8 RxDmaEnable;
u8 TxDmaEnable;
IRQ_HANDLE RxGdmaIrqHandle;
IRQ_HANDLE TxGdmaIrqHandle;
}SSI_DMA_CONFIG, *PSSI_DMA_CONFIG;
/**
* DesignWare SSI Configurations
*/
typedef struct _HAL_SSI_ADAPTOR_ {
SSI_DMA_CONFIG DmaConfig;
IRQ_HANDLE IrqHandle;
//
VOID (*RxCompCallback)(VOID *Para);
VOID *RxCompCbPara;
VOID *RxData;
VOID (*TxCompCallback)(VOID *Para);
VOID *TxCompCbPara;
VOID *TxData;
u32 DmaRxDataLevel;
u32 DmaTxDataLevel;
u32 InterruptPriority;
u32 RxLength;
u32 RxLengthRemainder;
u32 RxThresholdLevel;
u32 TxLength;
u32 TxThresholdLevel;
u32 SlaveSelectEnable;
//
u16 ClockDivider;
u16 DataFrameNumber;
//
u8 ControlFrameSize;
u8 DataFrameFormat;
u8 DataFrameSize;
u8 DmaControl;
u8 Index;
u8 InterruptMask;
u8 MicrowireDirection;
u8 MicrowireHandshaking;
u8 MicrowireTransferMode;
u8 PinmuxSelect;
u8 Role;
u8 SclkPhase;
u8 SclkPolarity;
u8 SlaveOutputEnable;
u8 TransferMode;
u8 TransferMechanism;
// Extend
u32 Reserved1;
u8 DefaultRxThresholdLevel;
}HAL_SSI_ADAPTOR, *PHAL_SSI_ADAPTOR;
typedef struct _HAL_SSI_OP_{
HAL_Status (*HalSsiPinmuxEnable)(VOID *Adaptor);
HAL_Status (*HalSsiPinmuxDisable)(VOID *Adaptor);
HAL_Status (*HalSsiEnable)(VOID *Adaptor);
HAL_Status (*HalSsiDisable)(VOID *Adaptor);
HAL_Status (*HalSsiInit)(VOID *Adaptor);
HAL_Status (*HalSsiSetSclkPolarity)(VOID *Adaptor);
HAL_Status (*HalSsiSetSclkPhase)(VOID *Adaptor);
HAL_Status (*HalSsiWrite)(VOID *Adaptor, u32 value);
HAL_Status (*HalSsiLoadSetting)(VOID *Adaptor, VOID *Setting);
HAL_Status (*HalSsiSetInterruptMask)(VOID *Adaptor);
HAL_Status (*HalSsiSetDeviceRole)(VOID *Adaptor, u32 Role);
HAL_Status (*HalSsiInterruptEnable)(VOID *Adaptor);
HAL_Status (*HalSsiInterruptDisable)(VOID *Adaptor);
HAL_Status (*HalSsiReadInterrupt)(VOID *Adaptor, VOID *RxData, u32 Length);
HAL_Status (*HalSsiSetRxFifoThresholdLevel)(VOID *Adaptor);
HAL_Status (*HalSsiSetTxFifoThresholdLevel)(VOID *Adaptor);
HAL_Status (*HalSsiWriteInterrupt)(VOID *Adaptor, u8 *TxData, u32 Length);
HAL_Status (*HalSsiSetSlaveEnableRegister)(VOID *Adaptor, u32 SlaveIndex);
u32 (*HalSsiBusy)(VOID *Adaptor);
u32 (*HalSsiReadable)(VOID *Adaptor);
u32 (*HalSsiWriteable)(VOID *Adaptor);
u32 (*HalSsiGetInterruptMask)(VOID *Adaptor);
u32 (*HalSsiGetRxFifoLevel)(VOID *Adaptor);
u32 (*HalSsiGetTxFifoLevel)(VOID *Adaptor);
u32 (*HalSsiGetStatus)(VOID *Adaptor);
u32 (*HalSsiGetInterruptStatus)(VOID *Adaptor);
u32 (*HalSsiRead)(VOID *Adaptor);
u32 (*HalSsiGetRawInterruptStatus)(VOID *Adaptor);
u32 (*HalSsiGetSlaveEnableRegister)(VOID *Adaptor);
}HAL_SSI_OP, *PHAL_SSI_OP;
typedef struct _DW_SSI_DEFAULT_SETTING_ {
VOID (*RxCompCallback)(VOID *Para);
VOID *RxCompCbPara;
VOID *RxData;
VOID (*TxCompCallback)(VOID *Para);
VOID *TxCompCbPara;
VOID *TxData;
u32 DmaRxDataLevel;
u32 DmaTxDataLevel;
u32 InterruptPriority;
u32 RxLength;
u32 RxLengthRemainder;
u32 RxThresholdLevel;
u32 TxLength;
u32 TxThresholdLevel;
u32 SlaveSelectEnable;
//
u16 ClockDivider;
u16 DataFrameNumber;
//
u8 ControlFrameSize;
u8 DataFrameFormat;
u8 DataFrameSize;
u8 DmaControl;
//u8 Index;
u8 InterruptMask;
u8 MicrowireDirection;
u8 MicrowireHandshaking;
u8 MicrowireTransferMode;
//u8 PinmuxSelect;
//u8 Role;
u8 SclkPhase;
u8 SclkPolarity;
u8 SlaveOutputEnable;
u8 TransferMode;
u8 TransferMechanism;
} DW_SSI_DEFAULT_SETTING, *PDW_SSI_DEFAULT_SETTING;
struct spi_s {
HAL_SSI_ADAPTOR spi_adp;
HAL_SSI_OP spi_op;
u32 irq_handler;
u32 irq_id;
u32 dma_en;
u32 state;
u8 sclk;
#ifdef CONFIG_GDMA_EN
HAL_GDMA_ADAPTER spi_gdma_adp_tx;
HAL_GDMA_ADAPTER spi_gdma_adp_rx;
#endif
};
VOID HalSsiOpInit(VOID *Adaptor);
static __inline__ VOID HalSsiSetSclk(
IN PHAL_SSI_ADAPTOR pHalSsiAdapter,
IN u32 ClkRate)
{
HalSsiSetSclkRtl8195a((VOID*)pHalSsiAdapter, ClkRate);
}
HAL_Status HalSsiInit(VOID * Data);
HAL_Status HalSsiDeInit(VOID * Data);
HAL_Status HalSsiEnable(VOID * Data);
HAL_Status HalSsiDisable(VOID * Data);
#ifdef CONFIG_GDMA_EN
HAL_Status HalSsiTxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
VOID HalSsiTxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
HAL_Status HalSsiRxGdmaInit(PHAL_SSI_OP pHalSsiOp, PHAL_SSI_ADAPTOR pHalSsiAdapter);
VOID HalSsiRxGdmaDeInit(PHAL_SSI_ADAPTOR pHalSsiAdapter);
static __inline__ VOID
HalSsiDmaInit(
IN PHAL_SSI_ADAPTOR pHalSsiAdapter
)
{
HalSsiDmaInitRtl8195a((void *)pHalSsiAdapter);
}
static __inline__ HAL_Status HalSsiDmaSend(VOID *Adapter, u8 *pTxData, u32 Length)
{
return (HalSsiDmaSendRtl8195a(Adapter, pTxData, Length));
}
static __inline__ HAL_Status HalSsiDmaRecv(VOID *Adapter, u8 *pRxData, u32 Length)
{
return (HalSsiDmaRecvRtl8195a(Adapter, pRxData, Length));
}
#endif // end of "#ifdef CONFIG_GDMA_EN"
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_TIMER_H_
#define _HAL_TIMER_H_
#include "basic_types.h"
#include "hal_platform.h"
#include "rtl8195a_timer.h"
#define GTIMER_CLK_HZ (32768)
#define GTIMER_TICK_US (1000000/GTIMER_CLK_HZ)
typedef enum _TIMER_MODE_ {
FREE_RUN_MODE = 0,
USER_DEFINED = 1
}TIMER_MODE, *PTIMER_MODE;
typedef struct _TIMER_ADAPTER_ {
u32 TimerLoadValueUs;
u32 TimerIrqPriority;
TIMER_MODE TimerMode;
IRQ_HANDLE IrqHandle;
u8 TimerId;
u8 IrqDis;
}TIMER_ADAPTER, *PTIMER_ADAPTER;
typedef struct _HAL_TIMER_OP_ {
u32 (*HalGetTimerId)(u32 *TimerId);
BOOL (*HalTimerInit)(VOID *Data);
u32 (*HalTimerReadCount)(u32 TimerId);
VOID (*HalTimerIrqClear)(u32 TimerId);
VOID (*HalTimerDis)(u32 TimerId);
VOID (*HalTimerEn)(u32 TimerId);
VOID (*HalTimerDumpReg)(u32 TimerId);
}HAL_TIMER_OP, *PHAL_TIMER_OP;
VOID HalTimerOpInit_Patch(
IN VOID *Data
);
//======================================================
// ROM Function prototype
_LONG_CALL_ VOID HalTimerOpInitV02(IN VOID *Data);
//pvxx #define HalTimerOpInit HalTimerOpInit_Patch
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_UART_H_
#define _HAL_UART_H_
#include "rtl8195a_uart.h"
/**
* RUART Configurations
*/
#define UART_WAIT_FOREVER 0xffffffff
typedef struct _UART_DMA_CONFIG_ {
u8 TxDmaEnable;
u8 RxDmaEnable;
u8 TxDmaBurstSize;
u8 RxDmaBurstSize;
VOID *pHalGdmaOp;
VOID *pTxHalGdmaAdapter;
VOID *pRxHalGdmaAdapter;
IRQ_HANDLE TxGdmaIrqHandle;
IRQ_HANDLE RxGdmaIrqHandle;
}UART_DMA_CONFIG, *PUART_DMA_CONFIG;
typedef struct _HAL_RUART_ADAPTER_ {
u32 BaudRate;
u32 FlowControl;
u32 FifoControl;
u32 Interrupts;
u32 TxCount; // how many byte to TX
u32 RxCount; // how many bytes to RX
u8 *pTxBuf;
u8 *pRxBuf;
HAL_UART_State State; // UART state
u8 Status; // Transfer Status
u8 Locked; // is UART locked for operation
u8 UartIndex;
u8 WordLen; // word length select: 0 -> 7 bits, 1 -> 8 bits
u8 StopBit; // word length select: 0 -> 1 stop bit, 1 -> 2 stop bit
u8 Parity; // parity check enable
u8 ParityType; // parity check type
u8 StickParity;
u8 ModemStatus; // the modem status
u8 DmaEnable;
u8 TestCaseNumber;
u8 PinmuxSelect;
BOOL PullMode;
IRQ_HANDLE IrqHandle;
PUART_DMA_CONFIG DmaConfig;
VOID (*ModemStatusInd)(VOID *pAdapter); // modem status indication interrupt handler
VOID (*TxTDCallback)(VOID *pAdapter); // User Tx Done callback function
VOID (*RxDRCallback)(VOID *pAdapter); // User Rx Data ready callback function
VOID (*TxCompCallback)(VOID *para); // User Tx complete callback function
VOID (*RxCompCallback)(VOID *para); // User Rx complete callback function
VOID *TxTDCbPara; // the pointer agrument for TxTDCallback
VOID *RxDRCbPara; // the pointer agrument for RxDRCallback
VOID *TxCompCbPara; // the pointer argument for TxCompCbPara
VOID *RxCompCbPara; // the pointer argument for RxCompCallback
VOID (*EnterCritical)(void);
VOID (*ExitCritical)(void);
//1 New member only can be added below: members above must be fixed for ROM code
u32 *pDefaultBaudRateTbl; // point to the table of pre-defined baud rate
u8 *pDefaultOvsrRTbl; // point to the table of OVSR for pre-defined baud rate
u16 *pDefaultDivTbl; // point to the table of DIV for pre-defined baud rate
u8 *pDefOvsrAdjBitTbl_10; // point to the table of OVSR-Adj bits for 10 bits
u8 *pDefOvsrAdjBitTbl_9; // point to the table of OVSR-Adj bits for 9 bits
u8 *pDefOvsrAdjBitTbl_8; // point to the table of OVSR-Adj bits for 8 bits
u16 *pDefOvsrAdjTbl_10; // point to the table of OVSR-Adj for pre-defined baud rate
u16 *pDefOvsrAdjTbl_9; // point to the table of OVSR-Adj for pre-defined baud rate
u16 *pDefOvsrAdjTbl_8; // point to the table of OVSR-Adj for pre-defined baud rate
u32 BaudRateUsing; // Current using Baud-Rate
#if CONFIG_CHIP_E_CUT
u8 TxState;
u8 RxState;
u32 TxInitSize; // how many byte to TX at atart
u32 RxInitSize; // how many bytes to RX at start
VOID (*RuartEnterCritical)(VOID *para); // enter critical: disable UART interrupt
VOID (*RuartExitCritical)(VOID *para); // exit critical: re-enable UART interrupt
VOID (*TaskYield)(VOID *para); // User Task Yield: do a context switch while waitting
VOID *TaskYieldPara; // the agrument (pointer) for TaskYield
#endif // #if CONFIG_CHIP_E_CUT
}HAL_RUART_ADAPTER, *PHAL_RUART_ADAPTER;
typedef struct _HAL_RUART_OP_ {
VOID (*HalRuartAdapterLoadDef)(VOID *pAdp, u8 UartIdx); // Load UART adapter default setting
VOID (*HalRuartTxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load TX GDMA default setting
VOID (*HalRuartRxGdmaLoadDef)(VOID *pAdp, VOID *pCfg); // Load RX GDMA default setting
HAL_Status (*HalRuartResetRxFifo)(VOID *Data);
HAL_Status (*HalRuartInit)(VOID *Data);
VOID (*HalRuartDeInit)(VOID *Data);
HAL_Status (*HalRuartPutC)(VOID *Data, u8 TxData);
u32 (*HalRuartSend)(VOID *Data, u8 *pTxData, u32 Length, u32 Timeout);
HAL_Status (*HalRuartIntSend)(VOID *Data, u8 *pTxData, u32 Length);
HAL_Status (*HalRuartDmaSend)(VOID *Data, u8 *pTxData, u32 Length);
HAL_Status (*HalRuartStopSend)(VOID *Data);
HAL_Status (*HalRuartGetC)(VOID *Data, u8 *pRxByte);
u32 (*HalRuartRecv)(VOID *Data, u8 *pRxData, u32 Length, u32 Timeout);
HAL_Status (*HalRuartIntRecv)(VOID *Data, u8 *pRxData, u32 Length);
HAL_Status (*HalRuartDmaRecv)(VOID *Data, u8 *pRxData, u32 Length);
HAL_Status (*HalRuartStopRecv)(VOID *Data);
u8 (*HalRuartGetIMR)(VOID *Data);
VOID (*HalRuartSetIMR)(VOID *Data);
u32 (*HalRuartGetDebugValue)(VOID *Data, u32 DbgSel);
VOID (*HalRuartDmaInit)(VOID *Data);
VOID (*HalRuartRTSCtrl)(VOID *Data, BOOLEAN RtsCtrl);
VOID (*HalRuartRegIrq)(VOID *Data);
VOID (*HalRuartIntEnable)(VOID *Data);
VOID (*HalRuartIntDisable)(VOID *Data);
}HAL_RUART_OP, *PHAL_RUART_OP;
typedef struct _RUART_DATA_ {
PHAL_RUART_ADAPTER pHalRuartAdapter;
BOOL PullMode;
u8 BinaryData;
u8 SendBuffer;
u8 RecvBuffer;
}RUART_DATA, *PRUART_DATA;
typedef struct _RUART_ADAPTER_ {
PHAL_RUART_OP pHalRuartOp;
PHAL_RUART_ADAPTER pHalRuartAdapter;
PUART_DMA_CONFIG pHalRuartDmaCfg;
}RUART_ADAPTER, *PRUART_ADAPTER;
extern VOID
HalRuartOpInit(
IN VOID *Data
);
extern HAL_Status
HalRuartTxGdmaInit(
PHAL_RUART_OP pHalRuartOp,
PHAL_RUART_ADAPTER pHalRuartAdapter,
PUART_DMA_CONFIG pUartGdmaConfig
);
extern VOID
HalRuartTxGdmaDeInit(
PUART_DMA_CONFIG pUartGdmaConfig
);
extern HAL_Status
HalRuartRxGdmaInit(
PHAL_RUART_OP pHalRuartOp,
PHAL_RUART_ADAPTER pHalRuartAdapter,
PUART_DMA_CONFIG pUartGdmaConfig
);
extern VOID
HalRuartRxGdmaDeInit(
PUART_DMA_CONFIG pUartGdmaConfig
);
extern HAL_Status
HalRuartResetTxFifo(
VOID *Data
);
extern HAL_Status
HalRuartSetBaudRate(
IN VOID *Data
);
extern HAL_Status
HalRuartInit(
IN VOID *Data
);
extern VOID
HalRuartDeInit(
IN VOID *Data
);
extern HAL_Status
HalRuartDisable(
IN VOID *Data
);
extern HAL_Status
HalRuartEnable(
IN VOID *Data
);
HAL_Status
HalRuartFlowCtrl(
IN VOID *Data
);
extern const HAL_RUART_OP _HalRuartOp;
extern HAL_Status RuartLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
extern VOID RuartUnLock (PHAL_RUART_ADAPTER pHalRuartAdapter);
#endif

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_USB_H_
#define _HAL_USB_H_
#include "rtl8195a_usb.h"
#endif //_HAL_USB_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_UTIL_H_
#define _HAL_UTIL_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* Simple doubly linked list implementation.
*
* Some of the internal functions ("__xxx") are useful when
* manipulating whole lists rather than single entries, as
* sometimes we already know the next/prev entries and we can
* generate better code by using them directly rather than
* using the generic single-entry routines.
*/
struct LIST_HEADER {
struct LIST_HEADER *Next, *Prev;
};
typedef struct LIST_HEADER _LIST;
//#define RTL_LIST_HEAD_INIT(name) { &(name), &(name) }
#define RTL_INIT_LIST_HEAD(ptr) do { \
(ptr)->Next = (ptr); (ptr)->Prev = (ptr); \
} while (0)
/*
* Insert a new entry between two known consecutive entries.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline__ VOID
__List_Add(
IN struct LIST_HEADER * New,
IN struct LIST_HEADER * Prev,
IN struct LIST_HEADER * Next
)
{
Next->Prev = New;
New->Next = Next;
New->Prev = Prev;
Prev->Next = New;
}
/*
* Delete a list entry by making the prev/next entries
* point to each other.
*
* This is only for internal list manipulation where we know
* the prev/next entries already!
*/
static __inline__ VOID
__List_Del(
IN struct LIST_HEADER * Prev,
IN struct LIST_HEADER * Next
)
{
Next->Prev = Prev;
Prev->Next = Next;
}
/**
* ListDel - deletes entry from list.
* @entry: the element to delete from the list.
* Note: list_empty on entry does not return true after this, the entry is in an undefined state.
*/
static __inline__ VOID
ListDel(
IN struct LIST_HEADER *Entry
)
{
__List_Del(Entry->Prev, Entry->Next);
}
/**
* ListDelInit - deletes entry from list and reinitialize it.
* @entry: the element to delete from the list.
*/
static __inline__ VOID
ListDelInit(
IN struct LIST_HEADER *Entry
)
{
__List_Del(Entry->Prev, Entry->Next);
RTL_INIT_LIST_HEAD(Entry);
}
/**
* ListEmpty - tests whether a list is empty
* @head: the list to test.
*/
static __inline__ u32
ListEmpty(
IN struct LIST_HEADER *Head
)
{
return Head->Next == Head;
}
/**
* ListSplice - join two lists
* @list: the new list to add.
* @head: the place to add it in the first list.
*/
static __inline__ VOID
ListSplice(
IN struct LIST_HEADER *List,
IN struct LIST_HEADER *Head
)
{
struct LIST_HEADER *First = List->Next;
if (First != List) {
struct LIST_HEADER *Last = List->Prev;
struct LIST_HEADER *At = Head->Next;
First->Prev = Head;
Head->Next = First;
Last->Next = At;
At->Prev = Last;
}
}
static __inline__ VOID
ListAdd(
IN struct LIST_HEADER *New,
IN struct LIST_HEADER *head
)
{
__List_Add(New, head, head->Next);
}
static __inline__ VOID
ListAddTail(
IN struct LIST_HEADER *New,
IN struct LIST_HEADER *head
)
{
__List_Add(New, head->Prev, head);
}
static __inline VOID
RtlInitListhead(
IN _LIST *list
)
{
RTL_INIT_LIST_HEAD(list);
}
/*
For the following list_xxx operations,
caller must guarantee the atomic context.
Otherwise, there will be racing condition.
*/
static __inline u32
RtlIsListEmpty(
IN _LIST *phead
)
{
if (ListEmpty(phead))
return _TRUE;
else
return _FALSE;
}
static __inline VOID
RtlListInsertHead(
IN _LIST *plist,
IN _LIST *phead
)
{
ListAdd(plist, phead);
}
static __inline VOID
RtlListInsertTail(
IN _LIST *plist,
IN _LIST *phead
)
{
ListAddTail(plist, phead);
}
static __inline _LIST
*RtlListGetNext(
IN _LIST *plist
)
{
return plist->Next;
}
static __inline VOID
RtlListDelete(
IN _LIST *plist
)
{
ListDelInit(plist);
}
#define RTL_LIST_CONTAINOR(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#ifndef CONTAINER_OF
#define CONTAINER_OF(ptr, type, member) \
((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member)))
#endif
/*
#define list_entry(ptr, type, member) \
CONTAINER_OF(ptr, type, member)
#define list_first_entry(ptr, type, member) \
list_entry((ptr)->Next, type, member)
#define list_next_entry(pos, member, type) \
list_entry((pos)->member.Next, type, member)
#define list_for_each_entry(pos, head, member, type) \
for (pos = list_first_entry(head, type, member); \
&pos->member != (head); \
pos = list_next_entry(pos, member, type))
#define list_for_each(pos, head) \
for (pos = (head)->Next; pos != (head); pos = pos->Next)
*/
#ifndef BIT
#define BIT(x) ( 1 << (x))
#endif
#ifdef __cplusplus
}
#endif
#endif //_HAL_UTIL_H_

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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef _HAL_VECTOR_TABLE_H_
#define _HAL_VECTOR_TABLE_H_
extern _LONG_CALL_ROM_ VOID
VectorTableInitRtl8195A(
IN u32 StackP
);
extern _LONG_CALL_ROM_ VOID
VectorTableInitForOSRtl8195A(
IN VOID *PortSVC,
IN VOID *PortPendSVH,
IN VOID *PortSysTick
);
extern _LONG_CALL_ROM_ BOOL
VectorIrqRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ BOOL
VectorIrqUnRegisterRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
VectorIrqEnRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
VectorIrqDisRtl8195A(
IN PIRQ_HANDLE pIrqHandle
);
extern _LONG_CALL_ROM_ VOID
HalPeripheralIntrHandle(VOID);
#endif //_HAL_VECTOR_TABLE_H_

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lib/fwlib/ram_lib/usb_otg/include/Rtl8195a_otg_zero.h Normal file
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/*
* Routines to access hardware
*
* Copyright (c) 2013 Realtek Semiconductor Corp.
*
* This module is a confidential and proprietary property of RealTek and
* possession or use of this module requires written permission of RealTek.
*/
#ifndef RTL8195A_OTG_ZERO_H
#define RTL8195A_OTG_ZERO_H
#include "usb_ch9.h"
#include "usb_gadget.h"
struct zero_dev {
//ModifiedByJD spinlock_t lock;
struct usb_gadget *gadget;
struct usb_request *req; /* for control responses */
/* when configured, we have one of two configs:
* - source data (in to host) and sink it (out from host)
* - or loop it back (out from host back in to host)
*/
u8 config;
struct usb_ep *in_ep, *out_ep, *status_ep;//ModifiedByJD
const struct usb_endpoint_descriptor
*in, *out, *status; //ModifiedByJD
/* autoresume timer */
//ModifiedByJD struct timer_list resume;
};
#endif

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//#include "../otg/osk/sys-support.h" //ModifiedByJD
/*
* USB Communications Device Class (CDC) definitions
*
* CDC says how to talk to lots of different types of network adapters,
* notably ethernet adapters and various modems. It's used mostly with
* firmware based USB peripherals.
*/
#define USB_CDC_SUBCLASS_ACM 0x02
#define USB_CDC_SUBCLASS_ETHERNET 0x06
#define USB_CDC_SUBCLASS_WHCM 0x08
#define USB_CDC_SUBCLASS_DMM 0x09
#define USB_CDC_SUBCLASS_MDLM 0x0a
#define USB_CDC_SUBCLASS_OBEX 0x0b
#define USB_CDC_PROTO_NONE 0
#define USB_CDC_ACM_PROTO_AT_V25TER 1
#define USB_CDC_ACM_PROTO_AT_PCCA101 2
#define USB_CDC_ACM_PROTO_AT_PCCA101_WAKE 3
#define USB_CDC_ACM_PROTO_AT_GSM 4
#define USB_CDC_ACM_PROTO_AT_3G 5
#define USB_CDC_ACM_PROTO_AT_CDMA 6
#define USB_CDC_ACM_PROTO_VENDOR 0xff
/*-------------------------------------------------------------------------*/
//#define UPACKED __attribute__ ((packed))
#define UPACKED
/*
* Class-Specific descriptors ... there are a couple dozen of them
*/
#define USB_CDC_HEADER_TYPE 0x00 /* header_desc */
#define USB_CDC_CALL_MANAGEMENT_TYPE 0x01 /* call_mgmt_descriptor */
#define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */
#define USB_CDC_UNION_TYPE 0x06 /* union_desc */
#define USB_CDC_COUNTRY_TYPE 0x07
#define USB_CDC_NETWORK_TERMINAL_TYPE 0x0a /* network_terminal_desc */
#define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */
#define USB_CDC_WHCM_TYPE 0x11
#define USB_CDC_MDLM_TYPE 0x12 /* mdlm_desc */
#define USB_CDC_MDLM_DETAIL_TYPE 0x13 /* mdlm_detail_desc */
#define USB_CDC_DMM_TYPE 0x14
#define USB_CDC_OBEX_TYPE 0x15
//ModifiedByJD (>>>) modify the data type to useable ones.
/* "Header Functional Descriptor" from CDC spec 5.2.3.1 */
struct usb_cdc_header_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u16 bcdCDC;
} UPACKED;
/* "Call Management Descriptor" from CDC spec 5.2.3.2 */
struct usb_cdc_call_mgmt_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bmCapabilities;
#define USB_CDC_CALL_MGMT_CAP_CALL_MGMT 0x01
#define USB_CDC_CALL_MGMT_CAP_DATA_INTF 0x02
u8 bDataInterface;
} UPACKED;
/* "Abstract Control Management Descriptor" from CDC spec 5.2.3.3 */
struct usb_cdc_acm_descriptor {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bmCapabilities;
} UPACKED;
/* "Union Functional Descriptor" from CDC spec 5.2.3.8 */
struct usb_cdc_union_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bMasterInterface0;
u8 bSlaveInterface0;
/* ... and there could be other slave interfaces */
} UPACKED;
/* "Network Channel Terminal Functional Descriptor" from CDC spec 5.2.3.11 */
struct usb_cdc_network_terminal_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 bEntityId;
u8 iName;
u8 bChannelIndex;
u8 bPhysicalInterface;
} UPACKED;
/* "Ethernet Networking Functional Descriptor" from CDC spec 5.2.3.16 */
struct usb_cdc_ether_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u8 iMACAddress;
u32 bmEthernetStatistics;
u16 wMaxSegmentSize;
u16 wNumberMCFilters;
u8 bNumberPowerFilters;
} UPACKED;
/* "MDLM Functional Descriptor" from CDC WMC spec 6.7.2.3 */
struct usb_cdc_mdlm_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
u16 bcdVersion;
u8 bGUID[16];
}UPACKED;
/* "MDLM Detail Functional Descriptor" from CDC WMC spec 6.7.2.4 */
struct usb_cdc_mdlm_detail_desc {
u8 bLength;
u8 bDescriptorType;
u8 bDescriptorSubType;
/* type is associated with mdlm_desc.bGUID */
u8 bGuidDescriptorType;
u8 bDetailData[0];
} UPACKED;
/*-------------------------------------------------------------------------*/
/*
* Class-Specific Control Requests (6.2)
*
* section 3.6.2.1 table 4 has the ACM profile, for modems.
* section 3.8.2 table 10 has the ethernet profile.
*
* Microsoft's RNDIS stack for Ethernet is a vendor-specific CDC ACM variant,
* heavily dependent on the encapsulated (proprietary) command mechanism.
*/
#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00
#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01
#define USB_CDC_REQ_SET_LINE_CODING 0x20
#define USB_CDC_REQ_GET_LINE_CODING 0x21
#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22
#define USB_CDC_REQ_SEND_BREAK 0x23
#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40
#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER 0x41
#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER 0x42
#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43
#define USB_CDC_GET_ETHERNET_STATISTIC 0x44
/* Line Coding Structure from CDC spec 6.2.13 */
struct usb_cdc_line_coding {
u32 dwDTERate;
u8 bCharFormat;
#define USB_CDC_1_STOP_BITS 0
#define USB_CDC_1_5_STOP_BITS 1
#define USB_CDC_2_STOP_BITS 2
u8 bParityType;
#define USB_CDC_NO_PARITY 0
#define USB_CDC_ODD_PARITY 1
#define USB_CDC_EVEN_PARITY 2
#define USB_CDC_MARK_PARITY 3
#define USB_CDC_SPACE_PARITY 4
u8 bDataBits;
} UPACKED;
/* table 62; bits in multicast filter */
#define USB_CDC_PACKET_TYPE_PROMISCUOUS (1 << 0)
#define USB_CDC_PACKET_TYPE_ALL_MULTICAST (1 << 1) /* no filter */
#define USB_CDC_PACKET_TYPE_DIRECTED (1 << 2)
#define USB_CDC_PACKET_TYPE_BROADCAST (1 << 3)
#define USB_CDC_PACKET_TYPE_MULTICAST (1 << 4) /* filtered */
/*-------------------------------------------------------------------------*/
/*
* Class-Specific Notifications (6.3) sent by interrupt transfers
*
* section 3.8.2 table 11 of the CDC spec lists Ethernet notifications
* section 3.6.2.1 table 5 specifies ACM notifications, accepted by RNDIS
* RNDIS also defines its own bit-incompatible notifications
*/
#define USB_CDC_NOTIFY_NETWORK_CONNECTION 0x00
#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE 0x01
#define USB_CDC_NOTIFY_SERIAL_STATE 0x20
#define USB_CDC_NOTIFY_SPEED_CHANGE 0x2a
struct usb_cdc_notification {
u8 bmRequestType;
u8 bNotificationType;
u16 wValue;
u16 wIndex;
u16 wLength;
}UPACKED;
//ModifiedByJD (<<<)

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lib/fwlib/ram_lib/usb_otg/include/dwc_list.h Normal file
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/* $OpenBSD: queue.h,v 1.26 2004/05/04 16:59:32 grange Exp $ */
/* $NetBSD: queue.h,v 1.11 1996/05/16 05:17:14 mycroft Exp $ */
/*
* Copyright (c) 1991, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)queue.h 8.5 (Berkeley) 8/20/94
*/
#ifndef _DWC_LIST_H_
#define _DWC_LIST_H_
#ifdef __cplusplus
extern "C" {
#endif
/** @file
*
* This file defines linked list operations. It is derived from BSD with
* only the MACRO names being prefixed with DWC_. This is because a few of
* these names conflict with those on Linux. For documentation on use, see the
* inline comments in the source code. The original license for this source
* code applies and is preserved in the dwc_list.h source file.
*/
/*
* This file defines five types of data structures: singly-linked lists,
* lists, simple queues, tail queues, and circular queues.
*
*
* A singly-linked list is headed by a single forward pointer. The elements
* are singly linked for minimum space and pointer manipulation overhead at
* the expense of O(n) removal for arbitrary elements. New elements can be
* added to the list after an existing element or at the head of the list.
* Elements being removed from the head of the list should use the explicit
* macro for this purpose for optimum efficiency. A singly-linked list may
* only be traversed in the forward direction. Singly-linked lists are ideal
* for applications with large datasets and few or no removals or for
* implementing a LIFO queue.
*
* A list is headed by a single forward pointer (or an array of forward
* pointers for a hash table header). The elements are doubly linked
* so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before
* or after an existing element or at the head of the list. A list
* may only be traversed in the forward direction.
*
* A simple queue is headed by a pair of pointers, one the head of the
* list and the other to the tail of the list. The elements are singly
* linked to save space, so elements can only be removed from the
* head of the list. New elements can be added to the list before or after
* an existing element, at the head of the list, or at the end of the
* list. A simple queue may only be traversed in the forward direction.
*
* A tail queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or
* after an existing element, at the head of the list, or at the end of
* the list. A tail queue may be traversed in either direction.
*
* A circle queue is headed by a pair of pointers, one to the head of the
* list and the other to the tail of the list. The elements are doubly
* linked so that an arbitrary element can be removed without a need to
* traverse the list. New elements can be added to the list before or after
* an existing element, at the head of the list, or at the end of the list.
* A circle queue may be traversed in either direction, but has a more
* complex end of list detection.
*
* For details on the use of these macros, see the queue(3) manual page.
*/
/*
* Double-linked List.
*/
typedef struct dwc_list_link {
struct dwc_list_link *next;
struct dwc_list_link *prev;
} dwc_list_link_t;
#define DWC_LIST_INIT(link) do { \
(link)->next = (link); \
(link)->prev = (link); \
} while (0)
#define DWC_LIST_FIRST(link) ((link)->next)
#define DWC_LIST_LAST(link) ((link)->prev)
#define DWC_LIST_END(link) (link)
#define DWC_LIST_NEXT(link) ((link)->next)
#define DWC_LIST_PREV(link) ((link)->prev)
#define DWC_LIST_EMPTY(link) \
(DWC_LIST_FIRST(link) == DWC_LIST_END(link))
#define DWC_LIST_ENTRY(link, type, field) \
(type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field))
#if 0
#define DWC_LIST_INSERT_HEAD(list, link) do { \
(link)->next = (list)->next; \
(link)->prev = (list); \
(list)->next->prev = (link); \
(list)->next = (link); \
} while (0)
#define DWC_LIST_INSERT_TAIL(list, link) do { \
(link)->next = (list); \
(link)->prev = (list)->prev; \
(list)->prev->next = (link); \
(list)->prev = (link); \
} while (0)
#else
#define DWC_LIST_INSERT_HEAD(list, link) do { \
dwc_list_link_t *__next__ = (list)->next; \
__next__->prev = (link); \
(link)->next = __next__; \
(link)->prev = (list); \
(list)->next = (link); \
} while (0)
#define DWC_LIST_INSERT_TAIL(list, link) do { \
dwc_list_link_t *__prev__ = (list)->prev; \
(list)->prev = (link); \
(link)->next = (list); \
(link)->prev = __prev__; \
__prev__->next = (link); \
} while (0)
#endif
#if 0
static inline void __list_add(struct list_head *new,
struct list_head *prev,
struct list_head *next)
{
next->prev = new;
new->next = next;
new->prev = prev;
prev->next = new;
}
static inline void list_add(struct list_head *new, struct list_head *head)
{
__list_add(new, head, head->next);
}
static inline void list_add_tail(struct list_head *new, struct list_head *head)
{
__list_add(new, head->prev, head);
}
static inline void __list_del(struct list_head * prev, struct list_head * next)
{
next->prev = prev;
prev->next = next;
}
static inline void list_del(struct list_head *entry)
{
__list_del(entry->prev, entry->next);
entry->next = LIST_POISON1;
entry->prev = LIST_POISON2;
}
#endif
#define DWC_LIST_REMOVE(link) do { \
(link)->next->prev = (link)->prev; \
(link)->prev->next = (link)->next; \
} while (0)
#define DWC_LIST_REMOVE_INIT(link) do { \
DWC_LIST_REMOVE(link); \
DWC_LIST_INIT(link); \
} while (0)
#define DWC_LIST_MOVE_HEAD(list, link) do { \
DWC_LIST_REMOVE(link); \
DWC_LIST_INSERT_HEAD(list, link); \
} while (0)
#define DWC_LIST_MOVE_TAIL(list, link) do { \
DWC_LIST_REMOVE(link); \
DWC_LIST_INSERT_TAIL(list, link); \
} while (0)
#define DWC_LIST_FOREACH(var, list) \
for((var) = DWC_LIST_FIRST(list); \
(var) != DWC_LIST_END(list); \
(var) = DWC_LIST_NEXT(var))
#define DWC_LIST_FOREACH_SAFE(var, var2, list) \
for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \
(var) != DWC_LIST_END(list); \
(var) = (var2), (var2) = DWC_LIST_NEXT(var2))
#define DWC_LIST_FOREACH_REVERSE(var, list) \
for((var) = DWC_LIST_LAST(list); \
(var) != DWC_LIST_END(list); \
(var) = DWC_LIST_PREV(var))
/*
* Singly-linked List definitions.
*/
#define DWC_SLIST_HEAD(name, type) \
struct name { \
struct type *slh_first; /* first element */ \
}
#define DWC_SLIST_HEAD_INITIALIZER(head) \
{ NULL }
#define DWC_SLIST_ENTRY(type) \
struct { \
struct type *sle_next; /* next element */ \
}
/*
* Singly-linked List access methods.
*/
#define DWC_SLIST_FIRST(head) ((head)->slh_first)
#define DWC_SLIST_END(head) NULL
#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head))
#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next)
#define DWC_SLIST_FOREACH(var, head, field) \
for((var) = SLIST_FIRST(head); \
(var) != SLIST_END(head); \
(var) = SLIST_NEXT(var, field))
#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \
for((varp) = &SLIST_FIRST((head)); \
((var) = *(varp)) != SLIST_END(head); \
(varp) = &SLIST_NEXT((var), field))
/*
* Singly-linked List functions.
*/
#define DWC_SLIST_INIT(head) { \
SLIST_FIRST(head) = SLIST_END(head); \
}
#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \
(elm)->field.sle_next = (slistelm)->field.sle_next; \
(slistelm)->field.sle_next = (elm); \
} while (0)
#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \
(elm)->field.sle_next = (head)->slh_first; \
(head)->slh_first = (elm); \
} while (0)
#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \
(elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \
} while (0)
#define DWC_SLIST_REMOVE_HEAD(head, field) do { \
(head)->slh_first = (head)->slh_first->field.sle_next; \
} while (0)
#define DWC_SLIST_REMOVE(head, elm, type, field) do { \
if ((head)->slh_first == (elm)) { \
SLIST_REMOVE_HEAD((head), field); \
} \
else { \
struct type *curelm = (head)->slh_first; \
while( curelm->field.sle_next != (elm) ) \
curelm = curelm->field.sle_next; \
curelm->field.sle_next = \
curelm->field.sle_next->field.sle_next; \
} \
} while (0)
/*
* Simple queue definitions.
*/
#define DWC_SIMPLEQ_HEAD(name, type) \
struct name { \
struct type *sqh_first; /* first element */ \
struct type **sqh_last; /* addr of last next element */ \
}
#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).sqh_first }
#define DWC_SIMPLEQ_ENTRY(type) \
struct { \
struct type *sqe_next; /* next element */ \
}
/*
* Simple queue access methods.
*/
#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first)
#define DWC_SIMPLEQ_END(head) NULL
#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next)
#define DWC_SIMPLEQ_FOREACH(var, head, field) \
for((var) = SIMPLEQ_FIRST(head); \
(var) != SIMPLEQ_END(head); \
(var) = SIMPLEQ_NEXT(var, field))
/*
* Simple queue functions.
*/
#define DWC_SIMPLEQ_INIT(head) do { \
(head)->sqh_first = NULL; \
(head)->sqh_last = &(head)->sqh_first; \
} while (0)
#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \
if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \
(head)->sqh_last = &(elm)->field.sqe_next; \
(head)->sqh_first = (elm); \
} while (0)
#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \
(elm)->field.sqe_next = NULL; \
*(head)->sqh_last = (elm); \
(head)->sqh_last = &(elm)->field.sqe_next; \
} while (0)
#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
(head)->sqh_last = &(elm)->field.sqe_next; \
(listelm)->field.sqe_next = (elm); \
} while (0)
#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \
if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
(head)->sqh_last = &(head)->sqh_first; \
} while (0)
/*
* Tail queue definitions.
*/
#define DWC_TAILQ_HEAD(name, type) \
struct name { \
struct type *tqh_first; /* first element */ \
struct type **tqh_last; /* addr of last next element */ \
}
#define DWC_TAILQ_HEAD_INITIALIZER(head) \
{ NULL, &(head).tqh_first }
#define DWC_TAILQ_ENTRY(type) \
struct { \
struct type *tqe_next; /* next element */ \
struct type **tqe_prev; /* address of previous next element */ \
}
/*
* tail queue access methods
*/
#define DWC_TAILQ_FIRST(head) ((head)->tqh_first)
#define DWC_TAILQ_END(head) NULL
#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
#define DWC_TAILQ_LAST(head, headname) \
(*(((struct headname *)((head)->tqh_last))->tqh_last))
/* XXX */
#define DWC_TAILQ_PREV(elm, headname, field) \
(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
#define DWC_TAILQ_EMPTY(head) \
(TAILQ_FIRST(head) == TAILQ_END(head))
#define DWC_TAILQ_FOREACH(var, head, field) \
for((var) = TAILQ_FIRST(head); \
(var) != TAILQ_END(head); \
(var) = TAILQ_NEXT(var, field))
#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \
for((var) = TAILQ_LAST(head, headname); \
(var) != TAILQ_END(head); \
(var) = TAILQ_PREV(var, headname, field))
/*
* Tail queue functions.
*/
#define DWC_TAILQ_INIT(head) do { \
(head)->tqh_first = NULL; \
(head)->tqh_last = &(head)->tqh_first; \
} while (0)
#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \
if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \
(head)->tqh_first->field.tqe_prev = \
&(elm)->field.tqe_next; \
else \
(head)->tqh_last = &(elm)->field.tqe_next; \
(head)->tqh_first = (elm); \
(elm)->field.tqe_prev = &(head)->tqh_first; \
} while (0)
#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \
(elm)->field.tqe_next = NULL; \
(elm)->field.tqe_prev = (head)->tqh_last; \
*(head)->tqh_last = (elm); \
(head)->tqh_last = &(elm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \
if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
(elm)->field.tqe_next->field.tqe_prev = \
&(elm)->field.tqe_next; \
else \
(head)->tqh_last = &(elm)->field.tqe_next; \
(listelm)->field.tqe_next = (elm); \
(elm)->field.tqe_prev = &(listelm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \
(elm)->field.tqe_prev = (listelm)->field.tqe_prev; \
(elm)->field.tqe_next = (listelm); \
*(listelm)->field.tqe_prev = (elm); \
(listelm)->field.tqe_prev = &(elm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_REMOVE(head, elm, field) do { \
if (((elm)->field.tqe_next) != NULL) \
(elm)->field.tqe_next->field.tqe_prev = \
(elm)->field.tqe_prev; \
else \
(head)->tqh_last = (elm)->field.tqe_prev; \
*(elm)->field.tqe_prev = (elm)->field.tqe_next; \
} while (0)
#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \
if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \
(elm2)->field.tqe_next->field.tqe_prev = \
&(elm2)->field.tqe_next; \
else \
(head)->tqh_last = &(elm2)->field.tqe_next; \
(elm2)->field.tqe_prev = (elm)->field.tqe_prev; \
*(elm2)->field.tqe_prev = (elm2); \
} while (0)
/*
* Circular queue definitions.
*/
#define DWC_CIRCLEQ_HEAD(name, type) \
struct name { \
struct type *cqh_first; /* first element */ \
struct type *cqh_last; /* last element */ \
}
#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \
{ DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
#define DWC_CIRCLEQ_ENTRY(type) \
struct { \
struct type *cqe_next; /* next element */ \
struct type *cqe_prev; /* previous element */ \
}
/*
* Circular queue access methods
*/
#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first)
#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last)
#define DWC_CIRCLEQ_END(head) ((void *)(head))
#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next)
#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev)
#define DWC_CIRCLEQ_EMPTY(head) \
(DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
#define DWC_CIRCLEQ_FOREACH(var, head, field) \
for((var) = DWC_CIRCLEQ_FIRST(head); \
(var) != DWC_CIRCLEQ_END(head); \
(var) = DWC_CIRCLEQ_NEXT(var, field))
#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \
for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \
(var) != DWC_CIRCLEQ_END(head); \
(var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \
for((var) = DWC_CIRCLEQ_LAST(head); \
(var) != DWC_CIRCLEQ_END(head); \
(var) = DWC_CIRCLEQ_PREV(var, field))
/*
* Circular queue functions.
*/
#define DWC_CIRCLEQ_INIT(head) do { \
(head)->cqh_first = DWC_CIRCLEQ_END(head); \
(head)->cqh_last = DWC_CIRCLEQ_END(head); \
} while (0)
#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \
(elm)->field.cqe_next = NULL; \
(elm)->field.cqe_prev = NULL; \
} while (0)
#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \
(elm)->field.cqe_next = (listelm)->field.cqe_next; \
(elm)->field.cqe_prev = (listelm); \
if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
(head)->cqh_last = (elm); \
else \
(listelm)->field.cqe_next->field.cqe_prev = (elm); \
(listelm)->field.cqe_next = (elm); \
} while (0)
#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \
(elm)->field.cqe_next = (listelm); \
(elm)->field.cqe_prev = (listelm)->field.cqe_prev; \
if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
(head)->cqh_first = (elm); \
else \
(listelm)->field.cqe_prev->field.cqe_next = (elm); \
(listelm)->field.cqe_prev = (elm); \
} while (0)
#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \
(elm)->field.cqe_next = (head)->cqh_first; \
(elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \
if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \
(head)->cqh_last = (elm); \
else \
(head)->cqh_first->field.cqe_prev = (elm); \
(head)->cqh_first = (elm); \
} while (0)
#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \
(elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \
(elm)->field.cqe_prev = (head)->cqh_last; \
if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \
(head)->cqh_first = (elm); \
else \
(head)->cqh_last->field.cqe_next = (elm); \
(head)->cqh_last = (elm); \
} while (0)
#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \
if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \
(head)->cqh_last = (elm)->field.cqe_prev; \
else \
(elm)->field.cqe_next->field.cqe_prev = \
(elm)->field.cqe_prev; \
if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \
(head)->cqh_first = (elm)->field.cqe_next; \
else \
(elm)->field.cqe_prev->field.cqe_next = \
(elm)->field.cqe_next; \
} while (0)
#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \
DWC_CIRCLEQ_REMOVE(head, elm, field); \
DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
} while (0)
#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \
if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \
DWC_CIRCLEQ_END(head)) \
(head).cqh_last = (elm2); \
else \
(elm2)->field.cqe_next->field.cqe_prev = (elm2); \
if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \
DWC_CIRCLEQ_END(head)) \
(head).cqh_first = (elm2); \
else \
(elm2)->field.cqe_prev->field.cqe_next = (elm2); \
} while (0)
#ifdef __cplusplus
}
#endif
#endif /* _DWC_LIST_H_ */

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/* ==========================================================================
* $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
* $Revision: #8 $
* $Date: 2013/04/09 $
* $Change: 2201932 $
*
* Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
* "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
* otherwise expressly agreed to in writing between Synopsys and you.
*
* The Software IS NOT an item of Licensed Software or Licensed Product under
* any End User Software License Agreement or Agreement for Licensed Product
* with Synopsys or any supplement thereto. You are permitted to use and
* redistribute this Software in source and binary forms, with or without
* modification, provided that redistributions of source code must retain this
* notice. You may not view, use, disclose, copy or distribute this file or
* any information contained herein except pursuant to this license grant from
* Synopsys. If you do not agree with this notice, including the disclaimer
* below, then you are not authorized to use the Software.
*
* THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
* ========================================================================== */
#ifndef __DWC_OTG_ADP_H__
#define __DWC_OTG_ADP_H__
/**
* @file
*
* This file contains the Attach Detect Protocol interfaces and defines
* (functions) and structures for Linux.
*
*/
#define DWC_OTG_ADP_UNATTACHED 0
#define DWC_OTG_ADP_ATTACHED 1
#define DWC_OTG_ADP_UNKOWN 2
#define HOST_RTIM_THRESHOLD 5
#define DEVICE_RTIM_THRESHOLD 3
typedef struct dwc_otg_adp {
uint32_t adp_started;
uint32_t initial_probe;
int32_t probe_timer_values[2];
uint32_t probe_enabled;
uint32_t sense_enabled;
dwc_timer_t *sense_timer;
uint32_t sense_timer_started;
dwc_timer_t *vbuson_timer;
uint32_t vbuson_timer_started;
uint32_t attached;
uint32_t probe_counter;
uint32_t gpwrdn;
} dwc_otg_adp_t;
/**
* Attach Detect Protocol functions
*/
extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
#endif //__DWC_OTG_ADP_H__

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