mirror of
https://github.com/pvvx/RTL00ConsoleROM.git
synced 2024-11-25 03:24:16 +00:00
255 lines
11 KiB
C
255 lines
11 KiB
C
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/*
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* Routines to access hardware
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*
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* Copyright (c) 2013 Realtek Semiconductor Corp.
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*
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* This module is a confidential and proprietary property of RealTek and
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* possession or use of this module requires written permission of RealTek.
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*/
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#ifndef _HAL_SPIFLASH__
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#define _HAL_SPIFLASH__
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//======================================================
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// Header files
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#define SPIC_CALIBRATION_IN_NVM 1 // if store the SPIC calibration data in the NVM
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#ifndef CONFIG_IMAGE_SEPARATE // Store SPIC Calibration only for seprated image
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#undef SPIC_CALIBRATION_IN_NVM
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#define SPIC_CALIBRATION_IN_NVM 0
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#endif
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//======================================================
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// Definition
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#define HAL_SPI_WRITE32(addr, value32) HAL_WRITE32(SPI_FLASH_CTRL_BASE, addr, value32)
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#define HAL_SPI_WRITE16(addr, value16) HAL_WRITE16(SPI_FLASH_CTRL_BASE, addr, value16)
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#define HAL_SPI_WRITE8(addr, value8) HAL_WRITE8(SPI_FLASH_CTRL_BASE, addr, value8)
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#define HAL_SPI_READ32(addr) HAL_READ32(SPI_FLASH_CTRL_BASE, addr)
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#define HAL_SPI_READ16(addr) HAL_READ16(SPI_FLASH_CTRL_BASE, addr)
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#define HAL_SPI_READ8(addr) HAL_READ8(SPI_FLASH_CTRL_BASE, addr)
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typedef struct _SPIC_PARA_MODE_ {
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u8 Valid:1; // valid
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u8 CpuClk:3; // CPU clock
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u8 BitMode:2; // Bit mode
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u8 Reserved:2; // reserved
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} SPIC_PARA_MODE, *PSPIC_PARA_MODE;
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typedef struct _SPIC_INIT_PARA_ {
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u8 BaudRate;
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u8 RdDummyCyle;
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u8 DelayLine;
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union {
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u8 Rsvd;
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u8 Valid;
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SPIC_PARA_MODE Mode;
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};
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#if defined(E_CUT_ROM_DOMAIN) || (!defined(CONFIG_RELEASE_BUILD_LIBRARIES))
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u8 id[3];
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u8 flashtype;
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#endif
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}SPIC_INIT_PARA, *PSPIC_INIT_PARA;
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enum _SPIC_BIT_MODE_ {
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SpicOneBitMode = 0,
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SpicDualBitMode = 1,
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SpicQuadBitMode = 2,
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};
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//======================================================
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// Flash type used
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#define FLASH_OTHERS 0
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#define FLASH_MXIC 1
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#define FLASH_WINBOND 2
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#define FLASH_MICRON 3
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#define FLASH_MXIC_MX25L4006E 1
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#define FLASH_MXIC_MX25L8073E 0
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// The below parts are based on the flash characteristics
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//====== Flash Command Definition ======
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#if FLASH_MXIC_MX25L4006E
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#define FLASH_CMD_WREN 0x06 //write enable
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#define FLASH_CMD_WRDI 0x04 //write disable
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#define FLASH_CMD_WRSR 0x01 //write status register
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#define FLASH_CMD_RDID 0x9F //read idenfication
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#define FLASH_CMD_RDSR 0x05 //read status register
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#define FLASH_CMD_READ 0x03 //read data
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#define FLASH_CMD_FREAD 0x0B //fast read data
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#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
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#define FLASH_CMD_RES 0xAB //Read Electronic ID
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#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
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#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
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#define FLASH_CMD_SE 0x20 //Sector Erase
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#define FLASH_CMD_BE 0xD8 //Block Erase(or 0x52)
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#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
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#define FLASH_CMD_PP 0x02 //Page Program
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#define FLASH_CMD_DP 0xB9 //Deep Power Down
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#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
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#elif FLASH_MXIC_MX25L8073E
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#define FLASH_CMD_WREN 0x06 //write enable
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#define FLASH_CMD_WRDI 0x04 //write disable
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#define FLASH_CMD_WRSR 0x01 //write status register
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#define FLASH_CMD_RDID 0x9F //read idenfication
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#define FLASH_CMD_RDSR 0x05 //read status register
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#define FLASH_CMD_READ 0x03 //read data
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#define FLASH_CMD_FREAD 0x0B //fast read data
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#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
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#define FLASH_CMD_RES 0xAB //Read Electronic ID
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#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
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#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
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#define FLASH_CMD_SE 0x20 //Sector Erase
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#define FLASH_CMD_BE 0x52 //Block Erase
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#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
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#define FLASH_CMD_PP 0x02 //Page Program
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#define FLASH_CMD_DP 0xB9 //Deep Power Down
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#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
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#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
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#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
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#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
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#define FLASH_CMD_4PP 0x38 //quad page program
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#define FLASH_CMD_FF 0xFF //Release Read Enhanced
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#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
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#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
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#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
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#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
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#define FLASH_CMD_RDSCUR 0x2B // read security register
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#define FLASH_CMD_WRSCUR 0x2F // write security register
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#else
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#define FLASH_CMD_WREN 0x06 //write enable
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#define FLASH_CMD_WRDI 0x04 //write disable
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#define FLASH_CMD_WRSR 0x01 //write status register
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#define FLASH_CMD_RDID 0x9F //read idenfication
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#define FLASH_CMD_RDSR 0x05 //read status register
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#define FLASH_CMD_READ 0x03 //read data
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#define FLASH_CMD_FREAD 0x0B //fast read data
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#define FLASH_CMD_RDSFDP 0x5A //Read SFDP
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#define FLASH_CMD_RES 0xAB //Read Electronic ID
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#define FLASH_CMD_REMS 0x90 //Read Electronic Manufacturer & Device ID
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#define FLASH_CMD_DREAD 0x3B //Double Output Mode command
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#define FLASH_CMD_SE 0x20 //Sector Erase
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#define FLASH_CMD_BE 0x52 //Block Erase
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#define FLASH_CMD_CE 0x60 //Chip Erase(or 0xC7)
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#define FLASH_CMD_PP 0x02 //Page Program
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#define FLASH_CMD_DP 0xB9 //Deep Power Down
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#define FLASH_CMD_RDP 0xAB //Release from Deep Power-Down
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#define FLASH_CMD_2READ 0xBB // 2 x I/O read command
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#define FLASH_CMD_4READ 0xEB // 4 x I/O read command
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#define FLASH_CMD_QREAD 0x6B // 1I / 4O read command
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#define FLASH_CMD_4PP 0x38 //quad page program
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#define FLASH_CMD_FF 0xFF //Release Read Enhanced
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#define FLASH_CMD_REMS2 0xEF // read ID for 2x I/O mode
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#define FLASH_CMD_REMS4 0xDF // read ID for 4x I/O mode
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#define FLASH_CMD_ENSO 0xB1 // enter secured OTP
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#define FLASH_CMD_EXSO 0xC1 // exit secured OTP
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#define FLASH_CMD_RDSCUR 0x2B // read security register
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#define FLASH_CMD_WRSCUR 0x2F // write security register
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#endif //#if FLASH_MXIC_MX25L4006E
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// ============================
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// ===== Flash Parameter Definition =====
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#if FLASH_MXIC_MX25L4006E
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#define FLASH_RD_2IO_EN 0
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#define FLASH_RD_2O_EN 1
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#define FLASH_RD_4IO_EN 0
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#define FLASH_RD_4O_EN 0
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#define FLASH_WR_2IO_EN 0
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#define FLASH_WR_2O_EN 0
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#define FLASH_WR_4IO_EN 0
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#define FLASH_WR_4O_EN 0
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#define FLASH_DM_CYCLE_2O 0x08
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#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_I)
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#define FLASH_VLD_QUAD_CMDS (0)
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#elif FLASH_MXIC_MX25L8073E //This flash model is just for prototype, if you want to use it,
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//the code MUST be rechecked according to the flash spec.
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#define FLASH_RD_2IO_EN 1
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#define FLASH_RD_2O_EN 0
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#define FLASH_RD_4IO_EN 1
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#define FLASH_RD_4O_EN 0
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#define FLASH_WR_2IO_EN 1
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#define FLASH_WR_2O_EN 0
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#define FLASH_WR_4IO_EN 1
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#define FLASH_WR_4O_EN 0
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#define FLASH_DM_CYCLE_2O 0x08
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#define FLASH_DM_CYCLE_2IO 0x04
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#define FLASH_DM_CYCLE_4O 0x08
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#define FLASH_DM_CYCLE_4IO 0x04
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#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
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#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
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#else
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#define FLASH_RD_2IO_EN 1
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#define FLASH_RD_2O_EN 0
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#define FLASH_RD_4IO_EN 1
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#define FLASH_RD_4O_EN 0
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#define FLASH_WR_2IO_EN 1
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#define FLASH_WR_2O_EN 0
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#define FLASH_WR_4IO_EN 1
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#define FLASH_WR_4O_EN 0
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#define FLASH_DM_CYCLE_2O 0x08
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#define FLASH_DM_CYCLE_2IO 0x04
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#define FLASH_DM_CYCLE_4O 0x08
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#define FLASH_DM_CYCLE_4IO 0x04
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#define FLASH_VLD_DUAL_CMDS (BIT_WR_BLOCKING | BIT_RD_DUAL_IO)
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#define FLASH_VLD_QUAD_CMDS (BIT_WR_BLOCKING | BIT_WR_QUAD_II | BIT_RD_QUAD_IO)
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#endif
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#if 0
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//======================================================
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// Function prototype
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BOOLEAN SpicFlashInitRtl8195A(u8 SpicBitMode);
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_LONG_CALL_
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extern VOID SpicLoadInitParaFromClockRtl8195A(u8 CpuClkMode, u8 BaudRate, PSPIC_INIT_PARA pSpicInitPara);
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// spi-flash controller initialization
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_LONG_CALL_
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extern VOID SpicInitRtl8195A(u8 InitBaudRate, u8 SpicBitMode);
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// wait sr[0] = 0, wait transmission done
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_LONG_CALL_
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extern VOID SpicWaitBusyDoneRtl8195A(VOID);
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// wait spi-flash status register[0] = 0
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//_LONG_CALL_
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//extern VOID SpicWaitWipDoneRtl8195A(SPIC_INIT_PARA SpicInitPara);
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#endif
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//======================================================
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// ROM Function prototype
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_LONG_CALL_ VOID SpiFlashAppV02(IN VOID *Data);
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_LONG_CALL_ROM_ VOID SpicInitRtl8195AV02(IN u8 InitBaudRate,IN u8 SpicBitMode);
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_LONG_CALL_ROM_ VOID SpicEraseFlashRtl8195AV02(VOID);
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_LONG_CALL_ROM_ VOID SpicLoadInitParaFromClockRtl8195AV02(IN u8 CpuClkMode,IN u8 BaudRate,IN PSPIC_INIT_PARA pSpicInitPara);
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VOID SpicBlockEraseFlashRtl8195A(IN u32 Address);
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VOID SpicSectorEraseFlashRtl8195A(IN u32 Address);
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VOID SpicDieEraseFlashRtl8195A(IN u32 Address);
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VOID SpicWriteProtectFlashRtl8195A(IN u32 Protect);
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VOID SpicWaitWipDoneRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
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VOID SpicWaitOperationDoneRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
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VOID SpicRxCmdRefinedRtl8195A(IN u8 cmd,IN SPIC_INIT_PARA SpicInitPara);
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u8 SpicGetFlashStatusRefinedRtl8195A(IN SPIC_INIT_PARA SpicInitPara);
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VOID SpicInitRefinedRtl8195A(IN u8 InitBaudRate,IN u8 SpicBitMode);
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u32 SpicWaitWipRtl8195A(VOID);
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u32 SpicOneBitCalibrationRtl8195A(IN u8 SysCpuClk);
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VOID SpicDisableRtl8195A(VOID);
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VOID SpicDeepPowerDownFlashRtl8195A(VOID);
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VOID SpicUserProgramRtl8195A(IN u8 * data, IN SPIC_INIT_PARA SpicInitPara, IN u32 addr, IN u32 * LengthInfo);
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#if SPIC_CALIBRATION_IN_NVM
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VOID SpicNVMCalLoad(u8 BitMode, u8 CpuClk);
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VOID SpicNVMCalLoadAll(void);
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VOID SpicNVMCalStore(u8 BitMode, u8 CpuClk);
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#endif // #if SPIC_CALIBRATION_IN_NVM
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#endif //_HAL_SPIFLASH__
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