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rel_1.6.0 init

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guocheng.kgc 2020-06-18 20:06:52 +08:00 • committed by shengdong.dsd
commit 27b3e2883d
19359 changed files with 8093121 additions and 0 deletions
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185
Living_SDK/platform/mcu/sv6266/aos.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <aos/aos.h>
#include <k_api.h>
#include <aos/kernel.h>
#include <stdio.h>
#include <stdlib.h>
#include "sys/xip.h"
#include "sys/dbgcon.h"
#include "osal.h"
#include "wifinetstack.h"
#include "idmanage/pbuf.h"
#include "security/drv_security.h"
//#include "phy/drv_phy.h"
#include "soc_defs.h"
#include "ieee80211_mgmt.h"
#include "ieee80211_mac.h"
#include "sta_func.h"
#include "wifi_api.h"
#include "netstack.h"
#include "netstack_def.h"
#include "wifi_api.h"
#include "rf/rf_api.h"
#include "wdt/drv_wdt.h"
#include "gpio/drv_gpio.h"
#include "drv_uart.h"
#if defined (VCALL_RHINO)
#if defined (CONFIG_AOS_CLI)
#include "dumpsys.h"
#endif
#endif
#define AOS_START_STACK (2048+512)
ktask_t *g_radio_init;
void uart_rx_isr(void);
extern int write_reg_rf_table_ex(struct st_rf_table * p_table);
extern struct st_rf_table ssv_rf_table;
static void ssvradio_init_task(void *pdata)
{
PBUF_Init();
NETSTACK_RADIO.init();
drv_sec_init();
write_reg_rf_table_ex(&ssv_rf_table);
netstack_init(NULL);
OS_TaskDelete(NULL);
}
extern uint32_t SAVED_PC;
extern uint32_t SAVED_LP;
extern void dump_ir();
static void aos_wdt_process() {
printf("LP:%xh\n", SAVED_LP);
printf("IPC:%xh\n", SAVED_PC);
//ktask_t *cur = krhino_cur_task_get();
ktask_t *task = g_active_task[0];
printf("TP:%xh\n", task);
printf("TN:%s\n", task->task_name);
printf("g_intrpt_nested_level[0]=%d\n", g_intrpt_nested_level[0]);
dump_ir();
#if defined (VCALL_RHINO)
#if defined (CONFIG_AOS_CLI)
dumpsys_task_func(NULL, 0, 1);
#endif
#endif
}
#if defined(CONFIG_ENABLE_WDT)
static void wdt_task(void *pdata)
{
drv_wdt_init();
drv_wdt_enable(SYS_WDT, 6000);
drv_wdt_register_isr(SYS_WDT, 255, aos_wdt_process);
while(1)
{
OS_MsDelay(3*1000);
drv_wdt_kick(SYS_WDT);
}
OS_TaskDelete(NULL);
}
#endif
ktask_t *g_aos_init;
static kinit_t kinit;
static void var_init()
{
kinit.argc = 0;
kinit.argv = NULL;
kinit.cli_enable = 1;
}
extern void hw_start_hal(void);
extern void board_init();
static void system_init(void)
{
board_init();
hw_start_hal();
var_init();
aos_kernel_init(&kinit);
}
static void do_awss_reset();
void isr_gpio_12()
{
drv_gpio_intc_clear(GPIO_12);
//aos_schedule_call(do_awss_reset, NULL);
REG32(0xc0000c00) = '?';
// REG32(0xc0000c00) = '1';
// REG32(0xc0000c00) = '2';
// REG32(0xc0000c00) = '\n';
}
extern void do_awss_active();
void isr_gpio_11()
{
drv_gpio_intc_clear(GPIO_11);
//aos_schedule_call(do_awss_active, NULL);
REG32(0xc0000c00) = '!';
// REG32(0xc0000c00) = '1';
// REG32(0xc0000c00) = '1';
// REG32(0xc0000c00) = '\n';
}
static void app_start(void)
{
xip_init();
xip_enter();
flash_init();
//load_rf_table_from_flash();
//write_reg_rf_table();
//dbgcon_init(UART_SPR_BAUD_921600);
drv_uart_init();
drv_uart_set_fifo(UART_INT_RXFIFO_TRGLVL_1, 0x0);
drv_uart_set_format(921600, UART_WORD_LEN_8, UART_STOP_BIT_1, UART_PARITY_DISABLE);
drv_uart_register_isr(UART_DATA_RDY_IE, uart_rx_isr);
OS_Init();
OS_MemInit();
//OS_PsramInit();
load_rf_table_from_flash();
if(ssv_rf_table.boot_flag == 0xFF)
{
build_default_rf_table(&ssv_rf_table);
load_rf_table_to_mac(&ssv_rf_table);
save_rf_table_to_flash();
dump_rf_table();
}
else
{
load_rf_table_to_mac(&ssv_rf_table);
dump_rf_table();
}
drv_gpio_set_dir(GPIO_12, GPIO_DIR_IN);
drv_gpio_set_dir(GPIO_11, GPIO_DIR_IN);
drv_gpio_set_pull(GPIO_12, GPIO_PULL_UP);
drv_gpio_set_pull(GPIO_11, GPIO_PULL_UP);
drv_gpio_intc_trigger_mode(GPIO_12, GPIO_INTC_FALLING_EDGE);
drv_gpio_intc_trigger_mode(GPIO_11, GPIO_INTC_FALLING_EDGE);
drv_gpio_register_isr(GPIO_12, isr_gpio_12);
drv_gpio_register_isr(GPIO_11, isr_gpio_11);
OS_TaskCreate(ssvradio_init_task, "ssvradio_init", 512, NULL, 1, NULL);
#if defined(CONFIG_ENABLE_WDT)
OS_TaskCreate(wdt_task, "wdt", 256+128, NULL, 15, NULL);
#endif
krhino_task_dyn_create(&g_aos_init, "aos-init", 0, AOS_DEFAULT_APP_PRI, 0, AOS_START_STACK, (task_entry_t)system_init, 1);
OS_StartScheduler();
}
void APP_Init(void)
{
app_start();
}

12
Living_SDK/platform/mcu/sv6266/cfg/cfg.mk Normal file
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NAME := cfg
$(NAME)_CFLAGS +=
$(NAME)_INCLUDES += ../$(SDKDIR)/components/third_party/cJSON
$(NAME)_INCLUDES += ../$(SDKDIR)/components/sys
$(NAME)_INCLUDES += ../$(SDKDIR)/components/drv
$(NAME)_INCLUDES += ../$(SDKDIR)/components/tools/atcmd
$(NAME)_SOURCES :=
$(NAME)_SOURCES += sa_cfg.c
$(NAME)_SOURCES += mac_cfg.c
$(NAME)_SOURCES += user_cfg.c

17
Living_SDK/platform/mcu/sv6266/cfg/mac.txt Normal file
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@ -0,0 +1,17 @@
{
"addr1":"44:57:18:3f:89:a3",
"addr2":"44:57:18:3f:89:a4",
"softap_ssid":"icomm-softap",
"softap_password":"1234567890",
"softap_channel":"1",
"softap_ack_timeout":"10000",
"softap_data_timeout":"20000",
"softap_autoconnect":"1",
"region_code":"0x00009c",
"__comment_taiwan_region_code":"Taiwan:0x00009e",
"watch_dog_count":"5000",
"__comment_watch_dog_count":"unit is ms",
"softap_encryt_mode":"0",
"__comment_softap_encryt_mode":"0: open, 1:WPA2-tkip 2:WPA2:CCMP",
"slink_mode":"0"
}

3
Living_SDK/platform/mcu/sv6266/cfg/mac_c_raw.sh Normal file
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#!/bin/bash
xxd -i mac.txt | head -n -2 | tail -n +2 > mac_raw.h

123
Living_SDK/platform/mcu/sv6266/cfg/mac_cfg.c Normal file
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#include <stdint.h>
#include <cJSON.h>
#include <string.h>
#include "sys/flash.h"
struct wifi_cfg {
char mac_string[4096];
};
#define M_MAC_ADDR_SIZE (36)
const struct wifi_cfg g_wifi_cfg __attribute__((section(".cfg_mac_data"))) = {
.mac_string =
{
#include "mac_raw.h"
, 0x00
}
};
const static char sg_basic_mac[] = {
0x7b, 0x22, 0x61, 0x64, 0x64, 0x72, 0x31, 0x22, 0x3a, 0x22, 0x34, 0x34,
0x3a, 0x35, 0x37, 0x3a, 0x31, 0x38, 0x3a, 0x33, 0x66, 0x3a, 0x37, 0x39,
0x3a, 0x41, 0x31, 0x22, 0x2c, 0x22, 0x61, 0x64, 0x64, 0x72, 0x32, 0x22,
0x3a, 0x22, 0x34, 0x34, 0x3a, 0x35, 0x37, 0x3a, 0x31, 0x38, 0x3a, 0x33,
0x66, 0x3a, 0x37, 0x39, 0x3a, 0x41, 0x32, 0x22, 0x7d, 0x0a, 0x00
};
cJSON *wifi_cfg_init() {
return cJSON_Parse(g_wifi_cfg.mac_string);
}
void macstring_parser(char *macstr, char *addr)
{
u8 len = strlen(macstr);
u8 i, index = 0;
if(len > 17)
{
goto err;
}
addr[index] = 0;
for(i = 0; i < len; i++)
{
if(index > 5)
goto err;
if('0' <= macstr[i] && macstr[i] <= '9')
{
addr[index] = (addr[index] << 4) + macstr[i] - '0';
}
else if('a' <= macstr[i] && macstr[i] <= 'f')
{
addr[index] = (addr[index] << 4) + macstr[i] - 'a' + 10;
}
else if('A' <= macstr[i] && macstr[i] <= 'F')
{
addr[index] = (addr[index] << 4) + macstr[i] - 'A' + 10;
}
else if(macstr[i] == ':')
{
index++;
addr[index] = 0;
}
else
{
goto err;
}
}
return;
err:
printf("Illegal mac string : %s\n", macstr);
}
void wifi_cfg_get_addr1(const cJSON *handle, char addr[6]) {
char *tmpchar = cJSON_GetObjectItem(handle, "addr1")->valuestring;
macstring_parser(tmpchar, addr);
// printf("addr1:%s\n", tmpchar);
}
void wifi_cfg_get_addr2(const cJSON *handle, char addr[6]) {
char *tmpchar = cJSON_GetObjectItem(handle, "addr2")->valuestring;
macstring_parser(tmpchar, addr);
// printf("addr2:%s\n", tmpchar);
}
void wifi_cfg_replace_mem_addr1(const cJSON *handle, char *str) {
cJSON_ReplaceItemInObject(handle, "addr1", cJSON_CreateString(str));
}
void wifi_cfg_replace_mem_addr2(const cJSON *handle, char *str) {
cJSON_ReplaceItemInObject(handle, "addr2", cJSON_CreateString(str));
}
void wifi_cfg_write_cfg(struct cJSON *handle) {
char *buf = sg_basic_mac;
if (handle != NULL) {
buf = cJSON_Print(handle);
}
printf("%s\n", buf);
flash_init();
uint32_t ptr = (uint32_t)((uint32_t)(&g_wifi_cfg) & (0xFFFFFF));
OS_DeclareCritical();
OS_EnterCritical();
flash_sector_erase((unsigned int)ptr);
int i;
for (i = 0; i < FLASH_SECTOR_SIZE; i+=FLASH_PAGE_SIZE) {
flash_page_program(ptr+i, FLASH_PAGE_SIZE, &(buf[i]));
}
OS_ExitCritical();
if (handle != NULL) {
cJSON_free(buf);
}
}
void wifi_cfg_deinit(cJSON *handle) {
cJSON_Delete(handle);
}

11
Living_SDK/platform/mcu/sv6266/cfg/mac_cfg.h Normal file
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@ -0,0 +1,11 @@
#ifndef _MAC_CFG_
#define _MAC_CFG_
void *wifi_cfg_init();
void wifi_cfg_get_addr1(const void *handle, char addr[6]);
void wifi_cfg_get_addr2(const void *handle, char addr[6]);
void wifi_cfg_replace_mem_addr1(const void *handle, char *str);
void wifi_cfg_replace_mem_addr2(const void *handle, char *str);
void wifi_cfg_write_cfg(const void *handle);
void wifi_cfg_deinit(void *handle);
#endif /* end of include guard */

46
Living_SDK/platform/mcu/sv6266/cfg/mac_raw.h Normal file
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@ -0,0 +1,46 @@
0x7b, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x22, 0x61, 0x64, 0x64, 0x72, 0x31,
0x22, 0x3a, 0x22, 0x34, 0x34, 0x3a, 0x35, 0x37, 0x3a, 0x31, 0x38, 0x3a,
0x33, 0x66, 0x3a, 0x38, 0x39, 0x3a, 0x61, 0x33, 0x22, 0x2c, 0x0a, 0x20,
0x20, 0x20, 0x20, 0x22, 0x61, 0x64, 0x64, 0x72, 0x32, 0x22, 0x3a, 0x22,
0x34, 0x34, 0x3a, 0x35, 0x37, 0x3a, 0x31, 0x38, 0x3a, 0x33, 0x66, 0x3a,
0x38, 0x39, 0x3a, 0x61, 0x34, 0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20, 0x20,
0x22, 0x73, 0x6f, 0x66, 0x74, 0x61, 0x70, 0x5f, 0x73, 0x73, 0x69, 0x64,
0x22, 0x3a, 0x22, 0x69, 0x63, 0x6f, 0x6d, 0x6d, 0x2d, 0x73, 0x6f, 0x66,
0x74, 0x61, 0x70, 0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x22, 0x73,
0x6f, 0x66, 0x74, 0x61, 0x70, 0x5f, 0x70, 0x61, 0x73, 0x73, 0x77, 0x6f,
0x72, 0x64, 0x22, 0x3a, 0x22, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
0x38, 0x39, 0x30, 0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x22, 0x73,
0x6f, 0x66, 0x74, 0x61, 0x70, 0x5f, 0x63, 0x68, 0x61, 0x6e, 0x6e, 0x65,
0x6c, 0x22, 0x3a, 0x22, 0x31, 0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20, 0x20,
0x22, 0x73, 0x6f, 0x66, 0x74, 0x61, 0x70, 0x5f, 0x61, 0x63, 0x6b, 0x5f,
0x74, 0x69, 0x6d, 0x65, 0x6f, 0x75, 0x74, 0x22, 0x3a, 0x22, 0x31, 0x30,
0x30, 0x30, 0x30, 0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x22, 0x73,
0x6f, 0x66, 0x74, 0x61, 0x70, 0x5f, 0x64, 0x61, 0x74, 0x61, 0x5f, 0x74,
0x69, 0x6d, 0x65, 0x6f, 0x75, 0x74, 0x22, 0x3a, 0x22, 0x32, 0x30, 0x30,
0x30, 0x30, 0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x22, 0x73, 0x6f,
0x66, 0x74, 0x61, 0x70, 0x5f, 0x61, 0x75, 0x74, 0x6f, 0x63, 0x6f, 0x6e,
0x6e, 0x65, 0x63, 0x74, 0x22, 0x3a, 0x22, 0x31, 0x22, 0x2c, 0x0a, 0x20,
0x20, 0x20, 0x20, 0x22, 0x72, 0x65, 0x67, 0x69, 0x6f, 0x6e, 0x5f, 0x63,
0x6f, 0x64, 0x65, 0x22, 0x3a, 0x22, 0x30, 0x78, 0x30, 0x30, 0x30, 0x30,
0x39, 0x63, 0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x22, 0x5f, 0x5f,
0x63, 0x6f, 0x6d, 0x6d, 0x65, 0x6e, 0x74, 0x5f, 0x74, 0x61, 0x69, 0x77,
0x61, 0x6e, 0x5f, 0x72, 0x65, 0x67, 0x69, 0x6f, 0x6e, 0x5f, 0x63, 0x6f,
0x64, 0x65, 0x22, 0x3a, 0x22, 0x54, 0x61, 0x69, 0x77, 0x61, 0x6e, 0x3a,
0x30, 0x78, 0x30, 0x30, 0x30, 0x30, 0x39, 0x65, 0x22, 0x2c, 0x0a, 0x20,
0x20, 0x20, 0x20, 0x22, 0x77, 0x61, 0x74, 0x63, 0x68, 0x5f, 0x64, 0x6f,
0x67, 0x5f, 0x63, 0x6f, 0x75, 0x6e, 0x74, 0x22, 0x3a, 0x22, 0x35, 0x30,
0x30, 0x30, 0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x22, 0x5f, 0x5f,
0x63, 0x6f, 0x6d, 0x6d, 0x65, 0x6e, 0x74, 0x5f, 0x77, 0x61, 0x74, 0x63,
0x68, 0x5f, 0x64, 0x6f, 0x67, 0x5f, 0x63, 0x6f, 0x75, 0x6e, 0x74, 0x22,
0x3a, 0x22, 0x75, 0x6e, 0x69, 0x74, 0x20, 0x69, 0x73, 0x20, 0x6d, 0x73,
0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x22, 0x73, 0x6f, 0x66, 0x74,
0x61, 0x70, 0x5f, 0x65, 0x6e, 0x63, 0x72, 0x79, 0x74, 0x5f, 0x6d, 0x6f,
0x64, 0x65, 0x22, 0x3a, 0x22, 0x30, 0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20,
0x20, 0x22, 0x5f, 0x5f, 0x63, 0x6f, 0x6d, 0x6d, 0x65, 0x6e, 0x74, 0x5f,
0x73, 0x6f, 0x66, 0x74, 0x61, 0x70, 0x5f, 0x65, 0x6e, 0x63, 0x72, 0x79,
0x74, 0x5f, 0x6d, 0x6f, 0x64, 0x65, 0x22, 0x3a, 0x22, 0x30, 0x3a, 0x20,
0x6f, 0x70, 0x65, 0x6e, 0x2c, 0x20, 0x31, 0x3a, 0x57, 0x50, 0x41, 0x32,
0x2d, 0x74, 0x6b, 0x69, 0x70, 0x20, 0x32, 0x3a, 0x57, 0x50, 0x41, 0x32,
0x3a, 0x43, 0x43, 0x4d, 0x50, 0x22, 0x2c, 0x0a, 0x20, 0x20, 0x20, 0x20,
0x22, 0x73, 0x6c, 0x69, 0x6e, 0x6b, 0x5f, 0x6d, 0x6f, 0x64, 0x65, 0x22,
0x3a, 0x22, 0x30, 0x22, 0x0a, 0x7d, 0x0a

24
Living_SDK/platform/mcu/sv6266/cfg/module.mk Normal file
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@ -0,0 +1,24 @@
LIB_SRC :=
ifeq ($(strip $(SUPPORT_PARTITION_MP_TABLE)), 1)
LIB_SRC += sa_cfg.c
endif
ifeq ($(strip $(SUPPORT_PARTITION_CFG_TABLE)), 1)
LIB_SRC += mac_cfg.c
endif
ifeq ($(strip $(SUPPORT_PARTITION_USER_RAW)), 1)
LIB_SRC += user_cfg.c
endif
LIB_ASRC :=
LIBRARY_NAME := cfg
LOCAL_CFLAGS :=
LOCAL_AFLAGS :=
LOCAL_INC := -Icomponents/bsp -Icomponents/sys
LOCAL_INC += -Icomponents/third_party/cJSON
#LOCAL_INC += -Iprojects/mac_atcmd/src/cli
LOCAL_INC += -Icomponents/tools/atcmd
LOCAL_INC += -Icomponents/third_party/crc16
$(eval $(call build-lib,$(LIBRARY_NAME),$(LIB_SRC),$(LIB_ASRC),$(LOCAL_CFLAGS),$(LOCAL_INC),$(LOCAL_AFLAGS),$(MYDIR)))

112
Living_SDK/platform/mcu/sv6266/cfg/sa_cfg.c Normal file
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@ -0,0 +1,112 @@
#include <stdint.h>
#include "flash.h"
#include "sa_cfg.h"
#include "osal.h"
#include <string.h>
#include <stdio.h>
#include "rf/rf_api.h"
#include "error.h"
#define CFG_ASSERT(cmp) \
do { \
} while(!(cmp))
extern const struct sa_cfg g_sa_cfg __attribute__((section(".sa_mp_data")));
const struct sa_cfg g_sa_cfg __attribute__((section(".sa_mp_data"))) = {
.buf_mp = {0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x97,0x97,0x07,0x09,0x0A,0x07,0x07,0x07,0x07,0x07,0x00,
0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x97,0x97,0x07,0x09,0x0A,0x07,0x07,0x07,0x07,0x07,0x00,
0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x0B,0x97,0x97,0x07,0x09,0x0A,0x07,0x07,0x07,0x07,0x07,0x00,
0x04,0x07,
0x0D,0x0B,0x09,0x07,
0x0D,0x0B,0x09,0x07,
0x0D,0x0B,0x09,0x07,
0x23,0x5A,
0x00,0x00,
0x0D,0x0D,0x0A,0x08,0x4A,0x92,0x64,0x92,0xCC,0xB6,0xDB,0x96,
0x0D,0x0D,0x0A,0x08,0x4A,0x92,0x64,0x92,0xCC,0xB6,0xDB,0x96,
0x0D,0x0D,0x0A,0x08,0x4A,0x92,0x64,0x92,0xCC,0xB6,0xDB,0x96,
0x1E,0x14,0x7C,0x15,0x44,0x16
}
};
void cfg_dump_sa_pre_table() {
int i;
volatile uint8_t *ptr = (volatile uint8_t *)&g_sa_cfg;
ptr -= 256;
for (i = 0; i < 256; i++) {
if ((i!=0) && (i%36 == 0)) {
printf("\n");
}
printf("%02X-", ptr[i]);
}
printf("\n");
}
void cfg_dump_sa_post_table() {
extern uint8_t __lds_sa_mp_data_end;
int i;
volatile uint8_t *ptr = (volatile uint8_t *)&__lds_sa_mp_data_end;
for (i = 0; i < 256; i++) {
if ((i!=0) && (i%36 == 0)) {
printf("\n");
}
printf("%02X-", ptr[i]);
}
printf("\n");
}
void cfg_dump_sa_table(int len) {
int i;
volatile uint8_t *ptr = (volatile uint8_t *)&g_sa_cfg;
for (i = 0; i < len; i++) {
if ((i!=0) && (i%36 == 0)) {
printf("\n");
}
printf("%02X-", ptr[i]);
}
printf("\n");
}
void cfg_sa_write_cfg(struct sa_cfg *new_cfg, uint16_t len) {
CFG_ASSERT(len <= FLASH_SECTOR_SIZE);
flash_init();
uint8_t *buf = OS_MemAlloc(FLASH_SECTOR_SIZE);
memcpy(&(buf[0]), (uint8_t*)new_cfg, len);
memcpy(&(buf[len]), (((uint8_t *)&g_sa_cfg)+len), FLASH_SECTOR_SIZE-len);
uint32_t ptr = (uint32_t)((uint32_t)(&g_sa_cfg) & (0xFFFFFF));
OS_DeclareCritical();
OS_EnterCritical();
flash_sector_erase((unsigned int)ptr);
int i;
for (i = 0; i < FLASH_SECTOR_SIZE; i+=FLASH_PAGE_SIZE) {
flash_page_program(ptr+i, FLASH_PAGE_SIZE, &(buf[i]));
}
OS_ExitCritical();
OS_MemFree(buf);
}
struct st_rf_table ssv_rf_table;
int load_rf_table_from_flash()
{
volatile uint8_t *ptr = (volatile uint8_t *)&g_sa_cfg;
memcpy((uint8_t*)&ssv_rf_table, (uint8_t*)ptr, sizeof(ssv_rf_table));
return 0;
}
int save_rf_table_to_flash()
{
uint8_t *ptr = (uint8_t *)OS_MemAlloc(sizeof(g_sa_cfg));
if (ptr == NULL)
{
printf("[%s] no memory, please check\n", __func__);
return ERROR_MEMORY_FAILED;
}
memset(ptr, 0, sizeof(g_sa_cfg));
memcpy(ptr, &ssv_rf_table, sizeof(ssv_rf_table));
cfg_sa_write_cfg((struct sa_cfg*)ptr, sizeof(g_sa_cfg));
OS_MemFree(ptr);
return 0;
}

16
Living_SDK/platform/mcu/sv6266/cfg/sa_cfg.h Normal file
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#ifndef SA_CFG_H
#define SA_CFG_H
struct sa_cfg {
char buf_mp[4096];
};
void cfg_sa_write_cfg(struct sa_cfg *new_cfg, uint16_t len);
void cfg_dump_sa_table(int len);
#if 1
void cfg_dump_sa_pre_table();
void cfg_dump_sa_post_table();
#endif
extern const struct sa_cfg g_sa_cfg;
#endif /* end of include guard: SA_CFG_H */

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#include <stdint.h>
#include "flash.h"
#include "user_cfg.h"
#include "osal.h"
#include <string.h>
#include <stdio.h>
#include "crc.h"
//#include "atcmd.h"
#include "error.h"
#define USER_CFG_ASSERT(cmp) \
do { \
} while(!(cmp))
const struct user_cfg g_user_cfg __attribute__((section(".user_data")));
void cfg_dump_user_pre_table() {
int i;
volatile uint8_t *ptr = (volatile uint8_t *)&g_user_cfg;
ptr -= 256;
for (i = 0; i < 256; i++) {
if ((i!=0) && (i%36 == 0)) {
printf("\n");
}
printf("%02X-", ptr[i]);
}
printf("\n");
}
void cfg_dump_user_post_table() {
extern uint8_t __lds_user_data_end;
int i;
volatile uint8_t *ptr = (volatile uint8_t *)&__lds_user_data_end;
for (i = 0; i < 256; i++) {
if ((i!=0) && (i%36 == 0)) {
printf("\n");
}
printf("%02X-", ptr[i]);
}
printf("\n");
}
void cfg_dump_user_table(int len) {
int i;
volatile uint8_t *ptr = (volatile uint8_t *)&g_user_cfg;
for (i = 0; i < len; i++) {
if ((i!=0) && (i%36 == 0)) {
printf("\n");
}
printf("%02X-", ptr[i]);
}
printf("\n");
}
void cfg_user_write_cfg(uint8_t *new_user_data, uint16_t len) {
OS_DeclareCritical();
USER_CFG_ASSERT(len <= (FLASH_SECTOR_SIZE<<1));
flash_init();
uint8_t *buf = OS_MemAlloc(FLASH_SECTOR_SIZE<<1);
memcpy(&(buf[0]), (uint8_t*)new_user_data, len);
memcpy(&(buf[len]), (((uint8_t *)&g_user_cfg)+len), (FLASH_SECTOR_SIZE<<1)-len);
uint32_t ptr = (uint32_t)((uint32_t)(&g_user_cfg) & (0xFFFFFF));
OS_EnterCritical();
flash_sector_erase((unsigned int)ptr);
int i;
for (i = 0; i < (FLASH_SECTOR_SIZE<<1); i+=FLASH_PAGE_SIZE) {
flash_page_program(ptr+i, FLASH_PAGE_SIZE, &(buf[i]));
}
OS_ExitCritical();
OS_MemFree(buf);
}
void cfg_user_read_cfg(uint8_t *flash_user_data, uint16_t len) {
OS_DeclareCritical();
USER_CFG_ASSERT(len <= FLASH_SECTOR_SIZE<<1);
flash_init();
uint8_t *buf = OS_MemZalloc(FLASH_SECTOR_SIZE<<1);
// uint32_t ptr = (uint32_t)((uint32_t)(&g_user_cfg) & (0xFFFFFF));
OS_EnterCritical();
// int i;
// for (i = 0; i < FLASH_SECTOR_SIZE<<1; i+=FLASH_PAGE_SIZE) {
// flash_fast_read(ptr+i, FLASH_PAGE_SIZE, &(buf[i]));
// }
memcpy(buf, (void *)&g_user_cfg, len);
OS_ExitCritical();
memcpy(flash_user_data, buf, len);
OS_MemFree(buf);
buf = NULL;
}
#if defined(SUPPORT_UASCENT_USER_CFG)
u8 *user_cfg_buf = NULL;
u8 *user_read_buf = NULL;
u8 user_cfg_flag = 0;
extern uint16_t crc16_ccitt_cal(uint16_t crc_start, unsigned char *buf, int len);
int do_At_User_Flsh(u8 action, u8 write_offset ,u8 *write_buffer)
{
int loop;
uint16_t write_crc,read_crc;
if( action == 1 )//write
{
if( user_cfg_flag == 0 )
{
user_cfg_buf = OS_MemAlloc(RW_TOTAL_SIZE);// 2k size
if(user_cfg_buf == NULL)
{
printf("no memory\n");
return ERROR_MEMORY_FAILED;
}
}
SET_CFG(user_cfg_flag,write_offset);
memcpy(user_cfg_buf + RW_BLOCK_SIZE*write_offset , write_buffer ,RW_BLOCK_SIZE);
if(CHECK_CFG_OK(user_cfg_flag) )
{
write_crc = crc16_ccitt_cal(0, user_cfg_buf, RW_TOTAL_SIZE);
cfg_user_write_cfg(user_cfg_buf,RW_TOTAL_SIZE);
memset(user_cfg_buf,0,RW_TOTAL_SIZE);
cfg_user_read_cfg(user_cfg_buf,RW_TOTAL_SIZE);//read 2K
read_crc = crc16_ccitt_cal(0, user_cfg_buf, RW_TOTAL_SIZE);
if(read_crc != write_crc)
{
printf("Flash crc check Fail\n");
printf("write_crc=%d read_crc=%d\n",write_crc,read_crc);
return ERROR_NOT_IMPLEMENT;
}
printf("Write Flash and check crc OK %d\n",read_crc);
CLEAR_CFG(user_cfg_flag);
OS_MemFree(user_cfg_buf);
user_cfg_buf = NULL;
}
}
else if( action == 0)//read
{
user_read_buf = OS_MemAlloc(RW_TOTAL_SIZE);// 2k size
if(user_read_buf == NULL)
return ERROR_MEMORY_FAILED;
memset(user_read_buf,0,RW_TOTAL_SIZE);
cfg_user_read_cfg(user_read_buf,RW_TOTAL_SIZE);//read 2K
printf("read crc=%d\n",crc16_ccitt_cal(0, user_read_buf, RW_TOTAL_SIZE));
printf("##########################################\n");
for(loop=0; loop<RW_TOTAL_SIZE ; loop++)
printf("%d\t",user_read_buf[loop]);
printf("\n##########################################\n");
OS_MemFree(user_read_buf);
}
return ERROR_SUCCESS;
}
#endif

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Living_SDK/platform/mcu/sv6266/cfg/user_cfg.h Normal file
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#ifndef USER_CFG_H
#define USER_CFG_H
struct user_cfg {
char buf_user[0];
};
void cfg_user_write_cfg(uint8_t *new_user_data, uint16_t len);
void cfg_user_read_cfg(uint8_t *flash_user_data, uint16_t len);
void cfg_dump_user_table(int len);
#if 1
void cfg_dump_user_pre_table();
void cfg_dump_user_post_table();
#endif
extern const struct user_cfg g_user_cfg;
#define SET_CFG(flag,bit) (flag = flag | 1<<bit)
#define CHECK_CFG_OK(flag) ((flag & 0x0F) == 0x0F)
#define CLEAR_CFG(flag) (flag = 0)
#define RW_BLOCK_SIZE (512)
#define RW_TOTAL_SIZE (4*512)
#endif /* end of include guard: USER_CFG_H */

BIN
Living_SDK/platform/mcu/sv6266/do_printf.o Normal file
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Living_SDK/platform/mcu/sv6266/gen_crc_bin.mk Normal file
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EXTRA_POST_BUILD_TARGETS += gen_crc_bin
OTA_BIN_OUTPUT_FILE := $(CLEANED_BUILD_STRING)$(RADIXPOINT)$(BINTYPE_LOWER)$(BIN_OUTPUT_SUFFIX)
$(info hello)
$(info $(OTA_BIN_OUTPUT_FILE))
$(info $(OUTPUT_DIR))
$(info python $(PYTHON))
gen_crc_bin:
cd $(OUTPUT_DIR)/binary/; \
/usr/bin/python ../../../$(SCRIPTS_PATH)/ota_gen_md5_bin.py $(OTA_BIN_OUTPUT_FILE);

32
Living_SDK/platform/mcu/sv6266/hal/adc.c Normal file
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#include "adc/drv_adc.h"
#include "adc/hal_adc.h"
#include "gpio/hal_gpio.h"
#include <hal/soc/adc.h>
#include "errno.h"
int32_t hal_adc_init(adc_dev_t *adc) {
//return (drv_adc_init(adc->port) < 0) ? EIO : 0;
return 0;
}
int32_t hal_adc_value_get(adc_dev_t *adc, void *output, uint32_t timeout) {
uint16_t buf = 0;
int ret;
if (drv_adc_init(adc->port) < 0) {
return EIO;
}
if (drv_adc_read(&buf) < 0) {
drv_adc_deinit(adc->port);
return EIO;
}
*(uint32_t *)output = (uint32_t)((ADC_CONVERT_OFFSET - (buf)*(ADC_CONVERT_SLOPE))/10000);
if (drv_adc_deinit(adc->port) < 0) {
return EIO;
}
return 0;
}
int32_t hal_adc_finalize(adc_dev_t *adc) {
return 0;
}

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Living_SDK/platform/mcu/sv6266/hal/flash_port.c Normal file
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#include "hal/soc/soc.h"
#include "sys/flash.h"
#include "osal.h"
#include "wdt/drv_wdt.h"
#include "errno.h"
#define ROUND_DOWN(a,b) (((a) / (b)) * (b))
#define MIN(a,b) (((a) < (b)) ? (a) : (b))
extern uint32_t FLASH_BEGIN;
extern uint32_t __lds_reserved_start;
const char* bootflag = "bootflag";
/*! \brief hal_ota_switch_to_new_fw update bootflag.
*
* check the ota image & update bootflag.
*
* \return 0: success, otherwise: failed.
*/
int flash_sw_bank()
{
#define M_OTA_HEADER_CHECK (6)
uint32_t reserved_addr = (uint32_t)(&__lds_reserved_start) - (uint32_t)(&FLASH_BEGIN);
uint32_t ota_data_check[M_OTA_HEADER_CHECK];
OS_DeclareCritical();
uint32_t offset = 4;
int32_t ret = 0;
hal_partition_t pno = HAL_PARTITION_OTA_TEMP;
ret = hal_flash_read(pno, &offset, ota_data_check, sizeof(uint32_t)*M_OTA_HEADER_CHECK);
if (ret == EIO) {
return -1;
}
if (ota_data_check[0] != XTAL) {
return -2;
}
if (ota_data_check[1] != SYS_BUS_SPEED) {
return -3;
}
if (ota_data_check[2] != XIP_BIT) {
return -4;
}
if (ota_data_check[5] != SETTING_PSRAM_HEAP_BASE) {
return -7;
}
OS_EnterCritical();
#if defined(CONFIG_ENABLE_WDT)
drv_wdt_kick(SYS_WDT);
#endif
flash_sector_erase(reserved_addr);
#if defined(CONFIG_ENABLE_WDT)
drv_wdt_kick(SYS_WDT);
#endif
flash_page_program(reserved_addr, strlen(bootflag), bootflag);
#if defined(CONFIG_ENABLE_WDT)
drv_wdt_kick(SYS_WDT);
#endif
OS_ExitCritical();
REG32(0xc0000000) = 0x00200000;
return 0;
}
static int FLASH_update(uint32_t dst_addr, const void *data, uint32_t size)
{
uint32_t remaining = size;
uint32_t fl_addr;
uint32_t fl_offset;
uint32_t len;
uint8_t* src_addr = (uint8_t *) data;
OS_DeclareCritical();
do
{
fl_addr = ROUND_DOWN(dst_addr, FLASH_PAGE_SIZE);
fl_offset = dst_addr - fl_addr;
len = MIN(FLASH_PAGE_SIZE - fl_offset, remaining);
#if defined(CONFIG_ENABLE_WDT)
drv_wdt_kick(SYS_WDT);
#endif
// if(fl_offset)
// {
OS_EnterCritical();
flash_page_program(dst_addr, len, src_addr);
OS_ExitCritical();
// }
// else
// {
// OS_EnterCritical();
// flash_page_program(fl_addr, len, src_addr);
// OS_ExitCritical();
// }
{
dst_addr += len;
src_addr += len;
remaining -= len;
}
} while(remaining > 0);
return 0;
}
int FLASH_read_at(uint32_t address, uint8_t* pData, uint32_t len_bytes)
{
uint8_t *src = (uint8_t*)(address+0x30000000);
while(len_bytes--)
{
*pData++ = *src++;
}
return 0;
}
int FLASH_unlock_erase(uint32_t address, uint32_t len_bytes)
{
uint32_t i = 0;
uint32_t erase_count = (len_bytes + FLASH_SECTOR_SIZE - 1) / FLASH_SECTOR_SIZE;
OS_DeclareCritical();
for (i = 0; i < erase_count; i++)
{
OS_EnterCritical();
#if defined(CONFIG_ENABLE_WDT)
drv_wdt_kick(SYS_WDT);
#endif
flash_sector_erase(address + (i * FLASH_SECTOR_SIZE));
OS_ExitCritical();
}
return 0;
}
extern const hal_logic_partition_t hal_partitions[];
hal_logic_partition_t *hal_flash_get_info(hal_partition_t pno)
{
hal_logic_partition_t *logic_partition;
logic_partition = (hal_logic_partition_t *)&hal_partitions[ pno ];
return logic_partition;
}
int32_t hal_flash_write(hal_partition_t pno, uint32_t* poff, const void* buf ,uint32_t buf_size)
{
uint32_t start_addr;
hal_logic_partition_t *partition_info;
hal_partition_t real_pno;
real_pno = pno;
partition_info = hal_flash_get_info( real_pno );
start_addr = partition_info->partition_start_addr + *poff;
if (buf_size == 0) {
return 0;
}
if ((poff == NULL) || (buf == NULL) || ((*poff + buf_size) > partition_info->partition_length)) {
printf("partition overwrite \r\n");
// overwrite.
return EIO;
}
if (0 != FLASH_update(start_addr, buf, buf_size)) {
printf("FLASH_update failed!\n");
}
*poff += buf_size;
return 0;
}
int32_t hal_flash_read(hal_partition_t pno, uint32_t* poff, void* buf, uint32_t buf_size)
{
uint32_t start_addr;
hal_logic_partition_t *partition_info;
hal_partition_t real_pno;
real_pno = pno;
partition_info = hal_flash_get_info( real_pno );
if (buf_size == 0) {
return 0;
}
if ((poff == NULL) || (buf == NULL) || ((*poff + buf_size) > partition_info->partition_length)) {
return EIO;
}
start_addr = partition_info->partition_start_addr + *poff;
FLASH_read_at(start_addr, buf, buf_size);
*poff += buf_size;
return 0;
}
int32_t hal_flash_erase(hal_partition_t pno, uint32_t off_set,
uint32_t size)
{
uint32_t start_addr;
hal_logic_partition_t *partition_info;
hal_partition_t real_pno;
real_pno = pno;
partition_info = hal_flash_get_info( real_pno );
if ((size + off_set) > partition_info->partition_length) {
return EIO;
}
start_addr = ROUND_DOWN((partition_info->partition_start_addr + off_set), FLASH_PAGE_SIZE);
FLASH_unlock_erase(start_addr, size);
return 0;
}
int32_t hal_flash_enable_secure(hal_partition_t partition, uint32_t off_set, uint32_t size)
{
return 0;
}
int32_t hal_flash_dis_secure(hal_partition_t partition, uint32_t off_set, uint32_t size)
{
return 0;
}

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Living_SDK/platform/mcu/sv6266/hal/gpio.c Executable file
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#include "gpio/hal_gpio.h"
#include <hal/soc/gpio.h>
#include "errno.h"
static struct GPIO_STATUS_T
{
gpio_irq_trigger_t intc_mode;
void *intc_data;
void (*callback)(void *pdata);
}gpio_status[22];
int32_t hal_gpio_init(gpio_dev_t *gpio)
{
if(gpio->port <0 || gpio->port > 22)
return -EIO;
//set gpio mode
hal_gpio_set_mode(gpio->port,PIN_MODE_GPIO);
//set input
if(gpio->config == IRQ_MODE || \
gpio->config == INPUT_PULL_UP || \
gpio->config == INPUT_PULL_DOWN || \
gpio->config == INPUT_PULL_DOWN )
{
hal_gpio_set_dir(gpio->port,GPIO_DIR_IN);
}
//set output
if(gpio->config == OUTPUT_PUSH_PULL || \
gpio->config == OUTPUT_OPEN_DRAIN_NO_PULL ||\
gpio->config == OUTPUT_OPEN_DRAIN_PULL_UP)
{
hal_gpio_set_dir(gpio->port,GPIO_DIR_OUT);
}
switch(gpio->config)
{
case ANALOG_MODE:
hal_gpio_set_dir(gpio->port,GPIO_DIR_IN_OUT);
break;
case INPUT_PULL_UP:
hal_gpio_set_pull(gpio->port,GPIO_PULL_UP);
break;
case INPUT_PULL_DOWN:
hal_gpio_set_pull(gpio->port,GPIO_PULL_DOWN);
break;
case INPUT_HIGH_IMPEDANCE:
hal_gpio_set_pull(gpio->port,GPIO_PULL_NONE);
break;
case OUTPUT_PUSH_PULL:
case IRQ_MODE:
hal_gpio_set_pull(gpio->port,GPIO_PULL_UP);
break;
case OUTPUT_OPEN_DRAIN_NO_PULL:
case OUTPUT_OPEN_DRAIN_PULL_UP:
hal_gpio_set_pull(gpio->port,GPIO_PULL_NONE);
break;
default:
return EIO;
}
return 0;
}
int32_t hal_gpio_output_high(gpio_dev_t *gpio)
{
hal_gpio_set_logic(gpio->port,GPIO_LOGIC_HIGH);
return 0;
}
int32_t hal_gpio_output_low(gpio_dev_t *gpio)
{
hal_gpio_set_logic(gpio->port,GPIO_LOGIC_LOW);
return 0;
}
int32_t hal_gpio_output_toggle(gpio_dev_t *gpio)
{
gpio_dir_t pre_dir;
gpio_logic_t val;
//save pre dir
pre_dir = hal_gpio_get_dir(gpio->port);
//change mode ,read logice
hal_gpio_set_dir(gpio->port, GPIO_DIR_IN_OUT);
val = hal_gpio_get_logic(gpio->port);
//out reverse val
hal_gpio_set_logic(gpio->port,!val);
hal_gpio_set_dir(gpio->port, pre_dir);
return 0;
}
int32_t hal_gpio_input_get(gpio_dev_t *gpio, uint32_t *value)
{
*value = hal_gpio_get_logic(gpio->port);
return 0;
}
static void gpio_intc_cb(uint32_t irq_num)
{
if(gpio_status[irq_num].callback != NULL)
{
gpio_status[irq_num].callback(gpio_status[irq_num].intc_data);
// hal_gpio_intc_clear_counter((gpio_pin_t)irq_num);
}
}
int32_t hal_gpio_enable_irq(gpio_dev_t *gpio, gpio_irq_trigger_t trigger,
gpio_irq_handler_t handler, void *arg)
{
gpio_status[gpio->port].intc_mode = trigger;
gpio_status[gpio->port].intc_data = arg;
gpio_status[gpio->port].callback = handler;
if(trigger == IRQ_TRIGGER_RISING_EDGE)
hal_gpio_intc_trigger_mode(gpio->port,GPIO_INTC_RISING_EDGE);
else if(trigger == IRQ_TRIGGER_FALLING_EDGE)
hal_gpio_intc_trigger_mode(gpio->port,GPIO_INTC_FALLING_EDGE);
else
{
hal_gpio_intc_trigger_mode(gpio->port,GPIO_INTC_RISING_EDGE);
hal_gpio_intc_trigger_mode(gpio->port,GPIO_INTC_FALLING_EDGE);
}
hal_gpio_register_isr(gpio->port,gpio_intc_cb);
return 0;
}
int32_t hal_gpio_disable_irq(gpio_dev_t *gpio)
{
intc_group31_irq_disable(gpio->port);
return 0;
}
int32_t hal_gpio_clear_irq(gpio_dev_t *gpio)
{
hal_gpio_intc_clear_counter(gpio->port);
return 0;
}
int32_t hal_gpio_finalize(gpio_dev_t *gpio)
{
hal_gpio_set_mode(gpio->port,PIN_MODE_ZSTATE);
if(gpio_status[gpio->port].callback != NULL)
{
gpio_status[gpio->port].callback = NULL;
hal_gpio_register_isr(gpio->port,NULL);
}
return 0;
}

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Living_SDK/platform/mcu/sv6266/hal/hw.c Normal file
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#include <hal/soc/soc.h>
#include <hal/wifi.h>
#include <hal/ota.h>
#include "soc_defs.h"
#include "osal.h"
void hal_reboot(void)
{
OS_DeclareCritical();
OS_EnterCritical();
drv_wdt_init();
drv_wdt_enable(1, 100);
while(1);
OS_ExitCritical();
}
extern hal_wifi_module_t sim_aos_wifi_icomm;
void hw_start_hal(void)
{
printf("start-----------hal\n");
hal_wifi_register_module(&sim_aos_wifi_icomm);
sim_aos_wifi_icomm.init(&sim_aos_wifi_icomm);
}

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Living_SDK/platform/mcu/sv6266/hal/i2c.c Executable file
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#include "soc_types.h"
#include "i2cmst/drv_i2cmst.h"
#include <hal/soc/i2c.h>
#include "errno.h"
#include <stdio.h>
#include "osal.h"
#ifndef DEV_ERROR(no)
#define DEV_ERROR(no) (no==0?0:EIO)
#endif
static void set_spi_timeout(uint32_t timeout)
{
drv_i2c_mst_retry_wait_time_us(timeout * 1000);
drv_i2c_mst_retry_count(1);
}
int32_t hal_i2c_init(i2c_dev_t *i2c)
{
int ret;
if(i2c->config.freq < 100 || i2c->config.freq > 1000 * 1000)
{
printf("Error set freq:I2C Clock (100 - 1000 KHz)\n");
return EIO;
}
if(i2c->config.mode == I2C_MODE_SLAVE)
{
printf("Error set mode.Unsuport SLAVE mode\n");
return EIO;
}
ret = drv_i2c_mst_init(i2c->config.freq);
return DEV_ERROR(ret);
}
int32_t hal_i2c_master_send(i2c_dev_t *i2c, uint16_t dev_addr, const uint8_t *data,
uint16_t size, uint32_t timeout)
{
int ret;
set_spi_timeout(timeout);
ret = drv_i2c_mst_write(dev_addr, data, size, 1, 1);
return DEV_ERROR(ret);
}
int32_t hal_i2c_master_recv(i2c_dev_t *i2c, uint16_t dev_addr, uint8_t *data,
uint16_t size, uint32_t timeout)
{
int ret;
set_spi_timeout(timeout);
ret = drv_i2c_mst_read(dev_addr, data, size, 1, 1);
return DEV_ERROR(ret);
}
int32_t hal_i2c_slave_send(i2c_dev_t *i2c, const uint8_t *data, uint16_t size, uint32_t timeout)
{
return EIO;
}
int32_t hal_i2c_slave_recv(i2c_dev_t *i2c, uint8_t *data, uint16_t size, uint32_t timeout)
{
return EIO;
}
int32_t hal_i2c_mem_write(i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_addr,
uint16_t mem_addr_size, const uint8_t *data, uint16_t size,
uint32_t timeout)
{
uint8_t *write_buffer;
int ret = EIO;
write_buffer = OS_MemAlloc(mem_addr_size + size);
if(write_buffer == NULL)
{
return EIO;
}
memcpy(write_buffer, mem_addr, mem_addr_size);
memcpy(write_buffer + mem_addr_size, data, size);
set_spi_timeout(timeout);
ret = drv_i2c_mst_write(dev_addr, write_buffer, mem_addr_size + size, 1, 1);
OS_MemFree(write_buffer);
return DEV_ERROR(ret);
}
int32_t hal_i2c_mem_read(i2c_dev_t *i2c, uint16_t dev_addr, uint16_t mem_addr,
uint16_t mem_addr_size, uint8_t *data, uint16_t size,
uint32_t timeout)
{
int ret;
set_spi_timeout(timeout);
if(0 != drv_i2c_mst_write(dev_addr, (uint8_t *)&mem_addr, mem_addr_size, 1, 1)){
printf("write fail!\n");
return EIO;
}
if(0 != drv_i2c_mst_read(dev_addr, data, size, 1, 1)){
printf("read fail!\n");
return EIO;
}
return 0;
}
int32_t hal_i2c_finalize(i2c_dev_t *i2c)
{
int ret;
ret = drv_i2c_mst_deinit();
return DEV_ERROR(ret);
}

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Living_SDK/platform/mcu/sv6266/hal/ota_port.c Normal file
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#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <unistd.h>
#include <aos/log.h>
#include <errno.h>
#include <hal/ota.h>
#include <hal/soc/soc.h>
#include "sys/flash.h"
#include "osal.h"
#include <CheckSumUtils.h>
#include "wdt/drv_wdt.h"
#include "common.h"
static int sv6266_ota_set_boot(hal_ota_module_t *m, void *something)
{
ota_finish_param_t *param = (ota_finish_param_t *)something;
if (param == NULL) {
return kGeneralErr;
}
if (param->result_type == OTA_FINISH) {
//CRC16_Final( &contex, (uint16_t *)&ota_info.ota_crc );
printf("switch to new fw\n");
memset(&ota_info, 0 , sizeof ota_info);
if (hal_ota_switch_to_new_fw() != 0) {
return kGeneralErr;
}
}
return kNoErr;
}

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#include "pwm/hal_pwm.h"
#include "gpio/hal_gpio.h"
#include <hal/soc/pwm.h>
#include "errno.h"
int32_t hal_pwm_init(pwm_dev_t *pwm) {
if ((pwm->port >= PWM_0) && (pwm->port <= PWM_4)) {
_hal_pwm_init(pwm->port);
hal_pwm_config(pwm->port, pwm->config.freq, (int32_t)pwm->config.duty_cycle, 0);
return 0;
}
return EIO;
}
int32_t hal_pwm_start(pwm_dev_t *pwm) {
if ((pwm->port >= PWM_0) && (pwm->port <= PWM_4)) {
hal_pwm_config(pwm->port, pwm->config.freq, (int32_t)(pwm->config.duty_cycle*4096), 0);
hal_pwm_enable(pwm->port);
return 0;
}
return EIO;
}
int32_t hal_pwm_stop(pwm_dev_t *pwm) {
if ((pwm->port >= PWM_0) && (pwm->port <= PWM_4)) {
hal_pwm_disable(pwm->port);
return 0;
}
return EIO;
}
int32_t hal_pwm_finalize(pwm_dev_t *pwm) {
if ((pwm->port >= PWM_0) && (pwm->port <= PWM_4)) {
hal_pwm_disable(pwm->port);
return 0;
}
return EIO;
}

1525
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106
Living_SDK/platform/mcu/sv6266/hal/spi.c Executable file
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#include "soc_types.h"
#include "spimst/drv_spimst.h"
#include <hal/soc/spi.h>
#include "errno.h"
#include "osal.h"
#ifndef DEV_ERROR(no)
#define DEV_ERROR(no) (no==0?0:EIO)
#endif
static int32_t spi_trans_data(const uint8_t *read_data,\
const uint8_t *write_data,uint16_t size)
{
uint8_t *duty_data = NULL;
uint8_t *spi_rx_data = read_data;
uint8_t *spi_tx_data = write_data;
int ret;
uint16_t index = 0;
uint16_t trans_size;
if(read_data == NULL || write_data == NULL)//alloc duty data
{
duty_data = OS_MemAlloc(size);
if(duty_data == NULL)
return EIO;
}
else if(read_data == NULL && write_data != NULL)//tx only
{
spi_rx_data = duty_data;
spi_tx_data = write_data;
}
else if(read_data != NULL && write_data == NULL)//rx ready
{
spi_rx_data = read_data;
spi_tx_data = duty_data;
}
do{
if(size > 1024)
{
trans_size = 1024;
size -= 1024;
}
else
{
trans_size = size;
size = 0;
}
ret = drv_spi_mst_dma_trx(spi_tx_data+index, spi_rx_data+index, trans_size);
if(ret != 0)
break;
}while(size != 0);
if(duty_data != NULL)
OS_MemFree(duty_data);
return DEV_ERROR(ret);
}
int32_t hal_spi_init(spi_dev_t *spi)
{
int ret;
if(spi->config.freq < 1 * 1000 * 1000 ||
spi->config.freq > 40 * 1000 * 1000)
{
return EIO;
}
if(spi->config.mode > 3)
{
return EIO;
}
ret = drv_spi_mst_init(spi->config.freq,
(spi->config.mode & 0x2) ,
(spi->config.mode & 0x1));
return DEV_ERROR(ret);;
}
int32_t hal_spi_send(spi_dev_t *spi, const uint8_t *data, uint16_t size, uint32_t timeout)
{
return spi_trans_data(NULL, data, size);
}
int32_t hal_spi_recv(spi_dev_t *spi, uint8_t *data, uint16_t size, uint32_t timeout)
{
return spi_trans_data(data, NULL, size);
}
int32_t hal_spi_send_recv(spi_dev_t *spi, uint8_t *tx_data, uint8_t *rx_data,
uint16_t size, uint32_t timeout)
{
return spi_trans_data(rx_data, tx_data, size);
}
int32_t hal_spi_finalize(spi_dev_t *spi)
{
int ret;
ret = drv_spi_mst_deinit();
return DEV_ERROR(ret);
}

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Living_SDK/platform/mcu/sv6266/hal/timer.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <stdlib.h>
#include "hal/soc/soc.h"
#include "drv/tmr/hal_tm.h"
timer_dev_t *sv6266_timer_handler_ptr[6];
/*
* The range of timers for sv6266 is [0, 65535], ID 0/1/2 is a microsecond timer, and 5/6/7 is a millisecond timer.
*/
const static TM_ID_E TM_ID_MAP[] = {
1, ///< ID for microsecond timer 0.
2, ///< ID for microsecond timer 1.
3, ///< ID for microsecond timer 2.
5, ///< ID for millisecond timer 3.
6, ///< ID for millisecond timer 4.
7 ///< ID for millisecond timer 5.
};
static void sv6266_timer_handler_0(void *arg)
{
drv_tmr_clear_interrupt_status((TM_ID_E) TM_ID_MAP[sv6266_timer_handler_ptr[0]->port]);
sv6266_timer_handler_ptr[0]->config.cb(sv6266_timer_handler_ptr[0]->config.arg);
}
static void sv6266_timer_handler_1(void *arg)
{
drv_tmr_clear_interrupt_status((TM_ID_E) TM_ID_MAP[sv6266_timer_handler_ptr[1]->port]);
sv6266_timer_handler_ptr[1]->config.cb(sv6266_timer_handler_ptr[1]->config.arg);
}
static void sv6266_timer_handler_2(void *arg)
{
drv_tmr_clear_interrupt_status((TM_ID_E) TM_ID_MAP[sv6266_timer_handler_ptr[2]->port]);
sv6266_timer_handler_ptr[2]->config.cb(sv6266_timer_handler_ptr[2]->config.arg);
}
static void sv6266_timer_handler_3(void *arg)
{
drv_tmr_clear_interrupt_status((TM_ID_E) TM_ID_MAP[sv6266_timer_handler_ptr[3]->port]);
sv6266_timer_handler_ptr[3]->config.cb(sv6266_timer_handler_ptr[3]->config.arg);
}
static void sv6266_timer_handler_4(void *arg)
{
drv_tmr_clear_interrupt_status((TM_ID_E) TM_ID_MAP[sv6266_timer_handler_ptr[4]->port]);
sv6266_timer_handler_ptr[4]->config.cb(sv6266_timer_handler_ptr[4]->config.arg);
}
static void sv6266_timer_handler_5(void *arg)
{
drv_tmr_clear_interrupt_status((TM_ID_E) TM_ID_MAP[sv6266_timer_handler_ptr[5]->port]);
sv6266_timer_handler_ptr[5]->config.cb(sv6266_timer_handler_ptr[5]->config.arg);
}
static isr_func sv6266_timer_handler[] = {
sv6266_timer_handler_0,sv6266_timer_handler_1,sv6266_timer_handler_2,
sv6266_timer_handler_3,sv6266_timer_handler_4,sv6266_timer_handler_5
};
int32_t hal_timer_init(timer_dev_t *tim)
{
int32_t retval;
if (tim == NULL) {
return -1;
}
if (tim->port < 0 || tim->port > 5) {
return -1;
}
retval = hal_tm_init((TM_ID_E) TM_ID_MAP[tim->port]);
if (retval != 0) {
return retval;
}
retval = hal_tm_sw_rst((TM_ID_E) TM_ID_MAP[tim->port]);
if (retval != 0) {
return retval;
}
if (tim->config.cb != NULL) {
sv6266_timer_handler_ptr[tim->port] = tim;
retval = hal_tm_register_irq_handler((TM_ID_E) TM_ID_MAP[tim->port], (isr_func) sv6266_timer_handler[tim->port]);
}
return retval;
}
int32_t hal_timer_start (timer_dev_t *tim)
{
TM_MODE_E reload = 0;
if (tim == NULL) {
return -1;
}
if (tim->port < 0 || tim->port > 5) {
return -1;
}
if (tim->config.reload_mode == TIMER_RELOAD_AUTO) {
reload = (TM_MODE_E) 1;
} else {
reload = (TM_MODE_E) 0;
}
return hal_tm_enable ((TM_ID_E) TM_ID_MAP[tim->port], reload, tim->config.period);
}
int32_t hal_timer_para_chg(timer_dev_t *tim, timer_config_t para)
{
TM_MODE_E reload = 0;
if (tim == NULL) {
return -1;
}
if (tim->port < 0 || tim->port > 5) {
return -1;
}
if (tim->config.reload_mode == TIMER_RELOAD_AUTO) {
reload = (TM_MODE_E) 1;
} else {
reload = (TM_MODE_E) 0;
}
hal_tm_disable ((TM_ID_E) TM_ID_MAP[tim->port]);
tim->config.period = para.period;
tim->config.reload_mode = para.reload_mode;
tim->config.arg = para.arg;
if (tim->port < 0 || tim->port > 5) {
return -1;
}
return hal_tm_enable ((TM_ID_E) TM_ID_MAP[tim->port], reload, tim->config.period);
}
void hal_timer_stop(timer_dev_t *tim)
{
if (tim == NULL) {
return;
}
if (tim->port < 0 || tim->port > 5) {
return;
}
hal_tm_disable ((TM_ID_E) TM_ID_MAP[tim->port]);
}
int32_t hal_timer_finalize(timer_dev_t *tim)
{
if (tim == NULL) {
return -1;
}
if (tim->port < 0 || tim->port > 5) {
return -1;
}
return hal_tm_deinit ((TM_ID_E) TM_ID_MAP[tim->port]);
}

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Living_SDK/platform/mcu/sv6266/hal/uart.c Normal file
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#include "hal/soc/soc.h"
#include "sys/dbgcon.h"
#include "drv_uart.h"
#include "osal.h"
uart_dev_t uart_0 = {
.port = 0,
.config = {
.baud_rate = 921600,
.data_width = DATA_WIDTH_8BIT,
.parity = NO_PARITY,
},
.priv = NULL,
};
#define M_UART_BUFFER_SIZE (256)
#define RINGBUF_SIZE (M_UART_BUFFER_SIZE)
#define RINGBUF_IDX_WRAP (RINGBUF_SIZE -1)
#define RINGBUF_VIDX_WRAP (RINGBUF_SIZE*2 -1)
typedef struct ringbuf {
uint32_t vidx_w;
uint32_t vidx_r;
uint8_t data[RINGBUF_SIZE];
} ringbuf_st;
ringbuf_st g_uart_rx_ringbuf = {
0,
0,
{0},
};
void uart_rx_isr(void)
{
uint32_t vidx_w_full;
uint32_t vidx_w;
uint32_t idx_w;
vidx_w_full = (g_uart_rx_ringbuf.vidx_r + RINGBUF_SIZE) & RINGBUF_VIDX_WRAP;
vidx_w = g_uart_rx_ringbuf.vidx_w;
// # when data ready ,move all data in fifo into ringbuf.
// ## if full, drop all and alert.
// TODO: rx error
while(hal_uart_get_line_status () & 1) {
if(vidx_w != vidx_w_full) {
// ### write data
idx_w = vidx_w & RINGBUF_IDX_WRAP;
g_uart_rx_ringbuf.data[idx_w] = (uint8_t)hal_uart_direct_read_byte();
//hal_uart_read_fifo (&g_uart_rx_ringbuf.data[idx_w], 1, UART_NON_BLOCKING);
//if(g_uart_rx_ringbuf.data[idx_w] == 0x00) {
// printf("\n!RX Error %d!\n", drv_uart_get_line_status());
//}
// ### update pointer
vidx_w = (vidx_w+1) & RINGBUF_VIDX_WRAP;
}
else {
// force output to screen,
putc(hal_uart_direct_read_byte());
putc('!');
}
}
// # update idx back to structure
g_uart_rx_ringbuf.vidx_w = vidx_w;
//OS_EventSet(cli_rx_evt);
}
static uint32_t uart_read(uint32_t char_2read, uint8_t* dst) {
uint32_t vidx_r;
uint32_t vidx_r_empty;
uint32_t idx_r ;
uint32_t cnt = 0;
vidx_r = g_uart_rx_ringbuf.vidx_r;
vidx_r_empty = g_uart_rx_ringbuf.vidx_w;
while((vidx_r != vidx_r_empty) && (cnt != char_2read)) {
idx_r = vidx_r & RINGBUF_IDX_WRAP;
//
if(dst) {
dst[cnt] = g_uart_rx_ringbuf.data[idx_r];
}
cnt++;
//
vidx_r = (vidx_r+1) & RINGBUF_VIDX_WRAP;
}
g_uart_rx_ringbuf.vidx_r = vidx_r;
return cnt;
}
int32_t hal_uart_init(uart_dev_t *uart)
{
return 0;
}
int32_t hal_uart_finalize(uart_dev_t *uart)
{
return 0;
}
int32_t hal_uart_send(uart_dev_t *uart, const void *data, uint32_t size, uint32_t timeout)
{
uint8_t* pTmp = (uint8_t*)data;
for (int i = 0; i < size; i++) {
dbgcon_tx(*pTmp++);
}
return size;
}
int32_t hal_uart_recv_II(uart_dev_t *uart, void *data, uint32_t expect_size,
uint32_t *recv_size, uint32_t timeout)
{
uint8_t* pTmp = (uint8_t*)data;
uint32_t size = 0;
while (expect_size > 0)
{
int one_time_size = 0;
size += (one_time_size = uart_read(expect_size, pTmp));
expect_size -= one_time_size;
pTmp += one_time_size;
if (!timeout)
{
break;
}
if (expect_size > 0)
{
OS_MsDelay(1);
timeout--;
}
}
if (recv_size != NULL) {
*recv_size = size;
}
return 0;
}
int32_t hal_uart_recv(uart_dev_t *uart, void *data, uint32_t expect_size, uint32_t timeout) {
// aMH: duplicate function to reduce stack size.
uint8_t* pTmp = (uint8_t*)data;
uint32_t size = 0;
while (expect_size > 0)
{
int one_time_size = 0;
size += (one_time_size = uart_read(expect_size, pTmp));
expect_size -= one_time_size;
pTmp += one_time_size;
if (!timeout)
{
break;
}
if (expect_size > 0)
{
OS_MsDelay(1);
timeout--;
}
}
return 0;
}

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Living_SDK/platform/mcu/sv6266/hal/wdg.c Normal file
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#include "hal/soc/soc.h"
#include "drv/wdt/hal_wdt.h"
int32_t
hal_wdg_init (
wdg_dev_t *wdg
)
{
int32_t retval;
hal_wdt_init ();
retval = hal_wdt_register_isr ((WDT_ID_E) wdg->port, 0, NULL);
return hal_wdt_enable ((WDT_ID_E) wdg->port, wdg->config.timeout);
}
void
hal_wdg_reload (
wdg_dev_t *wdg
)
{
int32_t retval;
retval = hal_wdt_kick ((WDT_ID_E) wdg->port);
}
int32_t
hal_wdg_finalize (
wdg_dev_t *wdg
)
{
return hal_wdt_disable ((WDT_ID_E) wdg->port);
}

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Living_SDK/platform/mcu/sv6266/hal/wifi_port.c Executable file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hal/base.h>
#include <hal/wifi.h>
#include <aos/network.h>
//#include "common.h"
#include "wifi_api.h"
#include "softap_func.h"
#if defined(PORTING_DEBUG)
#define LOG_AOS_HAL(...) \
printf(__VA_ARGS__)
#else
#define LOG_AOS_HAL(...)
#endif
#define ERROR_SUCCESS 0
#define ERROR_INVALID_PARAMETER -1
#define ERROR_NOT_IMPLEMENT -2
extern int mac_80211_tx_rawpkt(u8 *data, int len);
extern void mgmt_register_cbfn(void *fn);
static int get_ip_stat(hal_wifi_module_t *m, hal_wifi_ip_stat_t *out_net_para, hal_wifi_type_t wifi_type);
hal_wifi_module_t sim_aos_wifi_icomm;
monitor_data_cb_t gallpktfn = NULL;
monitor_data_cb_t gmgmtpktfn = NULL;
static bool factory_mode = false;
void inet_ntoa_icomm(ip4_addr_t *ipaddr, char *ipstr)
{
char *tmpstr;
tmpstr = ip4addr_ntoa(ipaddr);
memcpy(ipstr, tmpstr, strlen(tmpstr));
}
char hextochar(u8 hex)
{
if(0x0 <= hex && hex <= 0x9)
return '0' + hex;
else if(0xa <= hex && hex <= 0xf)
return 'A' + hex - 0xa;
else
return 0;
}
void machextostr(u8 *mac, char *str)
{
int i;
for(i = 0; i < 6; i++){
str[2 * i] = hextochar(mac[i] >> 4);
str[2 * i + 1] = hextochar(mac[i] & 0xF);
}
}
//struct AP_LIST_ADV{
// char ssid[32]; /* The SSID of an access point. */
// char ap_power; /* Signal strength, min:0, max:100 */
// char bssid[6]; /* The BSSID of an access point. */
// char channel; /* The RF frequency, 1-13 */
// uint8_t security; /* Security type, @ref wlan_sec_type_t */
//} AP_LIST_ADV;
void wifi_cbfu(WIFI_RSP *msg)
{
u8 dhcpen;
u8 mac[6];
u8 ipv4[4];
uip_ip4addr_t ipaddr, submask, gateway, dnsserver;
s8 ret;
char ipstr[16];
hal_wifi_ip_stat_t ipstat;
if(msg->wifistatus == 1) {
LOG_AOS_HAL("wifi connected:%d\n", msg->id);
get_ip_stat(&sim_aos_wifi_icomm, &ipstat, STATION);
sim_aos_wifi_icomm.ev_cb->stat_chg(&sim_aos_wifi_icomm, NOTIFY_STATION_UP, NULL);
sim_aos_wifi_icomm.ev_cb->ip_got(&sim_aos_wifi_icomm, &ipstat, NULL);
}
else {
LOG_AOS_HAL("wifi disconnected:%d\n", msg->id);
sim_aos_wifi_icomm.ev_cb->stat_chg(&sim_aos_wifi_icomm, NOTIFY_STATION_DOWN, NULL);
}
}
void scan_cp()
{
int i;
TAG_AP_INFO *tmpap;
hal_wifi_scan_result_t aplist;
if (sim_aos_wifi_icomm.ev_cb == NULL)
return;
if (sim_aos_wifi_icomm.ev_cb->scan_compeleted == NULL)
return;
aplist.ap_num = get_ap_lsit_total_num();
aplist.ap_list = OS_MemAlloc(aplist.ap_num * sizeof(ap_list_t));
memset(aplist.ap_list, 0, aplist.ap_num * sizeof(ap_list_t));
tmpap = OS_MemAlloc(aplist.ap_num * sizeof(TAG_AP_INFO));
get_ap_list(tmpap, (u8 *)&aplist.ap_num);
for(i = 0; i < aplist.ap_num; i++){
aplist.ap_list[i].ap_power = -tmpap[i].rssi;
memcpy(aplist.ap_list[i].ssid, tmpap[i].name, tmpap[i].name_len);
}
OS_MemFree(tmpap);
sim_aos_wifi_icomm.ev_cb->scan_compeleted(&sim_aos_wifi_icomm, (hal_wifi_scan_result_t*)&aplist, NULL);
OS_MemFree(aplist.ap_list);
}
u8 enctypeicommtoali(u8 type, u8 subtype)
{
u8 enctype;
if(type == NONE)
enctype = SECURITY_TYPE_NONE;
else if(type == WEP)
enctype = SECURITY_TYPE_WEP;
else if(type == WPA){
if(subtype == TKIP_CCMP || subtype == CCMP)
enctype = SECURITY_TYPE_WPA_AES;
else
enctype = SECURITY_TYPE_WPA_TKIP;
}
else{
if(subtype == TKIP_CCMP)
enctype = SECURITY_TYPE_WPA2_MIXED;
else if(subtype == CCMP)
enctype = SECURITY_TYPE_WPA2_AES;
else
enctype = SECURITY_TYPE_WPA2_TKIP;
}
return enctype;
}
u8 enctypealitoicomm(u8 type)
{
u8 enctype = SECURITY_TYPE_NONE;
if(type == SECURITY_TYPE_NONE)
enctype = NET80211_CRYPT_NONE;
else if(type == SECURITY_TYPE_WEP)
enctype = NET80211_CRYPT_WEP;
else if(type == SECURITY_TYPE_WPA_TKIP || type == SECURITY_TYPE_WPA2_TKIP){
enctype = NET80211_CRYPT_TKIP;
}
else if(type == SECURITY_TYPE_WPA_AES || type == SECURITY_TYPE_WPA2_AES){
enctype = NET80211_CRYPT_CCMP;
}
else if(type == SECURITY_TYPE_WPA2_MIXED){
enctype = NET80211_CRYPT_CCMP_TKIP;
}
return enctype;
}
void scan_cpadv()
{
int i;
TAG_AP_INFO *tmpap;
hal_wifi_scan_result_adv_t aplist;
if (sim_aos_wifi_icomm.ev_cb == NULL)
return;
if (sim_aos_wifi_icomm.ev_cb->scan_compeleted == NULL)
return;
aplist.ap_num = get_ap_lsit_total_num();
aplist.ap_list = OS_MemAlloc(aplist.ap_num * sizeof(ap_list_adv_t));
memset(aplist.ap_list, 0, aplist.ap_num * sizeof(ap_list_adv_t));
tmpap = OS_MemAlloc(aplist.ap_num * sizeof(TAG_AP_INFO));
get_ap_list(tmpap, (u8 *)&aplist.ap_num);
for(i = 0; i < aplist.ap_num; i++){
aplist.ap_list[i].ap_power = -tmpap[i].rssi;
memcpy(aplist.ap_list[i].ssid, tmpap[i].name, tmpap[i].name_len);
memcpy(aplist.ap_list[i].bssid, tmpap[i].mac, 6);
aplist.ap_list[i].channel = tmpap[i].channel;
aplist.ap_list[i].security = enctypeicommtoali(tmpap[i].security_type, tmpap[i].security_subType);
}
OS_MemFree(tmpap);
sim_aos_wifi_icomm.ev_cb->scan_adv_compeleted(&sim_aos_wifi_icomm, (hal_wifi_scan_result_adv_t*)&aplist, NULL);
OS_MemFree(aplist.ap_list);
}
//Need to modify this api for new parameter
void alisniffercb(packetinfo *pinfo)
{
monitor_data_cb_t fn = NULL;
hal_wifi_link_info_t info;
OS_DeclareCritical();
OS_EnterCritical();
fn = gallpktfn;
OS_ExitCritical();
if(fn != NULL)
{
info.rssi = -(pinfo->rssi);
fn(pinfo->data, pinfo->len, &info);
}
}
void alimgmtcb(packetinfo *pinfo)
{
hal_wifi_link_info_t info;
if(gmgmtpktfn != NULL)
{
info.rssi = -(pinfo->rssi);
gmgmtpktfn(pinfo->data, pinfo->len, &info);
}
}
static int wifi_init(hal_wifi_module_t *m)
{
LOG_AOS_HAL("wifi_init!!\n");
set_country_code(CN);
return 0;
};
static void wifi_get_mac_addr(hal_wifi_module_t *m, uint8_t *mac)
{
//LOG_AOS_HAL("wifi_get_mac_addr!!\n");
get_local_mac(0, mac, 6);
};
static int wifi_start(hal_wifi_module_t *m, hal_wifi_init_type_t *init_para)
{
u32 ipaddr, submask, gateway, dnsserver;
int ret;
if(init_para == NULL)
return -1;
if(init_para->wifi_mode == SOFT_AP){
DUT_wifi_start(DUT_AP);
}
else if(init_para->wifi_mode == STATION){
DUT_wifi_start(DUT_STA);
if(init_para->dhcp_mode == DHCP_SERVER){
return -1;
}else if(init_para->dhcp_mode == DHCP_DISABLE){
ipaddr = ipaddr_addr(init_para->local_ip_addr);
submask = ipaddr_addr(init_para->net_mask);
gateway = ipaddr_addr(init_para->gateway_ip_addr);
dnsserver = ipaddr_addr(init_para->dns_server_ip_addr);
set_if_config_2(0, 0, ipaddr, submask, gateway, dnsserver);
}
ret = set_wifi_config_3(0, (u8 *)init_para->wifi_ssid, strlen(init_para->wifi_ssid), (u8 *)init_para->wifi_key, strlen(init_para->wifi_key), NULL, 6, NET80211_CRYPT_UNKNOWN);
if(ret == 0) {
wifi_connect_2(0, wifi_cbfu);
}else {
wifi_connect_active_2((u8 *)init_para->wifi_ssid, strlen(init_para->wifi_ssid), (u8 *)init_para->wifi_key, strlen(init_para->wifi_key), wifi_cbfu, NET80211_CRYPT_UNKNOWN);
}
}
return 0;
}
int wifi_start_adv(hal_wifi_module_t *m, hal_wifi_init_type_adv_t *init_para_adv)
{
u32 ipaddr, submask, gateway, dnsserver;
int ret, i;
u8 apnum;
TAG_AP_INFO *tmpap;
LOG_AOS_HAL("wifi_start_adv!!\n");
if(init_para_adv == NULL)
return -1;
DUT_wifi_start(DUT_STA);
if(init_para_adv->dhcp_mode == DHCP_SERVER){
return -1;
}else if(init_para_adv->dhcp_mode == DHCP_DISABLE){
ipaddr = ipaddr_addr(init_para_adv->local_ip_addr);
submask = ipaddr_addr(init_para_adv->net_mask);
gateway = ipaddr_addr(init_para_adv->gateway_ip_addr);
dnsserver = ipaddr_addr(init_para_adv->dns_server_ip_addr);
set_if_config_2(0, 0, ipaddr, submask, gateway, dnsserver);
}
apnum = get_ap_lsit_total_num();
tmpap = OS_MemAlloc(apnum * sizeof(TAG_AP_INFO));
get_ap_list(tmpap, &apnum);
for(i = 0; i < apnum; i++)
{
if(memcmp(init_para_adv->ap_info.ssid, tmpap[i].name, tmpap[i].name_len) != 0){
continue;
}
if(memcmp(init_para_adv->ap_info.bssid, tmpap[i].mac, 6) != 0){
continue;
}
if(init_para_adv->ap_info.channel != 0 && init_para_adv->ap_info.channel != tmpap[i].channel){
continue;
}
if(init_para_adv->ap_info.security != enctypeicommtoali(tmpap[i].security_type, tmpap[i].security_subType)){
continue;
}
break;
}
OS_MemFree(tmpap);
if(i != apnum) {
set_wifi_config_3(0, (u8 *)init_para_adv->ap_info.ssid, strlen(init_para_adv->ap_info.ssid), (u8 *)init_para_adv->key, init_para_adv->key_len,
(u8 *)init_para_adv->ap_info.bssid, 6, enctypealitoicomm(init_para_adv->ap_info.security));
wifi_connect_2(0, wifi_cbfu);
}else {
/* wifi_connect_active_3 (init_para_adv->ap_info.ssid, strlen(init_para_adv->ap_info.ssid), init_para_adv->key, init_para_adv->key_len,
enctypealitoicomm(init_para_adv->ap_info.security), init_para_adv->ap_info.channel, init_para_adv->ap_info.bssid, wifirspcbfunc);*/
}
return 0;
}
typedef union icomm_ip4addr {
u8 u8[4];
u16 u16[2];
u32 u32;
} icomm_ip4addr;
static int get_ip_stat(hal_wifi_module_t *m, hal_wifi_ip_stat_t *out_net_para, hal_wifi_type_t wifi_type)
{
u8 dhcpen;
unsigned char mac[6];
ip4_addr_t ipaddr, submask, gateway, dnsserver;
char *ipstr;
if(out_net_para == NULL)
return -1;
if(wifi_type == STATION)
{
get_if_config_2(IF0_NAME, &out_net_para->dhcp, &ipaddr.addr, &submask.addr, &gateway.addr, &dnsserver.addr, mac, 6);
}
else if(wifi_type == SOFT_AP)
{
get_if_config_2(IF1_NAME, &out_net_para->dhcp, &ipaddr.addr, &submask.addr, &gateway.addr, &dnsserver.addr, mac, 6);
}
else
return -1;
machextostr(mac, out_net_para->mac);
inet_ntoa_icomm(&ipaddr, out_net_para->ip);
inet_ntoa_icomm(&submask, out_net_para->mask);
inet_ntoa_icomm(&gateway, out_net_para->gate);
inet_ntoa_icomm(&dnsserver, out_net_para->dns);
return 0;
}
static int get_link_stat(hal_wifi_module_t *m, hal_wifi_link_stat_t *out_stat)
{
u8 ssidlen = 32, keylen = 64;
u8 key[64];
LOG_AOS_HAL("get_link_stat!!\n");
if(out_stat == NULL)
return -1;
out_stat->is_connected = get_wifi_status_2(0);
if(out_stat->is_connected == 1)
{
//Need to use new channel information.
get_connectap_info(0, out_stat->ssid, &ssidlen, out_stat->bssid, 6, (u8 *)&(out_stat->wifi_strength), (u8 *)&(out_stat->channel));
out_stat->wifi_strength = -out_stat->wifi_strength;
}
return 0;
}
static void start_scan(hal_wifi_module_t *m)
{
if(factory_mode)
return;
LOG_AOS_HAL("start_scan!!\n");
scan_AP_custom(NULL, scan_cp, 0x1fff, 0x0, 250);
}
void start_scan_adv(hal_wifi_module_t *m)
{
if(factory_mode)
return;
LOG_AOS_HAL("start_scan_adv!!\n");
scan_AP_custom(NULL, scan_cpadv, 0x1fff, 0x0, 250);
}
static int power_off(hal_wifi_module_t *m)
{
if(factory_mode);
return 0;
LOG_AOS_HAL("power_off!!\n");
DUT_wifi_start(DUT_NONE);
return 0;
}
static int power_on(hal_wifi_module_t *m)
{
//Enable DUT_STA mode to make sure scan function can work
if(factory_mode)
return 0;
LOG_AOS_HAL("power_on!!\n");
DUT_wifi_start(DUT_STA);
return 0;
}
static int suspend(hal_wifi_module_t *m)
{
if(factory_mode)
return 0;
LOG_AOS_HAL("suspend!!\n");
DUT_wifi_start(DUT_NONE);
return 0;
}
static int suspend_station(hal_wifi_module_t *m)
{
if(factory_mode)
return 0;
LOG_AOS_HAL("suspend_station!!\n");
if(get_operation_mode() == DUT_STA)
DUT_wifi_start(DUT_NONE);
return 0;
}
static int suspend_soft_ap(hal_wifi_module_t *m)
{
LOG_AOS_HAL("suspend_soft_ap!!\n");
if(get_operation_mode() == DUT_AP)
DUT_wifi_start(DUT_NONE);
return 0;
}
static int set_channel(hal_wifi_module_t *m, int ch)
{
int ret;
if(factory_mode)
return 0;
//LOG_AOS_HAL("set_channel!!\n");
ret = wifi_set_channel(ch, 1);
return ret;
}
static void start_monitor(hal_wifi_module_t *m)
{
if(factory_mode)
return 0;
LOG_AOS_HAL("start_monitor!!\n");
DUT_wifi_start(DUT_SNIFFER);
}
static void stop_monitor(hal_wifi_module_t *m)
{
if(factory_mode)
return 0;
LOG_AOS_HAL("stop_monitor!!\n");
if(get_operation_mode() == DUT_SNIFFER)
DUT_wifi_start(DUT_NONE);
}
static void register_monitor_cb(hal_wifi_module_t *m, monitor_data_cb_t fn)
{
LOG_AOS_HAL("register_monitor_cb!! fn = %xh\n", fn);
OS_DeclareCritical();
OS_EnterCritical();
gallpktfn = fn;
OS_ExitCritical();
set_sniffer_config(RECV_MGMT | RECV_DATA, alisniffercb);
}
static void register_wlan_mgnt_monitor_cb(hal_wifi_module_t *m, monitor_data_cb_t fn)
{
LOG_AOS_HAL("register_wlan_mgnt_monitor_cb!!\n");
gmgmtpktfn = fn;
mgmt_register_cbfn(alimgmtcb);
}
static int wlan_send_80211_raw_frame(hal_wifi_module_t *m, uint8_t *buf, int len)
{
int ret;
if(factory_mode)
return 0;
//LOG_AOS_HAL("wlan_send_80211_raw_frame!!\n");
if(buf == NULL || len <= 0)
return -1;
ret = mac_80211_tx_rawpkt(buf, len);
return ret; // len-4=exclude FCS
}
extern void ssv_dbg_cmd_parse(char *pwbuf, int blen, int argc, char **argv);
static struct cli_command andycmd = {
.name = "SSV",
.help = "SSV dbgcmd",
.function = ssv_dbg_cmd_parse
};
void start_debug_mode(hal_wifi_module_t *m)
{
factory_mode = true;
DUT_wifi_start(DUT_NONE);
aos_cli_register_command(&andycmd);
//rwnx_go_debug_mode();
}
void stop_debug_mode(hal_wifi_module_t *m)
{
}
static int start_ap_mode(hal_wifi_module_t *m, const char *ssid, const char *passwd, int interval, int hide)
{
int ret;
hal_wifi_ip_stat_t ipstat;
SOFTAP_CUSTOM_CONFIG isoftap_custom_config;
memset(&isoftap_custom_config,0,sizeof(isoftap_custom_config));
DUT_wifi_start(DUT_NONE);
OS_MsDelay(100);
isoftap_custom_config.start_ip = 0xc0a80002; //192.168.0.2
isoftap_custom_config.end_ip = 0xc0a80005; //192.168.0.5
isoftap_custom_config.gw = 0xc0a80001; //192.168.0.1
isoftap_custom_config.subnet = 0xffffff00; //255.255.255.0
isoftap_custom_config.max_sta_num = 4;
isoftap_custom_config.beacon_interval = interval;
if(strlen(passwd) >= 8)
{
isoftap_custom_config.encryt_mode = 2;
isoftap_custom_config.keylen = strlen(passwd);
memcpy(&isoftap_custom_config.key[0],passwd,isoftap_custom_config.keylen);
}
else
{
isoftap_custom_config.encryt_mode = 0;
// isoftap_custom_config.keylen = 0;
isoftap_custom_config.keylen = strlen("12345678");
memcpy(&isoftap_custom_config.key[0],"12345678",isoftap_custom_config.keylen);
}
isoftap_custom_config.channel= 1;
isoftap_custom_config.ssid_length = strlen(ssid);
memcpy(&isoftap_custom_config.ssid[0],ssid,isoftap_custom_config.ssid_length);
ret = softap_set_custom_conf(&isoftap_custom_config);
DUT_wifi_start(DUT_AP);
netif_set_default(netif_find(IF1_NAME));
return 0;
}
static int stop_ap_mode(hal_wifi_module_t *m)
{
LOG_AOS_HAL("stop_ap_mode\n");
DUT_wifi_start(DUT_NONE);
netif_set_default(netif_find(IF0_NAME));
return 0;
}
hal_wifi_module_t sim_aos_wifi_icomm = {
.base.name = "sim_aos_wifi_icomm",
.init = wifi_init,
.get_mac_addr = wifi_get_mac_addr,
.start = wifi_start,
.start_adv = wifi_start_adv,
.get_ip_stat = get_ip_stat,
.get_link_stat = get_link_stat,
.start_scan = start_scan,
.start_scan_adv = start_scan_adv,
.power_off = power_off,
.power_on = power_on,
.suspend = suspend,
.suspend_station = suspend_station,
.suspend_soft_ap = suspend_soft_ap,
.set_channel = set_channel,
.start_monitor = start_monitor,
.stop_monitor = stop_monitor,
.register_monitor_cb = register_monitor_cb,
.register_wlan_mgnt_monitor_cb = register_wlan_mgnt_monitor_cb,
.wlan_send_80211_raw_frame = wlan_send_80211_raw_frame,
.start_ap = start_ap_mode,
.stop_ap = stop_ap_mode,
.start_debug_mode = start_debug_mode,
.stop_debug_mode = stop_debug_mode
};

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#pragma pack(push,1)

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/*
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#ifndef __ARCH_CC_H__
#define __ARCH_CC_H__
#if 1
/* Include some files for defining library routines */
//#include <ssv_ex_lib.h>
//#include <log.h>
#include "soc_types.h"
#include "lwip_os_porting.h"
#include <stdio.h>
//#include <ssv_lib.h>
#else
/* Declare fuction prototypes for assert/diag/error - leads to some warnings,
* but good to test if no includes are missing. */
int LOG_PRINTF(const char *format, ...);
void abort(void);
struct _iobuf;
typedef struct _iobuf FILE;
int fflush(FILE *stream);
#endif
#ifdef CONFIG_OS_RHINO
//#define FFLUSH(x)
//#define hal_print printf
#endif
/** @todo fix some warnings: don't use #pragma if compiling with cygwin gcc */
#ifndef __GNUC__
#include <limits.h>
#pragma warning (disable: 4244) /* disable conversion warning (implicit integer promotion!) */
#pragma warning (disable: 4127) /* conditional expression is constant */
#pragma warning (disable: 4996) /* 'strncpy' was declared deprecated */
#pragma warning (disable: 4103) /* structure packing changed by including file */
#endif
//#define LWIP_PROVIDE_ERRNO
#define ERRNO
#define LWIP_MAILBOX_QUEUE
/* Define platform endianness (might already be defined) */
#ifndef BYTE_ORDER
#define BYTE_ORDER LITTLE_ENDIAN
#endif /* BYTE_ORDER */
/* Define generic types used in lwIP */
#if 0
typedef unsigned char u8_t;
typedef signed char s8_t;
typedef unsigned short u16_t;
typedef signed short s16_t;
typedef unsigned long u32_t;
typedef signed long s32_t;
#endif
typedef size_t mem_ptr_t;
typedef u32_t sys_prot_t;
/* Define (sn)printf formatters for these lwIP types */
#define X8_F "02x"
#define U16_F "u"
#define S16_F "d"
#define X16_F "x"
#define U32_F "u"
#define S32_F "d"
#define X32_F "x"
#define SZT_F U32_F
/* Compiler hints for packing structures */
#ifndef PACK_STRUCT_STRUCT
#define PACK_STRUCT_STRUCT
#endif
#ifndef PACK_STRUCT_USE_INCLUDES
#define PACK_STRUCT_USE_INCLUDES
#endif
/* Plaform specific diagnostic output */
#define LWIP_PLATFORM_DIAG(x) do { hal_print x; } while(0)
#if ASSERT_ERROR_WITH_MSG
#define LWIP_PLATFORM_ASSERT(x) do { hal_print("Assertion \"%s\" failed at line %d in %s\r\n", \
x, __LINE__, __FILE__); FFLUSH(NULL); halt(); } while(0)
#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
hal_print("Assertion \"%s\" failed at line %d in %s\r\n", message, __LINE__, __FILE__); \
FFLUSH(NULL);handler;} } while(0)
#else
#define LWIP_PLATFORM_ASSERT(x) do { hal_print("Assertion failed at line %d in %s\r\n", \
__LINE__, __FILE__); FFLUSH(NULL); halt(); } while(0)
#define LWIP_ERROR(message, expression, handler) do { if (!(expression)) { \
hal_print("Assertion failed at line %d in %s\r\n", __LINE__, __FILE__); \
FFLUSH(NULL);handler;} } while(0)
#endif
/* C runtime functions redefined */
//#define snprintf _snprintf
u32_t dns_lookup_external_hosts_file(const char *name);
#define LWIP_RAND() ((u32_t)OS_Random())
#endif /* __ARCH_CC_H__ */

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#pragma pack(pop)

40
Living_SDK/platform/mcu/sv6266/inc/arch/perf.h Normal file
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/*
* Copyright (c) 2001, Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the Institute nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#ifndef __PERF_H__
#define __PERF_H__
#define PERF_START /* null definition */
#define PERF_STOP(x) /* null definition */
#endif /* __PERF_H__ */

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#ifndef CUSTOM_IO_HAL_H
#define CUSTOM_IO_HAL_H
#define M_CUSTOM_ALT0 (0)
#define M_CUSTOM_ALT1 (1)
#define M_CUSTOM_ALT2 (2)
#define M_CUSTOM_ALT3 (3)
#define M_CUSTOM_ALT4 (4)
#define M_CUSTOM_ALT5 (5)
/**
* +-----+---------+---------+---------+---------+---------+---------+
* | PIN | ALT0 | ALT1 | ALT2 | ALT3 | ALT4 | ALT5 |
* +-----+---------+---------+---------+---------+---------+---------+
* | 0 | AICE | PWM0 | | | ADC3 | GPIO00 |
* | 1 | AICE | PWM1 | | | | GPIO01 |
* | 2 | AICE | PWM2 | | | | GPIO02 |
* | 3 | UART0 | PWM3 | | | | GPIO03 |
* | 4 | UART0 | PWM4 | | | | GPIO04 |
* | 5 | UART1 | I2S0 | | | | GPIO05 |
* | 6 | UART1 | I2S0 | | | | GPIO06 |
* | 7 | UART1 | I2S0 | | | | SIO07 |
* | 8 | | SPIM | I2S0 | | | GPIO08 |
* | 9 | UART1 | I2S0 | | | | GPIO09 |
* | 10 | | SPIM | I2S0 | I2CM0 | SPIS | GPIO10 |
* | 11 | | | | | SPIS | GPIO11 |
* | 12 | | SPIM | I2S0 | I2CM0 | SPIS | GPIO12 |
* | 13 | | SPIM | I2S0 | PSRAM | SPIS | GPIO13 |
* +-----+---------+---------+---------+---------+---------+---------+
* | 20 | | I2S0 | I2S0 | | ADC2 | SIO20 |
* | 21 | | UART0 | I2CM0 | | ADC1 | GPIO21 |
* | 22 | | UART0 | I2CM0 | | ADC0 | GPIO22 |
* +-----+---------+---------+---------+---------+---------+---------+
*/
//ALT0 : AICE / ALT1 : PWM0 /ALT2 : NONE /ALT3 : NONE /ALT4 : ADC3 /ALT5 : GPIO00
#define M_CUSTOM_P00_MODE M_CUSTOM_ALT0
//ALT0 : AICE / ALT1 : PWM1 /ALT2 : NONE /ALT3 : NONE /ALT4 : NONE /ALT5 : GPIO01
#define M_CUSTOM_P01_MODE M_CUSTOM_ALT0
//ALT0 : AICE / ALT1 : PWM2 /ALT2 : NONE /ALT3 : NONE /ALT4 : NONE /ALT5 : GPIO02
#define M_CUSTOM_P02_MODE M_CUSTOM_ALT0
//ALT0 : UART0_RX / ALT1 : PWM3 /ALT2 : NONE /ALT3 : NONE /ALT4 : NONE /ALT5 : GPIO03
#define M_CUSTOM_P03_MODE M_CUSTOM_ALT0
//ALT0 : UART0_TX / ALT1 : PWM4 /ALT2 : NONE /ALT3 : NONE /ALT4 : NONE /ALT5 : GPIO04
#define M_CUSTOM_P04_MODE M_CUSTOM_ALT0
//ALT0 : UART1_RTS / ALT1 : I2S0_BCLK /ALT2 : NONE /ALT3 : NONE /ALT4 : NONE /ALT5 : GPIO05
#define M_CUSTOM_P05_MODE M_CUSTOM_ALT5
//ALT0 : UART1_RXD / ALT1 : I2S0_DI /ALT2 : NONE /ALT3 : NONE /ALT4 : NONE /ALT5 : GPIO06
#define M_CUSTOM_P06_MODE M_CUSTOM_ALT5
//ALT0 : UART1_TXD / ALT1 : I2S0_DO /ALT2 : NONE /ALT3 : NONE /ALT4 : NONE /ALT5 : SIO07
#define M_CUSTOM_P07_MODE M_CUSTOM_ALT5
//ALT0 : NONE / ALT1 : SPI_M_CLK /ALT2 : I2S0_BCLK /ALT3 : NONE /ALT4 : NONE /ALT5 : GPIO08
#define M_CUSTOM_P08_MODE M_CUSTOM_ALT5
//ALT0 : UART1_CTS / ALT1 : I2S0_LRCLK /ALT2 : NONE /ALT3 : NONE /ALT4 : NONE /ALT5 : GPIO09
#define M_CUSTOM_P09_MODE M_CUSTOM_ALT5
//ALT0 : NONE / ALT1 : SPI_M_MISO /ALT2 : I2S0_DI /ALT3 : I2C0_M_SDA /ALT4 : SPI_S_MOSI /ALT5 : GPIO10
#define M_CUSTOM_P10_MODE M_CUSTOM_ALT5
//ALT0 : NONE / ALT1 : NONE /ALT2 : NONE /ALT3 : NONE /ALT4 : SPI_S_CLK /ALT5 : GPIO11
#define M_CUSTOM_P11_MODE M_CUSTOM_ALT5
//ALT0 : NONE / ALT1 : SPI_M_MOSI /ALT2 : I2S0_DO /ALT3 : I2C0_M_SCL /ALT4 : SPI_S_MISO /ALT5 : GPIO12
#define M_CUSTOM_P12_MODE M_CUSTOM_ALT5
//ALT0 : NONE / ALT1 : SPI_M_CS /ALT2 : I2S0_LRCLK /ALT3 : PSRAM_CS /ALT4 : SPI_S_CS /ALT5 : GPIO13
#define M_CUSTOM_P13_MODE M_CUSTOM_ALT3
//ALT0 : NONE / ALT1 : I2S0_MCLK /ALT2 : I2S0_MCLK /ALT3 : NONE /ALT4 : ADC2 /ALT5 : SIO20
#define M_CUSTOM_P20_MODE M_CUSTOM_ALT5
//ALT0 : NONE / ALT1 : UART0_TXD /ALT2 : I2C0_M_SCL /ALT3 : NONE /ALT4 : ADC1 /ALT5 : GPIO21
#define M_CUSTOM_P21_MODE M_CUSTOM_ALT4
//ALT0 : NONE / ALT1 : UART0_RXD /ALT2 : I2C0_M_SDA /ALT3 : NONE /ALT4 : ADC0 /ALT5 : GPIO22
#define M_CUSTOM_P22_MODE M_CUSTOM_ALT4
#endif /* end of include guard: CUSTOM_IO_HAL_H */

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#ifndef _DRV_UART_H_
#define _DRV_UART_H_
#define UART_FIFO_LEVEL (16) ///< The UART has a 16-byte FIFO (First In, First Out).
uint32_t
hal_uart_direct_read_byte (
void
);
uint32_t
hal_uart_get_line_status (
void
);
typedef
void
(*UART_ISR) (
void
);
typedef enum _UART_IE_E {
UART_DATA_RDY_IE = 0x0, ///< Receiver Data Ready or Time out Interrupt Enable.
UART_RX_LINESTS_IE = 0x2, ///< Receiver Line Status Interrupt Enable.
UART_MDM_STS_IE = 0x3, ///< Modem Status Interrupt Enable.
UART_TX_THRL_IE = 0x5 ///< Tx FIFO Low Threshold Interrupt Enable.
} UART_IE_E;
typedef enum _UART_INT_RXFIFO_TRGLVL_E {
UART_INT_RXFIFO_TRGLVL_1 = 0x0, ///< Rx FIFO has 1 charcter trigger interrupt
UART_INT_RXFIFO_TRGLVL_4 = 0x1, ///< Rx FIFO has 4 charcter trigger interrupt
UART_INT_RXFIFO_TRGLVL_8 = 0x2, ///< Rx FIFO has 8 charcter trigger interrupt
UART_INT_RXFIFO_TRGLVL_14 = 0x3 ///< Rx FIFO has 14 charcter trigger interrupt
} UART_INT_RXFIFO_TRGLVL_E;
typedef enum _UART_WORD_LEN_E {
UART_WORD_LEN_5 = 0x0, ///< Character's Word Length 5 bits.
UART_WORD_LEN_6 = 0x1, ///< Character's Word Length 6 bits.
UART_WORD_LEN_7 = 0x2, ///< Character's Word Length 7 bits.
UART_WORD_LEN_8 = 0x3 ///< Character's Word Length 8 bits.
} UART_WORD_LEN_E;
typedef enum _UART_STOP_BIT_E {
UART_STOP_BIT_1 = 0x0, ///< One stop bit will be transmitted.
UART_STOP_BIT_2 = 0x1 ///< Two stop bits (1.5 with 5-bit data) will be transmitted.
} UART_STOP_BIT_E;
typedef enum _UART_PARITY_E {
UART_PARITY_DISABLE = 0x0, ///< No parity bit is transmitted nor expected.
UART_PARITY_ODD = 0x1, ///< The number of bits including the parity bit must be odd.
UART_PARITY_EVEN = 0x3, ///< The number of bits including the parity bit must be even.
UART_PARITY_FORCED1 = 0x5, ///< The parity bit is sent as/checked to be 1.
UART_PARITY_FORCED0 = 0x7 ///< The parity bit is sent as/checked to be 0.
} UART_PARITY_E;
typedef enum _UART_BLOCKING_MODE_E {
UART_NON_BLOCKING = 0x0, ///< Set the UART HAL driver to operate in non-blocking mode.
UART_BLOCKING = 0x1 ///< Set the UART HAL driver to operate in blocking mode.
} UART_BLOCKING_MODE_E;
typedef union _UART_LSR {
//
// Individual bit fields
//
struct {
uint32_t DR : 1; ///< This is the Data Ready bit.
uint32_t OE : 1; ///< This is the Overrun Error flag.
uint32_t PE : 1; ///< This is the Parity Error flag.
uint32_t FE : 1; ///< This is the Framing Error flag.
uint32_t BI : 1; ///< This is the Break Interrupt indicator.
uint32_t THRE : 1; ///< This is the Transmitter Holding Register Empty flag.
uint32_t TSRE : 1; ///< This is the Transmitter Shift Register Empty flag.
uint32_t FIFOE : 1; ///< This is the receiver FIFO data error bit.
uint32_t Reserved : 24; ///< Reserved.
} Bits;
//
// All bit fields as a 32-bit value
//
uint32_t Reg32;
} UART_LSR;
/**
* Registers an interrupt service routine to be called from the UART interrupt handler.
*
* If ISR is NULL, then the UART interrupt is disabled.
*
* @param INT_ENABLE Select the type of UART interrupt enable.
* @param ISR A pointer to an ISR function that is called when a UART interrupt handler occurs.
* NULL to disable interrupt.
*/
void
drv_uart_register_isr (
UART_IE_E INT_ENABLE,
UART_ISR ISR
);
/**
* Initialize the UART hardware.
*/
void
drv_uart_init (
void
);
/**
* Deinitialize the UART hardware.
*/
void
drv_uart_deinit (
void
);
/**
* The UART communications format to the specified settings.
*
* @param BaudRate The baud rate of the UART.
* Contains at least the [1, 921600] range.
* @param DataBits The number of data bits in each character.
* @param StopBits The number of stop bits per character.
* @param Parity That is computed or checked as each character is transmitted or received.
*
* @retval -3 The baud rate out of range.
* @retval -17 The clock source is no mapping.
* @retval 0 The operation completed successfully.
*/
int32_t
drv_uart_set_format (
int32_t BaudRate,
UART_WORD_LEN_E DataBits,
UART_STOP_BIT_E StopBits,
UART_PARITY_E Parity
);
/**
* The UART FIFOs to the specified settings.
*
* @param INT_RXFIFO_TRIGGER_LEVEL In FIFO mode an interrupt will be generated (if enabled) when the number of words
* in the receiver's FIFO is equal or greater than this trigger level.
* @param INT_TXFIFO_THRESHOLD_LOW In FIFO mode an interrupt will be generated (if enabled) when the number of words
* in the transmitter's FIFO is equal or less than this threshold.
* Contains at least the [0, 15] range.
*/
void
drv_uart_set_fifo (
UART_INT_RXFIFO_TRGLVL_E INT_RXFIFO_TRIGGER_LEVEL,
uint8_t INT_TXFIFO_THRESHOLD_LOW
);
/**
* Write data from buffer to UART transmitter FIFOs.
*
* Writes NumberOfBytes data bytes from Buffer to the UART transmitter FIFOs.
* The number of bytes actually written to the UART transmitter FIFOs is returned.
*
* @param Buffer Pointer to the data buffer to be written.
* @param NumberOfBytes Number of bytes to written to the UART transmitter FIFOs.
* @param BlockingMode Set the UART HAL driver to operate in blocking/non-blocking mode.
*
* @retval -9 Buffer is NULL.
* @retval >0 The number of bytes written to the UART transmitter FIFOs.
*/
int32_t
drv_uart_write_fifo (
uint8_t const *Buffer,
int32_t NumberOfBytes,
UART_BLOCKING_MODE_E BlockingMode
);
/**
* Reads data from a UART receiver FIFOs into a buffer.
*
* Reads NumberOfBytes data bytes from the UART receiver FIFOs.
* The number of bytes actually read from the UART receiver FIFOs is returned.
*
* @param Buffer Pointer to the data buffer to store the data read from the UART receiver FIFOs.
* @param NumberOfBytes Number of bytes to read from the UART receiver FIFOs.
* @param BlockingMode Set the UART HAL driver to operate in blocking/non-blocking mode.
*
* @retval -9 Buffer is NULL.
* @retval >0 The number of bytes read from the UART receiver FIFOs.
*/
int32_t
drv_uart_read_fifo (
uint8_t *Buffer,
int32_t NumberOfBytes,
UART_BLOCKING_MODE_E BlockingMode
);
/**
* The UART software reset.
*
* Write 1 to trigger a pulse to reset the whole UART.
*/
void
drv_uart_sw_rst (
void
);
/**
* This service reads the UART line status value.
*
* @return Returns the UART line status value.
*/
uint32_t
drv_uart_get_line_status (
void
);
/**
* This service checks the UART receiver is available or not.
*
* @retval 1 The UART receiver is available.
* @retval 0 The UART receiver is not available.
*/
uint32_t
drv_uart_is_receiver_available (
void
);
/**
* This service checks the UART transmitter is idle or not.
*
* @retval 1 The UART transmitter is idle.
* @retval 0 The UART transmitter is not idle.
*/
uint32_t
drv_uart_is_transmitter_idle (
void
);
#endif // #ifndef _DRV_UART_H_

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#ifndef LOW_POWER_H
#define LOW_POWER_H
#include "attrs.h"
#include <stdint.h>
void lowpower_idle_power(uint32_t ctrl);
#endif /* end of include guard */

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/*
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#ifndef __LWIPOPTS_H__
#define __LWIPOPTS_H__
#include <sys/time.h>
#include "osal.h"
/**
* Loopback demo related options.
*/
#define LWIP_NETIF_LOOPBACK 1
#define LWIP_HAVE_LOOPIF 1
#define LWIP_NETIF_LOOPBACK_MULTITHREADING 1
#define LWIP_LOOPBACK_MAX_PBUFS 8
#define TCPIP_THREAD_NAME "tcp/ip"
#define TCPIP_THREAD_STACKSIZE 3200
#define TCPIP_THREAD_PRIO (OS_TASK_PRIOBASE - 3)
#define DEFAULT_THREAD_STACKSIZE 200
#define DEFAULT_THREAD_PRIO 1
/* Disable lwIP asserts */
#define LWIP_NOASSERT 1
#define LWIP_DEBUG 0
#define LWIP_DEBUG_TRACE 0
#define SOCKETS_DEBUG LWIP_DBG_OFF // | LWIP_DBG_MASK_LEVEL
#define IP_DEBUG LWIP_DBG_OFF
#define ETHARP_DEBUG LWIP_DBG_OFF
#define NETIF_DEBUG LWIP_DBG_OFF
#define PBUF_DEBUG LWIP_DBG_OFF
#define MEMP_DEBUG LWIP_DBG_OFF
#define API_LIB_DEBUG LWIP_DBG_OFF
#define API_MSG_DEBUG LWIP_DBG_OFF
#define ICMP_DEBUG LWIP_DBG_OFF
#define IGMP_DEBUG LWIP_DBG_OFF
#define INET_DEBUG LWIP_DBG_OFF
#define IP_REASS_DEBUG LWIP_DBG_OFF
#define RAW_DEBUG LWIP_DBG_OFF
#define MEM_DEBUG LWIP_DBG_OFF
#define SYS_DEBUG LWIP_DBG_OFF
#define TCP_DEBUG LWIP_DBG_OFF
#define TCP_INPUT_DEBUG LWIP_DBG_OFF
#define TCP_FR_DEBUG LWIP_DBG_OFF
#define TCP_RTO_DEBUG LWIP_DBG_OFF
#define TCP_CWND_DEBUG LWIP_DBG_OFF
#define TCP_WND_DEBUG LWIP_DBG_OFF
#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF
#define TCP_RST_DEBUG LWIP_DBG_OFF
#define TCP_QLEN_DEBUG LWIP_DBG_OFF
#define UDP_DEBUG LWIP_DBG_OFF
#define TCPIP_DEBUG LWIP_DBG_OFF
#define PPP_DEBUG LWIP_DBG_OFF
#define SLIP_DEBUG LWIP_DBG_OFF
#define DHCP_DEBUG LWIP_DBG_OFF
#define AUTOIP_DEBUG LWIP_DBG_OFF
#define SNMP_MSG_DEBUG LWIP_DBG_OFF
#define SNMP_MIB_DEBUG LWIP_DBG_OFF
#define DNS_DEBUG LWIP_DBG_OFF
//#define LWIP_COMPAT_MUTEX 1
/**
* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
* critical regions during buffer allocation, deallocation and memory
* allocation and deallocation.
*/
#define SYS_LIGHTWEIGHT_PROT 1
/*
------------------------------------
---------- Memory options ----------
------------------------------------
*/
/**
* MEM_ALIGNMENT: should be set to the alignment of the CPU
* 4 byte alignment -> #define MEM_ALIGNMENT 4
* 2 byte alignment -> #define MEM_ALIGNMENT 2
*/
#define MEM_ALIGNMENT 4
#define MAX_SOCKETS_TCP 12
#define MAX_LISTENING_SOCKETS_TCP 4
#define MAX_SOCKETS_UDP 22
#define TCP_SND_BUF_COUNT 5
/* Value of TCP_SND_BUF_COUNT denotes the number of buffers and is set by
* CONFIG option available in the SDK
*/
/* Buffer size needed for TCP: Max. number of TCP sockets * Size of pbuf *
* Max. number of TCP sender buffers per socket
*
* Listening sockets for TCP servers do not require the same amount buffer
* space. Hence do not consider these sockets for memory computation
*/
#define TCP_MEM_SIZE (MAX_SOCKETS_TCP * \
PBUF_POOL_BUFSIZE * (TCP_SND_BUF/TCP_MSS))
/* Buffer size needed for UDP: Max. number of UDP sockets * Size of pbuf
*/
#define UDP_MEM_SIZE (MAX_SOCKETS_UDP * PBUF_POOL_BUFSIZE)
/**
* MEM_SIZE: the size of the heap memory. If the application will send
* a lot of data that needs to be copied, this should be set high.
*/
#define MEM_SIZE (32*1024)
/*
------------------------------------------------
---------- Internal Memory Pool Sizes ----------
------------------------------------------------
*/
/**
* MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
* If the application sends a lot of data out of ROM (or other static memory),
* this should be set high.
*/
#define MEMP_NUM_PBUF 10
/**
* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
* (requires the LWIP_TCP option)
*/
#define MEMP_NUM_TCP_PCB MAX_SOCKETS_TCP
#define MEMP_NUM_TCP_PCB_LISTEN MAX_LISTENING_SOCKETS_TCP
/**
* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
* (requires the LWIP_TCP option)
*/
//#define MEMP_NUM_TCP_SEG 12
/**
* MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
* for incoming packets.
* (only needed if you use tcpip.c)
*/
#define MEMP_NUM_TCPIP_MSG_INPKT 16
#define TCPIP_MBOX_SIZE 16
/**
* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
* (requires NO_SYS==0)
*/
#define MEMP_NUM_SYS_TIMEOUT 12
/**
* MEMP_NUM_NETBUF: the number of struct netbufs.
* (only needed if you use the sequential API, like api_lib.c)
*/
#define MEMP_NUM_NETBUF 16
/**
* MEMP_NUM_NETCONN: the number of struct netconns.
* (only needed if you use the sequential API, like api_lib.c)
*
* This number corresponds to the maximum number of active sockets at any
* given point in time. This number must be sum of max. TCP sockets, max. TCP
* sockets used for listening, and max. number of UDP sockets
*/
#define MEMP_NUM_NETCONN (MAX_SOCKETS_TCP + \
MAX_LISTENING_SOCKETS_TCP + MAX_SOCKETS_UDP)
/**
* PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
*/
#define PBUF_POOL_SIZE 10
/*
----------------------------------
---------- Pbuf options ----------
----------------------------------
*/
/**
* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
* designed to accomodate single full size TCP frame in one pbuf, including
* TCP_MSS, IP header, and link header.
*/
#define PBUF_POOL_BUFSIZE 1580
#define MAX_RECV_BUF 1516
/*
---------------------------------
---------- RAW options ----------
---------------------------------
*/
/**
* LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
*/
#define LWIP_RAW 1
#define LWIP_IPV6 0
/* Enable IPv4 Auto IP */
#ifdef CONFIG_AUTOIP
#define LWIP_AUTOIP 1
#define LWIP_DHCP_AUTOIP_COOP 1
#define LWIP_DHCP_AUTOIP_COOP_TRIES 5
#endif
/*
------------------------------------
---------- Socket options ----------
------------------------------------
*/
/**
* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
*/
#define LWIP_SOCKET 1
#define LWIP_NETIF_API 1
/**
* LWIP_RECV_CB==1: Enable callback when a socket receives data.
*/
#define LWIP_RECV_CB 1
/**
* SO_REUSE==1: Enable SO_REUSEADDR option.
*/
#define SO_REUSE 1
#define SO_REUSE_RXTOALL 1
/**
* Enable TCP_KEEPALIVE
*/
#define LWIP_TCP_KEEPALIVE 1
/*
----------------------------------------
---------- Statistics options ----------
----------------------------------------
*/
/**
* LWIP_STATS==1: Enable statistics collection in lwip_stats.
*/
#define LWIP_STATS 0
/**
* LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
*/
#define LWIP_STATS_DISPLAY 0
/*
----------------------------------
---------- DHCP options ----------
----------------------------------
*/
/**
* LWIP_DHCP==1: Enable DHCP module.
*/
#define LWIP_DHCP 1
#define LWIP_NETIF_STATUS_CALLBACK 1
/**
* DNS related options, revisit later to fine tune.
*/
#define LWIP_DNS 1
#define DNS_TABLE_SIZE 2 // number of table entries, default 4
//#define DNS_MAX_NAME_LENGTH 64 // max. name length, default 256
#define DNS_MAX_SERVERS 2 // number of DNS servers, default 2
#define DNS_DOES_NAME_CHECK 1 // compare received name with given,def 0
#define DNS_MSG_SIZE 512
#define MDNS_MSG_SIZE 512
#define MDNS_TABLE_SIZE 1 // number of mDNS table entries
#define MDNS_MAX_SERVERS 1 // number of mDNS multicast addresses
/* TODO: Number of active UDP PCBs is equal to number of active UDP sockets plus
* two. Need to find the users of these 2 PCBs
*/
#define MEMP_NUM_UDP_PCB (MAX_SOCKETS_UDP + 2)
/* NOTE: some times the socket() call for SOCK_DGRAM might fail if you dont
* have enough MEMP_NUM_UDP_PCB */
/*
----------------------------------
---------- IGMP options ----------
----------------------------------
*/
/**
* LWIP_IGMP==1: Turn on IGMP module.
*/
#define LWIP_IGMP 1
/**
* LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
* SO_SNDTIMEO processing.
*/
#define LWIP_SO_SNDTIMEO 1
/**
* LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
* SO_RCVTIMEO processing.
*/
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
/**
* TCP_LISTEN_BACKLOG==1: Handle backlog connections.
*/
#define TCP_LISTEN_BACKLOG 1
//#undef LWIP_PROVIDE_ERRNO
//#include <errno.h>
//#define ERRNO 1
//#define LWIP_SNMP 1
/*
------------------------------------------------
---------- Network Interfaces options ----------
------------------------------------------------
*/
/**
* LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
* field.
*/
#define LWIP_NETIF_HOSTNAME 1
/*
The STM32F107 allows computing and verifying the IP, UDP, TCP and ICMP checksums by hardware:
- To use this feature let the following define uncommented.
- To disable it and process by CPU comment the the checksum.
*/
//#define CHECKSUM_BY_HARDWARE
#ifdef CHECKSUM_BY_HARDWARE
/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 0
/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 0
/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 0
/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 0
/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 0
/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 0
#else
/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 1
/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 1
/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 1
/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 1
/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 1
/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 1
#endif
/**
* TCP_RESOURCE_FAIL_RETRY_LIMIT: limit for retrying sending of tcp segment
* on resource failure error returned by driver.
*/
#define TCP_RESOURCE_FAIL_RETRY_LIMIT 50
//yhb changed:
//#ifdef CONFIG_ENABLE_MXCHIP
/* save memory */
#define PBUF_POOL_SIZE 10
#define TCP_MSS (1500 - 40)
/* TCP receive window. */
#define TCP_WND (3*TCP_MSS)
/* TCP sender buffer space (bytes). */
#define TCP_SND_BUF (10*TCP_MSS)
#define TCP_SND_QUEUELEN (20)
/* ARP before DHCP causes multi-second delay - turn it off */
#define DHCP_DOES_ARP_CHECK (0)
#define TCP_MAX_ACCEPT_CONN 5
#define MEMP_NUM_TCP_SEG (TCP_SND_QUEUELEN*2)
#define IP_REASS_MAX_PBUFS 0
#define IP_REASSEMBLY 0
#define IP_REASS_MAX_PBUFS 0
#define IP_REASSEMBLY 0
#define MEMP_NUM_REASSDATA 0
#define IP_FRAG 0
#define MEM_LIBC_MALLOC (1)
#define MEMP_MEM_MALLOC (1)
#define TCP_MSL (TCP_TMR_INTERVAL)
#define LWIP_COMPAT_MUTEX_ALLOWED (1)
//#endif
#define TCPIP_MBOX_SIZE 16
#define DEFAULT_ACCEPTMBOX_SIZE 8
#define DEFAULT_RAW_RECVMBOX_SIZE 4
#define DEFAULT_UDP_RECVMBOX_SIZE 8
#define DEFAULT_TCP_RECVMBOX_SIZE 8
#ifdef CONFIG_AOS_MESH
#define LWIP_DECLARE_HOOK \
struct netif *lwip_hook_ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest); \
int lwip_hook_mesh_is_mcast_subscribed(const ip6_addr_t *dest);
#define LWIP_HOOK_IP6_ROUTE(src, dest) lwip_hook_ip6_route(src, dest)
#define LWIP_HOOK_MESH_IS_MCAST_SUBSCRIBED(dest) lwip_hook_mesh_is_mcast_subscribed(dest)
#define LWIP_ICMP6 1
#define CHECKSUM_CHECK_ICMP6 0
#define LWIP_MULTICAST_PING 1
#endif
#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 1
#define TCP_QUEUE_OOSEQ 1
#define LWIP_TIMEVAL_PRIVATE 0
#define LWIP_PRIVATE_FD_SET
#define LWIP_TCPIP_CORE_LOCKING 0
#endif /* __LWIPOPTS_H__ */

522
Living_SDK/platform/mcu/sv6266/ld/flash.lds.S Normal file
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@ -0,0 +1,522 @@
/* This file is generated by nds_ldsag (version (2015-08-19) ). */
#include "layout_flash_ilm_dlm.lds.S"
#define M_VMA_AT(section) AT (ALIGN(LOADADDR(section) + SIZEOF(section), 4) )
#define M_VMA_AT_START(section) AT (ALIGN(LOADADDR(section) + SIZEOF(section), 4) )
#define M_BOOT_SECTOR_SIZE 16K
#define M_FLASH_SECTOR_SIZE 4K
#define M_RAW_SECTOR_SIZE 8K
#define M_N10_LOOP 0xD500
/* CONFIG IN FLASH HEADER */
#if !defined(XTAL)
#define XTAL 25
#endif
#if !defined(SYS_BUS_SPEED)
#define SYS_BUS_SPEED 80
#endif
#if !defined(XIP_BIT)
#define XIP_BIT 1
#endif
#if !defined(SETTING_PARTITION_MAIN_SIZE)
#define SETTING_PARTITION_MAIN_SIZE 620K
#endif
#if !defined(SETTING_FLASH_TOTAL_SIZE)
#define SETTING_FLASH_TOTAL_SIZE 2M
#endif
#if !defined(SETTING_PSRAM_HEAP_BASE)
#define SETTING_PSRAM_HEAP_BASE 0x0
#endif
#if !defined(SETTING_PSRAM_HEAP_SIZE)
#define SETTING_PSRAM_HEAP_SIZE 0x0
#endif
ENTRY(OTA_BOOT)
EXTERN(_start)
EXTERN(retention_boot)
EXTERN(OTA_BOOT)
EXTERN(g_sa_cfg)
EXTERN(g_wifi_cfg)
EXTERN(g_user_cfg)
SECTIONS
{
_SDA_BASE_ = 0x00100000;
PROVIDE (__executable_start = 0x00000000);
NDS_SAG_LMA_ROM = 0x30000000 ;
FLASH_BEGIN = NDS_SAG_LMA_ROM;
. = ORIGIN(REGION_BURN);
.ota_boot :
{
__ota_boot_addr = .;
KEEP(*(.ota_boot_hdr))
. = ALIGN(4);
LONG(XTAL);
. = ALIGN(4);
LONG(SYS_BUS_SPEED);
. = ALIGN(4);
LONG(XIP_BIT);
. = ALIGN(4);
LONG(SETTING_PARTITION_MAIN_SIZE);
. = ALIGN(4);
LONG(SETTING_FLASH_TOTAL_SIZE);
. = ALIGN(4);
LONG(SETTING_PSRAM_HEAP_BASE);
. = ALIGN(4);
LONG(SETTING_PSRAM_HEAP_SIZE);
. = ALIGN(4);
KEEP(*(.ota_boot))
#ifdef CONFIG_OS_RHINO
KEEP(*bootloader.a:*.o (.text.* .rodata.*))
#else
KEEP(*libota_boot.a:*.o (.text.* .rodata.*))
#endif
. = ALIGN(4);
} > REGION_BURN
__ota_fast_boot_lmastart = LOADADDR (.ota_fast_boot_code);
__ota_fast_boot_start = ADDR(.ota_fast_boot_code);
.ota_fast_boot_code : M_VMA_AT(.ota_boot)
{
KEEP(*(.ota_fast_boot_code))
KEEP(*(.ota_fast_boot_data))
} > REGION_OTA_FAST
. = ALIGN(4);
__ota_fast_boot_end = .;
.empty : {
FILL(0xD500);
. = ORIGIN(REGION_BURN) + 0x3000;
__lds_reserved_start = .;
. = ORIGIN(REGION_BURN) + M_BOOT_SECTOR_SIZE;
} > REGION_BURN
.fix_table_section :
{
__lds_sa_mp_data_start = .;
KEEP(*(.sa_mp_data))
__lds_sa_mp_data_end = .;
. = ORIGIN(REGION_BURN) + M_BOOT_SECTOR_SIZE + M_FLASH_SECTOR_SIZE;
__lds_cfg_data_start = .;
KEEP(*(.cfg_mac_data))
__lds_cfg_data_end = .;
. = ORIGIN(REGION_BURN) + M_BOOT_SECTOR_SIZE + M_FLASH_SECTOR_SIZE + M_FLASH_SECTOR_SIZE;
__lds_user_data_start = .;
KEEP(*(.user_data))
__lds_user_data_end = .;
. = ORIGIN(REGION_BURN) + M_BOOT_SECTOR_SIZE + M_FLASH_SECTOR_SIZE + M_FLASH_SECTOR_SIZE + M_RAW_SECTOR_SIZE;
} > REGION_BURN
.magic_boot :
{
__magic_boot_addr = .;
KEEP(*(.magic_boot_hdr ))
KEEP(*(.magic_boot ))
KEEP(*(.magic_boot_c ))
} > REGION_BURN
.text :
{
. = ALIGN(4);
__XIP_TEXT_START = .;
#if defined(SETTING_THROUGHPUT_HIGH)
*(.text .stub EXCLUDE_FILE (*libota_boot.a:*.o *libsrm_sys.a:*flash.o *libflashctl.a:*flashctl.o *libfreertos.a:*queue.o *libfreertos.a:*list.o *libfreertos.a:*tasks.o *libfreertos.a:*port.o *libfreertos.a:*portISR.o *osal_freertos.o *heap_5.o *sys_arch.o *api_msg.o *edca.o) .text.* .gnu.linkonce.t.* ) KEEP(*(.text.*personality* )) *(.gnu.warning )
#else
#ifdef CONFIG_OS_RHINO
*(.text .stub EXCLUDE_FILE (*bootloader.a:*.o *sys.a:*flash.o *sys.a:*xip.o) .text.* .gnu.linkonce.t.* ) KEEP(*(.text.*personality* )) *(.gnu.warning )
#else
*(.text .stub EXCLUDE_FILE (*libota_boot.a:*.o *libsrm_sys.a:*flash.o *libflashctl.a:*flashctl.o *sys_arch.o *api_msg.o *edca.o) .text.* .gnu.linkonce.t.* ) KEEP(*(.text.*personality* )) *(.gnu.warning )
#endif
#endif
. = ALIGN(4);
__XIP_TEXT_END = .;
} > REGION_BURN
. = ALIGN(4);
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.rodata :
{
#if defined(SETTING_THROUGHPUT_HIGH)
#ifdef MBED_RO_TURN
*(.rodata EXCLUDE_FILE (*libota_boot.a:*.o *libsrm_sys.a:*flash.o *libflashctl.a:*flashctl.o *libfreertos.a:*queue.o *libfreertos.a:*list.o *libfreertos.a:*tasks.o *libfreertos.a:*port.o *libfreertos.a:*portISR.o *osal_freertos.o *heap_5.o *sys_arch.o *api_msg.o *edca.o *libmbedtls.a:*aes.o *libmbedtls.a:*sha512.o *libmbedtls.a:*bignum.o *libmbedtls.a:*gcm.o) .rodata.* .gnu.linkonce.r.* )
#else
*(.rodata EXCLUDE_FILE (*libota_boot.a:*.o *libsrm_sys.a:*flash.o *libflashctl.a:*flashctl.o *libfreertos.a:*queue.o *libfreertos.a:*list.o *libfreertos.a:*tasks.o *libfreertos.a:*port.o *libfreertos.a:*portISR.o *osal_freertos.o *heap_5.o *sys_arch.o *api_msg.o *edca.o) .rodata.* .gnu.linkonce.r.* )
#endif
#else
#ifdef CONFIG_OS_RHINO
*(.rodata EXCLUDE_FILE (*bootloader.a:*.o *sys.a:*flash.o *sys.a:*xip.o) .rodata.* .gnu.linkonce.r.* )
#else
*(.rodata EXCLUDE_FILE (*libota_boot.a:*.o *libsrm_sys.a:*flash.o *libflashctl.a:*flashctl.o *sys_arch.o *api_msg.o *edca.o) .rodata.* .gnu.linkonce.r.* )
#endif
#endif
} > REGION_BURN
.rodata1 :
{
*(.rodata1 )
} > REGION_BURN
.sdata2 :
{
*(.sdata2 .sdata2.* .gnu.linkonce.s2.* )
} > REGION_BURN
.sbss2 :
{
*(.sbss2 .sbss2.* .gnu.linkonce.sb2.* )
} > REGION_BURN
.ex9.itable :
{
*(.ex9.itable )
} > REGION_BURN
.eh_frame_hdr :
{
*(.eh_frame_hdr )
} > REGION_BURN
. = 0x00000000;
SDRAM_BEGIN = .;
__flash_lmastart = LOADADDR (.vector);
__flash_start = ADDR(.vector);
.vector : M_VMA_AT(.eh_frame_hdr)
{
KEEP(*(.vector ))
} > REGION_TEXT_FAST
.nds32_init : M_VMA_AT(.vector)
{
KEEP(*(.nds32_init ))
} > REGION_TEXT_FAST
.fast_boot_code : M_VMA_AT(.nds32_init)
{
KEEP(*(.fast_boot_code))
#ifdef CONFIG_OS_RHINO
KEEP(*sys.a:*flash.o (.text.* .rodata.*))
KEEP(*sys.a:*xip.o (.text.* .rodata.*))
#else
KEEP(*libsrm_sys.a:*flash.o (.text.* .rodata.*))
KEEP(*libflashctl.a:*flashctl.o (.text.* .rodata.*))
#endif
} > REGION_TEXT_FAST
.rela.text : M_VMA_AT(.fast_boot_code)
{
*(.rela.text .rela.text.* .rela.gnu.linkonce.t.* )
} > REGION_TEXT_FAST
.rela.dyn : M_VMA_AT(.rela.text)
{
*(rela.dyn ) *(.rela__libc_subfreeres ) *(.rela__libc_atexit ) *(.rela__libc_thread_subfreeres ) *(.rela.init_array ) *(.rela.fini_array )
} > REGION_TEXT_FAST
. = ALIGN(4);
_fast_code_end = .;
PROVIDE (_fast_code_end = .);
__flash_psram_lmastart = LOADADDR(.prog_in_sram);
__flash_psram_start = ADDR(.prog_in_sram);
__flash_end = ADDR(.prog_in_sram);
.prog_in_sram : M_VMA_AT(.rela.dyn)
{
KEEP(*sys_arch.o (.text.* .rodata.*))
KEEP(*api_msg.o (.text.* .rodata.*))*/
KEEP(*edca.o (.text.* .rodata.*))
#if defined(SETTING_THROUGHPUT_HIGH)
#ifdef CONFIG_OS_ALIOS
#else
KEEP(*libfreertos.a:*queue.o (.text.* .rodata.*))
KEEP(*libfreertos.a:*list.o (.text.* .rodata.*))
KEEP(*libfreertos.a:*tasks.o (.text.* .rodata.*))
KEEP(*libfreertos.a:*port.o (.text.* .rodata.*))
KEEP(*libfreertos.a:*portISR.o (.text.* .rodata.*))
KEEP(*osal_freertos.o (.text.* .rodata.*))
KEEP(*heap_5.o (.text.* .rodata.*))
#ifdef MBED_RO_TURN
KEEP(*libmbedtls.a:*aes.o (.rodata.*))
KEEP(*libmbedtls.a:*sha512.o (.rodata.*))
KEEP(*libmbedtls.a:*bignum.o (.rodata.*))
KEEP(*libmbedtls.a:*gcm.o (.rodata.*))
#endif
#endif
#endif
/* KEEP(*netstack.o (.text.* .rodata.*))
KEEP(*ethernetif.o (.text.* .rodata.*))
KEEP(*tcpip.o (.text.* .rodata.*))
KEEP(*ip4.o (.text.* .rodata.*))
KEEP(*tcp_in.o (.text.* .rodata.*))
KEEP(*udp.o (.text.* .rodata.*))
KEEP(*tcp_out.o (.text.* .rodata.*))
KEEP(*etharp.o (.text.* .rodata.*))
KEEP(*inet_chksum.o (.text.* .rodata.*))
KEEP(*sys_arch.o (.text.* .rodata.*))
KEEP(*netif.o (.text.* .rodata.*))
KEEP(*def.o (.text.* .rodata.*))
KEEP(*lwip_pbuf.o (.text.* .rodata.*))*/
*(.copy_to_sram .copy_to_sram.*)
*(.prog_in_sram .prog_in_sram.*)
} > REGION_TEXT_FAST
_eflash = .;
PROVIDE (eflash = .);
ilm_end = ORIGIN(OTA_ILM)+LENGTH(OTA_ILM);
ilm_remain = ilm_end - _eflash;
__retention_code_lmastart = LOADADDR(.retention_boot);
__retention_code_start = ADDR(.retention_boot);
.retention_boot : M_VMA_AT(.prog_in_sram)
{
KEEP(*(.retention_boot ))
} > REGION_LPRAM
__retention_code_end = .;
PROVIDE (retention_code_end = .);
__data_lmastart = LOADADDR (.eh_frame);
__data_start = ADDR(.eh_frame);
.eh_frame : AT(ALIGN(LOADADDR (.retention_boot) + SIZEOF (.retention_boot), 32))
{
KEEP(*(.eh_frame ))
} > REGION_DATA_FAST
.gcc_except_table : AT(ALIGN(LOADADDR (.eh_frame) + SIZEOF (.eh_frame), ALIGNOF(.gcc_except_table)))
{
KEEP(*(.gcc_except_table )) *(.gcc_except_table.* )
} > REGION_DATA_FAST
.tdata : AT(ALIGN(LOADADDR (.gcc_except_table) + SIZEOF (.gcc_except_table), ALIGNOF(.tdata)))
{
*(.tdata .tdata.* .gnu.linkonce.td.* )
} > REGION_DATA_FAST
. = ALIGN(4);
PROVIDE (__preinit_array_start = .);
.preinit_array : AT(ALIGN(ALIGN(LOADADDR (.tdata) + SIZEOF (.tdata), ALIGNOF(.preinit_array)), 4))
{
KEEP(*(.preinit_array ))
} > REGION_DATA_FAST
PROVIDE (__preinit_array_end = .);
PROVIDE (__init_array_start = .);
.init_array : AT(ALIGN(LOADADDR (.preinit_array) + SIZEOF (.preinit_array), ALIGNOF(.init_array)))
{
KEEP(*(.init_array ))
} > REGION_DATA_FAST
PROVIDE (__init_array_end = .);
PROVIDE (__fini_array_start = .);
.fini_array : AT(ALIGN(LOADADDR (.init_array) + SIZEOF (.init_array), ALIGNOF(.fini_array)))
{
KEEP(*(.fini_array ))
} > REGION_DATA_FAST
PROVIDE (__fini_array_end = .);
.ctors : AT(ALIGN(LOADADDR (.fini_array) + SIZEOF (.fini_array), ALIGNOF(.ctors)))
{
KEEP(*crtbegin*.o(.ctors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .ctors)) KEEP(*(SORT(.ctors.* ))) KEEP(*(.ctors ))
} > REGION_DATA_FAST
.dtors : AT(ALIGN(LOADADDR (.ctors) + SIZEOF (.ctors), ALIGNOF(.dtors)))
{
KEEP(*crtbegin*.o(.dtors)) KEEP(*(EXCLUDE_FILE (*crtend*.o) .dtors)) KEEP(*(SORT(.dtors.* ))) KEEP(*(.dtors ))
} > REGION_DATA_FAST
.jcr : AT(ALIGN(LOADADDR (.dtors) + SIZEOF (.dtors), ALIGNOF(.jcr)))
{
KEEP(*(.jcr ))
} > REGION_DATA_FAST
.data.rel.ro : AT(ALIGN(LOADADDR (.jcr) + SIZEOF (.jcr), ALIGNOF(.data.rel.ro)))
{
*(.data.rel.ro.local ) *(.data.rel.ro* )
} > REGION_DATA_FAST
.dynamic : AT(ALIGN(LOADADDR (.data.rel.ro) + SIZEOF (.data.rel.ro), ALIGNOF(.dynamic)))
{
*(.dynamic )
} > REGION_DATA_FAST
.data : AT(ALIGN(LOADADDR (.dynamic) + SIZEOF (.dynamic), ALIGNOF(.data)))
{
*(.data .data.* .gnu.linkonce.d.* ) KEEP(*(.gnu.linkonce.d.*personality* )) SORT(CONSTRUCTORS) . = ALIGN(8);
} > REGION_DATA_FAST
.data1 : AT(ALIGN(LOADADDR (.data) + SIZEOF (.data), ALIGNOF(.data1)))
{
*(.data1 ) . = ALIGN(8);
} > REGION_DATA_FAST
. = ALIGN(4);
.got : AT(ALIGN(ALIGN(LOADADDR (.data1) + SIZEOF (.data1), ALIGNOF(.got)), 4))
{
*(.got.plt ) *(.got )
} > REGION_DATA_FAST
.sdata_d : AT(ALIGN(LOADADDR (.got) + SIZEOF (.got), ALIGNOF(.sdata_d)))
{
*(.sdata_d .sdata_d.* )
} > REGION_DATA_FAST
.sdata_w : AT(ALIGN(LOADADDR (.sdata_d) + SIZEOF (.sdata_d), ALIGNOF(.sdata_w)))
{
*(.sdata_w .sdata_w.* )
} > REGION_DATA_FAST
.sdata_h : AT(ALIGN(LOADADDR (.sdata_w) + SIZEOF (.sdata_w), ALIGNOF(.sdata_h)))
{
*(.sdata_h .sdata_h.* )
} > REGION_DATA_FAST
.sdata_b : AT(ALIGN(LOADADDR (.sdata_h) + SIZEOF (.sdata_h), ALIGNOF(.sdata_b)))
{
*(.sdata_b .sdata_b.* )
} > REGION_DATA_FAST
.sdata_f : AT(ALIGN(LOADADDR (.sdata_b) + SIZEOF (.sdata_b), ALIGNOF(.sdata_f)))
{
*(.sdata_f .sdata_f.* )
} > REGION_DATA_FAST
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
__check_main_size = LOADADDR(.sdata_f) + SIZEOF(.sdata_f) - ORIGIN(REGION_BURN);
__bss_start = .;
PROVIDE (__sbss_start = .);
PROVIDE (___sbss_start = .);
.tbss : AT(ALIGN(ALIGN(LOADADDR (.sdata_f) + SIZEOF (.sdata_f), ALIGNOF(.tbss)), 4))
{
*(.tbss .tbss.* .gnu.linkonce.tb.* ) *(.tcommon )
} > REGION_DATA_FAST
.sbss_f : AT(ALIGN(LOADADDR (.tbss) + SIZEOF (.tbss), ALIGNOF(.sbss_f)))
{
*(.sbss_f .sbss_f.* ) *(.scommon_f .scommon_f.* )
} > REGION_DATA_FAST
.sbss_b : AT(ALIGN(LOADADDR (.sbss_f) + SIZEOF (.sbss_f), ALIGNOF(.sbss_b)))
{
*(.sbss_b .sbss_b.* ) *(.scommon_b .scommon_b.* ) . = ALIGN(2);
} > REGION_DATA_FAST
.sbss_h : AT(ALIGN(LOADADDR (.sbss_b) + SIZEOF (.sbss_b), ALIGNOF(.sbss_h)))
{
*(.sbss_h .sbss_h.* ) *(.scommon_h .scommon_h.* ) . = ALIGN(4);
} > REGION_DATA_FAST
.sbss_w : AT(ALIGN(LOADADDR (.sbss_h) + SIZEOF (.sbss_h), ALIGNOF(.sbss_w)))
{
*(.sbss_w .sbss_w.* ) *(.scommon_w .scommon_w.* ) *(.dynsbss ) *(.scommon ) . = ALIGN(8);
} > REGION_DATA_FAST
.sbss_d : AT(ALIGN(LOADADDR (.sbss_w) + SIZEOF (.sbss_w), ALIGNOF(.sbss_d)))
{
*(.sbss_d .sbss_d.* ) *(.scommon_d .scommon_d.* )
} > REGION_DATA_FAST
.bss : AT(ALIGN(LOADADDR (.sbss_d) + SIZEOF (.sbss_d), ALIGNOF(.bss)))
{
*(.dynbss ) *(.bss .bss.* .gnu.linkonce.b.* ) *(COMMON ) . = ALIGN(4);
} > REGION_DATA_FAST
PROVIDE (__sbss_end = .);
PROVIDE (___sbss_end = .);
. = ALIGN(32);
_end = .;
PROVIDE (end = .);
_show_dlm_end = .;
PROVIDE (_show_dlm_end = .);
#ifndef MINIMAL_STACK_SIZE
#define MINIMAL_STACK_SIZE (128)
#endif
#define _INT_STACK_SIZE (2048+256)
#define _EXCEPTION_STACK_SIZE (768)
PROVIDE (_stack = ORIGIN(REGION_DATA_FAST)+LENGTH(REGION_DATA_FAST));
__OS_Exception_Stack = _stack;
__OS_Int_Stack = __OS_Exception_Stack - (_EXCEPTION_STACK_SIZE);
__fence__ = __OS_Int_Stack - (_INT_STACK_SIZE);
dlm_remain = __fence__ - _end;
SDRAM_SIZE = . - SDRAM_BEGIN;
FLASH_SIZE = LOADADDR(.tbss) - FLASH_BEGIN;
.stab 0 :
{
*(.stab)
}
.stabstr 0 :
{
*(.stabstr)
}
.stab.excl 0 :
{
*(.stab.excl)
}
.stab.exclstr 0 :
{
*(.stab.exclstr)
}
.stab.index 0 :
{
*(.stab.index)
}
.stab.indexstr 0 :
{
*(.stab.indexstr)
}
.note.nds32 0 :
{
*(.note.nds32) *(.note.nds32.*)
}
.comment 0 :
{
*(.comment)
}
.debug 0 :
{
*(.debug)
}
.line 0 :
{
*(.line)
}
.debug_srcinfo 0 :
{
*(.debug_srcinfo)
}
.debug_sfnames 0 :
{
*(.debug_sfnames)
}
.debug_aranges 0 :
{
*(.debug_aranges)
}
.debug_pubnames 0 :
{
*(.debug_pubnames)
}
.debug_info 0 :
{
*(.debug_info .gnu.linkonce.wi.*)
}
.debug_abbrev 0 :
{
*(.debug_abbrev)
}
.debug_line 0 :
{
*(.debug_line)
}
.debug_frame 0 :
{
*(.debug_frame)
}
.debug_str 0 :
{
*(.debug_str)
}
.debug_loc 0 :
{
*(.debug_loc)
}
.debug_macinfo 0 :
{
*(.debug_macinfo)
}
.debug_weaknames 0 :
{
*(.debug_weaknames)
}
.debug_funcnames 0 :
{
*(.debug_funcnames)
}
.debug_typenames 0 :
{
*(.debug_typenames)
}
.debug_varnames 0 :
{
*(.debug_varnames)
}
}
ASSERT(((_fast_code_end - __flash_start) <= 8K), "FASTBOOT OVERFLOW");
ASSERT(((_eflash - __flash_psram_start + _fast_code_end - __flash_start) <= LENGTH(REGION_TEXT_FAST)), "ILM OVERFLOW");
ASSERT(((__ota_fast_boot_end - __ota_fast_boot_start) <= LENGTH(REGION_OTA_FAST)), "OTA FASTBOOT OVERFLOW");
ASSERT(((_edata - __data_start) <= LENGTH(REGION_DATA_FAST)), "DLM OVERFLOW");
ASSERT(((SIZEOF(.ota_fast_boot_code)+SIZEOF(.ota_boot)) <= 16K),"boot sector overflow");
ASSERT(((__lds_sa_mp_data_end - __lds_sa_mp_data_start) <= M_FLASH_SECTOR_SIZE),"sa mp table overflow");
ASSERT(((__lds_cfg_data_end - __lds_cfg_data_start) <= M_FLASH_SECTOR_SIZE),"cfg data table overflow");
ASSERT(((__lds_user_data_end - __lds_user_data_start) <= M_RAW_SECTOR_SIZE),"user data table overflow");
ASSERT((__check_main_size<=SETTING_PARTITION_MAIN_SIZE), "main partition size overflow");
PROVIDE(kernel_download_addr = 0x0000000);
PROVIDE(framework_download_addr = 0xffffffff);
PROVIDE(app_download_addr = 0xffffffff);
#if !defined(NO_ROM)
#include "rom_symbol.sym"
#endif

36
Living_SDK/platform/mcu/sv6266/ld/layout_flash_ilm_dlm.lds.S Normal file
View file

@ -0,0 +1,36 @@
MEMORY
{
SRAM_ILM (RWX) : ORIGIN = 0x00000000, LENGTH = (64K-3K)
OTA_ILM (RWX) : ORIGIN = (0x00010000-3K), LENGTH = 3K
#if defined(FPGAv3) || defined(ASICv2)
#if defined(NO_ROM)
SRAM_DLM (RW) : ORIGIN = 0x00100000, LENGTH = 128K
#else
SRAM_DLM (RW) : ORIGIN = 0x00100000, LENGTH = (128K-10K)
#endif
#else
/* SRAM (RWX) : ORIGIN = 0x000F8000, LENGTH = 32K*/
#if defined(NO_ROM)
SRAM_DLM (RW) : ORIGIN = 0x000f8000, LENGTH = 64K + 32K
#else
SRAM_DLM (RW) : ORIGIN = 0x00100000, LENGTH = (64K-10K)
#endif
#endif
RENT_SRAM (RWX) : ORIGIN = 0x00200000, LENGTH = 8K
#if !defined(LDS_FLASH_SIZE)
#define LDS_FLASH_SIZE (512K)
#endif
FLASH (RX) : ORIGIN = 0x30000000, LENGTH = SETTING_FLASH_TOTAL_SIZE
}
REGION_ALIAS("REGION_TEXT_FAST" , SRAM_ILM);
REGION_ALIAS("REGION_OTA_FAST" , OTA_ILM);
REGION_ALIAS("REGION_TEXT_SLOW" , FLASH);
REGION_ALIAS("REGION_BURN", FLASH);
REGION_ALIAS("REGION_DATA" , SRAM_DLM);
#if !defined(FPGAv3) && !defined(ASICv2)
/*REGION_ALIAS("REGION_DATA_SLOW" , SRAM);*/
#endif
REGION_ALIAS("REGION_DATA_FAST" , SRAM_DLM);
REGION_ALIAS("REGION_BSS" , SRAM_DLM);
REGION_ALIAS("REGION_LPRAM" , RENT_SRAM);

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#!/bin/bash
cp ../../../../out/linkkitapp@sv6266_evb/libraries/bootloader.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/cfg.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/common.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/crypto.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/efuse.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/efuseapi.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/hwmac.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/idmanage.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/iotapi.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/mbox.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/n10.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/netstack_wrapper.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/osal.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/phy.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/pinmux.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/security.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/soc_init.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/softmac.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/sys.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/timer.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/tmr.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/udhcp.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/wdt.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/rf_api.a .
cp ../../../../out/linkkitapp@sv6266_evb/libraries/gpio.a .

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Living_SDK/platform/mcu/sv6266/libc_patch.c Normal file
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#include <stdlib.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdarg.h>
#include <sys/time.h>
#include <aos/aos.h>
#include "sys/dbgcon.h"
struct stat;
int _fstat(int fd, struct stat* buf)
{
return 0;
}
int _write(int fd, const void* buf, size_t nbyte)
{
const unsigned char* tmp = buf;
int i;
for(i=0;i<nbyte;i++)
{
if(tmp[i] == '\n')
{
dbgcon_tx('\r');
}
dbgcon_tx(tmp[i]);
}
return nbyte;
}
//void _exit(int status)
//{
// while(1);
//}
int _gettimeofday(struct timeval *tv, void *__tzp)
{
uint64_t t = aos_now_ms();
tv->tv_sec = t / 1000;
tv->tv_usec = (t % 1000) * 1000;
return 0;
}
void* _sbrk(ptrdiff_t incr)
{
return NULL;
}
int _close(int fd)
{
return 0;
}
////////////////////////////////////////////////////////////////////////////////
// buffer size used for printf (created on stack)
#define PRINTF_BUFFER_SIZE 128U
// ntoa conversion buffer size, this must be big enough to hold one converted numeric number (created on stack)
#define NTOA_BUFFER_SIZE 32U
// ftoa conversion buffer size, this must be big enough to hold one converted float number (created on stack)
#define FTOA_BUFFER_SIZE 32U
// define this to support floating point (%f)
//#define PRINTF_FLOAT_SUPPORT
// define this to support long long types (%llu or %p)
#define PRINTF_LONG_LONG_SUPPORT
///////////////////////////////////////////////////////////////////////////////
// internal flag definitions
#define FLAGS_ZEROPAD (1U << 0U)
#define FLAGS_LEFT (1U << 1U)
#define FLAGS_PLUS (1U << 2U)
#define FLAGS_SPACE (1U << 3U)
#define FLAGS_HASH (1U << 4U)
#define FLAGS_UPPERCASE (1U << 5U)
#define FLAGS_LONG (1U << 6U)
#define FLAGS_LONG_LONG (1U << 7U)
#define FLAGS_PRECISION (1U << 8U)
#define FLAGS_WIDTH (1U << 9U)
// internal strlen
// \return The length of the string (excluding the terminating 0)
static inline size_t _strlen(const char* str)
{
size_t len = 0U;
while (str[len] != (char)0) {
len++;
}
return len;
}
// returns true if char is a digit
static inline bool _is_digit(char ch)
{
return (ch >= '0') && (ch <= '9');
}
// internal ASCII to unsigned int conversion
static inline unsigned int _atoi(const char** str)
{
unsigned int i = 0U;
while (_is_digit(**str)) {
i = i * 10U + (unsigned int)(*((*str)++) - '0');
}
return i;
}
// internal itoa format
static size_t _ntoa_format(char* buffer, char* buf, size_t len, bool negative, unsigned int base, size_t maxlen, unsigned int prec, unsigned int width, unsigned int flags)
{
if (maxlen == 0U) {
return 0U;
}
if (base > 16U) {
return 0U;
}
// pad leading zeros
while (!(flags & FLAGS_LEFT) && (len < prec) && (len < NTOA_BUFFER_SIZE)) {
buf[len++] = '0';
}
while (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD) && (len < width) && (len < NTOA_BUFFER_SIZE)) {
buf[len++] = '0';
}
// handle hash
if (flags & FLAGS_HASH) {
if (((len == prec) || (len == width)) && (len > 0U)) {
len--;
if ((base == 16U) && (len > 0U)) {
len--;
}
}
if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < NTOA_BUFFER_SIZE)) {
buf[len++] = 'x';
}
if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < NTOA_BUFFER_SIZE)) {
buf[len++] = 'X';
}
if (len < NTOA_BUFFER_SIZE) {
buf[len++] = '0';
}
}
// handle sign
if ((len == width) && (negative || (flags & FLAGS_PLUS) || (flags & FLAGS_SPACE))) {
len--;
}
if (len < NTOA_BUFFER_SIZE) {
if (negative) {
buf[len++] = '-';
}
else if (flags & FLAGS_PLUS) {
buf[len++] = '+'; // ignore the space if the '+' exists
}
else if (flags & FLAGS_SPACE) {
buf[len++] = ' ';
}
}
// pad spaces up to given width
if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) {
while ((len < width) && (len < NTOA_BUFFER_SIZE)) {
buf[len++] = ' ';
}
}
// reverse string
for (size_t i = 0U; (i < len) && (i < maxlen); ++i) {
buffer[i] = buf[len - i - 1U];
}
// append pad spaces up to given width
if (flags & FLAGS_LEFT) {
while ((len < width) && (len < maxlen)) {
buffer[len++] = ' ';
}
}
return len;
}
// internal itoa for 'long' type
static size_t _ntoa_long(char* buffer, unsigned long value, bool negative, unsigned long base, size_t maxlen, unsigned int prec, unsigned int width, unsigned int flags)
{
char buf[NTOA_BUFFER_SIZE];
size_t len = 0U;
// write if precision != 0 and value is != 0
if (!(flags & FLAGS_PRECISION) || value) {
do {
char digit = (char)(value % base);
buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;
value /= base;
} while ((len < NTOA_BUFFER_SIZE) && value);
}
return _ntoa_format(buffer, buf, len, negative, (unsigned int)base, maxlen, prec, width, flags);
}
// internal itoa for 'long long' type
#if defined(PRINTF_LONG_LONG_SUPPORT)
static size_t _ntoa_long_long(char* buffer, unsigned long long value, bool negative, unsigned long long base, size_t maxlen, unsigned int prec, unsigned int width, unsigned int flags)
{
char buf[NTOA_BUFFER_SIZE];
size_t len = 0U;
// write if precision != 0 and value is != 0
if (!(flags & FLAGS_PRECISION) || value) {
do {
char digit = (char)(value % base);
buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;
value /= base;
} while ((len < NTOA_BUFFER_SIZE) && value);
}
return _ntoa_format(buffer, buf, len, negative, (unsigned int)base, maxlen, prec, width, flags);
}
#endif // PRINTF_LONG_LONG_SUPPORT
#if defined(PRINTF_FLOAT_SUPPORT)
static size_t _ftoa(double value, char* buffer, size_t maxlen, unsigned int prec, unsigned int width, unsigned int flags)
{
char buf[FTOA_BUFFER_SIZE];
size_t len = 0U;
double diff = 0.0;
// if input is larger than thres_max, revert to exponential
const double thres_max = (double)0x7FFFFFFF;
// powers of 10
static const double pow10[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000 };
// test for negative
bool negative = false;
if (value < 0) {
negative = true;
value = 0 - value;
}
// limit precision
if (!(flags & FLAGS_PRECISION)) {
prec = 6U; // by default, precesion is 6
}
if (prec > 9U) {
// precision of >= 10 can lead to overflow errors
prec = 9U;
}
int whole = (int)value;
double tmp = (value - whole) * pow10[prec];
unsigned long frac = (unsigned long)tmp;
diff = tmp - frac;
if (diff > 0.5) {
++frac;
// handle rollover, e.g. case 0.99 with prec 1 is 1.0
if (frac >= pow10[prec]) {
frac = 0;
++whole;
}
}
else if ((diff == 0.5) && ((frac == 0) || (frac & 1))) {
// if halfway, round up if odd, OR if last digit is 0
++frac;
}
// for very large numbers switch back to native sprintf for exponentials. anyone want to write code to replace this?
// normal printf behavior is to print EVERY whole number digit which can be 100s of characters overflowing your buffers == bad
if (value > thres_max) {
return 0U;
}
if (prec == 0U) {
diff = value - whole;
if (diff > 0.5) {
// greater than 0.5, round up, e.g. 1.6 -> 2
++whole;
}
else if ((diff == 0.5) && (whole & 1)) {
// exactly 0.5 and ODD, then round up
// 1.5 -> 2, but 2.5 -> 2
++whole;
}
}
else {
unsigned int count = prec;
// now do fractional part, as an unsigned number
do {
--count;
buf[len++] = (char)(48U + (frac % 10U));
} while ((len < FTOA_BUFFER_SIZE) && (frac /= 10U));
// add extra 0s
while ((len < FTOA_BUFFER_SIZE) && (count-- > 0U)) {
buf[len++] = '0';
}
if (len < FTOA_BUFFER_SIZE) {
// add decimal
buf[len++] = '.';
}
}
// do whole part, number is reversed
while (len < FTOA_BUFFER_SIZE) {
buf[len++] = (char)(48 + (whole % 10));
if (!(whole /= 10)) {
break;
}
}
// pad leading zeros
while (!(flags & FLAGS_LEFT) && (len < prec) && (len < FTOA_BUFFER_SIZE)) {
buf[len++] = '0';
}
while (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD) && (len < width) && (len < FTOA_BUFFER_SIZE)) {
buf[len++] = '0';
}
// handle sign
if (len < FTOA_BUFFER_SIZE) {
if (negative) {
buf[len++] = '-';
}
else if (flags & FLAGS_PLUS) {
buf[len++] = '+'; // ignore the space if the '+' exists
}
else if (flags & FLAGS_SPACE) {
buf[len++] = ' ';
}
}
// pad spaces up to given width
if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) {
while ((len < width) && (len < FTOA_BUFFER_SIZE)) {
buf[len++] = ' ';
}
}
// reverse string
for (size_t i = 0U; (i < len) && (i < maxlen); ++i) {
buffer[i] = buf[len - i - 1];
}
// append pad spaces up to given width
if (flags & FLAGS_LEFT) {
while ((len < width) && (len < maxlen)) {
buffer[len++] = ' ';
}
}
return len;
}
#endif // PRINTF_FLOAT_SUPPORT
// internal vsnprintf
static size_t _vsnprintf(char* buffer, size_t buffer_len, const char* format, va_list va)
{
unsigned int flags, width, precision, n;
size_t idx = 0U;
while (idx < buffer_len) {
// end reached?
if (*format == (char)0) {
buffer[idx] = (char)0;
break;
}
// format specifier? %[flags][width][.precision][length]
if (*format != '%') {
// no
buffer[idx++] = *format;
format++;
continue;
}
else {
// yes, evaluate it
format++;
}
// evaluate flags
flags = 0U;
do {
switch (*format) {
case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break;
case '-': flags |= FLAGS_LEFT; format++; n = 1U; break;
case '+': flags |= FLAGS_PLUS; format++; n = 1U; break;
case ' ': flags |= FLAGS_SPACE; format++; n = 1U; break;
case '#': flags |= FLAGS_HASH; format++; n = 1U; break;
default : n = 0U; break;
}
} while (n);
// evaluate width field
width = 0U;
if (_is_digit(*format)) {
width = _atoi(&format);
}
else if (*format == '*') {
const int w = va_arg(va, int);
if (w < 0) {
flags |= FLAGS_LEFT; // reverse padding
width = (unsigned int)-w;
}
else {
width = (unsigned int)w;
}
format++;
}
// evaluate precision field
precision = 0U;
if (*format == '.') {
flags |= FLAGS_PRECISION;
format++;
if (_is_digit(*format)) {
precision = _atoi(&format);
}
else if (*format == '*') {
precision = (unsigned int)va_arg(va, int);
format++;
}
}
// evaluate length field
if (*format == 'l' || *format == 'L') {
flags |= FLAGS_LONG;
format++;
}
if ((*format == 'l') && (flags & FLAGS_LONG)) {
flags |= FLAGS_LONG_LONG;
format++;
}
// evaluate specifier
switch (*format) {
case 'd' :
case 'i' :
case 'u' :
case 'x' :
case 'X' :
case 'o' :
case 'b' : {
// set the base
unsigned int base;
if (*format == 'x' || *format == 'X') {
base = 16U;
}
else if (*format == 'o') {
base = 8U;
}
else if (*format == 'b') {
base = 2U;
flags &= ~FLAGS_HASH; // no hash for bin format
}
else {
base = 10U;
flags &= ~FLAGS_HASH; // no hash for dec format
}
// uppercase
if (*format == 'X') {
flags |= FLAGS_UPPERCASE;
}
// no plus or space flag for u, x, X, o, b
if ((*format != 'i') && (*format != 'd')) {
flags &= ~(FLAGS_PLUS | FLAGS_SPACE);
}
// convert the integer
if ((*format == 'i') || (*format == 'd')) {
// signed
if (flags & FLAGS_LONG_LONG) {
#if defined(PRINTF_LONG_LONG_SUPPORT)
const long long value = va_arg(va, long long);
idx += _ntoa_long_long(&buffer[idx], (unsigned long long)(value > 0 ? value : 0 - value), value < 0, base, buffer_len - idx, precision, width, flags);
#endif
}
else if (flags & FLAGS_LONG) {
const long value = va_arg(va, long);
idx += _ntoa_long(&buffer[idx], (unsigned long)(value > 0 ? value : 0 - value), value < 0, base, buffer_len - idx, precision, width, flags);
}
else {
const int value = va_arg(va, int);
idx += _ntoa_long(&buffer[idx], (unsigned int)(value > 0 ? value : 0 - value), value < 0, base, buffer_len - idx, precision, width, flags);
}
}
else {
// unsigned
if (flags & FLAGS_LONG_LONG) {
#if defined(PRINTF_LONG_LONG_SUPPORT)
idx += _ntoa_long_long(&buffer[idx], va_arg(va, unsigned long long), false, base, buffer_len - idx, precision, width, flags);
#endif
}
else if (flags & FLAGS_LONG) {
idx += _ntoa_long(&buffer[idx], va_arg(va, unsigned long), false, base, buffer_len - idx, precision, width, flags);
}
else {
idx += _ntoa_long(&buffer[idx], va_arg(va, unsigned int), false, base, buffer_len - idx, precision, width, flags);
}
}
format++;
break;
}
#if defined(PRINTF_FLOAT_SUPPORT)
case 'f' :
case 'F' :
idx += _ftoa(va_arg(va, double), &buffer[idx], buffer_len - idx, precision, width, flags);
format++;
break;
#endif // PRINTF_FLOAT_SUPPORT
case 'c' : {
size_t l = 1U;
// pre padding
if (!(flags & FLAGS_LEFT)) {
while ((idx < buffer_len) && (l++ < width)) {
buffer[idx++] = ' ';
}
}
// char output
buffer[idx++] = (char)va_arg(va, int);
// post padding
if (flags & FLAGS_LEFT) {
while ((idx < buffer_len) && (l++ < width)) {
buffer[idx++] = ' ';
}
}
format++;
break;
}
case 's' : {
char* p = va_arg(va, char*);
size_t l = _strlen(p);
// pre padding
if (flags & FLAGS_PRECISION) {
l = (l < precision ? l : precision);
}
if (!(flags & FLAGS_LEFT)) {
while ((idx < buffer_len) && (l++ < width)) {
buffer[idx++] = ' ';
}
}
// string output
while ((idx < buffer_len) && (*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) {
buffer[idx++] = *(p++);
}
// post padding
if (flags & FLAGS_LEFT) {
while ((idx < buffer_len) && (l++ < width)) {
buffer[idx++] = ' ';
}
}
format++;
break;
}
case 'p' : {
width = sizeof(void*) * 2U;
flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE;
if (sizeof(uintptr_t) == sizeof(long long)) {
#if defined(PRINTF_LONG_LONG_SUPPORT)
idx += _ntoa_long_long(&buffer[idx], (uintptr_t)va_arg(va, void*), false, 16U, buffer_len - idx, precision, width, flags);
#endif
}
else {
idx += _ntoa_long(&buffer[idx], (unsigned long)((uintptr_t)va_arg(va, void*)), false, 16U, buffer_len - idx, precision, width, flags);
}
format++;
break;
}
case '%' :
buffer[idx++] = '%';
format++;
break;
default :
buffer[idx++] = *format;
format++;
break;
}
}
return idx;
}
__attribute__((used))
int printf(const char* format, ...)
{
#ifdef AOS_DISABLE_ALL_LOGS
if (0 == log_get_enable_aos_log_flag()) return 0;
#endif
va_list va;
va_start(va, format);
char buffer[PRINTF_BUFFER_SIZE];
size_t ret = _vsnprintf(buffer, PRINTF_BUFFER_SIZE, format, va);
va_end(va);
for (size_t i = 0U; i < ret; ++i) {
if(buffer[i] == '\n')
{
dbgcon_tx('\r');
}
dbgcon_tx(buffer[i]);
}
return (int)ret;
}
__attribute__((used))
int fprintf(FILE* stream, const char* format, ...)
{
va_list va;
va_start(va, format);
char buffer[PRINTF_BUFFER_SIZE];
size_t ret = _vsnprintf(buffer, PRINTF_BUFFER_SIZE, format, va);
va_end(va);
for (size_t i = 0U; i < ret; ++i) {
if(buffer[i] == '\n')
{
dbgcon_tx('\r');
}
dbgcon_tx(buffer[i]);
}
return (int)ret;
}

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NAME := osal
${NAME}_CFLAGS += -Wno-implicit-function-declaration
$(NAME)_SOURCES := osal_rhino.c

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Living_SDK/platform/mcu/sv6266/osal/osal_rhino.c Normal file
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#include <stdlib.h>
#include <string.h>
#include "soc_defs.h"
#include "osal.h"
#include "sys/sys_random.h"
void OS_TaskSwitchInfo(void)
{
// aMH do nothing.
}
u8 OS_FromISR( void )
{
return (gOsFromISR>0) ? true : false;
}
u32 OS_Random(void)
{
return rand();
}
u32 OS_IntSave(void)
{
size_t psw = __nds32__mfsr(NDS32_SR_PSW);
__nds32__gie_dis();
return psw;
}
void OS_IntRestore(u32 psw)
{
__nds32__mtsr(psw, NDS32_SR_PSW);
}
/* Task: */
void OS_Init( void )
{
sys_rand_pwon();
sys_srand();
sys_rand_pwoff();
krhino_init();
}
void OS_StatInit( void )
{
}
u8 OS_TaskCreate( OsTask task, const char *name, u16 stackSize, void *param, u32 pri, OsTaskHandle *taskHandle )
{
kstat_t ret;
ktask_t *task_tmp;
u32 real_pri = (OS_TASK_PRIOBASE - pri);
ret = krhino_task_dyn_create(&task_tmp, name, param, real_pri, 0, stackSize, (task_entry_t)task, 1);
if (ret == RHINO_SUCCESS) {
if(taskHandle)
{
*taskHandle = task_tmp;
}
return true;
}
return false;
}
const char * OS_TaskGetName (OsTaskHandle taskHandle)
{
ktask_t* handle;
if(!taskHandle)
{
handle = krhino_cur_task_get();
}
else
{
handle = (ktask_t*)taskHandle;
}
return handle->task_name;
}
OsTaskHandle OS_TaskGetCurrHandle(void)
{
return ((OsTaskHandle)krhino_cur_task_get());
}
u32 OS_TaskGetPriority(OsTaskHandle taskHandle)
{
return ( OS_TASK_PRIOBASE - (((ktask_t*)taskHandle)->prio) );
}
void OS_TaskSetPriority(OsTaskHandle taskHandle, u32 prio)
{
u8 old_pri;
krhino_task_pri_change((ktask_t*)taskHandle, (OS_TASK_PRIOBASE-prio), &old_pri);
}
void OS_TaskDelete(OsTaskHandle taskHandle)
{
if (taskHandle == NULL){
krhino_task_dyn_del(NULL);
} else {
krhino_task_dyn_del((ktask_t *)taskHandle);
}
}
void OS_TaskSuspend( OsTaskHandle taskHandle )
{
ktask_t* handle;
if(!taskHandle)
{
handle = krhino_cur_task_get();
}
else
{
handle = (ktask_t*)taskHandle;
}
krhino_task_suspend(handle);
}
void OS_TaskResume( OsTaskHandle taskHandle )
{
krhino_task_resume((ktask_t*)taskHandle);
}
void OS_SysInfo(void)
{
}
void OS_StartScheduler( void )
{
krhino_start();
}
void OS_StopScheduler( void )
{
}
void OS_ForceScheduler( void )
{
/* trigger swi*/
__nds32__mtsr(0x10000,NDS32_SR_INT_PEND);
__nds32__isb();
}
void OS_SuspendScheduler( void )
{
krhino_sched_disable();
}
void OS_ResumeScheduler( void )
{
krhino_sched_enable();
}
OS_TICKTYPE OS_GetSysTick(void)
{
return (u32)krhino_sys_tick_get();
}
/* Mutex APIs: */
OS_STATUS OS_MutexInit( OsMutex *mutex )
{
kstat_t ret;
ret = krhino_mutex_dyn_create((kmutex_t**)mutex, "mutex");
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
OS_STATUS OS_MutexDelete( OsMutex mutex )
{
krhino_mutex_dyn_del((kmutex_t*)mutex);
return OS_SUCCESS;
}
OS_STATUS OS_MutexLock( OsMutex mutex )
{
kstat_t ret;
ret = krhino_mutex_lock((kmutex_t*)mutex, RHINO_WAIT_FOREVER);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
OS_STATUS OS_MutexUnLock( OsMutex mutex )
{
kstat_t ret;
ret = krhino_mutex_unlock((kmutex_t*)mutex);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
void OS_MsDelay(u32 ms)
{
OS_TICKTYPE ticks;
ticks = krhino_ms_to_ticks(ms);
if (ticks == 0) {
ticks = 1;
}
krhino_task_sleep(ticks);
}
void OS_UsDelay(u32 us)
{
OS_TICKTYPE ticks;
ticks = krhino_ms_to_ticks(us/1000);
if (ticks == 0) {
ticks = 1;
}
krhino_task_sleep(ticks);
}
void OS_TickDelay(OS_TICKTYPE ticks)
{
krhino_task_sleep(ticks);
}
/* Message Queue: */
OS_STATUS OS_MsgQCreate( OsMsgQ *MsgQ, u32 QLen )
{
kstat_t ret;
ret = krhino_buf_queue_dyn_create((kbuf_queue_t**)MsgQ, "default_queue", (QLen*sizeof(OsMsgQEntry)), sizeof(OsMsgQEntry));
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
OS_STATUS OS_MsgQEnqueue( OsMsgQ MsgQ, OsMsgQEntry *MsgItem )
{
kstat_t ret;
kbuf_queue_t *q = (kbuf_queue_t*)MsgQ;
ret = krhino_buf_queue_send(q, MsgItem, q->max_msg_size);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
OS_STATUS OS_MsgQDequeue( OsMsgQ MsgQ, OsMsgQEntry *MsgItem, OS_TICKTYPE TickToWait )
{
kstat_t ret;
size_t msg_len;
ret = krhino_buf_queue_recv((kbuf_queue_t*)MsgQ, TickToWait, MsgItem, &msg_len);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
u32 OS_MsgQWaitingSize( OsMsgQ MsgQ )
{
u32 num;
CPSR_ALLOC();
kbuf_queue_t *q = (kbuf_queue_t*)MsgQ;
RHINO_CRITICAL_ENTER();
num = q->cur_num;
RHINO_CRITICAL_EXIT();
return num;
}
void OS_MsgQDelete( OsMsgQ MsgQ)
{
krhino_buf_queue_dyn_del((kbuf_queue_t*)MsgQ);
}
/* Buffer Queue: */
OS_STATUS OS_BufQCreate(OsBufQ *bufq, u32 qlen, u32 item_size)
{
kstat_t ret;
ret = krhino_buf_queue_dyn_create((kbuf_queue_t**)bufq, "default_queue", (qlen*item_size), item_size);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
void OS_BufQDelete(OsBufQ bufq)
{
krhino_buf_queue_dyn_del((kbuf_queue_t*)bufq);
}
OS_STATUS OS_BufQPush( OsBufQ bufq, void* item)
{
kstat_t ret;
kbuf_queue_t *q = (kbuf_queue_t*)bufq;
ret = krhino_buf_queue_send(q, item, q->max_msg_size);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
OS_STATUS OS_BufQPushEx( OsBufQ bufq, void* item, OS_TICKTYPE tick_to_wait)
{
// aMH: todo review this pushEx implement is right?
return OS_BufQPush(bufq, item);
}
OS_STATUS OS_BufQPushFront( OsBufQ bufq, void* item)
{
kstat_t ret;
kbuf_queue_t *q = (kbuf_queue_t*)bufq;
ret = krhino_buf_queue_send_front(q, item, q->max_msg_size);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
OS_STATUS OS_BufQPop( OsBufQ bufq, void* item, OS_TICKTYPE tick_to_wait)
{
kstat_t ret;
size_t msg_len;
ret = krhino_buf_queue_recv((kbuf_queue_t*)bufq, tick_to_wait, item, &msg_len);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
u32 OS_BufQWaitingSize( OsBufQ bufq )
{
u32 num;
CPSR_ALLOC();
kbuf_queue_t *q = (kbuf_queue_t*)bufq;
RHINO_CRITICAL_ENTER();
num = q->cur_num;
RHINO_CRITICAL_EXIT();
return num;
}
/* Event */
OS_STATUS OS_EventCreate(OsEvent* event)
{
kstat_t ret;
ret = krhino_event_dyn_create((kevent_t **)event, "event", 0x00000000);
if (ret == RHINO_SUCCESS)
{
return OS_SUCCESS;
}
else
{
return OS_FAILED;
}
}
OS_STATUS OS_EventWait(OsEvent event, OS_TICKTYPE ticks_to_wait)
{
u32 real_flag;
if(!event)
{
return OS_FAILED;
}
krhino_event_get((kevent_t*)event, 0x00000001, RHINO_OR_CLEAR, &real_flag, ticks_to_wait);
if(real_flag & 0x00000001)
{
return OS_SUCCESS;
}
else
{
return OS_FAILED;
}
}
OS_STATUS OS_EventSet(OsEvent event)
{
kstat_t ret;
if(!event)
{
return OS_FAILED;
}
ret = krhino_event_set((kevent_t*)event, 0x00000001, RHINO_OR);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
else
{
return OS_FAILED;
}
}
u32 OS_EventGetStatus(OsEvent event)
{
u32 real_flag;
if(!event)
{
return 0;
}
krhino_event_get((kevent_t*)event, 0x00000001, RHINO_OR_CLEAR, &real_flag, RHINO_NO_WAIT);
return real_flag;
}
OS_STATUS OS_EventDelete(OsEvent event)
{
if(!event)
{
return OS_FAILED;
}
krhino_event_del((kevent_t*)event);
return OS_SUCCESS;
}
/* Timer: */
OS_STATUS OS_TimerCreate( OsTimer *timer, u32 ms, u8 autoReload, void *args, OsTimerHandler timHandler )
{
kstat_t ret;
if(autoReload)
{
ret = krhino_timer_dyn_create(
(ktimer_t**)timer,
"timer",
timHandler,
krhino_ms_to_ticks(ms),
krhino_ms_to_ticks(ms),
args,
0);
}
else
{
ret = krhino_timer_dyn_create(
(ktimer_t**)timer,
"timer",
timHandler,
krhino_ms_to_ticks(ms),
0,
args,
0);
}
if (ret == RHINO_SUCCESS)
{
return OS_SUCCESS;
}
else
{
return OS_FAILED;
}
}
u8 OS_TimerSet( OsTimer timer, u32 ms, u8 autoReload, void *args )
{
kstat_t ret;
if(autoReload)
{
ret = krhino_timer_arg_change((ktimer_t*)timer, args);
if(ret != RHINO_SUCCESS)
{
return OS_FAILED;
}
ret = krhino_timer_change((ktimer_t*)timer, krhino_ms_to_ticks(ms), krhino_ms_to_ticks(ms));
if(ret != RHINO_SUCCESS)
{
return OS_FAILED;
}
}
else
{
ret = krhino_timer_arg_change((ktimer_t*)timer, args);
if(ret != RHINO_SUCCESS)
{
return OS_FAILED;
}
ret = krhino_timer_change((ktimer_t*)timer, krhino_ms_to_ticks(ms), 0);
if(ret != RHINO_SUCCESS)
{
return OS_FAILED;
}
}
return OS_SUCCESS;
}
u8 OS_TimerCheckAutoReload(OsTimer timer)
{
ktimer_t* handle = (ktimer_t*)timer;
if(handle->round_ticks)
{
return true;
}
else
{
return false;
}
}
u8 OS_TimerStart( OsTimer timer )
{
if(!timer)
{
return false;
}
if( RHINO_SUCCESS == krhino_timer_start((ktimer_t*)timer) )
{
return true;
}
else
{
return false;
}
}
u8 OS_TimerStop( OsTimer timer )
{
if(!timer)
{
return false;
}
if( RHINO_SUCCESS == krhino_timer_stop((ktimer_t*)timer) )
{
return true;
}
else
{
return false;
}
}
u8 OS_TimerReset( OsTimer timer )
{
OS_TICKTYPE ticks;
if(!timer)
{
return false;
}
if( RHINO_SUCCESS == krhino_timer_stop((ktimer_t*)timer) )
{
if( RHINO_SUCCESS == krhino_timer_start((ktimer_t*)timer) )
{
return true;
}
else
{
return false;
}
}
else
{
return false;
}
}
u8 OS_TimerDelete( OsTimer timer )
{
kstat_t ret;
if(!timer)
{
return false;
}
if(RHINO_SUCCESS == krhino_timer_dyn_del((ktimer_t*)timer))
{
return true;
}
else
{
return false;
}
}
u8 OS_TimerIsActive( OsTimer timer)
{
if( TIMER_ACTIVE == ((ktimer_t*)timer)->timer_state )
{
return true;
}
else
{
return false;
}
}
void *OS_TimerGetData( OsTimer timer )
{
return ((ktimer_t*)timer)->timer_cb_arg;
}
/* Semaphore: */
OS_STATUS OS_SemInit( OsSemaphore* Sem , u32 maxcnt , u32 cnt)
{
kstat_t ret;
ret = krhino_sem_dyn_create((ksem_t**)Sem, "sema", cnt);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
OS_STATUS OS_SemWait( OsSemaphore Sem , OS_TICKTYPE timeout)
{
kstat_t ret;
ret = krhino_sem_take((ksem_t*)Sem, timeout);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_TIMEOUT;
}
u32 OS_SemGetCount( OsSemaphore Sem )
{
u32 count;
krhino_sem_count_get((ksem_t*)Sem, &count);
return count;
}
OS_STATUS OS_SemSignal( OsSemaphore Sem )
{
kstat_t ret;
ret = krhino_sem_give((ksem_t*)Sem);
if (ret == RHINO_SUCCESS) {
return OS_SUCCESS;
}
return OS_FAILED;
}
OS_STATUS OS_SemDelete(OsSemaphore Sem)
{
krhino_sem_dyn_del((ksem_t*)Sem);
}
/* Memory: */
//+++ OSAL API
extern k_mm_head *g_kmm_head;
u8 OS_MemInit(void)
{
// need to move
return true;
}
void OS_MemInfo(void)
{
// need to implement
}
u32 OS_MemTotalSize(void)
{
return ( g_kmm_head->used_size + g_kmm_head->free_size );
}
u32 OS_MemRemainSize(void)
{
return g_kmm_head->free_size;
}
void *OS_MemAlloc( u32 size )
{
void *tmp = NULL;
if (size == 0) {
return NULL;
}
#if (RHINO_CONFIG_MM_DEBUG > 0u && RHINO_CONFIG_GCC_RETADDR > 0u)
if ((size & AOS_UNSIGNED_INT_MSB) == 0) {
tmp = krhino_mm_alloc(size | AOS_UNSIGNED_INT_MSB);
#ifndef AOS_BINS
krhino_owner_attach(g_kmm_head, tmp, (size_t)__builtin_return_address(0));
#endif
} else {
tmp = krhino_mm_alloc(size);
}
#else
tmp = krhino_mm_alloc(size);
#endif
return tmp;
}
void OS_MemFree( void *mem )
{
if (mem == NULL) {
return;
}
krhino_mm_free(mem);
}
void* OS_MemCalloc(u32 count, u32 size)
{
void *p;
/* allocate 'count' objects of size 'size' */
p = OS_MemAlloc(count * size);
if (p)
{
/* zero the memory */
memset(p, 0, count * size);
}
return p;
}
void* OS_MemZalloc(u32 size)
{
return OS_MemCalloc(1, size);
}
void* OS_MemRealloc(void *mem, u32 size)
{
void *tmp = NULL;
#if (RHINO_CONFIG_MM_DEBUG > 0u && RHINO_CONFIG_GCC_RETADDR > 0u)
if ((size & AOS_UNSIGNED_INT_MSB) == 0) {
tmp = krhino_mm_realloc(mem, size | AOS_UNSIGNED_INT_MSB);
#ifndef AOS_BINS
krhino_owner_attach(g_kmm_head, tmp, (size_t)__builtin_return_address(0));
#endif
} else {
tmp = krhino_mm_realloc(mem, size);
}
#else
tmp = krhino_mm_realloc(mem, size);
#endif
return tmp;
}
//---

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 1
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 1
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 1
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 1
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_BLK_SIZE
#define RHINO_CONFIG_MM_BLK_SIZE 16
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 1
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 2048
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#define K_MM_STATISTIC 1
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 1
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 1
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 1
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 1
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 1
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 1
#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 1000
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 32u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 1
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 0
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#ifndef RHINO_CONFIG_BACKTRACE
#define RHINO_CONFIG_BACKTRACE 0
#endif
#ifndef RHINO_CONFIG_PANIC
#define RHINO_CONFIG_PANIC 0
#endif
#endif /* CONFIG_H */

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef TYPES_H
#define TYPES_H
#define RHINO_NO_WAIT 0u
//#define RHINO_WAIT_FOREVER 0xffffffffu /* 32 bit value, if tick type is 64 bit, you need change it to 64 bit */
#define RHINO_TASK_STACK_OVF_MAGIC 0xdeadbeafu /* 32 bit or 64 bit stack overflow magic value */
#define RHINO_INTRPT_STACK_OVF_MAGIC 0xdeaddeadu /* 32 bit or 64 bit stack overflow magic value */
#define RHINO_MM_FRAG_ALLOCATED 0xabcddcabu /* 32 bit value, if 64 bit system, you need change it to 64 bit */
#define RHINO_MM_FRAG_FREE 0xfefdecdbu /* 32 bit value, if 64 bit system, you need change it to 64 bit */
#define RHINO_INLINE static __inline /* inline keyword, it may change under different compilers */
#define RHINO_MM_FREE_DYE 0xABABABAB
#define RHINO_MM_CORRUPT_DYE 0xFEFEFEFE
typedef char name_t;
typedef uint32_t sem_count_t;
typedef uint32_t cpu_stack_t;
typedef uint32_t hr_timer_t;
typedef uint32_t lr_timer_t;
//typedef uint32_t tick_t;
typedef uint64_t idle_count_t;
//typedef uint64_t sys_time_t;
typedef uint32_t mutex_nested_t;
typedef uint8_t suspend_nested_t;
typedef uint64_t ctx_switch_t;
typedef uint32_t cpu_cpsr_t;
///* keil compiler not define ssize_t */
//#ifdef __CC_ARM
//typedef int32_t ssize_t;
//#endif
#endif /* TYPES_H */

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#ifndef __OTA_HAL_GPIO_H__
#define __OTA_HAL_GPIO_H__
typedef enum
{
PIN_MODE_GPIO = 0, /**< Gpio mode */
PIN_MODE_ZSTATE = 1
} pin_mode_t;
typedef enum
{
PIN_NONE = -1,
PWM_0 = 0,
PWM_1 = 1,
PWM_2 = 2,
PWM_3 = 3,
PWM_4 = 4,
UART0_TXD_I = 21,
UART0_RXD_I = 22,
UART0_RXD_II = 3,
UART0_TXD_II = 4,
UART1_RTS = 5,
UART1_RXD = 6,
UART1_TXD = 7,
UART1_CTS = 9,
I2C_M_SDA_I = 10,
I2C_M_SCL_I = 12,
I2C_M_SDA_II = 21,
I2C_M_SCL_II = 22,
I2C_S_SCL = 21,
I2C_S_SDA = 22,
SPI_M_CLK = 8,
SPI_M_MISO = 10,
SPI_M_MOSI = 12,
SPI_M_CS = 13,
SPI_S_MOSI = 10,
SPI_S_CLK = 11,
SPI_S_MISO = 12,
SPI_S_CS = 13,
SPI1_S_MISO = 16,
SPI1_S_CSN = 18,
SPI1_S_MOSI = 19,
SPI1_S_CLK = 20,
I2S_BCLK_I = 5,
I2S_DI_I = 6,
I2S_DO_I = 7,
I2S_LRCLK_I = 9,
I2S_MCLK_I = 20,
I2S_BCLK_II = 8,
I2S_DI_II = 10,
I2S_DO_II = 12,
I2S_LRCLK_II = 13,
I2S_MCLK_II = 20,
SPI_flash_IO0_DI = 14,
SPI_flash_CLK = 15,
SPI_flash_IO3_HD = 16,
SPI_flash_CSN = 17,
SPI_flash_IO1_DO = 18,
SPI_flash_IO2_WP = 19,
ADC_0 = 22,
ADC_1 = 21,
ADC_2 = 20,
ADC_3 = 0,
WIFI_TX_SW = 0,
WIFI_RX_SW = 1,
BT_SW = 2,
BT_PRIORITY = 3,
WLAN_ACTIVE = 4,
BT_ACTIVE = 22,
HS3W_DATA = 8,
HS3W_CSN = 9,
HS3W_CLK = 10,
EXT_LNAGC_0 = 11,
RX_RSSI_INDICATOR = 12,
EXT_LNAGC_1 = 13,
EXT_PGAGC_0 = 14,
CLK_REF_40M = 15,
EXT_PGAGC_3 = 16,
EXT_PGAGC_1 = 18,
EXT_PGAGC_2 = 19,
GPIO_00 = 0,
GPIO_01 = 1,
GPIO_02 = 2,
GPIO_03 = 3,
GPIO_04 = 4,
GPIO_05 = 5,
GPIO_06 = 6,
SIO_07 = 7,
GPIO_08 = 8,
GPIO_09 = 9,
GPIO_10 = 10,
GPIO_11 = 11,
GPIO_12 = 12,
GPIO_13 = 13,
SIO_14 = 14,
SIO_15 = 15,
GPIO_16 = 16,
GPIO_17 = 17,
GPIO_18 = 18,
GPIO_19 = 19,
SIO_20 = 20,
GPIO_21 = 21,
GPIO_22 = 22
} gpio_pin_t;
typedef enum
{
GPIO_DIR_IN = 0, /**< GPIO direction INPUT */
GPIO_DIR_OUT = 1, /**< GPIO direction OUTPUT */
GPIO_DIR_IN_OUT = 2, /**< GPIO direction INPUT and OUTPUT */
GPIO_DIR_IN_OUT_OFF = 3 /**< GPIO direction INPUT and OUTPUT OFF*/
} gpio_dir_t;
typedef enum
{
GPIO_PULL_DOWN = 0, /**< GPIO Pull Down */
GPIO_PULL_UP = 1, /**< GPIO Pull Up */
GPIO_PULL_NONE = 2,
GPIO_PULL_ERROR = 3
} gpio_pull_t;
typedef enum
{
GPIO_DRIVING_WEAK = 0, /**< GPIO weak driving strenght */
GPIO_DRIVING_STRONG = 1 /**< GPIO strong driving streght */
} gpio_driving_strengh_t;
typedef enum
{
GPIO_LOGIC_LOW = 0, /**< GPIO logic state LOW */
GPIO_LOGIC_HIGH = 1 /**< GPIO logic state HIGH */
} gpio_logic_t;
typedef enum
{
GPIO_INTC_HIGH_LEVEL = 2,
GPIO_INTC_RISING_EDGE = 3,
GPIO_INTC_LOW_LEVEL = 4,
GPIO_INTC_FALLING_EDGE = 5
} gpio_intc_trigger_mode_t;
typedef enum
{
GPIO_00_TO_07 = 0,
GPIO_08_TO_15 = 1,
GPIO_16_TO_22 = 2
} gpio_intc_group_t;
#endif

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Living_SDK/platform/mcu/sv6266/port/ota_hal_pinmux.h Normal file
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#ifndef __OTA_HAL_PINMUX_H__
#define __OTA_HAL_PINMUX_H__
typedef enum
{
FUNCTION_NONE = -1,
SEL_I2STRX_II = 0,
SEL_I2STRX_I = 1,
SEL_SPI_SLV = 2,
SEL_SPI_MST = 3,
SEL_I2C_SLV = 4,
SEL_I2C_MST_II = 5,
SEL_I2C_MST_I = 6,
SEL_UART0_II = 7,
SEL_UART0_I = 8,
SEL_BTCX = 9,
SEL_FLASH = 10,
SEL_RF = 11,
SEL_PWM_0 = 12,
SEL_PWM_1 = 13,
SEL_PWM_2 = 14,
SEL_PWM_3 = 15,
SEL_PWM_4 = 16,
SEL_DEBUG_I = 17,
SEL_DEBUG_II = 18,
SEL_MEM_BIST = 19,
SEL_USB_BIST = 20,
SEL_USB_TEST = 21,
SEL_USB_IDDQ = 22,
SEL_ADC_0 = 23,
SEL_ADC_1 = 24,
SEL_ADC_2 = 25,
SEL_ADC_3 = 26,
SEL_UART1 = 27,
I2S_RAW_DATA = 30,
SPI_RAW_DATA = 31
} pinmux_fun_t;
void _ota_hal_pinmux_set_raw(uint32_t io_sel, uint32_t fun_sel);
#endif // ___OTA_HAL_PINMUX_H__

16
Living_SDK/platform/mcu/sv6266/port/ota_soc_init.c Normal file
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#include <nds32_intrinsic.h>
#include "soc_types.h"
#include "soc_defs.h"
#include "ota_hal_gpio.h"
#include "ota_hal_pinmux.h"
#include "custom_io_hal.h"
#include "custom_io_chk.h"
#include "attrs.h"
void _ota_soc_io_init(void) ATTRIBUTE_SECTION_OTA_FBOOT;
void _ota_soc_io_init(void)
{
_ota_hal_pinmux_set_raw(_M_PIN_MODE, _M_FUNC_SEL);
}

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Living_SDK/platform/mcu/sv6266/port/port.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef PORT_H
#define PORT_H
#include "mcu_def.h"
//extern size_t cpu_intrpt_save(void);
//extern void cpu_intrpt_restore(size_t cpsr);
void cpu_intrpt_switch(void);
void cpu_task_switch(void);
void cpu_first_task_start(void);
void *cpu_task_stack_init(cpu_stack_t *base, size_t size, void *arg, task_entry_t entry);
RHINO_INLINE uint8_t cpu_cur_get(void)
{
return 0;
}
#define CPSR_ALLOC() size_t psw
#define RHINO_CPU_INTRPT_DISABLE() do { \
psw=cpu_intrpt_save(); \
} while(0)
#define RHINO_CPU_INTRPT_ENABLE() do { \
cpu_intrpt_restore(psw); \
} while(0)
#endif /* PORT_H */

36
Living_SDK/platform/mcu/sv6266/port/port_tick.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <k_api.h>
#include "mcu_def.h"
#include "soc_defs.h"
#include "sys/intc.h"
#include "sys/systick.h"
extern void systick_isr();
void cpu_first_task_start(void)
{
/* enable SWI for context switch */
intc_irq_set_priority(IRQ_SWI, LOWEST);
intc_irq_enable(IRQ_SWI);
/* enable systick */
intc_register_isr(IRQ_UTIMER_0, systick_isr);
intc_irq_set_priority(IRQ_UTIMER_0, HIGHEST);
intc_irq_enable(IRQ_UTIMER_0);
/* start timer */
systick_set_period((1000*1000)/RHINO_CONFIG_TICKS_PER_SECOND);
systick_start();
/* start first task */
__asm__ __volatile__
(
"b\t CtxRestore"
:
:
:
);
}

100
Living_SDK/platform/mcu/sv6266/port/soc_impl.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <k_api.h>
#include <assert.h>
#include "soc_defs.h"
#if (RHINO_CONFIG_HW_COUNT > 0)
void soc_hw_timer_init(void)
{
}
hr_timer_t soc_hr_hw_cnt_get(void)
{
return 0;
//return *(volatile uint64_t *)0xc0000120;
}
lr_timer_t soc_lr_hw_cnt_get(void)
{
return 0;
}
#endif /* RHINO_CONFIG_HW_COUNT */
#if (RHINO_CONFIG_INTRPT_GUARD > 0)
void soc_intrpt_guard(void)
{
}
#endif
#if (RHINO_CONFIG_INTRPT_STACK_REMAIN_GET > 0)
size_t soc_intrpt_stack_remain_get(void)
{
return 0;
}
#endif
#if (RHINO_CONFIG_INTRPT_STACK_OVF_CHECK > 0)
void soc_intrpt_stack_ovf_check(void)
{
}
#endif
#if (RHINO_CONFIG_DYNTICKLESS > 0)
void soc_tick_interrupt_set(tick_t next_ticks,tick_t elapsed_ticks)
{
}
tick_t soc_elapsed_ticks_get(void)
{
return 0;
}
#endif
extern uint32_t _eflash;
extern uint32_t ilm_remain;
extern uint32_t _end;
extern uint32_t dlm_remain;
k_mm_region_t g_mm_region[] = {{(uint8_t*)&_eflash,(size_t)&ilm_remain},{(uint8_t*)&_end,(size_t)&dlm_remain}};
int g_region_num = sizeof(g_mm_region)/sizeof(k_mm_region_t);
#if (RHINO_CONFIG_MM_LEAKCHECK > 0 )
extern uint32_t __bss_start, _end, __data_start, _edata;
void aos_mm_leak_region_init(void)
{
#if (RHINO_CONFIG_MM_DEBUG > 0)
krhino_mm_leak_region_init(&__bss_start, &_end);
krhino_mm_leak_region_init(&__data_start, &_edata);
#endif
}
#endif
size_t soc_get_cur_sp()
{
return __nds32__get_current_sp();
}
void soc_err_proc(kstat_t err)
{
(void)err;
}
void soc_asserted( const char *func, int line )
{
printf("<!!!OS Assert!!!> func = %s, line=%d\n", func, line);
__nds32__gie_dis();
while(1);
}
void trace_start(void)
{
printf("trace config close!!!\r\n");
}
krhino_err_proc_t g_err_proc = soc_err_proc;

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Living_SDK/platform/mcu/sv6266/sdk/Makefile Normal file
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##############################################################
# Make version check.
##############################################################
ifeq (3.82,$(firstword $(sort $(MAKE_VERSION) 3.82)))
##############################################################
# Global Variables
##############################################################
TOPDIR := $(CURDIR)
TOPOUT := out
BUILD := $(TOPDIR)/build
TARGET_CHIP ?= turismo
OS := freertos
BUILD_ROM ?= 0
FLASH_MODE ?= 0
SDKDIR ?= $(TOPDIR)
FLASH_CTRL ?= 1
SDK_VERSION := version.c
SDK_VERSION_OBJ := $(SDK_VERSION:.c=.o)
#CUSTOMER ?= none
POST_BUILD_CMD ?=
BUILD_MODE ?= release
BUILD_ENV := $(shell uname)
HOST_ARCH := $(shell uname -m)
REDIRECT_BUILDLOG := 1
SHELL=/bin/bash -o pipefail
export TOPDIR TOPOUT BUILD
# config will include project.mk
sinclude $(BUILD)/project_cfg.mk
include $(BUILD)/config.mk
include $(BUILD)/macro.mk
include $(BUILD)/link_macro.mk
#CFLAGS += -DCUSTOMER="$(CUSTOMER)"
##############################################################
# ROM Variables
##############################################################
##############################################################
# Local Variables
##############################################################
IMAGE_DIR := $(TOPDIR)/image
IMAGE_NAME := $(IMAGE_DIR)/$(PROJECT)
LOG_TABLE := $(IMAGE_DIR)/$(PROJECT).json
##############################################################
# init Variables
##############################################################
LIB_DEP :=
LIBRARIES :=
LIBRARIES_DIR :=
CLEAN_RULE :=
TMP_SRC :=
##############################################################
# Source directories to Make
##############################################################
SRC_DIRS += $(IMPORT_DIR)
#$(call foreach-dir,$(SRC_DIRS))
#$(foreach _d,$(SRC_DIRS),$(eval $(call inc-module,$(_d))))
.PHONY: all clean list_projects setup sync_subprojects bootloader bootloader_clean flashtool flashtool_clean
.SECONDARY: main-build
all: pre-build main-build flashtool
pre-build:
$(Q)echo static lib:
$(Q)echo $(STATIC_LIB)
$(Q)echo > build_error.log
$(Q)if [ -f $(BUILD)/project_cfg.mk ]; then \
$(UNLOCK) $(TOPOUT)/string_table.json; \
$(CHMOD) $(TOPDIR)/utils/*; \
else \
echo $(BUILD)/project_cfg.mk not found; \
echo please find project use \"make list_projects\", set project use \"make setup p=PROJECT_NAME\"; \
$(MAKE) list_projects; \
fi
post-build:
@echo build end
ifeq ($(strip $(BUILD_SHOW_ILM_INFO)), 1)
$(Q)echo ILM remain: $$( grep ilm_remain $(IMAGE_DIR)/$(PROJECT).map | awk --non-decimal-data '{printf "%d",$$1}' )
endif
ifeq ($(strip $(BUILD_SHOW_DLM_INFO)), 1)
$(Q)echo DLM remain: $$( grep dlm_remain $(IMAGE_DIR)/$(PROJECT).map | awk --non-decimal-data '{printf "%d",$$1}' )
endif
$(POST_BUILD_CMD)
ifeq ($(strip $(PROJECT)), )
main-build:
$(Q)$(MAKE) --no-print-directory post-build
else
main-build: $(LIB_DEP) $(IMAGE_DIR)/$(PROJECT).bin $(IMAGE_DIR)/$(PROJECT).asm
@echo "# linking with libraries $(LINK_LIBRARIES)"
@echo "# linking with libraries flags $(LIBRARIES_DIR)"
@echo "# making $(PROJECT) completed" "($(shell date))"
$(Q)$(MAKE) --no-print-directory post-build
endif
include build/docs.mk
$(call foreach-dir, $(SRC_DIRS))
LINK_LIBRARIES := $(addprefix -l,$(LIBRARIES))
LINKSCRIPT := $(TOPOUT)/linkscript.lds
##############################################################
# target
##############################################################
ifeq ($(strip $(ROM_MODE)), 1)
$(LINKSCRIPT): $(LDSCRIPT_S)
$(Q)$(CC) -E -P $< $(INC) -Irom_symbol/$(ROM_VERSION) $(CFLAGS) -o $@
else
$(LINKSCRIPT): $(LDSCRIPT_S)
$(Q)$(CC) -E -P $< $(INC) -DNO_ROM $(CFLAGS) -o $@
endif
#$(IMAGE_DIR):
# $(Q)$(MKDIR) $@
#
$(IMAGE_DIR)/$(PROJECT)$(ELFSUFFIX): $(LIB_DEP) $(LINKSCRIPT) $(PROJECT_SRC) $(SDK_VERSION_OBJ)
$(Q)if [ ! -d $(IMAGE_DIR) ]; then \
$(MKDIR) $(IMAGE_DIR); \
fi
$(Q)for SRC in $(PROJECT_SRC); \
do \
cd ${CURDIR}/`dirname $$SRC` && $(CC) $(CFLAGS) $(INC) -c `basename $$SRC`; \
done
$(Q)$(CC) $(LIBRARIES_DIR) $(LDFLAGS_PRE) $(patsubst %.S,%.o,$(patsubst %.c,%.o,$(PROJECT_SRC))) $(PROJECT_OBJ) -Wl,--start-group $(LINK_LIBRARIES) -Wl,--end-group $(INC) $(CFLAGS) $(LDFLAGS) -Xlinker -Map=$(IMAGE_DIR)/$(PROJECT).map -T $(LINKSCRIPT) -o $@ $(SDK_VERSION_OBJ) $(STATIC_LIB)
ifeq ($(strip $(FLASH_MODE)), 1)
ifeq ($(filter FPGAv2 ASIC ASICv2,$(TARGET_DEF)), $(TARGET_DEF))
$(IMAGE_DIR)/$(PROJECT).bin: $(IMAGE_DIR)/$(PROJECT)$(ELFSUFFIX)
$(Q)$(OBJCOPY) -O binary $< $@
md5sum $@ | awk '{print $$1}' > $(IMAGE_DIR)/$(PROJECT).md5
ifeq ($(strip $(SUPPORT_BOOTLOADER)), 1)
@if [ ! -f "$(IMAGE_DIR)/bootloader.bin" ]; then \
make bootloader; \
fi
@if [ -f "$(IMAGE_DIR)/bootloader.bin" ]; then \
echo "find bootloader.bin, will generate combined image"; \
mv $(IMAGE_DIR)/$(PROJECT).bin $(IMAGE_DIR)/$(PROJECT).bin.tmp; \
export bootloader_size=$$(stat -c%s $(IMAGE_DIR)/bootloader.bin); \
export padding_size=$$(echo 16384 $$bootloader_size | awk '{print $$1 - $$2}'); \
dd if=/dev/zero of=$(IMAGE_DIR)/padding.bin bs=1 count=$$padding_size; \
cat $(IMAGE_DIR)/bootloader.bin $(IMAGE_DIR)/padding.bin $(IMAGE_DIR)/$(PROJECT).bin.tmp > $(IMAGE_DIR)/$(PROJECT).bin; \
rm -f $(IMAGE_DIR)/padding.bin; \
rm -f $(IMAGE_DIR)/$(PROJECT).bin.tmp; \
make bootloader_clean; \
fi
endif
else
$(IMAGE_DIR)/$(PROJECT).bin: $(IMAGE_DIR)/$(PROJECT)$(ELFSUFFIX) utils/flash_header
$(OBJCOPY) -O binary $< $@.tmp
utils/test_flash_bin.sh $< $@.tmp $@
endif
else
$(IMAGE_DIR)/$(PROJECT).bin: $(IMAGE_DIR)/$(PROJECT)$(ELFSUFFIX)
$(Q)$(OBJCOPY) -O binary $< $@
md5sum $@ | awk '{print $$1}' > $(IMAGE_DIR)/$(PROJECT).md5
endif
$(IMAGE_DIR)/$(PROJECT).asm: $(IMAGE_DIR)/$(PROJECT)$(ELFSUFFIX)
$(Q)$(OBJDUMP) -d $< -S > $@
utils/flash_header: utils/flash_header.c
@echo "$(Q)gcc $< -o $@"
@echo "$(BUILD_ENV)"
$(Q)gcc $< -o $@
all_libs: $(addsuffix .a, $(addprefix lib, $(LIBRARIES)))
$(Q)$(SIZE) $(addsuffix .a, $(addprefix libs/lib, $(LIBRARIES)))
clean:
$(Q)$(RM) -f utils/flash_header utils/SPI_burn utils/USB_burn utils/*.so utils/*.dll
$(Q)$(RM) -f $(LOG_TABLE) 2> /dev/null | true
$(Q)$(RM) -Rf $(TOPDIR)/out 2> /dev/null | true
$(Q)$(RM) -f $(patsubst %.S,%.o,$(patsubst %.c,%.o,${PROJECT_SRC}))
$(Q)$(RM) -f $(IMAGE_DIR)/$(PROJECT)$(ELFSUFFIX)
$(Q)$(RM) -f $(IMAGE_DIR)/$(PROJECT).bin
$(Q)$(RM) -f $(IMAGE_DIR)/$(PROJECT).asm
$(Q)$(RM) -f $(IMAGE_DIR)/$(PROJECT).map
$(Q)$(RM) -f $(IMAGE_DIR)/$(PROJECT).md5
@echo "clean all completed" "($(shell date))"
#$(Q)$(RM) -Rf $(IMAGE_DIR) 2> /dev/null | true
distclean: flashtool_clean
make bootloader_clean
make clean
$(Q)$(RM) -f $(BUILD)/project_cfg.mk
@echo "distclean all completed" "($(shell date))"
bootloader:
@if [ -f "$(PROJ_DIR)/src/bootloader/bootloader.mk" ]; then \
echo "build bootloader"; \
make -f $(PROJ_DIR)/src/bootloader/bootloader.mk; \
mkdir -p $(IMAGE_DIR) && cp -f $(PROJ_DIR)/src/bootloader/bootloader.elf $(PROJ_DIR)/src/bootloader/bootloader.bin $(PROJ_DIR)/src/bootloader/bootloader.map $(IMAGE_DIR)/; \
echo bootloader size $$(stat -c%s $(IMAGE_DIR)/bootloader.bin); \
else \
echo "bootloader.mk not found"; \
fi
bootloader_clean:
@if [ -f "$(PROJ_DIR)/src/bootloader/bootloader.mk" ]; then \
echo "clean bootloader"; \
make -f $(PROJ_DIR)/src/bootloader/bootloader.mk clean; \
rm -f $(IMAGE_DIR)/bootloader.elf $(IMAGE_DIR)/bootloader.bin $(IMAGE_DIR)/bootloader.map; \
else \
echo "bootloader.mk not found"; \
fi
flashtool:
ifeq ($(strip $(BUILD_ENV)), Linux)
@cd $(TOPDIR)/utils/src-SPI_burn; \
make EXTRA_CFLAGS+=-DLINUX EXTRA_CFLAGS+=-DFLASH_CTL_v2 EXTRA_CFLAGS+=-DSPI_BURN --makefile=Makefile_SPIburn_linux; \
mkdir -p $(IMAGE_DIR); \
cp -f SPI_burn $(IMAGE_DIR)/;
ifeq ($(strip $(HOST_ARCH)), x86_64)
#make EXTRA_CFLAGS+=-DLINUX EXTRA_CFLAGS+=-DFLASH_CTL_v2 EXTRA_CFLAGS+=-DUSB_BURN --makefile=Makefile_USBburn_linux; \
#cp -f USB_burn linux_x64/*.so $(IMAGE_DIR)/;
else
#make EXTRA_CFLAGS+=-DLINUX EXTRA_CFLAGS+=-DFLASH_CTL_v2 EXTRA_CFLAGS+=-DUSB_BURN --makefile=Makefile_USBburn_linux; \
#cp -f USB_burn linux_x86/*.so $(IMAGE_DIR)/;
endif
echo "done"
endif
flashtool_clean:
ifeq ($(strip $(BUILD_ENV)), Linux)
@cd $(TOPDIR)/utils/src-SPI_burn; \
make EXTRA_CFLAGS+=-DLINUX EXTRA_CFLAGS+=-DFLASH_CTL_v2 EXTRA_CFLAGS+=-DSPI_BURN --makefile=Makefile_SPIburn_linux clean; \
#make EXTRA_CFLAGS+=-DLINUX EXTRA_CFLAGS+=-DFLASH_CTL_v2 EXTRA_CFLAGS+=-DUSB_BURN --makefile=utils/src-SPI_burn/Makefile_USBburn_linux clean; \
echo "clean done"
else
@cd $(TOPDIR)/utils/src-SPI_burn; \
make EXTRA_CFLAGS+=-DFLASH_CTL_v2 EXTRA_CFLAGS+=-DSPI_BURN --makefile=Makefile_SPIburn_win clean; \
make EXTRA_CFLAGS+=-DFLASH_CTL_v2 EXTRA_CFLAGS+=-DUSB_BURN --makefile=Makefile_USBburn_win clean; \
echo "clean done"
endif
.SECONDARY: $(TMP_SRC)
#
#_link: $(LDSCRIPT) $(SRC_DIRS)
# @echo "# link ...\n" $(shell cat .build)
# @$(CC) $(CFLAGS) $(LDFLAGS) $(shell cat .build) -Wl,--start-group $(LIB_OBJS) -Wl,--end-group \
# -Xlinker -Map=$(IMAGE_NAME).map \
# -o $(IMAGE_NAME).axf
# @$(OBJCOPY) -O binary $(IMAGE_NAME).axf $(IMAGE_NAME).bin
# @$(OBJDUMP) -d $(IMAGE_NAME).axf -S > $(IMAGE_NAME).asm
# @$(SIZE) -d $(IMAGE_NAME).axf
#
#$(LDSCRIPT): $(LDSCRIPT_S)
# @echo "# build ld ...\n $<"
# @$(CC) $(CFLAGS) -E -P $< -o $(LDSCRIPT)
# @cat $(ICMD_SYMBOLS) >> $(LDSCRIPT)
#
#target_check:
# @if [ "$(PROJECT)" = "" ]; then \
# echo "! no project specified"; \
# exit 0; \
# fi
# @$(RM) -rf .build
# @echo "# make project $(PROJECT)"
# @if ! [ -d $(IMAGE_DIR) ]; then mkdir $(IMAGE_DIR); fi
#
#clean: _clean
# @echo "# clean ..."
# @$(RM) $(LDSCRIPT)
#.DEFAULT_GOAL =
##############################################################
# Make rules
##############################################################
include $(BUILD)/rules.mk
include $(BUILD)/tool.mk
else
$(info Please use 3.82 or higher version)
all: utils/make
@utils/make
@echo "\033[0;31m"
@echo Please update the make tool to 3.82
@echo You can use this command
@echo cd utils \&\& sudo make install
@echo "\033[0m"
utils/make:
@cd utils && third_party/make-3.82/configure
@$(MAKE) -C utils
@utils/make --version
@echo "\033[0;31m"
@echo Please update the make tool to 3.82
@echo You can use this command
@echo cd utils \&\& sudo make install
@echo "\033[0m"
setup: utils/make
@utils/make $(MAKECMDGOALS) p=$(p)
@echo "\033[0;31m"
@echo Please update the make tool to 3.82
@echo You can use this command
@echo cd utils \&\& sudo make install
@echo "\033[0m"
clean: utils/make
@utils/make $(MAKECMDGOALS)
@echo "\033[0;31m"
@echo Please update the make tool to 3.82
@echo You can use this command
@echo cd utils \&\& sudo make install
@echo "\033[0m"
.DEFAULT_GOAL = all
#.PHONY: all
endif

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##############################################################
# Global variables
##############################################################
LIBSUFFIX = .a
ELFSUFFIX = .elf
ifeq ("$(VERBOSE)","1")
Q :=
else
Q := @
endif
################################################################
# Include project makefile
################################################################
#include $(TOPDIR)/projects/$(PROJECT)/mk/project.mk
################################################################
# Define the make variables
################################################################
AS = $(CROSS_COMPILER)as
LD = $(CROSS_COMPILER)ld
CC = $(CROSS_COMPILER)gcc
SIZE = $(CROSS_COMPILER)size
AR = $(CROSS_COMPILER)ar
STRIP = $(CROSS_COMPILER)strip
OBJDUMP = $(CROSS_COMPILER)objdump
OBJCOPY = $(CROSS_COMPILER)objcopy
RANLIB = $(CROSS_COMPILER)RANLIB
RM = rm
CP = cp -rf
MKDIR = mkdir -p
CHMOD = chmod +x
LOCK = $(TOPDIR)/utils/locker.sh
UNLOCK = $(TOPDIR)/utils/unlocker.sh
LOG = $(TOPDIR)/utils/icomm_log_parser
################################################################
export AS LD CC SIZE AR STRIP OBJDUMP OBJCOPY RANLIB RM CP MKDIR
export LDFLAGS CFLAGS AFLAGS
export CC_VERBOSE
################################################################

4
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docs:
doxygen components/bsp/soc/$(CHIP_NAME)/input/doxygen.conf

28
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define link-lib
libs/lib$(1)$(LIBSUFFIX): $(7)/lib$(1)$(LIBSUFFIX)
$(Q)$(MKDIR) $$(dir $$@)
$(Q)$(CP) $$^ $$@
lib$(1)$(LIBSUFFIX): libs/lib$(1)$(LIBSUFFIX)
$(eval LLNAME := $(7)/lib$(1)$(LIBSUFFIX))
LIBRARIES += $(1)
LIB_DEP += $(7)/lib$(1)$(LIBSUFFIX)
LIBRARIES_DIR += -L$(7)
endef
###$(eval $(call link-lib-internal,$(1),$(2)))
# $(1) = LIBRARY_NAME
#x $(2) = LIB_SRC
#x $(3) = LIB_ASRC
#x $(4) = LOCAL_CFLAGS
#x $(5) = LOCAL_INC
#x $(6) = LOCAL_AFLAGS
# $(7) = MYDIR
#define build-lib
# $(eval $(call link-lib-internal,$(1),$(2),$(3),$(4),$(5),$(6)))
#endef

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TOUT := out
define inc-imm
include $(1)
endef
define inc-module
$(eval MYDIR := $(1))
LIBRARY_NAME :=
LOCAL_CFLAGS :=
LOCAL_INC := -I$(1)
LIBRARIES_DIR += -L$(TOUT)/$(1)
CLEAN_RULE += clean_$(TOUT)/$(1)
include $(1)/module.mk
endef
#LIBRARIES += $(LIBRARY_NAME)
#LIB_DEP += $(TOUT)/$(1)/lib$(LIBRARY_NAME)$(LIBSUFFIX)
define foreach-dir
$(foreach d,$(1), $(eval $(call inc-module,$(d))))
endef
define build-lib
ifeq ($(filter clean distclean setup list_projects bootloader bootloader_clean flashtool flashtool_clean,$(MAKECMDGOALS)),)
-include $$(addprefix $(TOUT)/$(7)/,$$(patsubst %.c,%.d,$(2)))
-include $$(addprefix $(TOUT)/$(7)/,$$(patsubst %.S,%.d,$(3)))
endif
ifeq ($(strip $(REDIRECT_BUILDLOG)), 1)
$(TOUT)/$(7)/%.d: $(TOUT)/$(7)/%.c
$(Q)$(CC) $(CFLAGS) $(INC) $(4) $(5) -MM -MT $$(patsubst %.d,%.c,$$@) -MF $$@ $$(patsubst $(TOUT)/$(7)%,$(7)%,$$<) 2>&1 | tee -a build_error.log
$(TOUT)/$(7)/%.d: $(TOUT)/$(7)/%.S
$(Q)$(CC) $(CFLAGS) $(INC) $(4) $(5) -MM -MT $$(patsubst %.d,%.S,$$@) -MF $$@ $$(patsubst $(TOUT)/$(7)%,$(7)%,$$<) 2>&1 | tee -a build_error.log
$(TOUT)/$(7)/%.c: $(TOPDIR)/$(7)/%.c
$(Q)if [ ! -d $$(dir $$@) ]; then \
$(MKDIR) $$(dir $$@); \
fi
$(Q)$(CC) $(CFLAGS) $(INC) $(4) $(5) -E $$< -o $$@ 2>&1 | tee -a build_error.log
$(TOUT)/$(7)/%.S: $(TOPDIR)/$(7)/%.S
$(Q)if [ ! -d $$(dir $$@) ]; then \
$(MKDIR) $$(dir $$@); \
fi
$(Q)$(CC) $(AFLAGS) $(INC) $(6) $(5) -E $$< -o $$@ 2>&1 | tee -a build_error.log
$(TOUT)/$(7)/%.o: $(TOUT)/$(7)/%.c
$(Q)$(CC) $(CFLAGS) $(INC) $(4) $(5) -c $$< -o $$@ 2>&1 | tee -a build_error.log
$(Q)$(SIZE) $$@
$(TOUT)/$(7)/%.o: $(TOUT)/$(7)/%.S
$(Q)$(CC) $(AFLAGS) $(INC) $(6) $(5) -c $$< -o $$@ 2>&1 | tee -a build_error.log
$(Q)$(SIZE) $$@
else
$(TOUT)/$(7)/%.d: $(TOUT)/$(7)/%.c
$(Q)$(CC) $(CFLAGS) $(INC) $(4) $(5) -MM -MT $$(patsubst %.d,%.c,$$@) -MF $$@ $$(patsubst $(TOUT)/$(7)%,$(7)%,$$<)
$(TOUT)/$(7)/%.d: $(TOUT)/$(7)/%.S
$(Q)$(CC) $(CFLAGS) $(INC) $(4) $(5) -MM -MT $$(patsubst %.d,%.S,$$@) -MF $$@ $$(patsubst $(TOUT)/$(7)%,$(7)%,$$<)
$(TOUT)/$(7)/%.c: $(TOPDIR)/$(7)/%.c
$(Q)if [ ! -d $$(dir $$@) ]; then \
$(MKDIR) $$(dir $$@); \
fi
$(Q)$(CC) $(CFLAGS) $(INC) $(4) $(5) -E $$< -o $$@
$(TOUT)/$(7)/%.S: $(TOPDIR)/$(7)/%.S
$(Q)if [ ! -d $$(dir $$@) ]; then \
$(MKDIR) $$(dir $$@); \
fi
$(Q)$(CC) $(AFLAGS) $(INC) $(6) $(5) -E $$< -o $$@
$(TOUT)/$(7)/%.o: $(TOUT)/$(7)/%.c
$(Q)$(CC) $(CFLAGS) $(INC) $(4) $(5) -c $$< -o $$@
$(Q)$(SIZE) $$@
$(TOUT)/$(7)/%.o: $(TOUT)/$(7)/%.S
$(Q)$(CC) $(AFLAGS) $(INC) $(6) $(5) -c $$< -o $$@
$(Q)$(SIZE) $$@
endif
$(TOUT)/$(7)/lib$(1)$(LIBSUFFIX): $(addprefix $(TOUT)/$(7)/,$(patsubst %.c,%.o,$(2))) $(addprefix $(TOUT)/$(7)/,$(patsubst %.S,%.o,$(3)))
$(Q)echo "const char $(1)lib_version[] = \"#VERSION_START#" $(LIB_VERSION) "#VERSION_END#\";" > $$@.c
$(Q)echo "const char $(1)lib_customer[] = \"#CUSTOMER_START#" $(CUSTOMER) "#CUSTOMER_END#\";" >> $$@.c
$(Q)$(CC) -c $$@.c -o $$@.o
$(Q)$(AR) -rsc $$@ $$^ $$@.o
libs/lib$(1)$(LIBSUFFIX): $(TOUT)/$(7)/lib$(1)$(LIBSUFFIX)
$(Q)if [ ! -d $$(dir $$@) ]; then \
$(MKDIR) $$(dir $$@); \
fi
$(Q)$(CP) $$^ $$@
lib$(1)$(LIBSUFFIX): libs/lib$(1)$(LIBSUFFIX)
clean_$(TOUT)/$(7):
$(Q)$(RM) $(addprefix $(TOUT)/$(7)/,$(patsubst %.c,%.o,$(2))) $(addprefix $(TOUT)/$(7)/,$(patsubst %.S,%.o,$(3))) 2>/dev/null | true
$(Q)$(RM) $(addprefix $(TOUT)/$(7)/,$(patsubst %.c,%.d,$(2))) $(addprefix $(TOUT)/$(7)/,$(patsubst %.S,%.d,$(3))) 2>/dev/null | true
$(Q)$(RM) $(TOUT)/$(7)/lib$(1)$(LIBSUFFIX).c $(TOUT)/$(7)/lib$(1)$(LIBSUFFIX).o 2>/dev/null | true
$(Q)$(RM) $(TOUT)/$(7)/lib$(1)$(LIBSUFFIX) 2>/dev/null | true
$(eval LLNAME := $(TOUT)/$(7)/lib$(1)$(LIBSUFFIX))
LIBRARIES += $(1)
LIB_DEP += $(TOUT)/$(7)/lib$(1)$(LIBSUFFIX)
TMP_SRC += $(addprefix $(TOUT)/$(7)/,$(2)) $(addprefix $(TOUT)/$(7)/,$(3))
endef
define clear-lib-internal
endef
###$(eval $(call build-lib-internal,$(1),$(2)))
# $(1) = LIBRARY_NAME
# $(2) = LIB_SRC
# $(3) = LIB_ASRC
# $(4) = LOCAL_CFLAGS
# $(5) = LOCAL_INC
# $(6) = LOCAL_AFLAGS
# $(7) = MYDIR
#define build-lib
# $(eval $(call build-lib-internal,$(1),$(2),$(3),$(4),$(5),$(6)))
#endef

7
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OBJDIR = $(TOPOUT)/$(CURDIR)
LIBDIR = $(TOPOUT)/$(CURDIR)
CWD = "`pwd`"
.PHONY: $(PHONY)

124
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TARGET_DEF ?= none
TARGET_CHIP ?= none
CHIP_NAME ?= none
CHIP_ID ?= none
MCU_DEF ?= none
ifeq ($(strip $(BOARD)), EVB_v1_19M)
TARGET_DEF := ASIC
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), EVB_v1_20M)
TARGET_DEF := ASIC
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), EVB_v1_24M)
TARGET_DEF := ASIC
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), EVB_v1_25M)
TARGET_DEF := ASIC
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), EVB_v1_26M)
TARGET_DEF := ASIC
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), EVB_v1_38M)
TARGET_DEF := ASIC
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), EVB_v1_40M)
TARGET_DEF := ASIC
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), EVB_v1_52M)
TARGET_DEF := ASIC
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S197_25M)
TARGET_DEF := ASICv2
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S197_40M)
TARGET_DEF := ASICv2
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
_BOARD_SSV6006_LIST := \
SSV6006_MP_S236_19M \
SSV6006_MP_S236_20M \
SSV6006_MP_S236_24M \
SSV6006_MP_S236_25M \
SSV6006_MP_S236_26M \
SSV6006_MP_S236_38M \
SSV6006_MP_S236_40M \
SSV6006_MP_S236_52M
#ifeq ($(strip $(BOARD)),$(filter $(strip $(BOARD)),SSV6006_MP_S236_19M SSV6006_MP_S236_20M SSV6006_MP_S236_24M SSV6006_MP_S236_25M SSV6006_MP_S236_26M SSV6006_MP_S236_38M SSV6006_MP_S236_40M SSV6006_MP_S236_52M))
ifeq ($(strip $(BOARD)),$(filter $(strip $(BOARD)), $(_BOARD_SSV6006_LIST)))
TARGET_DEF := ASICv2
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), SSV6006_SHUTTLE_S197_25M)
TARGET_DEF := ASIC
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(BOARD)), SSV6006_SHUTTLE_S197_40M)
TARGET_DEF := ASIC
TARGET_CHIP := turismo
CHIP_NAME := ssv6006
CHIP_ID := 6006
MCU_DEF := ANDES_N10
endif
ifeq ($(strip $(TARGET_CHIP)), none)
$(error please check your TARGET_CHIP)
endif
ifeq ($(strip $(CHIP_NAME)), none)
$(error please check your CHIP_NAME)
endif
export TARGET_DEF TARGET_CHIP CHIP_NAME CHIP_ID MCU_DEF

50
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list_projects:
$(Q)for i in $(wildcard projects/*) ; do \
if [ -f "$$i/mk/project.mk" ]; then \
echo $$i; \
if [ -d "$$i/examples" ]; then \
echo $$i/examples/*; \
fi \
fi \
done
setup:
$(Q)if [ -z "$(p)" ]; then \
rm -f build/project_cfg.mk; \
echo "Please input p args like \"make setup p=base_proj_freertos\""; \
$(MAKE) list_projects; \
else \
if [ -f "projects/$(p)/mk/project.mk" ]; then \
if [ -z "$(sp)" ]; then \
rm -f build/project_cfg.mk; \
echo build project $(p); \
echo PROJECT := $(p) >> build/project_cfg.mk; \
echo PROJ_DIR := projects/$(p) >> build/project_cfg.mk; \
echo sinclude $(TOPDIR)/projects/$(p)/mk/project.mk >> build/project_cfg.mk; \
echo export PROJ_DIR PROJECT >> build/project_cfg.mk; \
else \
if [ -f "projects/$(p)/examples/$(sp)/mk/project.mk" ]; then \
rm -f build/project_cfg.mk; \
echo build subproject $(sp); \
echo PROJECT := $(sp) >> build/project_cfg.mk; \
echo PROJ_DIR := projects/$(p)/examples/$(sp) >> build/project_cfg.mk; \
echo sinclude $(TOPDIR)/projects/$(p)/examples/$(sp)/mk/project.mk >> build/project_cfg.mk; \
echo INC += -Iprojects/$(p)/src/inc >> build/project_cfg.mk; \
echo export PROJ_DIR PROJECT >> build/project_cfg.mk; \
else \
echo "Please setup a exist subproject, if you don't sure, please use \"make list_projects\""; \
$(MAKE) list_projects; \
fi \
fi \
else \
echo "Please setup a exist project, if you don't sure, please use \"make list_projects\""; \
$(MAKE) list_projects; \
fi \
fi
$(Q)if [ -n "$(version)" ]; then\
echo LIB_VERSION := $(version) >> build/project_cfg.mk; \
fi
$(Q)if [ -n "$(customer)" ]; then\
echo CUSTOMER := $(customer) >> build/project_cfg.mk; \
fi

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XTAL := -DXTAL=25
ifeq ($(strip $(BOARD)), EVB_v1_25M)
XTAL := -DXTAL=25
endif
ifeq ($(strip $(BOARD)), EVB_v1_26M)
XTAL := -DXTAL=26
endif
ifeq ($(strip $(BOARD)), EVB_v1_40M)
XTAL := -DXTAL=40
endif
ifeq ($(strip $(BOARD)), EVB_v1_38M)
XTAL := -DXTAL=384
endif
ifeq ($(strip $(BOARD)), EVB_v1_19M)
XTAL := -DXTAL=192
endif
ifeq ($(strip $(BOARD)), EVB_v1_20M)
XTAL := -DXTAL=20
endif
ifeq ($(strip $(BOARD)), EVB_v1_24M)
XTAL := -DXTAL=24
endif
ifeq ($(strip $(BOARD)), EVB_v1_52M)
XTAL := -DXTAL=52
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S197_25M)
XTAL := -DXTAL=25
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S197_40M)
XTAL := -DXTAL=40
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S236_19M)
XTAL := -DXTAL=192
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S236_20M)
XTAL := -DXTAL=20
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S236_24M)
XTAL := -DXTAL=24
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S236_25M)
XTAL := -DXTAL=25
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S236_26M)
XTAL := -DXTAL=26
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S236_38M)
XTAL := -DXTAL=384
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S236_40M)
XTAL := -DXTAL=40
endif
ifeq ($(strip $(BOARD)), SSV6006_MP_S236_52M)
XTAL := -DXTAL=52
endif
ifeq ($(strip $(BOARD)), SSV6006_SHUTTLE_S197_25M)
XTAL := -DXTAL=25
endif
ifeq ($(strip $(BOARD)), SSV6006_SHUTTLE_S197_40M)
XTAL := -DXTAL=25
endif

293
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/mcu/ANDES_N10/mcu_def.h Normal file
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#ifndef N10_DEF_H
#define N10_DEF_H
#define LITTLE 0x0
#define BIG 0x1
#ifdef __NDS32_EB__
#define ENDIAN BIG
#else
#ifdef __big_endian__
#define ENDIAN BIG
#else
#define ENDIAN LITTLE
#endif
#endif
#include "nds32_defs.h"
#ifndef __ASSEMBLER__
#include "nds32_regs.h"
#define TLBOP(op) __asm__ volatile ("tlbop "#op);
#define MSYNC(subtype) __asm__ volatile ("msync "#subtype);
#define STANDBY(cond) __asm__ volatile ("standby "#cond);
#define ISB() __asm__ volatile ("isb");
#define DSB() __asm__ volatile ("dsb");
#ifdef CONFIG_CPU_DCACHE_ENABLE
#define NDS_DCache_Flush n12_dcache_flush
#define NDS_DCache_Invalidate_Flush n12_dcache_invalidate
#define NDS_DCache_Writeback n12_dcache_flush_range
#else
#define NDS_DCache_Flush() ((void)0)
#define NDS_DCache_Invalidate_Flush() ((void)0)
#define NDS_DCache_Writeback() ((void)0)
#endif
/*
* Static inline function would be traded as macro function.
* It would be inlined into caller text object and wouldn't
* create an independent text object.
*/
static inline unsigned int cpu_intrpt_save(void)
{
unsigned int psw = GET_PSW();
__asm__ volatile
(
" setgie.d \n\t"
);
return psw;
}
static inline void cpu_intrpt_restore(unsigned int psw)
{
SET_PSW(psw);
}
#define CPU_INTRPT_FLAG_ALLOC() volatile unsigned int psw
#define CPU_INTRPT_DISABLE() do { \
psw = cpu_intrpt_save(); \
} while(0)
#define CPU_INTRPT_ENABLE() do { \
cpu_intrpt_restore(psw); \
} while(0)
#endif /* __ASSEMBLER__ */
/***********************************
* TARGET INITIALIZATION CONSTANTS
***********************************/
#define PSW_INIT \
(0x0 << PSW_offGIE \
| 0x0 << PSW_offINTL \
| 0x1 << PSW_offPOM \
| ENDIAN << PSW_offBE \
| 0x0 << PSW_offIT \
| 0x0 << PSW_offDT \
| 0x0 << PSW_offIME \
| 0x0 << PSW_offDME \
| 0x0 << PSW_offDEX \
| 0x0 << PSW_offHSS)
#define PSW_MSK \
(PSW_mskGIE \
| PSW_mskINTL \
| PSW_mskPOM \
| PSW_mskBE \
| PSW_mskIT \
| PSW_mskDT \
| PSW_mskIME \
| PSW_mskDME \
| PSW_mskDEX \
| PSW_mskHSS)
#define INT_MASK_INIT \
(0x0 << INT_MASK_offH0IM \
| 0x1 << INT_MASK_offH1IM \
| 0x0 << INT_MASK_offH2IM \
| 0x0 << INT_MASK_offH3IM \
| 0x0 << INT_MASK_offH4IM \
| 0x0 << INT_MASK_offH5IM \
| 0x1 << INT_MASK_offSIM \
| 0x1 << INT_MASK_offIDIVZE)
#define INT_MASK_MSK \
(INT_MASK_mskH0IM \
| INT_MASK_mskH1IM \
| INT_MASK_mskH2IM \
| INT_MASK_mskH3IM \
| INT_MASK_mskH4IM \
| INT_MASK_mskH5IM \
| INT_MASK_mskSIM \
| INT_MASK_mskIDIVZE)
#if 1
#define IVB_MSK \
(IVB_mskEVIC \
| IVB_mskESZ \
| IVB_mskNIVIC \
| IVB_mskIVBASE \
| IVB_mskPROG_PRI_LVL)
#define IVB_INIT \
(0x0 << IVB_offIVBASE \
| 0x1 << IVB_offESZ \
| 0x5 << IVB_offNIVIC \
| 0x0 << IVB_offEVIC)
#endif
#define MMU_CTL_MSK \
(MMU_CTL_mskD \
| MMU_CTL_mskNTC0 \
| MMU_CTL_mskNTC1 \
| MMU_CTL_mskNTC2 \
| MMU_CTL_mskNTC3 \
| MMU_CTL_mskTBALCK \
| MMU_CTL_mskMPZIU \
| MMU_CTL_mskNTM0 \
| MMU_CTL_mskNTM1 \
| MMU_CTL_mskNTM2 \
| MMU_CTL_mskNTM3)
#define MMU_CTL_INIT \
(0x0 << MMU_CTL_offD \
| 0x0 << MMU_CTL_offNTC0 \
| 0x0 << MMU_CTL_offNTC1 \
| 0x0 << MMU_CTL_offNTC2 \
| 0x0 << MMU_CTL_offNTC3 \
| 0x0 << MMU_CTL_offTBALCK \
| 0x0 << MMU_CTL_offMPZIU \
| 0x0 << MMU_CTL_offNTM0 \
| 0x0 << MMU_CTL_offNTM1 \
| 0x2 << MMU_CTL_offNTM2 \
| 0x3 << MMU_CTL_offNTM3)
#ifdef CONFIG_CPU_DCACHE_ENABLE
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
/* Write through */
#define CACHE_ABILITY 0x3
#else
/* Write back */
#define CACHE_ABILITY 0x2
#endif
#else
/* Device */
#define CACHE_ABILITY 0x0
#endif
#define MMU_CTL_INIT_CACHE_ON \
(0x0 << MMU_CTL_offD \
| CACHE_ABILITY << MMU_CTL_offNTC0 \
| 0x0 << MMU_CTL_offNTC1 \
| 0x0 << MMU_CTL_offNTC2 \
| 0x0 << MMU_CTL_offNTC3 \
| 0x0 << MMU_CTL_offTBALCK \
| 0x0 << MMU_CTL_offMPZIU \
| 0x0 << MMU_CTL_offNTM0 \
| 0x0 << MMU_CTL_offNTM1 \
| 0x2 << MMU_CTL_offNTM2 \
| 0x3 << MMU_CTL_offNTM3)
#define CACHE_CTL_MSK \
(CACHE_CTL_mskIC_EN \
| CACHE_CTL_mskDC_EN \
| CACHE_CTL_mskICALCK \
| CACHE_CTL_mskDCALCK \
| CACHE_CTL_mskDCCWF \
| CACHE_CTL_mskDCPMW)
#define CACHE_CTL_INIT \
(0x0 << CACHE_CTL_offIC_EN \
| 0x0 << CACHE_CTL_offDC_EN \
| 0x0 << CACHE_CTL_offICALCK \
| 0x0 << CACHE_CTL_offDCALCK \
| 0x1 << CACHE_CTL_offDCCWF \
| 0x1 << CACHE_CTL_offDCPMW)
#define CACHE_CTL_INIT_CACHE_ON \
(0x1 << CACHE_CTL_offIC_EN \
| 0x0 << CACHE_CTL_offDC_EN \
| 0x0 << CACHE_CTL_offICALCK \
| 0x0 << CACHE_CTL_offDCALCK \
| 0x1 << CACHE_CTL_offDCCWF \
| 0x1 << CACHE_CTL_offDCPMW)
/* Add by Junior, 2012.12.18 */
#define SRIDX(MAJOR, MINOR, EXTEND) \
(MAJOR << 7 \
+ MINOR << 3 \
+ EXTEND)
#define IVIC_MSK \
(0x0 << 0 \
| 0x0 << 1 \
| 0x1 << 2 \
| 0x1 << 3 \
| 0x1 << 4 \
| 0x1 << 5 \
| 0x1 << 6 \
| 0x1 << 7 \
| 0x0 << 8 \
| 0x1 << 9 \
| 0x0 << 10 \
| 0x1 << 11 \
| 0x0 << 12 \
| 0x1 << 13 \
| 0x0 << 14 \
| 0x0 << 15 \
| 0x1 << 16 \
| 0x1 << 17 \
| 0x1 << 18 \
| 0x1 << 19 \
| 0x0 << 20 \
| 0x1 << 21 \
| 0x0 << 22 \
| 0x0 << 23 \
| 0x1 << 24 \
| 0x1 << 25 \
| 0x0 << 26 \
| 0x0 << 27 \
| 0x0 << 28 \
| 0x0 << 29 \
| 0x0 << 30 \
| 0x0 << 31)
#define INT_PRIO_MASK1 \
(0x3 << 0 \
| 0x3 << 2 \
| 0x3 << 4 \
| 0x3 << 6 \
| 0x3 << 8 \
| 0x3 << 10 \
| 0x3 << 12 \
| 0x3 << 14 \
| 0x3 << 16 \
| 0x3 << 18 \
| 0x3 << 20 \
| 0x3 << 22 \
| 0x3 << 24 \
| 0x1 << 26 \
| 0x3 << 28 \
| 0x3 << 30)
#define INT_PRIO_MASK2 \
(0x3 << 0 \
| 0x3 << 2 \
| 0x2 << 4 \
| 0x3 << 6 \
| 0x3 << 8 \
| 0x3 << 10 \
| 0x3 << 12 \
| 0x3 << 14 \
| 0x3 << 16 \
| 0x3 << 18 \
| 0x3 << 20 \
| 0x3 << 22 \
| 0x3 << 24 \
| 0x3 << 26 \
| 0x3 << 28 \
| 0x3 << 30)
#endif /* end of include guard: N10_DEF_H */

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/*
* Copyright (C) 2008 Andes Technology, Inc.
*/
#ifndef __NDS32_DEFS_H__
#define __NDS32_DEFS_H__
/******************************************************************************
* cr0: CPU_VER (CPU Version Register)
*****************************************************************************/
#define CPU_VER_offCFGID 0 /* Minor configuration */
#define CPU_VER_offREV 16 /* Revision of the CPU version */
#define CPU_VER_offCPUID 24 /* Major CPU versions */
#define CPU_VER_mskCFGID ( 0xFFFF << CPU_VER_offCFGID )
#define CPU_VER_mskREV ( 0xFF << CPU_VER_offREV )
#define CPU_VER_mskCPUID ( 0xFF << CPU_VER_offCPUID )
/******************************************************************************
* cr1: ICM_CFG (Instruction Cache/Memory Configuration Register)
*****************************************************************************/
#define ICM_CFG_offISET 0 /* I-cache sets (# of cache lines) per way */
#define ICM_CFG_offIWAY 3 /* I-cache ways */
#define ICM_CFG_offISZ 6 /* I-cache line size */
#define ICM_CFG_offILCK 9 /* I-cache locking support */
#define ICM_CFG_offILMB 10 /* On-chip ILM banks */
#define ICM_CFG_offBSAV 13 /* ILM base register alignment version */
/* bit 15:31 reserved */
#define ICM_CFG_mskISET ( 0x7 << ICM_CFG_offISET )
#define ICM_CFG_mskIWAY ( 0x7 << ICM_CFG_offIWAY )
#define ICM_CFG_mskISZ ( 0x7 << ICM_CFG_offISZ )
#define ICM_CFG_mskILCK ( 0x1 << ICM_CFG_offILCK )
#define ICM_CFG_mskILMB ( 0x7 << ICM_CFG_offILMB )
#define ICM_CFG_mskBSAV ( 0x3 << ICM_CFG_offBSAV )
/******************************************************************************
* cr2: DCM_CFG (Data Cache/Memory Configuration Register)
*****************************************************************************/
#define DCM_CFG_offDSET 0 /* D-cache sets (# of cache lines) per way */
#define DCM_CFG_offDWAY 3 /* D-cache ways */
#define DCM_CFG_offDSZ 6 /* D-cache line size */
#define DCM_CFG_offDLCK 9 /* D-cache locking support */
#define DCM_CFG_offDLMB 10 /* On-chip DLM banks */
#define DCM_CFG_offBSAV 13 /* DLM base register alignment version */
/* bit 15:31 reserved */
#define DCM_CFG_mskDSET ( 0x7 << DCM_CFG_offDSET )
#define DCM_CFG_mskDWAY ( 0x7 << DCM_CFG_offDWAY )
#define DCM_CFG_mskDSZ ( 0x7 << DCM_CFG_offDSZ )
#define DCM_CFG_mskDLCK ( 0x1 << DCM_CFG_offDLCK )
#define DCM_CFG_mskDLMB ( 0x7 << DCM_CFG_offDLMB )
#define DCM_CFG_mskBSAV ( 0x3 << DCM_CFG_offBSAV )
/******************************************************************************
* cr3: MMU_CFG (MMU Configuration Register)
*****************************************************************************/
#define MMU_CFG_offMMPS 0 /* Memory management protection scheme */
#define MMU_CFG_offMMPV 2 /* Memory management protection version number */
#define MMU_CFG_offFATB 7 /* Fully-associative or non-fully-associative TLB */
#ifdef CONFIG_FULL_ASSOC
#define MMU_CFG_offFATBSZ 8 /* TLB entries while using full-associative TLB */
#else
#define MMU_CFG_offTBW 8 /* TLB ways(non-associative) TBS */
#define MMU_CFG_offTBS 11 /* TLB sets per way(non-associative) TBS */
/* bit 14:14 reserved */
#endif
#define MMU_CFG_offEP8MIN4 15 /* 8KB page supported while minimum page is 4KB */
#define MMU_CFG_offfEPSZ 16 /* Extra page size supported */
#define MMU_CFG_offTLBLCK 24 /* TLB locking support */
#define MMU_CFG_offHPTWK 25 /* Hardware Page Table Walker implemented */
#define MMU_CFG_offDE 26 /* Default endian */
#define MMU_CFG_offNTPT 27 /* Partitions for non-translated attributes */
#define MMU_CFG_offIVTB 28 /* Invisible TLB */
#define MMU_CFG_offVLPT 29 /* VLPT for fast TLB fill handling implemented */
#define MMU_CFG_offNTME 30 /* Non-translated VA to PA mapping */
/* bit 31 reserved */
#define MMU_CFG_mskMMPS ( 0x3 << MMU_CFG_offMMPS )
#define MMU_CFG_mskMMPV ( 0x1F << MMU_CFG_offMMPV )
#define MMU_CFG_mskFATB ( 0x1 << MMU_CFG_offFATB )
#ifdef CONFIG_FULL_ASSOC
#define MMU_CFG_mskFATBSZ ( 0x7f << MMU_CFG_offFATBSZ )
#else
#define MMU_CFG_mskTBW ( 0x7 << MMU_CFG_offTBW )
#define MMU_CFG_mskTBS ( 0x7 << MMU_CFG_offTBS )
#endif
#define MMU_CFG_mskEP8MIN4 ( 0x1 << MMU_CFG_offEP8MIN4 )
#define MMU_CFG_mskfEPSZ ( 0xFF << MMU_CFG_offfEPSZ )
#define MMU_CFG_mskTLBLCK ( 0x1 << MMU_CFG_offTLBLCK )
#define MMU_CFG_mskHPTWK ( 0x1 << MMU_CFG_offHPTWK )
#define MMU_CFG_mskDE ( 0x1 << MMU_CFG_offDE )
#define MMU_CFG_mskNTPT ( 0x1 << MMU_CFG_offNTPT )
#define MMU_CFG_mskIVTB ( 0x1 << MMU_CFG_offIVTB )
#define MMU_CFG_mskVLPT ( 0x1 << MMU_CFG_offVLPT )
#define MMU_CFG_mskNTME ( 0x1 << MMU_CFG_offNTME )
/******************************************************************************
* cr4: MSC_CFG (Misc Configuration Register)
*****************************************************************************/
#define MSC_CFG_offEDM 0
#define MSC_CFG_offLMDMA 1
#define MSC_CFG_offPFM 2
#define MSC_CFG_offHSMP 3
#define MSC_CFG_offTRACE 4
#define MSC_CFG_offDIV 5
#define MSC_CFG_offMAC 6
#define MSC_CFG_offAUDIO 7
#define MSC_CFG_offL2C 9
#define MSC_CFG_offRDREG 10
#define MSC_CFG_offADR24 11
#define MSC_CFG_offINTLC 12
/* bit 13:31 reserved */
#define MSC_CFG_mskEDM ( 0x1 << MSC_CFG_offEDM )
#define MSC_CFG_mskLMDMA ( 0x1 << MSC_CFG_offLMDMA )
#define MSC_CFG_mskPFM ( 0x1 << MSC_CFG_offPFM )
#define MSC_CFG_mskHSMP ( 0x1 << MSC_CFG_offHSMP )
#define MSC_CFG_mskTRACE ( 0x1 << MSC_CFG_offTRACE )
#define MSC_CFG_mskDIV ( 0x1 << MSC_CFG_offDIV )
#define MSC_CFG_mskMAC ( 0x1 << MSC_CFG_offMAC )
#define MSC_CFG_mskAUDIO ( 0x3 << MSC_CFG_offAUDIO )
#define MSC_CFG_mskL2C ( 0x1 << MSC_CFG_offL2C )
#define MSC_CFG_mskRDREG ( 0x1 << MSC_CFG_offRDREG )
#define MSC_CFG_mskADR24 ( 0x1 << MSC_CFG_offADR24 )
#define MSC_CFG_mskINTLC ( 0x1 << MSC_CFG_offINTLC )
/******************************************************************************
* cr5: CORE_CFG (Core Identification Register)
*****************************************************************************/
#define CORE_ID_offCOREID 0
/* bit 4:31 reserved */
#define CORE_ID_mskCOREID ( 0xF << CORE_ID_offCOREID )
/******************************************************************************
* cr6: FUCOP_EXIST (FPU and Coprocessor Existence Configuration Register)
*****************************************************************************/
#define FUCOP_EXIST_offCP0EX 0
#define FUCOP_EXIST_offCP1EX 1
#define FUCOP_EXIST_offCP2EX 2
#define FUCOP_EXIST_offCP3EX 3
#define FUCOP_EXIST_offCP0ISFPU 31
#define FUCOP_EXIST_mskCP0EX ( 0x1 << FUCOP_EXIST_offCP0EX )
#define FUCOP_EXIST_mskCP1EX ( 0x1 << FUCOP_EXIST_offCP1EX )
#define FUCOP_EXIST_mskCP2EX ( 0x1 << FUCOP_EXIST_offCP2EX )
#define FUCOP_EXIST_mskCP3EX ( 0x1 << FUCOP_EXIST_offCP3EX )
#define FUCOP_EXIST_mskCP0ISFPU ( 0x1 << FUCOP_EXIST_offCP0ISFPU )
/******************************************************************************
* ir0: PSW (Processor Status Word Register)
* ir1: IPSW (Interruption PSW Register)
* ir2: P_IPSW (Previous IPSW Register)
*****************************************************************************/
#define PSW_offGIE 0 /* Global Interrupt Enable */
#define PSW_offINTL 1 /* Interruption Stack Level */
#define PSW_offPOM 3 /* Processor Operation Mode, User/Superuser */
#define PSW_offBE 5 /* Endianness for data memory access, 1:MSB, 0:LSB */
#define PSW_offIT 6 /* Enable instruction address translation */
#define PSW_offDT 7 /* Enable data address translation */
#define PSW_offIME 8 /* Instruction Machine Error flag */
#define PSW_offDME 9 /* Data Machine Error flag */
#define PSW_offDEX 10 /* Debug Exception */
#define PSW_offHSS 11 /* Hardware Single Stepping */
#define PSW_offIFCON 15 /* Hardware Single Stepping */
/* bit 12:31 reserved */
#define PSW_mskGIE ( 0x1 << PSW_offGIE )
#define PSW_mskINTL ( 0x3 << PSW_offINTL )
#define PSW_mskPOM ( 0x3 << PSW_offPOM )
#define PSW_mskBE ( 0x1 << PSW_offBE )
#define PSW_mskIT ( 0x1 << PSW_offIT )
#define PSW_mskDT ( 0x1 << PSW_offDT )
#define PSW_mskIME ( 0x1 << PSW_offIME )
#define PSW_mskDME ( 0x1 << PSW_offDME )
#define PSW_mskDEX ( 0x1 << PSW_offDEX )
#define PSW_mskHSS ( 0x1 << PSW_offHSS )
#define PSW_mskIFCON ( 0x1 << PSW_offIFCON )
/******************************************************************************
* ir3: IVB (Interruption Vector Base Register)
*****************************************************************************/
/* bit 4:12 reserved */
#define IVB_offEVIC 13 /* External Vector Interrupt Controller mode */
#define IVB_offESZ 14 /* Size of each vector entry */
#define IVB_offIVBASE 16 /* BasePA of interrupt vector table */
#define IVB_offNIVIC 1 /* Number of input for Internal Vector Interrupt Controller*/
#define IVB_offPROG_PRI_LVL 0
#define IVB_mskEVIC ( 0x1 << IVB_offEVIC )
#define IVB_mskESZ ( 0x3 << IVB_offESZ )
#define IVB_mskIVBASE ( 0xFFFF << IVB_offIVBASE )
#define IVB_mskNIVIC ( 0x7 << IVB_offNIVIC)
#define IVB_mskPROG_PRI_LVL ( 0x1 << IVB_offPROG_PRI_LVL)
/******************************************************************************
* ir4: EVA (Exception Virtual Address Register)
* ir5: P_EVA (Previous EVA Register)
*****************************************************************************/
/* This register contains the VA that causes the exception */
/******************************************************************************
* ir6: ITYPE (Interruption Type Register)
* ir7: P_ITYPE (Previous ITYPE Register)
*****************************************************************************/
#define ITYPE_offETYPE 0 /* Exception Type */
#define ITYPE_offINST 4 /* Exception caused by insn fetch or data access */
/* bit 5:15 reserved */
#define ITYPE_offSWID 16 /* SWID of debugging exception */
/* bit 31:31 reserved */
#define ITYPE_mskETYPE ( 0xF << ITYPE_offETYPE )
#define ITYPE_mskINST ( 0x1 << ITYPE_offINST )
#define ITYPE_mskSWID ( 0x7FFF << ITYPE_offSWID )
/******************************************************************************
* ir8: MERR (Machine Error Log Register)
*****************************************************************************/
/* bit 0:30 reserved */
#define MERR_offBUSERR 31 /* Bus error caused by a load insn */
#define MERR_mskBUSERR ( 0x1 << MERR_offBUSERR )
/******************************************************************************
* ir9: IPC (Interruption Program Counter Register)
* ir10: P_IPC (Previous IPC Register)
* ir11: OIPC (Overflow Interruption Program Counter Register)
*****************************************************************************/
/* This is the shadow stack register of the Program Counter */
/******************************************************************************
* ir12: P_P0 (Previous P0 Register)
* ir13: P_P1 (Previous P1 Register)
*****************************************************************************/
/* These are shadow registers of $p0 and $p1 */
/******************************************************************************
* ir14: INT_MASK (Interruption Masking Register)
*****************************************************************************/
#define INT_MASK_offH0IM 0 /* Hardware Interrupt 0 Mask bit */
#define INT_MASK_offH1IM 1 /* Hardware Interrupt 1 Mask bit */
#define INT_MASK_offH2IM 2 /* Hardware Interrupt 2 Mask bit */
#define INT_MASK_offH3IM 3 /* Hardware Interrupt 3 Mask bit */
#define INT_MASK_offH4IM 4 /* Hardware Interrupt 4 Mask bit */
#define INT_MASK_offH5IM 5 /* Hardware Interrupt 5 Mask bit */
/* bit 6:15 reserved */
#define INT_MASK_offSIM 16 /* Software Interrupt Mask bit */
/* bit 17:29 reserved */
#define INT_MASK_offIDIVZE 30 /* Enable detection for Divide-By-Zero */
#define INT_MASK_offDSSIM 31 /* Default Single Stepping Interruption Mask */
#define INT_MASK_mskH0IM ( 0x1 << INT_MASK_offH0IM )
#define INT_MASK_mskH1IM ( 0x1 << INT_MASK_offH1IM )
#define INT_MASK_mskH2IM ( 0x1 << INT_MASK_offH2IM )
#define INT_MASK_mskH3IM ( 0x1 << INT_MASK_offH3IM )
#define INT_MASK_mskH4IM ( 0x1 << INT_MASK_offH4IM )
#define INT_MASK_mskH5IM ( 0x1 << INT_MASK_offH5IM )
#define INT_MASK_mskSIM ( 0x1 << INT_MASK_offSIM )
#define INT_MASK_mskIDIVZE ( 0x1 << INT_MASK_offIDIVZE )
#define INT_MASK_mskDSSIM ( 0x1 << INT_MASK_offDSSIM )
/******************************************************************************
* ir15: INT_PEND (Interrupt Pending Register)
*****************************************************************************/
#define INT_PEND_offH0I 0 /* Hardware Interrupt 0 pending bit */
#define INT_PEND_offH1I 1 /* Hardware Interrupt 1 pending bit */
#define INT_PEND_offH2I 2 /* Hardware Interrupt 2 pending bit */
#define INT_PEND_offH3I 3 /* Hardware Interrupt 3 pending bit */
#define INT_PEND_offH4I 4 /* Hardware Interrupt 4 pending bit */
#define INT_PEND_offH5I 5 /* Hardware Interrupt 5 pending bit */
#define INT_PEND_offCIPL 0 /* Current Interrupt Priority Level */
/* bit 6:15 reserved */
#define INT_PEND_offSWI 16 /* Software Interrupt pending bit */
/* bit 17:31 reserved */
#define INT_PEND_mskH0I ( 0x1 << INT_PEND_offH0I )
#define INT_PEND_mskH1I ( 0x1 << INT_PEND_offH1I )
#define INT_PEND_mskH2I ( 0x1 << INT_PEND_offH2I )
#define INT_PEND_mskH3I ( 0x1 << INT_PEND_offH3I )
#define INT_PEND_mskH4I ( 0x1 << INT_PEND_offH4I )
#define INT_PEND_mskH5I ( 0x1 << INT_PEND_offH5I )
#define INT_PEND_mskCIPL ( 0x1 << INT_PEND_offCIPL )
#define INT_PEND_mskSWI ( 0x1 << INT_PEND_offSWI )
/******************************************************************************
* mr0: MMU_CTL (MMU Control Register)
*****************************************************************************/
#define MMU_CTL_offD 0 /* Default minimum page size */
#define MMU_CTL_offNTC0 1 /* Non-Translated Cachebility of partition 0 */
#define MMU_CTL_offNTC1 3 /* Non-Translated Cachebility of partition 1 */
#define MMU_CTL_offNTC2 5 /* Non-Translated Cachebility of partition 2 */
#define MMU_CTL_offNTC3 7 /* Non-Translated Cachebility of partition 3 */
#define MMU_CTL_offTBALCK 9 /* TLB all-lock resolution scheme */
#define MMU_CTL_offMPZIU 10 /* Multiple Page Size In Use bit */
#define MMU_CTL_offNTM0 11 /* Non-Translated VA to PA of partition 0 */
#define MMU_CTL_offNTM1 13 /* Non-Translated VA to PA of partition 1 */
#define MMU_CTL_offNTM2 15 /* Non-Translated VA to PA of partition 2 */
#define MMU_CTL_offNTM3 17 /* Non-Translated VA to PA of partition 3 */
/* bit 19:31 reserved */
#define MMU_CTL_mskD ( 0x1 << MMU_CTL_offD )
#define MMU_CTL_mskNTC0 ( 0x3 << MMU_CTL_offNTC0 )
#define MMU_CTL_mskNTC1 ( 0x3 << MMU_CTL_offNTC1 )
#define MMU_CTL_mskNTC2 ( 0x3 << MMU_CTL_offNTC2 )
#define MMU_CTL_mskNTC3 ( 0x3 << MMU_CTL_offNTC3 )
#define MMU_CTL_mskTBALCK ( 0x1 << MMU_CTL_offTBALCK )
#define MMU_CTL_mskMPZIU ( 0x1 << MMU_CTL_offMPZIU )
#define MMU_CTL_mskNTM0 ( 0x3 << MMU_CTL_offNTM0 )
#define MMU_CTL_mskNTM1 ( 0x3 << MMU_CTL_offNTM1 )
#define MMU_CTL_mskNTM2 ( 0x3 << MMU_CTL_offNTM2 )
#define MMU_CTL_mskNTM3 ( 0x3 << MMU_CTL_offNTM3 )
/******************************************************************************
* mr1: L1_PPTB (L1 Physical Page Table Base Register)
*****************************************************************************/
#define L1_PPTB_offNV 0 /* Enable Hardware Page Table Walker (HPTWK) */
/* bit 1:11 reserved */
#define L1_PPTB_offBASE 12 /* First level physical page table base address */
#define L1_PPTB_mskNV ( 0x1 << L1_PPTB_offNV )
#define L1_PPTB_mskBASE ( 0xFFFFF << L1_PPTB_offBASE )
/******************************************************************************
* mr2: TLB_VPN (TLB Access VPN Register)
*****************************************************************************/
/* bit 0:11 reserved */
#define TLB_VPN_offVPN 12 /* Virtual Page Number */
#define TLB_VPN_mskVPN ( 0xFFFFF << TLB_VPN_offVPN )
/******************************************************************************
* mr3: TLB_DATA (TLB Access Data Register)
*****************************************************************************/
#define TLB_DATA_offV 0 /* PTE is valid and present */
#define TLB_DATA_offM 1 /* Page read/write access privilege */
#define TLB_DATA_offD 4 /* Dirty bit */
#define TLB_DATA_offX 5 /* Executable bit */
#define TLB_DATA_offA 6 /* Access bit */
#define TLB_DATA_offG 7 /* Global page (shared across contexts) */
#define TLB_DATA_offC 8 /* Cacheability atribute */
/* bit 11:11 reserved */
#define TLB_DATA_offPPN 12 /* Phisical Page Number */
#define TLB_DATA_mskV ( 0x1 << TLB_DATA_offV )
#define TLB_DATA_mskM ( 0x7 << TLB_DATA_offM )
#define TLB_DATA_mskD ( 0x1 << TLB_DATA_offD )
#define TLB_DATA_mskX ( 0x1 << TLB_DATA_offX )
#define TLB_DATA_mskA ( 0x1 << TLB_DATA_offA )
#define TLB_DATA_mskG ( 0x1 << TLB_DATA_offG )
#define TLB_DATA_mskC ( 0x7 << TLB_DATA_offC )
#define TLB_DATA_mskPPN ( 0xFFFFF << TLB_DATA_offPPN )
/******************************************************************************
* mr4: TLB_MISC (TLB Access Misc Register)
*****************************************************************************/
#define TLB_MISC_offACC_PSZ 0 /* Page size of a PTE entry */
#define TLB_MISC_offCID 4 /* Context id */
/* bit 13:31 reserved */
#define TLB_MISC_mskACC_PSZ ( 0xF << TLB_MISC_offACC_PSZ )
#define TLB_MISC_mskCID ( 0x1FF << TLB_MISC_offCID )
/******************************************************************************
* mr5: VLPT_IDX (Virtual Linear Page Table Index Register)
*****************************************************************************/
#define VLPT_IDX_offZERO 0 /* Always 0 */
#define VLPT_IDX_offEVPN 2 /* Exception Virtual Page Number */
#define VLPT_IDX_offVLPTB 22 /* Base VA of VLPT */
#define VLPT_IDX_mskZERO ( 0x3 << VLPT_IDX_offZERO )
#define VLPT_IDX_mskEVPN ( 0xFFFFF << VLPT_IDX_offEVPN )
#define VLPT_IDX_mskVLPTB ( 0x3FF << VLPT_IDX_offVLPTB )
/******************************************************************************
* mr6: ILMB (Instruction Local Memory Base Register)
*****************************************************************************/
#define ILMB_offIEN 0 /* Enable ILM */
#define ILMB_offILMSZ 1 /* Size of ILM */
/* bit 5:19 reserved */
#define ILMB_offIBPA 20 /* Base PA of ILM */
#define ILMB_mskIEN ( 0x1 << ILMB_offIEN )
#define ILMB_mskILMSZ ( 0xF << ILMB_offILMSZ )
#define ILMB_mskIBPA ( 0xFFF << ILMB_offIBPA )
/******************************************************************************
* mr7: DLMB (Data Local Memory Base Register)
*****************************************************************************/
#define DLMB_offDEN 0 /* Enable DLM */
#define DLMB_offDLMSZ 1 /* Size of DLM */
#define DLMB_offDBM 5 /* Enable Double-Buffer Mode for DLM */
#define DLMB_offDBB 6 /* Double-buffer bank which can be accessed by the processor */
/* bit 7:19 reserved */
#define DLMB_offDBPA 20 /* Base PA of DLM */
#define DLMB_mskDEN ( 0x1 << DLMB_offDEN )
#define DLMB_mskDLMSZ ( 0xF << DLMB_offDLMSZ )
#define DLMB_mskDBM ( 0x1 << DLMB_offDBM )
#define DLMB_mskDBB ( 0x1 << DLMB_offDBB )
#define DLMB_mskDBPA ( 0xFFF << DLMB_offDBPA )
/******************************************************************************
* mr8: CACHE_CTL (Cache Control Register)
*****************************************************************************/
#define CACHE_CTL_offIC_EN 0 /* Enable I-cache */
#define CACHE_CTL_offDC_EN 1 /* Enable D-cache */
#define CACHE_CTL_offICALCK 2 /* I-cache all-lock resolution scheme */
#define CACHE_CTL_offDCALCK 3 /* D-cache all-lock resolution scheme */
#define CACHE_CTL_offDCCWF 4 /* Enable D-cache Critical Word Forwarding */
#define CACHE_CTL_offDCPMW 5 /* Enable D-cache concurrent miss and write-back processing */
/* bit 6:31 reserved */
#define CACHE_CTL_mskIC_EN ( 0x1 << CACHE_CTL_offIC_EN )
#define CACHE_CTL_mskDC_EN ( 0x1 << CACHE_CTL_offDC_EN )
#define CACHE_CTL_mskICALCK ( 0x1 << CACHE_CTL_offICALCK )
#define CACHE_CTL_mskDCALCK ( 0x1 << CACHE_CTL_offDCALCK )
#define CACHE_CTL_mskDCCWF ( 0x1 << CACHE_CTL_offDCCWF )
#define CACHE_CTL_mskDCPMW ( 0x1 << CACHE_CTL_offDCPMW )
/******************************************************************************
* mr9: HSMP_SADDR (High Speed Memory Port Starting Address)
*****************************************************************************/
#define HSMP_SADDR_offEN 0 /* Enable control bit for the High Speed Memory port */
/* bit 1:19 reserved */
#define HSMP_SADDR_offRANGE 1 /* Denote the address range (only defined in HSMP v2 ) */
#define HSMP_SADDR_offSADJ1DR 20 /* Starting base PA of the High Speed Memory Port region */
#define HSMP_SADDR_mskEN ( 0x1 << HSMP_SADDR_offEN )
#define HSMP_SADDR_mskRANGE ( 0xFFF << HSMP_SADDR_offRANGE )
#define HSMP_SADDR_mskSADDR ( 0xFFF << HSMP_SADDR_offSADDR )
/******************************************************************************
* mr10: HSMP_EADDR (High Speed Memory Port Ending Address)
*****************************************************************************/
/* bit 0:19 reserved */
#define HSMP_EADDR_offEADDR 20
#define HSMP_EADDR_mskEADDR ( 0xFFF << HSMP_EADDR_offEADDR )
/******************************************************************************
* dr0+(n*5): BPCn (n=0-7) (Breakpoint Control Register)
*****************************************************************************/
#define BPC_offWP 0 /* Configuration of BPAn */
#define BPC_offEL 1 /* Enable BPAn */
#define BPC_offS 2 /* Data address comparison for a store instruction */
#define BPC_offP 3 /* Compared data address is PA */
#define BPC_offC 4 /* CID value is compared with the BPCIDn register */
#define BPC_offBE0 5 /* Enable byte mask for the comparison with register */
#define BPC_offBE1 6 /* Enable byte mask for the comparison with register */
#define BPC_offBE2 7 /* Enable byte mask for the comparison with register */
#define BPC_offBE3 8 /* Enable byte mask for the comparison with register */
#define BPC_offT 9 /* Enable breakpoint Embedded Tracer triggering operation */
#define BPC_mskWP ( 0x1 << BPC_offWP )
#define BPC_mskEL ( 0x1 << BPC_offEL )
#define BPC_mskS ( 0x1 << BPC_offS )
#define BPC_mskP ( 0x1 << BPC_offP )
#define BPC_mskC ( 0x1 << BPC_offC )
#define BPC_mskBE0 ( 0x1 << BPC_offBE0 )
#define BPC_mskBE1 ( 0x1 << BPC_offBE1 )
#define BPC_mskBE2 ( 0x1 << BPC_offBE2 )
#define BPC_mskBE3 ( 0x1 << BPC_offBE3 )
#define BPC_mskT ( 0x1 << BPC_offT )
/******************************************************************************
* dr1+(n*5): BPAn (n=0-7) (Breakpoint Address Register)
*****************************************************************************/
/* These registers contain break point address */
/******************************************************************************
* dr2+(n*5): BPAMn (n=0-7) (Breakpoint Address Mask Register)
*****************************************************************************/
/* These registerd contain the address comparison mask for the BPAn register */
/******************************************************************************
* dr3+(n*5): BPVn (n=0-7) Breakpoint Data Value Register
*****************************************************************************/
/* The BPVn register contains the data value that will be compared with the
* incoming load/store data value */
/******************************************************************************
* dr4+(n*5): BPCIDn (n=0-7) (Breakpoint Context ID Register)
*****************************************************************************/
#define BPCID_offCID 0 /* CID that will be compared with a process's CID */
/* bit 9:31 reserved */
#define BPCID_mskCID ( 0x1FF << BPCID_offCID )
/******************************************************************************
* dr40: EDM_CFG (EDM Configuration Register)
*****************************************************************************/
#define EDM_CFG_offBC 0 /* Number of hardware breakpoint sets implemented */
#define EDM_CFG_offDIMU 3 /* Debug Instruction Memory Unit exists */
/* bit 4:15 reserved */
#define EDM_CFG_offVER 16 /* EDM version */
#define EDM_CFG_mskBC ( 0x7 << EDM_CFG_offBC )
#define EDM_CFG_mskDIMU ( 0x1 << EDM_CFG_offDIMU )
#define EDM_CFG_mskVER ( 0xFFFF << EDM_CFG_offVER )
/******************************************************************************
* dr41: EDMSW (EDM Status Word)
*****************************************************************************/
#define EDMSW_offWV 0 /* Write Valid */
#define EDMSW_offRV 1 /* Read Valid */
#define EDMSW_offDE 2 /* Debug exception has occurred for this core */
/* bit 3:31 reserved */
#define EDMSW_mskWV ( 0x1 << EDMSW_offWV )
#define EDMSW_mskRV ( 0x1 << EDMSW_offRV )
#define EDMSW_mskDE ( 0x1 << EDMSW_offDE )
/******************************************************************************
* dr42: EDM_CTL (EDM Control Register)
*****************************************************************************/
/* bit 0:30 reserved */
#define EDM_CTL_offDEH_SEL 31 /* Controls where debug exception is directed to */
#define EDM_CTL_mskDEH_SEL ( 0x1 << EDM_CTL_offDEH_SEL )
/******************************************************************************
* dr43: EDM_DTR (EDM Data Transfer Register)
*****************************************************************************/
/* This is used to exchange data between the embedded EDM logic
* and the processor core */
/******************************************************************************
* dr44: BPMTC (Breakpoint Match Trigger Counter Register)
*****************************************************************************/
#define BPMTC_offBPMTC 0 /* Breakpoint match trigger counter value */
/* bit 16:31 reserved */
#define BPMTC_mskBPMTC ( 0xFFFF << BPMTC_offBPMTC )
/******************************************************************************
* dr45: DIMBR (Debug Instruction Memory Base Register)
*****************************************************************************/
/* bit 0:11 reserved */
#define DIMBR_offDIMB 12 /* Base address of the Debug Instruction Memory (DIM)*/
#define DIMBR_mskDIMB ( 0xFFFFF << DIMBR_offDIMB )
/******************************************************************************
* dr46: TECR0(Trigger Event Control register 0)
* dr47: TECR1 (Trigger Event Control register 1)
*****************************************************************************/
#define TECR_offBP 0 /* Controld which BP is used as a trigger source */
#define TECR_offNMI 8 /* Use NMI as a trigger source */
#define TECR_offHWINT 9 /* Corresponding interrupt is used as a trigger source */
#define TECR_offEVIC 15 /* Enable HWINT as a trigger source in EVIC mode */
#define TECR_offSYS 16 /* Enable SYSCALL instruction as a trigger source */
#define TECR_offDBG 17 /* Enable debug exception as a trigger source */
#define TECR_offMRE 18 /* Enable MMU related exception as a trigger source */
#define TECR_offE 19 /* An exception is used as a trigger source */
/* bit 20:30 reserved */
#define TECR_offL 31 /* Link/Cascade TECR0 trigger event to TECR1 trigger event */
#define TECR_mskBP ( 0xFF << TECR_offBP )
#define TECR_mskNMI ( 0x1 << TECR_offBNMI )
#define TECR_mskHWINT ( 0x3F << TECR_offBHWINT )
#define TECR_mskEVIC ( 0x1 << TECR_offBEVIC )
#define TECR_mskSYS ( 0x1 << TECR_offBSYS )
#define TECR_mskDBG ( 0x1 << TECR_offBDBG )
#define TECR_mskMRE ( 0x1 << TECR_offBMRE )
#define TECR_mskE ( 0x1 << TECR_offE )
#define TECR_mskL ( 0x1 << TECR_offL )
/******************************************************************************
* pfr0-2: PFMC0-2 (Performance Counter Register 0-2)
*****************************************************************************/
/* These registers contains performance event count */
/******************************************************************************
* pfr3: PFM_CTL (Performance Counter Control Register)
*****************************************************************************/
#define PFM_CTL_offEN0 0 /* Enable PFMC0 */
#define PFM_CTL_offEN1 1 /* Enable PFMC1 */
#define PFM_CTL_offEN2 2 /* Enable PFMC2 */
#define PFM_CTL_offIE0 3 /* Enable interrupt for PFMC0 */
#define PFM_CTL_offIE1 4 /* Enable interrupt for PFMC1 */
#define PFM_CTL_offIE2 5 /* Enable interrupt for PFMC2 */
#define PFM_CTL_offOVF0 6 /* Overflow bit of PFMC0 */
#define PFM_CTL_offOVF1 7 /* Overflow bit of PFMC1 */
#define PFM_CTL_offOVF2 8 /* Overflow bit of PFMC2 */
#define PFM_CTL_offKS0 9 /* Enable superuser mode event counting for PFMC0 */
#define PFM_CTL_offKS1 10 /* Enable superuser mode event counting for PFMC1 */
#define PFM_CTL_offKS2 11 /* Enable superuser mode event counting for PFMC2 */
#define PFM_CTL_offKU0 12 /* Enable user mode event counting for PFMC0 */
#define PFM_CTL_offKU1 13 /* Enable user mode event counting for PFMC1 */
#define PFM_CTL_offKU2 14 /* Enable user mode event counting for PFMC2 */
#define PFM_CTL_offSEL0 15 /* The event selection for PFMC0 */
#define PFM_CTL_offSEL1 21 /* The event selection for PFMC1 */
#define PFM_CTL_offSEL2 27 /* The event selection for PFMC2 */
/* bit 28:31 reserved */
#define PFM_CTL_mskEN0 ( 0x01 << PFM_CTL_offEN0 )
#define PFM_CTL_mskEN1 ( 0x01 << PFM_CTL_offEN1 )
#define PFM_CTL_mskEN2 ( 0x01 << PFM_CTL_offEN2 )
#define PFM_CTL_mskIE0 ( 0x01 << PFM_CTL_offIE0 )
#define PFM_CTL_mskIE1 ( 0x01 << PFM_CTL_offIE1 )
#define PFM_CTL_mskIE2 ( 0x01 << PFM_CTL_offIE2 )
#define PFM_CTL_mskOVF0 ( 0x01 << PFM_CTL_offOVF0 )
#define PFM_CTL_mskOVF1 ( 0x01 << PFM_CTL_offOVF1 )
#define PFM_CTL_mskOVF2 ( 0x01 << PFM_CTL_offOVF2 )
#define PFM_CTL_mskKS0 ( 0x01 << PFM_CTL_offKS0 )
#define PFM_CTL_mskKS1 ( 0x01 << PFM_CTL_offKS1 )
#define PFM_CTL_mskKS2 ( 0x01 << PFM_CTL_offKS2 )
#define PFM_CTL_mskKU0 ( 0x01 << PFM_CTL_offKU0 )
#define PFM_CTL_mskKU1 ( 0x01 << PFM_CTL_offKU1 )
#define PFM_CTL_mskKU2 ( 0x01 << PFM_CTL_offKU2 )
#define PFM_CTL_mskSEL0 ( 0x01 << PFM_CTL_offSEL0 )
#define PFM_CTL_mskSEL1 ( 0x3F << PFM_CTL_offSEL1 )
#define PFM_CTL_mskSEL2 ( 0x3F << PFM_CTL_offSEL2 )
/******************************************************************************
* SDZ_CTL (Structure Downsizing Control Register)
*****************************************************************************/
#define SDZ_CTL_offICDZ 0 /* I-cache downsizing control */
#define SDZ_CTL_offDCDZ 3 /* D-cache downsizing control */
#define SDZ_CTL_offMTBDZ 6 /* MTLB downsizing control */
#define SDZ_CTL_offBTBDZ 9 /* Branch Target Table downsizing control */
/* bit 12:31 reserved */
#define SDZ_CTL_mskICDZ ( 0x07 << SDZ_CTL_offICDZ )
#define SDZ_CTL_mskDCDZ ( 0x07 << SDZ_CTL_offDCDZ )
#define SDZ_CTL_mskMTBDZ ( 0x07 << SDZ_CTL_offMTBDZ )
#define SDZ_CTL_mskBTBDZ ( 0x07 << SDZ_CTL_offBTBDZ )
/******************************************************************************
* N12MISC_CTL (N12 Miscellaneous Control Register)
*****************************************************************************/
#define N12MISC_CTL_offBTB 0 /* Disable Branch Target Buffer */
#define N12MISC_CTL_offRTP 1 /* Disable Return Target Predictor */
#define N12MISC_CTL_offPTEEPF 2 /* Disable HPTWK L2 PTE pefetch */
/* bit 3:31 reserved */
#define N12MISC_CTL_makBTB ( 0x1 << N12MISC_CTL_makBTB )
#define N12MISC_CTL_makRTP ( 0x1 << N12MISC_CTL_makRTP )
#define N12MISC_CTL_makPTEEPF ( 0x1 << N12MISC_CTL_makPTEEPF )
/******************************************************************************
* PRUSR_ACC_CTL (Privileged Resource User Access Control Registers)
*****************************************************************************/
#define PRUSR_ACC_CTL_offDMA_EN 0 /* Allow user mode access of DMA registers */
#define PRUSR_ACC_CTL_offPFM_EN 1 /* Allow user mode access of PFM registers */
#define PRUSR_ACC_CTL_mskDMA_EN ( 0x1 << PRUSR_ACC_CTL_offDMA_EN )
#define PRUSR_ACC_CTL_mskPFM_EN ( 0x1 << PRUSR_ACC_CTL_offPFM_EN )
/******************************************************************************
* dmar0: DMA_CFG (DMA Configuration Register)
*****************************************************************************/
#define DMA_CFG_offNCHN 0 /* The number of DMA channels implemented */
#define DMA_CFG_offUNEA 2 /* Un-aligned External Address transfer feature */
#define DMA_CFG_off2DET 3 /* 2-D Element Transfer feature */
/* bit 4:15 reserved */
#define DMA_CFG_offVER 16 /* DMA architecture and implementation version */
#define DMA_CFG_mskNCHN ( 0x3 << DMA_CFG_offNCHN )
#define DMA_CFG_mskUNEA ( 0x1 << DMA_CFG_offUNEA )
#define DMA_CFG_msk2DET ( 0x1 << DMA_CFG_off2DET )
#define DMA_CFG_mskVER ( 0xFFFF << DMA_CFG_offVER )
/******************************************************************************
* dmar1: DMA_GCSW (DMA Global Control and Status Word Register)
*****************************************************************************/
#define DMA_GCSW_offC0STAT 0 /* DMA channel 0 state */
#define DMA_GCSW_offC1STAT 3 /* DMA channel 1 state */
/* bit 6:11 reserved */
#define DMA_GCSW_offC0INT 12 /* DMA channel 0 generate interrupt */
#define DMA_GCSW_offC1INT 13 /* DMA channel 1 generate interrupt */
/* bit 14:30 reserved */
#define DMA_GCSW_offEN 31 /* Enable DMA engine */
#define DMA_GCSW_mskC0STAT ( 0x7 << DMA_GCSW_offC0STAT )
#define DMA_GCSW_mskC1STAT ( 0x7 << DMA_GCSW_offC1STAT )
#define DMA_GCSW_mskC0INT ( 0x1 << DMA_GCSW_offC0INT )
#define DMA_GCSW_mskC1INT ( 0x1 << DMA_GCSW_offC1INT )
#define DMA_GCSW_mskEN ( 0x1 << DMA_GCSW_offEN )
/******************************************************************************
* dmar2: DMA_CHNSEL (DMA Channel Selection Register)
*****************************************************************************/
#define DMA_CHNSEL_offCHAN 0 /* Selected channel number */
/* bit 2:31 reserved */
#define DMA_CHNSEL_mskCHAN ( 0x3 << DMA_CHNSEL_offCHAN )
/******************************************************************************
* dmar3: DMA_ACT (DMA Action Register)
*****************************************************************************/
#define DMA_ACT_offACMD 0 /* DMA Action Command */
/* bit 2:31 reserved */
#define DMA_ACT_mskACMD ( 0x3 << DMA_ACT_offACMD )
/******************************************************************************
* dmar4: DMA_SETUP (DMA Setup Register)
*****************************************************************************/
#define DMA_SETUP_offLM 0 /* Local Memory Selection */
#define DMA_SETUP_offTDIR 1 /* Transfer Direction */
#define DMA_SETUP_offTES 2 /* Transfer Element Size */
#define DMA_SETUP_offESTR 4 /* External memory transfer Stride */
#define DMA_SETUP_offCIE 16 /* Interrupt Enable on Completion */
#define DMA_SETUP_offSIE 17 /* Interrupt Enable on explicit Stop */
#define DMA_SETUP_offEIE 18 /* Interrupt Enable on Error */
#define DMA_SETUP_offUE 19 /* Enable the Un-aligned External Address */
#define DMA_SETUP_off2DE 20 /* Enable the 2-D External Transfer */
#define DMA_SETUP_offCOA 21 /* Transfer Coalescable */
/* bit 22:31 reserved */
#define DMA_SETUP_mskLM ( 0x1 << DMA_SETUP_offLM )
#define DMA_SETUP_mskTDIR ( 0x1 << DMA_SETUP_offTDIR )
#define DMA_SETUP_mskTES ( 0x3 << DMA_SETUP_offTES )
#define DMA_SETUP_mskESTR ( 0xFFF << DMA_SETUP_offESTR )
#define DMA_SETUP_mskCIE ( 0x1 << DMA_SETUP_offCIE )
#define DMA_SETUP_mskSIE ( 0x1 << DMA_SETUP_offSIE )
#define DMA_SETUP_mskEIE ( 0x1 << DMA_SETUP_offEIE )
#define DMA_SETUP_mskUE ( 0x1 << DMA_SETUP_offUE )
#define DMA_SETUP_msk2DE ( 0x1 << DMA_SETUP_off2DE )
#define DMA_SETUP_mskCOA ( 0x1 << DMA_SETUP_offCOA )
/******************************************************************************
* dmar5: DMA_ISADDR (DMA Internal Start Address Register)
*****************************************************************************/
#define DMA_ISADDR_offISADDR 0 /* Internal Start Address */
/* bit 20:31 reserved */
#define DMA_ISADDR_mskISADDR ( 0xFFFFF << DMA_ISADDR_offISADDR )
/******************************************************************************
* dmar6: DMA_ESADDR (DMA External Start Address Register)
*****************************************************************************/
/* This register holds External Start Address */
/******************************************************************************
* dmar7: DMA_TCNT (DMA Transfer Element Count Register)
*****************************************************************************/
#define DMA_TCNT_offTCNT 0 /* DMA transfer element count */
/* bit 18:31 reserved */
#define DMA_TCNT_mskTCNT ( 0x3FFFF << DMA_TCNT_offTCNT )
/******************************************************************************
* dmar8: DMA_STATUS (DMA Status Register)
*****************************************************************************/
#define DMA_STATUS_offSTAT 0 /* DMA channel state */
#define DMA_STATUS_offSTUNA 3 /* Un-aligned error on External Stride value */
#define DMA_STATUS_offDERR 4 /* DMA Transfer Disruption Error */
#define DMA_STATUS_offEUNA 5 /* Un-aligned error on the External address */
#define DMA_STATUS_offIUNA 6 /* Un-aligned error on the Internal address */
#define DMA_STATUS_offIOOR 7 /* Out-Of-Range error on the Internal address */
#define DMA_STATUS_offEBUS 8 /* Bus Error on an External DMA transfer */
#define DMA_STATUS_offESUP 9 /* DMA setup error */
/* bit 10:31 reserved */
#define DMA_STATUS_mskSTAT ( 0x7 << DMA_STATUS_offSTAT )
#define DMA_STATUS_mskSTUNA ( 0x1 << DMDMA_STATUS_offSTUNA )
#define DMA_STATUS_mskDERR ( 0x1 << DMDMA_STATUS_offDERR )
#define DMA_STATUS_mskEUNA ( 0x1 << DMDMA_STATUS_offEUNA )
#define DMA_STATUS_mskIUNA ( 0x1 << DMDMA_STATUS_offIUNA )
#define DMA_STATUS_mskIOOR ( 0x1 << DMDMA_STATUS_offIOOR )
#define DMA_STATUS_mskEBUS ( 0x1 << DMDMA_STATUS_offEBUS )
#define DMA_STATUS_mskESUP ( 0x1 << DMDMA_STATUS_offESUP )
/******************************************************************************
* dmar9: DMA_2DSET (DMA 2D Setup Register)
*****************************************************************************/
#define DMA_2DSET_offWECNT 0 /* The Width Element Count for a 2-D region */
#define DMA_2DSET_offHTSTR 16 /* The Height Stride for a 2-D region */
#define DMA_2DSET_mskHTSTR ( 0xFFFF << DMA_2DSET_offHTSTR )
#define DMA_2DSET_mskWECNT ( 0xFFFF << DMA_2DSET_offWECNT )
/******************************************************************************
* dmar10: DMA_2DSCTL (DMA 2D Startup Control Register)
*****************************************************************************/
#define DMA_2DSCTL_offSTWECNT 0 /* Startup Width Element Count for a 2-D region */
/* bit 16:31 reserved */
#define DMA_2DSCTL_mskSTWECNT ( 0xFFFF << DMA_2DSCTL_offSTWECNT )
/******************************************************************************
* fpcsr: FPCSR (Floating-Point Control Status Register)
*****************************************************************************/
#define FPCSR_offRM 0
#define FPCSR_offIVO 2
#define FPCSR_offDBZ 3
#define FPCSR_offOVF 4
#define FPCSR_offUDF 5
#define FPCSR_offIEX 6
#define FPCSR_offIVOE 7
#define FPCSR_offDBZE 8
#define FPCSR_offOVFE 9
#define FPCSR_offUDFE 10
#define FPCSR_offIEXE 11
#define FPCSR_offDNZ 12
#define FPCSR_offIVOT 13
#define FPCSR_offDBZT 14
#define FPCSR_offOVFT 15
#define FPCSR_offUDFT 16
#define FPCSR_offIEXT 17
#define FPCSR_offDNIT 18
#define FPCSR_mskRM ( 0x3 << FPCSR_offRM )
#define FPCSR_mskIVO ( 0x1 << FPCSR_offIVO )
#define FPCSR_mskDBZ ( 0x1 << FPCSR_offDBZ )
#define FPCSR_mskOVF ( 0x1 << FPCSR_offOVF )
#define FPCSR_mskUDF ( 0x1 << FPCSR_offUDF )
#define FPCSR_mskIEX ( 0x1 << FPCSR_offIEX )
#define FPCSR_mskIVOE ( 0x1 << FPCSR_offIVOE )
#define FPCSR_mskDBZE ( 0x1 << FPCSR_offDBZE )
#define FPCSR_mskOVFE ( 0x1 << FPCSR_offOVFE )
#define FPCSR_mskUDFE ( 0x1 << FPCSR_offUDFE )
#define FPCSR_mskIEXE ( 0x1 << FPCSR_offIEXE )
#define FPCSR_mskDNZ ( 0x1 << FPCSR_offDNZ )
#define FPCSR_mskIVOT ( 0x1 << FPCSR_offIVOT )
#define FPCSR_mskDBZT ( 0x1 << FPCSR_offDBZT )
#define FPCSR_mskOVFT ( 0x1 << FPCSR_offOVFT )
#define FPCSR_mskUDFT ( 0x1 << FPCSR_offUDFT )
#define FPCSR_mskIEXT ( 0x1 << FPCSR_offIEXT )
#define FPCSR_mskDNIT ( 0x1 << FPCSR_offDNIT )
/******************************************************************************
* fpcfg: FPCFG (Floating-Point Configuration Register)
*****************************************************************************/
#define FPCFG_offSP 0
#define FPCFG_offDP 1
#define FPCFG_offVER 2
#define FPCFG_offFREG 7
#define FPCFG_mskSP ( 0x1 << FPCFG_offSP )
#define FPCFG_mskDP ( 0x1 << FPCFG_offDP )
#define FPCFG_mskVER ( 0x1F << FPCFG_offVER )
#define FPCFG_mskFREG ( 0x3 << FPCFG_offFREG )
/******************************************************************************
* fucpr: FUCOP_CTL (FPU and Coprocessor Enable Control Register)
*****************************************************************************/
#define FUCOP_CTL_offFPUEN 0
#define FUCOP_CTL_offCP1EN 1
#define FUCOP_CTL_offCP2EN 2
#define FUCOP_CTL_offCP3EN 3
#define FUCOP_CTL_mskFPUEN ( 0x1 << FUCOP_CTL_offFPUEN )
#define FUCOP_CTL_mskCP1EN ( 0x1 << FUCOP_CTL_offCP1EN )
#define FUCOP_CTL_mskCP2EN ( 0x1 << FUCOP_CTL_offCP2EN )
#define FUCOP_CTL_mskCP3EN ( 0x1 << FUCOP_CTL_offCP3EN )
#ifdef CONFIG_CACHE_L2
/******************************************************************************
* L2_CA_CONF (Cache architecture configuration)
*****************************************************************************/
#define L2_CA_CONF_offL2CLSZ 8
#define L2_CA_CONF_mskL2CLSZ (0x7 << L2_CA_CONF_offL2CLSZ)
//TODO finish this table
/******************************************************************************
* L2CC_SETUP (L2CC Setup register)
*****************************************************************************/
#define L2CC_SETUP_offPART 0
#define L2CC_SETUP_mskPART (0x3 << L2_CA_CONF_offPART)
#define L2CC_SETUP_offDDLATC 4
#define L2CC_SETUP_mskDDLATC (0x3 << L2_CA_CONF_offDDLATC)
#define L2CC_SETUP_offTDLATC 8
#define L2CC_SETUP_mskTDLATC (0x3 << L2_CA_CONF_offTDLATC)
/******************************************************************************
* L2CC_PROT (L2CC Protect register)
*****************************************************************************/
#define L2CC_PROT_offMRWEN 31
#define L2CC_PROT_mskMRWEN (0x1 << L2CC_PROT_offMRWEN)
//TODO finish this table
//
/******************************************************************************
* L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
*****************************************************************************/
#define L2CC_CTRL_offEN 31
#define L2CC_CTRL_mskEN (0x1 << L2CC_CTRL_offEN)
/******************************************************************************
* L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
*****************************************************************************/
#define L2_CCTL_STATUS_offCMD_COMP 31
#define L2_CCTL_STATUS_mskCMD_COMP (0x1 << L2_CCTL_STATUS_offCMD_COMP)
//TODO finish this table
#endif
#endif /* __NDS32_DEFS_H__ */

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/*
* Copyright (C) 2008 Andes Technology, Inc.
*/
#ifndef __NDS32_REGS_H__
#define __NDS32_REGS_H__
#ifndef __ASSEMBLER__
#define DEFINE_GET_SYS_REG(reg) \
inline static unsigned long GET_##reg(void){ \
unsigned long val; \
__asm__ volatile ("mfsr %0, $"#reg :"=&r" (val) ::"memory"); \
return val; \
}
#define DEFINE_PUT_SYS_REG(reg) \
inline static void SET_##reg(unsigned long val){ \
__asm__ volatile ("\n\tmtsr %0, $"#reg \
"\n\tdsb" ::"r" (val) :"memory"); \
}
#define DEFINE_PUT_SYS_REG_i(reg) \
inline static void SET_##reg(unsigned long val){ \
__asm__ volatile ("\n\tmtsr %0, $"#reg \
"\n\tisb" ::"r" (val) :"memory"); \
}
#define DEFINE_SYS_REG_OP(reg) \
DEFINE_GET_SYS_REG(reg); \
DEFINE_PUT_SYS_REG(reg);
#define DEFINE_SYS_REG_OP_i(reg) \
DEFINE_GET_SYS_REG(reg); \
DEFINE_PUT_SYS_REG_i(reg);
DEFINE_SYS_REG_OP(CPU_VER);
DEFINE_SYS_REG_OP(ICM_CFG);
DEFINE_SYS_REG_OP(DCM_CFG);
DEFINE_SYS_REG_OP(MMU_CFG);
DEFINE_SYS_REG_OP(MSC_CFG);
DEFINE_SYS_REG_OP(CORE_ID);
DEFINE_SYS_REG_OP(FUCOP_EXIST);
DEFINE_SYS_REG_OP_i(PSW);
DEFINE_SYS_REG_OP(IPSW);
DEFINE_SYS_REG_OP(P_IPSW);
DEFINE_SYS_REG_OP(IVB);
DEFINE_SYS_REG_OP(EVA);
DEFINE_SYS_REG_OP(P_EVA);
DEFINE_SYS_REG_OP(ITYPE);
DEFINE_SYS_REG_OP(P_ITYPE);
DEFINE_SYS_REG_OP(MERR);
DEFINE_SYS_REG_OP(IPC);
DEFINE_SYS_REG_OP(P_IPC);
DEFINE_SYS_REG_OP(OIPC);
DEFINE_SYS_REG_OP(P_P0);
DEFINE_SYS_REG_OP(P_P1);
DEFINE_SYS_REG_OP(INT_MASK);
DEFINE_SYS_REG_OP(INT_PEND);
DEFINE_SYS_REG_OP(MMU_CTL);
DEFINE_SYS_REG_OP(L1_PPTB);
DEFINE_SYS_REG_OP(TLB_VPN);
DEFINE_SYS_REG_OP(TLB_DATA);
DEFINE_SYS_REG_OP(TLB_MISC);
DEFINE_SYS_REG_OP(VLPT_IDX);
DEFINE_SYS_REG_OP(ILMB);
DEFINE_SYS_REG_OP(DLMB);
DEFINE_SYS_REG_OP(CACHE_CTL);
DEFINE_SYS_REG_OP(HSMP_SADDR);
DEFINE_SYS_REG_OP(HSMP_EADDR);
DEFINE_SYS_REG_OP(EDM_CFG);
DEFINE_SYS_REG_OP(EDMSW);
DEFINE_SYS_REG_OP(EDM_CTL);
DEFINE_SYS_REG_OP(EDM_DTR);
DEFINE_SYS_REG_OP(BPMTC);
DEFINE_SYS_REG_OP(DIMBR);
DEFINE_SYS_REG_OP(TECR0);
DEFINE_SYS_REG_OP(TECR1);
DEFINE_SYS_REG_OP(BPC0);
DEFINE_SYS_REG_OP(BPA0);
DEFINE_SYS_REG_OP(BPAM0);
DEFINE_SYS_REG_OP(BPV0);
DEFINE_SYS_REG_OP(BPCID0);
DEFINE_SYS_REG_OP(BPC1);
DEFINE_SYS_REG_OP(BPA1);
DEFINE_SYS_REG_OP(BPAM1);
DEFINE_SYS_REG_OP(BPV1);
DEFINE_SYS_REG_OP(BPCID1);
DEFINE_SYS_REG_OP(BPC2);
DEFINE_SYS_REG_OP(BPA2);
DEFINE_SYS_REG_OP(BPAM2);
DEFINE_SYS_REG_OP(BPV2);
DEFINE_SYS_REG_OP(BPCID2);
DEFINE_SYS_REG_OP(BPC3);
DEFINE_SYS_REG_OP(BPA3);
DEFINE_SYS_REG_OP(BPAM3);
DEFINE_SYS_REG_OP(BPV3);
DEFINE_SYS_REG_OP(BPCID3);
DEFINE_SYS_REG_OP(BPC4);
DEFINE_SYS_REG_OP(BPA4);
DEFINE_SYS_REG_OP(BPAM4);
DEFINE_SYS_REG_OP(BPV4);
DEFINE_SYS_REG_OP(BPCID4);
DEFINE_SYS_REG_OP(BPC5);
DEFINE_SYS_REG_OP(BPA5);
DEFINE_SYS_REG_OP(BPAM5);
DEFINE_SYS_REG_OP(BPV5);
DEFINE_SYS_REG_OP(BPCID5);
DEFINE_SYS_REG_OP(BPC6);
DEFINE_SYS_REG_OP(BPA6);
DEFINE_SYS_REG_OP(BPAM6);
DEFINE_SYS_REG_OP(BPV6);
DEFINE_SYS_REG_OP(BPCID6);
DEFINE_SYS_REG_OP(BPC7);
DEFINE_SYS_REG_OP(BPA7);
DEFINE_SYS_REG_OP(BPAM7);
DEFINE_SYS_REG_OP(BPV7);
DEFINE_SYS_REG_OP(BPCID7);
DEFINE_SYS_REG_OP(PFMC0);
DEFINE_SYS_REG_OP(PFMC1);
DEFINE_SYS_REG_OP(PFMC2);
DEFINE_SYS_REG_OP(PFM_CTL);
DEFINE_SYS_REG_OP(SDZ_CTL);
DEFINE_SYS_REG_OP(N12MISC_CTL);
DEFINE_SYS_REG_OP(PRUSR_ACC_CTL);
DEFINE_SYS_REG_OP(DMA_CFG);
DEFINE_SYS_REG_OP(DMA_GCSW);
DEFINE_SYS_REG_OP(DMA_CHNSEL);
DEFINE_SYS_REG_OP(DMA_ACT);
DEFINE_SYS_REG_OP(DMA_SETUP);
DEFINE_SYS_REG_OP(DMA_ISADDR);
DEFINE_SYS_REG_OP(DMA_ESADDR);
DEFINE_SYS_REG_OP(DMA_TCNT);
DEFINE_SYS_REG_OP(DMA_STATUS);
DEFINE_SYS_REG_OP(DMA_2DSET);
DEFINE_SYS_REG_OP(DMA_2DSCTL);
DEFINE_SYS_REG_OP(FPCSR);
DEFINE_SYS_REG_OP(FPCFG);
DEFINE_SYS_REG_OP(FUCOP_CTL);
#endif /* !__ASSEMBLER__ */
#endif /* __NDS32_REGS_H__ */

309
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/mcu/ANDES_N10/os_cpu_common.h Normal file
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#ifdef __ASSEMBLER__
#define IRQ_SYSTICK 20
#endif
! Switch to interruption level \lv
.macro IntlSwitch lv
! mfsr $r0, $PSW
! li $r1, #~PSW_mskINTL
! and $r0, $r0, $r1
! ori $r0, $r0, #(\lv << PSW_offINTL)
! mtsr $r0, $PSW
! isb
mfsr $r0, $PSW
#ifdef CONFIG_HWZOL
/* Also enable ZOL (PSW.AEN) */
xori $r0, $r0, #((1 << 13) | (1 << 1))
#else
addi $r0, $r0, #-2
#endif
mtsr $r0, $PSW
! isb
.endm
/* align $sp to 8B boundary */
.macro align_sp_8 R0="$r2", R1="$r3"
move \R0, $sp !keep original $sp to be pushed
#if !defined(__NDS32_ISA_V3M__) || 1 //could be optimized out
#ifndef __NDS32_EXT_PERF__
andi \R1, $sp, #4 ! R1 = $sp.bit2 // 0 or 4
subri \R1, \R1, #4 ! R1 = 4 - R1 // 4 or 0
sub $sp, $sp, \R1 ! $sp -= R1 //-4 or 0
push \R0
#else
addi $sp, $sp, #-4 ! $sp -= 4
bclr $sp, $sp, #2 ! $sp.bit2 = 0
swi \R0, [$sp]
#endif
#endif
.endm
.macro push_d0d1
#if (defined(__NDS32_ISA_V2__) && defined(__NDS32_DX_REGS__)) || (!defined(__NDS32_ISA_V2__) && (defined(__NDS32_DIV__)||defined(__NDS32_MAC__)))
mfusr $r1, $d1.lo
mfusr $r2, $d1.hi
mfusr $r3, $d0.lo
mfusr $r4, $d0.hi
pushm $r1, $r4
#endif
.endm
.macro pop_d0d1
#if (defined(__NDS32_ISA_V2__) && defined(__NDS32_DX_REGS__)) || (!defined(__NDS32_ISA_V2__) && (defined(__NDS32_DIV__)||defined(__NDS32_MAC__)))
popm $r1, $r4
mtusr $r1, $d1.lo
mtusr $r2, $d1.hi
mtusr $r3, $d0.lo
mtusr $r4, $d0.hi
#endif
.endm
.macro push_ifc_lp
#ifdef __NDS32_EXT_IFC__
# ifndef CONFIG_NO_NDS32_EXT_IFC
mfusr $r0, $IFC_LP
push $r0
# endif
#endif
.endm
.macro pop_ifc_lp
#ifdef __NDS32_EXT_IFC__
# ifndef CONFIG_NO_NDS32_EXT_IFC
pop $r0
mtusr $r0, $IFC_LP
# endif
#endif
.endm
.macro push_zol
#ifdef CONFIG_HWZOL
mfusr $r1, $LB
mfusr $r2, $LE
mfusr $r3, $LC
pushm $r1, $r3
#endif
.endm
.macro pop_zol
#ifdef CONFIG_HWZOL
popm $r1, $r3
mtusr $r1, $LB
mtusr $r2, $LE
mtusr $r3, $LC
#endif
.endm
.macro push_sp
#ifdef __NDS32_EXT_IFC__
# ifndef CONFIG_NO_NDS32_EXT_IFC
push $sp
# else
addi $sp, $sp, #-4
push $sp
# endif
#else
addi $sp, $sp, #-4
push $sp
#endif
.endm
.macro SAVE_FPU_REGS_00
fsdi.bi $fd3, [$sp], -8
fsdi.bi $fd2, [$sp], -8
fsdi.bi $fd1, [$sp], -8
fsdi $fd0, [$sp+0]
.endm
.macro SAVE_FPU_REGS_01
fsdi.bi $fd7, [$sp], -8
fsdi.bi $fd6, [$sp], -8
fsdi.bi $fd5, [$sp], -8
fsdi.bi $fd4, [$sp], -8
SAVE_FPU_REGS_00
.endm
.macro SAVE_FPU_REGS_02
fsdi.bi $fd15, [$sp], -8
fsdi.bi $fd14, [$sp], -8
fsdi.bi $fd13, [$sp], -8
fsdi.bi $fd12, [$sp], -8
fsdi.bi $fd11, [$sp], -8
fsdi.bi $fd10, [$sp], -8
fsdi.bi $fd9, [$sp], -8
fsdi.bi $fd8, [$sp], -8
SAVE_FPU_REGS_01
.endm
.macro SAVE_FPU_REGS_03
fsdi.bi $fd31, [$sp], -8
fsdi.bi $fd30, [$sp], -8
fsdi.bi $fd29, [$sp], -8
fsdi.bi $fd28, [$sp], -8
fsdi.bi $fd27, [$sp], -8
fsdi.bi $fd26, [$sp], -8
fsdi.bi $fd25, [$sp], -8
fsdi.bi $fd24, [$sp], -8
fsdi.bi $fd23, [$sp], -8
fsdi.bi $fd22, [$sp], -8
fsdi.bi $fd21, [$sp], -8
fsdi.bi $fd20, [$sp], -8
fsdi.bi $fd19, [$sp], -8
fsdi.bi $fd18, [$sp], -8
fsdi.bi $fd17, [$sp], -8
fsdi.bi $fd16, [$sp], -8
SAVE_FPU_REGS_02
.endm
.macro push_fpu
#if defined(__NDS32_EXT_FPU_CONFIG_0__)
addi $sp, $sp, -8
SAVE_FPU_REGS_00
#elif defined(__NDS32_EXT_FPU_CONFIG_1__)
addi $sp, $sp, -8
SAVE_FPU_REGS_01
#elif defined(__NDS32_EXT_FPU_CONFIG_2__)
addi $sp, $sp, -8
SAVE_FPU_REGS_02
#elif defined(__NDS32_EXT_FPU_CONFIG_3__)
addi $sp, $sp, -8
SAVE_FPU_REGS_03
#else
#endif
.endm
.macro RESTORE_FPU_REGS_00
fldi.bi $fd0, [$sp], 8
fldi.bi $fd1, [$sp], 8
fldi.bi $fd2, [$sp], 8
fldi.bi $fd3, [$sp], 8
.endm
.macro RESTORE_FPU_REGS_01
RESTORE_FPU_REGS_00
fldi.bi $fd4, [$sp], 8
fldi.bi $fd5, [$sp], 8
fldi.bi $fd6, [$sp], 8
fldi.bi $fd7, [$sp], 8
.endm
.macro RESTORE_FPU_REGS_02
RESTORE_FPU_REGS_01
fldi.bi $fd8, [$sp], 8
fldi.bi $fd9, [$sp], 8
fldi.bi $fd10, [$sp], 8
fldi.bi $fd11, [$sp], 8
fldi.bi $fd12, [$sp], 8
fldi.bi $fd13, [$sp], 8
fldi.bi $fd14, [$sp], 8
fldi.bi $fd15, [$sp], 8
.endm
.macro RESTORE_FPU_REGS_03
RESTORE_FPU_REGS_02
fldi.bi $fd16, [$sp], 8
fldi.bi $fd17, [$sp], 8
fldi.bi $fd18, [$sp], 8
fldi.bi $fd19, [$sp], 8
fldi.bi $fd20, [$sp], 8
fldi.bi $fd21, [$sp], 8
fldi.bi $fd22, [$sp], 8
fldi.bi $fd23, [$sp], 8
fldi.bi $fd24, [$sp], 8
fldi.bi $fd25, [$sp], 8
fldi.bi $fd26, [$sp], 8
fldi.bi $fd27, [$sp], 8
fldi.bi $fd28, [$sp], 8
fldi.bi $fd29, [$sp], 8
fldi.bi $fd30, [$sp], 8
fldi.bi $fd31, [$sp], 8
.endm
.macro pop_fpu
#if defined(__NDS32_EXT_FPU_CONFIG_0__)
RESTORE_FPU_REGS_00
#elif defined(__NDS32_EXT_FPU_CONFIG_1__)
RESTORE_FPU_REGS_01
#elif defined(__NDS32_EXT_FPU_CONFIG_2__)
RESTORE_FPU_REGS_02
#elif defined(__NDS32_EXT_FPU_CONFIG_3__)
RESTORE_FPU_REGS_03
#else
#endif
.endm
.macro SAVE_ALL
pushm $r2, $r30
push_d0d1
push_ifc_lp
push_zol
mfsr $r0, $PSW
mfsr $r1, $IPC
mfsr $r2, $IPSW
pushm $r0, $r2
/* Descend interrupt level */
align_sp_8
push_fpu
.endm
.macro RESTORE_ALL
pop_fpu
lwi $sp, [$sp]
popm $r0, $r2 /* popm $r1 ~ $r2*/
mtsr $r1, $IPC
mtsr $r2, $IPSW
pop_zol
pop_ifc_lp
pop_d0d1
popm $r2, $r30
.endm
.macro CALLER_SAVE
!pushm $r2, $r30
pushm $r2, $r5
pushm $r15,$r30 /* full: 16 gpr, reduce: 6 gpr*/
push_d0d1 /* 4 reg, optional */
push_ifc_lp /* 1 reg, optional */
push_zol
mfsr $r0, $PSW
mfsr $r1, $IPC
mfsr $r2, $IPSW
pushm $r0, $r2 /* 3 reg */
!push_sp /* 1 or 2 reg, depend on ifc on/off */
align_sp_8 /* already 8-byte align, needn't do again*/
push_fpu /* optional */
.endm
.macro CALLER_RESTORE
pop_fpu
lwi $sp, [$sp]
popm $r0, $r2 /* popm $r1 ~ $r2*/
mtsr $r1, $IPC
mtsr $r2, $IPSW
pop_zol
pop_ifc_lp
pop_d0d1
popm $r15, $r30
popm $r2, $r5
.endm
.macro CallFn fn
!#if defined(NDS32_ABI_2) || defined(NDS32_ABI_2FP)
! addi $sp, $sp, -4
!#else
! addi $sp, $sp, -28
!#endif
bal \fn
!#if defined(NDS32_ABI_2) || defined(NDS32_ABI_2FP)
! addi $sp, $sp, 4
!#else
! addi $sp, $sp, 28
!#endif
.endm

31
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/soc/efuseapi/efuse_api.h Normal file
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#ifndef EFUSE_API_H
#define EFUSE_API_H
//#include "efuse/hal_efuse.h"
typedef union USB_VPID {
uint8_t u8[2];
uint16_t u16;
} usb_pvid;
//export API
int efuse_dump_data();
int efuse_get_free_bits();
int efuse_write_mac(uint8_t *mac_addr);
int efuse_write_chip_id(uint32_t chip_id);
int efuse_write_usb_vid(uint16_t usb_vid);
int efuse_write_usb_pid(uint16_t usb_pid);
int efuse_write_tx_power1(uint8_t value);
int efuse_write_tx_power2(uint8_t value);
int efuse_write_xtal(uint8_t xtal);
int efuse_read_mac(uint8_t *mac_addr);
int efuse_read_mac_inc(uint8_t *mac_addr);
int efuse_read_chip_id(uint32_t *p_chip_id);
int efuse_read_usb_vid(uint16_t *pvid);
int efuse_read_usb_pid(uint16_t *ppid);
int efuse_read_tx_power1(uint8_t* pvalue);
int efuse_read_tx_power2(uint8_t* pvalue);
int efuse_read_xtal(uint8_t *pxtal);
#endif

13
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/soc/efuseapi/module.mk Normal file
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LIB_SRC := efuse_api.c
LIB_ASRC :=
LIBRARY_NAME := efuseapi
LOCAL_CFLAGS :=
LOCAL_AFLAGS :=
LOCAL_INC += -I$(TOPDIR)/components/drv
RELEASE_SRC := 1
$(eval $(call link-lib,$(LIBRARY_NAME),$(LIB_SRC),$(LIB_ASRC),$(LOCAL_CFLAGS),$(LOCAL_INC),$(LOCAL_AFLAGS),$(MYDIR)))

18
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/soc/lowpower/lowpower.h Normal file
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#ifndef LOW_POWER_H
#define LOW_POWER_H
#include "attrs.h"
#include <stdint.h>
enum lowpower_option {
E_LOW_POWER_ACTIVE = 0,
E_LOW_POWER_SLEEP = 1, //< Tick will not accuratcy
//E_LOW_POWER_HIBERNATE = 2,
};
extern enum lowpower_option g_lowpower_option;
void lowpower_mode(enum lowpower_option);
void system_delay(int delaytick) ATTRIBUTE_SECTION_FAST;
int sys_sleep(uint32_t) ATTRIBUTE_SECTION_FAST;
void sys_hibernate(int, uint32_t) ATTRIBUTE_SECTION_FAST;
#endif /* end of include guard */

14
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/soc/lowpower/module.mk Normal file
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@ -0,0 +1,14 @@
LIB_SRC := rtos_lowpower.c lowpower_control.c
#LIB_ASRC := retention_start.S
LIBRARY_NAME := lowpower
LOCAL_CFLAGS :=
LOCAL_AFLAGS :=
LOCAL_INC := -I$(TOPDIR)/components/inc/bsp/$(CHIP_NAME)
LOCAL_INC += -I$(TOPDIR)/components/drv
LOCAL_INC += -I$(TOPDIR)/components/drv/gpio
RELEASE_SRC := 1
$(eval $(call link-lib,$(LIBRARY_NAME),$(LIB_SRC),$(LIB_ASRC),$(LOCAL_CFLAGS),$(LOCAL_INC),$(LOCAL_AFLAGS),$(MYDIR)))

71
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/soc/soc_init/init_mem.c Normal file
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#include "attrs.h"
#define NDS32_FMEMCPY(dst, src, size) \
__asm__ __volatile__( \
"move $r3, %2 \n\t" \
"move $r1, %0 \n\t" \
"move $r2, %1 \n\t" \
"1:\n\t" \
"lwi.bi $r0, [$r2], 4 \n\t" \
"swi.bi $r0, [$r1], 4 \n\t" \
"addi $r3, $r3, -4 \n\t" \
"bgtz $r3, 1b \n\t" \
::"r"(dst),"r"(src),"r"(size):"$r0", "$r1","$r2","$r3")
#ifdef XIP_MODE
/* This must be a leaf function, no child function */
void _nds32_init_mem(void) __attribute__((no_prologue, optimize("Os"))) ATTRIBUTE_SECTION_FBOOT;
void _nds32_init_mem()
{
int size;
////// for DLM init.
// do Low Level Init
extern char __data_lmastart;
extern char __data_start;
extern char _edata;
/* Copy data section to RAM */
//asm("li $r0, 0x00100009\n"
asm("mtsr %0, $mr7"
:
: "r"(0x00100009)
:);
size = &_edata - &__data_start;
NDS32_FMEMCPY(&__data_start, &__data_lmastart, size);
}
/* This must be a leaf function, no child function */
void _move_prog_in_sram(void) __attribute__((no_prologue, optimize("Os"))) ATTRIBUTE_SECTION_FBOOT;
void _move_prog_in_sram() {
extern char __flash_psram_lmastart;
extern char __flash_psram_start;
extern char _eflash;
int size = &_eflash - &__flash_psram_start;
NDS32_FMEMCPY(&__flash_psram_start, &__flash_psram_lmastart, size);
}
void _move_fast_boot_code(void) __attribute__((no_prologue, optimize("Os"))) __attribute__((section(".magic_boot_c")));
void _move_fast_boot_code(void) {
extern char __flash_lmastart;
extern char __flash_start;
extern char _fast_code_end;
int size = &_fast_code_end - &__flash_start;
NDS32_FMEMCPY(&__flash_start, &__flash_lmastart, size);
}
#endif
#if defined(FEATURE_RETENTION_BOOT)
/* This must be a leaf function, no child function */
void _move_retention_sram(void) __attribute__((no_prologue, optimize("Os"))) ATTRIBUTE_SECTION_FBOOT;
void _move_retention_sram() {
extern char __retention_code_lmastart;
extern char __retention_code_start;
extern char __retention_code_end;
int size = &__retention_code_end - &__retention_code_start;
NDS32_FMEMCPY(&__retention_code_start, &__retention_code_lmastart, size);
}
#endif

13
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/soc/soc_init/module.mk Normal file
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LIB_SRC := init_mem.c
LIB_SRC += soc_init.c
LIB_ASRC :=
LIBRARY_NAME := soc_init
LOCAL_CFLAGS :=
LOCAL_AFLAGS :=
LOCAL_INC +=
LOCAL_INC += -I$(TOPDIR)/components/drv
RELEASE_SRC := 2
$(eval $(call build-lib,$(LIBRARY_NAME),$(LIB_SRC),$(LIB_ASRC),$(LOCAL_CFLAGS),$(LOCAL_INC),$(LOCAL_AFLAGS),$(MYDIR)))

14
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/soc/soc_init/soc_init.c Normal file
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@ -0,0 +1,14 @@
#include <nds32_intrinsic.h>
#include "soc_types.h"
#include "soc_defs.h"
#include "gpio/hal_gpio.h"
#include "pinmux/hal_pinmux.h"
#include "custom_io_hal.h"
#include "custom_io_chk.h"
void _soc_io_init(void)
{
hal_pinmux_set_raw(_M_PIN_MODE, _M_FUNC_SEL);
}

6
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/soc/soc_init/soc_init.mk Normal file
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@ -0,0 +1,6 @@
NAME := soc_init
$(NAME)_CFLAGS += -Wno-implicit-function-declaration
$(NAME)_INCLUDES += ../../../drv
$(NAME)_SOURCES := init_mem.c soc_init.c

30
Living_SDK/platform/mcu/sv6266/sdk/components/bsp/soc/ssv6006/attrs.h Normal file
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@ -0,0 +1,30 @@
#ifndef ATTRS_H
#define ATTRS_H
#if defined(M_BUILD_ROM) && (M_BUILD_ROM == 1)
#define ATTRIBUTE_SECTION_FAST
#else
// define P1.
#define ATTRIBUTE_SECTION_FBOOT __attribute__((section(".fast_boot_code")))
#define ATTRIBUTE_SECTION_OTA_FBOOT __attribute__((section(".ota_fast_boot_code")))
#define ATTRIBUTE_SECTION_OTA_FBOOT_DATA __attribute__((section(".ota_fast_boot_data")))
// define P2.
#define ATTRIBUTE_SECTION_RBOOT __attribute__((section(".rboot")))
// define P3.
#define ATTRIBUTE_SECTION_FAST_TEXT __attribute__((section(".prog_in_sram")))
#define ATTRIBUTE_SECTION_FAST __attribute__((section(".prog_in_sram")))
//#define ATTRIBUTE_SECTION_FAST_TEXT
//#define ATTRIBUTE_SECTION_FAST
// define P4.
#define ATTRIBUTE_SECTION_SLOW_TEXT
// define P5.
#define ATTRIBUTE_SECTION_DATA
// define P5.
#define ATTRIBUTE_SECTION_FAST_DATA
// define P6.
#define ATTRIBUTE_SECTION_BSS
// define P7.
#define ATTRIBUTE_SECTION_RSRAM __attribute__((section(".rsram")))
#endif
#endif /* end of include guard: ATTRS_H */

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