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rel_1.6.0 init

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guocheng.kgc 2020-06-18 20:06:52 +08:00 • committed by shengdong.dsd
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64
Living_SDK/platform/mcu/rda5981x/aos/aos.c Normal file
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/**
* File : aos.c
*/
#include <aos/aos.h>
#include <k_api.h>
#include <aos/kernel.h>
#include <stdio.h>
#include <stdlib.h>
#define AOS_START_STACK 2048
// #define WIFI_PRODUCT_INFO_SIZE ES_WIFI_MAX_SSID_NAME_SIZE
ktask_t *g_aos_init;
extern int application_start(int argc, char **argv);
extern int aos_framework_init(void);
extern void hw_start_hal(void);
void hal_init()
{
board_init();
}
extern void board_init_later() __attribute__((weak));
static void sys_init(void)
{
LOG("sys_init.");
rda_soc_init();
#ifdef BOOTLOADER
main();
#else
hal_init();
rda5981_init_sys_data();
hw_start_hal();
vfs_init();
vfs_device_init();
aos_cli_init();
aos_kv_init();
aos_loop_init();
aos_framework_init();
aos_show_welcome();
dumpsys_cli_init();
board_init_later();
#ifdef AOS_COMP_PWRMGMT
cpu_pwrmgmt_init();
#endif
application_start(0, NULL);
#endif
}
void sys_start(void)
{
aos_init();
krhino_task_dyn_create(&g_aos_init, "aos-init", 0, AOS_DEFAULT_APP_PRI, 0, AOS_START_STACK, (task_entry_t)sys_init, 1);
aos_start();
}
void entry_main(void)
{
sys_start();
}

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Living_SDK/platform/mcu/rda5981x/aos/soc_impl.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <k_api.h>
#include <assert.h>
#if (RHINO_CONFIG_HW_COUNT > 0)
void soc_hw_timer_init(void)
{
}
hr_timer_t soc_hr_hw_cnt_get(void)
{
return 0;
//return *(volatile uint64_t *)0xc0000120;
}
lr_timer_t soc_lr_hw_cnt_get(void)
{
return 0;
}
#endif /* RHINO_CONFIG_HW_COUNT */
#if (RHINO_CONFIG_INTRPT_GUARD > 0)
void soc_intrpt_guard(void)
{
}
#endif
#if (RHINO_CONFIG_INTRPT_STACK_REMAIN_GET > 0)
size_t soc_intrpt_stack_remain_get(void)
{
return 0;
}
#endif
#if (RHINO_CONFIG_INTRPT_STACK_OVF_CHECK > 0)
void soc_intrpt_stack_ovf_check(void)
{
}
#endif
#if (RHINO_CONFIG_DYNTICKLESS > 0)
void soc_tick_interrupt_set(tick_t next_ticks,tick_t elapsed_ticks)
{
}
tick_t soc_elapsed_ticks_get(void)
{
return 0;
}
#endif
extern void *heap_start;
extern void *heap_end;
extern void *heap_len;
extern void *__IramLeft;
extern void *__IramLeftLen;
extern void *__SmemLeft;
extern void *__SmemLeftLen;
k_mm_region_t g_mm_region[] =
{{(uint8_t*)&heap_start,(size_t)&heap_len},{(uint8_t*)&__SmemLeft,(size_t)&__SmemLeftLen},{(uint8_t*)&__IramLeft,(size_t)&__IramLeftLen}};
int g_region_num = sizeof(g_mm_region)/sizeof(k_mm_region_t);
#if (RHINO_CONFIG_MM_LEAKCHECK > 0 )
extern int __bss_start__, __bss_end__, __data_start__, __data_end__;
void aos_mm_leak_region_init(void)
{
//printf("heap_start = 0x%x, heap_len = 0x%x\n", (size_t)&heap_start, (size_t)&heap_len);
//krhino_add_mm_region(g_kmm_head, heap_start, heap_end - heap_start);
#if (RHINO_CONFIG_MM_DEBUG > 0)
krhino_mm_leak_region_init(&__bss_start__, &__bss_end__);
krhino_mm_leak_region_init(&__data_start__, &__data_end__);
#endif
}
#endif
size_t soc_get_cur_sp()
{
size_t sp = 0;
asm volatile(
"mov %0,sp\n"
:"=r"(sp));
return sp;
}
static void soc_print_stack()
{
uint32_t offset = 0;
kstat_t rst = RHINO_SUCCESS;
void *cur, *end;
int i=0;
int *p;
end = krhino_cur_task_get()->task_stack_base + krhino_cur_task_get()->stack_size;
cur = soc_get_cur_sp();
p = (int*)cur;
while(p < (int*)end) {
if(i%4==0) {
printf("\r\n%08x:",(uint32_t)p);
}
printf("%08x ", *p);
i++;
p++;
}
printf("\r\n");
return;
}
void soc_err_proc(kstat_t err)
{
(void)err;
soc_print_stack();
assert(0);
}
krhino_err_proc_t g_err_proc = soc_err_proc;

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Living_SDK/platform/mcu/rda5981x/bootloader/bootloader.bin Normal file
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Living_SDK/platform/mcu/rda5981x/cmsis/arm_common_tables.h Normal file
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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. October 2015
* $Revision: V.1.4.5 a
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
/* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

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/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
//#include "RDA5991H.h"
#include "rda5981.h"
#include "cmsis_nvic.h"
#endif

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return(result);
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "cmsis_nvic.h"
#include "k_dbg_api.h"
#define NVIC_RAM_VECTOR_ADDRESS (RDA_IRAM_BASE) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (RDA_CODE_BASE) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
#if 0
// reuse Bootrom NMI/HardFault/MemManage/BusFault/UsageFault handler
old_vectors = (uint32_t*)RDA_ROM_BASE;
for (i=2; i<7; i++) {
vectors[i] = old_vectors[i];
}
#endif
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}
void NVIC_Remap(void)
{
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
}
struct pt_regs
{
unsigned long uregs[18];
};
#define ARM_cpsr uregs[7]
#define ARM_pc uregs[6]
#define ARM_lr uregs[5]
#define ARM_ip uregs[4]
#define ARM_r3 uregs[3]
#define ARM_r2 uregs[2]
#define ARM_r1 uregs[1]
#define ARM_r0 uregs[0]
#define CC_V_BIT (0x01UL << 28)
#define CC_C_BIT (0x01UL << 29)
#define CC_Z_BIT (0x01UL << 30)
#define CC_N_BIT (0x01UL << 31)
#define condition_codes(regs) \
((regs)->ARM_cpsr & (CC_V_BIT | CC_C_BIT | CC_Z_BIT | CC_N_BIT))
typedef union
{
struct
{
struct
{
volatile uint8_t IACCVIOL :1;
volatile uint8_t DACCVIOL :1;
volatile uint8_t :1;
volatile uint8_t MUNSTKERR :1;
volatile uint8_t MSTKERR :1;
volatile uint8_t MLSPERR :1;
volatile uint8_t :1;
volatile uint8_t MMARVALID :1;
}MFSR;
struct
{
volatile uint8_t IBUSERR :1;
volatile uint8_t PRECISERR :1;
volatile uint8_t IMPRECISERR :1;
volatile uint8_t UNSTKERR :1;
volatile uint8_t STKERR :1;
volatile uint8_t LSPERR :1;
volatile uint8_t :1;
volatile uint8_t BFARVALID :1;
}BFSR;
struct
{
volatile uint16_t UNDEFINSTR :1;
volatile uint16_t INVSTATE :1;
volatile uint16_t INVPC :1;
volatile uint16_t NOCP :1;
volatile uint16_t :4;
volatile uint16_t UNALIGNED :1;
volatile uint16_t DIVBYZERO :1;
volatile uint16_t :6;
}UFSR;
}BITS;
volatile uint32_t WORD;
} SCB_CFSR_REG;
static void panic(void)
{
mbed_error_printf("Panic...\r\n");
while(1);
}
void stack_dump(struct pt_regs *regs){
uint8_t i = 0;
uint32_t *tmp = (uint32_t *)regs;
mbed_error_printf("stack dump:\r\n");
for (i = 0; i < 64; i++) {
mbed_error_printf("0x%08x, ",tmp[i]);
if ((i + 1) % 8 == 0)
mbed_error_printf("\r\n");
}
}
static void show_regs(struct pt_regs *regs)
{
uint32_t flags = 0;
SCB_CFSR_REG *pt_cFSR = ((void *)0);
mbed_error_printf("[Hard Faults Report - all numbers in hex]\r\n");
mbed_error_printf("R0 = 0x%08X\r\n", regs->ARM_r0);
mbed_error_printf("R1 = 0x%08X\r\n", regs->ARM_r1);
mbed_error_printf("R2 = 0x%08X\r\n", regs->ARM_r2);
mbed_error_printf("R3 = 0x%08X\r\n", regs->ARM_r3);
mbed_error_printf("R12 = 0x%08X\r\n", regs->ARM_ip);
mbed_error_printf("LR [R14] = 0x%08X\r\n", regs->ARM_lr);
mbed_error_printf("PC [R15] = 0x%08X\r\n", regs->ARM_pc);
mbed_error_printf("PSR = 0x%08X\r\n", regs->ARM_cpsr);
flags = __get_PRIMASK();
mbed_error_printf("PRIMASK = %x, IRQ:%sable\r\n", flags, flags ? "Dis" : "En");
flags = __get_FAULTMASK();
mbed_error_printf("FAULTMASK = 0x%08x\r\n", flags);
flags = __get_BASEPRI();
mbed_error_printf("BASEPRI = 0x%08x\r\n", flags);
flags = __get_CONTROL();
mbed_error_printf("CONTROL = 0x%08x\r\n", flags);
mbed_error_printf("BFAR = 0x%08x\r\n", (*((volatile unsigned long *)(0xE000ED38))));
mbed_error_printf("CFSR = 0x%08x\r\n", (*((volatile unsigned long *)(0xE000ED28))));
mbed_error_printf("HFSR = 0x%08x\r\n", (*((volatile unsigned long *)(0xE000ED2C))));
mbed_error_printf("DFSR = 0x%08x\r\n", (*((volatile unsigned long *)(0xE000ED30))));
mbed_error_printf("AFSR = 0x%08x\r\n", (*((volatile unsigned long *)(0xE000ED3C))));
mbed_error_printf("MMFAR = 0x%08x\r\n", (*((volatile unsigned long *)(0xE000ED34))));
mbed_error_printf("SCB_SHCSR = 0x%08x\r\n", SCB->SHCSR);
mbed_error_printf("\n\n[Detail report]\r\n");
flags = condition_codes(regs);
mbed_error_printf("APSR Flags: %c%c%c%c\r\n",
flags & CC_N_BIT ? 'N' : 'n',
flags & CC_Z_BIT ? 'Z' : 'z',
flags & CC_C_BIT ? 'C' : 'c',
flags & CC_V_BIT ? 'V' : 'v');
mbed_error_printf("ProcStack:0x%08x MainStack:0x%08x\r\n", __get_PSP(), __get_MSP());
flags = SCB->CFSR;
pt_cFSR = (SCB_CFSR_REG *)&flags;
mbed_error_printf("\nMemory Manage Faults\r\n");
mbed_error_printf("MM_FAULT_STAT:0x%02x\r\n", ((flags & SCB_CFSR_MEMFAULTSR_Msk) >> SCB_CFSR_MEMFAULTSR_Pos));
mbed_error_printf("\tIACCVIOL:0x%02x \t\tDACCVIOL:0x%02x\r\n",
pt_cFSR->BITS.MFSR.IACCVIOL, pt_cFSR->BITS.MFSR.DACCVIOL);
mbed_error_printf("\tMUNSTKERR:0x%02x \t\tMSTKERR:0x%02x\r\n",
pt_cFSR->BITS.MFSR.MUNSTKERR, pt_cFSR->BITS.MFSR.MSTKERR);
mbed_error_printf("\tMLSPERR:0x%02x \t\tMMARVALID:0x%02x\r\n",
pt_cFSR->BITS.MFSR.MLSPERR, pt_cFSR->BITS.MFSR.MMARVALID);
mbed_error_printf("\nBus Faults\r\n");
mbed_error_printf("BUS_FAULT_STAT:0x%02x\r\n", ((flags & SCB_CFSR_BUSFAULTSR_Msk) >> SCB_CFSR_BUSFAULTSR_Pos));
mbed_error_printf("\tIBUSERR:0x%02x \t\tPRECISERR:0x%02x\r\n",
pt_cFSR->BITS.BFSR.IBUSERR, pt_cFSR->BITS.BFSR.PRECISERR);
mbed_error_printf("\tIMPRECISERR:0x%02x \tUNSTKERR:0x%02x\r\n",
pt_cFSR->BITS.BFSR.IMPRECISERR, pt_cFSR->BITS.BFSR.UNSTKERR);
mbed_error_printf("\tSTKERR:0x%02x \t\tLSPERR:0x%02x\r\n",
pt_cFSR->BITS.BFSR.STKERR, pt_cFSR->BITS.BFSR.LSPERR);
mbed_error_printf("\tBFARVALID:0x%02x\r\n", pt_cFSR->BITS.BFSR.BFARVALID);
mbed_error_printf("\nUsage Faults\r\n");
mbed_error_printf("USG_FAULT_STAT:0x%02x\r\n", ((flags & SCB_CFSR_USGFAULTSR_Msk) >> SCB_CFSR_USGFAULTSR_Pos));
mbed_error_printf("\tUNDEFINSTR:0x%02x \tINVSTATE:0x%02x\r\n",
pt_cFSR->BITS.UFSR.UNDEFINSTR, pt_cFSR->BITS.UFSR.INVSTATE);
mbed_error_printf("\tINVPC:0x%02x \t\tNOCP:0x%02x\r\n",
pt_cFSR->BITS.UFSR.INVPC, pt_cFSR->BITS.UFSR.NOCP);
mbed_error_printf("\tUNALIGNED:0x%02x \t\tDIVBYZERO:0x%02x\r\n",
pt_cFSR->BITS.UFSR.UNALIGNED, pt_cFSR->BITS.UFSR.DIVBYZERO);
stack_dump(regs);
mbed_error_printf("\n[Report done]\r\n");
}
void NMI_Handler(void)
{
mbed_error_printf("#E NMI_Handler\n");
}
void HardFault_Handler_C(struct pt_regs *pt_regs)
{
if (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) {
__BKPT(0);
}
mbed_error_printf("#E HardFault_Handler\n");
show_regs(pt_regs);
panic();
}
void MemManage_Handler_C(struct pt_regs *pt_regs)
{
mbed_error_printf("#E MemManage_Handler\n");
show_regs(pt_regs);
panic();
}
void BusFault_Handler_C(struct pt_regs *pt_regs)
{
mbed_error_printf("#E BusFault_Handler\n");
show_regs(pt_regs);
panic();
}
void UsageFault_Handler_C(struct pt_regs *pt_regs)
{
mbed_error_printf("#E UsageFault_Handler\n");
show_regs(pt_regs);
panic();
}
#if defined (__CC_ARM)
__asm void HardFault_Handler(void)
{
TST LR, #4
ITE EQ
MRSEQ R0, MSP
MRSNE R0, PSP
B __cpp(HardFault_Handler_C)
}
__asm void MemManage_Handler(void)
{
TST LR, #4
ITE EQ
MRSEQ R0, MSP
MRSNE R0, PSP
B __cpp(MemManage_Handler_C)
}
__asm void BusFault_Handler(void)
{
TST LR, #4
ITE EQ
MRSEQ R0, MSP
MRSNE R0, PSP
B __cpp(BusFault_Handler_C)
}
__asm void UsageFault_Handler(void)
{
TST LR, #4
ITE EQ
MRSEQ R0, MSP
MRSNE R0, PSP
B __cpp(UsageFault_Handler_C)
}
#elif defined (__GNUC__) && (RHINO_CONFIG_PANIC == 0)
void HardFault_Handler(void)
{
__asm(" tst lr, #4\n"
"ite eq\n"
"mrseq r0, msp\n"
"mrsne r0, psp\n"
"b HardFault_Handler_C\n");
}
void MemManage_Handler(void)
{
__asm(" tst lr, #4\n"
"ite eq\n"
"mrseq r0, msp\n"
"mrsne r0, psp\n"
"b MemManage_Handler_C\n");
}
void BusFault_Handler(void)
{
__asm(" tst lr, #4\n"
"ite eq\n"
"mrseq r0, msp\n"
"mrsne r0, psp\n"
"b BusFault_Handler_C\n");
}
void UsageFault_Handler(void)
{
__asm(" tst lr, #4\n"
"ite eq\n"
"mrseq r0, msp\n"
"mrsne r0, psp\n"
"b UsageFault_Handler_C\n");
}
#endif

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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 15)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
void NVIC_Remap(void);
#ifdef __cplusplus
}
#endif
#endif

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/* ----------------------------------------------------------------------
* $Date: 5. February 2013
* $Revision: V1.02
*
* Project: CMSIS-RTOS API
* Title: cmsis_os.h template header file
*
* Version 0.02
* Initial Proposal Phase
* Version 0.03
* osKernelStart added, optional feature: main started as thread
* osSemaphores have standard behavior
* osTimerCreate does not start the timer, added osTimerStart
* osThreadPass is renamed to osThreadYield
* Version 1.01
* Support for C++ interface
* - const attribute removed from the osXxxxDef_t typedef's
* - const attribute added to the osXxxxDef macros
* Added: osTimerDelete, osMutexDelete, osSemaphoreDelete
* Added: osKernelInitialize
* Version 1.02
* Control functions for short timeouts in microsecond resolution:
* Added: osKernelSysTick, osKernelSysTickFrequency, osKernelSysTickMicroSec
* Removed: osSignalGet
*----------------------------------------------------------------------------
*
* Copyright (c) 2013 ARM LIMITED
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
/**
\page cmsis_os_h Header File Template: cmsis_os.h
The file \b cmsis_os.h is a template header file for a CMSIS-RTOS compliant Real-Time Operating System (RTOS).
Each RTOS that is compliant with CMSIS-RTOS shall provide a specific \b cmsis_os.h header file that represents
its implementation.
The file cmsis_os.h contains:
- CMSIS-RTOS API function definitions
- struct definitions for parameters and return types
- status and priority values used by CMSIS-RTOS API functions
- macros for defining threads and other kernel objects
<b>Name conventions and header file modifications</b>
All definitions are prefixed with \b os to give an unique name space for CMSIS-RTOS functions.
Definitions that are prefixed \b os_ are not used in the application code but local to this header file.
All definitions and functions that belong to a module are grouped and have a common prefix, i.e. \b osThread.
Definitions that are marked with <b>CAN BE CHANGED</b> can be adapted towards the needs of the actual CMSIS-RTOS implementation.
These definitions can be specific to the underlying RTOS kernel.
Definitions that are marked with <b>MUST REMAIN UNCHANGED</b> cannot be altered. Otherwise the CMSIS-RTOS implementation is no longer
compliant to the standard. Note that some functions are optional and need not to be provided by every CMSIS-RTOS implementation.
<b>Function calls from interrupt service routines</b>
The following CMSIS-RTOS functions can be called from threads and interrupt service routines (ISR):
- \ref osSignalSet
- \ref osSemaphoreRelease
- \ref osPoolAlloc, \ref osPoolCAlloc, \ref osPoolFree
- \ref osMessagePut, \ref osMessageGet
- \ref osMailAlloc, \ref osMailCAlloc, \ref osMailGet, \ref osMailPut, \ref osMailFree
Functions that cannot be called from an ISR are verifying the interrupt status and return in case that they are called
from an ISR context the status code \b osErrorISR. In some implementations this condition might be caught using the HARD FAULT vector.
Some CMSIS-RTOS implementations support CMSIS-RTOS function calls from multiple ISR at the same time.
If this is impossible, the CMSIS-RTOS rejects calls by nested ISR functions with the status code \b osErrorISRRecursive.
<b>Define and reference object definitions</b>
With <b>\#define osObjectsExternal</b> objects are defined as external symbols. This allows to create a consistent header file
that is used throughout a project as shown below:
<i>Header File</i>
\code
#include <cmsis_os.h> // CMSIS RTOS header file
// Thread definition
extern void thread_sample (void const *argument); // function prototype
osThreadDef (thread_sample, osPriorityBelowNormal, 1, 100);
// Pool definition
osPoolDef(MyPool, 10, long);
\endcode
This header file defines all objects when included in a C/C++ source file. When <b>\#define osObjectsExternal</b> is
present before the header file, the objects are defined as external symbols. A single consistent header file can therefore be
used throughout the whole project.
<i>Example</i>
\code
#include "osObjects.h" // Definition of the CMSIS-RTOS objects
\endcode
\code
#define osObjectExternal // Objects will be defined as external symbols
#include "osObjects.h" // Reference to the CMSIS-RTOS objects
\endcode
*/
#ifndef _CMSIS_OS_H
#define _CMSIS_OS_H
/// \note MUST REMAIN UNCHANGED: \b osCMSIS identifies the CMSIS-RTOS API version.
#define osCMSIS 0x10002 ///< API version (main [31:16] .sub [15:0])
/// \note CAN BE CHANGED: \b osCMSIS_KERNEL identifies the underlying RTOS kernel and version number.
#define osCMSIS_KERNEL 0x10000 ///< RTOS identification and version (main [31:16] .sub [15:0])
/// \note MUST REMAIN UNCHANGED: \b osKernelSystemId shall be consistent in every CMSIS-RTOS.
#define osKernelSystemId "KERNEL V1.00" ///< RTOS identification string
/// \note MUST REMAIN UNCHANGED: \b osFeature_xxx shall be consistent in every CMSIS-RTOS.
#define osFeature_MainThread 1 ///< main thread 1=main can be thread, 0=not available
#define osFeature_Pool 1 ///< Memory Pools: 1=available, 0=not available
#define osFeature_MailQ 1 ///< Mail Queues: 1=available, 0=not available
#define osFeature_MessageQ 1 ///< Message Queues: 1=available, 0=not available
#define osFeature_Signals 8 ///< maximum number of Signal Flags available per thread
#define osFeature_Semaphore 30 ///< maximum count for \ref osSemaphoreCreate function
#define osFeature_Wait 1 ///< osWait function: 1=available, 0=not available
#define osFeature_SysTick 1 ///< osKernelSysTick functions: 1=available, 0=not available
#include <stdint.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C"
{
#endif
// ==== Enumeration, structures, defines ====
/// Priority used for thread control.
/// \note MUST REMAIN UNCHANGED: \b osPriority shall be consistent in every CMSIS-RTOS.
typedef enum {
osPriorityIdle = -3, ///< priority: idle (lowest)
osPriorityLow = -2, ///< priority: low
osPriorityBelowNormal = -1, ///< priority: below normal
osPriorityNormal = 0, ///< priority: normal (default)
osPriorityAboveNormal = +1, ///< priority: above normal
osPriorityHigh = +2, ///< priority: high
osPriorityRealtime = +3, ///< priority: realtime (highest)
osPriorityError = 0x84 ///< system cannot determine priority or thread has illegal priority
} osPriority;
/// Timeout value.
/// \note MUST REMAIN UNCHANGED: \b osWaitForever shall be consistent in every CMSIS-RTOS.
#define osWaitForever 0xFFFFFFFF ///< wait forever timeout value
/// Status code values returned by CMSIS-RTOS functions.
/// \note MUST REMAIN UNCHANGED: \b osStatus shall be consistent in every CMSIS-RTOS.
typedef enum {
osOK = 0, ///< function completed; no error or event occurred.
osEventSignal = 0x08, ///< function completed; signal event occurred.
osEventMessage = 0x10, ///< function completed; message event occurred.
osEventMail = 0x20, ///< function completed; mail event occurred.
osEventTimeout = 0x40, ///< function completed; timeout occurred.
osErrorParameter = 0x80, ///< parameter error: a mandatory parameter was missing or specified an incorrect object.
osErrorResource = 0x81, ///< resource not available: a specified resource was not available.
osErrorTimeoutResource = 0xC1, ///< resource not available within given time: a specified resource was not available within the timeout period.
osErrorISR = 0x82, ///< not allowed in ISR context: the function cannot be called from interrupt service routines.
osErrorISRRecursive = 0x83, ///< function called multiple times from ISR with same object.
osErrorPriority = 0x84, ///< system cannot determine priority or thread has illegal priority.
osErrorNoMemory = 0x85, ///< system is out of memory: it was impossible to allocate or reserve memory for the operation.
osErrorValue = 0x86, ///< value of a parameter is out of range.
osErrorOS = 0xFF, ///< unspecified RTOS error: run-time error but no other error message fits.
os_status_reserved = 0x7FFFFFFF ///< prevent from enum down-size compiler optimization.
} osStatus;
/// Timer type value for the timer definition.
/// \note MUST REMAIN UNCHANGED: \b os_timer_type shall be consistent in every CMSIS-RTOS.
typedef enum {
osTimerOnce = 0, ///< one-shot timer
osTimerPeriodic = 1 ///< repeating timer
} os_timer_type;
/// Entry point of a thread.
/// \note MUST REMAIN UNCHANGED: \b os_pthread shall be consistent in every CMSIS-RTOS.
typedef void (*os_pthread) (void const *argument);
/// Entry point of a timer call back function.
/// \note MUST REMAIN UNCHANGED: \b os_ptimer shall be consistent in every CMSIS-RTOS.
typedef void (*os_ptimer) (void const *argument);
// >>> the following data type definitions may shall adapted towards a specific RTOS
/// Thread ID identifies the thread (pointer to a thread control block).
/// \note CAN BE CHANGED: \b os_thread_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_thread_cb *osThreadId;
/// Timer ID identifies the timer (pointer to a timer control block).
/// \note CAN BE CHANGED: \b os_timer_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_timer_cb *osTimerId;
/// Mutex ID identifies the mutex (pointer to a mutex control block).
/// \note CAN BE CHANGED: \b os_mutex_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_mutex_cb *osMutexId;
/// Semaphore ID identifies the semaphore (pointer to a semaphore control block).
/// \note CAN BE CHANGED: \b os_semaphore_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_semaphore_cb *osSemaphoreId;
/// Pool ID identifies the memory pool (pointer to a memory pool control block).
/// \note CAN BE CHANGED: \b os_pool_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_pool_cb *osPoolId;
/// Message ID identifies the message queue (pointer to a message queue control block).
/// \note CAN BE CHANGED: \b os_messageQ_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_messageQ_cb *osMessageQId;
/// Mail ID identifies the mail queue (pointer to a mail queue control block).
/// \note CAN BE CHANGED: \b os_mailQ_cb is implementation specific in every CMSIS-RTOS.
typedef struct os_mailQ_cb *osMailQId;
/// Thread Definition structure contains startup information of a thread.
/// \note CAN BE CHANGED: \b os_thread_def is implementation specific in every CMSIS-RTOS.
typedef struct os_thread_def {
os_pthread pthread; ///< start address of thread function
osPriority tpriority; ///< initial thread priority
uint32_t instances; ///< maximum number of instances of that thread function
uint32_t stacksize; ///< stack size requirements in bytes; 0 is default stack size
} osThreadDef_t;
/// Timer Definition structure contains timer parameters.
/// \note CAN BE CHANGED: \b os_timer_def is implementation specific in every CMSIS-RTOS.
typedef struct os_timer_def {
os_ptimer ptimer; ///< start address of a timer function
} osTimerDef_t;
/// Mutex Definition structure contains setup information for a mutex.
/// \note CAN BE CHANGED: \b os_mutex_def is implementation specific in every CMSIS-RTOS.
typedef struct os_mutex_def {
uint32_t dummy; ///< dummy value.
} osMutexDef_t;
/// Semaphore Definition structure contains setup information for a semaphore.
/// \note CAN BE CHANGED: \b os_semaphore_def is implementation specific in every CMSIS-RTOS.
typedef struct os_semaphore_def {
uint32_t dummy; ///< dummy value.
} osSemaphoreDef_t;
/// Definition structure for memory block allocation.
/// \note CAN BE CHANGED: \b os_pool_def is implementation specific in every CMSIS-RTOS.
typedef struct os_pool_def {
uint32_t pool_sz; ///< number of items (elements) in the pool
uint32_t item_sz; ///< size of an item
void *pool; ///< pointer to memory for pool
} osPoolDef_t;
/// Definition structure for message queue.
/// \note CAN BE CHANGED: \b os_messageQ_def is implementation specific in every CMSIS-RTOS.
typedef struct os_messageQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
void *pool; ///< memory array for messages
} osMessageQDef_t;
/// Definition structure for mail queue.
/// \note CAN BE CHANGED: \b os_mailQ_def is implementation specific in every CMSIS-RTOS.
typedef struct os_mailQ_def {
uint32_t queue_sz; ///< number of elements in the queue
uint32_t item_sz; ///< size of an item
void *pool; ///< memory array for mail
} osMailQDef_t;
/// Event structure contains detailed information about an event.
/// \note MUST REMAIN UNCHANGED: \b os_event shall be consistent in every CMSIS-RTOS.
/// However the struct may be extended at the end.
typedef struct {
osStatus status; ///< status code: event or error information
union {
uint32_t v; ///< message as 32-bit value
void *p; ///< message or mail as void pointer
int32_t signals; ///< signal flags
} value; ///< event value
union {
osMailQId mail_id; ///< mail id obtained by \ref osMailCreate
osMessageQId message_id; ///< message id obtained by \ref osMessageCreate
} def; ///< event definition
} osEvent;
// ==== Kernel Control Functions ====
/// Initialize the RTOS Kernel for creating objects.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osKernelInitialize shall be consistent in every CMSIS-RTOS.
osStatus osKernelInitialize (void);
/// Start the RTOS Kernel.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osKernelStart shall be consistent in every CMSIS-RTOS.
osStatus osKernelStart (void);
/// Check if the RTOS kernel is already started.
/// \note MUST REMAIN UNCHANGED: \b osKernelRunning shall be consistent in every CMSIS-RTOS.
/// \return 0 RTOS is not started, 1 RTOS is started.
int32_t osKernelRunning(void);
#if (defined (osFeature_SysTick) && (osFeature_SysTick != 0)) // System Timer available
/// Get the RTOS kernel system timer counter
/// \note MUST REMAIN UNCHANGED: \b osKernelSysTick shall be consistent in every CMSIS-RTOS.
/// \return RTOS kernel system timer as 32-bit value
uint32_t osKernelSysTick (void);
/// The RTOS kernel system timer frequency in Hz
/// \note Reflects the system timer setting and is typically defined in a configuration file.
#define osKernelSysTickFrequency 100000000
/// Convert a microseconds value to a RTOS kernel system timer value.
/// \param microsec time value in microseconds.
/// \return time value normalized to the \ref osKernelSysTickFrequency
#define osKernelSysTickMicroSec(microsec) (((uint64_t)microsec * (osKernelSysTickFrequency)) / 1000000)
#endif // System Timer available
// ==== Thread Management ====
/// Create a Thread Definition with function, priority, and stack requirements.
/// \param name name of the thread function.
/// \param priority initial priority of the thread function.
/// \param instances number of possible thread instances.
/// \param stacksz stack size (in bytes) requirements for the thread function.
/// \note CAN BE CHANGED: The parameters to \b osThreadDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osThreadDef(name, priority, instances, stacksz) \
extern const osThreadDef_t os_thread_def_##name
#else // define the object
#define osThreadDef(name, priority, instances, stacksz) \
const osThreadDef_t os_thread_def_##name = \
{ (name), (priority), (instances), (stacksz) }
#endif
/// Access a Thread definition.
/// \param name name of the thread definition object.
/// \note CAN BE CHANGED: The parameter to \b osThread shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osThread(name) \
&os_thread_def_##name
/// Create a thread and add it to Active Threads and set it to state READY.
/// \param[in] thread_def thread definition referenced with \ref osThread.
/// \param[in] argument pointer that is passed to the thread function as start argument.
/// \return thread ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osThreadCreate shall be consistent in every CMSIS-RTOS.
osThreadId osThreadCreate (const osThreadDef_t *thread_def, void *argument);
/// Return the thread ID of the current running thread.
/// \return thread ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osThreadGetId shall be consistent in every CMSIS-RTOS.
osThreadId osThreadGetId (void);
/// Terminate execution of a thread and remove it from Active Threads.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osThreadTerminate shall be consistent in every CMSIS-RTOS.
osStatus osThreadTerminate (osThreadId thread_id);
/// Pass control to next thread that is in state \b READY.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osThreadYield shall be consistent in every CMSIS-RTOS.
osStatus osThreadYield (void);
/// Change priority of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] priority new priority value for the thread function.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osThreadSetPriority shall be consistent in every CMSIS-RTOS.
osStatus osThreadSetPriority (osThreadId thread_id, osPriority priority);
/// Get current priority of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \return current priority value of the thread function.
/// \note MUST REMAIN UNCHANGED: \b osThreadGetPriority shall be consistent in every CMSIS-RTOS.
osPriority osThreadGetPriority (osThreadId thread_id);
// ==== Generic Wait Functions ====
/// Wait for Timeout (Time Delay).
/// \param[in] millisec time delay value
/// \return status code that indicates the execution status of the function.
osStatus osDelay (uint32_t millisec);
#if (defined (osFeature_Wait) && (osFeature_Wait != 0)) // Generic Wait available
/// Wait for Signal, Message, Mail, or Timeout.
/// \param[in] millisec timeout value or 0 in case of no time-out
/// \return event that contains signal, message, or mail information or error code.
/// \note MUST REMAIN UNCHANGED: \b osWait shall be consistent in every CMSIS-RTOS.
osEvent osWait (uint32_t millisec);
#endif // Generic Wait available
// ==== Timer Management Functions ====
/// Define a Timer object.
/// \param name name of the timer object.
/// \param function name of the timer call back function.
/// \note CAN BE CHANGED: The parameter to \b osTimerDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osTimerDef(name, function) \
extern const osTimerDef_t os_timer_def_##name
#else // define the object
#define osTimerDef(name, function) \
const osTimerDef_t os_timer_def_##name = \
{ (function) }
#endif
/// Access a Timer definition.
/// \param name name of the timer object.
/// \note CAN BE CHANGED: The parameter to \b osTimer shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osTimer(name) \
&os_timer_def_##name
/// Create a timer.
/// \param[in] timer_def timer object referenced with \ref osTimer.
/// \param[in] type osTimerOnce for one-shot or osTimerPeriodic for periodic behavior.
/// \param[in] argument argument to the timer call back function.
/// \return timer ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osTimerCreate shall be consistent in every CMSIS-RTOS.
osTimerId osTimerCreate (const osTimerDef_t *timer_def, os_timer_type type, void *argument);
/// Start or restart a timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \param[in] millisec time delay value of the timer.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osTimerStart shall be consistent in every CMSIS-RTOS.
osStatus osTimerStart (osTimerId timer_id, uint32_t millisec);
/// Stop the timer.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osTimerStop shall be consistent in every CMSIS-RTOS.
osStatus osTimerStop (osTimerId timer_id);
/// Delete a timer that was created by \ref osTimerCreate.
/// \param[in] timer_id timer ID obtained by \ref osTimerCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osTimerDelete shall be consistent in every CMSIS-RTOS.
osStatus osTimerDelete (osTimerId timer_id);
// ==== Signal Management ====
/// Set the specified Signal Flags of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] signals specifies the signal flags of the thread that should be set.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
/// \note MUST REMAIN UNCHANGED: \b osSignalSet shall be consistent in every CMSIS-RTOS.
int32_t osSignalSet (osThreadId thread_id, int32_t signals);
/// Clear the specified Signal Flags of an active thread.
/// \param[in] thread_id thread ID obtained by \ref osThreadCreate or \ref osThreadGetId.
/// \param[in] signals specifies the signal flags of the thread that shall be cleared.
/// \return previous signal flags of the specified thread or 0x80000000 in case of incorrect parameters.
/// \note MUST REMAIN UNCHANGED: \b osSignalClear shall be consistent in every CMSIS-RTOS.
int32_t osSignalClear (osThreadId thread_id, int32_t signals);
/// Wait for one or more Signal Flags to become signaled for the current \b RUNNING thread.
/// \param[in] signals wait until all specified signal flags set or 0 for any single signal flag.
/// \param[in] millisec timeout value or 0 in case of no time-out.
/// \return event flag information or error code.
/// \note MUST REMAIN UNCHANGED: \b osSignalWait shall be consistent in every CMSIS-RTOS.
osEvent osSignalWait (int32_t signals, uint32_t millisec);
// ==== Mutex Management ====
/// Define a Mutex.
/// \param name name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutexDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMutexDef(name) \
extern const osMutexDef_t os_mutex_def_##name
#else // define the object
#define osMutexDef(name) \
const osMutexDef_t os_mutex_def_##name = { 0 }
#endif
/// Access a Mutex definition.
/// \param name name of the mutex object.
/// \note CAN BE CHANGED: The parameter to \b osMutex shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMutex(name) \
&os_mutex_def_##name
/// Create and Initialize a Mutex object.
/// \param[in] mutex_def mutex definition referenced with \ref osMutex.
/// \return mutex ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMutexCreate shall be consistent in every CMSIS-RTOS.
osMutexId osMutexCreate (const osMutexDef_t *mutex_def);
/// Wait until a Mutex becomes available.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMutexWait shall be consistent in every CMSIS-RTOS.
osStatus osMutexWait (osMutexId mutex_id, uint32_t millisec);
/// Release a Mutex that was obtained by \ref osMutexWait.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMutexRelease shall be consistent in every CMSIS-RTOS.
osStatus osMutexRelease (osMutexId mutex_id);
/// Delete a Mutex that was created by \ref osMutexCreate.
/// \param[in] mutex_id mutex ID obtained by \ref osMutexCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMutexDelete shall be consistent in every CMSIS-RTOS.
osStatus osMutexDelete (osMutexId mutex_id);
// ==== Semaphore Management Functions ====
#if (defined (osFeature_Semaphore) && (osFeature_Semaphore != 0)) // Semaphore available
/// Define a Semaphore object.
/// \param name name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphoreDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osSemaphoreDef(name) \
extern const osSemaphoreDef_t os_semaphore_def_##name
#else // define the object
#define osSemaphoreDef(name) \
const osSemaphoreDef_t os_semaphore_def_##name = { 0 }
#endif
/// Access a Semaphore definition.
/// \param name name of the semaphore object.
/// \note CAN BE CHANGED: The parameter to \b osSemaphore shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osSemaphore(name) \
&os_semaphore_def_##name
/// Create and Initialize a Semaphore object used for managing resources.
/// \param[in] semaphore_def semaphore definition referenced with \ref osSemaphore.
/// \param[in] count number of available resources.
/// \return semaphore ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreCreate shall be consistent in every CMSIS-RTOS.
osSemaphoreId osSemaphoreCreate (const osSemaphoreDef_t *semaphore_def, int32_t count);
/// Wait until a Semaphore token becomes available.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out.
/// \return number of available tokens, or -1 in case of incorrect parameters.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreWait shall be consistent in every CMSIS-RTOS.
int32_t osSemaphoreWait (osSemaphoreId semaphore_id, uint32_t millisec);
/// Release a Semaphore token.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreRelease shall be consistent in every CMSIS-RTOS.
osStatus osSemaphoreRelease (osSemaphoreId semaphore_id);
/// Delete a Semaphore that was created by \ref osSemaphoreCreate.
/// \param[in] semaphore_id semaphore object referenced with \ref osSemaphoreCreate.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osSemaphoreDelete shall be consistent in every CMSIS-RTOS.
osStatus osSemaphoreDelete (osSemaphoreId semaphore_id);
#endif // Semaphore available
// ==== Memory Pool Management Functions ====
#if (defined (osFeature_Pool) && (osFeature_Pool != 0)) // Memory Pool Management available
/// \brief Define a Memory Pool.
/// \param name name of the memory pool.
/// \param no maximum number of blocks (objects) in the memory pool.
/// \param type data type of a single block (object).
/// \note CAN BE CHANGED: The parameter to \b osPoolDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osPoolDef(name, no, type) \
extern const osPoolDef_t os_pool_def_##name
#else // define the object
#define osPoolDef(name, no, type) \
const osPoolDef_t os_pool_def_##name = \
{ (no), sizeof(type), NULL }
#endif
/// \brief Access a Memory Pool definition.
/// \param name name of the memory pool
/// \note CAN BE CHANGED: The parameter to \b osPool shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osPool(name) \
&os_pool_def_##name
/// Create and Initialize a memory pool.
/// \param[in] pool_def memory pool definition referenced with \ref osPool.
/// \return memory pool ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osPoolCreate shall be consistent in every CMSIS-RTOS.
osPoolId osPoolCreate (const osPoolDef_t *pool_def);
/// Allocate a memory block from a memory pool.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
/// \note MUST REMAIN UNCHANGED: \b osPoolAlloc shall be consistent in every CMSIS-RTOS.
void *osPoolAlloc (osPoolId pool_id);
/// Allocate a memory block from a memory pool and set memory block to zero.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \return address of the allocated memory block or NULL in case of no memory available.
/// \note MUST REMAIN UNCHANGED: \b osPoolCAlloc shall be consistent in every CMSIS-RTOS.
void *osPoolCAlloc (osPoolId pool_id);
/// Return an allocated memory block back to a specific memory pool.
/// \param[in] pool_id memory pool ID obtain referenced with \ref osPoolCreate.
/// \param[in] block address of the allocated memory block that is returned to the memory pool.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osPoolFree shall be consistent in every CMSIS-RTOS.
osStatus osPoolFree (osPoolId pool_id, void *block);
#endif // Memory Pool Management available
// ==== Message Queue Management Functions ====
#if (defined (osFeature_MessageQ) && (osFeature_MessageQ != 0)) // Message Queues available
/// \brief Create a Message Queue Definition.
/// \param name name of the queue.
/// \param queue_sz maximum number of messages in the queue.
/// \param type data type of a single message element (for debugger).
/// \note CAN BE CHANGED: The parameter to \b osMessageQDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMessageQDef(name, queue_sz, type) \
extern const osMessageQDef_t os_messageQ_def_##name
#else // define the object
#define osMessageQDef(name, queue_sz, type) \
const osMessageQDef_t os_messageQ_def_##name = \
{ (queue_sz), sizeof (type) }
#endif
/// \brief Access a Message Queue Definition.
/// \param name name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMessageQ shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMessageQ(name) \
&os_messageQ_def_##name
/// Create and Initialize a Message Queue.
/// \param[in] queue_def queue definition referenced with \ref osMessageQ.
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return message queue ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMessageCreate shall be consistent in every CMSIS-RTOS.
osMessageQId osMessageCreate (const osMessageQDef_t *queue_def, osThreadId thread_id);
/// Put a Message to a Queue.
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
/// \param[in] info message information.
/// \param[in] millisec timeout value or 0 in case of no time-out.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMessagePut shall be consistent in every CMSIS-RTOS.
osStatus osMessagePut (osMessageQId queue_id, uint32_t info, uint32_t millisec);
/// Get a Message or Wait for a Message from a Queue.
/// \param[in] queue_id message queue ID obtained with \ref osMessageCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out.
/// \return event information that includes status code.
/// \note MUST REMAIN UNCHANGED: \b osMessageGet shall be consistent in every CMSIS-RTOS.
osEvent osMessageGet (osMessageQId queue_id, uint32_t millisec);
#endif // Message Queues available
// ==== Mail Queue Management Functions ====
#if (defined (osFeature_MailQ) && (osFeature_MailQ != 0)) // Mail Queues available
/// \brief Create a Mail Queue Definition.
/// \param name name of the queue
/// \param queue_sz maximum number of messages in queue
/// \param type data type of a single message element
/// \note CAN BE CHANGED: The parameter to \b osMailQDef shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#if defined (osObjectsExternal) // object is external
#define osMailQDef(name, queue_sz, type) \
extern const osMailQDef_t os_mailQ_def_##name
#else // define the object
#define osMailQDef(name, queue_sz, type) \
const osMailQDef_t os_mailQ_def_##name = \
{ (queue_sz), sizeof (type) }
#endif
/// \brief Access a Mail Queue Definition.
/// \param name name of the queue
/// \note CAN BE CHANGED: The parameter to \b osMailQ shall be consistent but the
/// macro body is implementation specific in every CMSIS-RTOS.
#define osMailQ(name) \
&os_mailQ_def_##name
/// Create and Initialize mail queue.
/// \param[in] queue_def reference to the mail queue definition obtain with \ref osMailQ
/// \param[in] thread_id thread ID (obtained by \ref osThreadCreate or \ref osThreadGetId) or NULL.
/// \return mail queue ID for reference by other functions or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMailCreate shall be consistent in every CMSIS-RTOS.
osMailQId osMailCreate (const osMailQDef_t *queue_def, osThreadId thread_id);
/// Allocate a memory block from a mail.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMailAlloc shall be consistent in every CMSIS-RTOS.
void *osMailAlloc (osMailQId queue_id, uint32_t millisec);
/// Allocate a memory block from a mail and set memory block to zero.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out
/// \return pointer to memory block that can be filled with mail or NULL in case of error.
/// \note MUST REMAIN UNCHANGED: \b osMailCAlloc shall be consistent in every CMSIS-RTOS.
void *osMailCAlloc (osMailQId queue_id, uint32_t millisec);
/// Put a mail to a queue.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] mail memory block previously allocated with \ref osMailAlloc or \ref osMailCAlloc.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMailPut shall be consistent in every CMSIS-RTOS.
osStatus osMailPut (osMailQId queue_id, void *mail);
/// Get a mail from a queue.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] millisec timeout value or 0 in case of no time-out
/// \return event that contains mail information or error code.
/// \note MUST REMAIN UNCHANGED: \b osMailGet shall be consistent in every CMSIS-RTOS.
osEvent osMailGet (osMailQId queue_id, uint32_t millisec);
/// Free a memory block from a mail.
/// \param[in] queue_id mail queue ID obtained with \ref osMailCreate.
/// \param[in] mail pointer to the memory block that was obtained with \ref osMailGet.
/// \return status code that indicates the execution status of the function.
/// \note MUST REMAIN UNCHANGED: \b osMailFree shall be consistent in every CMSIS-RTOS.
osStatus osMailFree (osMailQId queue_id, void *mail);
#endif // Mail Queues available
#ifdef __cplusplus
}
#endif
#endif // _CMSIS_OS_H

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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@ -0,0 +1,914 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex-M0+
@{
*/
/* CMSIS CM0+ definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000U
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0U
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1U)
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1U)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0+ header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_SC000_H_GENERIC
#define __CORE_SC000_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup SC000
@{
*/
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_SC (000U) /*!< Cortex secure core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __TMS470__ )
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __CSMC__ )
#define __packed
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
#define __STATIC_INLINE static inline
#else
#error Unknown compiler
#endif
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TMS470__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "core_cmInstr.h" /* Core Instruction Access */
#include "core_cmFunc.h" /* Core Function Access */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_SC000_H_DEPENDANT
#define __CORE_SC000_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV
#define __SC000_REV 0x0000U
#warning "__SC000_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0U
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group SC000 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED0[1U];
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED1[154U];
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1U)
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/**
\brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register Definitions */
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register Definitions */
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register Definitions */
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register Definitions */
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register Definitions */
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the SC000 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of SC000 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1U)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/**
\brief Enable External Interrupt
\details Enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Disable External Interrupt
\details Disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Get Pending Interrupt
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
/**
\brief Set Interrupt Priority
\details Sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of an interrupt.
The interrupt number can be positive to specify an external (device specific) interrupt,
or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_SC000_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "pinnames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART_0 = (int)RDA_UART0_BASE,
UART_1 = (int)RDA_UART1_BASE
} UARTName;
typedef enum {
// Make sure GPIO_BASE & 0x1F == 0, store GPIO index at this field when mapping pins
GPIO_0 = (int)RDA_GPIO_BASE
} GPIOName;
typedef enum {
I2C_0 = (int)RDA_I2C0_BASE
} I2CName;
typedef enum {
SPI_0 = (int)RDA_SPI0_BASE
} SPIName;
typedef enum {
I2S_0 = (int)RDA_I2S_BASE
} I2SName;
typedef enum {
WDT_0 = (int)RDA_WDT_BASE
} WDTName;
typedef enum {
PWM_0 = 0,
PWM_1,
PWM_2,
PWM_3,
PWM_4,
PWM_5,
PWM_6,
PWM_7
} PWMName;
typedef enum {
ADC0_0 = 0,
ADC0_1,
ADC0_2
} ADCName;
typedef enum {
GPADC0_0 = 0,
GPADC0_1
} GPADCName;
#define STDIO_UART_TX UART0_TX
#define STDIO_UART_RX UART0_RX
#define STDIO_UART UART_0
// Default peripherals
#define MBED_UART0 PA_0, PA_1
#define MBED_UART1 PB_1, PB_2
#define MBED_UARTUSB USBTX, USBRX
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 4,
PortD = 5
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "flash_api.h"
#include "flash_data.h"
//#include "mbed_critical.h"
#include "critical.h"
#include "rda_flash.h"
// This file is automagically generated
// This is a flash algo binary blob. It is PIC (position independent code) that should be stored in RAM
static uint32_t FLASH_ALGO[] = {
0x4df0e92d, 0x4180f04f, 0x68082400, 0xea322203, 0xbf1c62d0, 0x50c0f040, 0x49cc6008, 0xf0106808,
0xd1100f40, 0x00c0f040, 0x03086008, 0x68486088, 0x0001f040, 0x20006048, 0x28081c40, 0x6848d3fc,
0x0f01f010, 0x4dc2d1fb, 0x0835f04f, 0x8000f8c5, 0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01,
0xf0106928, 0xd17b0f02, 0x6c704eba, 0x007cf420, 0x1010f440, 0x68b06470, 0x2040f440, 0x209f60b0,
0x20006028, 0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x6928d1fb, 0x69286929, 0x2102b2ca, 0xf04f2705,
0xf04f0a00, 0x2a400b01, 0xb2c0d123, 0xd9202815, 0xf36f6868, 0xf4402010, 0x60687080, 0xf00060a9,
0x2031f92b, 0x20006028, 0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x602fd1fb, 0x1c402000, 0xd3fc2808,
0xf01068e8, 0xd1fb0f01, 0xf0106928, 0xd1f20f01, 0x6868e021, 0x2010f36f, 0x7000f440, 0xf8c56068,
0x60a9a008, 0xf908f000, 0xb000f8c5, 0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, 0x2000602f,
0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x6928d1fb, 0x0f01f010, 0x4a88d1f2, 0x444a2100, 0x8000f8c5,
0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, 0x1c496928, 0x6f80f5b1, 0x2401d303, 0xa000f882,
0xf010e00d, 0xd0e90f02, 0x6968b94c, 0x0001f040, 0x6c706168, 0x00d8f440, 0xf8826470, 0x4620b000,
0x8df0e8bd, 0x47702000, 0x47702000, 0xf000b510, 0x496ff8c3, 0x60082060, 0x1c402000, 0xd3fc2808,
0xf01068c8, 0xd1fb0f01, 0x600a2205, 0x1c402000, 0xd3fc2808, 0xf01068c8, 0xd1fb0f01, 0xf0106908,
0xd1f20f01, 0x68484961, 0x0001f040, 0x20006048, 0x28081c40, 0x6848d3fc, 0x0001f010, 0xbd10d1fb,
0x4604b510, 0xf898f000, 0x20204959, 0x2004ea40, 0x20006008, 0x28081c40, 0x68c8d3fc, 0x0f01f010,
0x2205d1fb, 0x2000600a, 0x28081c40, 0x68c8d3fc, 0x0f01f010, 0x6908d1fb, 0x0f01f010, 0x494bd1f2,
0xf0406848, 0x60480001, 0x1c402000, 0xd3fc2808, 0xf0106848, 0xd1fb0001, 0xe92dbd10, 0xf02005f0,
0x4845437c, 0x78004448, 0xbf142800, 0x24022432, 0x2c11ea5f, 0x68684d3e, 0x2010f36f, 0x3080f440,
0xf04f6068, 0xbf1c0100, 0x26052706, 0xf04fd042, 0x20000800, 0xa000f812, 0xa008f8c5, 0x28041c40,
0x1d12dbf8, 0x0801f108, 0x0f40f1b8, 0x602fdbf1, 0x1c402000, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01,
0x2000602e, 0x28081c40, 0x68e8d3fc, 0x0f01f010, 0x6928d1fb, 0x0f02f010, 0xea44d0f2, 0x60282003,
0xf5032000, 0x1c407380, 0xd3fc2808, 0xf01068e8, 0xd1fb0f01, 0x2000602e, 0x28081c40, 0x68e8d3fc,
0x0f01f010, 0x6928d1fb, 0x0f01f010, 0x1c49d1f2, 0xd3bc4561, 0x68484915, 0x0001f040, 0x20006048,
0x28081c40, 0x6848d3fc, 0x0001f010, 0xe8bdd1fb, 0x477005f0, 0x47704408, 0x2006490d, 0x20006008,
0x28081c40, 0x68c8d3fc, 0x0f01f010, 0x2205d1fb, 0x2000600a, 0x28081c40, 0x68c8d3fc, 0x0f01f010,
0x6908d1fb, 0x0f02f010, 0x4770d0f2, 0x40014000, 0x17fff000, 0x40001000, 0x00000004, 0x00000000,
0x00000000
};
static const flash_algo_t flash_algo_config = {
.init = 0x1,
.uninit = 0x185,
.erase_sector = 0x1e1,
.program_page = 0x23b,
.static_base = 0x35c,
.algo_blob = FLASH_ALGO
};
static const sector_info_t sectors_info[] = {
{0x18000000, 0x1000},
};
static const flash_target_config_t flash_target_config = {
.page_size = 0x100,
.flash_start = 0x18000000,
.flash_size = FLASH_SIZE,
.sectors = sectors_info,
.sector_info_count = sizeof(sectors_info) / sizeof(sector_info_t)
};
void flash_set_target_config(flash_t *obj)
{
obj->flash_algo = &flash_algo_config;
obj->target_config = &flash_target_config;
}

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/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "flash_api.h"
#include "flash_data.h"
//#include "mbed_critical.h"
#include "critical.h"
#define MBED_FLASH_ALGO_ERASE 1UL
#define MBED_FLASH_ALGO_PROGRAM 2UL
extern uint32_t SystemCoreClock;
/*
This binary blob (thumb code) sets r9 (static base) as the code we are jumping to
is PIC (position independent code).
These are the instructions (r0 is a pointer to arg_t):
push {r5, lr, r4}
mov r5, r9
push {r5}
ldr r5, [r0, #20]
ldr r3, [r0, #16]
mov r9, r3
ldr r3, [r0, #12]
ldr r2, [r0, #8]
ldr r1, [r0, #4]
ldr r0, [r0, #0]
blx r5
pop {r5}
mov r9, r5
pop {r4-r5, pc}
bx r14
*/
static uint32_t jump_to_flash_algo[] = {
0x464DB530,
0x6945B420,
0x46996903,
0x688268C3,
0x68006841,
0xBC2047A8,
0xBD3046A9
};
// should be called within critical section
static int32_t flash_algo_init(flash_t *obj, uint32_t address, uint32_t function)
{
args_t arguments = {
.r0 = address,
.r1 = SystemCoreClock,
.r2 = function,
.r3 = 0,
.r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
.pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->init
};
return ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
}
// should be called within critical section
static int32_t flash_algo_uninit(flash_t *obj, uint32_t address, uint32_t function)
{
args_t arguments = {
.r0 = address,
.r1 = SystemCoreClock,
.r2 = function,
.r3 = 0,
.r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
.pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->uninit
};
return ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
}
int32_t flash_init(flash_t *obj)
{
flash_set_target_config(obj);
return 0;
}
int32_t flash_free(flash_t *obj)
{
return 0;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
core_util_critical_section_enter();
flash_algo_init(obj, address, MBED_FLASH_ALGO_ERASE);
args_t arguments = {
.r0 = address,
.r1 = 0,
.r2 = 0,
.r3 = 0,
.r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
.pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->erase_sector
};
int32_t ret = ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
flash_algo_uninit(obj, address, MBED_FLASH_ALGO_ERASE);
core_util_critical_section_exit();
return ret ? -1 : 0;
}
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
{
core_util_critical_section_enter();
flash_algo_init(obj, address, MBED_FLASH_ALGO_PROGRAM);
args_t arguments = {
.r0 = address,
.r1 = size,
.r2 = (uint32_t)data,
.r3 = 0,
.r9 = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->static_base,
.pc = (uint32_t)obj->flash_algo->algo_blob + obj->flash_algo->program_page
};
int32_t ret = ((flash_algo_jump_t)(((uint32_t)&jump_to_flash_algo) | 1))(&arguments);
flash_algo_uninit(obj, address, MBED_FLASH_ALGO_PROGRAM);
core_util_critical_section_exit();
return ret ? -1 : 0;
}
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
const sector_info_t *sectors = obj->target_config->sectors;
if (address >= obj->target_config->flash_start + obj->target_config->flash_size) {
return MBED_FLASH_INVALID_SIZE;
}
int sector_index = obj->target_config->sector_info_count - 1;
for (; sector_index >= 0; sector_index--) {
if (address >= sectors[sector_index].start) {
return sectors[sector_index].size;
}
}
return MBED_FLASH_INVALID_SIZE;
}
uint32_t flash_get_page_size(const flash_t *obj)
{
return obj->target_config->page_size;
}
uint32_t flash_get_start_address(const flash_t *obj)
{
return obj->target_config->flash_start;
}
uint32_t flash_get_size(const flash_t *obj)
{
return obj->target_config->flash_size;
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "gpio_api.h"
#include "pinmap.h"
#include "rda_ccfg_api.h"
#include "stddef.h"
#define NONE (uint32_t)NC
#define GPIO_INT_CTRL_REG (RDA_GPIO->INTCTRL)
#define GPIO_INT_SEL_REG (RDA_GPIO->INTSEL)
#define GPIO_DATA_IN_REG (RDA_GPIO->DIN)
#if defined(GPIO_IRQ_DEBUG)
static uint32_t exception_cntr;
#endif /* GPIO_IRQ_DEBUG */
static uint32_t channel_ids[CHANNEL_NUM] = {0};
static uint32_t channel_arg[CHANNEL_NUM] = {0};
static uint32_t channel_pinidxs[CHANNEL_NUM] = {0};
static uint8_t channel_bothedge_flag[CHANNEL_NUM] = {0};
static gpio_irq_handler irq_handler[CHANNEL_NUM] = {NULL};
static const PinMap PinMap_GPIO[] = {
{PB_0, (GPIO_0 | 0), 0},
{PB_1, (GPIO_0 | 1), 0},
{PB_2, (GPIO_0 | 2), 0},
{PB_3, (GPIO_0 | 3), 0},
{PB_4, (GPIO_0 | 4), 0},
{PB_5, (GPIO_0 | 5), 0},
{PB_6, (GPIO_0 | 6), 0},
{PB_7, (GPIO_0 | 7), 0},
{PB_8, (GPIO_0 | 8), 0},
{PB_9, (GPIO_0 | 9), 0},
{PA_8, (GPIO_0 | 10), 0},
{PA_9, (GPIO_0 | 11), 0},
{PC_0, (GPIO_0 | 12), 1},
{PC_1, (GPIO_0 | 13), 1},
{PC_2, (GPIO_0 | 14), 0},
{PC_3, (GPIO_0 | 15), 0},
{PC_4, (GPIO_0 | 16), 0},
{PC_5, (GPIO_0 | 17), 0},
{PC_6, (GPIO_0 | 18), 0},
{PC_7, (GPIO_0 | 19), 0},
{PC_8, (GPIO_0 | 20), 0},
{PC_9, (GPIO_0 | 21), 0},
{PD_0, (GPIO_0 | 22), 0},
{PD_1, (GPIO_0 | 23), 0},
{PD_2, (GPIO_0 | 24), 0},
{PD_3, (GPIO_0 | 25), 0},
{PA_0, (GPIO_0 | 26), 1},
{PA_1, (GPIO_0 | 27), 1},
{PA_2, (GPIO_0 | 14), 1},
{PA_3, (GPIO_0 | 15), 1},
{PA_4, (GPIO_0 | 16), 1},
{PA_5, (GPIO_0 | 17), 1},
{PA_6, (GPIO_0 | 18), 1},
{PA_7, (GPIO_0 | 19), 1},
{NC, NC, 0}
};
#define PER_BITBAND_ADDR(reg, bit) (uint32_t *)(RDA_PERBTBND_BASE + (((uint32_t)(reg)-RDA_PER_BASE)<<5U) + (((uint32_t)(bit))<<2U))
PinName gpio_pinname(int pin_n) {
MBED_ASSERT(pin_n < GPIO_NUM);
return PinMap_GPIO[pin_n].pin;
}
uint32_t gpio_set(PinName pin) {
MBED_ASSERT(pin != (PinName)NC);
uint32_t func = 0;
uint32_t idx = 0;
func = pinmap_function(pin, PinMap_GPIO);
idx = pinmap_peripheral(pin, PinMap_GPIO) & 0x001F;
pin_function(pin, func);
return idx;
}
void gpio_init(gpio_t *obj, PinName pin) {
uint32_t gpio_idx = 0;
obj->pin = pin;
if (pin == (PinName)NC)
return;
gpio_idx = gpio_set(pin);
if((6U <= gpio_idx) && (9U >= gpio_idx)) {
rda_ccfg_gp((unsigned char)gpio_idx, 0x01U);
}
obj->reg_out = PER_BITBAND_ADDR(&RDA_GPIO->DOUT, gpio_idx);
obj->reg_in = PER_BITBAND_ADDR(&RDA_GPIO->DIN, gpio_idx);
obj->reg_dir = PER_BITBAND_ADDR(&RDA_GPIO->DIR, gpio_idx);
}
void gpio_mode(gpio_t *obj, PinMode mode) {
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
uint32_t dir = 0x00UL;
MBED_ASSERT(obj->pin != (PinName)NC);
if(PIN_INPUT == direction) {
dir = 0x01UL;
}
if(rda_ccfg_hwver() >= 5) {
uint32_t gpio_idx = pinmap_peripheral(obj->pin, PinMap_GPIO) & 0x001F;
/* Since U05, for gpio 2/3/8/14/15/16/17/20/21, 1'b1 means output */
if(0x00UL != (0x0033C10CUL & (0x01UL << gpio_idx))) {
dir ^= 0x01UL;
}
}
*obj->reg_dir = dir;
}
static GPIO_IRQ_IDX_T gpio_irq_ava_chidx(void)
{
GPIO_IRQ_IDX_T ret;
for(ret = GPIO_IRQ_CH0; ret < CHANNEL_NUM; ret++) {
if(0 == channel_ids[ret])
break;
}
return ret;
}
static uint32_t gpio_irq_pinidx(PinName pin)
{
uint8_t idx;
const uint32_t pinmap_gpio_irq[GPIO_NUM] = {
/* GPIO 0 ~ 13 */
PB_0, PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PA_8, PA_9, PC_0, PC_1,
/* GPIO 14 ~ 21, Not support interrupt */
NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,
/* GPIO 22 ~ 27 */
PD_0, PD_1, PD_2, PD_3, PA_0, PA_1
};
for(idx = 0; idx < GPIO_NUM; idx++) {
if(pinmap_gpio_irq[idx] == NONE) {
continue;
} else if(pinmap_gpio_irq[idx] == (uint32_t)pin) {
break;
}
}
if(GPIO_NUM == idx) {
error("The pin cannot generate interrupt");
}
return idx;
}
static void handle_interrupt_in(void) {
/* Read current interrupt register */
uint32_t int_ctrl = GPIO_INT_CTRL_REG;
uint32_t din_val = GPIO_DATA_IN_REG;
uint32_t idx;
if(int_ctrl & (0x01UL << 16)) {
GPIO_INT_CTRL_REG |= (0x01UL << 16);
while(GPIO_INT_CTRL_REG & (0x01UL << 16));
}
for(idx = GPIO_IRQ_CH0; idx < CHANNEL_NUM; idx++) {
if(int_ctrl & (0x01UL << (21 + idx))) {
gpio_irq_event flagRiseFall_1, flagRiseFall_2;
GPIO_INT_CTRL_REG |= (0x01UL << (17 + idx)); // clear int flag
flagRiseFall_1 = (int_ctrl & (0x01UL << (2 + idx))) ? IRQ_RISE : IRQ_FALL;
flagRiseFall_2 = (din_val & (0x01UL << channel_pinidxs[idx])) ? IRQ_RISE : IRQ_FALL;
if(channel_bothedge_flag[idx]){
if(0 != channel_ids[idx]){
irq_handler[idx](channel_ids[idx], flagRiseFall_2, channel_arg[idx]);
}
}else if(flagRiseFall_1 == flagRiseFall_2) {
// if(channel_bothedge_flag[idx]) {
// GPIO_INT_CTRL_REG ^= (0x01UL << (2 + idx));
// }
if (0 != channel_ids[idx]) {
irq_handler[idx](channel_ids[idx], flagRiseFall_1, channel_arg[idx]);
}
#if defined(GPIO_IRQ_DEBUG)
exception_cntr = 0;
#endif /* GPIO_IRQ_DEBUG */
}
#if defined(GPIO_IRQ_DEBUG)
else {
exception_cntr++;
if(exception_cntr >= 2) {
exception_cntr = 0;
mbed_error_printf("invalid gpio irq: %d,%d\r\n", (int)flagRiseFall_1, (int)flagRiseFall_2);
}
}
#endif /* GPIO_IRQ_DEBUG */
}
}
}
static void irq_handler_entry(uint32_t id, gpio_irq_event event, uint32_t arg) {
void(*handler)(void*) = (void(*)(void*))id;
switch (event) {
case IRQ_RISE: handler((void *)arg); break;
case IRQ_FALL: handler((void *)arg);
case IRQ_NONE: break;
}
}
int gpio_irq_init(gpio_t *obj, uint32_t handler, uint32_t arg) {
uint32_t regval;
if (obj->pin == NC) return -1;
obj->ch = (uint16_t)gpio_irq_ava_chidx();
MBED_ASSERT(CHANNEL_NUM != obj->ch);
irq_handler[obj->ch] = irq_handler_entry;
channel_ids[obj->ch] = handler;
channel_pinidxs[obj->ch] = gpio_irq_pinidx(obj->pin);
channel_arg[obj->ch] = arg;
regval = RDA_GPIO->INTSEL & ~(0x3FFUL << 10);
RDA_GPIO->INTSEL = regval | (0x3FFUL << 10);
NVIC_SetVector(GPIO_IRQn, (uint32_t)handle_interrupt_in);
NVIC_SetPriority(GPIO_IRQn, 0x1FUL);
return 0;
}
void gpio_irq_free(gpio_t *obj) {
channel_ids[obj->ch] = 0;
}
void gpio_irq_set(gpio_t *obj, gpio_irq_event event, uint32_t enable) {
uint32_t reg_val;
uint16_t intEn;
MBED_ASSERT(1 >= obj->ch);
if(IRQ_RISE == event) {
obj->flagR = (uint8_t)enable;
} else {
obj->flagF = (uint8_t)enable;
}
if(obj->flagR && obj->flagF)
channel_bothedge_flag[obj->ch] = 1U;
else
channel_bothedge_flag[obj->ch] = 0U;
if(obj->flagR || obj->flagF)
intEn = 1;
else
intEn = 0;
if(0 == intEn) {
GPIO_INT_CTRL_REG &= ~(0x01UL << (6 + obj->ch));
} else {
/* Set interrupt select reg */
NVIC_DisableIRQ(GPIO_IRQn);
if(!(obj->flagF && obj->flagR)){
reg_val = GPIO_INT_SEL_REG & ~(0x1FUL << (5 * obj->ch));
GPIO_INT_SEL_REG = reg_val | ((0x1FUL & ((channel_pinidxs[obj->ch] >= 22) ? (channel_pinidxs[obj->ch] - 8) : channel_pinidxs[obj->ch])) << (5 * obj->ch));
}
/* Set interrupt control reg */
reg_val = GPIO_INT_CTRL_REG & ~(0x01UL << (2 + obj->ch));
GPIO_INT_CTRL_REG = reg_val | (((channel_bothedge_flag[obj->ch]) ? (reg_val | (0x01U << obj->ch)) : (((1U == obj->flagR)) ? ((0x01UL << (2 + obj->ch)) | (0x01UL << (17+obj->ch))) : (0x00UL)))
| (0x01UL << (6 + obj->ch)));
NVIC_EnableIRQ(GPIO_IRQn);
}
}
void gpio_irq_enable() {
NVIC_EnableIRQ(GPIO_IRQn);
}
void gpio_irq_disable() {
NVIC_DisableIRQ(GPIO_IRQn);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
__IO uint32_t *reg_out;
__I uint32_t *reg_in;
__IO uint32_t *reg_dir;
uint16_t ch;
uint8_t flagR;
uint8_t flagF;
} gpio_t;
static inline void gpio_write(gpio_t *obj, int value) {
MBED_ASSERT(obj->pin != (PinName)NC);
*obj->reg_out = ((value) ? 1 : 0);
}
static inline int gpio_read(gpio_t *obj) {
MBED_ASSERT(obj->pin != (PinName)NC);
return ((*obj->reg_in) ? 1 : 0);
}
static inline int gpio_is_connected(const gpio_t *obj) {
return obj->pin != (PinName)NC;
}
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode)
{
gpio_init(gpio, pin);
if (pin != NC) {
gpio_dir(gpio, PIN_INPUT);
gpio_mode(gpio, mode);
}
}
static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value)
{
gpio_init(gpio, pin);
if (pin != NC) {
gpio_write(gpio, value);
gpio_dir(gpio, PIN_OUTPUT);
gpio_mode(gpio, mode);
}
}
void gpio_init_in(gpio_t* gpio, PinName pin) {
gpio_init_in_ex(gpio, pin, PullDefault);
}
void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
_gpio_init_in(gpio, pin, mode);
}
void gpio_init_out(gpio_t* gpio, PinName pin) {
gpio_init_out_ex(gpio, pin, 0);
}
void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
_gpio_init_out(gpio, pin, PullNone, value);
}
void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
if (direction == PIN_INPUT) {
_gpio_init_in(gpio, pin, mode);
if (pin != NC)
gpio_write(gpio, value); // we prepare the value in case it is switched later
} else {
_gpio_init_out(gpio, pin, mode, value);
}
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "cmsis.h"
#include "mbed_error.h"
#include "rda_ccfg_api.h"
#if RDA5991H_HW_VER <= 4
extern void sleep_cal_lpo(unsigned int calms);
#endif
/* This function is called after RAM initialization and before main. */
void mbed_sdk_init(void)
{
/* Update the SystemCoreClock variable. */
SystemCoreClockUpdate();
if(rda_ccfg_hwver() <= 4) {
sleep_cal_lpo(500U);
}
if(rda_ccfg_hwver() != RDA5991H_HW_VER) {
error("\r\nHW=%d/SW=%d not match\r\n", rda_ccfg_hwver(), RDA5991H_HW_VER);
}
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pinmap.h"
#include "mbed_error.h"
void pinmap_pinout(PinName pin, const PinMap *map) {
if (pin == NC)
return;
while (map->pin != NC) {
if (map->pin == pin) {
pin_function(pin, map->function);
pin_mode(pin, PullNone);
return;
}
map++;
}
error("could not pinout");
}
uint32_t pinmap_merge(uint32_t a, uint32_t b) {
// both are the same (inc both NC)
if (a == b)
return a;
// one (or both) is not connected
if (a == (uint32_t)NC)
return b;
if (b == (uint32_t)NC)
return a;
// mis-match error case
error("pinmap mis-match");
return (uint32_t)NC;
}
uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
while (map->pin != NC) {
if (map->pin == pin)
return map->peripheral;
map++;
}
return (uint32_t)NC;
}
uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
uint32_t peripheral = (uint32_t)NC;
if (pin == (PinName)NC)
return (uint32_t)NC;
peripheral = pinmap_find_peripheral(pin, map);
if ((uint32_t)NC == peripheral) // no mapping available
error("pinmap not found for peripheral");
return peripheral;
}
uint32_t pinmap_find_function(PinName pin, const PinMap* map) {
while (map->pin != NC) {
if (map->pin == pin)
return map->function;
map++;
}
return (uint32_t)NC;
}
uint32_t pinmap_function(PinName pin, const PinMap* map) {
uint32_t function = (uint32_t)NC;
if (pin == (PinName)NC)
return (uint32_t)NC;
function = pinmap_find_function(pin, map);
if ((uint32_t)NC == function) // no mapping available
error("pinmap not found for function");
return function;
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "pinnames.h"
#include "gpio_object.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
uint16_t ch;
uint8_t flagR;
uint8_t flagF;
};
struct port_s {
PortName port;
uint32_t mask;
__IO uint32_t *reg_out;
__I uint32_t *reg_in;
__IO uint32_t *reg_dir;
};
struct pwmout_s {
uint32_t channel;
uint32_t *base_clk_ptr;
uint32_t period_ticks;
uint32_t pulsewidth_ticks;
uint32_t period_ticks_max;
uint32_t period_ticks_min;
PinName pin;
__IO uint32_t *CFGR;
};
struct trng_s {
uint8_t dma_clk_flag;
uint8_t byte_idx;
uint32_t trng_data0;
};
struct serial_s {
RDA_UART_TypeDef *uart;
int index;
};
struct i2s_s {
RDA_I2S_TypeDef *i2s;
};
struct wdt_s {
RDA_WDT_TypeDef *wdt;
};
struct analogin_s {
ADCName adc;
};
struct gpadc_s {
GPADCName ch;
PinName pin;
};
#if 0
struct dac_s {
DACName dac;
};
#endif
struct i2c_s {
RDA_I2C0_TypeDef *i2c;
};
struct spi_s {
RDA_SPI_TypeDef *spi;
uint8_t bit_ofst[2];
};
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "rda_ccfg_api.h"
void pin_function(PinName pin, int function) {
int index = pin >> PORT_SHIFT;
int raw_ofst = pin & 0x00FF;
int offset;
MBED_ASSERT(pin != (PinName)NC);
switch(index) {
case 1:
if((8 == raw_ofst) && (rda_ccfg_hwver() >= 5)) {
function ^= 0x01;
}
break;
case 4:
if(1 < raw_ofst) {
offset = raw_ofst << 1;
RDA_PINCFG->MODE2 &= ~(0x03UL << offset);
}
break;
case 5:
if(2 > raw_ofst) {
offset = (raw_ofst << 1) + 20;
RDA_PINCFG->MODE2 &= ~(0x03UL << offset);
} else {
offset = (raw_ofst << 1) - 4;
RDA_PINCFG->MODE3 &= ~(0x03UL << offset);
}
break;
default:
break;
}
offset = raw_ofst * 3;
RDA_PINCFG->IOMUXCTRL[index] &= ~(0x07UL << offset);
RDA_PINCFG->IOMUXCTRL[index] |= ((function & 0x07UL) << offset);
}
void pin_mode(PinName pin, PinMode mode) {
MBED_ASSERT(pin != (PinName)NC);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 8
typedef enum {
PA_0 = (0 << PORT_SHIFT | 0 ),
PA_1 = (0 << PORT_SHIFT | 1 ),
PA_2 = (0 << PORT_SHIFT | 2 ),
PA_3 = (0 << PORT_SHIFT | 3 ),
PA_4 = (0 << PORT_SHIFT | 4 ),
PA_5 = (0 << PORT_SHIFT | 5 ),
PA_6 = (0 << PORT_SHIFT | 6 ),
PA_7 = (0 << PORT_SHIFT | 7 ),
PA_8 = (0 << PORT_SHIFT | 8 ),
PA_9 = (0 << PORT_SHIFT | 9 ),
PB_0 = (1 << PORT_SHIFT | 0 ),
PB_1 = (1 << PORT_SHIFT | 1 ),
PB_2 = (1 << PORT_SHIFT | 2 ),
PB_3 = (1 << PORT_SHIFT | 3 ),
PB_4 = (1 << PORT_SHIFT | 4 ),
PB_5 = (1 << PORT_SHIFT | 5 ),
PB_6 = (1 << PORT_SHIFT | 6 ),
PB_7 = (1 << PORT_SHIFT | 7 ),
PB_8 = (1 << PORT_SHIFT | 8 ),
PB_9 = (1 << PORT_SHIFT | 9 ),
PC_0 = (4 << PORT_SHIFT | 0 ),
PC_1 = (4 << PORT_SHIFT | 1 ),
PC_2 = (4 << PORT_SHIFT | 2 ),
PC_3 = (4 << PORT_SHIFT | 3 ),
PC_4 = (4 << PORT_SHIFT | 4 ),
PC_5 = (4 << PORT_SHIFT | 5 ),
PC_6 = (4 << PORT_SHIFT | 6 ),
PC_7 = (4 << PORT_SHIFT | 7 ),
PC_8 = (4 << PORT_SHIFT | 8 ),
PC_9 = (4 << PORT_SHIFT | 9 ),
PD_0 = (5 << PORT_SHIFT | 0 ),
PD_1 = (5 << PORT_SHIFT | 1 ),
PD_2 = (5 << PORT_SHIFT | 2 ),
PD_3 = (5 << PORT_SHIFT | 3 ),
PD_9 = (5 << PORT_SHIFT | 9 ), // Fake pin for GPADC_VBAT
UART0_RX = PA_0,
UART0_TX = PA_1,
UART1_RX = PB_1,
UART1_TX = PB_2,
USBRX = UART0_RX,
USBTX = UART0_TX,
I2C_SCL = PC_0,
I2C_SDA = PC_1,
I2S_TX_SD = PB_1,
I2S_TX_WS = PB_2,
I2S_TX_BCLK = PB_3,
I2S_RX_SD = PB_4,
I2S_RX_WS = PB_5,
I2S_RX_BCLK = PB_8,
GPIO_PIN0 = PB_0,
GPIO_PIN1 = PB_1,
GPIO_PIN2 = PB_2,
GPIO_PIN3 = PB_3,
GPIO_PIN4 = PB_4,
GPIO_PIN5 = PB_5,
GPIO_PIN6 = PB_6,
GPIO_PIN7 = PB_7,
GPIO_PIN8 = PB_8,
GPIO_PIN9 = PB_9,
GPIO_PIN10 = PA_8,
GPIO_PIN11 = PA_9,
GPIO_PIN12 = PC_0,
GPIO_PIN13 = PC_1,
GPIO_PIN14 = PC_2,
GPIO_PIN15 = PC_3,
GPIO_PIN16 = PC_4,
GPIO_PIN17 = PC_5,
GPIO_PIN18 = PC_6,
GPIO_PIN19 = PC_7,
GPIO_PIN20 = PC_8,
GPIO_PIN21 = PC_9,
GPIO_PIN22 = PD_0,
GPIO_PIN23 = PD_1,
GPIO_PIN24 = PD_2,
GPIO_PIN25 = PD_3,
GPIO_PIN26 = PA_0,
GPIO_PIN27 = PA_1,
// Another pin names for GPIO 14 - 19
GPIO_PIN14A = PA_2,
GPIO_PIN15A = PA_3,
GPIO_PIN16A = PA_4,
GPIO_PIN17A = PA_5,
GPIO_PIN18A = PA_6,
GPIO_PIN19A = PA_7,
ADC_PIN0 = PB_6,
ADC_PIN1 = PB_7,
ADC_PIN1A = PB_8, // Another pin name for ADC 1
ADC_PIN2 = PD_9,
LED1 = GPIO_PIN0,
LED2 = GPIO_PIN1,
LED3 = GPIO_PIN2,
LED4 = GPIO_PIN3,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
Repeater = 3,
PullDefault = Repeater,
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
extern PinName gpio_pinname(int pin_n);
PinName port_pin(PortName port, int pin_n) {
return (PinName)((port << PORT_SHIFT) | pin_n);
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
uint32_t i;
obj->port = port;
obj->mask = mask;
obj->reg_out = &RDA_GPIO->DOUT;
obj->reg_in = &RDA_GPIO->DIN;
obj->reg_dir = &RDA_GPIO->DIR;
// The mode is set per pin: reuse gpio logic
for (i = 0; i < 32; i++) {
if(obj->mask & (1 << i)) {
// For RDA5991H, port0,1,4,5 is about IOMUX, not GPIO number, cannot use port_pin here
//gpio_set(port_pin(obj->port, i));
gpio_set(gpio_pinname(i));
}
}
port_dir(obj, dir);
}
void port_mode(port_t *obj, PinMode mode) {
uint32_t i;
// The mode is set per pin: reuse pinmap logic
for (i = 0; i < 32; i++) {
if(obj->mask & (1 <<i )) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir) {
switch (dir) {
case PIN_INPUT :
*obj->reg_dir |= obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir &= ~obj->mask;
break;
}
}
void port_write(port_t *obj, int value) {
*obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
}
int port_read(port_t *obj) {
return (*obj->reg_in & obj->mask);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pwmout_api.h"
#include "gpio_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_interface.h"
#define PWM_CLK_SRC_20MHZ (20000000)
#define PWM_CLK_SRC_32KHZ (32768)
#define PWM_CLK_IDX_NUM (3)
#define PWM_DIFF_CHN_NUM (2)
#define PWM_SYNC_CHN_NUM (2)
#define PWM_CLKGATE_REG (RDA_SCU->CLKGATE1)
#define PWM_CLKSRC_REG (RDA_SCU->PWMCFG)
#define PWM_CLKDIV_REG (RDA_PWM->CLKR)
#define EXIF_PWM_EN_REG (RDA_EXIF->MISCCFG)
#define PWM_DIFF0_REG (RDA_EXIF->PWM0CFG)
#define PWM_DIFF3_REG (RDA_EXIF->PWM3CFG)
/* PORT ID, PWM ID, Pin function */
static const PinMap PinMap_PWM[] = {
{PA_0, PWM_6, 4},
{PA_1, PWM_3, 4},
{PB_0, PWM_2, 4},
{PB_1, PWM_7, 4},
{PB_2, PWM_5, 4},
{PB_3, PWM_4, 4},
{PB_8, PWM_0, 4},
{PC_1, PWM_1, 5},
{PD_0, PWM_0, 4},
{PD_1, PWM_1, 4},
{PD_2, PWM_2, 4},
{PD_3, PWM_3, 4},
{NC, NC, 0}
};
__IO uint32_t *PWM_MATCH[] = {
&(RDA_EXIF->PWM0CFG),
&(RDA_EXIF->PWM1CFG),
&(RDA_EXIF->PWM2CFG),
&(RDA_EXIF->PWM3CFG),
&( RDA_PWM->PWTCFG ),
&( RDA_PWM->LPGCFG ),
&( RDA_PWM->PWL0CFG),
&( RDA_PWM->PWL1CFG)
};
static uint32_t BaseClk_PWM[PWM_CLK_IDX_NUM] = {0UL};
static PinName PWM_DIFF_CHN[PWM_DIFF_CHN_NUM]= {0UL};
static uint32_t pwm0_period;
static uint32_t pwm0_sync_pulsewidth;
static uint32_t pwm0_duty;
static uint32_t pwm3_period;
static uint32_t pwm3_sync_pulsewidth;
static uint32_t pwm3_duty;
static uint8_t pwm_sync_cfged;
static PinName PWM_SYNC_CHN[PWM_SYNC_CHN_NUM]= {0UL};
extern gpio_t gpio_p1;
static uint8_t is_pwmout_started(pwmout_t* obj);
static void pwmout_start(pwmout_t* obj);
static void pwmout_stop(pwmout_t* obj);
static void pwmout_update_cfgreg(pwmout_t* obj);
static void pwmout_cfgreg(pwmout_t* obj);
void pwmout_clk_set(pwmout_t *obj, int src, int div)
{
uint32_t reg_val = 0UL;
uint32_t clk_idx = 0UL, clk_hz = PWM_CLK_SRC_32KHZ >> 1;
PWMName pwm = (PWMName)(obj->channel);
uint32_t divider = (uint32_t)div;
MBED_ASSERT(PWM_7 >= pwm);
if (PWM_5 == pwm) {
clk_idx = 1;
} else if (PWM_6 <= pwm) {
clk_idx = 2;
}
if (divider > 0x80UL) { // max divider is 128
divider = 0x80UL;
}
reg_val = PWM_CLKSRC_REG & ~((0x00FFUL << (clk_idx * 8)) | (0x01UL << (24 + clk_idx)));
if (src) {
reg_val |= (0x01UL << (7 + (clk_idx * 8)));
clk_hz = PWM_CLK_SRC_20MHZ >> 1;
}
if (divider) {
reg_val |= ((divider - 0x01UL) << (clk_idx * 8));
BaseClk_PWM[clk_idx] = clk_hz / divider;
} else {
BaseClk_PWM[clk_idx] = clk_hz;
}
PWM_CLKSRC_REG = reg_val | (0x01UL << (24 + clk_idx));
}
void pwmout_init(pwmout_t* obj, PinName pin)
{
/* determine the channel */
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
obj->channel = pwm;
obj->CFGR = PWM_MATCH[pwm];
obj->pin = pin;
if(obj->channel == PWM_0){
PWM_DIFF_CHN[0] = pin;
}else if(obj->channel == PWM_3){
PWM_DIFF_CHN[1] = pin;
}
/* Enable PWM Clock-gating */
PWM_CLKGATE_REG |= (0x01UL << 2);
/* Init PWM clock source and divider */
if (PWM_4 >= pwm) {
/* default to 20MHz / 2 */
pwmout_clk_set(obj, 1, 0);
if (PWM_4 == pwm) {
obj->period_ticks_max = 0x1FF8UL;
obj->period_ticks_min = 0x0008UL;
} else {
obj->period_ticks_max = 0x20000UL;
obj->period_ticks_min = 0x00002UL;
}
obj->base_clk_ptr = &(BaseClk_PWM[0]);
} else if (PWM_5 == pwm) {
/* default to 32KHz / 2 */
pwmout_clk_set(obj, 0, 0);
obj->period_ticks_max = 0x7000UL;
obj->period_ticks_min = 0x0800UL;
obj->base_clk_ptr = &(BaseClk_PWM[1]);
} else {
/* default to 20MHz / 2 */
pwmout_clk_set(obj, 1, 0);
//do not need to div
obj->period_ticks_max = 0x0FFUL; // TBD
obj->period_ticks_min = 0x001UL;
obj->base_clk_ptr = &(BaseClk_PWM[2]);
}
// default to half of max period
if (PWM_5 >= pwm) {
pwmout_period_us(obj, (obj->period_ticks_max * 1e6) / (*(obj->base_clk_ptr)) / 2);
}
//PWM6 PWM7 has no period
//pwmout_write (obj, 0.5f);
// Wire pinout
pinmap_pinout(pin, PinMap_PWM);
gpio_t gpio;
gpio_init(&gpio,pin);
gpio_dir(&gpio, PIN_OUTPUT);
}
void pwmout_free(pwmout_t* obj)
{
/* Disable PWM Clock-gating */
PWM_CLKGATE_REG &= ~(0x01UL << 2);
}
void pwmout_sync_write(pwmout_t *obj, float value, uint8_t duty_sel)
{
uint32_t ticks;
uint32_t p_ticks_h = 0xFFF;
uint32_t p_ticks_l = 0x0;
uint32_t reg_val;
uint32_t pwm_src_deft;
uint8_t clk_div;
uint8_t clk_sel; //0:32K 1:20M
int err_code = 0;
static float value0;
if (obj->period_ticks < obj->period_ticks_min) {
obj->period_ticks = obj->period_ticks_min;
err_code = 1; // too small period
}
if (obj->period_ticks > obj->period_ticks_max) {
obj->period_ticks = obj->period_ticks_max;
err_code = 2; // too large period
if (obj->pulsewidth_ticks > obj->period_ticks_max) {
obj->pulsewidth_ticks = obj->period_ticks_max;
err_code = 3; // too large period & duty
}
}
if (0 != err_code) {
mbed_error_printf("PwmCfgErr:%d\r\n",err_code);
}
if (value < 0.0f) {
value = 0.0;
} else if (value > 1.0f) {
value = 1.0;
}
ticks = (uint32_t)((float)(obj->period_ticks) * value);
if(ticks != obj->pulsewidth_ticks) {
obj->pulsewidth_ticks = ticks;
}
if(PWM_0 == (PWMName)obj->channel){
pwm0_period = obj->period_ticks;
pwm0_sync_pulsewidth = obj->pulsewidth_ticks;
PWM_SYNC_CHN[0] = obj->pin;
pwm0_duty = duty_sel;
pwm_sync_cfged |= 1;
}
if(PWM_3 == (PWMName)obj->channel){
pwm3_period = obj->period_ticks;
pwm3_sync_pulsewidth = obj->pulsewidth_ticks;
PWM_SYNC_CHN[1] = obj->pin;
pwm3_duty = duty_sel;
pwm_sync_cfged |= (1 << 1);
}
if(pwm_sync_cfged != 3){
}
else{
core_util_critical_section_enter();
if(pwm3_duty == pwm0_duty){
mbed_error_printf("PwmCfgErr: same duty in sync mode\r\n");
}
#if 1
gpio_t gpio;
gpio_init_out(&gpio, PWM_SYNC_CHN[0]);
gpio_write(&gpio, 0);
gpio_init_out_ex(&gpio, PWM_SYNC_CHN[1], 1);
gpio_write(&gpio, 1);
#endif
reg_val = PWM_CLKSRC_REG;
clk_div = reg_val & 0x7F;
clk_sel = ((reg_val& 0xFF) >> 7);
pwm_src_deft = (reg_val & (~((0x1 << 24) | 0x7F))) | (0x1 << 7); //pwt_clk:disable divider:0 pwt_fast_clk:20mhz
//mux to gpio
//disable PWM0 & PWM3
EXIF_PWM_EN_REG &= ~(0x9 << 8); //disable pwm0 pwm3
if(pwm0_duty == 1){
PWM_DIFF0_REG = (p_ticks_h << 16 | p_ticks_l); //pwm1:0xFF 0x00
}
else if(pwm3_duty == 1){
PWM_DIFF3_REG = (p_ticks_h << 16 | p_ticks_l);
}
#if 0
//reset clk
if((clk_sel == 0) | (clk_div >= 0x2)){
//---create a pwm clk---
PWM_CLKSRC_REG &= ~(0x1 << 24);
PWM_CLKSRC_REG = pwm_src_deft;
PWM_CLKSRC_REG |= (0x1 << 24); //pwt_clk:disable divider:0 pwt_fast_clk:20mhz
}
else{
}
//recfg clk_div
if((clk_sel == 0) | (clk_div >= 0x2)){
//---create a pwm clk---
PWM_CLKSRC_REG &= ~(0x1 << 24);
PWM_CLKSRC_REG |= (clk_sel << 7) | (clk_div); //divider:clk_div pwt_fast_clk:20mhz
PWM_CLKSRC_REG |= (0x1 << 24);
}
else{
}
#endif
//enable pwm 0
if(pwm0_duty == 1){
EXIF_PWM_EN_REG |= (0x1 << 8); //enable pwm0
}
else if(pwm3_duty == 1){
EXIF_PWM_EN_REG |= (0x1 << 11);
}
#if 0
if((clk_sel == 0) | (clk_div >= 0x1)){
if((clk_sel == 1) & (clk_div == 0x1)){
PWM_CLKSRC_REG &= ~(0x1 << 24);
PWM_CLKSRC_REG |= (0x1 << 24);
}
else{
//---create a pwm clk---
PWM_CLKSRC_REG &= ~(0x1 << 24);
PWM_CLKSRC_REG = pwm_src_deft;
PWM_CLKSRC_REG |= (0x1 << 24);
}
}
else{
}
if((clk_sel == 0) | (clk_div >= 0x2)){
//---create a pwm clk---
PWM_CLKSRC_REG &= ~(0x1 << 24);
PWM_CLKSRC_REG |= (clk_sel << 7) | (clk_div);
PWM_CLKSRC_REG |= (0x1 << 24);
}
else{
}
#endif
// if (obj->period_ticks == obj->pulsewidth_ticks) {
// PWM_DIFF0_REG = ((obj->pulsewidth_ticks - 1) << 16);
// } else {
PWM_DIFF0_REG = (pwm0_period - pwm0_sync_pulsewidth - 1) |
((pwm0_sync_pulsewidth - 1) << 16);
// }
// PWM_DIFF3_REG = (pwm3_sync_pulsewidth - 1) |
// ((pwm3_period - pwm3_sync_pulsewidth - 1) << 16);
PWM_DIFF3_REG = (pwm3_period - pwm3_sync_pulsewidth - 1) |
((pwm3_sync_pulsewidth - 1) << 16);
EXIF_PWM_EN_REG |= (0x9 << 8);
// gpio_t gpio;
if (pwm0_period == pwm0_sync_pulsewidth) {
gpio_init_out_ex(&gpio, PWM_SYNC_CHN[0],1);
gpio_write(&gpio, 1);
}
else if(0 == pwm0_sync_pulsewidth){
gpio_init_out(&gpio, PWM_SYNC_CHN[0]);
gpio_write(&gpio, 0);
}
else {
pinmap_pinout(PWM_SYNC_CHN[0], PinMap_PWM);
}
if (pwm3_period == pwm3_sync_pulsewidth) {
gpio_init_out_ex(&gpio, PWM_SYNC_CHN[1], 1);
gpio_write(&gpio, 1);
}
else if (0 == pwm3_sync_pulsewidth){
gpio_init_out(&gpio, PWM_SYNC_CHN[1]);
gpio_write(&gpio, 0);
}
else {
pinmap_pinout(PWM_SYNC_CHN[1], PinMap_PWM);
}
pwm_sync_cfged = 0;
core_util_critical_section_exit();
}
}
void pwmout_write(pwmout_t* obj, float value)
{
uint32_t ticks;
if (value < 0.0f) {
value = 0.0;
} else if (value > 1.0f) {
value = 1.0;
}
/* Set channel match to percentage */
if(PWM_5 >= (PWMName)obj->channel){
ticks = (uint32_t)((float)(obj->period_ticks) * value);
}
else if(PWM_6 <= (PWMName)obj->channel){
obj->period_ticks = 0xFF;
ticks = (uint32_t)((float)(obj->period_ticks) * value);
}
if (0 == ticks) {
obj->pulsewidth_ticks = 0;
} else {
/* Update Hw reg */
if(ticks != obj->pulsewidth_ticks) {
obj->pulsewidth_ticks = ticks;
pwmout_update_cfgreg(obj);
}
}
/* Check if already started */
if(is_pwmout_started(obj)){
if (PWM_4 != (PWMName)obj->channel){
pwmout_stop(obj);
}
}
/* Start PWM module */
pwmout_start(obj);
}
void pwmout_write_ext(pwmout_t* obj, uint32_t value)
{
uint32_t ticks;
ticks = value;
if (0 == ticks) {
obj->pulsewidth_ticks = 0;
} else {
/* Update Hw reg */
if(ticks != obj->pulsewidth_ticks) {
obj->pulsewidth_ticks = ticks;
pwmout_cfgreg(obj);
}
}
/* Check if already started */
if(is_pwmout_started(obj)){
if (PWM_4 != (PWMName)obj->channel){
pwmout_stop(obj);
}
}
/* Start PWM module */
pwmout_start(obj);
}
//only use in 10M source clk mode
//gpio0 ->PB_8 gpio1 ->PC_1
void pwmout_diff_write(pwmout_t *obj, float value)
{
uint32_t ticks;
uint32_t p_ticks_h = 0xFFF;
uint32_t p_ticks_l = 0x0;
uint32_t reg_val;
uint32_t pwm_src_deft;
uint8_t clk_div;
uint8_t clk_sel; //0:32K 1:20M
int err_code = 0;
MBED_ASSERT(PWM_0 >= (PWMName)(obj->channel));
if (obj->period_ticks < obj->period_ticks_min) {
obj->period_ticks = obj->period_ticks_min;
err_code = 1; // too small period
}
if (obj->period_ticks > obj->period_ticks_max) {
obj->period_ticks = obj->period_ticks_max;
err_code = 2; // too large period
if (obj->pulsewidth_ticks > obj->period_ticks_max) {
obj->pulsewidth_ticks = obj->period_ticks_max;
err_code = 3; // too large period & duty
}
}
if (0 != err_code) {
mbed_error_printf("PwmCfgErr:%d\r\n",err_code);
}
if (value < 0.0f) {
value = 0.0;
} else if (value > 1.0f) {
value = 1.0;
}
ticks = (uint32_t)((float)(obj->period_ticks) * value);
if(ticks != obj->pulsewidth_ticks) {
obj->pulsewidth_ticks = ticks;
}
reg_val = PWM_CLKSRC_REG;
clk_div = reg_val & 0x7F;
clk_sel = (reg_val & 0xFF) >> 7;
pwm_src_deft = (reg_val & (~((0x1 << 24) | 0x7F))) | (0x1 << 7);
//mux to gpio
//disable PWM pwm to 0
EXIF_PWM_EN_REG &= ~(0x9 << 8);
PWM_DIFF0_REG = (p_ticks_h << 16 | p_ticks_l);
if((clk_sel == 0) | (clk_div >= 0x2)){
//---create a pwm clk---
PWM_CLKSRC_REG &= ~(0x1 << 24);
PWM_CLKSRC_REG = pwm_src_deft;
PWM_CLKSRC_REG |= (0x1 << 24);
}
else{
}
if((clk_sel == 0) | (clk_div >= 0x2)){
//---create a pwm clk---
PWM_CLKSRC_REG &= ~(0x1 << 24);
PWM_CLKSRC_REG |= (clk_sel << 7) | (clk_div);
PWM_CLKSRC_REG |= (0x1 << 24);
}
else{
}
//enable pwm 0
EXIF_PWM_EN_REG |= (0x1 << 8);
if((clk_sel == 0) | (clk_div >= 0x1)){
if((clk_sel == 1) & (clk_div == 0x1)){
PWM_CLKSRC_REG &= ~(0x1 << 24);
PWM_CLKSRC_REG |= (0x1 << 24);
}
else{
//---create a pwm clk---
PWM_CLKSRC_REG &= ~(0x1 << 24);
PWM_CLKSRC_REG = pwm_src_deft;
PWM_CLKSRC_REG |= (0x1 << 24);
}
}
else{
}
if((clk_sel == 0) | (clk_div >= 0x2)){
PWM_CLKSRC_REG &= ~(0x1 << 24);
PWM_CLKSRC_REG |= (clk_sel << 7) | (clk_div);
PWM_CLKSRC_REG |= (0x1 << 24);
}
else{
}
if (obj->period_ticks == obj->pulsewidth_ticks) {
PWM_DIFF0_REG = ((obj->pulsewidth_ticks - 1) << 16);
} else {
PWM_DIFF0_REG = (obj->period_ticks - obj->pulsewidth_ticks - 1) |
((obj->pulsewidth_ticks - 1) << 16);
}
PWM_DIFF3_REG = (obj->pulsewidth_ticks - 1) |
((obj->period_ticks - obj->pulsewidth_ticks - 1) << 16);
EXIF_PWM_EN_REG |= (0x9 << 8);
if (obj->period_ticks == obj->pulsewidth_ticks) {
gpio_t gpio;
//gpio_init_out_ex(&gpio, PB_8, 1);
gpio_init_out_ex(&gpio, PWM_DIFF_CHN[0],1);
gpio_write(&gpio, 1);
gpio_init_out(&gpio, PWM_DIFF_CHN[1]);
gpio_write(&gpio, 0);
//mbed_error_printf("100\n");
} else if (0 == obj->pulsewidth_ticks) {
gpio_t gpio;
gpio_init_out(&gpio, PWM_DIFF_CHN[0]);
gpio_write(&gpio, 0);
gpio_init_out_ex(&gpio, PWM_DIFF_CHN[1], 1);
gpio_write(&gpio, 1);
//mbed_error_printf("0\n");
} else {
pinmap_pinout(PWM_DIFF_CHN[0], PinMap_PWM);
pinmap_pinout(PWM_DIFF_CHN[1], PinMap_PWM);
}
}
float pwmout_read(pwmout_t* obj)
{
float v = (float)(obj->pulsewidth_ticks) / (float)(obj->period_ticks);
return (v > 1.0f) ? (1.0f) : (v);
}
void pwmout_period(pwmout_t* obj, float seconds)
{
pwmout_period_us(obj, seconds * 1000000.0f);
}
void pwmout_period_ms(pwmout_t* obj, int ms)
{
pwmout_period_us(obj, ms * 1000);
}
/* Set the PWM period, keeping the duty cycle the same. */
void pwmout_period_us(pwmout_t* obj, int us)
{
uint32_t ticks;
MBED_ASSERT(PWM_5 >= (PWMName)(obj->channel));
/* Check if already started */
if(is_pwmout_started(obj))
pwmout_stop(obj);
/* Calculate number of ticks */
ticks = (uint64_t)(*(obj->base_clk_ptr)) * us / 1000000;
if(ticks != obj->period_ticks) {
float duty_ratio;
/* Preserve the duty ratio */
if (0 == obj->period_ticks)
duty_ratio = 0.5f;
else
duty_ratio = (float)obj->pulsewidth_ticks / (float)obj->period_ticks;
obj->period_ticks = ticks;
obj->pulsewidth_ticks = (uint32_t)(ticks * duty_ratio);
MBED_ASSERT(obj->period_ticks >= obj->pulsewidth_ticks);
pwmout_update_cfgreg(obj);
}
/* Start PWM module */
pwmout_start(obj);
}
void pwmout_pulsewidth(pwmout_t* obj, float seconds)
{
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
{
pwmout_pulsewidth_us(obj, ms * 1000);
}
/* Set the PWM pulsewidth, keeping the period the same. */
void pwmout_pulsewidth_us(pwmout_t* obj, int us)
{
uint32_t ticks;
MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel));
/* Check if already started */
if(is_pwmout_started(obj))
pwmout_stop(obj);
/* Calculate number of ticks */
ticks = (uint64_t)(*(obj->base_clk_ptr)) * us / 1000000;
if(ticks != obj->pulsewidth_ticks) {
obj->pulsewidth_ticks = ticks;
MBED_ASSERT(obj->period_ticks >= obj->pulsewidth_ticks);
pwmout_update_cfgreg(obj);
}
/* Start PWM module */
pwmout_start(obj);
}
static uint8_t is_pwmout_started(pwmout_t* obj)
{
uint8_t retVal = 0;
uint32_t reg_val;
MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel));
if(PWM_3 >= (PWMName)obj->channel) {
reg_val = (EXIF_PWM_EN_REG >> 8) & 0x0FUL;
if(reg_val & (0x01UL << obj->channel))
retVal = 1;
} else if(PWM_4 == (PWMName)obj->channel) {
if(*(obj->CFGR) & (0x01UL << 1))
retVal = 1;
} else if(PWM_5 == (PWMName)obj->channel) {
retVal = 1;
} else {
if(*(obj->CFGR) & (0x01UL << 16))
retVal = 1;
}
return retVal;
}
static void pwmout_start(pwmout_t* obj)
{
MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel));
if (obj->period_ticks == obj->pulsewidth_ticks) {
gpio_t gpio;
gpio_init_out_ex(&gpio, obj->pin,1);
gpio_write(&gpio, 1);
//mbed_error_printf("100\n");
} else if (0 == obj->pulsewidth_ticks) {
gpio_t gpio;
gpio_init_out(&gpio, obj->pin);
gpio_write(&gpio, 0);
//mbed_error_printf("0\n");
} else {
pinmap_pinout(obj->pin, PinMap_PWM);
}
if(PWM_3 >= (PWMName)obj->channel) {
EXIF_PWM_EN_REG |= (0x01UL << (8 + obj->channel));
} else if(PWM_4 == (PWMName)obj->channel) {
*(obj->CFGR) |= 0x01UL;
} else if(PWM_5 == (PWMName)obj->channel) {
/* Nothing to be done */
} else {
*(obj->CFGR) |= (0x01UL << 16);
}
}
static void pwmout_stop(pwmout_t* obj)
{
MBED_ASSERT(PWM_7 >= (PWMName)(obj->channel));
if (obj->period_ticks == obj->pulsewidth_ticks) {
gpio_t gpio;
gpio_init_out(&gpio, obj->pin);
gpio_write(&gpio, 0);
}
if(PWM_3 >= (PWMName)obj->channel) {
EXIF_PWM_EN_REG &= ~(0x01UL << (8 + obj->channel));
} else if(PWM_4 == (PWMName)(obj->channel)) {
*(obj->CFGR) &= ~0x01UL;
} else if(PWM_5 == (PWMName)(obj->channel)) {
/* Nothing to be done */
} else {
*(obj->CFGR) &= ~(0x01UL << 16);
}
}
static void pwmout_update_cfgreg(pwmout_t* obj)
{
int err_code = 0;
if (obj->period_ticks < obj->period_ticks_min) {
obj->period_ticks = obj->period_ticks_min;
err_code = 1; // too small duty & period
}
if (obj->period_ticks > obj->period_ticks_max) {
obj->period_ticks = obj->period_ticks_max;
err_code = 2; // too large period
if (obj->pulsewidth_ticks > obj->period_ticks_max) {
obj->pulsewidth_ticks = obj->period_ticks_max;
err_code = 3; // too large period & duty
}
}
if (0 != err_code) {
mbed_error_printf("PwmCfgErr:%d\r\n",err_code);
}
if(PWM_3 >= (PWMName)(obj->channel)) {
if (obj->period_ticks == obj->pulsewidth_ticks) {
*(obj->CFGR) = ((obj->pulsewidth_ticks - 1) << 16);
} else {
*(obj->CFGR) = ((obj->period_ticks - obj->pulsewidth_ticks - 1) & 0xFFFFUL) |
((obj->pulsewidth_ticks - 1) << 16);
}
} else if(PWM_4 == (PWMName)(obj->channel)) {
*(obj->CFGR) = ((obj->pulsewidth_ticks & ~0x07UL) << ( 4 - 3)) |
((obj->period_ticks & ~0x07UL) << (16 - 3));
} else if(PWM_5 == (PWMName)(obj->channel)) {
/* TBD */
uint32_t reg_val = *(obj->CFGR) & ~(0xFUL << 4) & ~(0x7UL << 16);
uint32_t lpg_field_ontime = (0x01UL << 4) & (0xFUL << 4); // to be confirm
uint32_t lpg_field_period = (obj->period_ticks << 4) & (0x7UL << 16);
*(obj->CFGR) = reg_val | lpg_field_ontime | lpg_field_period;
} else if(PWM_6 == (PWMName)(obj->channel)){
uint32_t reg_val = *(obj->CFGR) & ~(0xFF);
*(obj->CFGR) = reg_val | (obj->pulsewidth_ticks);//1~254
} else{
//PWM_7
uint32_t reg_val = *(obj->CFGR) & ~(0xFF);
*(obj->CFGR) = reg_val | (obj->pulsewidth_ticks);//1~254
}
}
static void pwmout_cfgreg(pwmout_t* obj)
{
__NOP();
if(PWM_3 >= (PWMName)(obj->channel)) {
if (obj->period_ticks == obj->pulsewidth_ticks) {
*(obj->CFGR) = ((obj->pulsewidth_ticks - 1) << 16);
} else {
*(obj->CFGR) = ((obj->period_ticks - obj->pulsewidth_ticks - 1) & 0xFFFFUL) |
((obj->pulsewidth_ticks - 1) << 16);
}
} else if(PWM_4 == (PWMName)(obj->channel)) {
*(obj->CFGR) = ((obj->pulsewidth_ticks & ~0x07UL) << ( 4 - 3)) |
((obj->period_ticks & ~0x07UL) << (16 - 3));
} else if(PWM_5 == (PWMName)(obj->channel)) {
/* TBD */
uint32_t reg_val = *(obj->CFGR) & ~(0xFUL << 4) & ~(0x7UL << 16);
uint32_t lpg_field_ontime = (0x01UL << 4) & (0xFUL << 4); // to be confirm
uint32_t lpg_field_period = (obj->period_ticks << 4) & (0x7UL << 16);
*(obj->CFGR) = reg_val | lpg_field_ontime | lpg_field_period;
} else if(PWM_6 == (PWMName)(obj->channel)){
uint32_t reg_val = *(obj->CFGR) & ~(0xFF);
*(obj->CFGR) = reg_val | (obj->pulsewidth_ticks);//1~254
} else{
//PWM_7
uint32_t reg_val = *(obj->CFGR) & ~(0xFF);
*(obj->CFGR) = reg_val | (obj->pulsewidth_ticks);//1~254
}
}

42
Living_SDK/platform/mcu/rda5981x/driver/rda5981x_pinconfig.h Normal file
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#ifndef RDA5981X_PINCONFIG_H
#define RDA5981X_PINCONFIG_H
#include "pinnames.h"
/* UART PIN defines */
#define RDA_UART0_TXD GPIO_PIN27
#define RDA_UART0_RXD GPIO_PIN26
#define RDA_UART1_TXD GPIO_PIN25
#define RDA_UART1_RXD GPIO_PIN24
#define RDA_UART1_RTS GPIO_PIN23
#define RDA_UART1_CTS GPIO_PIN22
#define RDA_UART1_TXD_2 GPIO_PIN2
#define RDA_UART1_RXD_2 GPIO_PIN1
/* SPI PIN defines */
#define RDA_SPI0_CLK GPIO_PIN22
#define RDA_SPI0_CS GPIO_PIN23
#define RDA_SPI0_MOSI GPIO_PIN24
#define RDA_SPI0_MISO GPIO_PIN25
#define RDA_SPI0_CLK_2 GPIO_PIN4
#define RDA_SPI0_CS_2 GPIO_PIN26
#define RDA_SPI0_MOSI_2 GPIO_PIN6
#define RDA_SPI0_MISO_2 GPIO_PIN7
#define RDA_SPI0_CS_3 GPIO_PIN27
#define RDA_SPI0_MOSI_3 GPIO_PIN12
#define RDA_SPI0_MISO_3 GPIO_PIN13
#define RDA_SPI0_CS_4 GPIO_PIN5
/* I2C PIN defines */
#define RDA_I2C0_SCL GPIO_PIN3
#define RDA_I2C0_SDA GPIO_PIN2
#define RDA_I2C0_SCL_2 GPIO_PIN23
#define RDA_I2C0_SDA_2 GPIO_PIN22
/* ADC PIN defines */
#define RDA_ADC0
#define RDA_ADC1
#endif

74
Living_SDK/platform/mcu/rda5981x/driver/rda_dma.h Normal file
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#ifndef _RDA_DMA_H_
#define _RDA_DMA_H_
#define RDA_HW_ACCELERATE_ENABLE 1
typedef enum _dma_mode {
NORMAL_MODE = 0,
AES_ENC_MODE = 1,
AES_DEC_MODE = 5,
TX_CRC_MODE = 2,
RX_CRC_MODE = 6
}dma_mode;
typedef enum _dma_int_out_dscp {
AHB_DMA_DONE = (1<<0),
PRNG_ALERT = (1<<1),
TRNG_ON_FLY_TEST_FAIL = (1<<2),
TRNG_START_TEST_FAIL = (1<<3),
TRNG_DATA_READY = (1<<4),
CIOS_DONE = (1<<5)
}dma_int_out_dscp;
typedef enum _dma_ctrl_hsizem{
DMACtrlHsizemByte = 0U, /*!< DMA ctrl hsizem 8 bits */
DMACtrlHsizemHalfword = 1U, /*!< DMA ctrl hsizem 16 bits */
DMACtrlHsizemWord = 2U /*!< DMA ctrl hsizem 32 bits */
}dma_ctrl_hsizem;
typedef enum _dma_ctrl_fix_src{
DMACtrlSrcAddrIncrease = 0U, /*!< DMA ctrl fix src off */
DMACtrlFixSrcAddr = 1U /*!< DMA ctrl fix src on */
}dma_ctrl_fix_src;
typedef enum _dma_ctrl_fix_dst{
DMACtrlDstAddrIncrease = 0U, /*!< DMA ctrl fix dst off */
DMACtrlFixDstAddr = 1U /*!< DMA ctrl fix dst on */
}dma_ctrl_fix_dst;
#ifndef RDA_SCU_CLK_GATE0_ENABLE
#define RDA_SCU_CLK_GATE0_ENABLE() do { \
RDA_SCU->CLKGATE0 |= (1 << 18); \
for (int j=0; j<4; j++) ; \
} while(0)
#endif
#ifndef RDA_SCU_CLK_GATE0_DISABLE
#define RDA_SCU_CLK_GATE0_DISABLE() do { \
RDA_SCU->CLKGATE0 &= ~(1 << 18); \
} while(0)
#endif
/*
* 32-bit integer manipulation macros (big endian)
*/
#ifndef PUT_UINT32_BE
#define PUT_UINT32_BE(n,b,i) \
{ \
(b)[(i) + 3] = (unsigned char) ( ( (n) ) & 0xFF ); \
(b)[(i) + 2] = (unsigned char) ( ( (n) >> 8 ) & 0xFF ); \
(b)[(i) + 1] = (unsigned char) ( ( (n) >> 16 ) & 0xFF ); \
(b)[(i) + 0] = (unsigned char) ( ( (n) >> 24 ) & 0xFF ); \
}
#endif /* PUT_UINT32_BE */
#ifndef GET_UINT32_BE
#define GET_UINT32_BE(n,b,i) \
{ \
(n) = ( (unsigned int) (b)[(i) + 3] ) \
| ( (unsigned int) (b)[(i) + 2] << 8 ) \
| ( (unsigned int) (b)[(i) + 1] << 16 ) \
| ( (unsigned int) (b)[(i) + 0] << 24 ); \
}
#endif /* GET_UINT32_BE */
#endif /* _RDA_DMA_H_ */

177
Living_SDK/platform/mcu/rda5981x/driver/rda_flash.c Normal file
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#include "rda_def.h"
#include "rda_flash.h"
r_u32 flash_size = FLASH_SIZE;
int rda5981_read_flash(r_u32 addr, char *buf, r_u32 len)
{
int ret = 0;
char *temp_buf = NULL, *temp_buf_aligned;
addr &= (flash_size -1);
if (addr < RDA5991H_PARTITION_TABLE_END_ADDR-0x18000000) {
printf(" couldn't read system data\n");
return -1;
}
if ((r_u32)buf % 4) {
temp_buf = r_malloc(len + 3);
if (temp_buf == NULL) {
ret = -1;
goto out;
}
if ((r_u32)temp_buf % 4)
temp_buf_aligned = temp_buf + (4-(r_u32)temp_buf%4);
else
temp_buf_aligned = temp_buf;
} else {
temp_buf_aligned = buf;
}
core_util_critical_section_enter();
//RDA5991H_READ_FLASH(addr, temp_buf_aligned, len);
spi_flash_flush_cache();
SPI_FLASH_READ_DATA_FOR_MBED((void *)addr, temp_buf_aligned, len);
core_util_critical_section_exit();
if (temp_buf_aligned != buf)
r_memcpy(buf, temp_buf_aligned, len);
out:
if (temp_buf)
r_free(temp_buf);
return ret;
}
void rda5981_spi_flash_erase_64KB_block(r_u32 addr)
{
if (rda_ccfg_hwver() < 4) {
spi_wip_reset();
spi_write_reset();
WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, CMD_64KB_BLOCK_ERASE | (addr<<8));
wait_busy_down();
spi_wip_reset();
} else {
spi_wip_reset_4();
spi_write_reset_4();
WRITE_REG32(FLASH_CTL_TX_CMD_ADDR_REG, CMD_64KB_BLOCK_ERASE | (addr<<8));
wait_busy_down_4();
spi_wip_reset_4();
}
}
void rda5981_spi_erase_partition(void *src, r_u32 counts)
{
r_u32 a4k, a64k, a64kend, a4kend, atmp;
if (counts > 0x00) {
a4k = ((r_u32)src ) & (~((0x01UL << 12) - 0x01UL));
a64k = ((r_u32)src + (0x01UL << 16) - 0x01UL) & (~((0x01UL << 16) - 0x01UL));
a64kend = ((r_u32)src + counts ) & (~((0x01UL << 16) - 0x01UL));
a4kend = ((r_u32)src + counts + (0x01UL << 12) - 0x01UL) & (~((0x01UL << 12) - 0x01UL));
for (atmp = a4k; atmp < a4kend; atmp += (0x01UL << 12)) {
if (a64kend > a64k) {
if (atmp == a64k) {
for (; atmp < a64kend; atmp += (0x01UL << 16)) {
core_util_critical_section_enter();
rda5981_spi_flash_erase_64KB_block(atmp);
core_util_critical_section_exit();
}
if (atmp == a4kend)
break;
}
}
core_util_critical_section_enter();
rda5981_spi_flash_erase_4KB_sector(atmp);
core_util_critical_section_exit();
}
}
}
//@len must be 4k aligment
int rda5981_erase_flash(r_u32 addr, r_u32 len)
{
//printf( "erase flash :%x:%x\n", addr, len);
addr &= (flash_size - 1);
if (addr < RDA5991H_PARTITION_TABLE_END_ADDR-0x18000000) {
printf( "couldn't erase system data\n");
return -1;
}
//addr &= (flash_size -1);
if (len & (SECTOR_SIZE-1)) {
len = ((len+SECTOR_SIZE) & (~(SECTOR_SIZE-1)));
}
//core_util_critical_section_enter();
rda5981_spi_erase_partition((void*)addr, len);
//core_util_critical_section_exit();
return 0;
}
//@len must be 256 aligment
int rda5981_write_flash(r_u32 addr, char *buf, r_u32 len)
{
int ret = 0;
r_u8 *temp_buf = NULL, *temp_buf_aligned;
r_u8 *check_buf = NULL;
addr &= (flash_size -1);
if (addr < RDA5991H_PARTITION_TABLE_END_ADDR-0x18000000) {
printf( "couldn't write system data\n");
return -1;
}
if ((r_u32)buf % 4) {
temp_buf = r_malloc(len + 3);
if (temp_buf == NULL) {
goto out;
}
if ((r_u32)temp_buf % 4)
temp_buf_aligned = temp_buf + (4-(r_u32)temp_buf%4);
else
temp_buf_aligned = temp_buf;
r_memcpy(temp_buf_aligned, buf, len);
} else {
temp_buf_aligned = (r_u8*)buf;
}
core_util_critical_section_enter();
//RDA5991H_ERASE_FLASH(addr, len);
RDA5991H_WRITE_FLASH(addr, temp_buf_aligned, len);
core_util_critical_section_exit();
#ifdef FLASH_READ_CHECK
if (ret == 0) {
check_buf = r_malloc(len);
rda5981_read_flash(addr, check_buf, len);
if (r_memcmp(buf, check_buf, len) == 0)
ret = 0;
else
ret = -1;
}
#endif /*FLASH_READ_CHECK*/
out:
if (temp_buf)
r_free(temp_buf);
if (check_buf)
r_free(check_buf);
return ret;
}
int rda5981_set_flash_size(const r_u32 size)
{
if (size == 0x100000 ||
size == 0x200000 ||
size == 0x400000) {
flash_size = size;
return 0;
}
return -1;
}

167
Living_SDK/platform/mcu/rda5981x/driver/rda_flash.h Normal file
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#ifndef _WLAND_FLASH_H_
#define _WLAND_FLASH_H_
//#include "wland_types.h"
// #include "rda5981_flash.h"
#include "rda_ccfg_api.h"
#include "rda_def.h"
//#define FLASH_READ_CHECK
#ifndef min
#define min(a, b) ((a)<(b)?(a):(b))
#endif /*min*/
#define SECTOR_SIZE 4096
#ifdef RDA5981A
#define FLASH_SIZE 0x100000
#elif RDA5981B
#define FLASH_SIZE 0x200000
#elif RDA5981C
#define FLASH_SIZE 0x400000
#endif
#define RDA5991H_PARTITION_TABLE_END_ADDR 0x18001000 //partition table end addr
#define FLASH_CTL_REG_BASE 0x17fff000
#define FLASH_CTL_TX_CMD_ADDR_REG (FLASH_CTL_REG_BASE + 0x00)
#define CMD_64KB_BLOCK_ERASE (0x000000d8UL)
#define WRITE_REG32(REG, VAL) ((*(volatile unsigned int*)(REG)) = (unsigned int)(VAL))
#define FLASH_ERASE_FUN_ADDR 0x21f1//smartlink_erase_for_mbed
#define FLASH_WRITE_FUN_ADDR 0x2241//smartlink_write_for_mbed
#define FLASH_READ_FUN_ADDR 0x2243//smartlink_read_for_mbed
#define FLASH_ERASE_PARTITION_FUN_ADDR 0x2139//spi_flash_erase_partition
#define SPI_FLASH_READ_DATA_FOR_MBED_ADDR 0x2007//spi_flash_read_data_for_mbed
#define spi_flash_disable_cache_addr 0x1eb7//spi_flash_disable_cache
#define spi_flash_flush_cache_addr 0x1ecd//spi_flash_flush_cache
#define spi_flash_cfg_cache_addr 0x1e9f//spi_flash_cfg_cache
#define spi_flash_erase_4KB_sector_addr 0x23a3
#define spi_wip_reset_addr 0x1d8b
#define spi_write_reset_addr 0x1d9f
#define wait_busy_down_addr 0x1d81
#define FLASH_ERASE_FUN_ADDR_4 0x2221//smartlink_erase_for_mbed
#define FLASH_WRITE_FUN_ADDR_4 0x2271//smartlink_write_for_mbed
#define FLASH_READ_FUN_ADDR_4 0x2273//smartlink_read_for_mbed
#define FLASH_ERASE_PARTITION_FUN_ADDR_4 0x2169//spi_flash_erase_partition
#define SPI_FLASH_READ_DATA_FOR_MBED_ADDR_4 0x2037//spi_flash_read_data_for_mbed
#define spi_flash_disable_cache_addr_4 0x1ee7//spi_flash_disable_cache
#define spi_flash_flush_cache_addr_4 0x1efd//spi_flash_flush_cache
#define spi_flash_cfg_cache_addr_4 0x1ecf//spi_flash_cfg_cache
#define spi_flash_erase_4KB_sector_addr_4 0x23d3
#define spi_wip_reset_addr_4 0x1dbb
#define spi_write_reset_addr_4 0x1dcf
#define wait_busy_down_addr_4 0x1db1
/*
* return 0 if find
*/
void rda5981_spi_erase_partition(void *src, r_u32 counts);
static inline void wait_busy_down(void)
{
((void(*)(void))wait_busy_down_addr)();
}
static inline void spi_write_reset(void)
{
((void(*)(void))spi_write_reset_addr)();
}
static inline void spi_wip_reset(void)
{
((void(*)(void))spi_wip_reset_addr)();
}
static inline void wait_busy_down_4(void)
{
((void(*)(void))wait_busy_down_addr_4)();
}
static inline void spi_write_reset_4(void)
{
((void(*)(void))spi_write_reset_addr_4)();
}
static inline void spi_wip_reset_4(void)
{
((void(*)(void))spi_wip_reset_addr_4)();
}
static inline void spi_flash_enable_cache(void)
{
unsigned int func = spi_flash_cfg_cache_addr;
if (rda_ccfg_hwver() >= 4) {
func = spi_flash_cfg_cache_addr_4;
}
((void(*)(void))func)();
}
static inline void spi_flash_disable_cache(void)
{
unsigned int func = spi_flash_disable_cache_addr;
if (rda_ccfg_hwver() >= 4) {
func = spi_flash_disable_cache_addr_4;
}
((void(*)(void))func)();
}
static inline void spi_flash_flush_cache(void)
{
unsigned int func = spi_flash_flush_cache_addr;
if (rda_ccfg_hwver() >= 4) {
func = spi_flash_flush_cache_addr_4;
}
((void(*)(void))func)();
}
static inline void rda5981_spi_flash_erase_4KB_sector(r_u32 addr)
{
unsigned int func = spi_flash_erase_4KB_sector_addr;
if (rda_ccfg_hwver() >= 4) {
func = spi_flash_erase_4KB_sector_addr_4;
}
((void(*)(r_u32))func)(addr);
}
static inline void RDA5991H_ERASE_FLASH(void *addr, r_u32 len)
{
unsigned int func = FLASH_ERASE_FUN_ADDR;
if (rda_ccfg_hwver() >= 4) {
func = FLASH_ERASE_FUN_ADDR_4;
}
((void(*)(void *, r_u32))func)(addr, len);
}
static inline void RDA5991H_WRITE_FLASH(r_u32 addr, r_u8 *data, r_u32 len)
{
unsigned int func = FLASH_WRITE_FUN_ADDR;
if (rda_ccfg_hwver() >= 4) {
//printf("rda_ccfg_hw > 4 \r\n");
func = FLASH_WRITE_FUN_ADDR_4;
}
((void(*)(r_u32, r_u8 *, r_u32))func)(addr, data, len);
}
static inline void RDA5991H_READ_FLASH(r_u32 addr, r_u8 *buf, r_u32 len)
{
unsigned int func = FLASH_READ_FUN_ADDR;
if (rda_ccfg_hwver() >= 4) {
func = FLASH_READ_FUN_ADDR_4;
}
((void(*)(r_u32, r_u8 *, r_u32))func)(addr, buf, len);
}
static inline void SPI_FLASH_READ_DATA_FOR_MBED(void *addr, void *buf, r_u32 len)
{
unsigned int func = SPI_FLASH_READ_DATA_FOR_MBED_ADDR;
if (rda_ccfg_hwver() >= 4) {
func = SPI_FLASH_READ_DATA_FOR_MBED_ADDR_4;
}
((void(*)(void *, void *, r_u32))func)(buf, addr, len);
}
#endif /*_WLAND_FLASH_H_*/

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
#include "mbed_assert.h"
#include <math.h>
#include <string.h>
#include <stdlib.h>
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "gpio_api.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define UART_NUM 2
#define UART_CLKGATE_REG (RDA_SCU->CLKGATE0)
#define UART1_CLKEN_MASK (0x01UL << 21)
#define RXFIFO_EMPTY_MASK (0x01UL << 0)
#define TXFIFO_FULL_MASK (0x01UL << 19)
#define AFCE_MASK (0x01UL << 5)
static const PinMap PinMap_UART_TX[] = {
{PA_1, UART_0, 0},
{PB_2, UART_1, 5},
{PD_3, UART_1, 2},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{PA_0, UART_0, 0},
{PB_1, UART_1, 5},
{PD_2, UART_1, 2},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RTS[] = {
{PD_1, UART_1, 2},
{NC, NC, 0}
};
static const PinMap PinMap_UART_CTS[] = {
{PD_0, UART_1, 2},
{NC, NC, 0}
};
static uart_irq_handler irq_handler[UART_NUM];
int stdio_uart_inited = 0;
serial_t stdio_uart;
struct serial_global_data_s {
uint32_t serial_irq_id;
gpio_t sw_rts, sw_cts;
uint8_t count, rx_irq_set_flow, rx_irq_set_api;
};
static struct serial_global_data_s uart_data[UART_NUM];
void serial_init(serial_t *obj, PinName tx, PinName rx) {
int is_stdio_uart = 0;
// determine the UART to use
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart != NC);
switch (uart) {
case UART_0:
obj->index = 0;
break;
case UART_1:
obj->index = 1;
/* Enable clock-gating */
UART_CLKGATE_REG |= UART1_CLKEN_MASK;
break;
}
obj->uart = (RDA_UART_TypeDef *)uart;
// enable fifos and default rx trigger level
obj->uart->FCR = 0 << 0 //FIFO Enable - 0 = Disables, 1 = Enabled
| 0 << 1 // Rx Fifo Reset
| 0 << 2 // Tx Fifo Reset
| 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
// disable irqs
obj->uart->IER = 0 << 0 // Rx Data available irq enable
| 0 << 1 // Tx Fifo empty irq enable
| 0 << 2; // Rx Line Status irq enable
obj->uart->MCR = 1 << 8; //select clock
obj->uart->FRR = 0x2001; //tx_trigger = 0x10, rx_trigger = 0x01
// set default baud rate and format
//serial_baud (obj, 921600);
serial_format(obj, 8, ParityNone, 1);
// pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
// set rx/tx pins in PullUp mode
if (tx != NC) {
pin_mode(tx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
if ((rx != NC) && (tx != NC)) {
obj->uart->FCR |= 1 << 0; //enable fifo
}
uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC;
serial_set_flow_control(obj, FlowControlNone, NC, NC);
is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
serial_clear(obj);
}
void serial_free(serial_t *obj) {
uart_data[obj->index].serial_irq_id = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) {
MBED_ASSERT((int)obj->uart <= UART_1);
uint32_t baud_divisor;
uint32_t baud_mod;
baud_divisor = (AHBBusClock / baudrate) >> 4;
baud_mod = (AHBBusClock / baudrate) & 0x0F;
obj->uart->LCR |= (1 << 7); //enable load devisor register
obj->uart->DLL = (baud_divisor >> 0) & 0xFF;
obj->uart->DLH = (baud_divisor >> 8) & 0xFF;
obj->uart->DL2 = (baud_mod>>1) + ((baud_mod - (baud_mod>>1))<<4);
obj->uart->LCR &= ~(1 << 7);// after loading, disable load devisor register
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
(parity == ParityForced1) || (parity == ParityForced0));
stop_bits -= 1;
data_bits -= 5;
int parity_enable, parity_select;
switch (parity) {
case ParityNone: parity_enable = 0; parity_select = 0; break;
case ParityOdd : parity_enable = 1; parity_select = 0; break;
case ParityEven: parity_enable = 1; parity_select = 1; break;
case ParityForced1: parity_enable = 1; parity_select = 2; break;
case ParityForced0: parity_enable = 1; parity_select = 3; break;
default:
parity_enable = 0; parity_select = 0;
break;
}
obj->uart->LCR |= (data_bits << 0
| stop_bits << 2
| parity_enable << 3
| parity_select << 4);
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static inline void uart_irq(uint32_t iir, uint32_t index, RDA_UART_TypeDef *puart) {
SerialIrq irq_type;
switch (iir) {
case 0x02UL: irq_type = TxIrq; break;
case 0x04UL: irq_type = RxIrq; break;
case 0x00UL: iir = puart->MSR;
default: return;
}
if ((RxIrq == irq_type) && ((NC != uart_data[index].sw_rts.pin) && ((puart->MCR & AFCE_MASK) != 1))) {
gpio_write(&uart_data[index].sw_rts, 1);
// Disable interrupt if it wasn't enabled by other part of the application
if (!uart_data[index].rx_irq_set_api)
puart->IER &= ~(1 << RxIrq);
}
if (uart_data[index].serial_irq_id != 0)
if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
(irq_handler[index])(index, irq_type);
}
void uart0_irq() {uart_irq((RDA_UART0->IIR & 0x0FUL), 0, (RDA_UART_TypeDef*)RDA_UART0);}
void uart1_irq() {uart_irq((RDA_UART1->IIR & 0x0FUL), 1, (RDA_UART_TypeDef*)RDA_UART1);}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler[obj->index] = handler;
uart_data[obj->index].serial_irq_id = id;
}
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type irq_n = (IRQn_Type)0;
uint32_t vector = 0;
switch ((int)obj->uart) {
case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
}
if (enable) {
obj->uart->IER |= 1 << irq;
NVIC_SetVector(irq_n, vector);
NVIC_SetPriority(irq_n, 0x1FUL);
NVIC_EnableIRQ(irq_n);
}
else if ((TxIrq == irq) ||
(uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
int all_disabled = 0;
SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
obj->uart->IER &= ~(1 << irq);
all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
if (all_disabled)
NVIC_DisableIRQ(irq_n);
}
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
if (RxIrq == irq)
uart_data[obj->index].rx_irq_set_api = enable;
serial_irq_set_internal(obj, irq, enable);
}
static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
uart_data[obj->index].rx_irq_set_flow = enable;
serial_irq_set_internal(obj, RxIrq, enable);
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
int data = 0;
while (!serial_readable(obj));
data = (int)(obj->uart->RBR & 0x00FFUL);
if (((obj->uart->MCR & AFCE_MASK) != 1) && (NC != uart_data[obj->index].sw_rts.pin)) { //enable flow control rx
gpio_write(&uart_data[obj->index].sw_rts, 0);
obj->uart->IER |= 1 << RxIrq;
}
return data;
}
void serial_putc(serial_t *obj, int c) {
while (serial_writable(obj));
obj->uart->THR = c;
}
int serial_readable(serial_t *obj) {
return (obj->uart->LSR & RXFIFO_EMPTY_MASK);
}
int serial_writable(serial_t *obj) {
int isWritable = 1;
if(obj->index == 0)
return (obj->uart->FSR & TXFIFO_FULL_MASK); // uart0 not have flow control
else {
if (((obj->uart->MCR & AFCE_MASK) != 1) && (NC != uart_data[obj->index].sw_cts.pin)) //If flow control: writable if CTS low + UART done
isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->FSR & TXFIFO_FULL_MASK);
else
isWritable = (obj->uart->FSR & TXFIFO_FULL_MASK);
return isWritable;
}
}
void serial_clear(serial_t *obj) {
obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
| 1 << 1 // rx FIFO reset
| 1 << 2; // tx FIFO reset
}
void serial_pinout_tx(PinName tx) {
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj) {
obj->uart->LCR |= (1 << 6);
}
void serial_break_clear(serial_t *obj) {
obj->uart->LCR &= ~(1 << 6);
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
// Only UART1 has hardware flow control on RDA5991H
MBED_ASSERT((rxflow != UART0_RX) && (txflow != UART0_TX));
RDA_UART_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)RDA_UART1 ? RDA_UART1 : NULL;
int index = obj->index;
// First, disable flow control completely
uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC;
serial_flow_irq_set(obj, 0);
if (FlowControlNone == type) {
RDA_GPIO->IFCTRL &= ~(0x01UL << 2); //disable flow control
return;
}
// Check type(s) of flow control to use
UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS);
UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS);
if ((UART_1 == uart_cts) && (NULL != uart1))
{
pinmap_pinout(txflow, PinMap_UART_CTS);
gpio_init_in(&uart_data[index].sw_cts, txflow);
}
if((UART_1 == uart_rts) && (NULL != uart1))
{
pinmap_pinout(rxflow, PinMap_UART_RTS);
gpio_init_out(&uart_data[index].sw_rts, rxflow);
serial_flow_irq_set(obj, 1);
}
uart1->MCR = uart1->MCR | AFCE_MASK; //enable auto flow control, in this case we don't have to read and write sw_cts & sw_rts
uart1->FRR = (0x3EUL << 0) | (0x3EUL << 9); //rts/cts fifo trigger
RDA_GPIO->IFCTRL |= 0x01UL << 2; //enable flow control
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if DEVICE_SPI
#include "mbed_assert.h"
#include <math.h>
#include "spi_api.h"
#include "rda_ccfg_api.h"
#include "cmsis.h"
#include "pinmap.h"
/*------------- Wlan Monitor (WLANMON) ---------------------------------------*/
typedef struct
{
__IO uint32_t PHYSEL_3_0; /* 0x00 : PHY select register 0 - 3 */
} RDA_WLANMON_TypeDef;
/*
* Macros
*/
#define RDA_MON ((RDA_WLANMON_TypeDef *)RDA_MON_BASE)
#define ENABLE_RDA_SPI_MODE 0
#define SPI_CLKGATE_REG (RDA_SCU->CLKGATE2)
#define SPI_MODESEL_REG (RDA_GPIO->CTRL)
#define SPI_PINSEL_REG0 (RDA_GPIO->MEMCFG)
#define SPI_PINSEL_REG1 (RDA_MON->PHYSEL_3_0)
#define SPI_PINSEL_REG2 (RDA_EXIF->MISCCFG)
/*
* Global Variables
*/
static const PinMap PinMap_SPI_SCLK[] = {
{PB_4, SPI_0, 4},
{PD_0, SPI_0, 1},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{PB_6, SPI_0, 3},
{PC_0, SPI_0, 6},
{PD_2, SPI_0, 1},
{PB_3, SPI_0, 2},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{PB_7, SPI_0, 3},
{PC_1, SPI_0, 6},
{PD_3, SPI_0, 1},
{PB_8, SPI_0, 3},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{PD_1, SPI_0, 1},
{PB_5, SPI_0, 4},
{PA_0, SPI_0, 3},
{PA_1, SPI_0, 3},
{NC , NC , 0}
};
/*
* Inline Functions
*/
static inline int spi_pin_cs_num(PinName ssel);
static inline void spi_write(spi_t *obj, int value);
static inline int spi_read(spi_t *obj);
/*
* Functions
*/
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
{
uint32_t reg_val;
/* Determine the SPI to use */
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (RDA_SPI_TypeDef*)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->spi != NC);
/* Enable power and clocking */
SPI_CLKGATE_REG |= (0x01UL << 18);
/* Select 4-wire SPI mode */
SPI_MODESEL_REG &= ~(0x01UL << 14);
/* Set Config Reg */
reg_val = obj->spi->CFG;
#if ENABLE_RDA_SPI_MODE
/* RDA SPI mode */
reg_val |= (0x01UL << 2);
#else /* ENABLE_RDA_SPI_MODE */
/* Normal SPI mode */
reg_val &= ~(0x01UL << 2);
/* Set read flag */
reg_val |= (0x01UL << 3);
#endif /* ENABLE_RDA_SPI_MODE */
/* Set core cfg for mosi, miso */
if(PB_6 == mosi) {
rda_ccfg_gp(6U, 0x01U);
}
if(PB_7 == miso) {
rda_ccfg_gp(7U, 0x01U);
}
/* Config gpio/wlan_mon regs */
if(PB_3 == mosi) {
SPI_MODESEL_REG &= ~(0x0FUL);
SPI_PINSEL_REG1 &= ~(0x3FUL << 24);
SPI_PINSEL_REG2 &= ~(0x0FUL << 12);
SPI_MODESEL_REG |= (0x0BUL);
SPI_PINSEL_REG1 |= (0x02UL << 24);
SPI_PINSEL_REG2 |= (0x01UL << 12);
}
if(PB_8 == miso) {
SPI_PINSEL_REG0 &= ~(0x01UL << 11);
}
/* Pin out the SPI pins */
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
int cs_num = spi_pin_cs_num(ssel);
reg_val &= ~(0x03UL << 23);
reg_val |= (((uint32_t)cs_num & 0x03UL) << 23);
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
obj->spi->CFG = reg_val;
}
void spi_free(spi_t *obj)
{
/* Disable SPI clock gating */
SPI_CLKGATE_REG &= ~(0x01UL << 18);
}
void spi_format(spi_t *obj, int bits, int mode, int slave)
{
uint32_t polarity = (mode & 0x2) ? (0x01UL) : (0x00UL);
uint32_t reg_val;
#if ENABLE_RDA_SPI_MODE
MBED_ASSERT(((bits >= 4) && (bits <= 64)) && (mode >= 0 && mode <= 3));
#else /* ENABLE_RDA_SPI_MODE */
MBED_ASSERT(((bits >= 4) && (bits <= 32)) && (mode >= 0 && mode <= 3));
#endif /* ENABLE_RDA_SPI_MODE */
/* Set number of frame bits and clock phase */
reg_val = obj->spi->CFG & ~(0x7FUL << 16) & ~(0x01UL << 1);
obj->spi->CFG = reg_val | ((uint32_t)bits << 16) | (polarity << 1);
#if ENABLE_RDA_SPI_MODE
/* Set bit offset value */
obj->bit_ofst[0] = 0;
obj->bit_ofst[1] = 0;
if(2 > (bits >> 5)) {
obj->bit_ofst[bits >> 5] = (uint8_t)(32 - (bits & 0x1F));
}
#else /* ENABLE_RDA_SPI_MODE */
obj->bit_ofst[0] = (uint8_t)(32 - bits);
#endif /* ENABLE_RDA_SPI_MODE */
}
void spi_frequency(spi_t *obj, int hz)
{
uint32_t clk_rate = ((AHBBusClock / (uint32_t)hz) >> 2) - 1U;
uint32_t reg_val;
/* Check for valid frequency */
MBED_ASSERT(clk_rate <= 0x3FUL);
/* Set clk rate field */
reg_val = obj->spi->CFG & ~(0x3FUL << 4);
obj->spi->CFG = reg_val | ((clk_rate & 0x3FUL) << 4);
}
int spi_master_write(spi_t *obj, int value)
{
spi_write(obj, value);
return spi_read(obj);
}
int spi_busy(spi_t *obj)
{
return (obj->spi->CFG & (0x01UL << 31)) ? (1) : (0);
}
static inline int spi_pin_cs_num(PinName ssel)
{
int idx = 0;
while(PinMap_SPI_SSEL[idx].pin != NC) {
if(PinMap_SPI_SSEL[idx].pin == ssel)
return idx;
idx++;
}
return (int)NC;
}
static inline void spi_write(spi_t *obj, int value)
{
#if ENABLE_RDA_SPI_MODE
/* Write data register */
if(obj->bit_ofst[0] != 0) {
obj->spi->D1CMD = (uint32_t)value << obj->bit_ofst[0];
} else {
obj->spi->D1CMD = (uint32_t)value;
obj->spi->D0CMD = (uint32_t)value << obj->bit_ofst[1];
}
/* Set write bit & start bit */
obj->spi->CFG = (obj->spi->CFG & ~(0x01UL << 3)) | 0x01UL;
#else /* ENABLE_RDA_SPI_MODE */
/* Write data reg */
if(obj->bit_ofst[0] != 0) {
obj->spi->D1CMD = ((uint32_t)value << obj->bit_ofst[0]) | (0xFFFFFFFFUL >> (32 - obj->bit_ofst[0]));
} else {
obj->spi->D1CMD = (uint32_t)value;
obj->spi->D0CMD = 0xFFFFFFFFUL;
}
/* Set start bit */
obj->spi->CFG |= 0x01UL;
#endif /* ENABLE_RDA_SPI_MODE */
while(spi_busy(obj));
}
static inline int spi_read(spi_t *obj)
{
uint32_t ret_val;
#if ENABLE_RDA_SPI_MODE
/* Set read bit & start bit */
obj->spi->CFG |= ((0x01UL << 3) | 0x01UL);
while (spi_busy(obj));
/* Read data register */
if(obj->bit_ofst[0] != 0) {
ret_val = obj->spi->D0CMD & ((0x01UL << (32UL - obj->bit_ofst[0])) - 1UL);
} else {
ret_val = obj->spi->D0CMD;
ret_val = obj->spi->D1CMD & ((0x01UL << (32UL - obj->bit_ofst[1])) - 1UL);
}
#else /* ENABLE_RDA_SPI_MODE */
/* Read data register */
ret_val = obj->spi->D0CMD & ((0x01UL << (32UL - obj->bit_ofst[0])) - 1UL);
#endif /* ENABLE_RDA_SPI_MODE */
return (int)ret_val;
}
#endif

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Living_SDK/platform/mcu/rda5981x/feature/sysdata/rda5981_sys_data.c Normal file
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#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "rda5981_sys_data.h"
#include "rda_def.h"
#include <hal/soc/flash.h>
#include "rda_flash.h"
static r_u32 sys_data_location = 0;
/*
* return 0:ok, else:error.
*/
rda5981_sys_data_t rda5981_sys_data;
r_u8 read_flag = 0;
r_s32 rda5981_write_sys_data(r_u8 *data, r_u16 len, r_u32 flag)
{
//WLAND_DBG(INFO, "Enter, flag:0x%x\r\n", flag);
if (!read_flag) {
if(0 == rda5981_read_flash(sys_data_location,
(char *)(&rda5981_sys_data), sizeof(rda5981_sys_data)))
read_flag = 1;
else
return -1;
}
if ((rda5981_sys_data.flag & RDA5981_SYS_DATA_FLAG_UNINITIALIZED) ||
strcmp((const char *)(rda5981_sys_data.rda5981_flag), RDA5981_FLAG_FLAG)) {
memset(&rda5981_sys_data, 0xff, sizeof(rda5981_sys_data));
rda5981_sys_data.flag = flag;
strcpy((char *)(rda5981_sys_data.rda5981_flag), RDA5981_FLAG_FLAG);
}
rda5981_sys_data.flag |= flag;
switch (flag) {
case RDA5981_SYS_DATA_FLAG_STA:
memcpy(&rda5981_sys_data.sta_data, data,
min(sizeof(rda5981_sys_data.sta_data), len));
break;
case RDA5981_SYS_DATA_FLAG_MAC:
memcpy(rda5981_sys_data.mac_addr, data,
min(sizeof(rda5981_sys_data.mac_addr), len));
break;
case RDA5981_SYS_DATA_FLAG_PMK:
memcpy(rda5981_sys_data.pmk, data,
min(sizeof(rda5981_sys_data.pmk), len));
break;
case RDA5981_SYS_DATA_FLAG_IP:
memcpy(rda5981_sys_data.ip, data,
min(RDA5981_SYS_DATA_IP_LENGTH, len));
break;
case RDA5981_SYS_DATA_FLAG_PARTER_DATA_LEN:
memcpy(&rda5981_sys_data.parter_data_len, data,
min(sizeof(rda5981_sys_data.parter_data_len), len));
break;
case RDA5981_SYS_DATA_FLAG_TX_POWER:
memcpy(&rda5981_sys_data.tx_power, data,
min(sizeof(rda5981_sys_data.tx_power), len));
break;
case RDA5981_SYS_DATA_FLAG_XTAL_CAL:
memcpy(&rda5981_sys_data.xtal_cal, data,
min(sizeof(rda5981_sys_data.xtal_cal), len));
break;
case RDA5981_SYS_DATA_FLAG_TX_POWER_RF:
memcpy(&rda5981_sys_data.tx_power_rf, data,
min(sizeof(rda5981_sys_data.tx_power_rf), len));
break;
case RDA5981_SYS_DATA_FLAG_TX_POWER_PHY_GN:
memcpy(&rda5981_sys_data.tx_power_phy_gn, data,
min(sizeof(rda5981_sys_data.tx_power_phy_gn), len));
break;
case RDA5981_SYS_DATA_FLAG_TX_POWER_PHY_B:
memcpy(&rda5981_sys_data.tx_power_phy_b, data,
min(sizeof(rda5981_sys_data.tx_power_phy_b), len));
break;
case RDA5981_SYS_DATA_FLAG_AP:
memcpy(&rda5981_sys_data.ap_data, data,
min(sizeof(rda5981_sys_data.ap_data), len));
break;
case RDA5981_SYS_DATA_FLAG_APNET:
memcpy(&rda5981_sys_data.ap_net_data, data,
min(sizeof(rda5981_sys_data.ap_net_data), len));
break;
case RDA5981_SYS_DATA_FLAG_DHCP:
memcpy(&rda5981_sys_data.dhcp, data,
min(sizeof(rda5981_sys_data.dhcp), len));
break;
case RDA5981_SYS_DATA_FLAG_UART:
memcpy(&rda5981_sys_data.uart, data,
min(sizeof(rda5981_sys_data.uart), len));
break;
case RDA5981_SYS_DATA_FLAG_RF:
memcpy(&rda5981_sys_data.rf, data,
min(sizeof(rda5981_sys_data.rf), len));
break;
case RDA5981_SYS_DATA_FLAG_RF_CHANNELS:
memcpy(&rda5981_sys_data.rf_channels, data,
min(sizeof(rda5981_sys_data.rf_channels), len));
break;
case RDA5981_SYS_DATA_FLAG_PHY:
memcpy(&rda5981_sys_data.phy, data,
min(sizeof(rda5981_sys_data.phy), len));
break;
case RDA5981_SYS_DATA_FLAG_PHY_CHANNELS:
memcpy(&rda5981_sys_data.phy_channels, data,
min(sizeof(rda5981_sys_data.phy_channels), len));
break;
case RDA5981_SYS_DATA_FLAG_TX_POWER_OFFSET:
memcpy(&rda5981_sys_data.tp_offset, data,
min(sizeof(rda5981_sys_data.tp_offset), len));
break;
default:
return -1;
}
rda5981_erase_flash(sys_data_location, sizeof(rda5981_sys_data));
return rda5981_write_flash(sys_data_location,
(char *)(&rda5981_sys_data), sizeof(rda5981_sys_data));
}
#if 0
/*
* return 0:ok, else:error.
*/
r_s32 rda5981_erase_sys_data(r_u32 flag)
{
//RDA5981_SYS_data rda5981_sys_data;
//WLAND_DBG(INFO, "Enter, flag:0x%x\r\n", flag);
if (!read_flag) {
read_flag = 1;
rda5981_read_flash(sys_data_location,
(char *)(&rda5981_sys_data), sizeof(rda5981_sys_data));
}
if (rda5981_sys_data.flag & RDA5981_SYS_DATA_FLAG_UNINITIALIZED)//flash init is 0xffffffff
return -1;
if ((rda5981_sys_data.flag & flag) == 0)
return 0;
rda5981_sys_data.flag &= (~flag);
if (rda5981_sys_data.flag == 0)
rda5981_sys_data.flag = RDA5981_SYS_DATA_FLAG_UNINITIALIZED;
if (flag & RDA5981_SYS_DATA_FLAG_STA) {
memset(&rda5981_sys_data.sta_data, 0xff,
sizeof(rda5981_sys_data.sta_data));
}
if (flag & RDA5981_SYS_DATA_FLAG_MAC) {
memset(rda5981_sys_data.mac_addr, 0xff,
sizeof(rda5981_sys_data.mac_addr));
}
if (flag & RDA5981_SYS_DATA_FLAG_PMK) {
memset(rda5981_sys_data.pmk, 0xff,
sizeof(rda5981_sys_data.pmk));
}
if (flag & RDA5981_SYS_DATA_FLAG_IP) {
memset(rda5981_sys_data.ip, 0xff,
RDA5981_SYS_DATA_IP_LENGTH);
}
if (flag & RDA5981_SYS_DATA_FLAG_PARTER_DATA_LEN) {
memset(&rda5981_sys_data.parter_data_len, 0xff,
sizeof(rda5981_sys_data.parter_data_len));
}
if (flag & RDA5981_SYS_DATA_FLAG_TX_POWER) {
memset(&rda5981_sys_data.tx_power, 0xff,
sizeof(rda5981_sys_data.tx_power));
}
if (flag & RDA5981_SYS_DATA_FLAG_XTAL_CAL) {
memset(&rda5981_sys_data.xtal_cal, 0xff,
sizeof(rda5981_sys_data.xtal_cal));
}
if (flag & RDA5981_SYS_DATA_FLAG_TX_POWER_RF) {
memset(&rda5981_sys_data.tx_power_rf, 0xff,
sizeof(rda5981_sys_data.tx_power_rf));
}
if (flag & RDA5981_SYS_DATA_FLAG_TX_POWER_PHY_GN) {
memset(&rda5981_sys_data.tx_power_phy_gn, 0xff,
sizeof(rda5981_sys_data.tx_power_phy_gn));
}
if (flag & RDA5981_SYS_DATA_FLAG_TX_POWER_PHY_B) {
memset(&rda5981_sys_data.tx_power_phy_b, 0xff,
sizeof(rda5981_sys_data.tx_power_phy_b));
}
if (flag & RDA5981_SYS_DATA_FLAG_AP) {
memset(&rda5981_sys_data.ap_data, 0xff,
sizeof(rda5981_sys_data.ap_data));
}
if (flag & RDA5981_SYS_DATA_FLAG_APNET) {
memset(&rda5981_sys_data.ap_net_data, 0xff,
sizeof(rda5981_sys_data.ap_net_data));
}
if (flag & RDA5981_SYS_DATA_FLAG_DHCP) {
memset(&rda5981_sys_data.dhcp, 0xff,
sizeof(rda5981_sys_data.dhcp));
}
if (flag & RDA5981_SYS_DATA_FLAG_UART) {
memset(&rda5981_sys_data.uart, 0xff,
sizeof(rda5981_sys_data.uart));
}
if (flag & RDA5981_SYS_DATA_FLAG_RF) {
memset(&rda5981_sys_data.rf, 0xff,
sizeof(rda5981_sys_data.rf));
}
if (flag & RDA5981_SYS_DATA_FLAG_RF_CHANNELS) {
memset(&rda5981_sys_data.rf_channels, 0xff,
sizeof(rda5981_sys_data.rf_channels));
}
if (flag & RDA5981_SYS_DATA_FLAG_PHY) {
memset(&rda5981_sys_data.phy, 0xff,
sizeof(rda5981_sys_data.phy));
}
if (flag & RDA5981_SYS_DATA_FLAG_PHY_CHANNELS) {
memset(&rda5981_sys_data.phy_channels, 0xff,
sizeof(rda5981_sys_data.phy_channels));
}
if (flag & RDA5981_SYS_DATA_FLAG_TX_POWER_OFFSET) {
memset(&rda5981_sys_data.tp_offset, 0xff,
sizeof(rda5981_sys_data.tp_offset));
}
rda5981_erase_flash(sys_data_location, sizeof(rda5981_sys_data));
return rda5981_write_flash(sys_data_location,
(char *)(&rda5981_sys_data), sizeof(rda5981_sys_data));
}
#endif
/*
* return 0:ok, else:error.
*/
r_s32 rda5981_read_sys_data(r_u8 *data, r_u16 len, r_u32 flag)
{
//RDA5981_SYS_data rda5981_sys_data;
//WLAND_DBG(INFO, "Enter, flag:0x%x\r\n", flag);
if (!read_flag) {
read_flag = 1;
rda5981_read_flash(sys_data_location,
(char *)(&rda5981_sys_data), sizeof(rda5981_sys_data));
}
if (rda5981_sys_data.flag & RDA5981_SYS_DATA_FLAG_UNINITIALIZED)//flash init is 0xffffffff
return -1;
if (strcmp((const char *)(rda5981_sys_data.rda5981_flag), RDA5981_FLAG_FLAG))
return -2;
if ((rda5981_sys_data.flag & flag) == 0)
return -3;
switch (flag) {
case RDA5981_SYS_DATA_FLAG_STA:
memcpy(data, &rda5981_sys_data.sta_data,
min(sizeof(rda5981_sys_data.sta_data), len));
break;
case RDA5981_SYS_DATA_FLAG_MAC:
memcpy(data, rda5981_sys_data.mac_addr,
min(sizeof(rda5981_sys_data.mac_addr), len));
break;
case RDA5981_SYS_DATA_FLAG_PMK:
memcpy(data, rda5981_sys_data.pmk,
min(sizeof(rda5981_sys_data.pmk), len));
break;
case RDA5981_SYS_DATA_FLAG_IP:
memcpy(data, rda5981_sys_data.ip,
min(RDA5981_SYS_DATA_IP_LENGTH, len));
break;
case RDA5981_SYS_DATA_FLAG_PARTER_DATA_LEN:
memcpy(data, &rda5981_sys_data.parter_data_len,
min(sizeof(rda5981_sys_data.parter_data_len), len));
break;
case RDA5981_SYS_DATA_FLAG_TX_POWER:
memcpy(data, &rda5981_sys_data.tx_power,
min(sizeof(rda5981_sys_data.tx_power), len));
break;
case RDA5981_SYS_DATA_FLAG_XTAL_CAL:
memcpy(data, &rda5981_sys_data.xtal_cal,
min(sizeof(rda5981_sys_data.xtal_cal), len));
break;
case RDA5981_SYS_DATA_FLAG_TX_POWER_RF:
memcpy(data, &rda5981_sys_data.tx_power_rf,
min(sizeof(rda5981_sys_data.tx_power_rf), len));
break;
case RDA5981_SYS_DATA_FLAG_TX_POWER_PHY_GN:
memcpy(data, &rda5981_sys_data.tx_power_phy_gn,
min(sizeof(rda5981_sys_data.tx_power_phy_gn), len));
break;
case RDA5981_SYS_DATA_FLAG_TX_POWER_PHY_B:
memcpy(data, &rda5981_sys_data.tx_power_phy_b,
min(sizeof(rda5981_sys_data.tx_power_phy_b), len));
break;
case RDA5981_SYS_DATA_FLAG_AP:
memcpy(data, &rda5981_sys_data.ap_data,
min(sizeof(rda5981_sys_data.ap_data), len));
break;
case RDA5981_SYS_DATA_FLAG_APNET:
memcpy(data, &rda5981_sys_data.ap_net_data,
min(sizeof(rda5981_sys_data.ap_net_data), len));
break;
case RDA5981_SYS_DATA_FLAG_DHCP:
memcpy(data, &rda5981_sys_data.dhcp,
min(sizeof(rda5981_sys_data.dhcp), len));
break;
case RDA5981_SYS_DATA_FLAG_UART:
memcpy(data, &rda5981_sys_data.uart,
min(sizeof(rda5981_sys_data.uart), len));
break;
case RDA5981_SYS_DATA_FLAG_RF:
memcpy(data, &rda5981_sys_data.rf,
min(sizeof(rda5981_sys_data.rf), len));
break;
case RDA5981_SYS_DATA_FLAG_RF_CHANNELS:
memcpy(data, &rda5981_sys_data.rf_channels,
min(sizeof(rda5981_sys_data.rf_channels), len));
break;
case RDA5981_SYS_DATA_FLAG_PHY:
memcpy(data, &rda5981_sys_data.phy,
min(sizeof(rda5981_sys_data.phy), len));
break;
case RDA5981_SYS_DATA_FLAG_PHY_CHANNELS:
memcpy(data, &rda5981_sys_data.phy_channels,
min(sizeof(rda5981_sys_data.phy_channels), len));
break;
case RDA5981_SYS_DATA_FLAG_TX_POWER_OFFSET:
memcpy(data, &rda5981_sys_data.tp_offset,
min(sizeof(rda5981_sys_data.tp_offset), len));
break;
default:
return -1;
}
return 0;
}
/*
* return 0:ok, else:error.
*/
__WEAK r_s32 rda5981_flash_read_mac_addr(r_u8 *mac_addr)
{
r_s32 ret;
//WLAND_DBG(DEBUG, "Enter\r\n");
ret = rda5981_read_sys_data(mac_addr, 6, RDA5981_SYS_DATA_FLAG_MAC);
#if 0
if (ret)
WLAND_DBG(ERROR, "read mac addr from flash fail\r\n");
else
WLAND_DBG(INFO, "Done(ret:%d)"MACDBG"\r\n", ret, MAC2STRDBG(mac_addr));
#endif
return ret;
}
#if 1
/*
* return 0:ok, else:error.
*/
r_s32 rda5981_flash_write_mac_addr(r_u8 *mac_addr)
{
//WLAND_DBG(INFO, "Enter"MACDBG"\r\n", MAC2STRDBG(mac_addr));
return rda5981_write_sys_data(mac_addr, 6, RDA5981_SYS_DATA_FLAG_MAC);
}
#endif
r_s32 rda5981_init_sys_data()
{
//WLAND_DBG(INFO, "Enter set userdata addr: %x:%x:%x\r\n", sys_data_addr);
hal_partition_t pno = HAL_PARTITION_SYS_DATA;
hal_logic_partition_t *partition_info;
partition_info = hal_flash_get_info(pno);
if ((partition_info->partition_start_addr)&(SECTOR_SIZE-1))
return -1;
if ((partition_info->partition_start_addr) <= RDA5991H_PARTITION_TABLE_END_ADDR)
return -2;
if ((partition_info->partition_start_addr + partition_info->partition_length) > 0x18000000 + FLASH_SIZE)
return -3;
sys_data_location = partition_info->partition_start_addr;
return 0;
}
#if 0
r_s32 rda5981_reboot_to_addr(r_u32 firmware_info_addr, r_u32 reboot_addr)
{
int ret;
int retry = 0;
struct firmware_info info;
WLAND_DBG(INFO, "Enter:0x%x\n", reboot_addr);
rda5981_read_flash(firmware_info_addr, (char *)(&info), sizeof(info));
if (1 || info.magic == RDA5981_FIRMWARE_MAGIC) {
info.bootaddr = reboot_addr;
info.bootmagic = RDA5981_FIRMWARE_MAGIC;
write:
if ((retry++) > 5) {
WLAND_DBG(ERROR, "try %d time, fail\n", retry-1);
return -1;
}
ret = rda5981_erase_flash(firmware_info_addr, sizeof(info));
if (ret) {
WLAND_DBG(ERROR, "erase fail\n");
goto write;
}
ret = rda5981_write_flash(firmware_info_addr, (char *)(&info), sizeof(info));
if (ret) {
WLAND_DBG(ERROR, "write fail\n");
goto write;
}
rda_wdt_softreset();
return 0;
} else {
WLAND_DBG(ERROR, "firmware magic error:0x%x\n", info.magic);
return -1;
}
}
#endif
r_s32 rda5981_write_sys_data_regs(r_u8 *reg, r_u8 *value, r_u32 flag)
{
r_u16 reg16 = 0;
r_u32 reg32 = 0;
r_u8 idx = 0;
if (!read_flag) {
if(0 == rda5981_read_flash(sys_data_location,
(char *)(&rda5981_sys_data), sizeof(rda5981_sys_data)))
read_flag = 1;
else
return -1;
}
if ((rda5981_sys_data.flag & RDA5981_SYS_DATA_FLAG_UNINITIALIZED) ||
strcmp((const char *)(rda5981_sys_data.rda5981_flag), RDA5981_FLAG_FLAG)) {
memset(&rda5981_sys_data, 0xff, sizeof(rda5981_sys_data));
rda5981_sys_data.flag = flag;
strcpy((char *)(rda5981_sys_data.rda5981_flag), RDA5981_FLAG_FLAG);
}
rda5981_sys_data.flag |= flag;
switch (flag) {
case RDA5981_SYS_DATA_FLAG_RF:
if (rda5981_sys_data.rf.valid != 1) {
rda5981_sys_data.rf.valid = 1;
rda5981_sys_data.rf.flag = 0;
}
reg16 = *((r_u16 *)reg);
if (rda5981_sys_data.rf.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.rf.flag & BIT(idx)) &&
(rda5981_sys_data.rf.reg_val[idx][0] == reg16)) {
rda5981_sys_data.rf.reg_val[idx][1] = *((r_u16 *)value);
break;
} else {
continue;
}
}
if ((8 == idx) && (0xFF == rda5981_sys_data.rf.flag))
return -2;
}
if ((8 == idx) || (0 == rda5981_sys_data.rf.flag)) {
for (idx = 0; idx < 8; idx++) {
if (!(rda5981_sys_data.rf.flag & BIT(idx))) {
rda5981_sys_data.rf.reg_val[idx][0] = reg16;
rda5981_sys_data.rf.reg_val[idx][1] = *((r_u16 *)value);
rda5981_sys_data.rf.flag |= BIT(idx);
break;
} else {
continue;
}
}
}
break;
case RDA5981_SYS_DATA_FLAG_RF_CHANNELS:
if (rda5981_sys_data.rf_channels.valid != 1) {
rda5981_sys_data.rf_channels.valid = 1;
rda5981_sys_data.rf_channels.flag = 0;
}
reg16 = *((r_u16 *)reg);
if (rda5981_sys_data.rf_channels.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.rf_channels.flag & BIT(idx)) &&
(rda5981_sys_data.rf_channels.reg_val[idx][0] == reg16)) {
memcpy(&rda5981_sys_data.rf_channels.reg_val[idx][1], value, 14 * sizeof(r_u16));
break;
} else {
continue;
}
}
if ((8 == idx) && (0xFF == rda5981_sys_data.rf_channels.flag))
return -2;
}
if ((8 == idx) || (0 == rda5981_sys_data.rf_channels.flag)) {
for (idx = 0; idx < 8; idx++) {
if (!(rda5981_sys_data.rf_channels.flag & BIT(idx))) {
rda5981_sys_data.rf_channels.reg_val[idx][0] = reg16;
memcpy(&rda5981_sys_data.rf_channels.reg_val[idx][1], value, 14 * sizeof(r_u16));
rda5981_sys_data.rf_channels.flag |= BIT(idx);
break;
} else {
continue;
}
}
}
break;
case RDA5981_SYS_DATA_FLAG_PHY:
if (rda5981_sys_data.phy.valid != 1) {
rda5981_sys_data.phy.valid = 1;
rda5981_sys_data.phy.flag = 0;
}
reg32 = *((r_u32 *)reg);
if (rda5981_sys_data.phy.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.phy.flag & BIT(idx)) &&
(rda5981_sys_data.phy.reg_val[idx][0] == reg32)) {
rda5981_sys_data.phy.reg_val[idx][1] = *((r_u32 *)value);
break;
} else {
continue;
}
}
if ((8 == idx) && (0xFF == rda5981_sys_data.phy.flag))
return -2;
}
if ((8 == idx) || (0 == rda5981_sys_data.phy.flag)) {
for (idx = 0; idx < 8; idx++) {
if (!(rda5981_sys_data.phy.flag & BIT(idx))) {
rda5981_sys_data.phy.reg_val[idx][0] = reg32;
rda5981_sys_data.phy.reg_val[idx][1] = *((r_u32 *)value);
rda5981_sys_data.phy.flag |= BIT(idx);
break;
} else {
continue;
}
}
}
break;
case RDA5981_SYS_DATA_FLAG_PHY_CHANNELS:
if (rda5981_sys_data.phy_channels.valid != 1) {
rda5981_sys_data.phy_channels.valid = 1;
rda5981_sys_data.phy_channels.flag = 0;
}
reg32 = *((r_u32 *)reg);
if (rda5981_sys_data.phy_channels.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.phy_channels.flag & BIT(idx)) &&
(rda5981_sys_data.phy_channels.reg_val[idx][0] == reg32)) {
memcpy(&rda5981_sys_data.phy_channels.reg_val[idx][1], value, 14 * sizeof(r_u32));
break;
} else {
continue;
}
}
if ((8 == idx) && (0xFF == rda5981_sys_data.phy_channels.flag))
return -2;
}
if ((8 == idx) || (0 == rda5981_sys_data.phy_channels.flag)) {
for (idx = 0; idx < 8; idx++) {
if (!(rda5981_sys_data.phy_channels.flag & BIT(idx))) {
rda5981_sys_data.phy_channels.reg_val[idx][0] = reg32;
memcpy(&rda5981_sys_data.phy_channels.reg_val[idx][1], value, 14 * sizeof(r_u32));
rda5981_sys_data.phy_channels.flag |= BIT(idx);
break;
} else {
continue;
}
}
}
break;
default:
//WLAND_DBG(ERROR, "Unknown flag:0x%08x\n", flag);
return -3;
}
rda5981_erase_flash(sys_data_location, sizeof(rda5981_sys_data));
return rda5981_write_flash(sys_data_location,
(char *)(&rda5981_sys_data), sizeof(rda5981_sys_data));
}
r_s32 rda5981_erase_sys_data_regs(r_u8 *reg, r_u32 flag)
{
r_u16 reg16 = 0;
r_u32 reg32 = 0;
r_u8 idx = 0;
if (!read_flag) {
if(0 == rda5981_read_flash(sys_data_location,
(char *)(&rda5981_sys_data), sizeof(rda5981_sys_data)))
read_flag = 1;
else
return -1;
}
if (rda5981_sys_data.flag & RDA5981_SYS_DATA_FLAG_UNINITIALIZED)//flash init is 0xffffffff
return -1;
if ((rda5981_sys_data.flag & flag) == 0)
return 0;
switch (flag) {
case RDA5981_SYS_DATA_FLAG_RF:
if (rda5981_sys_data.rf.valid != 1) {
return 0;
}
reg16 = *((r_u16 *)reg);
if (rda5981_sys_data.rf.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.rf.flag & BIT(idx)) &&
(rda5981_sys_data.rf.reg_val[idx][0] == reg16)) {
memset(&rda5981_sys_data.rf.reg_val[idx][0], 0xFF, 2 * sizeof(r_u16));
rda5981_sys_data.rf.flag &= ~BIT(idx);
break;
} else {
continue;
}
}
}
if (0 == rda5981_sys_data.rf.flag) {
rda5981_sys_data.rf.valid = 0xFFFFFFFF;
rda5981_sys_data.rf.flag = 0xFFFFFFFF;
rda5981_sys_data.flag &= (~flag);
}
break;
case RDA5981_SYS_DATA_FLAG_RF_CHANNELS:
if (rda5981_sys_data.rf_channels.valid != 1) {
return 0;
}
reg16 = *((r_u16 *)reg);
if (rda5981_sys_data.rf_channels.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.rf_channels.flag & BIT(idx)) &&
(rda5981_sys_data.rf_channels.reg_val[idx][0] == reg16)) {
memset(&rda5981_sys_data.rf_channels.reg_val[idx][0], 0xFF, 15 * sizeof(r_u16));
rda5981_sys_data.rf_channels.flag &= ~BIT(idx);
break;
} else {
continue;
}
}
}
if (0 == rda5981_sys_data.rf_channels.flag) {
rda5981_sys_data.rf_channels.valid = 0xFFFFFFFF;
rda5981_sys_data.rf_channels.flag = 0xFFFFFFFF;
rda5981_sys_data.flag &= (~flag);
}
break;
case RDA5981_SYS_DATA_FLAG_PHY:
if (rda5981_sys_data.phy.valid != 1) {
return 0;
}
reg32 = *((r_u32 *)reg);
if (rda5981_sys_data.phy.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.phy.flag & BIT(idx)) &&
(rda5981_sys_data.phy.reg_val[idx][0] == reg32)) {
memset(&rda5981_sys_data.phy.reg_val[idx][0], 0xFF, 2 * sizeof(r_u32));
rda5981_sys_data.phy.flag &= ~BIT(idx);
break;
} else {
continue;
}
}
}
if (0 == rda5981_sys_data.phy.flag) {
rda5981_sys_data.phy.valid = 0xFFFFFFFF;
rda5981_sys_data.phy.flag = 0xFFFFFFFF;
rda5981_sys_data.flag &= (~flag);
}
break;
case RDA5981_SYS_DATA_FLAG_PHY_CHANNELS:
if (rda5981_sys_data.phy_channels.valid != 1) {
return 0;
}
reg32 = *((r_u32 *)reg);
if (rda5981_sys_data.phy_channels.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.phy_channels.flag & BIT(idx)) &&
(rda5981_sys_data.phy_channels.reg_val[idx][0] == reg32)) {
memset(&rda5981_sys_data.phy_channels.reg_val[idx][0], 0xFF, 15 * sizeof(r_u32));
rda5981_sys_data.phy_channels.flag &= ~BIT(idx);
break;
} else {
continue;
}
}
}
if (0 == rda5981_sys_data.phy_channels.flag) {
rda5981_sys_data.phy_channels.valid = 0xFFFFFFFF;
rda5981_sys_data.phy_channels.flag = 0xFFFFFFFF;
rda5981_sys_data.flag &= (~flag);
}
break;
default:
//WLAND_DBG(ERROR, "Unknown flag:0x%08x\n", flag);
return -3;
}
rda5981_erase_flash(sys_data_location, sizeof(rda5981_sys_data));
return rda5981_write_flash(sys_data_location,
(char *)(&rda5981_sys_data), sizeof(rda5981_sys_data));
}
r_s32 rda5981_read_sys_data_regs(r_u8 *reg, r_u8 *value, r_u32 flag)
{
r_u16 reg16 = 0;
r_u32 reg32 = 0;
r_u8 idx = 0;
if (!read_flag) {
if(0 == rda5981_read_flash(sys_data_location,
(char *)(&rda5981_sys_data), sizeof(rda5981_sys_data)))
read_flag = 1;
else
return -1;
}
if (rda5981_sys_data.flag & RDA5981_SYS_DATA_FLAG_UNINITIALIZED)//flash init is 0xffffffff
return -1;
if (strcmp((const char *)(rda5981_sys_data.rda5981_flag), RDA5981_FLAG_FLAG))
return -2;
if ((rda5981_sys_data.flag & flag) == 0)
return -3;
switch (flag) {
case RDA5981_SYS_DATA_FLAG_RF:
if (rda5981_sys_data.rf.valid != 1) {
return -4;
}
reg16 = *((r_u16 *)reg);
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.rf.flag & BIT(idx)) &&
(rda5981_sys_data.rf.reg_val[idx][0] == reg16)) {
memcpy(value, &rda5981_sys_data.rf.reg_val[idx][1], sizeof(r_u16));
break;
} else {
continue;
}
}
if (8 == idx)
return -4;
break;
case RDA5981_SYS_DATA_FLAG_RF_CHANNELS:
if (rda5981_sys_data.rf_channels.valid != 1) {
return -4;
}
reg16 = *((r_u16 *)reg);
if (rda5981_sys_data.rf_channels.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.rf_channels.flag & BIT(idx)) &&
(rda5981_sys_data.rf_channels.reg_val[idx][0] == reg16)) {
memcpy(value, &rda5981_sys_data.rf_channels.reg_val[idx][1], 14 * sizeof(r_u16));
break;
} else {
continue;
}
}
}
if (8 == idx)
return -4;
break;
case RDA5981_SYS_DATA_FLAG_PHY:
if (rda5981_sys_data.phy.valid != 1) {
return -4;
}
reg32 = *((r_u32 *)reg);
if (rda5981_sys_data.phy.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.phy.flag & BIT(idx)) &&
(rda5981_sys_data.phy.reg_val[idx][0] == reg32)) {
memcpy(value, &rda5981_sys_data.phy.reg_val[idx][1], sizeof(r_u32));
break;
} else {
continue;
}
}
}
if (8 == idx)
return -4;
break;
case RDA5981_SYS_DATA_FLAG_PHY_CHANNELS:
if (rda5981_sys_data.phy_channels.valid != 1) {
return -4;
}
reg32 = *((r_u32 *)reg);
if (rda5981_sys_data.phy_channels.flag != 0) {
for (idx = 0; idx < 8; idx++) {
if ((rda5981_sys_data.phy_channels.flag & BIT(idx)) &&
(rda5981_sys_data.phy_channels.reg_val[idx][0] == reg32)) {
memcpy(value, &rda5981_sys_data.phy_channels.reg_val[idx][1], 14 * sizeof(r_u32));
break;
} else {
continue;
}
}
}
if (8 == idx)
return -4;
break;
default:
//WLAND_DBG(ERROR, "Unknown flag:0x%08x\n", flag);
return -3;
}
return 0;
}
#if 0
int rda5981_flash_get_mid(u8 *mid)
{
*mid = 0xC8;
return 0;
}
int rda5981_flash_get_did(u8 *did)
{
*did = 0x13;
return 0;
}
int rda5981_flash_get_jdid(u16 *jdid)
{
*jdid = 0x4014;
return 0;
}
int rda5981_read_default_config(char *buf, u32 len, u32 flag)
{
int ret = 0;
u32 addr;
u32 addr_offset = 0;
char *temp_buf = NULL, *temp_buf_aligned;
switch (flag) {
case RDA5981_VBAT_CAL:
addr = 0x18000088;
break;
case RDA5981_GPADC0_CAL:
case RDA5981_GPADC1_CAL:
addr = 0x1800008C;
break;
case RDA5981_PRODUCT_ID:
addr = 0x18000084;
break;
case RDA5981_POWER_CLASS:
addr = 0x18000085;
break;
default:
WLAND_DBG(ERROR, "Unknown flag\n");
return -1;
}
addr_offset = addr % 4;
addr = (addr - addr_offset) & (flash_size -1);
if (((u32)buf % 4) || (addr_offset != 0)) {
temp_buf = (char *)malloc(addr_offset + len + 4);
if (temp_buf == NULL) {
ret = -1;
goto out;
}
if ((u32)temp_buf % 4)
temp_buf_aligned = temp_buf + (4 - (u32)temp_buf % 4);
else
temp_buf_aligned = temp_buf;
} else {
temp_buf_aligned = buf;
}
core_util_critical_section_enter();
spi_flash_flush_cache();
SPI_FLASH_READ_DATA_FOR_MBED((void *)addr, temp_buf_aligned, (len + addr_offset));
core_util_critical_section_exit();
if (temp_buf_aligned != buf)
memcpy(buf, temp_buf_aligned + addr_offset, len);
out:
if (temp_buf)
free(temp_buf);
return ret;
}
int rda5981_flash_read_vbat_cal(float *k, float *b)
{
int ret = 0;
u32 value = 0;
u32 x1 = 0;//y1 3.0f
u32 x2 = 0;//y2 4.2f
float k_tmp = 0;
float b_tmp = 0;
ret = rda5981_read_default_config((char *)&value, 4, RDA5981_VBAT_CAL);
if (ret < 0) {
WLAND_DBG(ERROR, "read vbat_cal form flash fail\n");
return -1;
}
if ((0 == (value & 0xFFFFFUL)) || (0xFFFFFUL == (value & 0xFFFFFUL))) {
WLAND_DBG(ERROR, "invalid vbat_cal:0x%08x\n", value);
return -1;
} else {
x1 = value & 0x3FFUL;
x2 = (value >> 10) & 0x3FFUL;
}
if (x1 == x2) {
return -1;
}
k_tmp = (4.2f - 3.0f) / (float)(x2 - x1);
b_tmp = 4.2f - k_tmp * x2;
*k = k_tmp;
*b = b_tmp;
return ret;
}
#endif
#if 0
int rda5981_flash_read_gpadc0_cal(float *k, float *b)
{
int ret = 0;
u32 value = 0;
u32 x1 = 0;//y1 0.2f
u32 x2 = 0;//y2 1.6f
float k_tmp = 0;
float b_tmp = 0;
ret = rda5981_read_default_config((char *)&value, 4, RDA5981_GPADC0_CAL);
if (ret < 0) {
WLAND_DBG(ERROR, "read vbat_cal form flash fail\n");
return -1;
}
if ((0 == (value & 0x3FFFFFFF)) || (0x3FFFFFFF == (value & 0x3FFFFFFF))) {
WLAND_DBG(ERROR, "invalid vbat_cal:0x%08x\n", value);
return -1;
} else {
x1 = value & 0x3FFUL;
x2 = (value >> 20) & 0x3FFUL;
}
if (x1 == x2) {
return -1;
}
k_tmp = (1.6f - 0.2f) / (float)(x2 - x1);
b_tmp = 1.6f - k_tmp * x2;
*k = k_tmp;
*b = b_tmp;
return ret;
}
#endif

169
Living_SDK/platform/mcu/rda5981x/feature/sysdata/rda5981_sys_data.h Normal file
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#ifndef _RDA5981_SYS_DATA_H_
#define _RDA5981_SYS_DATA_H_
#include "rda_def.h"
/** This struct contains all smartconfig mbed flash parameter. */
typedef struct
{
r_u8 ssid[36];
r_u8 key[64];
} wland_sta_data_t;
/** This struct contains ap data, include ssid key and channel. */
typedef struct
{
r_u8 channel;
r_u8 ssid[35];
r_u8 key[64];
} wland_ap_data_t;
/** This struct contains ap net data. */
typedef struct
{
r_u32 ip;
r_u32 msk;
r_u32 gw;
r_u32 dhcps;
r_u32 dhcpe;
} wland_ap_net_data_t;
typedef struct
{
r_u32 fixip;
r_u32 ip;
r_u32 msk;
r_u32 gw;
} wland_dhcp_t;
/** This struct contains tx power parameter. */
typedef struct
{
r_u8 b[14];
r_u8 g[14];
r_u8 n[14];
r_u8 sum;
r_u8 padding1;//alignment
} wland_tx_power_t;
/*
*function: store reg and corresponding value related to test mode
*@valid: 1 means data is valid
*@flag: if biti(i=0~7) == 1, it means reg_val[i] is in use
*@reg_val: store reg and value, reg_val[i][0] is reg, reg_val[i][1] ~ reg_val[i][14] is value
*/
typedef struct {
r_u32 valid;
r_u32 flag;
r_u16 reg_val[8][2];
} wland_rf_t;
typedef struct {
r_u32 valid;
r_u32 flag;
r_u16 reg_val[8][15];
} wland_rf_channels_t;
typedef struct {
r_u32 valid;
r_u32 flag;
r_u32 reg_val[8][2];
} wland_phy_t;
typedef struct {
r_u32 valid;
r_u32 flag;
r_u32 reg_val[8][15];
} wland_phy_channels_t;
/* if you add or delete any macros below, modify RDA5981_SYS_DATA_FLAG_UNINITIALIZED at the same time */
#define RDA5981_SYS_DATA_FLAG_MAC BIT0
#define RDA5981_SYS_DATA_FLAG_STA BIT1
#define RDA5981_SYS_DATA_FLAG_PMK BIT2
#define RDA5981_SYS_DATA_FLAG_IP BIT3
#define RDA5981_SYS_DATA_FLAG_PARTER_DATA_LEN BIT4
#define RDA5981_SYS_DATA_FLAG_TX_POWER BIT5
#define RDA5981_SYS_DATA_FLAG_XTAL_CAL BIT6
#define RDA5981_SYS_DATA_FLAG_TX_POWER_RF BIT7
#define RDA5981_SYS_DATA_FLAG_TX_POWER_PHY_GN BIT8
#define RDA5981_SYS_DATA_FLAG_TX_POWER_PHY_B BIT9
#define RDA5981_SYS_DATA_FLAG_AP BIT10
#define RDA5981_SYS_DATA_FLAG_APNET BIT11
#define RDA5981_SYS_DATA_FLAG_DHCP BIT12
#define RDA5981_SYS_DATA_FLAG_UART BIT13
#define RDA5981_SYS_DATA_FLAG_RF BIT14
#define RDA5981_SYS_DATA_FLAG_RF_CHANNELS BIT15
#define RDA5981_SYS_DATA_FLAG_PHY BIT16
#define RDA5981_SYS_DATA_FLAG_PHY_CHANNELS BIT17
#define RDA5981_SYS_DATA_FLAG_TX_POWER_OFFSET BIT18
#define RDA5981_VBAT_CAL BIT0
#define RDA5981_GPADC0_CAL BIT1
#define RDA5981_GPADC1_CAL BIT2
#define RDA5981_PRODUCT_ID BIT3
#define RDA5981_POWER_CLASS BIT4
#define RDA5981_SYS_DATA_FLAG_UNINITIALIZED (0xFFFFFFFF & \
(~(RDA5981_SYS_DATA_FLAG_MAC | \
RDA5981_SYS_DATA_FLAG_STA | \
RDA5981_SYS_DATA_FLAG_PMK | \
RDA5981_SYS_DATA_FLAG_IP | \
RDA5981_SYS_DATA_FLAG_PARTER_DATA_LEN | \
RDA5981_SYS_DATA_FLAG_TX_POWER | \
RDA5981_SYS_DATA_FLAG_XTAL_CAL | \
RDA5981_SYS_DATA_FLAG_TX_POWER_RF | \
RDA5981_SYS_DATA_FLAG_TX_POWER_PHY_GN | \
RDA5981_SYS_DATA_FLAG_TX_POWER_PHY_B | \
RDA5981_SYS_DATA_FLAG_AP | \
RDA5981_SYS_DATA_FLAG_APNET | \
RDA5981_SYS_DATA_FLAG_DHCP | \
RDA5981_SYS_DATA_FLAG_UART | \
RDA5981_SYS_DATA_FLAG_RF | \
RDA5981_SYS_DATA_FLAG_RF_CHANNELS | \
RDA5981_SYS_DATA_FLAG_PHY | \
RDA5981_SYS_DATA_FLAG_PHY_CHANNELS | \
RDA5981_SYS_DATA_FLAG_TX_POWER_OFFSET)))
#define RDA5981_SYS_DATA_IP_LENGTH 8
#define RDA5981_FLAG_FLAG "RDA5981"
typedef struct
{
r_u32 flag;
r_u8 rda5981_flag[8];
r_u8 mac_addr[6];
r_u8 tp_offset;
r_u8 padding1;//alignment
wland_sta_data_t sta_data;
r_u8 pmk[32];
r_u8 ip[RDA5981_SYS_DATA_IP_LENGTH];
r_u32 parter_data_len;
wland_tx_power_t tx_power;
r_u16 xtal_cal;
r_u8 padding2[2];//alignment
r_u16 tx_power_rf[14];
r_u8 tx_power_phy_gn;
r_u8 tx_power_phy_b;
r_u8 padding3[2];
wland_ap_data_t ap_data;
wland_ap_net_data_t ap_net_data;
wland_dhcp_t dhcp;
r_u32 uart;
wland_rf_t rf;
wland_rf_channels_t rf_channels;
wland_phy_t phy;
wland_phy_channels_t phy_channels;
}rda5981_sys_data_t;
extern r_s32 rda5981_write_sys_data(r_u8 *data, r_u16 len, r_u32 flag);
extern r_s32 rda5981_erase_sys_data(r_u32 flag);
extern r_s32 rda5981_read_sys_data(r_u8 *data, r_u16 len, r_u32 flag);
extern r_s32 rda5981_init_sys_data();
extern r_s32 rda5981_write_sys_data_regs(r_u8 *reg, r_u8 *value, r_u32 flag);
extern r_s32 rda5981_erase_sys_data_regs(r_u8 *reg, r_u32 flag);
extern r_s32 rda5981_read_sys_data_regs(r_u8 *reg, r_u8 *value, r_u32 flag);
#endif /*_RDA5981_SYS_DATA_H_*/

48
Living_SDK/platform/mcu/rda5981x/gen_crc_bin.mk Normal file
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ifeq ($(HOST_OS),Win32)
XZ := $(TOOLS_ROOT)/cmd/win32/xz.exe
CP := $(TOOLS_ROOT)/cmd/win32/cp.exe
else # Win32
ifeq ($(HOST_OS),Linux32)
XZ := $(TOOLS_ROOT)/cmd/linux32/xz
CP := $(TOOLS_ROOT)/cmd/linux32/cp
else # Linux32
ifeq ($(HOST_OS),Linux64)
XZ := $(TOOLS_ROOT)/cmd/linux64/xz
CP := $(TOOLS_ROOT)/cmd/linux64/cp
else # Linux64
ifeq ($(HOST_OS),OSX)
XZ := $(TOOLS_ROOT)/cmd/osx/xz
CP := $(TOOLS_ROOT)/cmd/osx/cp
else # OSX
$(error not surport for $(HOST_OS))
endif # OSX
endif # Linux64
endif # Linux32
endif # Win32
XZ_CMD := if [ -f $(XZ) ]; then $(XZ) --format=lzma -A -z -k -f -v $(BIN_OUTPUT_FILE); else echo "xz need be installed"; fi
OTA_BIN_OUTPUT_FILE :=$(LINK_OUTPUT_FILE:$(LINK_OUTPUT_SUFFIX)=_ota$(BIN_OUTPUT_SUFFIX))
ALI_OTA_BIN_OUTPUT_FILE :=$(LINK_OUTPUT_FILE:$(LINK_OUTPUT_SUFFIX)=_ali_ota$(BIN_OUTPUT_SUFFIX))
BOOTLOADER_FILE := platform/mcu/$(HOST_MCU_FAMILY)/bootloader/bootloader.bin
FACTORY_FILE := board/$(PLATFORM)/factory/factory.bin
ENCRYPT := "$(SOURCE_ROOT)/platform/mcu/$(HOST_MCU_FAMILY)/scripts/gen_firmware_img.py"
ifneq ($(findstring $(PLATFORM), hf-lpb130 hf-lpb135 hf-lpt130 hf-lpt230),)
HF_XZ_CMD := if [ -f $(XZ) ]; then $(XZ) --format=lzma -a -z -k -f -v $(BIN_OUTPUT_FILE); else echo "xz need be installed"; fi
endif
EXTRA_POST_BUILD_TARGETS += gen_crc_bin
gen_crc_bin:
@$(CP) $(BIN_OUTPUT_FILE) $(BIN_OUTPUT_FILE).org
@$(XZ_CMD)
$(PYTHON) $(ENCRYPT) $(BIN_OUTPUT_FILE) 0 $(BOOTLOADER_FILE) NONE $(FACTORY_FILE)
$(PYTHON) $(SCRIPTS_PATH)/ota_gen_md5_bin.py $(OTA_BIN_OUTPUT_FILE)
ifneq ($(HF_XZ_CMD), )
@$(CP) $(BIN_OUTPUT_FILE).lzma $(BIN_OUTPUT_FILE).ali.lzma
@$(CP) $(OTA_BIN_OUTPUT_FILE) $(ALI_OTA_BIN_OUTPUT_FILE)
@$(HF_XZ_CMD)
$(PYTHON) $(ENCRYPT) $(BIN_OUTPUT_FILE) 0 $(BOOTLOADER_FILE) HF $(FACTORY_FILE)
$(PYTHON) $(SCRIPTS_PATH)/ota_gen_md5_bin.py $(OTA_BIN_OUTPUT_FILE)
endif

332
Living_SDK/platform/mcu/rda5981x/hal/flash.c Normal file
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#include <string.h>
#include "hal/soc/soc.h"
#include "flash_api.h"
#include "flash_data.h"
#include "aos/kernel.h"
#include "board.h"
#include "rda_flash.h"
#define PARTITION_TABLE_END_ADDR 0x18001000
static flash_t flash_obj;
static uint8_t flash_inited = 0;
static aos_mutex_t *flash_mutex;
#if 0
static const hal_logic_partition_t hal_partitions[] = {
[HAL_PARTITION_APPLICATION] =
{
.partition_owner = HAL_FLASH_EMBEDDED,
.partition_description = "Application",
.partition_start_addr = 0x18000000,
.partition_length = 0x400000, //4MB
.partition_options = PAR_OPT_READ_EN | PAR_OPT_WRITE_EN,
},
};
#else
extern const hal_logic_partition_t hal_partitions[];
#endif
static inline uint8_t is_aligned(uint32_t number, uint32_t alignment)
{
//printf("is_aligned number 0x%x, alignment 0x%x \r\n", number, alignment);
if ((number % alignment) != 0) {
return 0;
} else {
return 1;
}
}
uint8_t is_aligned_to_sector(uint32_t addr, uint32_t size)
{
uint32_t current_sector_size = flash_get_sector_size(&flash_obj, addr);
if (!is_aligned(size, current_sector_size) ||
!is_aligned(addr, current_sector_size)) {
return 0;
} else {
return 1;
}
}
uint32_t get_page_size()
{
if (0 == flash_inited) {
flash_init(&flash_obj);
aos_mutex_new(flash_mutex);
flash_inited = 1;
}
return flash_get_page_size(&flash_obj);
}
uint32_t get_sector_size(uint32_t addr)
{
if (0 == flash_inited) {
flash_init(&flash_obj);
aos_mutex_new(flash_mutex);
flash_inited = 1;
}
return flash_get_sector_size(&flash_obj, addr);
}
uint32_t get_flash_start()
{
if (0 == flash_inited) {
flash_init(&flash_obj);
aos_mutex_new(flash_mutex);
flash_inited = 1;
}
return flash_get_start_address(&flash_obj);
}
uint32_t get_flash_size()
{
if (0 == flash_inited) {
flash_init(&flash_obj);
aos_mutex_new(flash_mutex);
flash_inited = 1;
}
return flash_get_size(&flash_obj);
}
hal_logic_partition_t *hal_flash_get_info(hal_partition_t in_partition)
{
hal_logic_partition_t *logic_partition;
// if (in_partition != HAL_PARTITION_APPLICATION)
// return NULL;
logic_partition = (hal_logic_partition_t *)&hal_partitions[in_partition];
return logic_partition;
}
int32_t hal_flash_erase(hal_partition_t in_partition, uint32_t off_set, uint32_t size)
{
hal_logic_partition_t *partition_info;
uint32_t start_address, end_addr;
if (0 == flash_inited) {
flash_init(&flash_obj);
aos_mutex_new(flash_mutex);
flash_inited = 1;
}
partition_info = hal_flash_get_info( in_partition );
start_address = partition_info->partition_start_addr + off_set;
#if 0
//uint32_t start_address = flash_get_start_address(&flash_obj);
uint32_t current_sector_size = flash_get_sector_size(&flash_obj, off_set + start_address);
if ((off_set + start_address < PARTITION_TABLE_END_ADDR) ||
(off_set + size > flash_get_size(&flash_obj))) {
printf("size err \r\n");
return -1;
}
if (!is_aligned_to_sector(off_set + start_address, size)) {
printf("is_aligned_to_sector err \r\n");
return -1;
}
int32_t ret = 0;
aos_mutex_lock(flash_mutex, 0xFFFFFFFF);
while (size) {
ret = flash_erase_sector(&flash_obj, off_set + start_address);
//printf("flash erase sector ret %d \r\n", ret);
if (ret != 0) {
ret = -1;
break;
}
size -= current_sector_size;
off_set += current_sector_size;
}
aos_mutex_unlock(flash_mutex);
return ret;
#else
//printf("hal_flash_erase start_address is 0x%x, size is %d \r\n", start_address, size);
return rda5981_erase_flash(start_address, size);
#endif
}
int flash_write(unsigned int addr, char *buf, unsigned int len)
{
int ret;
int left;
unsigned int addr_t, len_t;
char *temp_buf = NULL;
if (NULL == buf) { /* NULL pointer error */
return -1;
}
if (0 == len) { /* length is zero */
return 0;
}
addr_t = addr & 0xffffff00;
len_t = addr - addr_t + len;
if(len_t%256)
len_t += 256-len_t%256;
//printf("addr %x addr_t %x\r\n", addr, addr_t);
//printf("len %d len_t %d\r\n", len, len_t);
temp_buf = (char*)malloc(256);
if(temp_buf == NULL)
return -1;
ret = rda5981_read_flash(addr_t, temp_buf, 256);
if(ret){
free(temp_buf);
return -1;
}
left = 256 - (addr - addr_t);
if (len < left)
memcpy(temp_buf+addr-addr_t, buf, len);//256-(addr-addr_t));
else
memcpy(temp_buf+addr-addr_t, buf, left);
ret = rda5981_write_flash(addr_t, temp_buf, 256);
if(ret){
free(temp_buf);
return -1;
}
len_t -= 256;
buf += 256-(addr-addr_t);
len -= 256-(addr-addr_t);
addr_t += 256;
while(len_t != 0){
//printf("len_t %d buf %x len %d addr_t %x\r\n", len_t, buf, len, addr_t);
if(len >= 256){
memcpy(temp_buf, buf, 256);
}else{
ret = rda5981_read_flash(addr_t, temp_buf, 256);
if(ret){
free(temp_buf);
return -1;
}
memcpy(temp_buf, buf, len);
}
ret = rda5981_write_flash(addr_t, temp_buf, 256);
if(ret){
free(temp_buf);
return -1;
}
len_t -= 256;
buf += 256;
len -= 256;
addr_t += 256;
}
free(temp_buf);
return 0;
}
int32_t hal_flash_write(hal_partition_t in_partition, uint32_t *off_set,
const void *in_buf, uint32_t in_buf_len)
{
int32_t ret = 0;
hal_logic_partition_t *partition_info;
uint32_t page_size = get_page_size();
//uint32_t start_address = flash_get_start_address(&flash_obj);
partition_info = hal_flash_get_info( in_partition );
uint32_t start_address = partition_info->partition_start_addr + *off_set;
uint32_t partition_end = partition_info->partition_start_addr + partition_info->partition_length;
if(start_address >= partition_end){
printf("flash over write\r\n");
return -1;
}
if((start_address + in_buf_len) > partition_end){
in_buf_len = partition_end - start_address;
printf("flash over write, new len is %d\r\n", in_buf_len);
}
#if 0
uint32_t current_sector_size = flash_get_sector_size(&flash_obj, (uint32_t)off_set + start_address);
if (((uint32_t)*off_set + start_address < PARTITION_TABLE_END_ADDR) ||
((uint32_t)*off_set + in_buf_len > flash_get_size(&flash_obj))){
return -1;
}
if (0 == is_aligned((uint32_t)*off_set + start_address, page_size)) {
printf("hal_flash_write not aligned\r\n");
return -1;
}
int32_t ret = 0;
aos_mutex_lock(flash_mutex, 0xFFFFFFFF);
if (flash_program_page(&flash_obj, (uint32_t)*off_set + start_address, (const uint8_t *)in_buf, in_buf_len)) {
ret = -1;
}
aos_mutex_unlock(flash_mutex);
return ret;
#else
if ((start_address < PARTITION_TABLE_END_ADDR) ||
((uint32_t)*off_set + in_buf_len > flash_get_size(&flash_obj))){
return -1;
}
ret = flash_write(start_address, (const uint8_t *)in_buf, in_buf_len);
*off_set += in_buf_len;
return ret;
#endif
}
int32_t hal_flash_erase_write(hal_partition_t in_partition, uint32_t *off_set,
const void *in_buf, uint32_t in_buf_len)
{
int32_t ret = 0;
ret = hal_flash_erase(in_partition, (uint32_t)*off_set, in_buf_len);
if (ret != 0)
return -1;
ret = hal_flash_write(in_partition, *off_set, in_buf, in_buf_len);
if (ret != 0)
return -1;
return 0;
}
int32_t hal_flash_read(hal_partition_t in_partition, uint32_t *off_set,
void *out_buf, uint32_t in_buf_len)
{
hal_logic_partition_t *partition_info;
if (0 == flash_inited) {
flash_init(&flash_obj);
flash_inited = 1;
}
partition_info = hal_flash_get_info( in_partition );
uint32_t start_address = partition_info->partition_start_addr + *off_set;
if ((start_address < PARTITION_TABLE_END_ADDR) ||
((uint32_t)*off_set + in_buf_len > flash_get_size(&flash_obj))){
return -1;
}
*off_set += in_buf_len;
return rda5981_read_flash(start_address, (const uint8_t *)out_buf, in_buf_len);
#if 0
//uint32_t start_address = flash_get_start_address(&flash_obj);
if (((uint32_t)*off_set + start_address < PARTITION_TABLE_END_ADDR) ||
((uint32_t)*off_set + in_buf_len > flash_get_size(&flash_obj))){
return -1;
}
aos_mutex_lock(flash_mutex, 0xFFFFFFFF);
memcpy(out_buf, (const void *)((uint32_t)*off_set + start_address), in_buf_len);
aos_mutex_unlock(flash_mutex);
#endif
return 0;
}
int32_t hal_flash_enable_secure(hal_partition_t partition, uint32_t off_set, uint32_t size)
{
return 0;
}
int32_t hal_flash_dis_secure(hal_partition_t partition, uint32_t off_set, uint32_t size)
{
return 0;
}

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#include <stdio.h>
#include <stdint.h>
#include "hal/soc/gpio.h"
#include "pinnames.h"
#include "gpio_api.h"
int32_t hal_gpio_init(gpio_dev_t *gpio)
{
if (gpio->port >= GPIO_NUM)
return -1;
gpio->priv = &gpio_obj[gpio->port];
gpio_init(gpio->priv, gpio_map[gpio->port]);
return 0;
}
int32_t hal_gpio_output_high(gpio_dev_t *gpio)
{
gpio_dir(gpio->priv, PIN_OUTPUT);
gpio_write(gpio->priv, 1);
return 0;
}
int32_t hal_gpio_output_low(gpio_dev_t *gpio)
{
gpio_dir(gpio->priv, PIN_OUTPUT);
gpio_write(gpio->priv, 0);
return 0;
}
int32_t hal_gpio_output_toggle(gpio_dev_t *gpio)
{
int32_t val;
val = ((gpio_t *)gpio->priv)->reg_out;
val ^= 1;
gpio_dir(gpio->priv, PIN_OUTPUT);
gpio_write(gpio->priv, val);
return 0;
}
int32_t hal_gpio_input_get(gpio_dev_t *gpio, uint32_t *value)
{
int32_t rc = -1;
if(NULL != gpio ) {
gpio_dir(gpio->priv, PIN_INPUT);
rc = gpio_read(gpio->priv);
if ( NULL != value) {
*value = rc;
rc = 0;
}
}
return rc;
}
int32_t hal_gpio_enable_irq(gpio_dev_t *gpio, gpio_irq_trigger_t trigger,
gpio_irq_handler_t handler, void *arg)
{
gpio_dir(gpio->priv, PIN_INPUT);
gpio_irq_init(gpio->priv, (unsigned int)handler, (unsigned int)arg);
if(trigger == IRQ_TRIGGER_RISING_EDGE){
gpio_irq_set(gpio->priv, IRQ_RISE, 1);
}else if(trigger == IRQ_TRIGGER_FALLING_EDGE){
gpio_irq_set(gpio->priv, IRQ_FALL, 1);
}else{
gpio_irq_set(gpio->priv, IRQ_RISE, 1);
gpio_irq_set(gpio->priv, IRQ_FALL, 1);
}
return 0;
}
int32_t hal_gpio_disable_irq(gpio_dev_t *gpio)
{
gpio_irq_free(gpio->priv);
return 0;
}
int32_t hal_gpio_clear_irq(gpio_dev_t *gpio)
{
gpio_irq_free(gpio->priv);
return 0;
}
int32_t hal_gpio_finalize(gpio_dev_t *gpio)
{
return 0;
}

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <stdio.h>
#include <stdbool.h>
#include <string.h>
#include <unistd.h>
#include <k_api.h>
#include <aos/log.h>
#include <hal/soc/soc.h>
#include <hal/soc/timer.h>
#include <hal/base.h>
#include <hal/wifi.h>
#include "rda5981.h"
#define TAG "hw"
#define us2tick(us) \
((us * RHINO_CONFIG_TICKS_PER_SECOND + 999999) / 1000000)
//uart_dev_t uart_0;
void hal_reboot(void)
{
rda_ccfg_ckrst();
rda_ccfg_perrst();
/* Ensure all outstanding memory accesses included buffered write are completed before reset */
__DSB();
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */
SCB_AIRCR_VECTRESET_Msk);
/* Ensure completion of memory access */
__DSB();
/* wait until reset */
while(1) { __NOP(); }
}
#if 0
static void _timer_cb(void *timer, void *arg)
{
timer_dev_t *tmr = arg;
tmr->config.cb(tmr->config.arg);
}
int32_t hal_timer_init(timer_dev_t *tim)
{
if (tim->config.reload_mode == TIMER_RELOAD_AUTO) {
krhino_timer_dyn_create((ktimer_t **)&tim->priv, "hwtmr", _timer_cb,
us2tick(tim->config.period), us2tick(tim->config.period), tim, 0);
}
else {
krhino_timer_dyn_create((ktimer_t **)&tim->priv, "hwtmr", _timer_cb,
us2tick(tim->config.period), 0, tim, 0);
}
}
int32_t hal_timer_start(timer_dev_t *tmr)
{
return krhino_timer_start(tmr->priv);
}
void hal_timer_stop(timer_dev_t *tmr)
{
krhino_timer_stop(tmr->priv);
krhino_timer_dyn_del(tmr->priv);
tmr->priv = NULL;
}
#endif
extern hal_wifi_module_t aos_wifi_rda59xx;
void hw_start_hal(void)
{
printf("start-----------hal\n");
hal_wifi_register_module(&aos_wifi_rda59xx);
hal_wifi_init();
}

174
Living_SDK/platform/mcu/rda5981x/hal/pwrmgmt_hal/board_cpu_pwr.c Executable file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
DESCRIPTION
This library provides the support for the STM32L496G-DISCOVERY
CPU power state control.
CPU power management:
provides low-level interface for setting CPU C-states.
provides low-level interface for setting CPU P-states.
*/
#include <k_api.h>
#if RHINO_CONFIG_CPU_PWR_MGMT
#include <pwrmgmt_api.h>
#include <cpu_pwr_hal_lib.h>
#include <pwrmgmt_debug.h>
#include <cpu_tickless.h>
#include "rda_def.h"
#include "rda5981.h"
/* forward declarations */
extern one_shot_timer_t lpticker_one_shot; /* wakeup source for C3,C4 */
static cpu_pwr_t cpu_pwr_node_core_0;
/**
* board_cpu_c_state_set - program CPU into Cx idle state
*
* RUN Context: could be called from ISR context or task context.
*
* SMP Consider: STM32L496G-DISCOVERY do not support SMP, so only UP is enough.
*
* @return PWR_OK or PWR_ERR when failed.
*/
static pwr_status_t board_cpu_c_state_set(uint32_t cpuCState, int master)
{
int cnt;
switch (cpuCState) {
case CPU_CSTATE_C0:
if (master) {
/*
* do something needed when CPU waked up from C1 or higher
* Cx state.
*/
//printf("enter C0\r\n");
//wland_set_sta_sleep(1);
}
break;
case CPU_CSTATE_C1: /* SLEEP_NORMAL */
/* put CPU into C1 state, for ARM we can call WFI instruction
to put CPU into C1 state. */
PWR_DBG(DBG_INFO, "enter C1\n");
__DSB();
__WFI();
__ISB();
PWR_DBG(DBG_INFO, "exit C1\n");
break;
default:
PWR_DBG(DBG_ERR, "invalid C state: C%d\n", cpuCState);
break;
}
return PWR_OK;
}
/**
* board_cpu_pwr_init() is called by HAL lib to
* init board powr manage configure.
*
* RUN Context: could be called from task context only, ISR context is not
* supported.
*
* SMP Consider: STM32L496G-DISCOVERY do not support SMP, so only UP is enough.
*
* @return PWR_OK or PWR_ERR when failed.
*/
pwr_status_t board_cpu_pwr_init(void)
{
cpu_pwr_t *pCpuNode = NULL;
pwr_status_t retVal = PWR_OK;
uint32_t cpuIndex = 0; /* 0 for UP */
pCpuNode = &cpu_pwr_node_core_0;
retVal = cpu_pwr_node_init_static("core", 0, pCpuNode);
if (retVal != PWR_OK) {
return PWR_ERR;
}
/* record this node */
retVal = cpu_pwr_node_record(pCpuNode, cpuIndex);
if (retVal == PWR_ERR) {
return PWR_ERR;
}
/*
* According reference manual of STM32L496G-DISCOVERY
*
* C0 - RUN, Power supplies are on,all clocks are on.
* C1 - Sleep mode, CPU clock off, all peripherals including
* Cortex®-M4 core peripherals such as NVIC, SysTick, etc. can run
* and wake up the CPU when an interrupt or an event occurs.
*/
retVal = cpu_pwr_c_method_set(cpuIndex, board_cpu_c_state_set);
if (retVal == PWR_ERR) {
return PWR_ERR;
}
/* save support C status bitset : C0,C1 */
cpu_pwr_c_state_capability_set(cpuIndex, CPU_STATE_BIT(CPU_CSTATE_C0)
| CPU_STATE_BIT(CPU_CSTATE_C1)
);
if (retVal == PWR_ERR) {
return PWR_ERR;
}
/*
* According reference manual of STM32L496G-DISCOVERY,
* the wakeup latency of Cx is:
* resume from C1 (Low Power mode) : immediate
*/
cpu_pwr_c_state_latency_save(cpuIndex, CPU_CSTATE_C0, 0);
cpu_pwr_c_state_latency_save(cpuIndex, CPU_CSTATE_C1, 0);
tickless_one_shot_timer_save(CPU_CSTATE_C1, &lpticker_one_shot);
/*
Tell the CPU PWR MGMT module which C state is supported with
tickless function through tickless_c_states_add(c_state_x).
*/
tickless_c_states_add(CPU_STATE_BIT(CPU_CSTATE_C1));
#if RHINO_CONFIG_CPU_PWR_SHOW
cpu_pwr_info_show();
cpu_pwr_state_show();
#endif
return retVal;
}
unsigned int pwrmgmt_suspend_flag = 0;
int pwrmgmt_suspend_lowpower() {
CPSR_ALLOC();
RHINO_CRITICAL_ENTER();
pwrmgmt_suspend_flag = 1;
RHINO_CRITICAL_EXIT_SCHED();
#if (WIFI_CONFIG_SUPPORT_LOWPOWER > 0)
wland_set_sta_sleep(1);
#endif
return 1;
}
int pwrmgmt_resume_lowpower() {
CPSR_ALLOC();
RHINO_CRITICAL_ENTER();
pwrmgmt_suspend_flag = 0;
RHINO_CRITICAL_EXIT_SCHED();
#if (WIFI_CONFIG_SUPPORT_LOWPOWER > 0)
wland_set_sta_sleep(0);
#endif
return 1;
}
#endif /* RHINO_CONFIG_CPU_PWR_MGMT */

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Living_SDK/platform/mcu/rda5981x/hal/pwrmgmt_hal/board_cpu_pwr_systick.c Executable file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
DESCRIPTION
This file provides two fundtions systick_suspend()/systick_resume()
which is used by cpu tickless module to suspend/resume system tick
interrupt.
Differrent board may has different way to suspend/resume system tick
interrupt, please reference your board/soc user manual to find the
detail for how to implement these two functions.
*/
#include <k_api.h>
#include "rda5981.h"
#if (RHINO_CONFIG_CPU_PWR_MGMT > 0)
void systick_suspend(void)
{
SysTick->CTRL &= ~(SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk);
}
void systick_resume(void)
{
SysTick->CTRL |= (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
}
#endif /* RHINO_CONFIG_CPU_PWR_MGMT */

285
Living_SDK/platform/mcu/rda5981x/hal/pwrmgmt_hal/board_lp_ticker.c Executable file
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/* mbed Microcontroller Library
* Copyright (c) 2006-2018 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if RHINO_CONFIG_CPU_PWR_MGMT
#include <cpu_tickless.h>
#include "rda5981.h"
#include "rda_ccfg_api.h"
#define rFREE_TIMER_INITVAL (RDA_SCU->FTMRINITVAL)
#define rFREE_TIMER_PRESCALE (RDA_SCU->FTMRPREVAL)
#define rFREE_TIMER_TIMESTAMP (RDA_SCU->FTMRTS)
#define rRDA_POWER_CONTROL (RDA_SCU->PWRCTRL)
#define rTIMER1_CONTROL (RDA_TIM1->TCTRL)
#define rTIMER1_INTCLR (RDA_TIM1->INTCLR)
#define FREE_TIMER_INIT_VAL (0xFFFFFFFFUL)
#define US_TIMER_HZ (1000000)
#define LP_TIMER_CLOCK_SOURCE (32768)
static int lp_ticker_inited = 0;
//static int32_t lp_ticker_int_flag = 0;
//int32_t lp_ticker_soft_int_flag = 0;
extern void rda_timer_irq_set(void);
extern void rda_ccfg_aontmr_cksrc(int cksrc);
static pwr_status_t lpticker_init(void);
static uint32_t lpticker_one_shot_max_seconds(void);
static pwr_status_t lpticker_one_shot_start(uint64_t planUs);
static pwr_status_t lpticker_one_shot_stop(uint64_t *pPassedUs);
static void lp_timer_isr(void);
static uint32_t last_timetamp;
one_shot_timer_t lpticker_one_shot = {
lpticker_init,
lpticker_one_shot_max_seconds,
lpticker_one_shot_start,
lpticker_one_shot_stop,
};
pwr_status_t lpticker_init(void)
{
uint32_t regval;
if (lp_ticker_inited)
return;
rda_ccfg_aontmr_cksrc(1);
/* Enable apb timer clock */
RDA_SCU->CLKGATE1 |= (0x01UL << 3);
/* Set free timer power */
rda_ccfg_aontmr();
/* Delay 300us at least */
{
unsigned int idx = (SystemCoreClock / US_TIMER_HZ / 4UL) * 300UL;
regval = 0U;
while (idx--) {
regval += rFREE_TIMER_TIMESTAMP;
}
}
/* Set free timer write_en */
rRDA_POWER_CONTROL |= (uint32_t)(0x01UL << 8);
rFREE_TIMER_INITVAL = FREE_TIMER_INIT_VAL;
/* Enable int */
//rTIMER1_CONTROL |= (0x01UL << 4);
rRDA_POWER_CONTROL &= ~(0x01UL << 18);
/* mask int */
//rTIMER1_CONTROL |= (0x01UL << 3);
/* Unmask int */
rTIMER1_CONTROL &= ~(0x01UL << 3);
/* Set free timer prescale */
rFREE_TIMER_PRESCALE = 0U;
/* Enable free timer */
rRDA_POWER_CONTROL |= (uint32_t)(0x01UL << 17);
/* Clr free timer write_en */
rRDA_POWER_CONTROL &= (~(uint32_t)(1 << 8));
NVIC_SetVector(TIMER_IRQn, (uint32_t)lp_timer_isr);
NVIC_SetPriority(TIMER_IRQn, 0x1FUL);
NVIC_EnableIRQ(TIMER_IRQn);
/* Set lp_ticker_inited true, after all settings done */
lp_ticker_inited = 1;
return PWR_OK;
}
#if 0
static inline uint32_t lp_ticker_read(void)
{
if (!lp_ticker_inited)
lpticker_init();
/* Get timestamp */
return (uint32_t)(rFREE_TIMER_TIMESTAMP);
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
uint32_t delta = (int32_t)(timestamp - lp_ticker_read());
/* Set free timer write_en */
rRDA_POWER_CONTROL |= (uint32_t)(0x01UL << 8);
rFREE_TIMER_INITVAL = delta;
/* Enable int */
//rTIMER1_CONTROL |= (0x01UL << 4);
rRDA_POWER_CONTROL |= (0x01UL << 18);
/* Unmask int */
//rTIMER1_CONTROL &= ~(0x01UL << 3);
/* Clr free timer write_en */
rRDA_POWER_CONTROL &= (~(uint32_t)(1 << 8));
lp_ticker_int_flag = 1;
}
void lp_ticker_int_callback()
{
/* Check the flag firstly, because following hanlder can change it */
if (lp_ticker_soft_int_flag) {
lp_ticker_soft_int_flag = 0;
}else if(lp_ticker_int_flag){
//mbed_error_printf("lp\r\n");
lp_ticker_int_flag = 0;
/* Set free timer write_en */
rRDA_POWER_CONTROL |= (uint32_t)(0x01UL << 8);
/* Disable int */
rRDA_POWER_CONTROL &= ~(0x01UL << 18);
/* Clr free timer write_en */
rRDA_POWER_CONTROL &= (~(uint32_t)(1 << 8));
rRDA_POWER_CONTROL |= (0x01UL << 28);
__DSB();
while (rRDA_POWER_CONTROL & (0x01UL << 28));
}
return;
}
void lp_ticker_fire_interrupt(void)
{
lp_ticker_soft_int_flag = 1;
NVIC_SetPendingIRQ(TIMER_IRQn);
}
#endif
static inline void lp_ticker_disable_interrupt(void)
{
/* Disable int */
rRDA_POWER_CONTROL &= ~(0x01UL << 18);
}
static inline void lp_ticker_clear_interrupt(void)
{
rRDA_POWER_CONTROL |= (0x01UL << 28); // clear int
__DSB();
while (rRDA_POWER_CONTROL & (0x01UL << 28));
}
static inline void lp_ticker_free(void)
{
/* Set free timer write_en */
rRDA_POWER_CONTROL |= (uint32_t)(0x01UL << 8);
/* Disable free timer */
rRDA_POWER_CONTROL &= ~(0x01UL << 17);
/* Clr free timer write_en */
rRDA_POWER_CONTROL &= (~(uint32_t)(1 << 8));
}
static pwr_status_t lpticker_one_shot_start(uint64_t planUs)
{
#if (PWRMGMT_CONFIG_LOG_ENTERSLEEP > 0)
static sys_time_t last_log_entersleep = 0;
#endif
uint32_t cc_counter = planUs * LP_TIMER_CLOCK_SOURCE / 1000000;
//printf("%s:%d\r\n",__func__,cc_counter);
if (cc_counter < 3) {
return PWR_ERR;
}
#if (PWRMGMT_CONFIG_LOG_ENTERSLEEP > 0)
if (krhino_sys_tick_get() > (last_log_entersleep + RHINO_CONFIG_TICKS_PER_SECOND)) {
last_log_entersleep = krhino_sys_tick_get();
printf("enter sleep %d ms\r\n", (uint32_t) planUs/1000);
}
#endif
/* Set free timer write_en */
rRDA_POWER_CONTROL |= (uint32_t)(0x01UL << 8);
last_timetamp = rFREE_TIMER_TIMESTAMP;
rFREE_TIMER_INITVAL = cc_counter;
/* Enable int */
//rTIMER1_CONTROL |= (0x01UL << 4);
rRDA_POWER_CONTROL |= (0x01UL << 18);
/* Enable free timer */
rRDA_POWER_CONTROL |= (uint32_t)(0x01UL << 17);
/* Unmask int */
//rTIMER1_CONTROL &= ~(0x01UL << 3);
/* Clr free timer write_en */
rRDA_POWER_CONTROL &= (~(uint32_t)(1 << 8));
return PWR_OK;
}
uint8_t int_flag = 0; /* use this vale for hardware bug */
static pwr_status_t lpticker_one_shot_stop(uint64_t *pPassedUs)
{
uint32_t interval = 0, timetamp = 0, delta = 0;
timetamp = rFREE_TIMER_TIMESTAMP;
interval = rFREE_TIMER_INITVAL;
lp_ticker_disable_interrupt();
if (int_flag == 1) {
lp_ticker_clear_interrupt();
}
lp_ticker_free();
/* fix hardware bug */
if ((timetamp < last_timetamp) && (last_timetamp < 0x0f000000)) {
printf("warning : lp timer wrapped\r\n");
last_timetamp = 0xffffffff;
}
delta = (timetamp >= last_timetamp) ? (timetamp - last_timetamp) : (timetamp + 0xffffffff - last_timetamp);
*pPassedUs = (uint64_t)delta * 1000000 / LP_TIMER_CLOCK_SOURCE;
// *pPassedUs = *pPassedUs + 30;
//mbed_error_printf("last:%d now:%d delta:%d\r\n",last_timetamp,timetamp,delta);
//mbed_error_printf("%s:%d\r\n",__func__,*pPassedUs);
return PWR_OK;
}
extern unsigned int pwrmgmt_suspend_flag;
static uint32_t lpticker_one_shot_max_seconds(void){
if (pwrmgmt_suspend_flag == 1) {
return 0;
}
return (FREE_TIMER_INIT_VAL/LP_TIMER_CLOCK_SOURCE);
}
static void lp_timer_isr(void){
//mbed_error_printf("%s\r\n",__func__);
int_flag = 1;
krhino_intrpt_enter();
int_flag = 0;
krhino_intrpt_exit();
}
#endif

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#include "rda_ccfg_api.h"
#include "rda5981.h"
#define CLK_FREQ_40M (0x00U)
#define CLK_FREQ_80M (0x01U)
#define CLK_FREQ_160M (0x02U)
#define ADDR2REG(addr) (*((volatile unsigned int *)(addr)))
#define RF_SPI_REG ADDR2REG(0x4001301CUL)
#define TRAP_CTRL_REG ADDR2REG(0x40011000UL)
#define TRAP0_SRC_REG ADDR2REG(0x40011004UL)
#define TRAP0_DST_REG ADDR2REG(0x40011024UL)
#define TRAP1_SRC_REG ADDR2REG(0x40011008UL)
#define TRAP1_DST_REG ADDR2REG(0x40011028UL)
#define SPIF_CFG_REG ADDR2REG(0x17FFF014UL)
#define MACHW_RST_REG ADDR2REG(0x4002003CUL)
#define TRAP_RAM_BASE (0x00100000UL)
#define SYS_CPU_CLK CLK_FREQ_160M
#define AHB_BUS_CLK CLK_FREQ_80M
static int ChipHwVersion = 0;
static inline void wr_rf_usb_reg(unsigned char a, unsigned short d, int isusb)
{
while(RF_SPI_REG & (0x01UL << 31));
while(RF_SPI_REG & (0x01UL << 31));
RF_SPI_REG = (unsigned int)d | ((unsigned int)a << 16) | (0x01UL << 25) | ((isusb) ? (0x01UL << 27) : 0x00UL);
}
static inline void rd_rf_usb_reg(unsigned char a, unsigned short *d, int isusb)
{
while(RF_SPI_REG & (0x01UL << 31));
while(RF_SPI_REG & (0x01UL << 31));
RF_SPI_REG = ((unsigned int)a << 16) | (0x01UL << 24) | (0x01UL << 25) | ((isusb) ? (0x01UL << 27) : 0x00UL);
__asm volatile ("nop");
while(RF_SPI_REG & (0x01UL << 31));
while(RF_SPI_REG & (0x01UL << 31));
*d = (unsigned short)(RF_SPI_REG & 0xFFFFUL);
}
#if RDA5991H_HW_VER == 1
/* Config UART0 RX pin */
static inline int rda_ccfg_gp26(void)
{
int ret = 0;
unsigned short val = 0U;
rd_rf_usb_reg(0xCD, &val, 0);
ret = (int)((val >> 6) & 0x01U);
if(!ret) {
wr_rf_usb_reg(0xCD, (val | (0x01U << 6)), 0);
}
return ret;
}
/* Config USB */
static inline void rda_ccfg_usb(void)
{
wr_rf_usb_reg(0x89, 0xEEDD, 1);
}
/* Config PMU */
static inline void rda_ccfg_pmu(void)
{
unsigned short val = 0U;
rd_rf_usb_reg(0xC0, &val, 0);
wr_rf_usb_reg(0xC0, (val | (0x01U << 2)), 0); /* set sido_ctrl_comp2 */
}
#endif /* RDA5991H_HW_VER */
/* Power down the debug-usage I2C */
static inline void rda_ccfg_pdi2c(void)
{
unsigned int val = RDA_PINCFG->MUX2;
if(0x00UL == (val & 0x3FUL)) {
RDA_PINCFG->MUX2 = val | 0x09UL;
}
wr_rf_usb_reg(0xA1, 0x0000, 0);
}
/* Config CPU & Bus clock */
static inline void rda_ccfg_ck(void)
{
unsigned short val = 0U, cfg = 0U;
#if ((SYS_CPU_CLK == CLK_FREQ_160M) && (AHB_BUS_CLK == CLK_FREQ_80M))
#if 0
const unsigned int trap_ram_code[] = {
/* addr_ofst, val */
/* 0x0000 */ 0xB8A6F0FEUL,
/* 0x0004 */ 0xBF006008UL,
/* 0x0008 */ 0xBF00BF00UL,
/* 0x000C */ 0xBF00BF00UL,
/* 0x0010 */ 0xBF00BF00UL,
/* 0x0014 */ 0x6848BF00UL,
/* 0x0018 */ 0xD1FC07C0UL,
/* 0x001C */ 0xF000F8DFUL,
/* 0x0020 */ 0x00001EBCUL
};
#endif
#endif /* CLK_FREQ_160M && CLK_FREQ_80M */
cfg = (RDA_SCU->CORECFG >> 11) & 0x07U;
rd_rf_usb_reg(0xA4, &val, 0);
#if ((SYS_CPU_CLK == CLK_FREQ_160M) && (AHB_BUS_CLK == CLK_FREQ_80M))
/* HCLK inv */
if(((CLK_FREQ_40M << 1) | CLK_FREQ_40M) == cfg) {
val |= (0x01U << 12);
}
#endif /* CLK_FREQ_160M && CLK_FREQ_80M */
/* Config CPU & BUS clock */
cfg ^= (((SYS_CPU_CLK << 1) | AHB_BUS_CLK) & 0x07U);
val &= ~(0x07U << 9); /* bit[11:10] = 2'b00:40M, 2'b01:80M, 2'b1x:160M */
val |= (cfg << 9); /* bit[9] = 1'b0:40M, 1'b1:80M */
val &= ~(0x01U); /* i2c_wakeup_en */
wr_rf_usb_reg(0xA4, val, 0);
#if ((SYS_CPU_CLK == CLK_FREQ_160M) && (AHB_BUS_CLK == CLK_FREQ_80M))
#if 0
/* Load RAM code */
for(val = 0; val < sizeof(trap_ram_code); val += 4) {
ADDR2REG(TRAP_RAM_BASE + val) = trap_ram_code[val >> 2];
}
#endif
#endif /* CLK_FREQ_160M && CLK_FREQ_80M */
#if RDA5991H_HW_VER == 1
/* Trap baud rate config for bootrom */
/* Matrix between BusClk & TrapVal: */
/* */
/* -----+---------+--------+-------- */
/* C\T | 0x2814 | 0x2834 | 0x282C */
/* -----+---------+--------+-------- */
/* 40M | 921600 | 460800 | 230400 */
/* -----+------------------+-------- */
/* 80M | 1843200 | 921600 | 460800 */
/* -----+---------+--------+-------- */
/* */
TRAP0_SRC_REG = 0x00001CA4UL;
#if (AHB_BUS_CLK == CLK_FREQ_80M)
TRAP0_DST_REG = 0x0000282CUL;
#else /* CLK_FREQ_80M */
TRAP0_DST_REG = 0x00002834UL;
#endif /* CLK_FREQ_80M */
#if ((SYS_CPU_CLK == CLK_FREQ_160M) && (AHB_BUS_CLK == CLK_FREQ_80M))
/* Trap simple delay after ICACHE en */
TRAP1_SRC_REG = 0x00001EB4UL;
#if 0
TRAP1_DST_REG = TRAP_RAM_BASE + 0x0000UL;
#else
TRAP1_DST_REG = 0x00005A8CUL;
#endif
/* Enable Trap0, Trap1 */
TRAP_CTRL_REG |= (0x01UL | (0x01UL << 1));
#else /* CLK_FREQ_160M && CLK_FREQ_80M */
/* Enable Trap0 */
TRAP_CTRL_REG |= 0x01UL;
#endif /* CLK_FREQ_160M && CLK_FREQ_80M */
#endif /* RDA5991H_HW_VER */
}
/* Config SPI flash clock */
static inline void rda_ccfg_spifck(void)
{
unsigned int val;
__DSB();
val = SPIF_CFG_REG & ~(0x00FFUL << 8);
SPIF_CFG_REG = val | (0x0004UL << 8); // divider
__DSB();
}
/* Handle abort booting */
static inline int rda_ccfg_abort_hdlr(void)
{
int ret = 0;
unsigned short val = 0U;
rd_rf_usb_reg(0xA1, &val, 0);
ret = (int)((val >> 2) & 0x01U);
if(ret) {
unsigned short val2 = 0U;
rd_rf_usb_reg(0xB2, &val2, 0);
wr_rf_usb_reg(0xB2, (val2 | (0x01U << 11)), 0);
RDA_GPIO->PCCTRL |= (0x01UL << 31); // set abort flag
for(val = 0; val < 0x00FFU; val++) { // delay
;
}
wr_rf_usb_reg(0xB2, (val2 & ~(0x01U << 11)), 0);
}
return ret;
}
/* Power up the always-on timer */
void rda_ccfg_aontmr(void)
{
unsigned short val = 0U;
rd_rf_usb_reg(0xA3, &val, 0);
wr_rf_usb_reg(0xA3, (val | (0x01U << 12)), 0);
}
/* Config clock source of always-on timer */
void rda_ccfg_aontmr_cksrc(int cksrc)
{
unsigned short val;
if(0 == cksrc) { // use lpo 32K clk, hw default
wr_rf_usb_reg(0xDD, 0x5100U, 0);
rd_rf_usb_reg(0xD8, &val, 0);
wr_rf_usb_reg(0xD8, (val & ~(0x03U << 14)), 0);
rd_rf_usb_reg(0xA8, &val, 0);
val |= ((0x01U << 10) | (0x01U << 14));
wr_rf_usb_reg(0xA8, (val & ~(0x01U << 12)), 0);
} else { // use 6m5xtal 32K clk, more accurate
int idx;
wr_rf_usb_reg(0xDD, 0x8100U, 0);
rd_rf_usb_reg(0xD8, &val, 0);
wr_rf_usb_reg(0xD8, (val | (0x01U << 15)), 0);
for(idx = 0; idx < 5; idx++) { // for dealy
rd_rf_usb_reg(0x00, &val, 0);
}
wr_rf_usb_reg(0xDD, 0x9100U, 0);
rd_rf_usb_reg(0xD8, &val, 0);
wr_rf_usb_reg(0xD8, (val | (0x01U << 15) | (0x01U << 14)), 0);
rd_rf_usb_reg(0xA8, &val, 0);
val &= ~((0x01U << 10) | (0x01U << 14));
wr_rf_usb_reg(0xA8, (val | (0x01U << 12)), 0);
}
}
/* Config GPIO6 to dig core */
void rda_ccfg_gp6(unsigned short cfg)
{
unsigned short val = 0U;
rd_rf_usb_reg(0xCD, &val, 0);
val &= ~(0x01U << 11);
wr_rf_usb_reg(0xCD, (val | ((cfg & 0x01U) << 11)), 0);
}
/* Config GPIO7 to dig core */
void rda_ccfg_gp7(unsigned short cfg)
{
unsigned short val = 0U;
rd_rf_usb_reg(0xB0, &val, 0);
val &= ~(0x01U << 14);
wr_rf_usb_reg(0xB0, (val | ((cfg & 0x01U) << 14)), 0);
}
/* Config GPIO6/7/8/9 to pmu intf or dig core */
void rda_ccfg_gp(unsigned char gp, unsigned short cfg)
{
unsigned short val = 0U;
unsigned char reg = 0xCDU;
const int ofs_lst[4] = {11, 14, 10, 9};
if((6 > gp) || (9 < gp)) {
return;
}
if(7 == gp) {
reg = 0xB0U;
}
rd_rf_usb_reg(reg, &val, 0);
val &= ~(0x01U << ofs_lst[gp - 6]);
wr_rf_usb_reg(reg, (val | ((cfg & 0x01U) << ofs_lst[gp - 6])), 0);
}
/* Set some core config when booting */
int rda_ccfg_boot(void)
{
int ret = 1;
int abort_flag = rda_ccfg_abort_hdlr();
#if RDA5991H_HW_VER == 1
if(abort_flag) {
rda_ccfg_ck();
} else {
int gp26_flag = rda_ccfg_gp26();
if(!gp26_flag) {
rda_ccfg_usb();
rda_ccfg_pmu();
rda_ccfg_pdi2c();
rda_ccfg_ck();
}
ret = gp26_flag;
}
#else /* RDA5991H_HW_VER */
if(!abort_flag) {
rda_ccfg_pdi2c();
}
rda_ccfg_ck();
#endif /* RDA5991H_HW_VER */
/*close usb polling*/
RDA_GPIO->CTRL &= ~(0x01UL << 12);
/* Set flash clock */
rda_ccfg_spifck();
/* Set aon timer clock source */
rda_ccfg_aontmr_cksrc(1);
return ret;
}
/* Reset CPU & Bus clock config */
void rda_ccfg_ckrst(void)
{
unsigned short val = 0U;
rd_rf_usb_reg(0xA4, &val, 0);
/* HCLK inv */
val &= ~(0x01U << 12);
/* Config CPU clock */
val &= ~(0x03U << 10);
val |= (0x00U << 10); /* 2'b00:40M, 2'b01:80M, 2'b1x:160M */
/* Config BUS clock */
val &= ~(0x01U << 9);
val |= (0x00U << 9); /* 1'b0:40M, 1'b1:80M */
wr_rf_usb_reg(0xA4, val, 0);
}
/* Reset peripheral module */
void rda_ccfg_perrst(void)
{
MACHW_RST_REG ^= 0x01UL;
}
/* Init ADC module */
void rda_ccfg_adc_init(void)
{
unsigned short val = 0U;
rd_rf_usb_reg(0xA3, &val, 0); /* adc en */
wr_rf_usb_reg(0xA3, (val | (0x01U << 3)), 0);
rd_rf_usb_reg(0xD8, &val, 0); /* clk 6p5m en */
wr_rf_usb_reg(0xD8, (val | (0x01U << 15)), 0);
rd_rf_usb_reg(0xB7, &val, 0); /* clk 26m en */
wr_rf_usb_reg(0xB7, (val | (0x01U << 14)), 0);
}
/* Config GPIO6/7/8 pdn or pup for ADC usage */
void rda_ccfg_adc_gp(unsigned char gp, unsigned short cfg)
{
unsigned short val = 0U;
const int ofs_lst[3] = {8, 9, 7};
if((6 > gp) || (8 < gp)) {
return;
}
rd_rf_usb_reg(0xB2, &val, 0);
val &= ~(0x01U << ofs_lst[gp - 6]);
wr_rf_usb_reg(0xB2, (val | ((cfg & 0x01U) << ofs_lst[gp - 6])), 0);
}
/* Read ADC value */
unsigned short rda_ccfg_adc_read(unsigned char ch)
{
unsigned short val = 0U;
rd_rf_usb_reg(0xB6, &val, 0); /* channel select */
val &= ~((0x03U) << 12);
wr_rf_usb_reg(0xB6, (val | ((ch & 0x03U) << 12)), 0);
rd_rf_usb_reg(0xB6, &val, 0); /* set read en */
wr_rf_usb_reg(0xB6, (val | (0x01U << 2)), 0);
for(val = 0; val < 0x0FFU; val++) { // delay
;
}
rd_rf_usb_reg(0xB6, &val, 0); /* clr read en */
wr_rf_usb_reg(0xB6, (val & ~(0x01U << 2)), 0);
do {
rd_rf_usb_reg(0xB7, &val, 0); /* finish loop flag */
} while(0x00U == (val & (0x01U << 10)));
return (val & 0x03FFU);
}
/* Free ADC module */
void rda_ccfg_adc_free(void)
{
unsigned short val = 0U;
rd_rf_usb_reg(0xA3, &val, 0); /* adc disable */
wr_rf_usb_reg(0xA3, (val & ~(0x01U << 3)), 0);
//rd_rf_usb_reg(0xD8, &val, 0); /* clk 6p5m disable */
//wr_rf_usb_reg(0xD8, (val & ~(0x01U << 15)), 0);
rd_rf_usb_reg(0xB7, &val, 0); /* clk 26m disable */
wr_rf_usb_reg(0xB7, (val & ~(0x01U << 14)), 0);
}
/* Get abort flag */
int rda_ccfg_abort_flag(void)
{
int ret = 0;
if(0x00UL != (RDA_GPIO->PCCTRL & (0x01UL << 31))) {
ret = 1;
}
return ret;
}
#if RDA5991H_HW_VER >= 2
/* Set wdt en */
void rda_ccfg_wdt_en(void)
{
unsigned short val = 0U;
rd_rf_usb_reg(0xC8, &val, 0);
wr_rf_usb_reg(0xC8, (val | (0x01U << 13)), 0);
}
#endif /* RDA5991H_HW_VER */
unsigned short rf_reg_read(unsigned short addr)
{
unsigned short val = 0U;
if(addr <= 0x1FF) {
if((((addr & 0xFFU) >= 0xA0) && ((addr & 0xFFU) <= 0xDF)) ||
(addr == 0x30U) || (addr == 0x34U) || (addr == 0x35U)) { /* PMU & RF_30H/34H/35H */
rd_rf_usb_reg((unsigned char)(addr & 0xFFU), &val, 0);
} else { /* RF */
char isrun = 0;
rd_rf_usb_reg(0x30U, &val, 0);
isrun = (val & 0x01U) ? 1 : 0;
if(isrun) {
wr_rf_usb_reg(0x02U, (0x5000U | addr), 0);
rd_rf_usb_reg(0x34U, &val, 0);
} else {
if(addr & (0x01U << 8)) {
wr_rf_usb_reg(0x3FU, 1, 0);
}
rd_rf_usb_reg((unsigned char)(addr & 0xFFU), &val, 0);
if(addr & (0x01U << 8)) {
wr_rf_usb_reg(0x3FU, 0, 0);
}
}
}
}
return val;
}
void rf_reg_write(unsigned short addr, unsigned short val)
{
if(addr <= 0x1FF) {
if((((addr & 0xFFU) >= 0xA0) && ((addr & 0xFFU) <= 0xDF)) ||
(addr == 0x30U) || (addr == 0x34U) || (addr == 0x35U)) { /* PMU & RF_30H/34H/35H */
wr_rf_usb_reg((unsigned char)(addr & 0xFFU), val, 0);
} else { /* RF */
char isrun = 0;
rd_rf_usb_reg(0x30U, &val, 0);
isrun = (val & 0x01U) ? 1 : 0;
if(isrun) {
wr_rf_usb_reg(0x32U, val, 0);
wr_rf_usb_reg(0x02U, (0x4000U | addr), 0);
} else {
if(addr & (0x01U << 8)) {
wr_rf_usb_reg(0x3FU, 1, 0);
}
wr_rf_usb_reg((unsigned char)(addr & 0xFFU), val, 0);
if(addr & (0x01U << 8)) {
wr_rf_usb_reg(0x3FU, 0, 0);
}
}
}
}
}
/* Get chip hw version */
int rda_ccfg_hwver(void)
{
if(0 == ChipHwVersion) {
ChipHwVersion = (int)((RDA_GPIO->REVID >> 16) & 0xFFUL) + 1;
}
return ChipHwVersion;
}

109
Living_SDK/platform/mcu/rda5981x/hal/rda_trng_api.c Normal file
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#include "rda_dma.h"
#include "hal/soc/soc.h"
#include "rda5981.h"
#ifdef RDA_HW_ACCELERATE_ENABLE
#include <string.h>
//#include "RDA5991H.h"
//#include "wait_api.h"
/* TRNG CTRL DESC. */
// ctrl, default value 0xC
#define TRNG_EN (1<<0)
#define TRNG_CONT_MODE (1<<1)
#define TRNG_ONCE_MODE (0<<1)
#define TRNG_START_EN (1<<2)
#define TRNG_ON_FLY_EN (1<<3)
#define TRNG_ON_FLY_DISABLE (0<<3)
#define TRNG_SRC_OPEN (1<<4)
#define TRNG_TEST_EN (1<<5)
#define TRNG_DATA_MASK_EN (1<<6)
// mask, default value 0x0
#define TRNG_SRC_MASK (0xff<<16)
#define RDA_TRNG_CGEN_ENABLE() do { \
RDA_DMACFG->dma_func_ctrl |= (1 << 30); \
} while(0)
#define RDA_TRNG_CGEN_DISABLE() do { \
RDA_DMACFG->dma_func_ctrl &= ~(1 << 30); \
} while(0)
/* a very simple delay */
static void rda_trng_simple_delay(int n)
{
int i, j;
for (i=0;i<n;i++)
for (j=0;j<1000;j++)
asm volatile("");
}
void rda_trng_simple_delay(int n) __attribute__ ((noinline));
int rda_trng_generator( unsigned char *output, uint32_t output_len )
{
uint32_t idx = 0;
uint32_t d0;
uint8_t *temp_buf = (uint8_t *)malloc(output_len + 8);
if(NULL ==temp_buf) return (-1);
RDA_SCU_CLK_GATE0_ENABLE();
RDA_TRNG_CGEN_ENABLE();
#ifdef GEN_TRNG_CONTINUOUSLY
uint32_t d1, ret;
flag_0:
RDA_DMACFG->trng_ctrl = TRNG_SRC_MASK | TRNG_EN | TRNG_CONT_MODE | TRNG_START_EN \
| TRNG_ON_FLY_EN | TRNG_SRC_OPEN;//0xff001f;
while (1) {
ret = RDA_DMACFG->dma_int_out;
if(ret&TRNG_ON_FLY_TEST_FAIL) {
RDA_DMACFG->dma_int_out |= TRNG_ON_FLY_TEST_FAIL ;
goto flag_0;
}
if(ret&TRNG_START_TEST_FAIL) {
RDA_DMACFG->dma_int_out |= TRNG_START_TEST_FAIL ;
goto flag_0;
}
if(ret&TRNG_DATA_READY) {
d0 = RDA_DMACFG->trng_data0;
d1 = RDA_DMACFG->trng_data1;
RDA_DMACFG->dma_int_out |= TRNG_DATA_READY ;
PUT_UINT32_BE(d0, temp_buf, 4*idx);
idx++;
PUT_UINT32_BE(d1, temp_buf, 4*idx);
idx++;
if(output_len <= 4*idx) break;
goto flag_0;
}
}
#else
RDA_DMACFG->trng_ctrl = TRNG_SRC_MASK | TRNG_EN | TRNG_ONCE_MODE | TRNG_SRC_OPEN\
| TRNG_ON_FLY_DISABLE; //0x00ff0011;
while(1) {
rda_trng_simple_delay(5);
d0 = RDA_DMACFG->prng_data;
PUT_UINT32_BE(d0, temp_buf, 4*idx);
idx++;
if(output_len <= 4*idx) break;
}
#endif
RDA_TRNG_CGEN_DISABLE();
RDA_SCU_CLK_GATE0_DISABLE();
memcpy(output, temp_buf, output_len);
if(temp_buf) {
free(temp_buf);
}
return (0);
}
#endif /* RDA_HW_ACCELERATE_ENABLE */

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#include <stdio.h>
#include <stdint.h>
#include "hal/soc/rtc.h"
#include "rda5981.h"
#define rFREE_TIMER_INITVAL (RDA_SCU->FTMRINITVAL)
#define rFREE_TIMER_PRESCALE (RDA_SCU->FTMRPREVAL)
#define rFREE_TIMER_TIMESTAMP (RDA_SCU->FTMRTS)
#define rRDA_POWER_CONTROL (RDA_SCU->PWRCTRL)
#define rTIMER1_CONTROL (RDA_TIM1->TCTRL)
#define rTIMER1_INTCLR (RDA_TIM1->INTCLR)
#define FREE_TIMER_INIT_VAL (0xFFFFFFFFUL)
#define US_TIMER_HZ (1000000)
rtc_time_t rtc_time = {0, 0, 0, 1, 1, 1, 0};
static uint32_t sec_suppliment = 0;
void free_ticker_irq_handle()
{
uint32_t delta,sec,min,hr,weekday,date,month,year;
delta = 0xFFFFFFFF;
sec = ((delta+sec_suppliment)/32768);
sec_suppliment = ((delta+sec_suppliment)%32768);
min = sec/60;
min += (rtc_time.sec + sec%60)/60;
rtc_time.sec = (rtc_time.sec + sec%60)%60;
hr = min/60;
hr += (rtc_time.min + min%60)/60;
rtc_time.min = (rtc_time.min + min%60)%60;
date = hr/24;
date += (rtc_time.hr + hr%24)/24;
rtc_time.hr = (rtc_time.hr + hr%24)%24;
month = (rtc_time.date + date)/32;
rtc_time.date = (rtc_time.date + date)%32;
if(rtc_time.date == 0)
rtc_time.date = 1;
year = (rtc_time.month + month)/13;
rtc_time.month = (rtc_time.month + month)%13;
if(rtc_time.month == 0)
rtc_time.month = 1;
rtc_time.year = (rtc_time.year + year)%100;
rtc_time.weekday = (rtc_time.weekday + date)%8;
if(rtc_time.weekday == 0)
rtc_time.weekday = 1;
return;
}
int32_t hal_rtc_init(rtc_dev_t *rtc)
{
rda_ccfg_aontmr_cksrc(1);
/* Enable apb timer clock */
RDA_SCU->CLKGATE1 |= (0x01UL << 3);
/* Set free timer power */
rda_ccfg_aontmr();
/* Delay 300us at least */
{
unsigned int idx = (SystemCoreClock / US_TIMER_HZ / 4UL) * 300UL;
unsigned int regval = 0U;
while (idx--) {
regval += rFREE_TIMER_TIMESTAMP;
}
}
/* Set free timer write_en */
rRDA_POWER_CONTROL |= (uint32_t)(0x01UL << 8);
rFREE_TIMER_INITVAL = FREE_TIMER_INIT_VAL;
/* Enable int */
rRDA_POWER_CONTROL |= (0x01UL << 18);
/* Unmask int */
rTIMER1_CONTROL &= ~(0x01UL << 3);
/* Set free timer prescale */
rFREE_TIMER_PRESCALE = 0U;
/* Enable free timer */
rRDA_POWER_CONTROL |= (uint32_t)(0x01UL << 17);
/* Clr free timer write_en */
rRDA_POWER_CONTROL &= (~(uint32_t)(1 << 8));
sec_suppliment = 0;
rda_timer_irq_set();
}
int32_t hal_rtc_get_time(rtc_dev_t *rtc, rtc_time_t *time)
{
uint32_t delta,sec,min,hr,weekday,date,month,year;
delta = rFREE_TIMER_TIMESTAMP;
RDA_SCU->PWRCTRL |= (0x01UL << 27); // clear timestamp
__DSB();
while (RDA_SCU->PWRCTRL & (0x01UL << 27));
sec = ((delta+sec_suppliment)/32768);
sec_suppliment = ((delta+sec_suppliment)%32768);
min = sec/60;
min += (rtc_time.sec + sec%60)/60;
rtc_time.sec = (rtc_time.sec + sec%60)%60;
hr = min/60;
hr += (rtc_time.min + min%60)/60;
rtc_time.min = (rtc_time.min + min%60)%60;
date = hr/24;
date += (rtc_time.hr + hr%24)/24;
rtc_time.hr = (rtc_time.hr + hr%24)%24;
month = (rtc_time.date + date)/32;
rtc_time.date = (rtc_time.date + date)%32;
if(rtc_time.date == 0)
rtc_time.date = 1;
year = (rtc_time.month + month)/13;
rtc_time.month = (rtc_time.month + month)%13;
if(rtc_time.month == 0)
rtc_time.month = 1;
rtc_time.year = (rtc_time.year + year)%100;
rtc_time.weekday = (rtc_time.weekday + date)%8;
if(rtc_time.weekday == 0)
rtc_time.weekday = 1;
memcpy(time, &rtc_time, sizeof(rtc_time_t));
}
int32_t hal_rtc_set_time(rtc_dev_t *rtc, const rtc_time_t *time)
{
RDA_SCU->PWRCTRL |= (0x01UL << 27); // clear timestamp
__DSB();
while (RDA_SCU->PWRCTRL & (0x01UL << 27));
sec_suppliment = 0;
memcpy(&rtc_time, time, sizeof(rtc_time_t));
}
int32_t hal_rtc_finalize(rtc_dev_t *rtc)
{
/* Set free timer write_en */
rRDA_POWER_CONTROL |= (uint32_t)(0x01UL << 8);
/* Disnable int */
rRDA_POWER_CONTROL &= ~(0x01UL << 18);
/* mask int */
rTIMER1_CONTROL |= (0x01UL << 3);
/* Disable free timer */
rRDA_POWER_CONTROL &= ~(0x01UL << 17);
/* Clr free timer write_en */
rRDA_POWER_CONTROL &= (~(uint32_t)(1 << 8));
sec_suppliment = 0;
return 0;
}

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#include "hal/soc/soc.h"
#include "spi_api.h"
#include "rda5981x_pinconfig.h"
#define SPI_NUM 1
static spi_t spi_obj[SPI_NUM];
int32_t hal_spi_init(spi_dev_t *spi)
{
if (spi->port >= SPI_NUM)
return -1;
spi->priv = &spi_obj[spi->port];
spi_init(spi->priv, RDA_SPI0_MOSI, RDA_SPI0_MISO, RDA_SPI0_CLK, RDA_SPI0_CS);
spi_format(spi->priv, 8, spi->config.mode, 0);
spi_frequency(spi->priv, spi->config.freq);
return 0;
}
int32_t hal_spi_send(spi_dev_t *spi, const uint8_t *data, uint16_t size, uint32_t timeout)
{
if (NULL == data)
return -1;
while (size > 0) {
spi_master_write(spi->priv, *data);
data++;
size--;
}
return 0;
}
int32_t hal_spi_recv(spi_dev_t *spi, uint8_t *data, uint16_t size, uint32_t timeout)
{
uint8_t val;
if (NULL == data)
return -1;
while (size > 0) {
val = (uint8_t)spi_master_write(spi->priv, 0xFF);
*data = val;
data++;
size--;
}
return 0;
}
int32_t hal_spi_send_recv(spi_dev_t *spi, uint8_t *tx_data, uint8_t *rx_data,
uint16_t size, uint32_t timeout)
{
#if 0
uint8_t val;
uint16_t rx_size = size, tx_size = size;
if ((NULL == tx_data) || (NULL == rx_data))
return -1;
while (tx_size > 0) {
val = (uint8_t)spi_master_write(spi->priv, *tx_data);
tx_data++;
tx_size--;
if (rx_size > 0) {
*rx_data = val;
rx_data++;
rx_size--;
}
}
while (rx_size > 0) {
val = val = (uint8_t)spi_master_write(spi->priv, 0xFF);
*rx_data = val;
rx_data++;
rx_size--;
}
#endif
return 0;
}
int32_t hal_spi_finalize(spi_dev_t *spi)
{
return 0;
}

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/**************************************************************************//**
* @file system_rda5981.c
******************************************************************************/
#include <stdint.h>
#include "rda5981.h"
/** @addtogroup RDA5981_System
* @{
*/
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*--------------------- Clock Configuration ----------------------------------
//
// <e> Clock Configuration
// <h> Clock Gating Control 0 Register (CLKGATE0)
// <o1.0> DEEPSLEEP: Deep sleep mode enable
// <o1.15> EXIF: EXIF clock gating enable
// </h>
//
// <h> Clock Gating Control 1 Register (CLKGATE1)
// <o2.0> GPIO: GPIO clock gating enable
// <o2.1> I2S: I2S clock gating enable
// <o2.2> PWM: PWM clock gating enable
// <o2.3> TIMER: APB Timer clock gating enable
// <o2.4> PSRAM_PCLK: PSRAM PCLK clock gating enable
// <o2.5> SDMMC: SDMMC clock gating enable
// <o2.6> I2C: I2C clock gating enable
// <o2.4> PSRAM_HCLK: PSRAM HCLK clock gating enable
// </h>
//
// <h> Clock Gating Control 2 Register (CLKGATE2)
// <o3.16> I2SIN: I2SIN clock gating enable
// <o3.17> I2SOUT: I2SOUT clock gating enable
// <o3.18> GSPI: General SPI clock gating enable
// <o3.19> RFSPI: RF SPI clock gating enable
// <o3.31> SLOWFLASH: Slow flash clock gating enable
// </h>
//
// <h> Clock Gating Control 3 Register (CLKGATE3)
// <o4.30> DOZEMODE: Doze mode enable
// <o4.31> CLKMODE: Clock mode enable
// </h>
//
// <h> Clock Core Configure Register (CORECFG)
// <o5.11> HCLK: HCLK config
// <o5.12..13> CPUCLK: CPU Clock config
// </h>
//
// </e>
*/
/** @addtogroup RDA5981_System_Defines RDA5981 System Defines
@{
*/
/*
//-------- <<< end of configuration section >>> ------------------------------
*/
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define RDA_SYS_CLK_FREQUENCY_40M ( 40000000UL)
#define RDA_SYS_CLK_FREQUENCY_80M ( 80000000UL)
#define RDA_SYS_CLK_FREQUENCY_160M (160000000UL)
#define RDA_BUS_CLK_FREQUENCY_40M ( 40000000UL)
#define RDA_BUS_CLK_FREQUENCY_80M ( 80000000UL)
/**
* @}
*/
/** @addtogroup RDA5981_System_Public_Variables RDA5981 System Public Variables
@{
*/
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
//uint32_t SystemCoreClock = RDA_SYS_CLK_FREQUENCY_160M; /*!< System Clock Frequency (Core Clock)*/
//uint32_t AHBBusClock = RDA_BUS_CLK_FREQUENCY_80M; /*!< AHB Bus Clock Frequency (Bus Clock)*/
uint32_t SystemCoreClock = RDA_SYS_CLK_FREQUENCY_40M; /*!< System Clock Frequency (Core Clock)*/
uint32_t AHBBusClock = RDA_BUS_CLK_FREQUENCY_40M; /*!< AHB Bus Clock Frequency (Bus Clock)*/
/**
* @}
*/
/** @addtogroup RDA5981_System_Public_Functions RDA5981 System Public Functions
@{
*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate (void) /* Get Core/Bus Clock Frequency */
{
uint32_t val = RDA_SCU->CORECFG;
/* Determine clock frequency according to SCU core config register values */
switch ((val >> 12) & 0x03UL) {
case 0:
SystemCoreClock = RDA_SYS_CLK_FREQUENCY_40M;
break;
case 1:
SystemCoreClock = RDA_SYS_CLK_FREQUENCY_80M;
break;
case 2:
case 3:
SystemCoreClock = RDA_SYS_CLK_FREQUENCY_160M;
break;
}
/* Determine clock frequency according to SCU core config register values */
switch ((val >> 11) & 0x01UL) {
case 0:
AHBBusClock = RDA_BUS_CLK_FREQUENCY_40M;
break;
case 1:
AHBBusClock = RDA_BUS_CLK_FREQUENCY_80M;
break;
}
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
SCB->VTOR = RDA_CODE_BASE; /* vector table in flash */
NVIC_SetPriorityGrouping(0x06); /* 1 bit for pre-emption pri */
__enable_irq();
}
/**
* @}
*/
/**
* @}
*/

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#include <stdint.h>
#include <stddef.h>
#include "hal/soc/timer.h"
#include "rda5981.h"
#define TICKER_TIMER0 (RDA_TIM0)
#define TICKER_TIMER1 (RDA_TIM1)
#define TIMER0_CONTROL_ENABLE (0x01)
#define TIMER0_CONTROL_MODE (0x02)
#define TIMER0_CONTROL_INT_MSK (0x04)
#define TIMER1_CONTROL_ENABLE (0x20)
#define TIMER1_CONTROL_MODE (0x40)
#define TIMER1_CONTROL_INT_MSK (0x80)
#define US_TIMER_HZ (1000000)
hal_timer_cb_t timer_cb = NULL;
void *arg = NULL;
timer_config_t timer0_config;
timer_config_t timer1_config;
void ticker0_irq_handler()
{
if(timer0_config.reload_mode == TIMER_RELOAD_AUTO){
/* Disable timer */
TICKER_TIMER0->TCTRL &= (~TIMER0_CONTROL_ENABLE);
/* Enable timer */
TICKER_TIMER0->TCTRL |= (TIMER0_CONTROL_ENABLE);
}
timer0_config.cb(timer0_config.arg);
}
void ticker1_irq_handler()
{
if(timer1_config.reload_mode == TIMER_RELOAD_AUTO){
/* Disable timer */
TICKER_TIMER1->TCTRL &= (~TIMER1_CONTROL_ENABLE);
/* Delay 125us at least */
{
unsigned int idx = (SystemCoreClock / US_TIMER_HZ / 4UL) * 125UL;
volatile unsigned int regval = 0U;
while (idx--)
regval ++;
}
/* Enable timer */
TICKER_TIMER1->TCTRL |= (TIMER1_CONTROL_ENABLE);
}
timer1_config.cb(timer1_config.arg);
}
int32_t hal_timer_init(timer_dev_t *tim)
{
/* Enable apb timer clock */
RDA_SCU->CLKGATE1 |= (0x01UL << 3);
if(tim->port == 0){
/* Set timer0 mode */
TICKER_TIMER0->TCTRL |= (TIMER0_CONTROL_MODE);
/* mask timer0, disable an overflow int */
TICKER_TIMER0->TCTRL |= (TIMER0_CONTROL_INT_MSK);
}else if(tim->port == 1){
/* Set timer1 mode */
TICKER_TIMER1->TCTRL |= (TIMER1_CONTROL_MODE);
/* mask timer1, disable an overflow int */
TICKER_TIMER1->TCTRL |= (TIMER1_CONTROL_INT_MSK);
}
rda_timer_irq_set();
return 0;
}
int32_t hal_timer_start(timer_dev_t *tim)
{
if(tim->port == 0){
/* Set period mode */
if(tim->config.reload_mode == TIMER_RELOAD_MANU)
RDA_GPIO->REVID &= ~(0x01UL << 25);
else
RDA_GPIO->REVID |= (0x01UL << 25);
/* Set timer0 count */
TICKER_TIMER0->LDCNT = tim->config.period * 40 * 1000;
/* Enable timer0 */
TICKER_TIMER0->TCTRL |= (TIMER0_CONTROL_ENABLE);
/* Unmask timer0, enable an overflow int */
TICKER_TIMER0->TCTRL &= (~(TIMER0_CONTROL_INT_MSK));
timer0_config = tim->config;
}else if(tim->port == 1){
/* Set period mode */
if(tim->config.reload_mode == TIMER_RELOAD_MANU)
RDA_GPIO->REVID &= ~(0x01UL << 26);
else
RDA_GPIO->REVID |= (0x01UL << 26);
/* Set timer1 count */
if(timer1_config.reload_mode == TIMER_RELOAD_AUTO)
TICKER_TIMER1->LDCNT = (tim->config.period * 32768)/1000 - 4;
else
TICKER_TIMER1->LDCNT = (tim->config.period * 32768)/1000;
/* Enable timer1 */
TICKER_TIMER1->TCTRL |= (TIMER1_CONTROL_ENABLE);
/* Unmask timer, enable an overflow int */
TICKER_TIMER1->TCTRL &= (~(TIMER1_CONTROL_INT_MSK));
timer1_config = tim->config;
}
return 0;
}
void hal_timer_stop(timer_dev_t *tim)
{
if(tim->port == 0){
/* Disable timer0 */
TICKER_TIMER0->TCTRL &= (~TIMER0_CONTROL_ENABLE);
/* mask timer0, disable an overflow int */
TICKER_TIMER0->TCTRL |= (TIMER0_CONTROL_INT_MSK);
}if(tim->port == 1){
/* Disable timer1 */
TICKER_TIMER1->TCTRL &= (~TIMER1_CONTROL_ENABLE);
/* mask timer1, disable an overflow int */
TICKER_TIMER1->TCTRL |= (TIMER1_CONTROL_INT_MSK);
}
return;
}
int32_t hal_timer_finalize(timer_dev_t *tim)
{
if(tim->port == 0){
/* Disable timer0 */
TICKER_TIMER0->TCTRL &= (~TIMER0_CONTROL_ENABLE);
/* mask timer0, disable an overflow int */
TICKER_TIMER0->TCTRL |= (TIMER0_CONTROL_INT_MSK);
}if(tim->port == 1){
/* Disable timer1 */
TICKER_TIMER1->TCTRL &= (~TIMER1_CONTROL_ENABLE);
/* mask timer1, disable an overflow int */
TICKER_TIMER1->TCTRL |= (TIMER1_CONTROL_INT_MSK);
}
return 0;
}

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#include "rda5981.h"
#define rTIMER_INTSTATE (RDA_TIMINTST->INTST)
#define RDA_TIMER_IRQn (TIMER_IRQn)
#define TIMER0_CONTROL_ENABLE (0x01)
extern void ticker0_irq_handler();
extern void ticker1_irq_handler();
extern void free_ticker_irq_handle();
static void rda_timer_isr(void)
{
uint32_t int_status = rTIMER_INTSTATE & 0x000FUL;
if (int_status & (0x01UL << 2)){
volatile uint32_t us_ticker_clrInt = RDA_TIM0->INTCLR;
ticker0_irq_handler();
}
if (int_status & (0x01UL << 3)){
volatile uint32_t lp_ticker_clrInt = RDA_TIM1->INTCLR;
ticker1_irq_handler();
}
if(int_status & (0x01UL << 1)){
RDA_SCU->PWRCTRL |= (0x01UL << 28); // clear int
__DSB();
while (RDA_SCU->PWRCTRL & (0x01UL << 28));
RDA_SCU->PWRCTRL |= (0x01UL << 27); // clear timestamp
__DSB();
while (RDA_SCU->PWRCTRL & (0x01UL << 27));
free_ticker_irq_handle();
}
}
void rda_timer_irq_set(void)
{
NVIC_SetVector(RDA_TIMER_IRQn, (uint32_t)rda_timer_isr);
NVIC_SetPriority(RDA_TIMER_IRQn, 0x1FUL);
NVIC_EnableIRQ(RDA_TIMER_IRQn);
}

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/*
* Hardware entropy collector for the UNO_91H, using RDA's TRNG
*
* Copyright (C) 2006-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
#include "trng_api.h"
#define rRNG_CLKGATE (RDA_SCU->CLKGATE0)
#define rRNG_CLKGEN (RDA_DMACFG->dma_func_ctrl)
#define rRNG_INTSTATE (RDA_DMACFG->dma_int_out)
#define rTRNG_CTRL (RDA_RNG->TCTRL)
#define rTRNG_DATA0 (RDA_RNG->TD0)
#define rTRNG_DATA1 (RDA_RNG->TD1)
#define rPRNG_DATA (RDA_RNG->PD)
/** trng_get_byte
* @brief Get one byte of entropy from the RNG, assuming it is up and running.
* @param obj TRNG obj
* @param pointer to the hardware generated random byte.
*/
static void trng_get_byte(trng_t *obj, unsigned char *byte )
{
if(0U == obj->byte_idx) {
int n;
/* Delay for PRNG data ready */
for(n = 0; n < 4096; n++);
obj->trng_data0 = rPRNG_DATA;
}
*byte = (unsigned char)((obj->trng_data0 >> (obj->byte_idx << 3)) & 0x00FFUL);
obj->byte_idx++;
obj->byte_idx &= ~0xFCU;
}
void trng_init(trng_t *obj)
{
uint32_t regval;
obj->dma_clk_flag = (uint8_t)((rRNG_CLKGATE >> 18) & 0x01U);
obj->byte_idx = 0;
if(0x00U == obj->dma_clk_flag) {
int j;
/* DMA Peripheral clock enable */
rRNG_CLKGATE |= (0x01UL << 18);
/* dealy after clk en */
for(j = 0; j < 4; j++);
}
/* RNG Engine clock enable */
rRNG_CLKGEN |= (0x01UL << 30);
/* Set TRNG enable bit, once mode */
regval = rTRNG_CTRL | ((0x01UL << 0) | (0x01UL << 4) | (0xFFUL << 16));
rTRNG_CTRL = regval & ~((0x01UL << 1) | (0x01UL << 2) | (0x01UL << 3));
}
void trng_free(trng_t *obj)
{
/* Clear TRNG enable bit */
rTRNG_CTRL = 0x00UL;
/* RNG Engine clock disable */
rRNG_CLKGEN &= ~(0x01UL << 30);
if(0x00U == obj->dma_clk_flag) {
/* DMA Peripheral clock disable */
rRNG_CLKGATE &= ~(0x01UL << 18);
}
}
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length)
{
int ret = 0;
/* Get Random byte */
for( uint32_t i = 0; i < length; i++ ){
trng_get_byte(obj, output + i );
}
return ret;
}
int rda_get_random_bytes(unsigned char *output, size_t len)
{
trng_t trng_obj;
trng_init(&trng_obj);
int ret = trng_get_bytes(&trng_obj, output, len);
trng_free(&trng_obj);
return ret;
}

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#include "hal/soc/soc.h"
#include "serial_api.h"
#include "rda5981x_pinconfig.h"
#include "aos/kernel.h"
#include "rda_def.h"
#include "rda_sys_wrapper.h"
#include "k_dftdbg_config.h"
#define UART_NUM 2
#define DEFAULT_UART_RECV_BUF_SIZE 512
static serial_t serial_obj[UART_NUM];
static uint8_t is_inited[UART_NUM] = {0};
r_void *uart_recv_buf_queue[UART_NUM] = {NULL, NULL};
static void console_irq_handler(uint32_t index, SerialIrq event);
/*---------------------------------------------------------------------------*/
#define HFUART_RX_BUFFER_SIZE (1024)
struct ringbuf {
uint8_t *data;
uint16_t mask;
uint16_t put_ptr, get_ptr;
};
typedef struct {
char *rxbuf;
struct ringbuf uart_rx_buf;
uint8_t b_wait_rx;
aos_sem_t rx_wait_event;
} uart_cfg_t;
static uart_cfg_t serial_cfg[UART_NUM];
static void ringbuf_init(struct ringbuf *r, uint8_t *dataptr, uint16_t size)
{
r->data = dataptr;
r->mask = size;
r->put_ptr = 0;
r->get_ptr = 0;
}
static int ringbuf_put(struct ringbuf *r, uint8_t c)
{
if(((r->put_ptr+1)%r->mask)== r->get_ptr ) {
return 0;
}
r->data[r->put_ptr] = c;
r->put_ptr = (r->put_ptr + 1) % r->mask;
if(((r->put_ptr+1)%r->mask)== r->get_ptr )
return 2;
return 1;
}
static int ringbuf_get(struct ringbuf *r)
{
uint8_t c;
if(r->put_ptr != r->get_ptr) {
c = r->data[r->get_ptr];
r->get_ptr +=1;
if(r->get_ptr>=r->mask)
r->get_ptr = r->get_ptr-r->mask;
return c;
} else {
return -1;
}
}
static int ringbuf_gets(struct ringbuf *r,uint8_t *data,int size)
{
int cnt=0;
uint8_t *src=r->data;
while((r->put_ptr != r->get_ptr)&&(cnt<size)){
data[cnt++] = src[r->get_ptr++];
if(r->get_ptr>=r->mask)
r->get_ptr = 0;
}
return cnt;
}
static void uart_rx_irq_handler(uint32_t id, SerialIrq event)
{
int ret, fc=0;
serial_t * p_uart=NULL;
uart_cfg_t *uart_cfg = NULL;
if(1 == id){
p_uart = &serial_obj[id];
uart_cfg = &serial_cfg[id];
}
else
return;
if(p_uart==NULL)
{
return;
}
if(RxIrq == event)
{
while(serial_readable(p_uart))
{
int c = serial_getc(p_uart);
ret = ringbuf_put(&uart_cfg->uart_rx_buf,c);
if(ret!=1)//uart cache is full
{
}
if(uart_cfg->b_wait_rx)
{
aos_sem_signal(&uart_cfg->rx_wait_event);
uart_cfg->b_wait_rx = 0;
}
}
}
}
uart_dev_t uart_0 = {
0,
{921600, DATA_WIDTH_8BIT, NO_PARITY, STOP_BITS_1, FLOW_CONTROL_DISABLED},
NULL,
};
int32_t hal_uart_init(uart_dev_t *uart)
{
if (uart->port >= UART_NUM)
return -1;
if ((0 == uart->port) && (FLOW_CONTROL_DISABLED != uart->config.flow_control))
return -1;
uart->priv = &serial_obj[uart->port];
if (0 == uart->port) {
serial_init(uart->priv, RDA_UART0_TXD, RDA_UART0_RXD);
uart_recv_buf_queue[0] = rda_queue_create(DEFAULT_UART_RECV_BUF_SIZE, sizeof(unsigned char));
} else {
serial_init(uart->priv, RDA_UART1_TXD_2, RDA_UART1_RXD_2);
uart_recv_buf_queue[1] = rda_queue_create(DEFAULT_UART_RECV_BUF_SIZE, sizeof(unsigned char));
}
serial_baud(uart->priv, uart->config.baud_rate);
serial_format(uart->priv, (uart->config.data_width + 5), uart->config.parity, (uart->config.stop_bits + 1));
if(1 == uart->port)
{
aos_sem_new(&serial_cfg[uart->port].rx_wait_event, 0);
serial_cfg[uart->port].rxbuf = (char*)aos_malloc(HFUART_RX_BUFFER_SIZE);
ringbuf_init(&serial_cfg[uart->port].uart_rx_buf, (uint8_t*)serial_cfg[uart->port].rxbuf, HFUART_RX_BUFFER_SIZE);
serial_irq_handler(uart->priv, uart_rx_irq_handler, (uint32_t)uart->port);
serial_irq_set(uart->priv, RxIrq, 1);
serial_irq_set(uart->priv, TxIrq, 0);
} else {
#if (RHINO_CONFIG_PANIC_CLI == 0)
serial_irq_handler(uart->priv, console_irq_handler, (uint32_t)1);
serial_irq_set(uart->priv, RxIrq, 1);
#endif
}
if (FLOW_CONTROL_CTS_RTS == uart->config.flow_control) {
serial_set_flow_control(uart->priv, FLOW_CONTROL_CTS_RTS, RDA_UART1_RTS, RDA_UART1_CTS);
}
is_inited[uart->port] = 1;
return 0;
}
int32_t hal_uart_send(uart_dev_t *uart, const void *data, uint32_t size, uint32_t timeout)
{
if (0 == is_inited[uart->port]) {
/* To avoid opening the UART0 automatically when testing power consumption,
the user needs to explicitly initialize the UART0 .
The debug UART does not print when the UART is not initialized */
#if 0
hal_uart_init(uart);
is_inited[uart->port] = 1;
#endif
return 0;
}
uint8_t *send_data = (char *)data;
while (size > 0) {
serial_putc(uart->priv, (int)*send_data);
send_data++;
size--;
}
return 0;
}
int32_t hal_uart_recv(uart_dev_t *uart, void *data, uint32_t expect_size, uint32_t timeout)
{
hal_uart_recv_II(uart, data, expect_size, NULL, timeout);
return 0;
}
int32_t hal_uart_recv_II(uart_dev_t *uart, void *data, uint32_t expect_size,
uint32_t *recv_size, uint32_t timeout)
{
uint32_t rx_count = 0;
int ret;
if (0 == is_inited[uart->port]) {
/* To avoid opening the UART0 automatically when testing power consumption,
the user needs to explicitly initialize the UART0 .
The debug UART does not print when the UART is not initialized */
#if 0
hal_uart_init(uart);
is_inited[uart->port] = 1;
#endif
return 0;
}
if(0 == uart->port){
uint8_t *recv_data = (char *)data;
uint8_t queue_data;
if(uart_recv_buf_queue[uart->port] == NULL){
mbed_error_printf("uart_%d_recv_buf_queue create failed\r\n",uart->port);
if(recv_size != NULL)
*recv_size = 0;
return;
}
#if (RHINO_CONFIG_PANIC_CLI == 0)
for(rx_count = 0; rx_count < expect_size; rx_count++){
ret = rda_queue_recv(uart_recv_buf_queue[uart->port], &queue_data, RDA_WAIT_FOREVER);
if(!ret) {
*recv_data ++ = queue_data;
} else
break;
}
#else
while (rx_count < expect_size) {
while(serial_readable(&serial_obj[0])) {
recv_data[rx_count++] = serial_getc(&serial_obj[0]);
if(rx_count == expect_size)
break;
}
if(rx_count == expect_size)
break;
}
#endif
if(rx_count != expect_size)
printf("uart recv error:expect=%d recv=%d\r\n",expect_size,rx_count);
if (NULL != recv_size)
*recv_size = rx_count;
}
else
{
uint8_t *p_data = (uint8_t*)data;
int ch, recvnum=0;
uart_cfg_t *uart_cfg = &serial_cfg[uart->port];
if((ch=ringbuf_get(&uart_cfg->uart_rx_buf))==-1){
uart_cfg->b_wait_rx = 1;
aos_sem_wait(&uart_cfg->rx_wait_event, timeout);
uart_cfg->b_wait_rx = 0;
if((ch=ringbuf_get(&uart_cfg->uart_rx_buf))==-1){
if(recv_size != NULL)
*recv_size = recvnum;
return 0;
}
}
recvnum = 1;
*p_data = (uint8_t)ch;
p_data++;
while(recvnum<(int)expect_size)
{
if((ch=ringbuf_get(&uart_cfg->uart_rx_buf))==-1){
uart_cfg->b_wait_rx = 1;
aos_sem_wait(&uart_cfg->rx_wait_event, 20);
uart_cfg->b_wait_rx = 0;
if((ch=ringbuf_get(&uart_cfg->uart_rx_buf))==-1){
if(recv_size != NULL)
*recv_size = recvnum;
return 0;
}
}
recvnum++;
*p_data = (uint8_t)ch;
p_data++;
}
if(recv_size != NULL)
*recv_size = recvnum;
}
return 0;
}
int32_t hal_uart_finalize(uart_dev_t *uart)
{
return 0;
}
static void console_irq_handler(uint32_t index, SerialIrq event){
unsigned char c;
int ret;
if(RxIrq == event){
while(serial_readable(&serial_obj[index])){
c = serial_getc(&serial_obj[index]);
ret = rda_queue_send(uart_recv_buf_queue[index], (r_u32) &c, RDA_NO_WAIT);
if(ret != 0) {
mbed_error_printf("uart_recv_buf_queue full\r\n");
}
}
}
}

63
Living_SDK/platform/mcu/rda5981x/hal/wdg.c Normal file
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#include <sys/errno.h>
#include <stddef.h>
#include "hal/soc/wdg.h"
#include "rda_ccfg_api.h"
#include "rda5981.h"
#include "PeripheralNames.h"
/** WDT HAL macro
*/
#define WDT_EN_BIT (9)
#define WDT_CLR_BIT (10)
#define WDT_TMRCNT_OFST (11)
#define WDT_TMRCNT_WIDTH (4)
/* the timeout only can be set to 1s/2s/3s/4s/5s/6s/7s/8s/9s/10s/11s/12s/13s/14s/15s */
int32_t hal_wdg_init(wdg_dev_t *wdg)
{
uint32_t reg = 0;
uint8_t to = 0;
if(wdg == NULL) {
return -1;
}
RDA_WDT_TypeDef *wdt = NULL;
rda_ccfg_wdt_en();
to = wdg->config.timeout/1000;
if(0x00U != (to & 0xF0U)) {
return EIO;
}
wdt = (RDA_WDT_TypeDef *)WDT_0;
reg = wdt->WDTCFG & ~(((0x01UL << WDT_TMRCNT_WIDTH) - 0x01UL) << WDT_TMRCNT_OFST);
wdt->WDTCFG = reg | (to << WDT_TMRCNT_OFST);
wdt->WDTCFG |= (0x01UL << WDT_EN_BIT);//start wdt
wdg->priv = (void*)wdt;
return 0;
}
void hal_wdg_reload(wdg_dev_t *wdg)
{
if(wdg == NULL) {
return -1;
}
RDA_WDT_TypeDef * wdt = (RDA_WDT_TypeDef *)(wdg->priv);
wdt->WDTCFG |= (0x01UL << WDT_CLR_BIT);
}
int32_t hal_wdg_finalize(wdg_dev_t *wdg)
{
if(wdg == NULL) {
return -1;
}
RDA_WDT_TypeDef * wdt = (RDA_WDT_TypeDef *)(wdg->priv);
wdt->WDTCFG &= ~(0x01UL << WDT_EN_BIT);
return 0;
}

494
Living_SDK/platform/mcu/rda5981x/hal/wifi_port.c Executable file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include "rda59xx_daemon.h"
#include "rda59xx_wifi_include.h"
#include "hal/wifi.h"
#include "lwip/ip4_addr.h"
#include "lwip/inet.h"
typedef enum {
SCAN_NORMAL,
SCAN_ADV
} scan_type_t;
hal_wifi_ip_stat_t ip_stat;
unsigned int filter_backup = 0;
static rda59xx_sta_info sta_info = {0};
static bool sta_try_reconnect = false;
static void handle_connect_fail(void *arg)
{
LOG("%s\r\n", __func__);
aos_msleep(500);
if (sta_try_reconnect) {
rda59xx_sta_connect(&sta_info);
}
// rda59xx_sta_connect will auto retry 4 times, need 25 seconds
// when ap connect first fail, retry reconnect(actual retry 4 times)
// then stop reconnect, to avoid blocking upper applications
sta_try_reconnect = false;
}
void wifi_event_cb(WIFI_EVENT evt, void* info)
{
hal_wifi_module_t *m = hal_wifi_get_default_module();
hal_wifi_ip_stat_t ip_stat;
hal_wifi_ap_info_adv_t ap_info;
rda59xx_bss_info bss_info;
switch (evt) {
case EVENT_STA_GOT_IP: {
#if (WIFI_CONFIG_SUPPORT_LOWPOWER > 0)
m->enter_powersave(m, WIFI_CONFIG_RECEIVE_DTIM);
#endif
rda59xx_sta_get_bss_info(&bss_info);
memcpy(ip_stat.ip, ip4addr_ntoa(&(bss_info.ipaddr)), sizeof(ip_stat.ip));
memcpy(ip_stat.gate, ip4addr_ntoa(&(bss_info.gateway)), sizeof(ip_stat.gate));
memcpy(ip_stat.mask, ip4addr_ntoa(&(bss_info.mask)), sizeof(ip_stat.mask));
memcpy(ip_stat.dns, ip4addr_ntoa(&(bss_info.dns1)), sizeof(ip_stat.dns));
snprintf(ip_stat.mac, 12, "%02x%02x%02x%02x%02x%02x",
bss_info.bssid[0], bss_info.bssid[1], bss_info.bssid[2], bss_info.bssid[3], bss_info.bssid[4], bss_info.bssid[5]);
if (m->ev_cb && m->ev_cb->ip_got) {
m->ev_cb->ip_got(m, &ip_stat, NULL);
}
memcpy(ap_info.bssid, bss_info.bssid, 6);
memcpy(ap_info.ssid, bss_info.ssid, bss_info.ssid_len);
ap_info.channel = bss_info.channel;
ap_info.security = bss_info.secure;
if (m->ev_cb && m->ev_cb->para_chg) {
m->ev_cb->para_chg(m, &ap_info, NULL, 0, NULL);
}
break;
}
case EVENT_STA_CONNECTTED: {
if (m->ev_cb && m->ev_cb->stat_chg) {
m->ev_cb->stat_chg(m, NOTIFY_STATION_UP, NULL);
}
break;
}
case EVENT_STA_DISCONNECTTED: {
if (m->ev_cb && m->ev_cb->stat_chg) {
m->ev_cb->stat_chg(m, NOTIFY_STATION_DOWN, NULL);
}
break;
}
case EVENT_STA_CONNECT_FAIL: {
LOG("%s EVENT_STA_CONNECT_FAIL\r\n", __func__);
if (m->ev_cb && m->ev_cb->connect_fail) {
m->ev_cb->connect_fail(m, 0, NULL);
}
if (sta_try_reconnect) {
aos_schedule_call(handle_connect_fail, NULL);
}
break;
}
default: {
break;
}
}
return;
}
/**
@brief Wifi scan ready
*/
static void scan_done(hal_wifi_module_t *m, scan_type_t t)
{
uint16_t ap_num = 16;
rda59xx_scan_result *ap_records;
int i;
hal_wifi_scan_result_t *result = NULL;
hal_wifi_scan_result_adv_t *result_adv = NULL;
if (t != SCAN_NORMAL && t != SCAN_ADV) return;
ap_num = rda59xx_get_scan_num();
if (ap_num > 16)
ap_num = 16;
ap_records = malloc(ap_num * sizeof(*ap_records));
if (!ap_records)
return;
if (t == SCAN_NORMAL) {
result = malloc(sizeof(hal_wifi_scan_result_t));
if (!result) goto end;
result->ap_num = ap_num;
result->ap_list = malloc(ap_num * sizeof(ap_list_t));
if (!result->ap_list) goto end;
} else {
result_adv = malloc(sizeof(hal_wifi_scan_result_adv_t));
if (!result_adv) goto end;
result_adv->ap_num = ap_num;
result_adv->ap_list = malloc(ap_num * sizeof(ap_list_adv_t));
if (!result_adv->ap_list) goto end;
}
rda59xx_get_scan_result(ap_records, ap_num);
for (i = 0; i < ap_num; i++) {
rda59xx_scan_result *r = ap_records + i;
if (t == SCAN_NORMAL) {
ap_list_t *res = result->ap_list + i;
memcpy(res->ssid, r->SSID, sizeof(res->ssid));
res->ap_power = r->RSSI;
} else {
ap_list_adv_t *res_adv = result_adv->ap_list + i;
memcpy(res_adv->ssid, r->SSID, sizeof(res_adv->ssid));
res_adv->ap_power = r->RSSI;
memcpy(res_adv->bssid, r->BSSID, sizeof(res_adv->bssid));
res_adv->channel = r->channel;
res_adv->security = r->secure_type;
}
}
if (t == SCAN_NORMAL) {
if (m->ev_cb && m->ev_cb->scan_compeleted) {
m->ev_cb->scan_compeleted(m, result, NULL);
}
} else {
if (m->ev_cb && m->ev_cb->scan_adv_compeleted) {
m->ev_cb->scan_adv_compeleted(m, result_adv, NULL);
}
}
end:
if (ap_records)
free(ap_records);
if (result) {
if (result->ap_list)
free(result->ap_list);
free(result);
}
if (result_adv) {
if (result_adv->ap_list)
free(result_adv->ap_list);
free(result_adv);
}
}
static monitor_data_cb_t data_cb = NULL;
static monitor_data_cb_t mngt_data_cb = NULL;
//static monitor_data_cb_t mesh_data_cb = NULL;
typedef enum {
HAL_WIFI_MODE_STATION,
HAL_WIFI_MODE_SOFTAP
} hal_wifi_mode_t;
__WEAK int board_wifi_init_hook(hal_wifi_module_t *m)
{
return 0;
}
static int wifi_init(hal_wifi_module_t *m)
{
static int inited;
if (inited) return 0;
inited = 1;
board_wifi_init_hook(m);
rda59xx_wifi_init();
rda59xx_wifi_set_event_cb(wifi_event_cb);
return 0;
};
static void wifi_get_mac_addr(hal_wifi_module_t *m, uint8_t *mac)
{
rda59xx_get_macaddr(mac, 0);
};
static void wifi_set_mac_addr(hal_wifi_module_t *m, const uint8_t *mac)
{
rda59xx_set_macaddr(mac, 0);
};
static int wifi_start(hal_wifi_module_t *m, hal_wifi_init_type_t *init_para)
{
sta_try_reconnect = true;
memset(&sta_info, 0, sizeof(rda59xx_sta_info));
memcpy(sta_info.ssid, init_para->wifi_ssid, 32+1);
memcpy(sta_info.pw, init_para->wifi_key, 64+1);
if(init_para->dhcp_mode){
sta_info.dhcp = 1;
}else{
sta_info.dhcp = 0;
ip4addr_aton((const char *)(init_para->local_ip_addr), (ip4_addr_t*)&(sta_info.ip));
ip4addr_aton((const char *)(init_para->net_mask), (ip4_addr_t*)&(sta_info.netmask));
ip4addr_aton((const char *)(init_para->gateway_ip_addr), (ip4_addr_t*)&(sta_info.gateway));
}
rda59xx_sta_connect(&sta_info);
return 0;
}
static int wifi_start_adv(hal_wifi_module_t *m,
hal_wifi_init_type_adv_t *init_para_adv)
{
LOG("WiFi HAL %s not implemeted yet!\r\n", __func__);
return 0;
}
static int get_ip_stat(hal_wifi_module_t *m,
hal_wifi_ip_stat_t *out_net_para,
hal_wifi_type_t wifi_type)
{
rda59xx_bss_info bss_info;
unsigned int state = 0;
state = rda59xx_get_module_state();
if ((wifi_type == STATION) && (state & STATE_STA)){
rda59xx_sta_get_bss_info(&bss_info);
strcpy(out_net_para->ip, ip4addr_ntoa(&bss_info.ipaddr));
strcpy(out_net_para->mask, ip4addr_ntoa(&bss_info.mask));
strcpy(out_net_para->gate, ip4addr_ntoa(&bss_info.gateway));
strcpy(out_net_para->dns, ip4addr_ntoa(&bss_info.dns1));
r_u32 broadcastip;
broadcastip = (bss_info.mask&bss_info.ipaddr)|(~bss_info.mask);
strcpy(out_net_para->broadcastip, ip4addr_ntoa(&broadcastip));
snprintf(out_net_para->mac, 12, "%02x%02x%02x%02x%02x%02x",
bss_info.bssid[0], bss_info.bssid[1], bss_info.bssid[2], bss_info.bssid[3], bss_info.bssid[4], bss_info.bssid[5]);
}
return 0;
}
static int get_link_stat(hal_wifi_module_t *m,
hal_wifi_link_stat_t *out_stat)
{
rda59xx_bss_info bss_info;
unsigned int state = 0;
state = rda59xx_get_module_state();
out_stat->is_connected = 0;
if(state & STATE_STA){
rda59xx_sta_get_bss_info(&bss_info);
out_stat->is_connected = 1;
out_stat->channel = bss_info.channel;
out_stat->wifi_strength = bss_info.rssi;
memcpy(out_stat->bssid, bss_info.bssid, 6);
memcpy(out_stat->ssid, bss_info.ssid, sizeof(bss_info.ssid));
}
return 0;
}
static void wifi_scan(hal_wifi_module_t *m)
{
rda59xx_scan_info scan_info;
memset(&scan_info, 0, sizeof(rda59xx_scan_info));
scan_info.scan_mode = 0;
scan_info.scan_time = 1;
rda59xx_scan(&scan_info);
scan_done(m, SCAN_NORMAL);;
}
static void start_scan_adv(hal_wifi_module_t *m)
{
rda59xx_scan_info scan_info;
memset(&scan_info, 0, sizeof(rda59xx_scan_info));
scan_info.scan_mode = 1;
scan_info.scan_time = 2;
rda59xx_scan(&scan_info);
scan_done(m, SCAN_ADV);
}
static void start_scan_direct(hal_wifi_module_t *m)
{
start_scan_adv(m);
}
static int power_off(hal_wifi_module_t *m)
{
LOG("WiFi HAL %s not implemeted yet!\r\n", __func__);
return 0;
}
static int power_on(hal_wifi_module_t *m)
{
LOG("WiFi HAL %s not implemeted yet!\r\n", __func__);
return 0;
}
static int suspend(hal_wifi_module_t *m)
{
sta_try_reconnect = false;
rda59xx_sta_disconnect();
return 0;
}
static int suspend_station(hal_wifi_module_t *m)
{
sta_try_reconnect = false;
rda59xx_sta_disconnect();
return 0;
}
static int suspend_soft_ap(hal_wifi_module_t *m)
{
return 0;
}
static int set_channel(hal_wifi_module_t *m, int ch)
{
//unsigned int mode = rda59xx_get_module_state();
//if(mode & STATE_SNIFFER)
// rda59xx_sniffer_set_channel(ch);
//else
rda59xx_set_channel(ch);
return 0;
}
static int get_channel(hal_wifi_module_t *m)
{
rda59xx_bss_info bss_info;
unsigned int state = 0;
if(state & STATE_STA){
rda59xx_sta_get_bss_info(&bss_info);
return bss_info.channel;
}
return 0;
}
int sniffer_cb(void *data, unsigned short data_len)
{
if(data_cb != NULL) {
(*data_cb)((uint8_t*)data, (int)data_len, (hal_wifi_link_info_t *)((int8_t*)data + data_len));
}
return 0;
}
static void start_monitor(hal_wifi_module_t *m)
{
//if softap smartconfig failed, it will start monitor dirictly
//so add disconnect to end last link
sta_try_reconnect = false;
rda59xx_sta_disconnect();
rda59xx_sniffer_enable(sniffer_cb);
rda59xx_sniffer_set_filter(1, 1, 0x27e77);
filter_backup = 0x27e77;
}
static int start_ap(hal_wifi_module_t *m, const char *ssid, const char *passwd, int interval, int hide)
{
rda59xx_ap_info aws_ap_info;
memset((void*)&aws_ap_info, 0, sizeof(rda59xx_ap_info));
strncpy(aws_ap_info.ssid, ssid, sizeof(aws_ap_info.ssid));
strncpy(aws_ap_info.pw, passwd, sizeof(aws_ap_info.pw));
aws_ap_info.channel = 6;
aws_ap_info.hidden = hide;
aws_ap_info.beacon = interval;
aws_ap_info.dhcps=inet_addr("10.10.100.1");
aws_ap_info.dhcpe=inet_addr("10.10.100.255");
aws_ap_info.ip=inet_addr("10.10.100.1");
aws_ap_info.gateway=inet_addr("10.10.100.1");
aws_ap_info.netmask=inet_addr("255.255.255.0");
return rda59xx_ap_enable(&aws_ap_info);
}
static int stop_ap(hal_wifi_module_t *m)
{
return rda59xx_ap_disable();
}
static void stop_monitor(hal_wifi_module_t *m)
{
rda59xx_sniffer_disable();
}
static void register_monitor_cb(hal_wifi_module_t *m, monitor_data_cb_t fn)
{
data_cb = fn;
}
static void register_wlan_mgnt_monitor_cb(hal_wifi_module_t *m,
monitor_data_cb_t fn)
{
data_cb = fn;
if (data_cb) {
rda59xx_sniffer_enable(sniffer_cb);
rda59xx_sniffer_set_filter(1, 1, 0x7fe77);
filter_backup = 0x7fe77;
} else {
rda59xx_sniffer_disable();
}
return 0;
}
static int wlan_send_80211_raw_frame(hal_wifi_module_t *m,
uint8_t *buf, int len)
{
rda59xx_send_rawdata(buf, len);
return 0;
}
#if (WIFI_CONFIG_SUPPORT_LOWPOWER > 0)
static int set_listeninterval(hal_wifi_module_t *m, uint8_t listen_interval)
{
rda5981_set_sta_listen_interval(listen_interval);
return 0;
}
static int enter_powersave(hal_wifi_module_t *m, uint8_t recvDTIMs)
{
printf("enter_powersave\n");
wland_set_sta_sleep(1);
return 0;
}
static int exit_powersave(hal_wifi_module_t *m)
{
wland_set_sta_sleep(0);
return 0;
}
#endif
hal_wifi_module_t aos_wifi_rda59xx = {
.base.name = "aos_wifi_rda59xx",
.init = wifi_init,
.get_mac_addr = wifi_get_mac_addr,
.set_mac_addr = wifi_set_mac_addr,
.start = wifi_start,
.start_adv = wifi_start_adv,
.get_ip_stat = get_ip_stat,
.get_link_stat = get_link_stat,
.start_scan = wifi_scan,
.start_scan_adv = start_scan_adv,
.start_scan_direct = start_scan_direct,
.power_off = power_off,
.power_on = power_on,
.suspend = suspend,
.suspend_station = suspend_station,
.suspend_soft_ap = suspend_soft_ap,
.set_channel = set_channel,
.get_channel = get_channel,
.start_monitor = start_monitor,
.stop_monitor = stop_monitor,
.start_ap = start_ap,
.stop_ap = stop_ap,
.register_monitor_cb = register_monitor_cb,
.register_wlan_mgnt_monitor_cb = register_wlan_mgnt_monitor_cb,
.wlan_send_80211_raw_frame = wlan_send_80211_raw_frame,
#if (WIFI_CONFIG_SUPPORT_LOWPOWER > 0)
.set_listeninterval = set_listeninterval,
.enter_powersave = enter_powersave,
.exit_powersave = exit_powersave,
#endif
/* mesh related */
//.mesh_register_cb = register_mesh_cb,
//.mesh_enable = mesh_enable,
//.mesh_disable = mesh_disable,
};

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/* mbed Microcontroller Library
* Copyright (c) 2014-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_BUFFER_H
#define MBED_BUFFER_H
#include <stddef.h>
/** Generic buffer structure
*/
typedef struct buffer_s {
void *buffer; /**< the pointer to a buffer */
size_t length; /**< the buffer length */
size_t pos; /**< actual buffer position */
uint8_t width; /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
} buffer_t;
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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/* mbed Microcontroller Library
* Copyright (c) 2014-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DMA_API_H
#define MBED_DMA_API_H
#include <stdint.h>
#define DMA_ERROR_OUT_OF_CHANNELS (-1)
typedef enum {
DMA_USAGE_NEVER,
DMA_USAGE_OPPORTUNISTIC,
DMA_USAGE_ALWAYS,
DMA_USAGE_TEMPORARY_ALLOCATED,
DMA_USAGE_ALLOCATED
} DMAUsage;
#ifdef __cplusplus
extern "C" {
#endif
void dma_init(void);
int dma_channel_allocate(uint32_t capabilities);
int dma_channel_free(int channelid);
#ifdef __cplusplus
}
#endif
#endif

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/** \addtogroup hal */
/** @{*/
/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_FLASH_API_H
#define MBED_FLASH_API_H
#include "device.h"
#include <stdint.h>
#if DEVICE_FLASH
#define MBED_FLASH_INVALID_SIZE 0xFFFFFFFF
typedef struct flash_s flash_t;
#if TARGET_FLASH_CMSIS_ALGO
#include "flash_data.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup flash_hal Flash HAL API
* @{
*/
/** Initialize the flash peripheral and the flash_t object
*
* @param obj The flash object
* @return 0 for success, -1 for error
*/
int32_t flash_init(flash_t *obj);
/** Uninitialize the flash peripheral and the flash_t object
*
* @param obj The flash object
* @return 0 for success, -1 for error
*/
int32_t flash_free(flash_t *obj);
/** Erase one sector starting at defined address
*
* The address should be at sector boundary. This function does not do any check for address alignments
* @param obj The flash object
* @param address The sector starting address
* @return 0 for success, -1 for error
*/
int32_t flash_erase_sector(flash_t *obj, uint32_t address);
/** Program one page starting at defined address
*
* The page should be at page boundary, should not cross multiple sectors.
* This function does not do any check for address alignments or if size is aligned to a page size.
* @param obj The flash object
* @param address The sector starting address
* @param data The data buffer to be programmed
* @param size The number of bytes to program
* @return 0 for success, -1 for error
*/
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size);
/** Get sector size
*
* @param obj The flash object
* @param address The sector starting address
* @return The size of a sector
*/
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address);
/** Get page size
*
* @param obj The flash object
* @param address The page starting address
* @return The size of a page
*/
uint32_t flash_get_page_size(const flash_t *obj);
/** Get start address for the flash region
*
* @param obj The flash object
* @return The start address for the flash region
*/
uint32_t flash_get_start_address(const flash_t *obj);
/** Get the flash region size
*
* @param obj The flash object
* @return The flash region size
*/
uint32_t flash_get_size(const flash_t *obj);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif
#endif
/** @}*/

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/* mbed Microcontroller Library
* Copyright (c) 2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_FLASH_DATA_H
#define MBED_FLASH_DATA_H
#include <stdint.h>
// Target flash algorithm structure
typedef struct {
const uint32_t init;
const uint32_t uninit;
const uint32_t erase_sector;
const uint32_t program_page;
const uint32_t static_base;
uint32_t *algo_blob;
} flash_algo_t;
typedef struct {
const uint32_t start;
const uint32_t size;
} sector_info_t;
typedef struct {
const uint32_t page_size;
const uint32_t flash_start;
const uint32_t flash_size;
const sector_info_t *sectors;
const uint32_t sector_info_count;
} flash_target_config_t;
// Target flash configuration
struct flash_s {
const flash_target_config_t *target_config;
const flash_algo_t *flash_algo;
};
typedef struct {
uint32_t r0;
uint32_t r1;
uint32_t r2;
uint32_t r3;
uint32_t r9;
uint32_t pc;
} args_t;
typedef int32_t (*flash_algo_jump_t)(args_t*);
// prototypes for flash algo CMSIS API
typedef int (*CMSIS_Algo_Function_Init)(unsigned long adr, unsigned long clk, unsigned long fnc);
typedef int (*CMSIS_Algo_Function_UnInit)(unsigned long fnc);
typedef int (*CMSIS_Algo_Function_EraseSector)(unsigned long adr);
typedef int (*CMSIS_Algo_Function_EraseChip)(void);
typedef int (*CMSIS_Algo_Function_ProgramPage)(unsigned long adr, unsigned long sz, unsigned char *buf);
typedef unsigned long (*CMSIS_Algo_Function_Verify)(unsigned long adr, unsigned long sz, unsigned char *buf);
#ifdef __cplusplus
extern "C" {
#endif
/* Set target configuration
*/
void flash_set_target_config(flash_t *obj);
#ifdef __cplusplus
};
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_GPIO_API_H
#define MBED_GPIO_API_H
#include <stdint.h>
#include "device.h"
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_NUM 28
static gpio_t gpio_obj[GPIO_NUM];
static const uint16_t gpio_map[GPIO_NUM] = {
[0] = GPIO_PIN0,
[1] = GPIO_PIN1,
[2] = GPIO_PIN2,
[3] = GPIO_PIN3,
[4] = GPIO_PIN4,
[5] = GPIO_PIN5,
[6] = GPIO_PIN6,
[7] = GPIO_PIN7,
[8] = GPIO_PIN8,
[9] = GPIO_PIN9,
[10] = GPIO_PIN10,
[11] = GPIO_PIN11,
[12] = GPIO_PIN12,
[13] = GPIO_PIN13,
[14] = GPIO_PIN14,
[15] = GPIO_PIN15,
[16] = GPIO_PIN16,
[17] = GPIO_PIN17,
[18] = GPIO_PIN18,
[19] = GPIO_PIN19,
[20] = GPIO_PIN20,
[21] = GPIO_PIN21,
[22] = GPIO_PIN22,
[23] = GPIO_PIN23,
[24] = GPIO_PIN24,
[25] = GPIO_PIN25,
[26] = GPIO_PIN26,
[27] = GPIO_PIN27,
};
typedef enum {
IRQ_NONE,
IRQ_RISE,
IRQ_FALL
} gpio_irq_event;
typedef enum {
GPIO_IRQ_CH0,
GPIO_IRQ_CH1,
CHANNEL_NUM
} GPIO_IRQ_IDX_T;
typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event, uint32_t arg);
/**
* \defgroup hal_gpio GPIO HAL functions
* @{
*/
/** Set the given pin as GPIO
*
* @param pin The pin to be set as GPIO
* @return The GPIO port mask for this pin
**/
uint32_t gpio_set(PinName pin);
/* Checks if gpio object is connected (pin was not initialized with NC)
* @param pin The pin to be set as GPIO
* @return 0 if port is initialized with NC
**/
int gpio_is_connected(const gpio_t *obj);
/** Initialize the GPIO pin
*
* @param obj The GPIO object to initialize
* @param pin The GPIO pin to initialize
*/
void gpio_init(gpio_t *obj, PinName pin);
/** Set the input pin mode
*
* @param obj The GPIO object
* @param mode The pin mode to be set
*/
void gpio_mode(gpio_t *obj, PinMode mode);
/** Set the pin direction
*
* @param obj The GPIO object
* @param direction The pin direction to be set
*/
void gpio_dir(gpio_t *obj, PinDirection direction);
/** Set the output value
*
* @param obj The GPIO object
* @param value The value to be set
*/
void gpio_write(gpio_t *obj, int value);
/** Read the input value
*
* @param obj The GPIO object
* @return An integer value 1 or 0
*/
int gpio_read(gpio_t *obj);
// the following functions are generic and implemented in the common gpio.c file
// TODO: fix, will be moved to the common gpio header file
/** Init the input pin and set mode to PullDefault
*
* @param obj The GPIO object
* @param pin The pin name
*/
void gpio_init_in(gpio_t* gpio, PinName pin);
/** Init the input pin and set the mode
*
* @param obj The GPIO object
* @param pin The pin name
* @param mode The pin mode to be set
*/
void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
/** Init the output pin as an output, with predefined output value 0
*
* @param obj The GPIO object
* @param pin The pin name
* @return An integer value 1 or 0
*/
void gpio_init_out(gpio_t* gpio, PinName pin);
/** Init the pin as an output and set the output value
*
* @param obj The GPIO object
* @param pin The pin name
* @param value The value to be set
*/
void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
/** Init the pin to be in/out
*
* @param obj The GPIO object
* @param pin The pin name
* @param direction The pin direction to be set
* @param mode The pin mode to be set
* @param value The value to be set for an output pin
*/
void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
/** Init the pin to support irq
*
* @param obj The GPIO object
* @param handler irq callback handler
* @param arg argument of irq callback handler
*/
int gpio_irq_init(gpio_t *obj, uint32_t handler, uint32_t arg);
/** Enables or disable an interrupt trigger and set trigger type
*
* @param obj The GPIO object
* @param event trigger type
* @param enable Enables or disable an interrupt trigger
*/
void gpio_irq_set(gpio_t *obj, gpio_irq_event event, uint32_t enable);
/** Disables an interrupt trigger for an input GPIO pin
*
* @param obj The GPIO object
*/
void gpio_irq_free(gpio_t *obj);
/** Enable gpio interrupt trigger
*/
void gpio_irq_enable();
/** Disable gpio interrupt trigger
*/
void gpio_irq_disable();
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINMAP_H
#define MBED_PINMAP_H
#include "pinnames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
int peripheral;
int function;
} PinMap;
void pin_function(PinName pin, int function);
void pin_mode (PinName pin, PinMode mode);
uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
uint32_t pinmap_function(PinName pin, const PinMap* map);
uint32_t pinmap_merge (uint32_t a, uint32_t b);
void pinmap_pinout (PinName pin, const PinMap *map);
uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
uint32_t pinmap_find_function(PinName pin, const PinMap* map);
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTMAP_H
#define MBED_PORTMAP_H
#include "device.h"
#if DEVICE_PORTIN || DEVICE_PORTOUT
#ifdef __cplusplus
extern "C" {
#endif
/** Port HAL structure. port_s is declared in the target's HAL
*/
typedef struct port_s port_t;
/**
* \defgroup hal_port Port HAL functions
* @{
*/
/** Get the pin name from the port's pin number
*
* @param port The port name
* @param pin_n The pin number within the specified port
* @return The pin name for the port's pin number
*/
PinName port_pin(PortName port, int pin_n);
/** Initilize the port
*
* @param obj The port object to initialize
* @param port The port name
* @param mask The bitmask to identify which bits in the port should be included (0 - ignore)
* @param dir The port direction
*/
void port_init(port_t *obj, PortName port, int mask, PinDirection dir);
/** Set the input port mode
*
* @param obj The port object
* @param mode THe port mode to be set
*/
void port_mode(port_t *obj, PinMode mode);
/** Set port direction (in/out)
*
* @param obj The port object
* @param dir The port direction to be set
*/
void port_dir(port_t *obj, PinDirection dir);
/** Write value to the port
*
* @param obj The port object
* @param value The value to be set
*/
void port_write(port_t *obj, int value);
/** Read the current value on the port
*
* @param obj The port object
* @return An integer with each bit corresponding to an associated port pin setting
*/
int port_read(port_t *obj);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PWMOUT_API_H
#define MBED_PWMOUT_API_H
#include "device.h"
#ifdef __cplusplus
extern "C" {
#endif
/** Pwmout hal structure. pwmout_s is declared in the target's hal
*/
typedef struct pwmout_s pwmout_t;
/**
* \defgroup hal_pwmout Pwmout hal functions
* @{
*/
/** Set the pwm out clock, PWM0~4 share the same clock source, and
* the period equals (1 / (frequency / divider)) * ticks, there are tables:
*
* =================================================
* | PWM \ ticks | max | 1% | min |
* |-----------------------------------------------|
* | PWM0~3 | 0x20000 | 0x64 | 0x2 |
* |-----------------------------------------------|
* | PWM4 | 0x1FF8 | 0x320 | 0x8 |
* =================================================
*
* ==============================================================================================================
* | div \ freq | 16.384KHz | 10MHz |
* ==============================================================================================================
* | | PWM \ period | max | 1% | min | PWM \ period | max | 1% | min |
* | |-----------------------------------------------|-----------------------------------------------|
* | 0 | PWM0~3 | 8s | 6.1ms | 122us | PWM0~3 | 13.1ms | 10us | 200ns |
* | |-----------------------------------------------|-----------------------------------------------|
* | | PWM4 | 499.5ms | 48.8ms | 488.3us | PWM4 | 818.4us | 80us | 800ns |
* ==============================================================================================================
* | | PWM \ period | max | 1% | min | PWM \ period | max | 1% | min |
* | |-----------------------------------------------|-----------------------------------------------|
* | 128 | PWM0~3 | 1024s | 781ms | 15.6ms | PWM0~3 | 1677.7ms | 1.28ms | 25.6us |
* | |-----------------------------------------------|-----------------------------------------------|
* | | PWM4 | 63.9s | 6.25s | 62.5ms | PWM4 | 104.8ms | 10.24ms | 102.4us |
* ==============================================================================================================
*
* @param obj The pwmout object
* @param src The pwmout clock source, 0 represents 16KHz, 1 represents 10MHz
* @param div The pwmout clock divider, 0 represents no divider, 2/4/6/8/.../126/128 is valid
*/
void pwmout_clk_set(pwmout_t *obj, int src, int div);
void pwmout_diff_write(pwmout_t *obj, float percent);
#endif /* TARGET_UNO_91H */
/** Initialize the pwm out peripheral and configure the pin
*
* @param obj The pwmout object to initialize
* @param pin The pwmout pin to initialize
*/
void pwmout_init(pwmout_t *obj, PinName pin);
/** Deinitialize the pwmout object
*
* @param obj The pwmout object
*/
void pwmout_free(pwmout_t *obj);
/** Set the output duty-cycle in range <0.0f, 1.0f>
*
* Value 0.0f represents 0 percentage, 1.0f represents 100 percent.
* @param obj The pwmout object
* @param percent The floating-point percentage number
*/
void pwmout_write(pwmout_t *obj, float percent);
/** Read the current float-point output duty-cycle
*
* @param obj The pwmout object
* @return A floating-point output duty-cycle
*/
float pwmout_read(pwmout_t *obj);
/** Set the PWM period specified in seconds, keeping the duty cycle the same
*
* Periods smaller than microseconds (the lowest resolution) are set to zero.
* @param obj The pwmout object
* @param seconds The floating-point seconds period
*/
void pwmout_period(pwmout_t *obj, float seconds);
/** Set the PWM period specified in miliseconds, keeping the duty cycle the same
*
* @param obj The pwmout object
* @param ms The milisecond period
*/
void pwmout_period_ms(pwmout_t *obj, int ms);
/** Set the PWM period specified in microseconds, keeping the duty cycle the same
*
* @param obj The pwmout object
* @param us The microsecond period
*/
void pwmout_period_us(pwmout_t *obj, int us);
/** Set the PWM pulsewidth specified in seconds, keeping the period the same.
*
* @param obj The pwmout object
* @param seconds The floating-point pulsewidth in seconds
*/
void pwmout_pulsewidth(pwmout_t *obj, float seconds);
/** Set the PWM pulsewidth specified in miliseconds, keeping the period the same.
*
* @param obj The pwmout object
* @param ms The floating-point pulsewidth in miliseconds
*/
void pwmout_pulsewidth_ms(pwmout_t *obj, int ms);
/** Set the PWM pulsewidth specified in microseconds, keeping the period the same.
*
* @param obj The pwmout object
* @param us The floating-point pulsewidth in microseconds
*/
void pwmout_pulsewidth_us(pwmout_t *obj, int us);
void pwmout_sync_write(pwmout_t *obj, float value, uint8_t duty_sel);
/**@}*/
#ifdef __cplusplus
}
#endif

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/******************************************************************************
* @file RDA5981.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for
* RDA RDA5981 Device Series
* @version: V1.09
* @date: 07. July 2016
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __RDA5981_H__
#define __RDA5981_H__
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** RDA5981 Specific Interrupt Numbers ******************************************************/
SPIFLASH_IRQn = 0, /*!< SPI Flash Interrupt */
PTA_IRQn = 1, /*!< PTA Interrupt */
SDIO_IRQn = 2, /*!< SDIO Interrupt */
USBDMA_IRQn = 3, /*!< USBDMA Interrupt */
USB_IRQn = 4, /*!< USB Interrupt */
GPIO_IRQn = 5, /*!< GPIO Interrupt */
TIMER_IRQn = 6, /*!< Timer Interrupt */
UART0_IRQn = 7, /*!< UART0 Interrupt */
MACHW_IRQn = 8, /*!< MAC Hardware Interrupt */
UART1_IRQn = 9, /*!< UART1 Interrupt */
AHBDMA_IRQn = 10, /*!< AHBDMA Interrupt */
PSRAM_IRQn = 11, /*!< PSRAM Interrupt */
SDMMC_IRQn = 12, /*!< SDMMC Interrupt */
EXIF_IRQn = 13, /*!< EXIF Interrupt */
I2C_IRQn = 14 /*!< I2C Interrupt */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M4 Processor and Core Peripherals */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1 /*!< FPU present */
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_rda5981.h" /* System Header */
#include <stdint.h>
/** @addtogroup Exported_types
* @{
*/
/*!< RDA5981 Standard Peripheral Library old types (maintained for legacy purpose) */
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef const int32_t sc32; /*!< Read Only */
typedef const int16_t sc16; /*!< Read Only */
typedef const int8_t sc8; /*!< Read Only */
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef __I int32_t vsc32; /*!< Read Only */
typedef __I int16_t vsc16; /*!< Read Only */
typedef __I int8_t vsc8; /*!< Read Only */
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef const uint32_t uc32; /*!< Read Only */
typedef const uint16_t uc16; /*!< Read Only */
typedef const uint8_t uc8; /*!< Read Only */
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef __I uint32_t vuc32; /*!< Read Only */
typedef __I uint16_t vuc16; /*!< Read Only */
typedef __I uint8_t vuc8; /*!< Read Only */
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
/**
* @}
*/
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- System Control Unit (SCU) ------------------------------------*/
typedef struct
{
__IO uint32_t CLKGATE0; /* 0x00 : Clock Gating 0 */
__IO uint32_t PWRCTRL; /* 0x04 : Power Control */
__IO uint32_t CLKGATE1; /* 0x08 : Clock Gating 1 */
__IO uint32_t CLKGATE2; /* 0x0C : Clock Gating 2 */
__IO uint32_t RESETCTRL; /* 0x10 : Power Control */
__IO uint32_t CLKGATE3; /* 0x14 : Clock Gating 3 */
__IO uint32_t CORECFG; /* 0x18 : Core Config */
__IO uint32_t CPUCFG; /* 0x1C : CPU Config */
__IO uint32_t FTMRINITVAL; /* 0x20 : Free Timer Initial Value */
__IO uint32_t FTMRTS; /* 0x24 : Free Timer Timestamp */
__IO uint32_t CLKGATEBP; /* 0x28 : Clock Gating Bypass */
uint32_t RESERVED0[2];
__IO uint32_t PWMCFG; /* 0x34 : PWM Config */
__IO uint32_t FUN0WAKEVAL; /* 0x38 : SDIO Func0 Wake Val */
__IO uint32_t FUN1WAKEVAL; /* 0x3C : SDIO Func1 Wake Val */
__IO uint32_t BOOTJUMPADDR; /* 0x40 : Boot Jump Addr */
__IO uint32_t SDIOINTVAL; /* 0x44 : SDIO Int Val */
__IO uint32_t I2SCLKDIV; /* 0x48 : I2S Clock Divider */
__IO uint32_t BOOTJUMPADDRCFG; /* 0x4C : Boot Jump Addr Config */
__IO uint32_t FTMRPREVAL; /* 0x50 : Free Timer Prescale Init Val*/
__IO uint32_t PWROPENCFG; /* 0x54 : Power Open Config */
__IO uint32_t PWRCLOSECFG; /* 0x58 : Power Close Config */
} RDA_SCU_TypeDef;
/*------------- Timer0 (TIM0) ------------------------------------------------*/
typedef struct
{
__IO uint32_t LDCNT; /* 0x00 : Timer Load Count Register */
__I uint32_t CVAL; /* 0x04 : Current Timer Value Register*/
__IO uint32_t TCTRL; /* 0x08 : Timer Control Register */
__I uint32_t INTCLR; /* 0x0C : Interrupt Clear Register */
} RDA_TIM0_TypeDef;
/*------------- Timer1 (TIM1) ------------------------------------------------*/
typedef struct
{
__IO uint32_t TCTRL; /* 0x00 : Timer Control Register */
uint32_t RESERVED0[2];
__IO uint32_t LDCNT; /* 0x0C : Timer Load Count Register */
__I uint32_t CVAL; /* 0x10 : Current Timer Value Register*/
uint32_t RESERVED1;
__I uint32_t INTCLR; /* 0x18 : Interrupt Clear Register */
} RDA_TIM1_TypeDef;
/*------------- Timer Interrupt Status (TIMINTST) ----------------------------*/
typedef struct
{
__I uint32_t INTST; /* 0x00 : Timer Int Stat Register */
} RDA_TIMINTST_TypeDef;
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
typedef struct
{
__IO uint32_t CTRL; /* 0x00 : GPIO Control */
uint32_t RESERVED0;
__IO uint32_t DOUT; /* 0x08 : GPIO Data Output */
__IO uint32_t DIN; /* 0x0C : GPIO Data Input */
__IO uint32_t DIR; /* 0x10 : GPIO Direction */
__IO uint32_t SLEW0; /* 0x14 : GPIO Slew Config 0 */
__IO uint32_t SLEWIOMUX; /* 0x18 : GPIO IOMUX Slew Config */
__IO uint32_t INTCTRL; /* 0x1C : GPIO Interrupt Control */
__IO uint32_t IFCTRL; /* 0x20 : Interface Control */
__IO uint32_t SLEW1; /* 0x24 : GPIO Slew Config 1 */
__IO uint32_t REVID; /* 0x28 : ASIC Reversion ID */
__IO uint32_t LPOSEL; /* 0x2C : LPO Select */
uint32_t RESERVED1;
__IO uint32_t INTSEL; /* 0x34 : GPIO Interrupt Select */
uint32_t RESERVED2;
__IO uint32_t SDIOCFG; /* 0x3C : SDIO Config */
__IO uint32_t MEMCFG; /* 0x40 : Memory Config */
__IO uint32_t IOMUXCTRL[8]; /* 0x44 - 0x60 : IOMUX Control */
__IO uint32_t PCCTRL; /* 0x64 : Pulse Counter Control */
} RDA_GPIO_TypeDef;
/*------------- Inter-Integrated Circuit 0 (I2C0) ----------------------------*/
typedef struct
{
__IO uint32_t CR0; /* 0x00 : Control Register 0 */
__I uint32_t SR; /* 0x04 : Status Register */
__IO uint32_t DR; /* 0x08 : TX/RX Data Register */
__O uint32_t CMD; /* 0x0C : Command Register */
__O uint32_t ICR; /* 0x10 : Interrupt Clear Register */
__IO uint32_t CR1; /* 0x14 : Control Register 1 */
} RDA_I2C0_TypeDef;
/*------------- Pulse Width Modulator (PWM) ----------------------------------*/
typedef struct
{
__IO uint32_t PWTCFG; /* 0x00 : PWT Config Register */
__IO uint32_t LPGCFG; /* 0x04 : LPG Config Register */
__IO uint32_t PWL0CFG; /* 0x08 : PWL0 Config Register */
__IO uint32_t PWL1CFG; /* 0x0C : PWL1 Config Register */
__IO uint32_t CLKR; /* 0x10 : Clock Config Register */
} RDA_PWM_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct
{
union {
__I uint32_t RBR; /* 0x00 : UART Receive buffer register */
__O uint32_t THR; /* 0x00 : UART Transmit holding register */
__IO uint32_t DLL; /* 0x00 : UART Divisor latch(low) */
};
union {
__IO uint32_t DLH; /* 0x04 : UART Divisor latch(high) */
__IO uint32_t IER; /* 0x04 : UART Interrupt enable register */
};
union {
__I uint32_t IIR; /* 0x08 : UART Interrupt id register */
__O uint32_t FCR; /* 0x08 : UART Fifo control register */
};
__IO uint32_t LCR; /* 0x0C : UART Line control register */
__IO uint32_t MCR; /* 0x10 : UART Moderm control register */
__I uint32_t LSR; /* 0x14 : UART Line status register */
__I uint32_t MSR; /* 0x18 : UART Moderm status register */
__IO uint32_t SCR; /* 0x1C : UART Scratchpad register */
__I uint32_t FSR; /* 0x20 : UART FIFO status register */
__IO uint32_t FRR; /* 0x24 : UART FIFO tx/rx trigger resiger */
__IO uint32_t DL2; /* 0x28 : UART Baud rate adjust register */
__I uint32_t RESERVED0[4];
__I uint32_t BAUD; /* 0x3C : UART Auto baud counter */
__I uint32_t DL_SLOW; /* 0x40 : UART Divisor Adjust when slow clk */
__I uint32_t DL_FAST; /* 0x44 : UART Divisor Adjust when fast clk */
} RDA_UART_TypeDef;
/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
typedef struct
{
__IO uint32_t CFG;
__IO uint32_t D0CMD;
__IO uint32_t D1CMD;
} RDA_SPI_TypeDef;
/*------------- Integrated Interchip Sound (I2S) -----------------------------*/
typedef struct
{
__IO uint32_t CFG;
__IO uint32_t DOUTWR;
__I uint32_t DINRD;
} RDA_I2S_TypeDef;
/*------------- External Interface (EXIF) ------------------------------------*/
typedef struct
{
RDA_SPI_TypeDef SPI0; /* 0x00 - 0x08 : SPI0 registers group */
RDA_I2S_TypeDef I2S; /* 0x0C - 0x14 : I2S registers group */
__IO uint32_t MISCSTCFG; /* 0x18 : Misc status config register */
__IO uint32_t SPI1CTRL; /* 0x1C : SPI1 Control register */
uint32_t RESERVED0[4];
__IO uint32_t MISCINTCFG; /* 0x30 : Misc int config register */
__IO uint32_t MBB2W; /* 0x34 : BT to WiFi mailbox register */
__IO uint32_t MBW2B; /* 0x38 : WiFi to BT mailbox register */
__IO uint32_t MISCCFG; /* 0x3C : Misc configure register */
__IO uint32_t PWM0CFG; /* 0x40 : PWM0 configure register */
__IO uint32_t PWM1CFG; /* 0x44 : PWM1 configure register */
__IO uint32_t PWM2CFG; /* 0x48 : PWM2 configure register */
__IO uint32_t PWM3CFG; /* 0x4C : PWM3 configure register */
} RDA_EXIF_TypeDef;
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
typedef struct
{
__IO uint32_t WDTCFG;
} RDA_WDT_TypeDef;
/*------------- Pin Configure (PINCFG) ---------------------------------------*/
typedef struct
{
union {
__IO uint32_t IOMUXCTRL[8];
struct {
__IO uint32_t MUX0;
__IO uint32_t MUX1;
__IO uint32_t MODE0;
__IO uint32_t MODE1;
__IO uint32_t MUX2;
__IO uint32_t MUX3;
__IO uint32_t MODE2;
__IO uint32_t MODE3;
};
};
} RDA_PINCFG_TypeDef;
/*------------- AHB Direct Memory Access (DMA) -------------------------------*/
typedef struct
{
__IO uint32_t dma_ctrl; /* 0x00 : DMA ctrl */
__IO uint32_t dma_src; /* 0x04 : DMA src */
__IO uint32_t dma_dst; /* 0x08 : DMA dst */
__IO uint32_t dma_len; /* 0x0c : DMA len */
__IO uint32_t crc_gen; /* 0x10 : CRC gen */
__IO uint32_t dma_func_ctrl; /* 0x14 : DMA func ctrl */
__IO uint32_t aes_key0; /* 0x18 : AES key 0 */
__IO uint32_t aes_key1; /* 0x1c : AES key 1 */
__IO uint32_t aes_key2; /* 0x20 : AES key 2 */
__IO uint32_t aes_key3; /* 0x24 : AES key 2 */
__IO uint32_t aes_iv0; /* 0x28 : AES iv 0 */
__IO uint32_t aes_iv1; /* 0x2c : AES iv 1 */
__IO uint32_t aes_iv2; /* 0x30 : AES iv 2 */
__IO uint32_t aes_iv3; /* 0x34 : AES iv 2 */
__IO uint32_t aes_mode; /* 0x38 : AES mode */
__IO uint32_t cios_ctrl; /* 0x3c : cios ctrl */
__IO uint32_t cios_reg0; /* 0x40 : cios reg 0 */
__IO uint32_t crc_init_val; /* 0x44 : CRC init val */
__IO uint32_t crc_out_xorval; /* 0x48 : CRC out xorval */
__I uint32_t crc_out_val; /* 0x4c : CRC out val */
uint32_t RESERVED0[12];
__IO uint32_t dma_int_out; /* 0x80 : DMA int out */
__IO uint32_t dma_int_mask; /* 0x84 : DMA int mask */
uint32_t RESERVED1[30];
__IO uint32_t trng_ctrl; /* 0x100 : TRNG ctrl */
__IO uint32_t prng_ctrl; /* 0x104 : PRNG ctrl */
__IO uint32_t prng_seed; /* 0x108 : PRNG seed */
__IO uint32_t prng_timer_int; /* 0x10c : PRNG timer init */
__IO uint32_t prng_timer; /* 0x110 : PRNG timer */
__I uint32_t trng_data0; /* 0x114 : TRNG data 0 */
__I uint32_t trng_data0_mask; /* 0x118 : TRNG data 0 mask */
__I uint32_t trng_data1; /* 0x11c : TRNG data 1 */
__I uint32_t trng_data1_mask; /* 0x120 : TRNG data 1 mask */
__I uint32_t prng_data; /* 0x124 : PRNG data */
__I uint32_t trng_hc; /* 0x128 : TRNG hc */
uint32_t RESERVED2[437];
__IO uint32_t cios_data_base; /* 0x800 : CIOS data base */
} RDA_DMACFG_TypeDef;
/*------------- Universal Serial Bus (USB) -------------------------------------------*/
typedef struct
{
struct {
__IO uint8_t FUNC_ADDR; /* 0x00: Function Address */
__IO uint8_t POWER; /* 0x01: Power */
__IO uint16_t INTRTX; /* 0x02-0x03: IntrTx */
};
struct {
__IO uint16_t INTRRX; /* 0x04-0x05: IntrRx */
__IO uint16_t INTRTXEN; /* 0x06-0x07: IntrTx Enable */
};
struct {
__IO uint16_t INTRRXEN; /* 0x08-0x09: IntrRx Enable */
__IO uint8_t INTR; /* 0x0a: Interrupt */
__IO uint8_t INTREN; /* 0x0b: Intr Enable */
};
struct {
__IO uint16_t FRAMENUM; /* 0x0c-0x0d: Frame Number */
__IO uint8_t EPIDX; /* 0x0e: Endpoint Index */
__IO uint8_t TESTMODE; /* 0x0f: Test Mode */
};
struct {
__IO uint16_t TXMAXPKTSIZE; /* 0x10-0x11: Tx Max Packet Size */
union {
__IO uint16_t CSR0; /* 0x12-0x13: CSR0 */
__IO uint16_t TXCSR; /* 0x12-0x13: CSR0 */
};
};
struct {
__IO uint16_t RXMAXPKTSIZE; /* 0x14-0x15: Rx Max Packet Size */
__IO uint16_t RXCSR; /* 0x16-0x17: Rx CSR */
};
struct {
union {
__IO uint16_t RXCOUNT0; /* 0x18-0x19: Rx Counter of EP0 */
__IO uint16_t RXCOUNT; /* 0x18-0x19: Rx Counter of Rx EP */
};
#if 0
uint16_t RESERVED0; /* 0x1a-0x1b: reserved */
#else
/* host mode only */
__IO uint8_t TXTYPE; /* 0x1a: TxType */
__IO uint8_t TXINTERVAL; /* 0x1B: TxInterval */
#endif
};
struct {
__IO uint8_t RXTYPE; /* 0x1c: rxtype */
__IO uint8_t RXINTERVAL; /* 0x1d: rxInterval */
uint8_t RESERVED1[1]; /* 0x1e: reserved */
union {
__IO uint8_t CONFIGDATA; /* 0x1f: Data of Core Configuration */
__IO uint8_t FIFOSIZE; /* 0x1f: Size of Selected TX/RX Fifo */
};
};
__IO uint32_t FIFOs[16]; /* 0x20-0x5F: fifos for Endpoint */
struct {
__IO uint8_t DEVCTL; /* 0x60: OTG device control */
uint8_t RESERVED2; /* 0x61: unused */
__IO uint8_t TXFIFOSZ; /* 0x62: Tx Endpoint FIFO Size */
__IO uint8_t RXFIFOSZ; /* 0x63: Rx Endpoint FIFO Size */
};
struct {
__IO uint16_t TXFIFOADDR; /* 0x64-0x65: Tx Endpoint FIFO Address */
__IO uint16_t RXFIFOADDR; /* 0x66-0x67: Rx Endpoint FIFO Address */
};
union {
__IO uint32_t VCONTROL; /* 0x68-0x6b: UTMI+PHY Vendor Register */
__IO uint32_t VSTATUS; /* 0x68-0x6b: UTMI+PHY Vendor Register */
};
struct {
__IO uint16_t HWVERSION; /* 0x6c-0x6d: Hardware Version Number Register */
uint16_t RESERVED3; /* 0x6e-0x6f: Unused */
};
__IO uint8_t ULPIREG[8]; /* 0x70-0x77: ulpi register, not used */
struct {
__IO uint8_t EPINFO; /* 0x78: numbers of tx/rx ep */
__IO uint8_t RAMINFO; /* 0x79: width of RAM and number of DMA channels */
__IO uint8_t LINKINFO; /* 0x7a: delays to be applied */
__IO uint8_t VPLEN; /* 0x7b: Duration of the VBus pulsing charge */
};
struct {
__IO uint8_t HSEOF; /* 0x7c: Timer buffer available on HS transaction */
__IO uint8_t FSEOF; /* 0x7d: Timer buffer available on HS transaction */
__IO uint8_t LSEOF; /* 0x7e: Timer buffer available on HS transaction */
uint8_t RESERVED4; /* 0x7f: unused */
};
uint32_t RESERVED5[3]; /* 0x80-0x8b: unused */
__IO uint32_t FIFO_CTRL; /* 0x8c: FIFO Control */
__IO uint32_t ANAREG2; /* 0x90-0x93 */
uint32_t RESERVED6[91]; /* 0x94-0x1ff: unused */
struct {
__IO uint8_t DMAINTR; /* 0x200: DMA Interrrupt */
__IO uint8_t RESERVED7[3]; /* 0x201-0x203: unused; */
};
__IO uint32_t DMACTRL0; /* 0x204: channel 0 */
__IO uint32_t DMAADDR0; /* 0x208: AHB Memory Address channel 0 */
__IO uint32_t COUNT0; /* 0x20c: DMA Counter for channel 0 */
uint32_t RESERVED8; /* 0x210-0x213: unused */
__IO uint32_t DMACTRL1; /* 0x214: channel 1 */
__IO uint32_t DMAADDR1; /* 0x218: AHB Memory Address channel 1 */
__IO uint32_t COUNT1; /* 0x21c: DMA Counter for channel 1 */
uint8_t RESERVED9[224]; /* 0x220 - 0x2FF: unused */
__IO uint32_t PKCNT0; /* 0X300: packet count epnum 0 */
__IO uint32_t PKCNT1; /* 0X304: packet count epnum 1 */
__IO uint32_t PKCNT2; /* 0X308:packet count epnum 1 */
}RDA_USB_TypeDef;
/*------------- Random Number Generator (RNG) --------------------------------*/
typedef struct
{
__IO uint32_t TCTRL; /* 0x00 : TRNG ctrl */
__IO uint32_t PCTRL; /* 0x04 : PRNG ctrl */
__IO uint32_t PSEED; /* 0x08 : PRNG seed */
__IO uint32_t PTMRINIT; /* 0x0C : PRNG timer init */
__I uint32_t PTMR; /* 0x10 : PRNG timer */
__I uint32_t TD0; /* 0x14 : TRNG data 0 */
__I uint32_t TD0MSK; /* 0x18 : TRNG data 0 mask */
__I uint32_t TD1; /* 0x1C : TRNG data 1 */
__I uint32_t TD1MSK; /* 0x20 : TRNG data 1 mask */
__I uint32_t PD; /* 0x24 : PRNG data */
__I uint32_t THC; /* 0x28 : TRNG h/c value */
} RDA_RNG_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
//#define RDA_ICACHE_DISABLE
#define RDA_PARTITION_INDEX 0
/* Base addresses */
#define RDA_ROM_BASE (0x00000000UL)
#define RDA_IRAM_BASE (0x00100000UL)
#define RDA_DRAM_BASE (0x00180000UL)
#define RDA_PSRAM_BASE (0x10000000UL)
#define RDA_FLASH_BASE (0x14000000UL)
#define RDA_ICACHE_BASE (0x18000000UL)
#if (0 == RDA_PARTITION_INDEX)
#define RDA_PADDR_OFST (0x00004000UL)
#elif (1 == RDA_PARTITION_INDEX)
#define RDA_PADDR_OFST (0x0007E000UL)
#else
#error "Not supported"
#endif
#if defined(RDA_ICACHE_DISABLE)
#define RDA_CODE_BASE (RDA_FLASH_BASE + RDA_PADDR_OFST)
#else /* RDA_ICACHE_DISABLE */
#define RDA_CODE_BASE (RDA_ICACHE_BASE + RDA_PADDR_OFST)
#endif /* RDA_ICACHE_DISABLE */
#define RDA_PER_BASE (0x40000000UL)
#define RDA_AHB0_BASE (0x40000000UL)
#define RDA_APB_BASE (RDA_AHB0_BASE)
#define RDA_AHB1_BASE (0x40100000UL)
#define RDA_PERBTBND_BASE (0x42000000UL)
#define RDA_CM4_BASE (0xE0000000UL)
/* APB peripherals */
#define RDA_SCU_BASE (RDA_APB_BASE + 0x00000)
#define RDA_GPIO_BASE (RDA_APB_BASE + 0x01000)
#define RDA_TIM0_BASE (RDA_APB_BASE + 0x02000)
#define RDA_TIM1_BASE (RDA_APB_BASE + 0x02008)
#define RDA_TIMINTST_BASE (RDA_APB_BASE + 0x02010)
#define RDA_I2C0_BASE (RDA_APB_BASE + 0x03000)
/* AHB0 peripherals */
#define RDA_PWM_BASE (RDA_AHB0_BASE + 0x04000)
#define RDA_PSRAMCFG_BASE (RDA_AHB0_BASE + 0x05000)
#define RDA_SDMMC_BASE (RDA_AHB0_BASE + 0x06000)
#define RDA_I2C_BASE (RDA_AHB0_BASE + 0x10000)
#define RDA_TRAP_BASE (RDA_AHB0_BASE + 0x11000)
#define RDA_UART0_BASE (RDA_AHB0_BASE + 0x12000)
#define RDA_EXIF_BASE (RDA_AHB0_BASE + 0x13000)
#define RDA_PA_BASE (RDA_AHB0_BASE + 0x20000)
#define RDA_CE_BASE (RDA_AHB0_BASE + 0x22000)
#define RDA_MON_BASE (RDA_AHB0_BASE + 0x24000)
#define RDA_SDIO_BASE (RDA_AHB0_BASE + 0x30000)
#define RDA_USB_BASE (RDA_AHB0_BASE + 0x31000)
/* AHB1 peripherals */
#define RDA_MEMC_BASE (RDA_AHB1_BASE + 0x00000)
#define RDA_UART1_BASE (RDA_AHB1_BASE + 0x80000)
#define RDA_DMACFG_BASE (RDA_AHB1_BASE + 0x81000)
#define RDA_RNG_BASE (RDA_AHB1_BASE + 0x81100)
/* EXIF peripherals */
#define RDA_SPI0_BASE (RDA_EXIF_BASE + 0x00000)
#define RDA_I2S_BASE (RDA_EXIF_BASE + 0x0000C)
/* MISC peripherals */
#define RDA_WDT_BASE (RDA_SCU_BASE + 0x0000C)
#define RDA_PINCFG_BASE (RDA_GPIO_BASE + 0x00044)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define RDA_SCU ((RDA_SCU_TypeDef *) RDA_SCU_BASE )
#define RDA_GPIO ((RDA_GPIO_TypeDef *) RDA_GPIO_BASE )
#define RDA_TIM0 ((RDA_TIM0_TypeDef *) RDA_TIM0_BASE )
#define RDA_TIM1 ((RDA_TIM1_TypeDef *) RDA_TIM1_BASE )
#define RDA_TIMINTST ((RDA_TIMINTST_TypeDef *) RDA_TIMINTST_BASE )
#define RDA_I2C0 ((RDA_I2C0_TypeDef *) RDA_I2C0_BASE )
#define RDA_PWM ((RDA_PWM_TypeDef *) RDA_PWM_BASE )
#define RDA_UART0 ((RDA_UART_TypeDef *) RDA_UART0_BASE )
#define RDA_UART1 ((RDA_UART_TypeDef *) RDA_UART1_BASE )
#define RDA_SPI0 ((RDA_SPI_TypeDef *) RDA_SPI0_BASE )
#define RDA_I2S ((RDA_I2S_TypeDef *) RDA_I2S_BASE )
#define RDA_EXIF ((RDA_EXIF_TypeDef *) RDA_EXIF_BASE )
#define RDA_WDT ((RDA_WDT_TypeDef *) RDA_WDT_BASE )
#define RDA_PINCFG ((RDA_PINCFG_TypeDef *) RDA_PINCFG_BASE )
#define RDA_DMACFG ((RDA_DMACFG_TypeDef *) RDA_DMACFG_BASE )
#define RDA_USB ((RDA_USB_TypeDef *) RDA_USB_BASE )
#define RDA_RNG ((RDA_RNG_TypeDef *) RDA_RNG_BASE )
#ifdef USE_STDPERIPH_DRIVER
// #include "rda5981_conf.h"
#endif /* USE_STDPERIPH_DRIVER */
#endif /* __RDA5981_H__ */

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#ifndef RDA_CCFG_API_H
#define RDA_CCFG_API_H
#ifdef __cplusplus
extern "C" {
#endif
void rda_ccfg_aontmr(void);
void rda_ccfg_gp6(unsigned short cfg);
void rda_ccfg_gp7(unsigned short cfg);
void rda_ccfg_gp(unsigned char gp, unsigned short cfg);
void rda_ccfg_ckrst(void);
void rda_ccfg_perrst(void);
void rda_ccfg_adc_init(void);
void rda_ccfg_adc_gp(unsigned char gp, unsigned short cfg);
unsigned short rda_ccfg_adc_read(unsigned char ch);
void rda_ccfg_adc_free(void);
int rda_ccfg_abort_flag(void);
#if RDA5991H_HW_VER >= 2
void rda_ccfg_wdt_en(void);
#endif /* RDA5991H_HW_VER */
int rda_ccfg_hwver(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_SERIAL_API_H
#define MBED_SERIAL_API_H
#include "device.h"
#include "buffer.h"
#include "dma_api.h"
#if DEVICE_SERIAL
#define SERIAL_EVENT_TX_SHIFT (2)
#define SERIAL_EVENT_RX_SHIFT (8)
#define SERIAL_EVENT_TX_MASK (0x00FC)
#define SERIAL_EVENT_RX_MASK (0x3F00)
#define SERIAL_EVENT_ERROR (1 << 1)
/**
* @defgroup SerialTXEvents Serial TX Events Macros
*
* @{
*/
#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0))
#define SERIAL_EVENT_TX_ALL (SERIAL_EVENT_TX_COMPLETE)
/**@}*/
/**
* @defgroup SerialRXEvents Serial RX Events Macros
*
* @{
*/
#define SERIAL_EVENT_RX_COMPLETE (1 << (SERIAL_EVENT_RX_SHIFT + 0))
#define SERIAL_EVENT_RX_OVERRUN_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 1))
#define SERIAL_EVENT_RX_FRAMING_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 2))
#define SERIAL_EVENT_RX_PARITY_ERROR (1 << (SERIAL_EVENT_RX_SHIFT + 3))
#define SERIAL_EVENT_RX_OVERFLOW (1 << (SERIAL_EVENT_RX_SHIFT + 4))
#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5))
#define SERIAL_EVENT_RX_ALL (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \
SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \
SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH)
/**@}*/
#define SERIAL_RESERVED_CHAR_MATCH (255)
typedef enum {
ParityNone = 0,
ParityOdd = 1,
ParityEven = 2,
ParityForced1 = 3,
ParityForced0 = 4
} SerialParity;
typedef enum {
RxIrq,
TxIrq
} SerialIrq;
typedef enum {
FlowControlNone,
FlowControlRTS,
FlowControlCTS,
FlowControlRTSCTS
} FlowControl;
typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
#if DEVICE_SERIAL_ASYNCH
/** Asynch serial HAL structure
*/
typedef struct {
struct serial_s serial; /**< Target specific serial structure */
struct buffer_s tx_buff; /**< TX buffer */
struct buffer_s rx_buff; /**< RX buffer */
uint8_t char_match; /**< Character to be matched */
uint8_t char_found; /**< State of the matched character */
} serial_t;
#else
/** Non-asynch serial HAL structure
*/
typedef struct serial_s serial_t;
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup hal_GeneralSerial Serial Configuration Functions
* @{
*/
/** Initialize the serial peripheral. It sets the default parameters for serial
* peripheral, and configures its specifieds pins.
*
* @param obj The serial object
* @param tx The TX pin name
* @param rx The RX pin name
*/
void serial_init(serial_t *obj, PinName tx, PinName rx);
/** Release the serial peripheral, not currently invoked. It requires further
* resource management.
*
* @param obj The serial object
*/
void serial_free(serial_t *obj);
/** Configure the baud rate
*
* @param obj The serial object
* @param baudrate The baud rate to be configured
*/
void serial_baud(serial_t *obj, int baudrate);
/** Configure the format. Set the number of bits, parity and the number of stop bits
*
* @param obj The serial object
* @param data_bits The number of data bits
* @param parity The parity
* @param stop_bits The number of stop bits
*/
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
/** The serial interrupt handler registration
*
* @param obj The serial object
* @param handler The interrupt handler which will be invoked when the interrupt fires
* @param id The SerialBase object
*/
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
/** Configure serial interrupt. This function is used for word-approach
*
* @param obj The serial object
* @param irq The serial IRQ type (RX or TX)
* @param enable Set to non-zero to enable events, or zero to disable them
*/
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable);
/** Get character. This is a blocking call, waiting for a character
*
* @param obj The serial object
*/
int serial_getc(serial_t *obj);
/** Send a character. This is a blocking call, waiting for a peripheral to be available
* for writing
*
* @param obj The serial object
* @param c The character to be sent
*/
void serial_putc(serial_t *obj, int c);
/** Check if the serial peripheral is readable
*
* @param obj The serial object
* @return Non-zero value if a character can be read, 0 if nothing to read
*/
int serial_readable(serial_t *obj);
/** Check if the serial peripheral is writable
*
* @param obj The serial object
* @return Non-zero value if a character can be written, 0 otherwise.
*/
int serial_writable(serial_t *obj);
/** Clear the serial peripheral
*
* @param obj The serial object
*/
void serial_clear(serial_t *obj);
/** Set the break
*
* @param obj The serial object
*/
void serial_break_set(serial_t *obj);
/** Clear the break
*
* @param obj The serial object
*/
void serial_break_clear(serial_t *obj);
/** Configure the TX pin for UART function.
*
* @param tx The pin name used for TX
*/
void serial_pinout_tx(PinName tx);
/** Configure the serial for the flow control. It sets flow control in the hardware
* if a serial peripheral supports it, otherwise software emulation is used.
*
* @param obj The serial object
* @param type The type of the flow control. Look at the available FlowControl types.
* @param rxflow The TX pin name
* @param txflow The RX pin name
*/
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
#if DEVICE_SERIAL_ASYNCH
/**@}*/
/**
* \defgroup hal_AsynchSerial Asynchronous Serial Hardware Abstraction Layer
* @{
*/
/** Begin asynchronous TX transfer. The used buffer is specified in the serial object,
* tx_buff
*
* @param obj The serial object
* @param tx The transmit buffer
* @param tx_length The number of bytes to transmit
* @param tx_width Deprecated argument
* @param handler The serial handler
* @param event The logical OR of events to be registered
* @param hint A suggestion for how to use DMA with this transfer
* @return Returns number of data transfered, otherwise returns 0
*/
int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint);
/** Begin asynchronous RX transfer (enable interrupt for data collecting)
* The used buffer is specified in the serial object - rx_buff
*
* @param obj The serial object
* @param rx The receive buffer
* @param rx_length The number of bytes to receive
* @param rx_width Deprecated argument
* @param handler The serial handler
* @param event The logical OR of events to be registered
* @param handler The serial handler
* @param char_match A character in range 0-254 to be matched
* @param hint A suggestion for how to use DMA with this transfer
*/
void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint);
/** Attempts to determine if the serial peripheral is already in use for TX
*
* @param obj The serial object
* @return Non-zero if the RX transaction is ongoing, 0 otherwise
*/
uint8_t serial_tx_active(serial_t *obj);
/** Attempts to determine if the serial peripheral is already in use for RX
*
* @param obj The serial object
* @return Non-zero if the RX transaction is ongoing, 0 otherwise
*/
uint8_t serial_rx_active(serial_t *obj);
/** The asynchronous TX and RX handler.
*
* @param obj The serial object
* @return Returns event flags if an RX transfer termination condition was met; otherwise returns 0
*/
int serial_irq_handler_asynch(serial_t *obj);
/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and
* flushes the TX hardware buffer if TX FIFO is used
*
* @param obj The serial object
*/
void serial_tx_abort_asynch(serial_t *obj);
/** Abort the ongoing RX transaction. It disables the enabled interrupt for RX and
* flushes the RX hardware buffer if RX FIFO is used
*
* @param obj The serial object
*/
void serial_rx_abort_asynch(serial_t *obj);
/**@}*/
#endif
#ifdef __cplusplus
}
#endif
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_SPI_API_H
#define MBED_SPI_API_H
#include "device.h"
#include "dma_api.h"
#include "buffer.h"
#if DEVICE_SPI
#define SPI_EVENT_ERROR (1 << 1)
#define SPI_EVENT_COMPLETE (1 << 2)
#define SPI_EVENT_RX_OVERFLOW (1 << 3)
#define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
#define SPI_FILL_WORD (0xFFFF)
#if DEVICE_SPI_ASYNCH
/** Asynch SPI HAL structure
*/
typedef struct {
struct spi_s spi; /**< Target specific SPI structure */
struct buffer_s tx_buff; /**< Tx buffer */
struct buffer_s rx_buff; /**< Rx buffer */
} spi_t;
#else
/** Non-asynch SPI HAL structure
*/
typedef struct spi_s spi_t;
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup hal_GeneralSPI SPI Configuration Functions
* @{
*/
/** Initialize the SPI peripheral
*
* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
* @param[out] obj The SPI object to initialize
* @param[in] mosi The pin to use for MOSI
* @param[in] miso The pin to use for MISO
* @param[in] sclk The pin to use for SCLK
* @param[in] ssel The pin to use for SSEL
*/
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
/** Release a SPI object
*
* TODO: spi_free is currently unimplemented
* This will require reference counting at the C++ level to be safe
*
* Return the pins owned by the SPI object to their reset state
* Disable the SPI peripheral
* Disable the SPI clock
* @param[in] obj The SPI object to deinitialize
*/
void spi_free(spi_t *obj);
/** Configure the SPI format
*
* Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
* The default bit order is MSB.
* @param[in,out] obj The SPI object to configure
* @param[in] bits The number of bits per frame
* @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
* @param[in] slave Zero for master mode or non-zero for slave mode
*/
void spi_format(spi_t *obj, int bits, int mode, int slave);
/** Set the SPI baud rate
*
* Actual frequency may differ from the desired frequency due to available dividers and bus clock
* Configures the SPI peripheral's baud rate
* @param[in,out] obj The SPI object to configure
* @param[in] hz The baud rate in Hz
*/
void spi_frequency(spi_t *obj, int hz);
/**@}*/
/**
* \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
* @{
*/
/** Write a byte out in master mode and receive a value
*
* @param[in] obj The SPI peripheral to use for sending
* @param[in] value The value to send
* @return Returns the value received during send
*/
int spi_master_write(spi_t *obj, int value);
/** Check if a value is available to read
*
* @param[in] obj The SPI peripheral to check
* @return non-zero if a value is available
*/
int spi_slave_receive(spi_t *obj);
/** Get a received value out of the SPI receive buffer in slave mode
*
* Blocks until a value is available
* @param[in] obj The SPI peripheral to read
* @return The value received
*/
int spi_slave_read(spi_t *obj);
/** Write a value to the SPI peripheral in slave mode
*
* Blocks until the SPI peripheral can be written to
* @param[in] obj The SPI peripheral to write
* @param[in] value The value to write
*/
void spi_slave_write(spi_t *obj, int value);
/** Checks if the specified SPI peripheral is in use
*
* @param[in] obj The SPI peripheral to check
* @return non-zero if the peripheral is currently transmitting
*/
int spi_busy(spi_t *obj);
/** Get the module number
*
* @param[in] obj The SPI peripheral to check
* @return The module number
*/
uint8_t spi_get_module(spi_t *obj);
/**@}*/
#if DEVICE_SPI_ASYNCH
/**
* \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
* @{
*/
/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
*
* @param[in] obj The SPI object that holds the transfer information
* @param[in] tx The transmit buffer
* @param[in] tx_length The number of bytes to transmit
* @param[in] rx The receive buffer
* @param[in] rx_length The number of bytes to receive
* @param[in] bit_width The bit width of buffer words
* @param[in] event The logical OR of events to be registered
* @param[in] handler SPI interrupt handler
* @param[in] hint A suggestion for how to use DMA with this transfer
*/
void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
/** The asynchronous IRQ handler
*
* Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
* conditions, such as buffer overflows or transfer complete.
* @param[in] obj The SPI object that holds the transfer information
* @return Event flags if a transfer termination condition was met; otherwise 0.
*/
uint32_t spi_irq_handler_asynch(spi_t *obj);
/** Attempts to determine if the SPI peripheral is already in use
*
* If a temporary DMA channel has been allocated, peripheral is in use.
* If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
* channel were allocated.
* If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
* if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
* there are any bytes in the FIFOs.
* @param[in] obj The SPI object to check for activity
* @return Non-zero if the SPI port is active or zero if it is not.
*/
uint8_t spi_active(spi_t *obj);
/** Abort an SPI transfer
*
* @param obj The SPI peripheral to stop
*/
void spi_abort_asynch(spi_t *obj);
#endif
/**@}*/
#ifdef __cplusplus
}
#endif // __cplusplus
#endif // SPI_DEVICE
#endif // MBED_SPI_API_H

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/******************************************************************************
* @file: system_RDA5991H.h
* @purpose: CMSIS Cortex-M4 Device Peripheral Access Layer Header File
* for the RDA RDA5991H Device Series
* @version: V1.02
* @date: 07. July 2016
*----------------------------------------------------------------------------
*
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* ARM Limited (ARM) is supplying this software for use with Cortex-M3
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_RDA5991H_H
#define __SYSTEM_RDA5991H_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t AHBBusClock; /*!< AHB Bus Clock Frequency (Bus Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_RDA5991H_H */

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/** \addtogroup hal */
/** @{*/
/* mbed Microcontroller Library
* Copyright (c) 2016 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef TRNG_API_H
#define TRNG_API_H
#include <stddef.h>
#include "device.h"
/** TRNG HAL structure. trng_s is declared in the target's HAL
*/
typedef struct trng_s trng_t;
#ifdef __cplusplus
extern "C" {
#endif
/**
* \defgroup hal_trng TRNG hal functions
* @{
*/
/** Initialize the TRNG peripheral
*
* @param obj The TRNG object
*/
void trng_init(trng_t *obj);
/** Deinitialize the TRNG peripheral
*
* @param obj The TRNG object
*/
void trng_free(trng_t *obj);
/** Get random data from TRNG peripheral
*
* @param obj The TRNG object
* @param output The pointer to an output array
* @param length The size of output data, to avoid buffer overwrite
* @param output_length The length of generated data
* @return 0 success, -1 fail
*/
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length);
int rda_get_random_bytes(unsigned char *output, size_t len);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif
/** @}*/

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/*
* Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __MBED_UTIL_CRITICAL_H__
#define __MBED_UTIL_CRITICAL_H__
#include <stdbool.h>
#include <stdint.h>
#include <stddef.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Determine the current interrupts enabled state
*
* This function can be called to determine whether or not interrupts are currently enabled.
* \note
* NOTE:
* This function works for both cortex-A and cortex-M, although the underlyng implementation
* differs.
* @return true if interrupts are enabled, false otherwise
*/
bool core_util_are_interrupts_enabled(void);
/** Mark the start of a critical section
*
* This function should be called to mark the start of a critical section of code.
* \note
* NOTES:
* 1) The use of this style of critical section is targetted at C based implementations.
* 2) These critical sections can be nested.
* 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
* section) will be preserved on exit from the section.
* 4) This implementation will currently only work on code running in privileged mode.
*/
void core_util_critical_section_enter(void);
/** Mark the end of a critical section
*
* This function should be called to mark the end of a critical section of code.
* \note
* NOTES:
* 1) The use of this style of critical section is targetted at C based implementations.
* 2) These critical sections can be nested.
* 3) The interrupt enable state on entry to the first critical section (of a nested set, or single
* section) will be preserved on exit from the section.
* 4) This implementation will currently only work on code running in privileged mode.
*/
void core_util_critical_section_exit(void);
/**
* Atomic compare and set. It compares the contents of a memory location to a
* given value and, only if they are the same, modifies the contents of that
* memory location to a given new value. This is done as a single atomic
* operation. The atomicity guarantees that the new value is calculated based on
* up-to-date information; if the value had been updated by another thread in
* the meantime, the write would fail due to a mismatched expectedCurrentValue.
*
* Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
* you to the article on compare-and swap].
*
* @param ptr The target memory location.
* @param[in,out] expectedCurrentValue A pointer to some location holding the
* expected current value of the data being set atomically.
* The computed 'desiredValue' should be a function of this current value.
* @Note: This is an in-out parameter. In the
* failure case of atomic_cas (where the
* destination isn't set), the pointee of expectedCurrentValue is
* updated with the current value.
* @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
*
* @return true if the memory location was atomically
* updated with the desired value (after verifying
* that it contained the expectedCurrentValue),
* false otherwise. In the failure case,
* exepctedCurrentValue is updated with the new
* value of the target memory location.
*
* pseudocode:
* function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
* if *p != *old {
* *old = *p
* return false
* }
* *p = new
* return true
* }
*
* @Note: In the failure case (where the destination isn't set), the value
* pointed to by expectedCurrentValue is still updated with the current value.
* This property helps writing concise code for the following incr:
*
* function incr(p : pointer to int, a : int) returns int {
* done = false
* value = *p // This fetch operation need not be atomic.
* while not done {
* done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
* }
* return value + a
* }
*/
bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
/**
* Atomic compare and set. It compares the contents of a memory location to a
* given value and, only if they are the same, modifies the contents of that
* memory location to a given new value. This is done as a single atomic
* operation. The atomicity guarantees that the new value is calculated based on
* up-to-date information; if the value had been updated by another thread in
* the meantime, the write would fail due to a mismatched expectedCurrentValue.
*
* Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
* you to the article on compare-and swap].
*
* @param ptr The target memory location.
* @param[in,out] expectedCurrentValue A pointer to some location holding the
* expected current value of the data being set atomically.
* The computed 'desiredValue' should be a function of this current value.
* @Note: This is an in-out parameter. In the
* failure case of atomic_cas (where the
* destination isn't set), the pointee of expectedCurrentValue is
* updated with the current value.
* @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
*
* @return true if the memory location was atomically
* updated with the desired value (after verifying
* that it contained the expectedCurrentValue),
* false otherwise. In the failure case,
* exepctedCurrentValue is updated with the new
* value of the target memory location.
*
* pseudocode:
* function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
* if *p != *old {
* *old = *p
* return false
* }
* *p = new
* return true
* }
*
* @Note: In the failure case (where the destination isn't set), the value
* pointed to by expectedCurrentValue is still updated with the current value.
* This property helps writing concise code for the following incr:
*
* function incr(p : pointer to int, a : int) returns int {
* done = false
* value = *p // This fetch operation need not be atomic.
* while not done {
* done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
* }
* return value + a
* }
*/
bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
/**
* Atomic compare and set. It compares the contents of a memory location to a
* given value and, only if they are the same, modifies the contents of that
* memory location to a given new value. This is done as a single atomic
* operation. The atomicity guarantees that the new value is calculated based on
* up-to-date information; if the value had been updated by another thread in
* the meantime, the write would fail due to a mismatched expectedCurrentValue.
*
* Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
* you to the article on compare-and swap].
*
* @param ptr The target memory location.
* @param[in,out] expectedCurrentValue A pointer to some location holding the
* expected current value of the data being set atomically.
* The computed 'desiredValue' should be a function of this current value.
* @Note: This is an in-out parameter. In the
* failure case of atomic_cas (where the
* destination isn't set), the pointee of expectedCurrentValue is
* updated with the current value.
* @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
*
* @return true if the memory location was atomically
* updated with the desired value (after verifying
* that it contained the expectedCurrentValue),
* false otherwise. In the failure case,
* exepctedCurrentValue is updated with the new
* value of the target memory location.
*
* pseudocode:
* function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
* if *p != *old {
* *old = *p
* return false
* }
* *p = new
* return true
* }
*
* @Note: In the failure case (where the destination isn't set), the value
* pointed to by expectedCurrentValue is still updated with the current value.
* This property helps writing concise code for the following incr:
*
* function incr(p : pointer to int, a : int) returns int {
* done = false
* value = *p // This fetch operation need not be atomic.
* while not done {
* done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
* }
* return value + a
* }
*/
bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
/**
* Atomic compare and set. It compares the contents of a memory location to a
* given value and, only if they are the same, modifies the contents of that
* memory location to a given new value. This is done as a single atomic
* operation. The atomicity guarantees that the new value is calculated based on
* up-to-date information; if the value had been updated by another thread in
* the meantime, the write would fail due to a mismatched expectedCurrentValue.
*
* Refer to https://en.wikipedia.org/wiki/Compare-and-set [which may redirect
* you to the article on compare-and swap].
*
* @param ptr The target memory location.
* @param[in,out] expectedCurrentValue A pointer to some location holding the
* expected current value of the data being set atomically.
* The computed 'desiredValue' should be a function of this current value.
* @Note: This is an in-out parameter. In the
* failure case of atomic_cas (where the
* destination isn't set), the pointee of expectedCurrentValue is
* updated with the current value.
* @param[in] desiredValue The new value computed based on '*expectedCurrentValue'.
*
* @return true if the memory location was atomically
* updated with the desired value (after verifying
* that it contained the expectedCurrentValue),
* false otherwise. In the failure case,
* exepctedCurrentValue is updated with the new
* value of the target memory location.
*
* pseudocode:
* function cas(p : pointer to int, old : pointer to int, new : int) returns bool {
* if *p != *old {
* *old = *p
* return false
* }
* *p = new
* return true
* }
*
* @Note: In the failure case (where the destination isn't set), the value
* pointed to by expectedCurrentValue is still updated with the current value.
* This property helps writing concise code for the following incr:
*
* function incr(p : pointer to int, a : int) returns int {
* done = false
* value = *p // This fetch operation need not be atomic.
* while not done {
* done = atomic_cas(p, &value, value + a) // *value gets updated automatically until success
* }
* return value + a
* }
*/
bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue);
/**
* Atomic increment.
* @param valuePtr Target memory location being incremented.
* @param delta The amount being incremented.
* @return The new incremented value.
*/
uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta);
/**
* Atomic increment.
* @param valuePtr Target memory location being incremented.
* @param delta The amount being incremented.
* @return The new incremented value.
*/
uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta);
/**
* Atomic increment.
* @param valuePtr Target memory location being incremented.
* @param delta The amount being incremented.
* @return The new incremented value.
*/
uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta);
/**
* Atomic increment.
* @param valuePtr Target memory location being incremented.
* @param delta The amount being incremented in bytes.
* @return The new incremented value.
*
* @note The type of the pointer argument is not taken into account
* and the pointer is incremented by bytes.
*/
void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta);
/**
* Atomic decrement.
* @param valuePtr Target memory location being decremented.
* @param delta The amount being decremented.
* @return The new decremented value.
*/
uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta);
/**
* Atomic decrement.
* @param valuePtr Target memory location being decremented.
* @param delta The amount being decremented.
* @return The new decremented value.
*/
uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta);
/**
* Atomic decrement.
* @param valuePtr Target memory location being decremented.
* @param delta The amount being decremented.
* @return The new decremented value.
*/
uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta);
/**
* Atomic decrement.
* @param valuePtr Target memory location being decremented.
* @param delta The amount being decremented in bytes.
* @return The new decremented value.
*
* @note The type of the pointer argument is not taken into account
* and the pointer is decremented by bytes
*/
void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta);
#ifdef __cplusplus
} // extern "C"
#endif
#endif // __MBED_UTIL_CRITICAL_H__

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "device.h"
#include "mbed_interface.h"
#include "critical.h"
void mbed_assert_internal(const char *expr, const char *file, int line)
{
core_util_critical_section_enter();
mbed_error_printf("mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
mbed_die();
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_ASSERT_H
#define MBED_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
* This function is active only if NDEBUG is not defined prior to including this
* assert header file.
* In case of MBED_ASSERT failing condition, error() is called with the assertation message.
* @param expr Expresion to be checked.
* @param file File where assertation failed.
* @param line Failing assertation line number.
*/
void mbed_assert_internal(const char *expr, const char *file, int line);
#ifdef __cplusplus
}
#endif
#ifdef NDEBUG
#define MBED_ASSERT(expr) ((void)0)
#else
#define MBED_ASSERT(expr) \
do { \
if (!(expr)) { \
mbed_assert_internal(#expr, __FILE__, __LINE__); \
} \
} while (0)
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
//#include "gpio_api.h"
//#include "wait_api.h"
//#include "toolchain.h"
#include "mbed_interface.h"
#include "critical.h"
#include "serial_api.h"
#if DEVICE_SERIAL
extern int stdio_uart_inited;
extern serial_t stdio_uart;
#endif
__attribute__((weak)) void mbed_die(void) {
while (1);
}
#if 0
WEAK void mbed_die(void) {
#if !defined (NRF51_H) && !defined(TARGET_EFM32)
core_util_critical_section_enter();
#endif
#if (DEVICE_ERROR_RED == 1)
gpio_t led_red; gpio_init_out(&led_red, LED_RED);
#elif (DEVICE_ERROR_PATTERN == 1)
gpio_t led_1; gpio_init_out(&led_1, LED1);
gpio_t led_2; gpio_init_out(&led_2, LED2);
gpio_t led_3; gpio_init_out(&led_3, LED3);
gpio_t led_4; gpio_init_out(&led_4, LED4);
#endif
while (1) {
#if (DEVICE_ERROR_RED == 1)
gpio_write(&led_red, 1);
#elif (DEVICE_ERROR_PATTERN == 1)
gpio_write(&led_1, 1);
gpio_write(&led_2, 0);
gpio_write(&led_3, 0);
gpio_write(&led_4, 1);
#endif
wait_ms(150);
#if (DEVICE_ERROR_RED == 1)
gpio_write(&led_red, 0);
#elif (DEVICE_ERROR_PATTERN == 1)
gpio_write(&led_1, 0);
gpio_write(&led_2, 1);
gpio_write(&led_3, 1);
gpio_write(&led_4, 0);
#endif
wait_ms(150);
}
}
#endif
void mbed_error_printf(const char* format, ...) {
va_list arg;
va_start(arg, format);
mbed_error_vfprintf(format, arg);
va_end(arg);
}
void mbed_error_vfprintf(const char * format, va_list arg) {
#if DEVICE_SERIAL
core_util_critical_section_enter();
char buffer[128];
int size = vsprintf(buffer, format, arg);
if (size > 0) {
if (!stdio_uart_inited) {
serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
}
for (int i = 0; i < size; i++) {
serial_putc(&stdio_uart, buffer[i]);
}
}
core_util_critical_section_exit();
#endif
}

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/*
* Copyright (c) 2015-2016, ARM Limited, All Rights Reserved
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "critical.h"
#include "cmsis.h"
#include "mbed_assert.h"
#define EXCLUSIVE_ACCESS (!defined (__CORTEX_M0) && !defined (__CORTEX_M0PLUS))
static volatile uint32_t interrupt_enable_counter = 0;
static volatile bool critical_interrupts_disabled = false;
bool core_util_are_interrupts_enabled(void)
{
#if defined(__CORTEX_A9)
return ((__get_CPSR() & 0x80) == 0);
#else
return ((__get_PRIMASK() & 0x1) == 0);
#endif
}
void core_util_critical_section_enter(void)
{
bool interrupts_disabled = !core_util_are_interrupts_enabled();
__disable_irq();
/* Save the interrupt disabled state as it was prior to any nested critical section lock use */
if (!interrupt_enable_counter) {
critical_interrupts_disabled = interrupts_disabled;
}
/* If the interrupt_enable_counter overflows or we are in a nested critical section and interrupts
are enabled, then something has gone badly wrong thus assert an error.
*/
MBED_ASSERT(interrupt_enable_counter < UINT32_MAX);
// FIXME
#ifndef FEATURE_UVISOR
if (interrupt_enable_counter > 0) {
MBED_ASSERT(interrupts_disabled);
}
#else
#warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
#endif /* FEATURE_UVISOR */
interrupt_enable_counter++;
}
void core_util_critical_section_exit(void)
{
/* If critical_section_enter has not previously been called, do nothing */
if (interrupt_enable_counter) {
// FIXME
#ifndef FEATURE_UVISOR
bool interrupts_disabled = !core_util_are_interrupts_enabled(); /* get the current interrupt disabled state */
MBED_ASSERT(interrupts_disabled); /* Interrupts must be disabled on invoking an exit from a critical section */
#else
#warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
#endif /* FEATURE_UVISOR */
interrupt_enable_counter--;
/* Only re-enable interrupts if we are exiting the last of the nested critical sections and
interrupts were enabled on entry to the first critical section.
*/
if (!interrupt_enable_counter && !critical_interrupts_disabled) {
__enable_irq();
}
}
}
#if EXCLUSIVE_ACCESS
/* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
#if defined (__CC_ARM)
#pragma diag_suppress 3731
#endif
bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
{
uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr);
if (currentValue != *expectedCurrentValue) {
*expectedCurrentValue = currentValue;
__CLREX();
return false;
}
return !__STREXB(desiredValue, (volatile uint8_t*)ptr);
}
bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
{
uint16_t currentValue = __LDREXH((volatile uint16_t*)ptr);
if (currentValue != *expectedCurrentValue) {
*expectedCurrentValue = currentValue;
__CLREX();
return false;
}
return !__STREXH(desiredValue, (volatile uint16_t*)ptr);
}
bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
{
uint32_t currentValue = __LDREXW((volatile uint32_t*)ptr);
if (currentValue != *expectedCurrentValue) {
*expectedCurrentValue = currentValue;
__CLREX();
return false;
}
return !__STREXW(desiredValue, (volatile uint32_t*)ptr);
}
uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
{
uint8_t newValue;
do {
newValue = __LDREXB((volatile uint8_t*)valuePtr) + delta;
} while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
return newValue;
}
uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
{
uint16_t newValue;
do {
newValue = __LDREXH((volatile uint16_t*)valuePtr) + delta;
} while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
return newValue;
}
uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
{
uint32_t newValue;
do {
newValue = __LDREXW((volatile uint32_t*)valuePtr) + delta;
} while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
return newValue;
}
uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
{
uint8_t newValue;
do {
newValue = __LDREXB((volatile uint8_t*)valuePtr) - delta;
} while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
return newValue;
}
uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
{
uint16_t newValue;
do {
newValue = __LDREXH((volatile uint16_t*)valuePtr) - delta;
} while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
return newValue;
}
uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
{
uint32_t newValue;
do {
newValue = __LDREXW((volatile uint32_t*)valuePtr) - delta;
} while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
return newValue;
}
#else
bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
{
bool success;
uint8_t currentValue;
core_util_critical_section_enter();
currentValue = *ptr;
if (currentValue == *expectedCurrentValue) {
*ptr = desiredValue;
success = true;
} else {
*expectedCurrentValue = currentValue;
success = false;
}
core_util_critical_section_exit();
return success;
}
bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
{
bool success;
uint16_t currentValue;
core_util_critical_section_enter();
currentValue = *ptr;
if (currentValue == *expectedCurrentValue) {
*ptr = desiredValue;
success = true;
} else {
*expectedCurrentValue = currentValue;
success = false;
}
core_util_critical_section_exit();
return success;
}
bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
{
bool success;
uint32_t currentValue;
core_util_critical_section_enter();
currentValue = *ptr;
if (currentValue == *expectedCurrentValue) {
*ptr = desiredValue;
success = true;
} else {
*expectedCurrentValue = currentValue;
success = false;
}
core_util_critical_section_exit();
return success;
}
uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
{
uint8_t newValue;
core_util_critical_section_enter();
newValue = *valuePtr + delta;
*valuePtr = newValue;
core_util_critical_section_exit();
return newValue;
}
uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
{
uint16_t newValue;
core_util_critical_section_enter();
newValue = *valuePtr + delta;
*valuePtr = newValue;
core_util_critical_section_exit();
return newValue;
}
uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
{
uint32_t newValue;
core_util_critical_section_enter();
newValue = *valuePtr + delta;
*valuePtr = newValue;
core_util_critical_section_exit();
return newValue;
}
uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
{
uint8_t newValue;
core_util_critical_section_enter();
newValue = *valuePtr - delta;
*valuePtr = newValue;
core_util_critical_section_exit();
return newValue;
}
uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
{
uint16_t newValue;
core_util_critical_section_enter();
newValue = *valuePtr - delta;
*valuePtr = newValue;
core_util_critical_section_exit();
return newValue;
}
uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
{
uint32_t newValue;
core_util_critical_section_enter();
newValue = *valuePtr - delta;
*valuePtr = newValue;
core_util_critical_section_exit();
return newValue;
}
#endif
bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue) {
return core_util_atomic_cas_u32(
(uint32_t *)ptr,
(uint32_t *)expectedCurrentValue,
(uint32_t)desiredValue);
}
void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta) {
return (void *)core_util_atomic_incr_u32((uint32_t *)valuePtr, (uint32_t)delta);
}
void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta) {
return (void *)core_util_atomic_decr_u32((uint32_t *)valuePtr, (uint32_t)delta);
}

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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdlib.h>
#include <stdarg.h>
#include "device.h"
//#include "toolchain.h"
#include "mbed_error.h"
#include "mbed_interface.h"
#if DEVICE_STDIO_MESSAGES
#include <stdio.h>
#endif
__attribute__((weak)) void error(const char* format, ...) {
va_list arg;
va_start(arg, format);
mbed_error_vfprintf(format, arg);
va_end(arg);
exit(1);
}

66
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_ERROR_H
#define MBED_ERROR_H
/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
*
* @code
* #error "That shouldn't have happened!"
* @endcode
*
* If the compiler evaluates this line, it will report the error and stop the compile.
*
* For example, you could use this to check some user-defined compile-time variables:
*
* @code
* #define NUM_PORTS 7
* #if (NUM_PORTS > 4)
* #error "NUM_PORTS must be less than 4"
* #endif
* @endcode
*
* Reporting Run-Time Errors:
* To generate a fatal run-time error, you can use the mbed error() function.
*
* @code
* error("That shouldn't have happened!");
* @endcode
*
* If the mbed running the program executes this function, it will print the
* message via the USB serial port, and then die with the blue lights of death!
*
* The message can use printf-style formatting, so you can report variables in the
* message too. For example, you could use this to check a run-time condition:
*
* @code
* if(x >= 5) {
* error("expected x to be less than 5, but got %d", x);
* }
* #endcode
*/
#ifdef __cplusplus
extern "C" {
#endif
void error(const char* format, ...);
#ifdef __cplusplus
}
#endif
#endif

130
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_INTERFACE_H
#define MBED_INTERFACE_H
#include <stdarg.h>
#include "device.h"
/* Mbed interface mac address
* if MBED_MAC_ADD_x are zero, interface uid sets mac address,
* otherwise MAC_ADD_x are used.
*/
#define MBED_MAC_ADDR_INTERFACE 0x00
#define MBED_MAC_ADDR_0 MBED_MAC_ADDR_INTERFACE
#define MBED_MAC_ADDR_1 MBED_MAC_ADDR_INTERFACE
#define MBED_MAC_ADDR_2 MBED_MAC_ADDR_INTERFACE
#define MBED_MAC_ADDR_3 MBED_MAC_ADDR_INTERFACE
#define MBED_MAC_ADDR_4 MBED_MAC_ADDR_INTERFACE
#define MBED_MAC_ADDR_5 MBED_MAC_ADDR_INTERFACE
#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
#ifdef __cplusplus
extern "C" {
#endif
#if DEVICE_SEMIHOST
/** Functions to control the mbed interface
*
* mbed Microcontrollers have a built-in interface to provide functionality such as
* drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
* system. These functions provide means to control the interface suing semihost
* calls it supports.
*/
/** Determine whether the mbed interface is connected, based on whether debug is enabled
*
* @returns
* 1 if interface is connected,
* 0 otherwise
*/
int mbed_interface_connected(void);
/** Instruct the mbed interface to reset, as if the reset button had been pressed
*
* @returns
* 1 if successful,
* 0 otherwise (e.g. interface not present)
*/
int mbed_interface_reset(void);
/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
* The interface will still support the USB serial aspect
*
* @returns
* 0 if successful,
* -1 otherwise (e.g. interface not present)
*/
int mbed_interface_disconnect(void);
/** This will disconnect the debug aspect of the interface, and if the USB cable is not
* connected, also power down the interface. If the USB cable is connected, the interface
* will remain powered up and visible to the host
*
* @returns
* 0 if successful,
* -1 otherwise (e.g. interface not present)
*/
int mbed_interface_powerdown(void);
/** This returns a string containing the 32-character UID of the mbed interface
* This is a weak function that can be overwritten if required
*
* @param uid A 33-byte array to write the null terminated 32-byte string
*
* @returns
* 0 if successful,
* -1 otherwise (e.g. interface not present)
*/
int mbed_interface_uid(char *uid);
#endif
/** This returns a unique 6-byte MAC address, based on the interface UID
* If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
*
* This is a weak function that can be overwritten if you want to provide your own mechanism to
* provide a MAC address.
*
* @param mac A 6-byte array to write the MAC address
*/
void mbed_mac_address(char *mac);
/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
*/
void mbed_die(void);
/** Print out an error message. This is typically called when
* hanlding a crash.
*
* @Note Synchronization level: Interrupt safe
*/
void mbed_error_printf(const char* format, ...);
/** Print out an error message. Similar to mbed_error_printf
* but uses a va_list.
*
* @Note Synchronization level: Interrupt safe
*/
void mbed_error_vfprintf(const char * format, va_list arg);
#ifdef __cplusplus
}
#endif
#endif

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Living_SDK/platform/mcu/rda5981x/rda5981x.mk Executable file
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NAME := RDA5981x
HOST_OPENOCD := rda5981x
$(NAME)_TYPE := kernel
$(NAME)_COMPONENTS += platform/arch/arm/armv7m
$(NAME)_COMPONENTS += libc rhino hal netmgr framework.common cjson cli digest_algorithm protocols.net
GLOBAL_DEFINES += DEVICE_SERIAL=1
GLOBAL_DEFINES += DEVICE_STDIO_MESSAGES=1
GLOBAL_DEFINES += DEVICE_SPI=1
GLOBAL_DEFINES += DEVICE_FLASH=1
GLOBAL_DEFINES += TARGET_FLASH_CMSIS_ALGO=1
GLOBAL_DEFINES += RDA5991H_HW_VER=4
GLOBAL_DEFINES += CONFIG_AOS_CLI_STACK_SIZE=4096
GLOBAL_DEFINES += RHINO_CONFIG_TASK_STACK_CUR_CHECK=1
GLOBAL_INCLUDES += ../../../kernel/protocols/net/include
GLOBAL_INCLUDES += include \
startup \
driver \
cmsis \
middleware \
wifi/inc \
wifi/inc/arch \
wifi/inc/driver \
wifi/inc/lib \
wifi/inc/wpa \
feature/sysdata
GLOBAL_CFLAGS += -DRDA5981x
GLOBAL_CFLAGS += -mcpu=cortex-m4 \
-march=armv7-m \
-mthumb -mthumb-interwork \
-mlittle-endian
GLOBAL_CFLAGS += -w
GLOBAL_LDFLAGS += -mcpu=cortex-m4 \
-mthumb -mthumb-interwork \
-mlittle-endian \
-nostartfiles \
--specs=nosys.specs \
$(CLIB_LDFLAGS_NANO_FLOAT)
#-libwifi_sta_ap_gcc
GLOBAL_LDFLAGS += platform/mcu/rda5981x/wifi/lib/TOOLCHAIN_GCC_ARM/libwifi_sta_ap.a
$(NAME)_CFLAGS += -Wall -Werror -Wno-unused-variable -Wno-unused-parameter -Wno-implicit-function-declaration
$(NAME)_CFLAGS += -Wno-type-limits -Wno-sign-compare -Wno-pointer-sign -Wno-uninitialized
$(NAME)_CFLAGS += -Wno-return-type -Wno-unused-function -Wno-unused-but-set-variable
$(NAME)_CFLAGS += -Wno-unused-value -Wno-strict-aliasing
#GLOBAL_LDFLAGS += -T platform/mcu/rda5981x/rda5981x.ld
$(NAME)_SOURCES := startup/soc_init.c \
aos/aos.c \
aos/soc_impl.c \
hal/system_rda5981x.c \
hal/rda_ccfg_api.c \
hal/hw.c \
hal/uart.c \
hal/gpio.c \
hal/spi.c \
hal/flash.c \
hal/wdg.c \
hal/rda_trng_api.c \
hal/wifi_port.c \
hal/trng_api.c \
hal/timer_isr.c \
hal/timer.c \
hal/rtc.c
$(NAME)_SOURCES += cmsis/cmsis_nvic.c \
driver/serial_api.c \
driver/gpio_api.c \
driver/mbed_pinmap_common.c \
driver/mbed_gpio.c \
driver/pinmap.c \
driver/spi_api.c \
driver/flash_api.c \
driver/rda_flash.c \
driver/flash_common_algo.c \
driver/pwmout_api.c \
middleware/mbed_assert.c \
middleware/mbed_board.c \
middleware/mbed_critical.c \
middleware/mbed_error.c
$(NAME)_SOURCES += wifi/rda_sys_wrapper.c \
wifi/rda59xx_daemon.c \
wifi/rda59xx_lwip.c \
$(NAME)_SOURCES += feature/sysdata/rda5981_sys_data.c
$(NAME)_SOURCES += hal/pwrmgmt_hal/board_cpu_pwr.c \
hal/pwrmgmt_hal/board_cpu_pwr_systick.c \
hal/pwrmgmt_hal/board_lp_ticker.c
GLOBAL_INCLUDES += ../include
GLOBAL_INCLUDES += ../../../include/hal/soc
#GLOBAL_INCLUDES += ../../../kernel/protocols/net/include
#GLOBAL_INCLUDES += ../../../kernel/protocols/net/include/lwip
$(NAME)_INCLUDES += .
$(NAME)_INCLUDES += ../include
$(NAME)_INCLUDES += ../../../include/hal/soc
#$(NAME)_INCLUDES += ../../../kernel/protocols/net/include
#$(NAME)_INCLUDES += ../../../kernel/protocols/net/include/lwip

3
Living_SDK/platform/mcu/rda5981x/readme.txt Normal file
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1.为避免修改阿里公共代码，目前将HAL_PARTITION_SYS_DATA重定义为HAL_PARTITION_MAX，相关修改在board\uno-81a\board.c,board\uno-81c\board.c以及platform\mcu\rda5981x\feature\sysdata\rda5981_sys_data.c中
实际使用时可注释掉相关代码并将HAL_PARTITION_SYS_DATA添加至include\hal\soc\flash.h中的hal_partition_t。
2.如需升级Alios，只需将board\uno-81a，board\uno-81c以及platform\mcu\rda5981x拷贝至新版本相应路径即可

117
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import os
import sys
import struct
import zlib
import time
def pack_image(fw_file, version, boot_file, enc_arg, factory_fw):
fname = os.path.splitext(fw_file)
with_factory = "false"
print 'firmware file:', fw_file
print 'enc image file:', fname[0] + '.bin.lzma'
print 'bootloader:', boot_file
print 'enc arg:', enc_arg
if os.access(factory_fw, os.F_OK):
with_factory = "true"
print 'factory firmware:', factory_fw
f = file(boot_file, 'rb')
bootloader = f.read()
f.close()
f = file(fw_file, 'rb')
data_fw = f.read()
f.close()
f = file(fname[0] + '.bin.lzma', 'rb')
data_img = f.read()
f.close()
magic_img = 0xAEAE
magic_fw = 0x0000EAEA
if(enc_arg == "HF"):
encrypt_algo = 0
else:
encrypt_algo = 1
rescv_img = 0
time_fmt='%Y%m%d%H%M%S'
crc32_img = zlib.crc32(data_img, 0) & 0xFFFFFFFF
crc32_img ^= 0xFFFFFFFF
crc32_fw = zlib.crc32(data_fw, 0) & 0xFFFFFFFF
crc32_fw ^= 0xFFFFFFFF
if(enc_arg == "HF"):
version = str(crc32_fw)
else:
version = time.strftime( time_fmt, time.localtime() )
size_img = len(data_img)
size_fw = len(data_fw)
if(enc_arg == "HF"):
header_img = struct.pack("<HBB24sLL", magic_img, encrypt_algo, rescv_img, version, crc32_img, size_img)
else:
header_img = struct.pack("<HBB16sLLLL", magic_img, encrypt_algo, rescv_img, version, crc32_fw, size_fw, crc32_img, size_img)
f = file(fname[0] + '_ota.bin', "wb")
f.write(header_img)
f.write(data_img)
f.close()
i = len(bootloader)
if(i > 8192):
print 'bootloader sizeover flow!!!'
exit(1)
f = file(fname[0] + '_all.bin', "wb")
f.write(bootloader)
print 'ota image version:', version
print 'ota image size:', size_img
print 'ota image crc32: %08x' % crc32_img
print 'firmware size:', size_fw
print 'firmware crc32: %08x' % crc32_fw
print 'bootloader size:', i
while i < 8192:
i += 1
f.write("\xff")
if("true" == with_factory):
f_fact = open(factory_fw, 'r')
buffer_fact = f_fact.read()
f_fact.close()
size_fact = len(buffer_fact)
crc32_fact = zlib.crc32(buffer_fact, 0) & 0xFFFFFFFF
crc32_fact ^= 0xFFFFFFFF
magic_fact = 0x4FAC
addr_fact = 0x18095000
resv_fact = 0
header_fact = struct.pack("<L16sLLLLL", magic_fact, version, addr_fact, size_fact, crc32_fact, resv_fact, resv_fact)
i += len(header_fact)
f.write(header_fact)
elif(enc_arg != "HF"):
addr_fw = 0x18004000
resv_fw = 0
header_fw = struct.pack("<L16sLLLLL", magic_fw, version, addr_fw, size_fw, crc32_fw, resv_fw, resv_fw)
i += len(header_fw)
f.write(header_fw)
while i < 12288:
i += 1
f.write("\xff")
i += len(data_fw)
f.write(data_fw)
if("true" == with_factory):
while i < (12288 + 593920):
i += 1
f.write("\xff")
f.write(buffer_fact)
f.close()
if __name__ == "__main__":
if len(sys.argv) < 5:
print sys.argv[0], "firmware file"
exit(0)
pack_image(sys.argv[1], sys.argv[2], sys.argv[3], sys.argv[4], sys.argv[5])

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Living_SDK/platform/mcu/rda5981x/startup/soc_init.c Normal file
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#include "k_api.h"
#include "soc_init.h"
#include "hal/soc/uart.h"
#include "rda5981.h"
#include "cmsis_nvic.h"
static volatile uint8_t button_flags = 0;
static void SystemClock_Config(void);
static void SystemClock_Config(void)
{
uint32_t cnts;
/* TODO: update SystemCoreClock */
cnts = SystemCoreClock / RHINO_CONFIG_TICKS_PER_SECOND;
SysTick_Config(cnts);
}
/**
* This is the timer interrupt service routine.
*/
void SysTick_Handler(void)
{
krhino_intrpt_enter();
krhino_tick_proc();
krhino_intrpt_exit();
}
void rda_soc_init(void)
{
SystemCoreClockUpdate();
/* Configure the system clock */
SystemClock_Config();
NVIC_Remap();
}

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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __RDA59XX_SOC_H
#define __RDA59XX_SOC_H
#define __main_h__
#ifdef __cplusplus
extern "C" {
#endif
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
void rda_soc_init();
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
enum {BP_NOT_PUSHED=0, BP_SINGLE_PUSH, BP_MULTIPLE_PUSH};
/* Exported functions --------------------------------------------------------*/
void Error_Handler(void);
uint8_t Button_WaitForPush(uint32_t timeout);
void Led_On(void);
void Led_Off(void);
//extern RNG_HandleTypeDef hrng;
//extern RTC_HandleTypeDef hrtc;
#ifdef __cplusplus
}
#endif
#endif /* __RDA59XX_SOC_H */

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/*
* cc.h - Architecture environment, some compiler specific, some
* environment specific (probably should move env stuff
* to sys_arch.h.)
*
* Typedefs for the types used by lwip -
* u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
*
* Compiler hints for packing lwip's structures -
* PACK_STRUCT_FIELD(x)
* PACK_STRUCT_STRUCT
* PACK_STRUCT_BEGIN
* PACK_STRUCT_END
*
* Platform specific diagnostic output -
* LWIP_PLATFORM_DIAG(x) - non-fatal, print a message.
* LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution.
* Portability defines for printf formatters:
* U16_F, S16_F, X16_F, U32_F, S32_F, X32_F, SZT_F
*
* "lightweight" synchronization mechanisms -
* SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
* SYS_ARCH_PROTECT(x) - enter protection mode.
* SYS_ARCH_UNPROTECT(x) - leave protection mode.
*
* If the compiler does not provide memset() this file must include a
* definition of it, or include a file which defines it.
*
* This file must either include a system-local <errno.h> which defines
* the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
* to make lwip/arch.h define the codes which are used throughout.
*/
#ifndef __CC_H__
#define __CC_H__
//#include "typedef.h"
// for printf
//#include "uart_pub.h"
// for sys interrupt
//#include "ll.h"
/*
* Typedefs for the types used by lwip -
* u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
*/
typedef unsigned char u8_t; /* Unsigned 8 bit quantity */
typedef signed char s8_t; /* Signed 8 bit quantity */
typedef unsigned short u16_t; /* Unsigned 16 bit quantity */
typedef signed short s16_t; /* Signed 16 bit quantity */
typedef unsigned long u32_t; /* Unsigned 32 bit quantity */
typedef signed long s32_t; /* Signed 32 bit quantity */
//typedef unsigned long mem_ptr_t; /* Unsigned 32 bit quantity */
typedef int intptr_t;
typedef unsigned int uintptr_t;
#define LWIP_MAILBOX_QUEUE 1
#define LWIP_TIMEVAL_PRIVATE 0
#define LWIP_NO_INTTYPES_H 1
#if defined(__GNUC__)
#define PACK_STRUCT_BEGIN
#define PACK_STRUCT_STRUCT __attribute__((packed))
#define PACK_STRUCT_FIELD(x) x
#elif defined(__ICCARM__)
#define PACK_STRUCT_BEGIN __packed
#define PACK_STRUCT_STRUCT
#define PACK_STRUCT_FIELD(x) x
#else
#define PACK_STRUCT_BEGIN
#define PACK_STRUCT_STRUCT
#define PACK_STRUCT_FIELD(x) x
#endif
#if LWIP_NO_INTTYPES_H
#define U8_F "d"
#define X8_F "x"
#define U16_F "hu"
#define S16_F "hd"
#define X16_F "hx"
#define U32_F "lu"
#define S32_F "ld"
#define X32_F "lx"
#define SZT_F U32_F
#endif
/*
* Platform specific diagnostic output -
* LWIP_PLATFORM_DIAG(x) - non-fatal, print a message.
* LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution.
* Portability defines for printf formatters:
* U16_F, S16_F, X16_F, U32_F, S32_F, X32_F, SZT_F
*/
#ifndef LWIP_PLATFORM_ASSERT
#define LWIP_PLATFORM_ASSERT(x) \
do \
{ \
} while(0)
#endif
#ifndef LWIP_PLATFORM_DIAG
#define LWIP_PLATFORM_DIAG(x) printf x
#endif
/*
* unknow defination
*/
// cup byte order
#ifndef BYTE_ORDER
#define BYTE_ORDER LITTLE_ENDIAN
#endif
#define LWIP_RAND() ((u32_t)rand())
#endif
// eof

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/*
* Copyright (c) 2001-2003 Swedish Institute of Computer Science.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
* SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*
* This file is part of the lwIP TCP/IP stack.
*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#ifndef __LWIPOPTS_H__
#define __LWIPOPTS_H__
#include "lwip/arch.h"
/**
* Loopback demo related options.
*/
#ifdef CONFIG_YTS_TEST
#define LWIP_NETIF_LOOPBACK 1
#define LWIP_HAVE_LOOPIF 1
#define LWIP_NETIF_LOOPBACK_MULTITHREADING 1
#define LWIP_LOOPBACK_MAX_PBUFS 8
#endif
#define TCP_MAXRTX 5
#define TCPIP_THREAD_NAME "tcp/ip"
#define TCPIP_THREAD_STACKSIZE 3072
#define TCPIP_THREAD_PRIO 4
#define DEFAULT_THREAD_STACKSIZE 200
#define DEFAULT_THREAD_PRIO 1
/* Disable lwIP asserts */
#define LWIP_NOASSERT 1
#define LWIP_DEBUG 0
#define LWIP_DEBUG_TRACE 0
#define SOCKETS_DEBUG LWIP_DBG_OFF // | LWIP_DBG_MASK_LEVEL
#define IP_DEBUG LWIP_DBG_OFF
#define ETHARP_DEBUG LWIP_DBG_OFF
#define NETIF_DEBUG LWIP_DBG_OFF
#define PBUF_DEBUG LWIP_DBG_OFF
#define MEMP_DEBUG LWIP_DBG_OFF
#define API_LIB_DEBUG LWIP_DBG_OFF
#define API_MSG_DEBUG LWIP_DBG_OFF
#define ICMP_DEBUG LWIP_DBG_OFF
#define IGMP_DEBUG LWIP_DBG_OFF
#define INET_DEBUG LWIP_DBG_OFF
#define IP_REASS_DEBUG LWIP_DBG_OFF
#define RAW_DEBUG LWIP_DBG_OFF
#define MEM_DEBUG LWIP_DBG_OFF
#define SYS_DEBUG LWIP_DBG_OFF
#define TCP_DEBUG LWIP_DBG_OFF
#define TCP_INPUT_DEBUG LWIP_DBG_OFF
#define TCP_FR_DEBUG LWIP_DBG_OFF
#define TCP_RTO_DEBUG LWIP_DBG_OFF
#define TCP_CWND_DEBUG LWIP_DBG_OFF
#define TCP_WND_DEBUG LWIP_DBG_OFF
#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF
#define TCP_RST_DEBUG LWIP_DBG_OFF
#define TCP_QLEN_DEBUG LWIP_DBG_OFF
#define UDP_DEBUG LWIP_DBG_OFF
#define TCPIP_DEBUG LWIP_DBG_OFF
#define PPP_DEBUG LWIP_DBG_OFF
#define SLIP_DEBUG LWIP_DBG_OFF
#define DHCP_DEBUG LWIP_DBG_OFF
#define AUTOIP_DEBUG LWIP_DBG_OFF
#define SNMP_MSG_DEBUG LWIP_DBG_OFF
#define SNMP_MIB_DEBUG LWIP_DBG_OFF
#define DNS_DEBUG LWIP_DBG_OFF
//#define LWIP_COMPAT_MUTEX 1
/**
* SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
* critical regions during buffer allocation, deallocation and memory
* allocation and deallocation.
*/
#define SYS_LIGHTWEIGHT_PROT 1
/*
------------------------------------
---------- Memory options ----------
------------------------------------
*/
/**
* MEM_ALIGNMENT: should be set to the alignment of the CPU
* 4 byte alignment -> #define MEM_ALIGNMENT 4
* 2 byte alignment -> #define MEM_ALIGNMENT 2
*/
#define MEM_ALIGNMENT 4
#define MAX_SOCKETS_TCP 12
#define MAX_LISTENING_SOCKETS_TCP 4
#define MAX_SOCKETS_UDP 22
#define TCP_SND_BUF_COUNT 5
/* Value of TCP_SND_BUF_COUNT denotes the number of buffers and is set by
* CONFIG option available in the SDK
*/
/* Buffer size needed for TCP: Max. number of TCP sockets * Size of pbuf *
* Max. number of TCP sender buffers per socket
*
* Listening sockets for TCP servers do not require the same amount buffer
* space. Hence do not consider these sockets for memory computation
*/
#define TCP_MEM_SIZE (MAX_SOCKETS_TCP * \
PBUF_POOL_BUFSIZE * (TCP_SND_BUF/TCP_MSS))
/* Buffer size needed for UDP: Max. number of UDP sockets * Size of pbuf
*/
#define UDP_MEM_SIZE (MAX_SOCKETS_UDP * PBUF_POOL_BUFSIZE)
/**
* MEM_SIZE: the size of the heap memory. If the application will send
* a lot of data that needs to be copied, this should be set high.
*/
#define MEM_SIZE (32*1024)
/*
------------------------------------------------
---------- Internal Memory Pool Sizes ----------
------------------------------------------------
*/
/**
* MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
* If the application sends a lot of data out of ROM (or other static memory),
* this should be set high.
*/
#define MEMP_NUM_PBUF 10
/**
* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
* (requires the LWIP_TCP option)
*/
#define MEMP_NUM_TCP_PCB MAX_SOCKETS_TCP
#define MEMP_NUM_TCP_PCB_LISTEN MAX_LISTENING_SOCKETS_TCP
/**
* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
* (requires the LWIP_TCP option)
*/
//#define MEMP_NUM_TCP_SEG 12
/**
* MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
* for incoming packets.
* (only needed if you use tcpip.c)
*/
#define MEMP_NUM_TCPIP_MSG_INPKT 16
#define TCPIP_MBOX_SIZE 16
/**
* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
* (requires NO_SYS==0)
*/
#define MEMP_NUM_SYS_TIMEOUT 12
/**
* MEMP_NUM_NETBUF: the number of struct netbufs.
* (only needed if you use the sequential API, like api_lib.c)
*/
#define MEMP_NUM_NETBUF 16
/**
* MEMP_NUM_NETCONN: the number of struct netconns.
* (only needed if you use the sequential API, like api_lib.c)
*
* This number corresponds to the maximum number of active sockets at any
* given point in time. This number must be sum of max. TCP sockets, max. TCP
* sockets used for listening, and max. number of UDP sockets
*/
#define MEMP_NUM_NETCONN (MAX_SOCKETS_TCP + \
MAX_LISTENING_SOCKETS_TCP + MAX_SOCKETS_UDP)
/**
* PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
*/
#define PBUF_POOL_SIZE 10
/*
----------------------------------
---------- Pbuf options ----------
----------------------------------
*/
/**
* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
* designed to accomodate single full size TCP frame in one pbuf, including
* TCP_MSS, IP header, and link header.
*/
#define PBUF_POOL_BUFSIZE 1580
/*
---------------------------------
---------- RAW options ----------
---------------------------------
*/
/**
* LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
*/
#define LWIP_RAW 1
#define LWIP_IPV6 0
/* Enable IPv4 Auto IP */
#ifdef CONFIG_AUTOIP
#define LWIP_AUTOIP 1
#define LWIP_DHCP_AUTOIP_COOP 1
#define LWIP_DHCP_AUTOIP_COOP_TRIES 5
#endif
/*
------------------------------------
---------- Socket options ----------
------------------------------------
*/
/**
* LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
*/
#define LWIP_SOCKET 1
#define LWIP_NETIF_API 1
/**
* LWIP_RECV_CB==1: Enable callback when a socket receives data.
*/
#define LWIP_RECV_CB 1
/**
* SO_REUSE==1: Enable SO_REUSEADDR option.
*/
#define SO_REUSE 1
#define SO_REUSE_RXTOALL 1
/**
* Enable TCP_KEEPALIVE
*/
#define LWIP_TCP_KEEPALIVE 1
/*
----------------------------------------
---------- Statistics options ----------
----------------------------------------
*/
/**
* LWIP_STATS==1: Enable statistics collection in lwip_stats.
*/
#define LWIP_STATS 0
/**
* LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
*/
#define LWIP_STATS_DISPLAY 0
/*
----------------------------------
---------- DHCP options ----------
----------------------------------
*/
/**
* LWIP_DHCP==1: Enable DHCP module.
*/
#define LWIP_DHCP 1
#define LWIP_NETIF_STATUS_CALLBACK 1
/**
* DNS related options, revisit later to fine tune.
*/
#define LWIP_DNS 1
#define DNS_TABLE_SIZE 2 // number of table entries, default 4
//#define DNS_MAX_NAME_LENGTH 64 // max. name length, default 256
#define DNS_MAX_SERVERS 2 // number of DNS servers, default 2
#define DNS_DOES_NAME_CHECK 1 // compare received name with given,def 0
#define DNS_MSG_SIZE 512
#define MDNS_MSG_SIZE 512
#define MDNS_TABLE_SIZE 1 // number of mDNS table entries
#define MDNS_MAX_SERVERS 1 // number of mDNS multicast addresses
/* TODO: Number of active UDP PCBs is equal to number of active UDP sockets plus
* two. Need to find the users of these 2 PCBs
*/
#define MEMP_NUM_UDP_PCB (MAX_SOCKETS_UDP + 2)
/* NOTE: some times the socket() call for SOCK_DGRAM might fail if you dont
* have enough MEMP_NUM_UDP_PCB */
/*
----------------------------------
---------- IGMP options ----------
----------------------------------
*/
/**
* LWIP_IGMP==1: Turn on IGMP module.
*/
#define LWIP_IGMP 1
/**
* LWIP_SO_SNDTIMEO==1: Enable send timeout for sockets/netconns and
* SO_SNDTIMEO processing.
*/
#define LWIP_SO_SNDTIMEO 1
/**
* LWIP_SO_RCVTIMEO==1: Enable receive timeout for sockets/netconns and
* SO_RCVTIMEO processing.
*/
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
/**
* TCP_LISTEN_BACKLOG==1: Handle backlog connections.
*/
#define TCP_LISTEN_BACKLOG 1
#define LWIP_PROVIDE_ERRNO 1
#include <errno.h>
#define ERRNO 1
//#define LWIP_SNMP 1
/*
------------------------------------------------
---------- Network Interfaces options ----------
------------------------------------------------
*/
/**
* LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
* field.
*/
#define LWIP_NETIF_HOSTNAME 1
/**
* LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
* changes its up/down status (i.e., due to DHCP IP acquisition)
*/
#define LWIP_NETIF_STATUS_CALLBACK 1
/**
* LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
* whenever the link changes (i.e., link down)
*/
#define LWIP_NETIF_LINK_CALLBACK 1
/*
The STM32F107 allows computing and verifying the IP, UDP, TCP and ICMP checksums by hardware:
- To use this feature let the following define uncommented.
- To disable it and process by CPU comment the the checksum.
*/
//#define CHECKSUM_BY_HARDWARE
#ifdef CHECKSUM_BY_HARDWARE
/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 0
/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 0
/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 0
/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 0
/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 0
/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 0
#else
/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/
#define CHECKSUM_GEN_IP 1
/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/
#define CHECKSUM_GEN_UDP 1
/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/
#define CHECKSUM_GEN_TCP 1
/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/
#define CHECKSUM_CHECK_IP 1
/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/
#define CHECKSUM_CHECK_UDP 1
/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/
#define CHECKSUM_CHECK_TCP 1
#endif
/**
* TCP_RESOURCE_FAIL_RETRY_LIMIT: limit for retrying sending of tcp segment
* on resource failure error returned by driver.
*/
#define TCP_RESOURCE_FAIL_RETRY_LIMIT 50
//yhb changed:
//#ifdef CONFIG_ENABLE_MXCHIP
/* save memory */
#define PBUF_POOL_SIZE 10
#define TCP_MSS (1500 - 40)
/* TCP receive window. */
#define TCP_WND (3*TCP_MSS)
/* TCP sender buffer space (bytes). */
#define TCP_SND_BUF (10*TCP_MSS)
#define TCP_SND_QUEUELEN (20)
/* ARP before DHCP causes multi-second delay - turn it off */
#define DHCP_DOES_ARP_CHECK (0)
#define TCP_MAX_ACCEPT_CONN 5
#define MEMP_NUM_TCP_SEG (TCP_SND_QUEUELEN*2)
#define IP_REASS_MAX_PBUFS 0
#define IP_REASSEMBLY 0
#define IP_REASS_MAX_PBUFS 0
#define IP_REASSEMBLY 0
#define MEMP_NUM_REASSDATA 0
#define IP_FRAG 0
#define MEM_LIBC_MALLOC (1)
#define DEFAULT_UDP_RECVMBOX_SIZE 3 // yhb set, each udp socket max buffer 3 packets.
#define MEMP_MEM_MALLOC (1)
#define TCP_MSL (TCP_TMR_INTERVAL)
#define LWIP_COMPAT_MUTEX_ALLOWED (1)
//#endif
#define TCPIP_MBOX_SIZE 16
#define DEFAULT_ACCEPTMBOX_SIZE 8
#define DEFAULT_RAW_RECVMBOX_SIZE 4
#define DEFAULT_UDP_RECVMBOX_SIZE 8
#define DEFAULT_TCP_RECVMBOX_SIZE 8
#ifdef CONFIG_AOS_MESH
#define LWIP_DECLARE_HOOK \
struct netif *lwip_hook_ip6_route(const ip6_addr_t *src, const ip6_addr_t *dest); \
int lwip_hook_mesh_is_mcast_subscribed(const ip6_addr_t *dest);
#define LWIP_HOOK_IP6_ROUTE(src, dest) lwip_hook_ip6_route(src, dest)
#define LWIP_HOOK_MESH_IS_MCAST_SUBSCRIBED(dest) lwip_hook_mesh_is_mcast_subscribed(dest)
#define LWIP_ICMP6 1
#define CHECKSUM_CHECK_ICMP6 0
#define LWIP_MULTICAST_PING 1
#endif
#define LWIP_RANDOMIZE_INITIAL_LOCAL_PORTS 1
#define TCP_QUEUE_OOSEQ 1
#endif /* __LWIPOPTS_H__ */

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#ifndef __DHCPS_H__
#define __DHCPS_H__
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include <stdio.h>
#include <string.h>
#include "cmsis_os.h"
#include "lwip/arch.h"
#include "lwip/netif.h"
#include "lwip/udp.h"
#include "lwip/stats.h"
#include "lwip/sys.h"
//#include <platform/platform_stdlib.h>
#define IS_USE_FIXED_IP 0
#define debug_dhcps 1
/* dhcp server states */
#define DHCP_SERVER_STATE_OFFER (1)
#define DHCP_SERVER_STATE_DECLINE (2)
#define DHCP_SERVER_STATE_ACK (3)
#define DHCP_SERVER_STATE_NAK (4)
#define DHCP_SERVER_STATE_IDLE (5)
#define BOOTP_BROADCAST (0x8000)
#define DHCP_MESSAGE_OP_REQUEST (1)
#define DHCP_MESSAGE_OP_REPLY (2)
#define DHCP_MESSAGE_HTYPE (1)
#define DHCP_MESSAGE_HLEN (6)
#ifndef DHCP_SERVER_PORT
#define DHCP_SERVER_PORT (67)
#endif
#ifndef DHCP_CLIENT_PORT
#define DHCP_CLIENT_PORT (68)
#endif
#define DHCP_MESSAGE_TYPE_DISCOVER (1)
#define DHCP_MESSAGE_TYPE_OFFER (2)
#define DHCP_MESSAGE_TYPE_REQUEST (3)
#define DHCP_MESSAGE_TYPE_DECLINE (4)
#define DHCP_MESSAGE_TYPE_ACK (5)
#define DHCP_MESSAGE_TYPE_NAK (6)
#define DHCP_MESSAGE_TYPE_RELEASE (7)
#define DHCP_OPTION_LENGTH_ONE (1)
#define DHCP_OPTION_LENGTH_TWO (2)
#define DHCP_OPTION_LENGTH_THREE (3)
#define DHCP_OPTION_LENGTH_FOUR (4)
#define DHCP_OPTION_CODE_SUBNET_MASK (1)
#define DHCP_OPTION_CODE_ROUTER (3)
#define DHCP_OPTION_CODE_DNS_SERVER (6)
#define DHCP_OPTION_CODE_INTERFACE_MTU (26)
#define DHCP_OPTION_CODE_BROADCAST_ADDRESS (28)
#define DHCP_OPTION_CODE_PERFORM_ROUTER_DISCOVERY (31)
#define DHCP_OPTION_CODE_REQUEST_IP_ADDRESS (50)
#define DHCP_OPTION_CODE_LEASE_TIME (51)
#define DHCP_OPTION_CODE_MSG_TYPE (53)
#define DHCP_OPTION_CODE_SERVER_ID (54)
#define DHCP_OPTION_CODE_REQ_LIST (55)
#define DHCP_OPTION_CODE_END (255)
#define IP_FREE_TO_USE (1)
#define IP_ALREADY_IN_USE (0)
#define HW_ADDRESS_LENGTH (6)
typedef uint32_t TickType_t;
#define portMAX_DELAY 0xffffffffUL
/* Reference by RFC 2131 */
struct dhcps_msg {
uint8_t op; /* Message op code/message type. 1 = BOOTREQUEST, 2 = BOOTREPLY */
uint8_t htype; /* Hardware address type */
uint8_t hlen; /* Hardware address length */
uint8_t hops; /* Client sets to zero, optionally used by relay agents
when booting via a relay agent */
uint8_t xid[4]; /* Transaction ID, a random number chosen by the client,
used by the client and server to associate messages and
responses between a client and a server */
uint16_t secs; /* Filled in by client, seconds elapsed since client began address
acquisition or renewal process.*/
uint16_t flags; /* bit 0: Broadcast flag, bit 1~15:MBZ must 0*/
uint8_t ciaddr[4]; /* Client IP address; only filled in if client is in BOUND,
RENEW or REBINDING state and can respond to ARP requests. */
uint8_t yiaddr[4]; /* 'your' (client) IP address */
uint8_t siaddr[4]; /* IP address of next server to use in bootstrap;
returned in DHCPOFFER, DHCPACK by server. */
uint8_t giaddr[4]; /* Relay agent IP address, used in booting via a relay agent.*/
uint8_t chaddr[16]; /* Client hardware address */
uint8_t sname[64]; /* Optional server host name, null terminated string.*/
uint8_t file[128]; /* Boot file name, null terminated string; "generic" name or
null in DHCPDISCOVER, fully qualified directory-path name in DHCPOFFER.*/
uint8_t options[312]; /* Optional parameters field. reference the RFC 2132 */
};
struct table {
uint32_t ip_range[8];
};
struct address_pool{
uint32_t start;
uint32_t end;
};
/* 01~32 */
#define MARK_RANGE1_IP_BIT(table, ip) ((table.ip_range[0]) | (1 << ((ip) - 1)))
/* 33~64 */
#define MARK_RANGE2_IP_BIT(table, ip) ((table.ip_range[1]) | (1 << ((ip) - 1)))
/* 65~96 */
#define MARK_RANGE3_IP_BIT(table, ip) ((table.ip_range[2]) | (1 << ((ip) - 1)))
/* 97~128 */
#define MARK_RANGE4_IP_BIT(table, ip) ((table.ip_range[3]) | (1 << ((ip) - 1)))
/* 129~160 */
#define MARK_RANGE5_IP_BIT(table, ip) ((table.ip_range[4]) | (1 << ((ip) - 1)))
/* 161~192 */
#define MARK_RANGE6_IP_BIT(table, ip) ((table.ip_range[5]) | (1 << ((ip) - 1)))
/* 193~224 */
#define MARK_RANGE7_IP_BIT(table, ip) ((table.ip_range[6]) | (1 << ((ip) - 1)))
/* 225~255 */
#define MARK_RANGE8_IP_BIT(table, ip) ((table.ip_range[7]) | (1 << ((ip) - 1)))
/* 01~32 */
#define UNMARK_RANGE1_IP_BIT(table, ip) ((table.ip_range[0]) & ~(1 << ((ip) - 1)))
/* 33~64 */
#define UNMARK_RANGE2_IP_BIT(table, ip) ((table.ip_range[1]) & ~(1 << ((ip) - 1)))
/* 65~96 */
#define UNMARK_RANGE3_IP_BIT(table, ip) ((table.ip_range[2]) & ~(1 << ((ip) - 1)))
/* 97~128 */
#define UNMARK_RANGE4_IP_BIT(table, ip) ((table.ip_range[3]) & ~(1 << ((ip) - 1)))
/* 129~160 */
#define UNMARK_RANGE5_IP_BIT(table, ip) ((table.ip_range[4]) & ~(1 << ((ip) - 1)))
/* 161~192 */
#define UNMARK_RANGE6_IP_BIT(table, ip) ((table.ip_range[5]) & ~(1 << ((ip) - 1)))
/* 193~224 */
#define UNMARK_RANGE7_IP_BIT(table, ip) ((table.ip_range[6]) & ~(1 << ((ip) - 1)))
/* 225~255 */
#define UNMARK_RANGE8_IP_BIT(table, ip) ((table.ip_range[7]) & ~(1 << ((ip) - 1)))
/* expose API */
void dhcps_set_addr_pool(int addr_pool_set, ip4_addr_t * addr_pool_start, ip4_addr_t *addr_pool_end);
void dhcps_init(struct netif * pnetif);
void dhcps_deinit(void);
void unmark_ip_in_table(uint8_t d);
void dhcps_set_release_time(u32_t release_time);
extern struct netif *netif_default;
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __DHCPS_H__ */

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Living_SDK/platform/mcu/rda5981x/wifi/inc/maclib_task.h Normal file
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@ -0,0 +1,71 @@
/******************************************************************************
* @file : maclib_task.h
* @brief : WiFi MACLib task header file
* @version: V1.0
* @date : 6. May 2017
*
* @note :
*
******************************************************************************/
#ifndef _MACLIB_TASK_H_
#define _MACLIB_TASK_H_
#define MAC_LIB_MAX_FLEN 1536
/**
* Enums
*/
typedef enum {
MACLIB_MSG_EVNT_HNDL,
MACLIB_MSG_WLAND_XMIT_PKT,
MACLIB_MSG_LWIP_XMIT_PKT
} MACLIB_MSG_TYPE_T;
/**
* Structures
*/
typedef struct {
MACLIB_MSG_TYPE_T type;
r_void *msg;
r_s32 is_free;
} maclib_msg_t;
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief : MACLib main task [MACLib api]
* @param[in] : pvParameters(pointer to enet data)
* @param[out]:
* @return :
*/
extern r_void maclib_task(r_void *pvParameters);
extern r_void event_handle_cb(r_u32 event);
extern r_void mltask_sleep_cb(r_void);
extern r_void mltask_wakeup_cb(r_void);
#if 0
/**
* @brief : pkt transmiting interface [MACLib api]
* @param[in] : p(wland use memory pointer, lwip use pbuf)
* @param[out]:
* @return : 0 for succsess, others for error
*/
extern int maclib_xmit_pkt(void *p, MACLIB_MSG_TYPE_T type);
/**
* @brief : pkt receiving callback interface [user implemented]
* @param[in] : buf(pointer to maclib_buf_t structure)
* @param[out]:
* @return : 0 for succsess, others for error
*/
extern int wland_recv_pkt(unsigned char *buf);
#endif
#ifdef __cplusplus
}
#endif
#endif /* _MACLIB_TASK_H_ */

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