mirror of
https://github.com/Ai-Thinker-Open/Ai-Thinker-Open_RTL8710BX_ALIOS_SDK.git
synced 2025-07-31 19:31:05 +00:00
rel_1.6.0 init
This commit is contained in:
guocheng.kgc
shengdong.dsd
commit
27b3e2883d
19359 changed files with 8093121 additions and 0 deletions
83
Living_SDK/platform/mcu/r5f100lea/ccrl/bsp.c
Normal file
83
Living_SDK/platform/mcu/r5f100lea/ccrl/bsp.c
Normal file
|
|
@ -0,0 +1,83 @@
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|||
#include <k_api.h>
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#include "bsp.h"
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uint32_t sys_freq(void);
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void int_dummy(void)
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{
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while (1);
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}
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void tick_init(uint32_t ticks_per_sec)
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{
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REG_PER0 |= PER0_ENABLE_CLOCK;
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REG_TPS0 = TPS0_SET_CLOCK_FRQ;
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REG_TMR00 = TMR00_SET_CK00_SRC;
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REG_TDR00 = (sys_freq() / ticks_per_sec) - 1;
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REG_TOE0 &= 0x00FE;
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REG_TO0 &= 0x00FE;
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REG_TOM0 &= 0x00FE;
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REG_TOL0 &= 0x00FE;
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REG_PR01L = 1;
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REG_PR11L = 1;
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REG_IF1L &= ~BIT_04;
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REG_MK1L &= ~BIT_04;
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REG_TS0 |= TS0_EN_TMR_OUTPUT;
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}
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uint32_t sys_freq(void)
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{
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uint8_t freq_sel;
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uint8_t clk_src;
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uint32_t cpu_clk;
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freq_sel = OPTBYTE2_VAL & 0x0F;
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clk_src = REG_CLK_GEN_CKC;
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if (BIT_IS_SET(clk_src, BIT_CKC_CSS)) {
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cpu_clk = FSUB_CLKRATE;
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if (BIT_IS_SET(clk_src, BIT_CKC_MCM0)) {
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clk_src = REG_CLK_GEN_CMC;
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cpu_clk = FMX_CLKRATE;
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} else {
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switch(freq_sel) {
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case FRQSEL_32MHz:
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cpu_clk = CLKRATE32;
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break;
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case FRQSEL_24MHz:
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cpu_clk = CLKRATE24;
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break;
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case FRQSEL_16MHz:
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cpu_clk = CLKRATE16;
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break;
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case FRQSEL_12MHz:
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cpu_clk = CLKRATE12;
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break;
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case FRQSEL_8MHz:
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cpu_clk = CLKRATE08;
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break;
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case FRQSEL_4MHz:
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cpu_clk = CLKRATE04;
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break;
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case FRQSEL_1MHz:
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cpu_clk = CLKRATE01;
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break;
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default:
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break;
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}
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}
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}
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return (cpu_clk);
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}
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122
Living_SDK/platform/mcu/r5f100lea/ccrl/bsp.h
Normal file
122
Living_SDK/platform/mcu/r5f100lea/ccrl/bsp.h
Normal file
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@ -0,0 +1,122 @@
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#ifndef BSP_H
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#define BSP_H
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#define CLK_GEN_BASE_ADDR ((uint32_t )0x000FFF00u)
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#define REG_CLK_GEN_CMC (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA0u))
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#define REG_CLK_GEN_CKC (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA4u))
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#define REG_CLK_GEN_CSC (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA1u))
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#define REG_CLK_GEN_OSTC (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA2u))
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#define REG_CLK_GEN_OSTS (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA3u))
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#define REG_CLK_GEN_OSMC (*(volatile uint8_t __far*)(0xF0000000 + 0xF3u))
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#define REG_CLK_GEN_HOCODIV (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA8u))
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#define REG_CLK_GEN_HIOTRM (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA0u))
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#define REG_PORT_BASE_ADDR_00 ((uint32_t )0x000F0000u)
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#define REG_P(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0xFF00 + n ))
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#define REG_PM(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0xFF20 + n ))
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||||
#define REG_PU(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0x30 + n ))
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#define REG_PIM(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0x40 + n ))
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#define REG_POM(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0x50 + n ))
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#define REG_PMC(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0x60 + n ))
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#define REG_PER0 (*(volatile uint8_t __far*)0x000F00F0u)
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#define REG_TPS0 (*(volatile uint16_t __far*)0x000F01B6u)
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#define REG_TMR00 (*(volatile uint16_t __far*)0x000F0190u)
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||||
#define REG_TDR00 (*(volatile uint16_t __far*)0x000FFF18u)
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||||
#define REG_TOE0 (*(volatile uint16_t __far*)0x000F01BAu)
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||||
#define REG_TO0 (*(volatile uint16_t __far*)0x000F01B8u)
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||||
#define REG_TOM0 (*(volatile uint16_t __far*)0x000F01BEu)
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||||
#define REG_TOL0 (*(volatile uint16_t __far*)0x000F01BCu)
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||||
#define REG_TS0 (*(volatile uint16_t __far*)0x000F01B2u)
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||||
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||||
#define REG_PR01L (*(volatile uint8_t __far*)0x000FFFEAu)
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||||
#define REG_PR11L (*(volatile uint8_t __far*)0x000FFFEEu)
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||||
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||||
#define REG_IF1L (*(volatile uint8_t __far*)0x000FFFE2u)
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||||
#define REG_MK1L (*(volatile uint8_t __far*)0x000FFFE6u)
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||||
|
||||
#define BIT_MASK(bit_mask, bit_shift) ((bit_mask) << (bit_shift))
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#define BIT_IS_SET(val, mask) ((((mask) != 0u) && \
|
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(((val) & (mask)) == (mask))) ? (1) : (0))
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||||
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||||
#define BIT_NONE 0x00u
|
||||
#define BIT_00 0x01u
|
||||
#define BIT_01 0x02u
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||||
#define BIT_02 0x04u
|
||||
#define BIT_03 0x08u
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||||
#define BIT_04 0x10u
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||||
#define BIT_05 0x20u
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#define BIT_06 0x40u
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||||
#define BIT_07 0x80u
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||||
#define BIT_08 0x0100u
|
||||
|
||||
#define REG_PIOR (*(volatile uint8_t __far*)0x000F0077u)
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#define REG_CRC0CTL (*(volatile uint8_t __far*)0x000F02F0u)
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#define REG_IAWCTL (*(volatile uint8_t __far*)0x000F0078u)
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#define REG_PMS (*(volatile uint8_t __far*)0x000F007Bu)
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||||
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#define BIT_CKC_MCM0 BIT_04
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||||
#define BIT_CKC_MCS BIT_05
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||||
#define BIT_CSC_MSTOP BIT_06
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#define BIT_CSC_XTSTOP BIT_06
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#define BIT_CKC_CSS BIT_06
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||||
#define BIT_CSC_HIOSTOP BIT_00
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#define BIT_CMC_AMPH BIT_00
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|
||||
#define BIT_MK1L_TMMK00 BIT_04
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#define BIT_IF1L_TMIF00 BIT_04
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#define BIT_PRO1L_TMPR000 BIT_04
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||||
#define BIT_PR11L_TMPR100 BIT_04
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||||
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||||
#define OSC_HSCLK_INPUT BIT_NONE
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||||
#define OSC_SUBCLK_INPUT BIT_NONE
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||||
#define OSC_XT1_DEFAULT BIT_NONE
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#define OSC_FRQ_DEFAULT BIT_NONE
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||||
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||||
#define OSCSTAB_SEL_26_21ms BIT_MASK(7, 0)
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#define OSCSTAB_STA 0xFFu
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||||
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#define CLK_SUBINHALT_ON BIT_NONE
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#define CLK_FSUB_ON BIT_NONE
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||||
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||||
#define OSCSUB_WAITTIME 160
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||||
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#define CLKFREQ_DIV 512
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#define FSUB_CLKRATE 32768
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||||
#define LOWSPEED_CLKRATE 15000
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||||
#define FMX_CLKRATE 12000000
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#define CLKRATE32 32000000
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#define CLKRATE24 24000000
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#define CLKRATE16 16000000
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#define CLKRATE12 12000000
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#define CLKRATE08 8000000
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#define CLKRATE04 4000000
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#define CLKRATE01 1000000
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#define FRQSEL_1MHz 0x0D
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#define FRQSEL_4MHz 0x0B
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#define FRQSEL_8MHz 0x0A
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#define FRQSEL_12MHz 0x01
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#define FRQSEL_16MHz 0x09
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#define FRQSEL_24MHz 0x00
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#define FRQSEL_32MHz 0x08
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#define PIOR_REDIRECT_DIS 0x00
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#define CRC0CTL_FLASH_OFF 0x00
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#define IWACTL_INVALID_MEM_DET_OFF 0x00
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#define PMS_PORT_MODE_READ 0x00
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||||
#define PER0_ENABLE_CLOCK 0x0001
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#define TPS0_SET_CLOCK_FRQ 0x0000
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#define TMR00_SET_CK00_SRC 0x0000
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#define TS0_EN_TMR_OUTPUT 0x0001
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#define OPTBYTE2_VAL 0xE8u
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#endif
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445
Living_SDK/platform/mcu/r5f100lea/ccrl/bsp_vect_a.asm
Normal file
445
Living_SDK/platform/mcu/r5f100lea/ccrl/bsp_vect_a.asm
Normal file
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@ -0,0 +1,445 @@
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$INCLUDE(port_cpu.inc)
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;.NAME ?bsp_vect
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.EXTERN _int_dummy
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.EXTERN _krhino_tick_proc
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.PUBLIC _SOC_WDTI
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.PUBLIC _SOC_LVI
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||||
.PUBLIC _SOC_P0
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||||
.PUBLIC _SOC_P1
|
||||
.PUBLIC _SOC_P2
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||||
.PUBLIC _SOC_P3
|
||||
.PUBLIC _SOC_P4
|
||||
.PUBLIC _SOC_P5
|
||||
.PUBLIC _SOC_ST2_CSI20_IIC20
|
||||
.PUBLIC _SOC_SR2_CSI20_IIC21
|
||||
.PUBLIC _SOC_SRE2_TM11H
|
||||
.PUBLIC _SOC_DMA0
|
||||
.PUBLIC _SOC_DMA1
|
||||
.PUBLIC _SOC_ST0_CSI00_IIC00
|
||||
.PUBLIC _SOC_ST0_CSI00_IIC00
|
||||
.PUBLIC _SOC_SR0_CSI01_IIC01
|
||||
.PUBLIC _SOC_SRE0_TM01H
|
||||
.PUBLIC _SOC_ST1_CSI10_IIC10
|
||||
.PUBLIC _SOC_SR1_CSI11_IIC11
|
||||
.PUBLIC _SOC_IICA0
|
||||
.PUBLIC _SOC_TM00
|
||||
.PUBLIC _SOC_TM01
|
||||
.PUBLIC _SOC_TM02
|
||||
.PUBLIC _SOC_TM03
|
||||
.PUBLIC _SOC_AD
|
||||
.PUBLIC _SOC_RTC
|
||||
.PUBLIC _SOC_IT
|
||||
.PUBLIC _SOC_KR
|
||||
.PUBLIC _SOC_ST3_CSI30_IIC30
|
||||
.PUBLIC _SOC_SR3_CSI31_IIC31
|
||||
.PUBLIC _SOC_TM13
|
||||
.PUBLIC _SOC_TM04
|
||||
.PUBLIC _SOC_TM05
|
||||
.PUBLIC _SOC_TM06
|
||||
.PUBLIC _SOC_TM07
|
||||
.PUBLIC _SOC_P6
|
||||
.PUBLIC _SOC_P7
|
||||
.PUBLIC _SOC_P8
|
||||
.PUBLIC _SOC_P9
|
||||
.PUBLIC _SOC_P10
|
||||
.PUBLIC _SOC_P11
|
||||
.PUBLIC _SOC_TM10
|
||||
.PUBLIC _SOC_TM11
|
||||
.PUBLIC _SOC_TM12
|
||||
.PUBLIC _SOC_SRE3_TM13H
|
||||
.PUBLIC _SOC_MD
|
||||
.PUBLIC _SOC_IICA1
|
||||
.PUBLIC _SOC_FL
|
||||
.PUBLIC _SOC_DMA2
|
||||
.PUBLIC _SOC_DMA3
|
||||
.PUBLIC _SOC_TM14
|
||||
.PUBLIC _SOC_TM15
|
||||
.PUBLIC _SOC_TM16
|
||||
.PUBLIC _SOC_TM17
|
||||
|
||||
_SOC_WDTI .VECTOR 0x0004
|
||||
_SOC_LVI .VECTOR 0x0006
|
||||
_SOC_P0 .VECTOR 0x0008
|
||||
_SOC_P1 .VECTOR 0x000A
|
||||
_SOC_P2 .VECTOR 0x000C
|
||||
_SOC_P3 .VECTOR 0x000E
|
||||
_SOC_P4 .VECTOR 0x0010
|
||||
_SOC_P5 .VECTOR 0x0012
|
||||
_SOC_ST2_CSI20_IIC20 .VECTOR 0x0014
|
||||
_SOC_SR2_CSI20_IIC21 .VECTOR 0x0016
|
||||
_SOC_SRE2_TM11H .VECTOR 0x0018
|
||||
_SOC_DMA0 .VECTOR 0x001A
|
||||
_SOC_DMA1 .VECTOR 0x001C
|
||||
_SOC_ST0_CSI00_IIC00 .VECTOR 0x001E
|
||||
_SOC_ST0_CSI00_IIC00 .VECTOR 0x0020
|
||||
_SOC_SR0_CSI01_IIC01 .VECTOR 0x0022
|
||||
_SOC_SRE0_TM01H .VECTOR 0x0024
|
||||
_SOC_ST1_CSI10_IIC10 .VECTOR 0x0026
|
||||
_SOC_SR1_CSI11_IIC11 .VECTOR 0x0028
|
||||
_SOC_IICA0 .VECTOR 0x002A
|
||||
_SOC_TM00 .VECTOR 0x002C
|
||||
_SOC_TM01 .VECTOR 0x002E
|
||||
_SOC_TM02 .VECTOR 0x0030
|
||||
_SOC_TM03 .VECTOR 0x0032
|
||||
_SOC_AD .VECTOR 0x0034
|
||||
_SOC_RTC .VECTOR 0x0036
|
||||
_SOC_IT .VECTOR 0x0038
|
||||
_SOC_KR .VECTOR 0x003A
|
||||
_SOC_ST3_CSI30_IIC30 .VECTOR 0x003C
|
||||
_SOC_SR3_CSI31_IIC31 .VECTOR 0x003E
|
||||
_SOC_TM13 .VECTOR 0x0040
|
||||
_SOC_TM04 .VECTOR 0x0042
|
||||
_SOC_TM05 .VECTOR 0x0044
|
||||
_SOC_TM06 .VECTOR 0x0046
|
||||
_SOC_TM07 .VECTOR 0x0048
|
||||
_SOC_P6 .VECTOR 0x004A
|
||||
_SOC_P7 .VECTOR 0x004C
|
||||
_SOC_P8 .VECTOR 0x004E
|
||||
_SOC_P9 .VECTOR 0x0050
|
||||
_SOC_P10 .VECTOR 0x0052
|
||||
_SOC_P11 .VECTOR 0x0054
|
||||
_SOC_TM10 .VECTOR 0x0056
|
||||
_SOC_TM11 .VECTOR 0x0058
|
||||
_SOC_TM12 .VECTOR 0x005A
|
||||
_SOC_SRE3_TM13H .VECTOR 0x005C
|
||||
_SOC_MD .VECTOR 0x005E
|
||||
_SOC_IICA1 .VECTOR 0x0060
|
||||
_SOC_FL .VECTOR 0x0062
|
||||
_SOC_DMA2 .VECTOR 0x0064
|
||||
_SOC_DMA3 .VECTOR 0x0066
|
||||
_SOC_TM14 .VECTOR 0x0068
|
||||
_SOC_TM15 .VECTOR 0x006A
|
||||
_SOC_TM16 .VECTOR 0x006C
|
||||
_SOC_TM17 .VECTOR 0x006E
|
||||
|
||||
|
||||
|
||||
.SECTION .text, TEXT
|
||||
|
||||
_SOC_WDTI:
|
||||
sys_isr_enter
|
||||
MOVW AX, #0
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_LVI:
|
||||
sys_isr_enter
|
||||
MOVW AX, #1
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P0:
|
||||
sys_isr_enter
|
||||
MOVW AX, #2
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P1:
|
||||
sys_isr_enter
|
||||
MOVW AX, #3
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P2:
|
||||
sys_isr_enter
|
||||
MOVW AX, #4
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P3:
|
||||
sys_isr_enter
|
||||
MOVW AX, #5
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P4:
|
||||
sys_isr_enter
|
||||
MOVW AX, #6
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P5:
|
||||
sys_isr_enter
|
||||
MOVW AX, #7
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_ST2_CSI20_IIC20:
|
||||
sys_isr_enter
|
||||
MOVW AX, #8
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_SR2_CSI20_IIC21:
|
||||
sys_isr_enter
|
||||
MOVW AX, #9
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_SRE2_TM11H:
|
||||
sys_isr_enter
|
||||
MOVW AX, #10
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_DMA0:
|
||||
sys_isr_enter
|
||||
MOVW AX, #11
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_DMA1:
|
||||
sys_isr_enter
|
||||
MOVW AX, #12
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_ST0_CSI00_IIC00:
|
||||
sys_isr_enter
|
||||
MOVW AX, #13
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_SR0_CSI01_IIC01:
|
||||
sys_isr_enter
|
||||
MOVW AX, #14
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_SRE0_TM01H:
|
||||
sys_isr_enter
|
||||
MOVW AX, #15
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_ST1_CSI10_IIC10:
|
||||
sys_isr_enter
|
||||
MOVW AX, #16
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_SR1_CSI11_IIC11:
|
||||
sys_isr_enter
|
||||
MOVW AX, #17
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_SRE1_TM03H:
|
||||
sys_isr_enter
|
||||
MOVW AX, #18
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_IICA0:
|
||||
sys_isr_enter
|
||||
MOVW AX, #19
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM00:
|
||||
sys_isr_enter
|
||||
MOVW AX, #20
|
||||
CALL !_krhino_tick_proc
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM01:
|
||||
sys_isr_enter
|
||||
MOVW AX, #21
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM02:
|
||||
sys_isr_enter
|
||||
MOVW AX, #22
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM03:
|
||||
sys_isr_enter
|
||||
MOVW AX, #23
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_AD:
|
||||
sys_isr_enter
|
||||
MOVW AX, #24
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_RTC:
|
||||
sys_isr_enter
|
||||
MOVW AX, #25
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_IT:
|
||||
sys_isr_enter
|
||||
MOVW AX, #26
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_KR:
|
||||
sys_isr_enter
|
||||
MOVW AX, #27
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_ST3_CSI30_IIC30:
|
||||
sys_isr_enter
|
||||
MOVW AX, #28
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_SR3_CSI31_IIC31:
|
||||
sys_isr_enter
|
||||
MOVW AX, #29
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM13:
|
||||
sys_isr_enter
|
||||
MOVW AX, #30
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM04:
|
||||
sys_isr_enter
|
||||
MOVW AX, #31
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM05:
|
||||
sys_isr_enter
|
||||
MOVW AX, #32
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM06:
|
||||
sys_isr_enter
|
||||
MOVW AX, #33
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM07:
|
||||
sys_isr_enter
|
||||
MOVW AX, #34
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P6:
|
||||
sys_isr_enter
|
||||
MOVW AX, #35
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P7:
|
||||
sys_isr_enter
|
||||
MOVW AX, #36
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P8:
|
||||
sys_isr_enter
|
||||
MOVW AX, #37
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P9:
|
||||
sys_isr_enter
|
||||
MOVW AX, #38
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P10:
|
||||
sys_isr_enter
|
||||
MOVW AX, #39
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_P11:
|
||||
sys_isr_enter
|
||||
MOVW AX, #40
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM10:
|
||||
sys_isr_enter
|
||||
MOVW AX, #41
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM11:
|
||||
sys_isr_enter
|
||||
MOVW AX, #42
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM12:
|
||||
sys_isr_enter
|
||||
MOVW AX, #43
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_SRE3_TM13H:
|
||||
sys_isr_enter
|
||||
MOVW AX, #44
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_MD:
|
||||
sys_isr_enter
|
||||
MOVW AX, #45
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_IICA1:
|
||||
sys_isr_enter
|
||||
MOVW AX, #46
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_FL:
|
||||
sys_isr_enter
|
||||
MOVW AX, #47
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_DMA2:
|
||||
sys_isr_enter
|
||||
MOVW AX, #48
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_DMA3:
|
||||
sys_isr_enter
|
||||
MOVW AX, #49
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM14:
|
||||
sys_isr_enter
|
||||
MOVW AX, #50
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM15:
|
||||
sys_isr_enter
|
||||
MOVW AX, #51
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM16:
|
||||
sys_isr_enter
|
||||
MOVW AX, #52
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
_SOC_TM17:
|
||||
sys_isr_enter
|
||||
MOVW AX, #53
|
||||
CALL !!_int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
|
||||
226
Living_SDK/platform/mcu/r5f100lea/ccrl/k_config.h
Normal file
226
Living_SDK/platform/mcu/r5f100lea/ccrl/k_config.h
Normal file
|
|
@ -0,0 +1,226 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_H
|
||||
#define CONFIG_H
|
||||
|
||||
/* chip level conf */
|
||||
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
|
||||
#define RHINO_CONFIG_LITTLE_ENDIAN 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
|
||||
#define RHINO_CONFIG_CPU_STACK_DOWN 1
|
||||
#endif
|
||||
|
||||
/* kernel feature conf */
|
||||
#ifndef RHINO_CONFIG_SEM
|
||||
#define RHINO_CONFIG_SEM 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_QUEUE
|
||||
#define RHINO_CONFIG_QUEUE 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TASK_SEM
|
||||
#define RHINO_CONFIG_TASK_SEM 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_EVENT_FLAG
|
||||
#define RHINO_CONFIG_EVENT_FLAG 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TIMER
|
||||
#define RHINO_CONFIG_TIMER 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_BUF_QUEUE
|
||||
#define RHINO_CONFIG_BUF_QUEUE 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_MM_BLK
|
||||
#define RHINO_CONFIG_MM_BLK 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_MM_DEBUG
|
||||
#define RHINO_CONFIG_MM_DEBUG 0
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_MM_TLF
|
||||
#define RHINO_CONFIG_MM_TLF 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
|
||||
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
|
||||
#endif
|
||||
#define K_MM_STATISTIC 0
|
||||
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
|
||||
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_GCC_RETADDR
|
||||
#define RHINO_CONFIG_GCC_RETADDR 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_MM_LEAKCHECK
|
||||
#define RHINO_CONFIG_MM_LEAKCHECK 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
|
||||
#define RHINO_CONFIG_RINGBUF_VENDOR 0
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_KOBJ_SET
|
||||
#define RHINO_CONFIG_KOBJ_SET 0
|
||||
#endif
|
||||
|
||||
/* kernel task conf */
|
||||
#ifndef RHINO_CONFIG_TASK_SUSPEND
|
||||
#define RHINO_CONFIG_TASK_SUSPEND 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TASK_INFO
|
||||
#define RHINO_CONFIG_TASK_INFO 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TASK_DEL
|
||||
#define RHINO_CONFIG_TASK_DEL 1
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
|
||||
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 0
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
|
||||
#define RHINO_CONFIG_TASK_WAIT_ABORT 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
|
||||
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_SCHED_RR
|
||||
#define RHINO_CONFIG_SCHED_RR 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
|
||||
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_PRI_MAX
|
||||
#define RHINO_CONFIG_PRI_MAX 62
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_USER_PRI_MAX
|
||||
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
|
||||
#endif
|
||||
|
||||
/* kernel workqueue conf */
|
||||
#ifndef RHINO_CONFIG_WORKQUEUE
|
||||
#define RHINO_CONFIG_WORKQUEUE 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
|
||||
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
|
||||
#endif
|
||||
|
||||
/* kernel mm_region conf */
|
||||
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
|
||||
#define RHINO_CONFIG_MM_REGION_MUTEX 0
|
||||
#endif
|
||||
|
||||
/* kernel timer&tick conf */
|
||||
#ifndef RHINO_CONFIG_HW_COUNT
|
||||
#define RHINO_CONFIG_HW_COUNT 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TICK_TASK
|
||||
#define RHINO_CONFIG_TICK_TASK 0
|
||||
#endif
|
||||
|
||||
#if (RHINO_CONFIG_TICK_TASK > 0)
|
||||
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
|
||||
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TICK_TASK_PRI
|
||||
#define RHINO_CONFIG_TICK_TASK_PRI 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_TICKLESS
|
||||
#define RHINO_CONFIG_TICKLESS 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
|
||||
#define RHINO_CONFIG_TICKS_PER_SECOND 1000
|
||||
#endif
|
||||
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
|
||||
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
|
||||
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
|
||||
#endif
|
||||
|
||||
/*must reserve enough stack size for timer cb will consume*/
|
||||
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
|
||||
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TIMER_RATE
|
||||
#define RHINO_CONFIG_TIMER_RATE 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
|
||||
#define RHINO_CONFIG_TIMER_TASK_PRI 5
|
||||
#endif
|
||||
|
||||
/* kernel intrpt conf */
|
||||
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
|
||||
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
|
||||
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
|
||||
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_INTRPT_GUARD
|
||||
#define RHINO_CONFIG_INTRPT_GUARD 0
|
||||
#endif
|
||||
|
||||
/* kernel dyn alloc conf */
|
||||
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
|
||||
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 0
|
||||
#endif
|
||||
|
||||
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
|
||||
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
|
||||
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
|
||||
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
|
||||
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* kernel idle conf */
|
||||
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
|
||||
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 100
|
||||
#endif
|
||||
|
||||
/* kernel hook conf */
|
||||
#ifndef RHINO_CONFIG_USER_HOOK
|
||||
#define RHINO_CONFIG_USER_HOOK 0
|
||||
#endif
|
||||
|
||||
/* kernel stats conf */
|
||||
#ifndef RHINO_CONFIG_SYSTEM_STATS
|
||||
#define RHINO_CONFIG_SYSTEM_STATS 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
|
||||
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
|
||||
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
|
||||
#define RHINO_CONFIG_CPU_USAGE_STATS 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
|
||||
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
|
||||
#define RHINO_CONFIG_TASK_SCHED_STATS 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
|
||||
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_CPU_NUM
|
||||
#define RHINO_CONFIG_CPU_NUM 1
|
||||
#endif
|
||||
|
||||
/* kernel trace conf */
|
||||
#ifndef RHINO_CONFIG_TRACE
|
||||
#define RHINO_CONFIG_TRACE 0
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_H */
|
||||
|
||||
15
Living_SDK/platform/mcu/r5f100lea/ccrl/soc_impl.c
Normal file
15
Living_SDK/platform/mcu/r5f100lea/ccrl/soc_impl.c
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
|
||||
*/
|
||||
|
||||
#include <k_api.h>
|
||||
#include <stdio.h>
|
||||
|
||||
void soc_err_proc(kstat_t err)
|
||||
{
|
||||
(void)err;
|
||||
while(1);
|
||||
}
|
||||
|
||||
krhino_err_proc_t g_err_proc = soc_err_proc;
|
||||
|
||||
83
Living_SDK/platform/mcu/r5f100lea/iar/bsp.c
Normal file
83
Living_SDK/platform/mcu/r5f100lea/iar/bsp.c
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
#include <k_api.h>
|
||||
#include "bsp.h"
|
||||
|
||||
uint32_t sys_freq(void);
|
||||
|
||||
void int_dummy(void)
|
||||
{
|
||||
while (1);
|
||||
}
|
||||
|
||||
void tick_init(uint32_t ticks_per_sec)
|
||||
{
|
||||
REG_PER0 |= PER0_ENABLE_CLOCK;
|
||||
REG_TPS0 = TPS0_SET_CLOCK_FRQ;
|
||||
REG_TMR00 = TMR00_SET_CK00_SRC;
|
||||
|
||||
REG_TDR00 = (sys_freq() / ticks_per_sec) - 1;
|
||||
|
||||
REG_TOE0 &= 0x00FE;
|
||||
REG_TO0 &= 0x00FE;
|
||||
REG_TOM0 &= 0x00FE;
|
||||
REG_TOL0 &= 0x00FE;
|
||||
|
||||
REG_PR01L |= 0x10;
|
||||
REG_PR11L |= 0x10;
|
||||
|
||||
REG_IF1L &= ~BIT_04;
|
||||
REG_MK1L &= ~BIT_04;
|
||||
REG_TS0 |= TS0_EN_TMR_OUTPUT;
|
||||
}
|
||||
|
||||
uint32_t sys_freq(void)
|
||||
{
|
||||
uint8_t freq_sel;
|
||||
uint8_t clk_src;
|
||||
uint32_t cpu_clk;
|
||||
|
||||
freq_sel = OPTBYTE2_VAL & 0x0F;
|
||||
clk_src = REG_CLK_GEN_CKC;
|
||||
if (BIT_IS_SET(clk_src, BIT_CKC_CSS)) {
|
||||
cpu_clk = FSUB_CLKRATE;
|
||||
if (BIT_IS_SET(clk_src, BIT_CKC_MCM0)) {
|
||||
clk_src = REG_CLK_GEN_CMC;
|
||||
cpu_clk = FMX_CLKRATE;
|
||||
} else {
|
||||
switch(freq_sel) {
|
||||
case FRQSEL_32MHz:
|
||||
cpu_clk = CLKRATE32;
|
||||
break;
|
||||
|
||||
case FRQSEL_24MHz:
|
||||
cpu_clk = CLKRATE24;
|
||||
break;
|
||||
|
||||
case FRQSEL_16MHz:
|
||||
cpu_clk = CLKRATE16;
|
||||
break;
|
||||
|
||||
case FRQSEL_12MHz:
|
||||
cpu_clk = CLKRATE12;
|
||||
break;
|
||||
|
||||
case FRQSEL_8MHz:
|
||||
cpu_clk = CLKRATE08;
|
||||
break;
|
||||
|
||||
case FRQSEL_4MHz:
|
||||
cpu_clk = CLKRATE04;
|
||||
break;
|
||||
|
||||
case FRQSEL_1MHz:
|
||||
cpu_clk = CLKRATE01;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return (cpu_clk);
|
||||
}
|
||||
|
||||
122
Living_SDK/platform/mcu/r5f100lea/iar/bsp.h
Normal file
122
Living_SDK/platform/mcu/r5f100lea/iar/bsp.h
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
#ifndef BSP_H
|
||||
#define BSP_H
|
||||
|
||||
#define CLK_GEN_BASE_ADDR ((uint32_t )0x000FFF00u)
|
||||
#define REG_CLK_GEN_CMC (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA0u))
|
||||
#define REG_CLK_GEN_CKC (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA4u))
|
||||
#define REG_CLK_GEN_CSC (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA1u))
|
||||
#define REG_CLK_GEN_OSTC (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA2u))
|
||||
#define REG_CLK_GEN_OSTS (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA3u))
|
||||
#define REG_CLK_GEN_OSMC (*(volatile uint8_t __far*)(0xF0000000 + 0xF3u))
|
||||
#define REG_CLK_GEN_HOCODIV (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA8u))
|
||||
#define REG_CLK_GEN_HIOTRM (*(volatile uint8_t __far*)(CLK_GEN_BASE_ADDR + 0xA0u))
|
||||
|
||||
#define REG_PORT_BASE_ADDR_00 ((uint32_t )0x000F0000u)
|
||||
|
||||
#define REG_P(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0xFF00 + n ))
|
||||
#define REG_PM(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0xFF20 + n ))
|
||||
#define REG_PU(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0x30 + n ))
|
||||
#define REG_PIM(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0x40 + n ))
|
||||
#define REG_POM(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0x50 + n ))
|
||||
#define REG_PMC(n) (*(volatile uint8_t __far*)(REG_PORT_BASE_ADDR_00 + 0x60 + n ))
|
||||
|
||||
#define REG_PER0 (*(volatile uint8_t __far*)0x000F00F0u)
|
||||
|
||||
#define REG_TPS0 (*(volatile uint16_t __far*)0x000F01B6u)
|
||||
#define REG_TMR00 (*(volatile uint16_t __far*)0x000F0190u)
|
||||
#define REG_TDR00 (*(volatile uint16_t __far*)0x000FFF18u)
|
||||
#define REG_TOE0 (*(volatile uint16_t __far*)0x000F01BAu)
|
||||
#define REG_TO0 (*(volatile uint16_t __far*)0x000F01B8u)
|
||||
#define REG_TOM0 (*(volatile uint16_t __far*)0x000F01BEu)
|
||||
#define REG_TOL0 (*(volatile uint16_t __far*)0x000F01BCu)
|
||||
#define REG_TS0 (*(volatile uint16_t __far*)0x000F01B2u)
|
||||
|
||||
#define REG_PR01L (*(volatile uint8_t __far*)0x000FFFEAu)
|
||||
#define REG_PR11L (*(volatile uint8_t __far*)0x000FFFEEu)
|
||||
|
||||
#define REG_IF1L (*(volatile uint8_t __far*)0x000FFFE2u)
|
||||
#define REG_MK1L (*(volatile uint8_t __far*)0x000FFFE6u)
|
||||
|
||||
#define BIT_MASK(bit_mask, bit_shift) ((bit_mask) << (bit_shift))
|
||||
#define BIT_IS_SET(val, mask) ((((mask) != 0u) && \
|
||||
(((val) & (mask)) == (mask))) ? (1) : (0))
|
||||
|
||||
#define BIT_NONE 0x00u
|
||||
#define BIT_00 0x01u
|
||||
#define BIT_01 0x02u
|
||||
#define BIT_02 0x04u
|
||||
#define BIT_03 0x08u
|
||||
#define BIT_04 0x10u
|
||||
#define BIT_05 0x20u
|
||||
#define BIT_06 0x40u
|
||||
#define BIT_07 0x80u
|
||||
#define BIT_08 0x0100u
|
||||
|
||||
#define REG_PIOR (*(volatile uint8_t __far*)0x000F0077u)
|
||||
#define REG_CRC0CTL (*(volatile uint8_t __far*)0x000F02F0u)
|
||||
#define REG_IAWCTL (*(volatile uint8_t __far*)0x000F0078u)
|
||||
#define REG_PMS (*(volatile uint8_t __far*)0x000F007Bu)
|
||||
|
||||
#define BIT_CKC_MCM0 BIT_04
|
||||
#define BIT_CKC_MCS BIT_05
|
||||
#define BIT_CSC_MSTOP BIT_06
|
||||
#define BIT_CSC_XTSTOP BIT_06
|
||||
#define BIT_CKC_CSS BIT_06
|
||||
#define BIT_CSC_HIOSTOP BIT_00
|
||||
#define BIT_CMC_AMPH BIT_00
|
||||
|
||||
#define BIT_MK1L_TMMK00 BIT_04
|
||||
#define BIT_IF1L_TMIF00 BIT_04
|
||||
#define BIT_PRO1L_TMPR000 BIT_04
|
||||
#define BIT_PR11L_TMPR100 BIT_04
|
||||
|
||||
#define OSC_HSCLK_INPUT BIT_NONE
|
||||
#define OSC_SUBCLK_INPUT BIT_NONE
|
||||
#define OSC_XT1_DEFAULT BIT_NONE
|
||||
#define OSC_FRQ_DEFAULT BIT_NONE
|
||||
|
||||
#define OSCSTAB_SEL_26_21ms BIT_MASK(7, 0)
|
||||
#define OSCSTAB_STA 0xFFu
|
||||
|
||||
#define CLK_SUBINHALT_ON BIT_NONE
|
||||
#define CLK_FSUB_ON BIT_NONE
|
||||
|
||||
|
||||
#define OSCSUB_WAITTIME 160
|
||||
|
||||
#define CLKFREQ_DIV 512
|
||||
|
||||
#define FSUB_CLKRATE 32768
|
||||
#define LOWSPEED_CLKRATE 15000
|
||||
|
||||
#define FMX_CLKRATE 12000000
|
||||
|
||||
#define CLKRATE32 32000000
|
||||
#define CLKRATE24 24000000
|
||||
#define CLKRATE16 16000000
|
||||
#define CLKRATE12 12000000
|
||||
#define CLKRATE08 8000000
|
||||
#define CLKRATE04 4000000
|
||||
#define CLKRATE01 1000000
|
||||
|
||||
#define FRQSEL_1MHz 0x0D
|
||||
#define FRQSEL_4MHz 0x0B
|
||||
#define FRQSEL_8MHz 0x0A
|
||||
#define FRQSEL_12MHz 0x01
|
||||
#define FRQSEL_16MHz 0x09
|
||||
#define FRQSEL_24MHz 0x00
|
||||
#define FRQSEL_32MHz 0x08
|
||||
|
||||
#define PIOR_REDIRECT_DIS 0x00
|
||||
#define CRC0CTL_FLASH_OFF 0x00
|
||||
#define IWACTL_INVALID_MEM_DET_OFF 0x00
|
||||
#define PMS_PORT_MODE_READ 0x00
|
||||
|
||||
#define PER0_ENABLE_CLOCK 0x0001
|
||||
#define TPS0_SET_CLOCK_FRQ 0x0000
|
||||
#define TMR00_SET_CK00_SRC 0x0000
|
||||
#define TS0_EN_TMR_OUTPUT 0x0001
|
||||
#define OPTBYTE2_VAL 0xE8u
|
||||
|
||||
#endif
|
||||
|
||||
513
Living_SDK/platform/mcu/r5f100lea/iar/bsp_vect_a.asm
Normal file
513
Living_SDK/platform/mcu/r5f100lea/iar/bsp_vect_a.asm
Normal file
|
|
@ -0,0 +1,513 @@
|
|||
|
||||
#include "port_cpu.inc"
|
||||
|
||||
NAME ?bsp_vect
|
||||
|
||||
EXTERN _int_dummy
|
||||
EXTERN _krhino_tick_proc
|
||||
PUBLIC SOC_WDTI
|
||||
PUBLIC SOC_LVI
|
||||
PUBLIC SOC_P0
|
||||
PUBLIC SOC_P1
|
||||
PUBLIC SOC_P2
|
||||
PUBLIC SOC_P3
|
||||
PUBLIC SOC_P4
|
||||
PUBLIC SOC_P5
|
||||
PUBLIC SOC_ST2_CSI20_IIC20
|
||||
PUBLIC SOC_SR2_CSI20_IIC21
|
||||
PUBLIC SOC_SRE2_TM11H
|
||||
PUBLIC SOC_DMA0
|
||||
PUBLIC SOC_DMA1
|
||||
PUBLIC SOC_ST0_CSI00_IIC00
|
||||
PUBLIC SOC_ST0_CSI00_IIC00
|
||||
PUBLIC SOC_SR0_CSI01_IIC01
|
||||
PUBLIC SOC_SRE0_TM01H
|
||||
PUBLIC SOC_ST1_CSI10_IIC10
|
||||
PUBLIC SOC_SR1_CSI11_IIC11
|
||||
PUBLIC SOC_IICA0
|
||||
PUBLIC SOC_TM00
|
||||
PUBLIC SOC_TM01
|
||||
PUBLIC SOC_TM02
|
||||
PUBLIC SOC_TM03
|
||||
PUBLIC SOC_AD
|
||||
PUBLIC SOC_RTC
|
||||
PUBLIC SOC_IT
|
||||
PUBLIC SOC_KR
|
||||
PUBLIC SOC_ST3_CSI30_IIC30
|
||||
PUBLIC SOC_SR3_CSI31_IIC31
|
||||
PUBLIC SOC_TM13
|
||||
PUBLIC SOC_TM04
|
||||
PUBLIC SOC_TM05
|
||||
PUBLIC SOC_TM06
|
||||
PUBLIC SOC_TM07
|
||||
PUBLIC SOC_P6
|
||||
PUBLIC SOC_P7
|
||||
PUBLIC SOC_P8
|
||||
PUBLIC SOC_P9
|
||||
PUBLIC SOC_P10
|
||||
PUBLIC SOC_P11
|
||||
PUBLIC SOC_TM10
|
||||
PUBLIC SOC_TM11
|
||||
PUBLIC SOC_TM12
|
||||
PUBLIC SOC_SRE3_TM13H
|
||||
PUBLIC SOC_MD
|
||||
PUBLIC SOC_IICA1
|
||||
PUBLIC SOC_FL
|
||||
PUBLIC SOC_DMA2
|
||||
PUBLIC SOC_DMA3
|
||||
PUBLIC SOC_TM14
|
||||
PUBLIC SOC_TM15
|
||||
PUBLIC SOC_TM16
|
||||
PUBLIC SOC_TM17
|
||||
|
||||
PUBLIC ___interrupt_0x04
|
||||
PUBLIC ___interrupt_0x06
|
||||
PUBLIC ___interrupt_0x08
|
||||
PUBLIC ___interrupt_0x0A
|
||||
PUBLIC ___interrupt_0x0C
|
||||
PUBLIC ___interrupt_0x0E
|
||||
PUBLIC ___interrupt_0x10
|
||||
PUBLIC ___interrupt_0x12
|
||||
PUBLIC ___interrupt_0x14
|
||||
PUBLIC ___interrupt_0x16
|
||||
PUBLIC ___interrupt_0x18
|
||||
PUBLIC ___interrupt_0x1A
|
||||
PUBLIC ___interrupt_0x1C
|
||||
PUBLIC ___interrupt_0x1E
|
||||
PUBLIC ___interrupt_0x20
|
||||
PUBLIC ___interrupt_0x22
|
||||
PUBLIC ___interrupt_0x24
|
||||
PUBLIC ___interrupt_0x26
|
||||
PUBLIC ___interrupt_0x28
|
||||
PUBLIC ___interrupt_0x2A
|
||||
PUBLIC ___interrupt_0x2C
|
||||
PUBLIC ___interrupt_0x2E
|
||||
PUBLIC ___interrupt_0x30
|
||||
PUBLIC ___interrupt_0x32
|
||||
PUBLIC ___interrupt_0x34
|
||||
PUBLIC ___interrupt_0x36
|
||||
PUBLIC ___interrupt_0x38
|
||||
PUBLIC ___interrupt_0x3A
|
||||
PUBLIC ___interrupt_0x3C
|
||||
PUBLIC ___interrupt_0x3E
|
||||
PUBLIC ___interrupt_0x40
|
||||
PUBLIC ___interrupt_0x42
|
||||
PUBLIC ___interrupt_0x44
|
||||
PUBLIC ___interrupt_0x46
|
||||
PUBLIC ___interrupt_0x48
|
||||
PUBLIC ___interrupt_0x4A
|
||||
PUBLIC ___interrupt_0x4C
|
||||
PUBLIC ___interrupt_0x4E
|
||||
PUBLIC ___interrupt_0x50
|
||||
PUBLIC ___interrupt_0x52
|
||||
PUBLIC ___interrupt_0x54
|
||||
PUBLIC ___interrupt_0x56
|
||||
PUBLIC ___interrupt_0x58
|
||||
PUBLIC ___interrupt_0x5A
|
||||
PUBLIC ___interrupt_0x5C
|
||||
PUBLIC ___interrupt_0x5E
|
||||
PUBLIC ___interrupt_0x60
|
||||
PUBLIC ___interrupt_0x62
|
||||
PUBLIC ___interrupt_0x64
|
||||
PUBLIC ___interrupt_0x66
|
||||
PUBLIC ___interrupt_0x68
|
||||
PUBLIC ___interrupt_0x6A
|
||||
PUBLIC ___interrupt_0x6C
|
||||
PUBLIC ___interrupt_0x6E
|
||||
|
||||
;********************************************************************************************************
|
||||
; OPTION BYTES CONFIGURATIONS
|
||||
;********************************************************************************************************
|
||||
|
||||
SECTION .option_byte:CODE:ROOT(1)
|
||||
DB 0xEF, 0x57, 0xE8, 0x84
|
||||
|
||||
SECTION .security_id:CODE:ROOT(1)
|
||||
DB 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
;********************************************************************************************************
|
||||
; INTERRUPT HANDLERS
|
||||
;********************************************************************************************************
|
||||
|
||||
SECTION .text:CODE:ROOT(1)
|
||||
|
||||
SOC_WDTI:
|
||||
___interrupt_0x04:
|
||||
sys_isr_enter
|
||||
MOVW AX, #0
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_LVI:
|
||||
___interrupt_0x06:
|
||||
sys_isr_enter
|
||||
MOVW AX, #1
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P0:
|
||||
___interrupt_0x08:
|
||||
sys_isr_enter
|
||||
MOVW AX, #2
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P1:
|
||||
___interrupt_0x0A:
|
||||
sys_isr_enter
|
||||
MOVW AX, #3
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P2:
|
||||
___interrupt_0x0C:
|
||||
sys_isr_enter
|
||||
MOVW AX, #4
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P3:
|
||||
___interrupt_0x0E:
|
||||
sys_isr_enter
|
||||
MOVW AX, #5
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P4:
|
||||
___interrupt_0x10:
|
||||
sys_isr_enter
|
||||
MOVW AX, #6
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P5:
|
||||
___interrupt_0x12:
|
||||
sys_isr_enter
|
||||
MOVW AX, #7
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_ST2_CSI20_IIC20:
|
||||
___interrupt_0x14:
|
||||
sys_isr_enter
|
||||
MOVW AX, #8
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_SR2_CSI20_IIC21:
|
||||
___interrupt_0x16:
|
||||
sys_isr_enter
|
||||
MOVW AX, #9
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_SRE2_TM11H:
|
||||
___interrupt_0x18:
|
||||
sys_isr_enter
|
||||
MOVW AX, #10
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_DMA0:
|
||||
___interrupt_0x1A:
|
||||
sys_isr_enter
|
||||
MOVW AX, #11
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_DMA1:
|
||||
___interrupt_0x1C:
|
||||
sys_isr_enter
|
||||
MOVW AX, #12
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_ST0_CSI00_IIC00:
|
||||
___interrupt_0x1E:
|
||||
sys_isr_enter
|
||||
MOVW AX, #13
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_SR0_CSI01_IIC01:
|
||||
___interrupt_0x20:
|
||||
sys_isr_enter
|
||||
MOVW AX, #14
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_SRE0_TM01H:
|
||||
___interrupt_0x22:
|
||||
sys_isr_enter
|
||||
MOVW AX, #15
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_ST1_CSI10_IIC10:
|
||||
___interrupt_0x24:
|
||||
sys_isr_enter
|
||||
MOVW AX, #16
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_SR1_CSI11_IIC11:
|
||||
___interrupt_0x26:
|
||||
sys_isr_enter
|
||||
MOVW AX, #17
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_SRE1_TM03H:
|
||||
___interrupt_0x28:
|
||||
sys_isr_enter
|
||||
MOVW AX, #18
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_IICA0:
|
||||
___interrupt_0x2A:
|
||||
sys_isr_enter
|
||||
MOVW AX, #19
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM00:
|
||||
___interrupt_0x2C:
|
||||
sys_isr_enter
|
||||
MOVW AX, #20
|
||||
CALL _krhino_tick_proc
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM01:
|
||||
___interrupt_0x2E:
|
||||
sys_isr_enter
|
||||
MOVW AX, #21
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM02:
|
||||
___interrupt_0x30:
|
||||
sys_isr_enter
|
||||
MOVW AX, #22
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM03:
|
||||
___interrupt_0x32:
|
||||
sys_isr_enter
|
||||
MOVW AX, #23
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_AD:
|
||||
___interrupt_0x34:
|
||||
sys_isr_enter
|
||||
MOVW AX, #24
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_RTC:
|
||||
___interrupt_0x36:
|
||||
sys_isr_enter
|
||||
MOVW AX, #25
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_IT:
|
||||
___interrupt_0x38:
|
||||
sys_isr_enter
|
||||
MOVW AX, #26
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_KR:
|
||||
___interrupt_0x3A:
|
||||
sys_isr_enter
|
||||
MOVW AX, #27
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_ST3_CSI30_IIC30:
|
||||
___interrupt_0x3C:
|
||||
sys_isr_enter
|
||||
MOVW AX, #28
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_SR3_CSI31_IIC31:
|
||||
___interrupt_0x3E:
|
||||
sys_isr_enter
|
||||
MOVW AX, #29
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM13:
|
||||
___interrupt_0x40:
|
||||
sys_isr_enter
|
||||
MOVW AX, #30
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM04:
|
||||
___interrupt_0x42:
|
||||
sys_isr_enter
|
||||
MOVW AX, #31
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM05:
|
||||
___interrupt_0x44:
|
||||
sys_isr_enter
|
||||
MOVW AX, #32
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM06:
|
||||
___interrupt_0x46:
|
||||
sys_isr_enter
|
||||
MOVW AX, #33
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM07:
|
||||
___interrupt_0x48:
|
||||
sys_isr_enter
|
||||
MOVW AX, #34
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P6:
|
||||
___interrupt_0x4A:
|
||||
sys_isr_enter
|
||||
MOVW AX, #35
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P7:
|
||||
___interrupt_0x4C:
|
||||
sys_isr_enter
|
||||
MOVW AX, #36
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P8:
|
||||
___interrupt_0x4E:
|
||||
sys_isr_enter
|
||||
MOVW AX, #37
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P9:
|
||||
___interrupt_0x50:
|
||||
sys_isr_enter
|
||||
MOVW AX, #38
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P10:
|
||||
___interrupt_0x52:
|
||||
sys_isr_enter
|
||||
MOVW AX, #39
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_P11:
|
||||
___interrupt_0x54:
|
||||
sys_isr_enter
|
||||
MOVW AX, #40
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM10:
|
||||
___interrupt_0x56:
|
||||
sys_isr_enter
|
||||
MOVW AX, #41
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM11:
|
||||
___interrupt_0x58:
|
||||
sys_isr_enter
|
||||
MOVW AX, #42
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM12:
|
||||
___interrupt_0x5A:
|
||||
sys_isr_enter
|
||||
MOVW AX, #43
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_SRE3_TM13H:
|
||||
___interrupt_0x5C:
|
||||
sys_isr_enter
|
||||
MOVW AX, #44
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_MD:
|
||||
___interrupt_0x5E:
|
||||
sys_isr_enter
|
||||
MOVW AX, #45
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_IICA1:
|
||||
___interrupt_0x60:
|
||||
sys_isr_enter
|
||||
MOVW AX, #46
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_FL:
|
||||
___interrupt_0x62:
|
||||
sys_isr_enter
|
||||
MOVW AX, #47
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_DMA2:
|
||||
___interrupt_0x64:
|
||||
sys_isr_enter
|
||||
MOVW AX, #48
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_DMA3:
|
||||
___interrupt_0x66:
|
||||
sys_isr_enter
|
||||
MOVW AX, #49
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM14:
|
||||
___interrupt_0x68:
|
||||
sys_isr_enter
|
||||
MOVW AX, #50
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM15:
|
||||
___interrupt_0x6A:
|
||||
sys_isr_enter
|
||||
MOVW AX, #51
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM16:
|
||||
___interrupt_0x6C:
|
||||
sys_isr_enter
|
||||
MOVW AX, #52
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
SOC_TM17:
|
||||
___interrupt_0x6E:
|
||||
sys_isr_enter
|
||||
MOVW AX, #53
|
||||
CALL _int_dummy
|
||||
sys_isr_exit
|
||||
|
||||
END
|
||||
|
||||
226
Living_SDK/platform/mcu/r5f100lea/iar/k_config.h
Normal file
226
Living_SDK/platform/mcu/r5f100lea/iar/k_config.h
Normal file
|
|
@ -0,0 +1,226 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_H
|
||||
#define CONFIG_H
|
||||
|
||||
/* chip level conf */
|
||||
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
|
||||
#define RHINO_CONFIG_LITTLE_ENDIAN 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
|
||||
#define RHINO_CONFIG_CPU_STACK_DOWN 1
|
||||
#endif
|
||||
|
||||
/* kernel feature conf */
|
||||
#ifndef RHINO_CONFIG_SEM
|
||||
#define RHINO_CONFIG_SEM 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_QUEUE
|
||||
#define RHINO_CONFIG_QUEUE 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TASK_SEM
|
||||
#define RHINO_CONFIG_TASK_SEM 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_EVENT_FLAG
|
||||
#define RHINO_CONFIG_EVENT_FLAG 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TIMER
|
||||
#define RHINO_CONFIG_TIMER 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_BUF_QUEUE
|
||||
#define RHINO_CONFIG_BUF_QUEUE 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_MM_BLK
|
||||
#define RHINO_CONFIG_MM_BLK 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_MM_DEBUG
|
||||
#define RHINO_CONFIG_MM_DEBUG 0
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_MM_TLF
|
||||
#define RHINO_CONFIG_MM_TLF 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
|
||||
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
|
||||
#endif
|
||||
#define K_MM_STATISTIC 0
|
||||
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
|
||||
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_GCC_RETADDR
|
||||
#define RHINO_CONFIG_GCC_RETADDR 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_MM_LEAKCHECK
|
||||
#define RHINO_CONFIG_MM_LEAKCHECK 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
|
||||
#define RHINO_CONFIG_RINGBUF_VENDOR 0
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_KOBJ_SET
|
||||
#define RHINO_CONFIG_KOBJ_SET 0
|
||||
#endif
|
||||
|
||||
/* kernel task conf */
|
||||
#ifndef RHINO_CONFIG_TASK_SUSPEND
|
||||
#define RHINO_CONFIG_TASK_SUSPEND 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TASK_INFO
|
||||
#define RHINO_CONFIG_TASK_INFO 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TASK_DEL
|
||||
#define RHINO_CONFIG_TASK_DEL 1
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
|
||||
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 0
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
|
||||
#define RHINO_CONFIG_TASK_WAIT_ABORT 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
|
||||
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_SCHED_RR
|
||||
#define RHINO_CONFIG_SCHED_RR 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
|
||||
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_PRI_MAX
|
||||
#define RHINO_CONFIG_PRI_MAX 62
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_USER_PRI_MAX
|
||||
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
|
||||
#endif
|
||||
|
||||
/* kernel workqueue conf */
|
||||
#ifndef RHINO_CONFIG_WORKQUEUE
|
||||
#define RHINO_CONFIG_WORKQUEUE 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
|
||||
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
|
||||
#endif
|
||||
|
||||
/* kernel mm_region conf */
|
||||
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
|
||||
#define RHINO_CONFIG_MM_REGION_MUTEX 0
|
||||
#endif
|
||||
|
||||
/* kernel timer&tick conf */
|
||||
#ifndef RHINO_CONFIG_HW_COUNT
|
||||
#define RHINO_CONFIG_HW_COUNT 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TICK_TASK
|
||||
#define RHINO_CONFIG_TICK_TASK 0
|
||||
#endif
|
||||
|
||||
#if (RHINO_CONFIG_TICK_TASK > 0)
|
||||
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
|
||||
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TICK_TASK_PRI
|
||||
#define RHINO_CONFIG_TICK_TASK_PRI 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_TICKLESS
|
||||
#define RHINO_CONFIG_TICKLESS 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
|
||||
#define RHINO_CONFIG_TICKS_PER_SECOND 1000
|
||||
#endif
|
||||
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
|
||||
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
|
||||
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
|
||||
#endif
|
||||
|
||||
/*must reserve enough stack size for timer cb will consume*/
|
||||
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
|
||||
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TIMER_RATE
|
||||
#define RHINO_CONFIG_TIMER_RATE 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
|
||||
#define RHINO_CONFIG_TIMER_TASK_PRI 5
|
||||
#endif
|
||||
|
||||
/* kernel intrpt conf */
|
||||
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
|
||||
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
|
||||
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
|
||||
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_INTRPT_GUARD
|
||||
#define RHINO_CONFIG_INTRPT_GUARD 0
|
||||
#endif
|
||||
|
||||
/* kernel dyn alloc conf */
|
||||
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
|
||||
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 0
|
||||
#endif
|
||||
|
||||
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
|
||||
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
|
||||
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
|
||||
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
|
||||
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* kernel idle conf */
|
||||
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
|
||||
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 100
|
||||
#endif
|
||||
|
||||
/* kernel hook conf */
|
||||
#ifndef RHINO_CONFIG_USER_HOOK
|
||||
#define RHINO_CONFIG_USER_HOOK 0
|
||||
#endif
|
||||
|
||||
/* kernel stats conf */
|
||||
#ifndef RHINO_CONFIG_SYSTEM_STATS
|
||||
#define RHINO_CONFIG_SYSTEM_STATS 1
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
|
||||
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
|
||||
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
|
||||
#define RHINO_CONFIG_CPU_USAGE_STATS 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
|
||||
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
|
||||
#define RHINO_CONFIG_TASK_SCHED_STATS 0
|
||||
#endif
|
||||
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
|
||||
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
|
||||
#endif
|
||||
|
||||
#ifndef RHINO_CONFIG_CPU_NUM
|
||||
#define RHINO_CONFIG_CPU_NUM 1
|
||||
#endif
|
||||
|
||||
/* kernel trace conf */
|
||||
#ifndef RHINO_CONFIG_TRACE
|
||||
#define RHINO_CONFIG_TRACE 0
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_H */
|
||||
|
||||
15
Living_SDK/platform/mcu/r5f100lea/iar/soc_impl.c
Normal file
15
Living_SDK/platform/mcu/r5f100lea/iar/soc_impl.c
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
|
||||
*/
|
||||
|
||||
#include <k_api.h>
|
||||
#include <stdio.h>
|
||||
|
||||
void soc_err_proc(kstat_t err)
|
||||
{
|
||||
(void)err;
|
||||
while(1);
|
||||
}
|
||||
|
||||
krhino_err_proc_t g_err_proc = soc_err_proc;
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue