mirror of
https://github.com/Ai-Thinker-Open/Ai-Thinker-Open_RTL8710BX_ALIOS_SDK.git
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rel_1.6.0 init
This commit is contained in:
guocheng.kgc
shengdong.dsd
commit
27b3e2883d
19359 changed files with 8093121 additions and 0 deletions
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{\f14\fbidi \froman\fcharset136\fprq2{\*\panose 02020500000000000000}PMingLiU{\*\falt \'b7\'73\'b2\'d3\'a9\'fa\'c5\'e9};}{\f34\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria Math;}
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{\f37\fbidi \fswiss\fcharset0\fprq2{\*\panose 020f0502020204030204}Calibri;}{\f38\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604030504040204}Tahoma;}{\f39\fbidi \fmodern\fcharset0\fprq1{\*\panose 020b0609020204030204}Consolas;}
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{\f40\fbidi \froman\fcharset136\fprq2{\*\panose 02020500000000000000}@PMingLiU;}{\flomajor\f31500\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}
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{\fdbmajor\f31501\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\fhimajor\f31502\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria;}
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{\fbimajor\f31503\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\flominor\f31504\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}
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{\fdbminor\f31505\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\fhiminor\f31506\fbidi \fswiss\fcharset0\fprq2{\*\panose 020f0502020204030204}Calibri;}
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{\fbiminor\f31507\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f41\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\f42\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
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{\f44\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\f45\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\f46\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\f47\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
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{\f48\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\f49\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\f51\fbidi \fswiss\fcharset238\fprq2 Arial CE;}{\f52\fbidi \fswiss\fcharset204\fprq2 Arial Cyr;}
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{\f54\fbidi \fswiss\fcharset161\fprq2 Arial Greek;}{\f55\fbidi \fswiss\fcharset162\fprq2 Arial Tur;}{\f56\fbidi \fswiss\fcharset177\fprq2 Arial (Hebrew);}{\f57\fbidi \fswiss\fcharset178\fprq2 Arial (Arabic);}
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{\f58\fbidi \fswiss\fcharset186\fprq2 Arial Baltic;}{\f59\fbidi \fswiss\fcharset163\fprq2 Arial (Vietnamese);}{\f61\fbidi \fmodern\fcharset238\fprq1 Courier New CE;}{\f62\fbidi \fmodern\fcharset204\fprq1 Courier New Cyr;}
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{\f64\fbidi \fmodern\fcharset161\fprq1 Courier New Greek;}{\f65\fbidi \fmodern\fcharset162\fprq1 Courier New Tur;}{\f66\fbidi \fmodern\fcharset177\fprq1 Courier New (Hebrew);}{\f67\fbidi \fmodern\fcharset178\fprq1 Courier New (Arabic);}
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{\f68\fbidi \fmodern\fcharset186\fprq1 Courier New Baltic;}{\f69\fbidi \fmodern\fcharset163\fprq1 Courier New (Vietnamese);}{\f183\fbidi \froman\fcharset0\fprq2 PMingLiU Western{\*\falt \'b7\'73\'b2\'d3\'a9\'fa\'c5\'e9};}
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{\f381\fbidi \froman\fcharset238\fprq2 Cambria Math CE;}{\f382\fbidi \froman\fcharset204\fprq2 Cambria Math Cyr;}{\f384\fbidi \froman\fcharset161\fprq2 Cambria Math Greek;}{\f385\fbidi \froman\fcharset162\fprq2 Cambria Math Tur;}
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{\f388\fbidi \froman\fcharset186\fprq2 Cambria Math Baltic;}{\f389\fbidi \froman\fcharset163\fprq2 Cambria Math (Vietnamese);}{\f411\fbidi \fswiss\fcharset238\fprq2 Calibri CE;}{\f412\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}
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{\f414\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;}{\f415\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;}{\f418\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}{\f419\fbidi \fswiss\fcharset163\fprq2 Calibri (Vietnamese);}
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{\f421\fbidi \fswiss\fcharset238\fprq2 Tahoma CE;}{\f422\fbidi \fswiss\fcharset204\fprq2 Tahoma Cyr;}{\f424\fbidi \fswiss\fcharset161\fprq2 Tahoma Greek;}{\f425\fbidi \fswiss\fcharset162\fprq2 Tahoma Tur;}
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{\f426\fbidi \fswiss\fcharset177\fprq2 Tahoma (Hebrew);}{\f427\fbidi \fswiss\fcharset178\fprq2 Tahoma (Arabic);}{\f428\fbidi \fswiss\fcharset186\fprq2 Tahoma Baltic;}{\f429\fbidi \fswiss\fcharset163\fprq2 Tahoma (Vietnamese);}
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{\f430\fbidi \fswiss\fcharset222\fprq2 Tahoma (Thai);}{\f431\fbidi \fmodern\fcharset238\fprq1 Consolas CE;}{\f432\fbidi \fmodern\fcharset204\fprq1 Consolas Cyr;}{\f434\fbidi \fmodern\fcharset161\fprq1 Consolas Greek;}
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||||
{\f435\fbidi \fmodern\fcharset162\fprq1 Consolas Tur;}{\f438\fbidi \fmodern\fcharset186\fprq1 Consolas Baltic;}{\f439\fbidi \fmodern\fcharset163\fprq1 Consolas (Vietnamese);}{\f443\fbidi \froman\fcharset0\fprq2 @PMingLiU Western;}
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{\flomajor\f31508\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\flomajor\f31509\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\flomajor\f31511\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}
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{\flomajor\f31512\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\flomajor\f31513\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\flomajor\f31514\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
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||||
{\flomajor\f31515\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\flomajor\f31516\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fdbmajor\f31518\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}
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||||
{\fdbmajor\f31519\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fdbmajor\f31521\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fdbmajor\f31522\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}
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||||
{\fdbmajor\f31523\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fdbmajor\f31524\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fdbmajor\f31525\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}
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||||
{\fdbmajor\f31526\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fhimajor\f31528\fbidi \froman\fcharset238\fprq2 Cambria CE;}{\fhimajor\f31529\fbidi \froman\fcharset204\fprq2 Cambria Cyr;}
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||||
{\fhimajor\f31531\fbidi \froman\fcharset161\fprq2 Cambria Greek;}{\fhimajor\f31532\fbidi \froman\fcharset162\fprq2 Cambria Tur;}{\fhimajor\f31535\fbidi \froman\fcharset186\fprq2 Cambria Baltic;}
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||||
{\fhimajor\f31536\fbidi \froman\fcharset163\fprq2 Cambria (Vietnamese);}{\fbimajor\f31538\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fbimajor\f31539\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
|
||||
{\fbimajor\f31541\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fbimajor\f31542\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\fbimajor\f31543\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}
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||||
{\fbimajor\f31544\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbimajor\f31545\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fbimajor\f31546\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}
|
||||
{\flominor\f31548\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\flominor\f31549\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\flominor\f31551\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}
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||||
{\flominor\f31552\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\flominor\f31553\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\flominor\f31554\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}
|
||||
{\flominor\f31555\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\flominor\f31556\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fdbminor\f31558\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}
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||||
{\fdbminor\f31559\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}{\fdbminor\f31561\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fdbminor\f31562\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}
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||||
{\fdbminor\f31563\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}{\fdbminor\f31564\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fdbminor\f31565\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}
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||||
{\fdbminor\f31566\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}{\fhiminor\f31568\fbidi \fswiss\fcharset238\fprq2 Calibri CE;}{\fhiminor\f31569\fbidi \fswiss\fcharset204\fprq2 Calibri Cyr;}
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||||
{\fhiminor\f31571\fbidi \fswiss\fcharset161\fprq2 Calibri Greek;}{\fhiminor\f31572\fbidi \fswiss\fcharset162\fprq2 Calibri Tur;}{\fhiminor\f31575\fbidi \fswiss\fcharset186\fprq2 Calibri Baltic;}
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||||
{\fhiminor\f31576\fbidi \fswiss\fcharset163\fprq2 Calibri (Vietnamese);}{\fbiminor\f31578\fbidi \froman\fcharset238\fprq2 Times New Roman CE;}{\fbiminor\f31579\fbidi \froman\fcharset204\fprq2 Times New Roman Cyr;}
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||||
{\fbiminor\f31581\fbidi \froman\fcharset161\fprq2 Times New Roman Greek;}{\fbiminor\f31582\fbidi \froman\fcharset162\fprq2 Times New Roman Tur;}{\fbiminor\f31583\fbidi \froman\fcharset177\fprq2 Times New Roman (Hebrew);}
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||||
{\fbiminor\f31584\fbidi \froman\fcharset178\fprq2 Times New Roman (Arabic);}{\fbiminor\f31585\fbidi \froman\fcharset186\fprq2 Times New Roman Baltic;}{\fbiminor\f31586\fbidi \froman\fcharset163\fprq2 Times New Roman (Vietnamese);}}
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||||
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||||
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|
||||
\ltrch\fcs0 \fs22\lang2057\langfe1033\loch\f37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 \snext31 \shidden \ssemihidden Revision;}{\s32\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch\fcs1
|
||||
\af0\afs21\alang1025 \ltrch\fcs0 \f39\fs21\lang2057\langfe1033\cgrid\langnp2057\langfenp1033 \sbasedon0 \snext32 \slink33 \sunhideused Plain Text;}{\*\cs33 \additive \f39\fs21\lang0\langfe1033\langfenp1033 \slink32 \slocked Plain Text Char;}{
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||||
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||||
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||||
{\sp{\sn borderLeftColor}{\sv -16777216}}{\sp{\sn borderBottomColor}{\sv -16777216}}{\sp{\sn borderRightColor}{\sv -16777216}}{\sp{\sn fIsBullet}{\sv 1}}{\sp{\sn fLayoutInCell}{\sv 1}}}\picscalex100\picscaley100\piccropl0\piccropr0\piccropt0\piccropb0
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||||
\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext
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||||
\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0
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||||
\ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2
|
||||
\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext
|
||||
\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0
|
||||
\ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid39328222}{\list\listtemplateid-917765150\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1080\lin1080 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel
|
||||
\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }
|
||||
{\listname ;}\listid144588935}{\list\listtemplateid-1026387870{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0
|
||||
\fi-360\li360\lin360 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li360\lin360 }{\listlevel\levelnfc0
|
||||
\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0
|
||||
\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\levelspace0\levelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\levelspace0\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0b;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1080\li1080\lin1080 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\levelspace0\levelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1080\li1080\lin1080 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\levelspace0\levelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1440\li1440\lin1440 }{\listlevel\levelnfc0\levelnfcn0\leveljc0
|
||||
\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1440\li1440\lin1440 }{\listname
|
||||
;}\listid155655221}{\list\listtemplateid466939434\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat6\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0
|
||||
\fi-360\li1080\lin1080 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1800\lin1800 }{\listlevel
|
||||
\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2520\lin2520 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3240\lin3240 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3960\lin3960 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4680\lin4680 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5400\lin5400 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li6120\lin6120 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6840\lin6840 }{\listname ;}\listid207642902}
|
||||
{\list\listtemplateid-868587660\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \cf1\dbch\af0\fbias0
|
||||
\fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2
|
||||
\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0
|
||||
\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid244075828}
|
||||
{\list\listtemplateid-301287646\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \cf1\dbch\af0\fbias0
|
||||
\fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2
|
||||
\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0
|
||||
\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid358317280}
|
||||
{\list\listtemplateid572415416\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \cf0\dbch\af37\fbias0
|
||||
\fi-360\li786\lin786 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1506\lin1506 }{\listlevel\levelnfc2
|
||||
\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2226\lin2226 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2946\lin2946 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0
|
||||
\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3666\lin3666 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4386\lin4386 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5106\lin5106 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5826\lin5826 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6546\lin6546 }{\listname ;}\listid423112302}
|
||||
{\list\listtemplateid-1459612926\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'00.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li1275\lin1275 }
|
||||
{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1995\lin1995 }{\listlevel\levelnfc2\levelnfcn2\leveljc2
|
||||
\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2715\lin2715 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3435\lin3435 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0
|
||||
{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li4155\lin4155 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4875\lin4875 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-360\li5595\lin5595 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li6315\lin6315 }{\listlevel
|
||||
\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li7035\lin7035 }{\listname ;}\listid454718230}
|
||||
{\list\listtemplateid-551514274\listhybrid{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'01-;}{\levelnumbers;}\loch\af1\hich\af1\dbch\af0\fbias0 \fi-360\li1080\lin1080 }{\listlevel
|
||||
\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li1800\lin1800 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li2520\lin2520 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0
|
||||
{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li3240\lin3240 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0
|
||||
\fi-360\li3960\lin3960 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li4680\lin4680 }{\listlevel\levelnfc23\levelnfcn23
|
||||
\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li5400\lin5400 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li6120\lin6120 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}
|
||||
\f10\fbias0 \fi-360\li6840\lin6840 }{\listname ;}\listid474840100}{\list\listtemplateid-1601537400{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}
|
||||
\f3\fs20\fbias0 \fi-360\li720\jclisttab\tx720\lin720 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fs20\fbias0 \levelpicture0\fi-360\li1440
|
||||
\jclisttab\tx1440\lin1440 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li2160\jclisttab\tx2160\lin2160 }
|
||||
{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li2880\jclisttab\tx2880\lin2880 }{\listlevel\levelnfc23\levelnfcn23
|
||||
\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li3600\jclisttab\tx3600\lin3600 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li4320\jclisttab\tx4320\lin4320 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li5040\jclisttab\tx5040\lin5040 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li5760\jclisttab\tx5760\lin5760 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}
|
||||
\f10\fs20\fbias0 \fi-360\li6480\jclisttab\tx6480\lin6480 }{\listname ;}\listid891499942}{\list\listtemplateid-2106560774\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext
|
||||
\'02\'00.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel
|
||||
\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid939029968}{\list\listtemplateid1475657882\listhybrid{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'01-;}{\levelnumbers;}
|
||||
\loch\af1\hich\af1\dbch\af0\fbias0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li2160\lin2160 }{\listlevel\levelnfc23
|
||||
\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li4320\lin4320 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li5040\lin5040 }
|
||||
{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li6480\lin6480 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0
|
||||
{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li7200\lin7200 }{\listname ;}\listid1080055287}{\list\listtemplateid345380616\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0
|
||||
{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1864\lin1864 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2224\lin2224 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-180\li2944\lin2944 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3664\lin3664 }
|
||||
{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li4384\lin4384 }{\listlevel\levelnfc2\levelnfcn2\leveljc2
|
||||
\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li5104\lin5104 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5824\lin5824 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0
|
||||
{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li6544\lin6544 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li7264\lin7264 }{\listname ;}\listid1198470673}{\list\listtemplateid-1488150726\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext
|
||||
\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1080\lin1080 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel
|
||||
\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid1264800667}{\list\listtemplateid1709371634{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li360\lin360 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0
|
||||
\fi-360\li360\lin360 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel
|
||||
\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0
|
||||
\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0\leveljc0
|
||||
\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0b;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1080\li1080\lin1080 }{\listlevel\levelnfc0\levelnfcn0\leveljc0
|
||||
\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1080\li1080\lin1080 }{\listlevel\levelnfc0\levelnfcn0
|
||||
\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1440\li1440\lin1440 }{\listlevel
|
||||
\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0
|
||||
\fi-1440\li1440\lin1440 }{\listname ;}\listid1335182434}{\list\listtemplateid-1861725538\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'00.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel
|
||||
\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0
|
||||
\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative
|
||||
\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }
|
||||
{\listname ;}\listid1556695208}{\list\listtemplateid-301287646\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\cf1\dbch\af0\fbias0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0
|
||||
\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1
|
||||
\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0
|
||||
{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}
|
||||
\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname
|
||||
;}\listid1583906200}{\list\listtemplateid1806592008\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0
|
||||
\fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2
|
||||
\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0
|
||||
\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0
|
||||
\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext
|
||||
\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1
|
||||
\af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid1801338294}
|
||||
{\list\listtemplateid-1056679890\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1429
|
||||
\jclisttab\tx1429\lin1429 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1789\jclisttab\tx1789\lin1789 }
|
||||
{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2509\jclisttab\tx2509\lin2509 }{\listlevel\levelnfc0
|
||||
\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3229\jclisttab\tx3229\lin3229 }{\listlevel\levelnfc4\levelnfcn4\leveljc0
|
||||
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{\title LEC-PRE-00489 ~ EULA for CMSIS Deliverables}{\author Emily Drea}{\operator Joachim Krech}{\creatim\yr2015\mo8\dy27\hr7\min15}{\revtim\yr2015\mo8\dy27\hr7\min15}{\printim\yr2015\mo8\dy18\hr8\min33}{\version2}{\edmins1}{\nofpages5}{\nofwords2395}
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||||
\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 END USER LICENCE AGREEMENT FOR THE }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD (CMSIS) DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
\par THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5861575
|
||||
SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE CMSIS }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5861575 . ARM IS ONLY WILLING TO LICENSE THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5861575 TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING OR OTHERWISE USING OR COPYING THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
YOU INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 OF }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 AND YOU MAY NOT INSTALL, USE OR COPY THE }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 .
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93Deliverables\'94
|
||||
means (i) the CMSIS Deliverables; (ii) CMSIS-DAP Specification; (iii) CMSIS-DAP Firmware; and (iv) RDDI DLL.
|
||||
\par \'93CMSIS-DAP Specification\'94 means any documentation defining the application programming interface, naming and coding conventions of the Cortex Microcontroller Software Interface Standard Debug Access Port (\'93CMSIS-DAP\'94). }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 \hich\f1 Notwithstanding the foregoing, \'93}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 \hich\f1 Specification\'94\loch\f1 shall not include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 (i) the implementation of other published specifications referenced in th}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 Specific\hich\af1\dbch\af37\loch\f1 ation; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 (ii) any enabling technologies that may be necessary to make or use any product or portion}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 s}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 thereof that complies with the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 CMSIS-DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 Specification, but are not themselves expressly set forth in th}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
CMSIS-DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 Specification (e.g. compiler front en\hich\af1\dbch\af37\loch\f1
|
||||
ds, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hardware; applications, operating system or driver software; RISC architecture; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 processor microarchitecture)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid11929640 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP Fi\hich\af1\dbch\af37\loch\f1
|
||||
rmware}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'94
|
||||
means the C programming language source code accompanying this Licence which implements the functionality of the application programming interface as defined in the CMSIS-DAP Specification and any updates, patches and modifications ARM may make ava
|
||||
ilable under the terms of this Licence.
|
||||
\par \'93CMSIS Deliverables\'94 means the following components: (i) CMSIS-CORE; (ii) CMSIS-DRIVER; (iii) CMSIS-DSP; (iv) CMSIS-PACK; (v) CMSIS-RTOS API; and (vi) CMSIS-SVD .
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-CORE
|
||||
\'94 means the specification defining the application programming interface, naming and coding conventions for the Cortex-M processor cores.
|
||||
\par \'94}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 CMSIS-DRIVER}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\insrsid14553496 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 means the specification defining }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 a generic}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 p}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 eripheral }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 d}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 river application programming interface, naming and coding conventions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496 .
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-DSP\'94
|
||||
means the digital signal process (DSP) library specification defining the application programming interface of a DSP library implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15023647 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13240697 \hich\af1\dbch\af37\loch\f1 CMSIS-PACK}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0
|
||||
\insrsid14553496\charrsid13240697 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13240697 \hich\af1\dbch\af37\loch\f1 means the specification defining a software pack file format}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 , verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13240697 \hich\af1\dbch\af37\loch\f1 and the associated XML
|
||||
\hich\af1\dbch\af37\loch\f1 schema file}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496\charrsid13240697 .}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-RTOS API\'94
|
||||
means the real-time operating system (RTOS) specification defining a generic application programming interface layer for a RTOS system}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15023647 .}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-SVD\'94 }{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid9306407 means }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
the specification defining the System View Description (SVD), verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid14553496\charrsid9306407 and associated XML}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid14553496 schema}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid14553496\charrsid9306407 files. }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid9306407
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93Firmware\'94 means firmware that complies with the CMSIS-DAP Specification.
|
||||
\par \'93RDDI DLL\'94 means the reference implementation of a device driver }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6236778 accompanying this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 in object code form and any updates, patch
|
||||
es and modifications ARM may agree to make available under the terms of this Licence and is used with targets containing microprocessors manufactured or simulated under licence from ARM.
|
||||
\par \'93Separate Files\'94 means the components }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid10227990 identified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 in the Schedule.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid3618484 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par \'93Target Connection Product\'94 means a target connection product that complies with the CMSIS-DAP Specification and is used on or with a target containing microprocessors manufactured or simulated under licence from ARM.
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid5577184 \hich\af1\dbch\af37\loch\f1
|
||||
Notwithstanding the foregoing, the Deliverables shall not include: (i) the implementation of other published specifications referenced in the Deliverables; (ii) any enabling technologies that may be necessary to make or use any product or portion thereof
|
||||
\hich\af1\dbch\af37\loch\f1
|
||||
that complies with the Deliverables, but are not themselves expressly set forth in the Deliverables (e.g. compiler front ends, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hard
|
||||
\hich\af1\dbch\af37\loch\f1 w\hich\af1\dbch\af37\loch\f1
|
||||
are; applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs.}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 1. LICENCE GRANTS.
|
||||
\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1317547 licence, to use and copy the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS D}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 for the purpose of: }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar
|
||||
\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 (i) subject to clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 5(i)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 , developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 ; and
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1317547 (ii) distributing and having distributed (directly or through your customers and authorised distributors) the CMSIS-D}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1317547 unmodified, with the products}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 you have developed under }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Clause 1.1 (i) }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 provided you preserve any copyright notices which are included with the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par 1.2 CMSIS-DAP SPECIFICATION
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable licence, to }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid3605578 use and copy the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -DAP }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6386005 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 for the purposes of:
|
||||
\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar\tx567\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (a)\tab }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765
|
||||
developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
, distributing or having distributed a Target Connection Product}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ;}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (b)\tab }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765 developing, having developed, }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 subject to clause 1.5(ii) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765
|
||||
offering to sell, selling, supplying}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765
|
||||
distributing}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 or having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
(directly or through your cus\hich\af1\dbch\af37\loch\f1 tomers and authorised distributors) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Firmware to run on a Target Connection Product; and
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 (c)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \tab subject to clause 1.5(ii), }{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 distributing }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 and }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
(directly or through your customers and authorised distributors) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification unmodified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 with}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 either or both the}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 Target Connection Products and Firmware}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , developed under the licences granted in this Clause 1.2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar
|
||||
\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par 1.3 CMSIS-DAP FIRMWARE
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496
|
||||
\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-trans\hich\af1\dbch\af37\loch\f1 ferable licence, to:
|
||||
|
||||
\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar
|
||||
\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 (a)\tab }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid10356267 \hich\af1\dbch\af37\loch\f1 use, copy}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid2558325
|
||||
\hich\af1\dbch\af37\loch\f1 , and modify the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP Firmware }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
for the purposes of developing and having developed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid8745136 firmware to run on}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 a Target Connection Product; and
|
||||
\par (b)\tab subject to clause 1.5(ii), offer to sell, selling, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5058240 supply}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , supplying, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid8745136 distributing}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 or having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
(directly or through your customers and authorised distributors)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS-DAP Firmware or any modified version created under Clause 1.3 (a) }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid8745136 in}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6192099 object code form only }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 to run on a Target Connection Product. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid9913780 }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar
|
||||
\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 1.4 RDDI DLL
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496
|
||||
\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable licence, to:
|
||||
\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar
|
||||
\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (a)\tab use and copy the RDDI DLL for the purpose }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid13793259 of connecting }{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 a Target Connection Product }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076
|
||||
running CMSIS-DAP compatible firmware }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (either the Firmware or the firmware created pursuant to Clause 1.3) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076 to }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 software debug tools installed on }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076 a host }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 computer running a Windows platform}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076 ; and}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par (b)\tab subject to clause 1.5(ii), offer to sell, selling, supplying, distributing or having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 (directly or
|
||||
\hich\af1\dbch\af37\loch\f1 through your customers and authorised distributors) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 the RDDI DLL in object code form only.
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar
|
||||
\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135
|
||||
\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 1.5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 CONDITIONS ON REDISTRIBUTION}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496
|
||||
\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 (i) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237
|
||||
\hich\af1\dbch\af37\loch\f1 If you distribute (directly or through your customers and authorised distributors) the products you have created pursuant \hich\af1\dbch\af37\loch\f1 to Clause 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (i) you agree: (a) not to use ARM
|
||||
\hich\f1 \rquote \loch\f1 s name, logo or trademarks to market any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1928237 products created under Clause 1.1 (i); }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (b) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 to }{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 pr}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 e}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 serve any copyright notices included in the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 ; and (c) to ensure your customers and aut\hich\af1\dbch\af37\loch\f1 horised distributors comply with this Clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 5(i)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
(ii) If you are authorised and choose to distribute (directly or through your customers and authorised distributors) the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 CMSIS}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Firmware, CMSIS-DAP Firmware or any modified version \hich\af1\dbch\af37\loch\f1
|
||||
thereof, or the RDDI DLL, you agree; (a) to ensure that they are licensed for use with targets containing microprocessors manufactured or simulated under licence from ARM; (b) to preserve any copyright notices which are included with the }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , CMSIS-DAP Firmware}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1
|
||||
, and include valid copyright notices in; (i) any modified version of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS-DAP Firmware}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ; and (ii) the Firmware; (c) not to use ARM\hich\f1 \rquote \loch\f1 s name, logo or trademarks to market -any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , Firmware,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSI\hich\af1\dbch\af37\loch\f1
|
||||
S-DAP Firmware or any modified version therof, the RDDI DLL or the Target Connection Products; and (d) to ensure your customers and authorised distributors comply with this Clause 1.5(ii).
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496
|
||||
\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 2. RESTRICTIONS ON USE OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 DELIVERABLES
|
||||
}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 .
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496
|
||||
\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 PERMITTED USERS: The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 shall be used only by you (either a single individual, or single legal entity) your employees, or by your }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 on-site }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
bona fide sub-contractors for whose acts and omissions you hereby agree to be responsible to ARM}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 for}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 to the same extent as }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 you are for }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 your employees, and provided always that such sub-contractors}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 :}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 (i) are contractually obligated to use the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 only for your benefit}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ;}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 and (i}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 i}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 ) agree to assign all their work product and any rights they create therein in the supply of such work to you.
|
||||
\par COPYRIGHT AND RESERVATION OF RIGHTS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 : The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502
|
||||
are owned by ARM or its licensors and are protected by copyright and other intellectual property laws and international treaties. The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the }{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502
|
||||
or any intellectual property therein. In no event shall the licences granted herein be construed as granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 3}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . SUPPORT.
|
||||
\par ARM is not obligated to support the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables but}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 may do so entirely at ARM's discretion.
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 4}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 NO }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 WARRANT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Y.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
\par YOU AGREE THAT THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 DELIVERABLES ARE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
LICENSED "AS IS", AND THAT ARM EXPRESSLY DISCLA
|
||||
IMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF NON-INFRINGEMENT, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE.}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 THE DELIVERABLES MAY CONTAIN ERRORS. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . LIMITATION OF LIABILITY.
|
||||
\par THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS LICENCE SHALL NOT EXCEED }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 THE GREATER OF (I) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 THE TO
|
||||
TAL OF SUMS PAID BY YOU TO ARM (IF ANY) FOR THIS LICENCE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 AND (II) US$10.00}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN THIS LICENCE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW.
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 6
|
||||
}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid13830602 \hich\af1\dbch\af37\loch\f1 . THIRD PARTY RIGHTS.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13830602
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid13830602 \hich\af1\dbch\af37\loch\f1 The Separate Files are delivered su\hich\af1\dbch\af37\loch\f1 \hich\f1
|
||||
bject to and your use is governed by their own separate licence agreements. This Licence does not apply to such Separate Files and they are not included in the term \'93}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid13830602 \loch\af1\dbch\af37\hich\f1 \'94\loch\f1
|
||||
under this Licence. You agree to comply with all terms and conditions impose\hich\af1\dbch\af37\loch\f1 \hich\f1 d on you in respect of such Separate Files including those identified in the Schedule (\'93\loch\f1 \hich\f1 Third Party Terms\'94\loch\f1
|
||||
).
|
||||
\par \hich\af1\dbch\af37\loch\f1 ARM HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INC\hich\af1\dbch\af37\loch\f1 \hich\f1
|
||||
LUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY \'93\loch\f1 \hich\f1 OTHER CODE\'94\loch\f1
|
||||
), AND THE USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALIT\hich\af1\dbch\af37\loch\f1 Y\hich\af1\dbch\af37\loch\f1 OR FITNESS FOR A PARTICULAR PURPOSE.
|
||||
\par \hich\af1\dbch\af37\loch\f1 NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER
|
||||
\hich\af1\dbch\af37\loch\f1
|
||||
MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENCE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADV
|
||||
\hich\af1\dbch\af37\loch\f1 I\hich\af1\dbch\af37\loch\f1 SED OF THE POSSIBILITY OF SUCH DAMAGES.
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 7}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . U.S. GOVERNMENT END USERS.
|
||||
\par US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this commercial product and accompanying documentation is restricted in accordance with the terms of this Licence.
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 8}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . TERM AND TERMINATION.
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 8.1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
This Licence shall remain in force until terminated }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 in accordance with the terms of Clause 8.2 or Clause 8.3 below}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par 8.2 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 Without prejudice to any of its other rights if you are in breach of
|
||||
any of the terms and conditions of this Licence then ARM may terminate this Licence immediately upon giving written notice to you}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid7630822
|
||||
. You may terminate this Licence at any time. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1
|
||||
8.3 This Licence shall immediately terminate and shall be unavailable to you i\hich\af1\dbch\af37\loch\f1
|
||||
f you or any party affiliated to you asserts any patents against ARM, ARM affiliates, third parties who have a valid licence from ARM for the Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate) pa
|
||||
\hich\af1\dbch\af37\loch\f1 t\hich\af1\dbch\af37\loch\f1 ent is Necessary to implement the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 . In this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724
|
||||
\hich\af1\dbch\af37\loch\f1 (i) "affiliate" means any entity controlling, controlled by or under common control with a party (in fact or in law, via voting securities, management control or otherwise) and "affiliated" s\hich\af1\dbch\af37\loch\f1
|
||||
hall be construed accordingly; (ii) "assert" means to allege infringement in legal or administrative proceedings, or proceedings before any other competent trade, arbitral or international authority; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 \hich\f1 (iii) \'93\loch\f1 \hich\f1 Necessary\'94\loch\f1
|
||||
means with respect to any claims o\hich\af1\dbch\af37\loch\f1 f any patent, those claims which, without the appropriate permission of the patent owner, will be infringed when implementing the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 because no alternative, commercially reasonable, non-infringing way of implementing the }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 is known.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496\charrsid5900444 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 8.4 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid7630822 Upon termination of this Licence,}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 you shall stop }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396
|
||||
using the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396
|
||||
and destroy all copies of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 in your possession. The provisions of clauses 5, 6, 7, 8 and 9 shall survive termination of this Licence.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 9}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . GENERAL.
|
||||
\par This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by you and ARM, this is the only agreement between you and ARM relating to the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636
|
||||
and it may only be modified by written agreement between you and ARM. Except a
|
||||
s expressly agreed in writing, this Licence may not be modified by purchase orders, advertising or other representation by any person. If any clause or sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisi
|
||||
o
|
||||
ns of this Licence shall not be affected thereby. The failure by ARM to enforce any of the provisions of this Licence, unless waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of this Licence
|
||||
in the future.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 This Licence may not be assigned without the prior written consent of ARM.
|
||||
\par }\pard \ltrpar\qc \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \page SCHEDULE
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Separate Files
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 The }{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 package }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 also }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 includes the components}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 contained in the following directories}{\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496
|
||||
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (a)\tab}}\pard \ltrpar
|
||||
\qj \fi-360\li720\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\ls16\adjustright\rin0\lin720\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ./}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778
|
||||
\hich\af1\dbch\af37\loch\f1 DSP_Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396
|
||||
DSP Library sources and examples}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ;
|
||||
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (b)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ./}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMS\hich\af1\dbch\af37\loch\f1 IS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 Include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - Header files;
|
||||
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (c)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ./}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778
|
||||
\hich\af1\dbch\af37\loch\f1 Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1
|
||||
DSP Library build for various toolchains}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ;
|
||||
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (d)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ./}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778
|
||||
\hich\af1\dbch\af37\loch\f1 RTOS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1
|
||||
Header file template for CMSIS-RTOS implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ; and
|
||||
\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (e)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 .}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /Device - T}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid14488502 \hich\af1\dbch\af37\loch\f1 emplate files and implementations for Cortex-M class processors}{
|
||||
\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 .
|
||||
\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par \hich\af1\dbch\af37\loch\f1 All of the above com\hich\af1\dbch\af37\loch\f1 ponents (a\hich\f1 \endash \loch\f1 e) are licensed to you under the terms of the BSD licence, which is incorporated within or alongside the above components.
|
||||
\par }\pard \ltrpar\qj \li284\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin284\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0
|
||||
\f1\fs18\insrsid14553496\charrsid13975144 \hich\af1\dbch\af37\loch\f1 (f)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13975144
|
||||
\hich\af1\dbch\af37\loch\f1 ./CMSIS/Driver \hich\f1 \endash \loch\f1 CMSIS-Driver header files}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13975144 \hich\af1\dbch\af37\loch\f1 (g)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496
|
||||
\hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ./CMSIS/Pack \hich\f1 \endash \loch\f1 Example Device Family Pack}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496\charrsid13975144
|
||||
|
||||
\par }\pard\plain \ltrpar\s32\ql \li0\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \rtlch\fcs1 \af0\afs21\alang1025 \ltrch\fcs0 \f39\fs21\lang2057\langfe1033\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1
|
||||
\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496
|
||||
\par The above components (f \endash g) are licensed to you under the terms of the zlib licence, which is incorporated within or alongside the above components.
|
||||
\par
|
||||
\par
|
||||
\par }\pard\plain \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0
|
||||
\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid2958685 \hich\af1\dbch\af37\loch\f1 ARM contract reference LEC-PRE-00489}{\rtlch\fcs1 \af1\afs18
|
||||
\ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - v4.0}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid2958685
|
||||
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||||
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656e743e0d0a3c78733a656c656d656e74207265663d2270633a456e7469747949643322206d696e4f63637572733d2230223e3c2f78733a656c656d656e743e0d0a3c78733a656c656d656e74207265663d2270633a456e7469747949643422206d696e4f63637572733d2230223e3c2f78733a656c656d656e743e0d0a
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656d656e74206e616d653d22456e746974794964352220747970653d2278733a737472696e67223e3c2f78733a656c656d656e743e0d0a3c78733a656c656d656e74206e616d653d225465726d73223e0d0a3c78733a636f6d706c6578547970653e0d0a3c78733a73657175656e63653e0d0a3c78733a656c656d656e74
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||||
207265663d2270633a5465726d496e666f22206d696e4f63637572733d223022206d61784f63637572733d22756e626f756e646564223e3c2f78733a656c656d656e743e0d0a3c2f78733a73657175656e63653e0d0a3c2f78733a636f6d706c6578547970653e0d0a3c2f78733a656c656d656e743e0d0a3c78733a656c
|
||||
656d656e74206e616d653d225465726d496e666f223e0d0a3c78733a636f6d706c6578547970653e0d0a3c78733a73657175656e63653e0d0a3c78733a656c656d656e74207265663d2270633a5465726d4e616d6522206d696e4f63637572733d2230223e3c2f78733a656c656d656e743e0d0a3c78733a656c656d656e
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||||
74207265663d2270633a5465726d496422206d696e4f63637572733d2230223e3c2f78733a656c656d656e743e0d0a3c2f78733a73657175656e63653e0d0a3c2f78733a636f6d706c6578547970653e0d0a3c2f78733a656c656d656e743e0d0a3c78733a656c656d656e74206e616d653d225465726d4e616d65222074
|
||||
7970653d2278733a737472696e67223e3c2f78733a656c656d656e743e0d0a3c78733a656c656d656e74206e616d653d225465726d49642220747970653d2278733a737472696e67223e3c2f78733a656c656d656e743e0d0a3c2f78733a736368656d613e0d0a3c2f63743a636f6e74656e7454797065536368656d613e
|
||||
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|
||||
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000500072006f00700065007200740069006500
|
||||
7300000000000000000000000000000000000000000000000000000000000000000000000000000000000000000016000200ffffffffffffffffffffffff00000000000000000000000000000000000000000000000000000000000000000000000066000000400400000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffffffffffffffffffffffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006e733a64733d22687474
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||||
703a2f2f736368656d61732e6f70656e786d6c666f726d6174732e6f72672f6f6666696365446f63756d656e742f323030362f637573746f6d586d6c223e3c64733a736368656d61526566733e3c64733a736368656d615265662064733a7572693d22687474703a2f2f736368656d61732e6d6963726f736f66742e636f
|
||||
6d2f6f66666963652f323030362f6d657461646174612f636f6e74656e7454797065222f3e3c64733a736368656d615265662064733a7572693d22687474703a2f2f736368656d61732e6d6963726f736f66742e636f6d2f6f66666963652f323030362f6d657461646174612f70726f706572746965732f6d6574614174
|
||||
7472696275746573222f3e3c64733a736368656d615265662064733a7572693d22687474703a2f2f7777772e77332e6f72672f323030312f584d4c536368656d61222f3e3c64733a736368656d615265662064733a7572693d22687474703a2f2f736368656d61732e6d6963726f736f66742e636f6d2f6f66666963652f
|
||||
323030362f6d657461646174612f70726f70657274696573222f3e3c64733a736368656d615265662064733a7572693d2232656334313736362d353237652d346338342d623438342d646633663235393966643061222f3e3c64733a736368656d615265662064733a7572693d22687474703a2f2f736368656d61732e6d
|
||||
6963726f736f66742e636f6d2f6f66666963652f323030362f646f63756d656e744d616e6167656d656e742f7479706573222f3e3c64733a736368656d615265662064733a7572693d22687474703a2f2f736368656d61732e6d6963726f736f66742e636f6d2f6f66666963652f696e666f706174682f323030372f5061
|
||||
72746e6572436f6e74726f6c73222f3e3c64733a736368656d615265662064733a7572693d22687474703a2f2f736368656d61732e6f70656e786d6c666f726d6174732e6f72672f7061636b6167652f323030362f6d657461646174612f636f72652d70726f70657274696573222f3e3c64733a736368656d6152656620
|
||||
64733a7572693d22687474703a2f2f7075726c2e6f72672f64632f656c656d656e74732f312e312f222f3e3c64733a736368656d615265662064733a7572693d22687474703a2f2f7075726c2e6f72672f64632f7465726d732f222f3e3c64733a736368656d615265662064733a7572693d22687474703a2f2f73636865
|
||||
6d61732e6d6963726f736f66742e636f6d2f696e7465726e616c2f6f6264222f3e3c2f64733a736368656d61526566733e3c2f64733a6461746173746f72654974656d3e00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
0000000000000105000000000000}}
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. October 2015
|
||||
* $Revision: V.1.4.5 a
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
*
|
||||
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
/* extern const q31_t realCoefAQ31[1024]; */
|
||||
/* extern const q31_t realCoefBQ31[1024]; */
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
|
||||
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
|
||||
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
|
||||
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
|
||||
*
|
||||
* $Date: 19. March 2015
|
||||
* $Revision: V.1.4.5
|
||||
*
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
*
|
||||
* Description: This file has constant structs that are initialized for
|
||||
* user convenience. For example, some can be given as
|
||||
* arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* Target Processor: Cortex-M4/Cortex-M3
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* - Neither the name of ARM LIMITED nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
* -------------------------------------------------------------------- */
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
7154
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/arm_math.h
Normal file
7154
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/arm_math.h
Normal file
File diff suppressed because it is too large
Load diff
734
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/cmsis_armcc.h
Normal file
734
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/cmsis_armcc.h
Normal file
|
|
@ -0,0 +1,734 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS Cortex-M Core Function/Instruction Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/* intrinsic void __enable_irq(); */
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
|
||||
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() do {\
|
||||
__schedule_barrier();\
|
||||
__isb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() do {\
|
||||
__schedule_barrier();\
|
||||
__dsb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() do {\
|
||||
__schedule_barrier();\
|
||||
__dmb(0xF);\
|
||||
__schedule_barrier();\
|
||||
} while (0U)
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in integer value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in two unsigned short values.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Reverse byte order in signed short value
|
||||
\details Reverses the byte order in a signed short value with sign extension to integer.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return(result);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x04) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
1800
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/cmsis_armcc_V6.h
Normal file
1800
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/cmsis_armcc_V6.h
Normal file
File diff suppressed because it is too large
Load diff
1373
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/cmsis_gcc.h
Normal file
1373
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load diff
798
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cm0.h
Normal file
798
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cm0.h
Normal file
|
|
@ -0,0 +1,798 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Cortex-M0 Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
914
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cm0plus.h
Normal file
914
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cm0plus.h
Normal file
|
|
@ -0,0 +1,914 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cm0plus.h
|
||||
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_GENERIC
|
||||
#define __CORE_CM0PLUS_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex-M0+
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS CM0+ definitions */
|
||||
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __CM0PLUS_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0PLUS_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0x00U) /*!< Cortex-M Core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0PLUS_H_DEPENDANT
|
||||
#define __CORE_CM0PLUS_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0PLUS_REV
|
||||
#define __CM0PLUS_REV 0x0000U
|
||||
#warning "__CM0PLUS_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __VTOR_PRESENT
|
||||
#define __VTOR_PRESENT 0U
|
||||
#warning "__VTOR_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex-M0+ */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
- Core MPU Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
|
||||
#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
#if (__VTOR_PRESENT == 1U)
|
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||
#else
|
||||
uint32_t RESERVED0;
|
||||
#endif
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
#if (__VTOR_PRESENT == 1U)
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
#endif
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
/* MPU Type Register Definitions */
|
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
|
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register Definitions */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
|
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register Definitions */
|
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register Definitions */
|
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
|
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */
|
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
|
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
|
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
|
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
|
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
|
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
|
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
|
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
|
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
|
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||
|
||||
/*@} end of group CMSIS_MPU */
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0+ header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Cortex-M0+ Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
1763
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cm3.h
Normal file
1763
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load diff
1937
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cm4.h
Normal file
1937
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load diff
2512
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cm7.h
Normal file
2512
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cm7.h
Normal file
File diff suppressed because it is too large
Load diff
87
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cmFunc.h
Normal file
87
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cmFunc.h
Normal file
|
|
@ -0,0 +1,87 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
96
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cmSimd.h
Normal file
96
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_cmSimd.h
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h
|
||||
* @brief CMSIS Cortex-M SIMD Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMSIMD_H
|
||||
#define __CORE_CMSIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CMSIMD_H */
|
||||
926
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_sc000.h
Normal file
926
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_sc000.h
Normal file
|
|
@ -0,0 +1,926 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_sc000.h
|
||||
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_SC000_H_GENERIC
|
||||
#define __CORE_SC000_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup SC000
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS SC000 definitions */
|
||||
#define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_SC (000U) /*!< Cortex secure core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __packed
|
||||
#define __ASM _asm /*!< asm keyword for COSMIC Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_PCS_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TMS470__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "core_cmInstr.h" /* Core Instruction Access */
|
||||
#include "core_cmFunc.h" /* Core Function Access */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_SC000_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_SC000_H_DEPENDANT
|
||||
#define __CORE_SC000_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __SC000_REV
|
||||
#define __SC000_REV 0x0000U
|
||||
#warning "__SC000_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0U
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group SC000 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
- Core MPU Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
__IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED0[1U];
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
uint32_t RESERVED1[154U];
|
||||
__IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2U];
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
|
||||
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Memory Protection Unit (MPU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
/* MPU Type Register Definitions */
|
||||
#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
|
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register Definitions */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
|
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register Definitions */
|
||||
#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register Definitions */
|
||||
#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
|
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||
|
||||
#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register Definitions */
|
||||
#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
|
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||
|
||||
#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
|
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||
|
||||
#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
|
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||
|
||||
#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
|
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||
|
||||
#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
|
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||
|
||||
#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
|
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||
|
||||
#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
|
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||
|
||||
#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
|
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
|
||||
#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||
|
||||
/*@} end of group CMSIS_MPU */
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the SC000 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of SC000 Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
#if (__MPU_PRESENT == 1U)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt
|
||||
\details Enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt
|
||||
\details Disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of an external interrupt.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of an external interrupt.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of an interrupt.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of an interrupt.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) < 0)
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_SC000_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
1745
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_sc300.h
Normal file
1745
Living_SDK/platform/mcu/lpc54102/CMSIS/Include/core_sc300.h
Normal file
File diff suppressed because it is too large
Load diff
Binary file not shown.
Binary file not shown.
28
Living_SDK/platform/mcu/lpc54102/CMSIS/Lib/license.txt
Normal file
28
Living_SDK/platform/mcu/lpc54102/CMSIS/Lib/license.txt
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
All pre-build libraries contained in the folders "ARM" and "GCC"
|
||||
are guided by the following license:
|
||||
|
||||
Copyright (C) 2009-2014 ARM Limited.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
14
Living_SDK/platform/mcu/lpc54102/CMSIS/index.html
Normal file
14
Living_SDK/platform/mcu/lpc54102/CMSIS/index.html
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head>
|
||||
<title>Redirect to the CMSIS main page after 0 seconds</title>
|
||||
<meta http-equiv="refresh" content="0; URL=Documentation/General/html/index.html">
|
||||
<meta name="keywords" content="automatic redirection">
|
||||
</head>
|
||||
|
||||
<body>
|
||||
|
||||
If the automatic redirection is failing, click <a href="Documentation/General/html/index.html">open CMSIS Documentation</a>.
|
||||
|
||||
</body>
|
||||
</html>
|
||||
5558
Living_SDK/platform/mcu/lpc54102/LPC54102_cm0plus.h
Normal file
5558
Living_SDK/platform/mcu/lpc54102/LPC54102_cm0plus.h
Normal file
File diff suppressed because it is too large
Load diff
600
Living_SDK/platform/mcu/lpc54102/LPC54102_cm0plus_features.h
Normal file
600
Living_SDK/platform/mcu/lpc54102/LPC54102_cm0plus_features.h
Normal file
|
|
@ -0,0 +1,600 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Version: rev. 1.0, 2016-05-09
|
||||
** Build: b170512
|
||||
**
|
||||
** Abstract:
|
||||
** Chip specific module features.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2017 NXP
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2016-05-09)
|
||||
** Initial version.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#ifndef _LPC54102_cm0plus_FEATURES_H_
|
||||
#define _LPC54102_cm0plus_FEATURES_H_
|
||||
|
||||
/* SOC module features */
|
||||
|
||||
/* @brief ACMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ACMP_COUNT (0)
|
||||
/* @brief ADC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ADC_COUNT (1)
|
||||
/* @brief ADC12 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ADC12_COUNT (0)
|
||||
/* @brief ADC16 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ADC16_COUNT (0)
|
||||
/* @brief ADC_5HC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0)
|
||||
/* @brief AES availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AES_COUNT (0)
|
||||
/* @brief AFE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AFE_COUNT (0)
|
||||
/* @brief AGC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AGC_COUNT (0)
|
||||
/* @brief AIPS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AIPS_COUNT (0)
|
||||
/* @brief AIPSTZ availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AIPSTZ_COUNT (0)
|
||||
/* @brief ANATOP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ANATOP_COUNT (0)
|
||||
/* @brief AOI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AOI_COUNT (0)
|
||||
/* @brief APBH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_APBH_COUNT (0)
|
||||
/* @brief ASMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ASMC_COUNT (0)
|
||||
/* @brief ASRC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ASRC_COUNT (0)
|
||||
/* @brief ASYNC_SYSCON availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
|
||||
/* @brief ATX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ATX_COUNT (0)
|
||||
/* @brief AXBS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AXBS_COUNT (0)
|
||||
/* @brief BCH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_BCH_COUNT (0)
|
||||
/* @brief BLEDP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_BLEDP_COUNT (0)
|
||||
/* @brief BOD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_BOD_COUNT (0)
|
||||
/* @brief CAAM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CAAM_COUNT (0)
|
||||
/* @brief CADC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CADC_COUNT (0)
|
||||
/* @brief CALIB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CALIB_COUNT (0)
|
||||
/* @brief CAN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPC_CAN_COUNT (0)
|
||||
/* @brief CAU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CAU_COUNT (0)
|
||||
/* @brief CAU3 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CAU3_COUNT (0)
|
||||
/* @brief CCM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CCM_COUNT (0)
|
||||
/* @brief CCM_ANALOG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (0)
|
||||
/* @brief CHRG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CHRG_COUNT (0)
|
||||
/* @brief CMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CMP_COUNT (0)
|
||||
/* @brief CMT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CMT_COUNT (0)
|
||||
/* @brief CNC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CNC_COUNT (0)
|
||||
/* @brief COP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_COP_COUNT (0)
|
||||
/* @brief CRC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CRC_COUNT (1)
|
||||
/* @brief CS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CS_COUNT (0)
|
||||
/* @brief CSI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CSI_COUNT (0)
|
||||
/* @brief CT32B availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CT32B_COUNT (0)
|
||||
/* @brief CTI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CTI_COUNT (0)
|
||||
/* @brief CTIMER availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
|
||||
/* @brief DAC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DAC_COUNT (0)
|
||||
/* @brief DAC32 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DAC32_COUNT (0)
|
||||
/* @brief DCDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DCDC_COUNT (0)
|
||||
/* @brief DCP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DCP_COUNT (0)
|
||||
/* @brief DDR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DDR_COUNT (0)
|
||||
/* @brief DDRC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DDRC_COUNT (0)
|
||||
/* @brief DDRC_MP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0)
|
||||
/* @brief DDR_PHY availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0)
|
||||
/* @brief DMA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DMA_COUNT (1)
|
||||
/* @brief DMAMUX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DMAMUX_COUNT (0)
|
||||
/* @brief DMIC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DMIC_COUNT (0)
|
||||
/* @brief DRY availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DRY_COUNT (0)
|
||||
/* @brief DSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DSPI_COUNT (0)
|
||||
/* @brief ECSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ECSPI_COUNT (0)
|
||||
/* @brief EDMA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EDMA_COUNT (0)
|
||||
/* @brief EEPROM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EEPROM_COUNT (0)
|
||||
/* @brief EIM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EIM_COUNT (0)
|
||||
/* @brief EMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EMC_COUNT (0)
|
||||
/* @brief EMVSIM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
|
||||
/* @brief ENC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ENC_COUNT (0)
|
||||
/* @brief ENET availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPC_ENET_COUNT (0)
|
||||
/* @brief EPDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EPDC_COUNT (0)
|
||||
/* @brief EPIT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EPIT_COUNT (0)
|
||||
/* @brief ESAI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ESAI_COUNT (0)
|
||||
/* @brief EWM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EWM_COUNT (0)
|
||||
/* @brief FB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FB_COUNT (0)
|
||||
/* @brief FGPIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
|
||||
/* @brief FLASH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLASH_COUNT (0)
|
||||
/* @brief FLEXCAN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
|
||||
/* @brief FLEXCOMM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0)
|
||||
/* @brief FLEXIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
|
||||
/* @brief FLEXRAM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXRAM_COUNT (0)
|
||||
/* @brief FLEXSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXSPI_COUNT (0)
|
||||
/* @brief FMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FMC_COUNT (0)
|
||||
/* @brief FSKDT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
|
||||
/* @brief FSP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FSP_COUNT (0)
|
||||
/* @brief FTFA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTFA_COUNT (0)
|
||||
/* @brief FTFE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTFE_COUNT (0)
|
||||
/* @brief FTFL availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTFL_COUNT (0)
|
||||
/* @brief FTM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTM_COUNT (0)
|
||||
/* @brief FTMRA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
|
||||
/* @brief FTMRE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
|
||||
/* @brief FTMRH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
|
||||
/* @brief GINT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GINT_COUNT (2)
|
||||
/* @brief GPC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPC_COUNT (0)
|
||||
/* @brief GPC_PGC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0)
|
||||
/* @brief GPIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPIO_COUNT (1)
|
||||
/* @brief GPMI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPMI_COUNT (0)
|
||||
/* @brief GPT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPT_COUNT (0)
|
||||
/* @brief HSADC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_HSADC_COUNT (0)
|
||||
/* @brief I2C availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_I2C_COUNT (3)
|
||||
/* @brief I2S availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_I2S_COUNT (0)
|
||||
/* @brief ICS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ICS_COUNT (0)
|
||||
/* @brief IEE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IEE_COUNT (0)
|
||||
/* @brief IEER availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IEER_COUNT (0)
|
||||
/* @brief IGPIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IGPIO_COUNT (0)
|
||||
/* @brief II2C availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_II2C_COUNT (0)
|
||||
/* @brief INPUTMUX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
|
||||
/* @brief INTMUX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
|
||||
/* @brief IOCON availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOCON_COUNT (1)
|
||||
/* @brief IOMUXC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_COUNT (0)
|
||||
/* @brief IOMUXC_GPR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (0)
|
||||
/* @brief IOMUXC_LPSR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0)
|
||||
/* @brief IOMUXC_LPSR_GPR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0)
|
||||
/* @brief IOMUXC_SNVS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (0)
|
||||
/* @brief IPWM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IPWM_COUNT (0)
|
||||
/* @brief IRQ availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IRQ_COUNT (0)
|
||||
/* @brief IUART availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IUART_COUNT (0)
|
||||
/* @brief KBI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_KBI_COUNT (0)
|
||||
/* @brief KPP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_KPP_COUNT (0)
|
||||
/* @brief L2CACHEC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0)
|
||||
/* @brief LCD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LCD_COUNT (0)
|
||||
/* @brief LCDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LCDC_COUNT (0)
|
||||
/* @brief LCDIF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LCDIF_COUNT (0)
|
||||
/* @brief LDO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LDO_COUNT (0)
|
||||
/* @brief LLWU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LLWU_COUNT (0)
|
||||
/* @brief LMEM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LMEM_COUNT (0)
|
||||
/* @brief LPADC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPADC_COUNT (0)
|
||||
/* @brief LPCMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPCMP_COUNT (0)
|
||||
/* @brief LPDAC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPDAC_COUNT (0)
|
||||
/* @brief LPI2C availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
|
||||
/* @brief LPIT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPIT_COUNT (0)
|
||||
/* @brief LPSCI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
|
||||
/* @brief LPSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
|
||||
/* @brief LPTMR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPTMR_COUNT (0)
|
||||
/* @brief LPTPM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
|
||||
/* @brief LPUART availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPUART_COUNT (0)
|
||||
/* @brief LTC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LTC_COUNT (0)
|
||||
/* @brief MAILBOX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
|
||||
/* @brief MC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MC_COUNT (0)
|
||||
/* @brief MCG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MCG_COUNT (0)
|
||||
/* @brief MCGLITE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
|
||||
/* @brief MCM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MCM_COUNT (0)
|
||||
/* @brief MIPI_CSI2 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0)
|
||||
/* @brief MIPI_DSI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0)
|
||||
/* @brief MIPI_DSI_HOST availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0)
|
||||
/* @brief MMAU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MMAU_COUNT (0)
|
||||
/* @brief MMCAU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
|
||||
/* @brief MMDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MMDC_COUNT (0)
|
||||
/* @brief MMDVSQ availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
|
||||
/* @brief MPU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MPU_COUNT (0)
|
||||
/* @brief MRT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MRT_COUNT (1)
|
||||
/* @brief MSCAN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
|
||||
/* @brief MSCM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MSCM_COUNT (0)
|
||||
/* @brief MTB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MTB_COUNT (0)
|
||||
/* @brief MTBDWT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
|
||||
/* @brief MU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MU_COUNT (0)
|
||||
/* @brief NFC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_NFC_COUNT (0)
|
||||
/* @brief OCOTP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OCOTP_COUNT (0)
|
||||
/* @brief OPAMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
|
||||
/* @brief OSC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OSC_COUNT (0)
|
||||
/* @brief OSC32 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OSC32_COUNT (0)
|
||||
/* @brief OTFAD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
|
||||
/* @brief PCC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PCC_COUNT (0)
|
||||
/* @brief PCIE_PHY_CMN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0)
|
||||
/* @brief PCIE_PHY_TRSV availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0)
|
||||
/* @brief PDB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PDB_COUNT (0)
|
||||
/* @brief PGA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PGA_COUNT (0)
|
||||
/* @brief PINT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PINT_COUNT (1)
|
||||
/* @brief PIT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PIT_COUNT (0)
|
||||
/* @brief PMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PMC_COUNT (0)
|
||||
/* @brief PMU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PMU_COUNT (0)
|
||||
/* @brief PORT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PORT_COUNT (0)
|
||||
/* @brief PROP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PROP_COUNT (0)
|
||||
/* @brief PWM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PWM_COUNT (0)
|
||||
/* @brief PWT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PWT_COUNT (0)
|
||||
/* @brief PXP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PXP_COUNT (0)
|
||||
/* @brief QDEC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_QDEC_COUNT (0)
|
||||
/* @brief QuadSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
|
||||
/* @brief RCM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RCM_COUNT (0)
|
||||
/* @brief RDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RDC_COUNT (0)
|
||||
/* @brief RDC_SEMAPHORE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0)
|
||||
/* @brief RFSYS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RFSYS_COUNT (0)
|
||||
/* @brief RFVBAT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
|
||||
/* @brief RIT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RIT_COUNT (1)
|
||||
/* @brief RNG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPC_RNG_COUNT (0)
|
||||
/* @brief RNGB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RNGB_COUNT (0)
|
||||
/* @brief ROM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ROM_COUNT (0)
|
||||
/* @brief ROMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ROMC_COUNT (0)
|
||||
/* @brief RSIM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RSIM_COUNT (0)
|
||||
/* @brief RTC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RTC_COUNT (1)
|
||||
/* @brief SCG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SCG_COUNT (0)
|
||||
/* @brief SCI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SCI_COUNT (0)
|
||||
/* @brief SCT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SCT_COUNT (1)
|
||||
/* @brief SDHC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDHC_COUNT (0)
|
||||
/* @brief SDIF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDIF_COUNT (0)
|
||||
/* @brief SDIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDIO_COUNT (0)
|
||||
/* @brief SDMA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDMA_COUNT (0)
|
||||
/* @brief SDMAARM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDMAARM_COUNT (0)
|
||||
/* @brief SDMABP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDMABP_COUNT (0)
|
||||
/* @brief SDMACORE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDMACORE_COUNT (0)
|
||||
/* @brief SDMCORE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDMCORE_COUNT (0)
|
||||
/* @brief SDRAM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
|
||||
/* @brief SEMA4 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SEMA4_COUNT (0)
|
||||
/* @brief SEMA42 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
|
||||
/* @brief SHA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SHA_COUNT (0)
|
||||
/* @brief SIM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SIM_COUNT (0)
|
||||
/* @brief SIMDGO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SIMDGO_COUNT (0)
|
||||
/* @brief SJC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SJC_COUNT (0)
|
||||
/* @brief SLCD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SLCD_COUNT (0)
|
||||
/* @brief SMARTCARD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0)
|
||||
/* @brief SMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SMC_COUNT (0)
|
||||
/* @brief SNVS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SNVS_COUNT (0)
|
||||
/* @brief SPBA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPBA_COUNT (0)
|
||||
/* @brief SPDIF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPDIF_COUNT (0)
|
||||
/* @brief SPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPI_COUNT (2)
|
||||
/* @brief SPIFI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPIFI_COUNT (0)
|
||||
/* @brief SPM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPM_COUNT (0)
|
||||
/* @brief SRC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SRC_COUNT (0)
|
||||
/* @brief SYSCON availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
|
||||
/* @brief TEMPMON availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TEMPMON_COUNT (0)
|
||||
/* @brief TMR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TMR_COUNT (0)
|
||||
/* @brief TPM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TPM_COUNT (0)
|
||||
/* @brief TRGMUX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
|
||||
/* @brief TRIAMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
|
||||
/* @brief TRNG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TRNG_COUNT (0)
|
||||
/* @brief TSC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TSC_COUNT (0)
|
||||
/* @brief TSI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TSI_COUNT (0)
|
||||
/* @brief TSTMR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
|
||||
/* @brief UART availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_UART_COUNT (0)
|
||||
/* @brief USART availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USART_COUNT (4)
|
||||
/* @brief USB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USB_COUNT (0)
|
||||
/* @brief USBHS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBHS_COUNT (0)
|
||||
/* @brief USBDCD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
|
||||
/* @brief USBFSH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBFSH_COUNT (0)
|
||||
/* @brief USBHSD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBHSD_COUNT (0)
|
||||
/* @brief USBHSDCD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
|
||||
/* @brief USBHSH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBHSH_COUNT (0)
|
||||
/* @brief USBNC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBNC_COUNT (0)
|
||||
/* @brief USBPHY availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
|
||||
/* @brief USB_HSIC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0)
|
||||
/* @brief USB_OTG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USB_OTG_COUNT (0)
|
||||
/* @brief USDHC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USDHC_COUNT (0)
|
||||
/* @brief UTICK availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_UTICK_COUNT (1)
|
||||
/* @brief VIU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_VIU_COUNT (0)
|
||||
/* @brief VREF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_VREF_COUNT (0)
|
||||
/* @brief VFIFO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_VFIFO_COUNT (1)
|
||||
/* @brief WDOG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_WDOG_COUNT (0)
|
||||
/* @brief WKPU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_WKPU_COUNT (0)
|
||||
/* @brief WWDT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
|
||||
/* @brief XBAR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XBAR_COUNT (0)
|
||||
/* @brief XBARA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XBARA_COUNT (0)
|
||||
/* @brief XBARB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XBARB_COUNT (0)
|
||||
/* @brief XCVR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XCVR_COUNT (0)
|
||||
/* @brief XRDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XRDC_COUNT (0)
|
||||
/* @brief XTALOSC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XTALOSC_COUNT (0)
|
||||
/* @brief XTALOSC24M availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (0)
|
||||
/* @brief ZLL availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ZLL_COUNT (0)
|
||||
|
||||
/* ADC module features */
|
||||
|
||||
/* @brief Has input select (register INSEL). */
|
||||
#define FSL_FEATURE_ADC_HAS_NO_INSEL (1)
|
||||
|
||||
/* DMA module features */
|
||||
|
||||
/* @brief Number of channels */
|
||||
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (22)
|
||||
|
||||
/* PINT module features */
|
||||
|
||||
/* @brief Number of connected outputs */
|
||||
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (4)
|
||||
|
||||
/* RTC module features */
|
||||
|
||||
/* @brief Has CTRL:RTC_OSC_PD Bit */
|
||||
#define FSL_FEATURE_RTC_HAS_NO_OSC_PD (1)
|
||||
|
||||
/* SCT module features */
|
||||
|
||||
/* @brief Number of events */
|
||||
#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (13)
|
||||
/* @brief Number of states */
|
||||
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (13)
|
||||
/* @brief Number of match capture */
|
||||
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (13)
|
||||
|
||||
/* SYSCON module features */
|
||||
|
||||
#if defined(CPU_LPC54102J256BD64_cm0plus) || defined(CPU_LPC54102J256UK49_cm0plus)
|
||||
/* @brief Pointer to ROM IAP entry functions */
|
||||
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
|
||||
/* @brief Flash page size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
|
||||
/* @brief Flash sector size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
|
||||
/* @brief Flash size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144)
|
||||
#elif defined(CPU_LPC54102J512BD64_cm0plus) || defined(CPU_LPC54102J512UK49_cm0plus)
|
||||
/* @brief Pointer to ROM IAP entry functions */
|
||||
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
|
||||
/* @brief Flash page size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
|
||||
/* @brief Flash sector size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
|
||||
/* @brief Flash size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
|
||||
#endif /* defined(CPU_LPC54102J256BD64) || defined(CPU_LPC54102J256UK49) */
|
||||
|
||||
#endif /* _LPC54102_cm0plus_FEATURES_H_ */
|
||||
|
||||
5572
Living_SDK/platform/mcu/lpc54102/LPC54102_cm4.h
Normal file
5572
Living_SDK/platform/mcu/lpc54102/LPC54102_cm4.h
Normal file
File diff suppressed because it is too large
Load diff
600
Living_SDK/platform/mcu/lpc54102/LPC54102_cm4_features.h
Normal file
600
Living_SDK/platform/mcu/lpc54102/LPC54102_cm4_features.h
Normal file
|
|
@ -0,0 +1,600 @@
|
|||
/*
|
||||
** ###################################################################
|
||||
** Version: rev. 1.0, 2016-05-09
|
||||
** Build: b170512
|
||||
**
|
||||
** Abstract:
|
||||
** Chip specific module features.
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2017 NXP
|
||||
** Redistribution and use in source and binary forms, with or without modification,
|
||||
** are permitted provided that the following conditions are met:
|
||||
**
|
||||
** o Redistributions of source code must retain the above copyright notice, this list
|
||||
** of conditions and the following disclaimer.
|
||||
**
|
||||
** o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
** list of conditions and the following disclaimer in the documentation and/or
|
||||
** other materials provided with the distribution.
|
||||
**
|
||||
** o Neither the name of the copyright holder nor the names of its
|
||||
** contributors may be used to endorse or promote products derived from this
|
||||
** software without specific prior written permission.
|
||||
**
|
||||
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** Revisions:
|
||||
** - rev. 1.0 (2016-05-09)
|
||||
** Initial version.
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
#ifndef _LPC54102_cm4_FEATURES_H_
|
||||
#define _LPC54102_cm4_FEATURES_H_
|
||||
|
||||
/* SOC module features */
|
||||
|
||||
/* @brief ACMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ACMP_COUNT (0)
|
||||
/* @brief ADC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ADC_COUNT (1)
|
||||
/* @brief ADC12 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ADC12_COUNT (0)
|
||||
/* @brief ADC16 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ADC16_COUNT (0)
|
||||
/* @brief ADC_5HC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0)
|
||||
/* @brief AES availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AES_COUNT (0)
|
||||
/* @brief AFE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AFE_COUNT (0)
|
||||
/* @brief AGC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AGC_COUNT (0)
|
||||
/* @brief AIPS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AIPS_COUNT (0)
|
||||
/* @brief AIPSTZ availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AIPSTZ_COUNT (0)
|
||||
/* @brief ANATOP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ANATOP_COUNT (0)
|
||||
/* @brief AOI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AOI_COUNT (0)
|
||||
/* @brief APBH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_APBH_COUNT (0)
|
||||
/* @brief ASMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ASMC_COUNT (0)
|
||||
/* @brief ASRC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ASRC_COUNT (0)
|
||||
/* @brief ASYNC_SYSCON availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
|
||||
/* @brief ATX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ATX_COUNT (0)
|
||||
/* @brief AXBS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_AXBS_COUNT (0)
|
||||
/* @brief BCH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_BCH_COUNT (0)
|
||||
/* @brief BLEDP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_BLEDP_COUNT (0)
|
||||
/* @brief BOD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_BOD_COUNT (0)
|
||||
/* @brief CAAM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CAAM_COUNT (0)
|
||||
/* @brief CADC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CADC_COUNT (0)
|
||||
/* @brief CALIB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CALIB_COUNT (0)
|
||||
/* @brief CAN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPC_CAN_COUNT (0)
|
||||
/* @brief CAU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CAU_COUNT (0)
|
||||
/* @brief CAU3 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CAU3_COUNT (0)
|
||||
/* @brief CCM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CCM_COUNT (0)
|
||||
/* @brief CCM_ANALOG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (0)
|
||||
/* @brief CHRG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CHRG_COUNT (0)
|
||||
/* @brief CMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CMP_COUNT (0)
|
||||
/* @brief CMT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CMT_COUNT (0)
|
||||
/* @brief CNC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CNC_COUNT (0)
|
||||
/* @brief COP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_COP_COUNT (0)
|
||||
/* @brief CRC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CRC_COUNT (1)
|
||||
/* @brief CS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CS_COUNT (0)
|
||||
/* @brief CSI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CSI_COUNT (0)
|
||||
/* @brief CT32B availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CT32B_COUNT (0)
|
||||
/* @brief CTI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CTI_COUNT (0)
|
||||
/* @brief CTIMER availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
|
||||
/* @brief DAC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DAC_COUNT (0)
|
||||
/* @brief DAC32 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DAC32_COUNT (0)
|
||||
/* @brief DCDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DCDC_COUNT (0)
|
||||
/* @brief DCP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DCP_COUNT (0)
|
||||
/* @brief DDR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DDR_COUNT (0)
|
||||
/* @brief DDRC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DDRC_COUNT (0)
|
||||
/* @brief DDRC_MP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0)
|
||||
/* @brief DDR_PHY availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0)
|
||||
/* @brief DMA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DMA_COUNT (1)
|
||||
/* @brief DMAMUX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DMAMUX_COUNT (0)
|
||||
/* @brief DMIC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DMIC_COUNT (0)
|
||||
/* @brief DRY availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DRY_COUNT (0)
|
||||
/* @brief DSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_DSPI_COUNT (0)
|
||||
/* @brief ECSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ECSPI_COUNT (0)
|
||||
/* @brief EDMA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EDMA_COUNT (0)
|
||||
/* @brief EEPROM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EEPROM_COUNT (0)
|
||||
/* @brief EIM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EIM_COUNT (0)
|
||||
/* @brief EMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EMC_COUNT (0)
|
||||
/* @brief EMVSIM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
|
||||
/* @brief ENC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ENC_COUNT (0)
|
||||
/* @brief ENET availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPC_ENET_COUNT (0)
|
||||
/* @brief EPDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EPDC_COUNT (0)
|
||||
/* @brief EPIT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EPIT_COUNT (0)
|
||||
/* @brief ESAI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ESAI_COUNT (0)
|
||||
/* @brief EWM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_EWM_COUNT (0)
|
||||
/* @brief FB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FB_COUNT (0)
|
||||
/* @brief FGPIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
|
||||
/* @brief FLASH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLASH_COUNT (0)
|
||||
/* @brief FLEXCAN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0)
|
||||
/* @brief FLEXCOMM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0)
|
||||
/* @brief FLEXIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXIO_COUNT (0)
|
||||
/* @brief FLEXRAM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXRAM_COUNT (0)
|
||||
/* @brief FLEXSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FLEXSPI_COUNT (0)
|
||||
/* @brief FMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FMC_COUNT (0)
|
||||
/* @brief FSKDT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
|
||||
/* @brief FSP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FSP_COUNT (0)
|
||||
/* @brief FTFA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTFA_COUNT (0)
|
||||
/* @brief FTFE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTFE_COUNT (0)
|
||||
/* @brief FTFL availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTFL_COUNT (0)
|
||||
/* @brief FTM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTM_COUNT (0)
|
||||
/* @brief FTMRA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
|
||||
/* @brief FTMRE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
|
||||
/* @brief FTMRH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
|
||||
/* @brief GINT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GINT_COUNT (2)
|
||||
/* @brief GPC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPC_COUNT (0)
|
||||
/* @brief GPC_PGC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0)
|
||||
/* @brief GPIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPIO_COUNT (1)
|
||||
/* @brief GPMI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPMI_COUNT (0)
|
||||
/* @brief GPT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_GPT_COUNT (0)
|
||||
/* @brief HSADC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_HSADC_COUNT (0)
|
||||
/* @brief I2C availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_I2C_COUNT (3)
|
||||
/* @brief I2S availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_I2S_COUNT (0)
|
||||
/* @brief ICS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ICS_COUNT (0)
|
||||
/* @brief IEE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IEE_COUNT (0)
|
||||
/* @brief IEER availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IEER_COUNT (0)
|
||||
/* @brief IGPIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IGPIO_COUNT (0)
|
||||
/* @brief II2C availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_II2C_COUNT (0)
|
||||
/* @brief INPUTMUX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
|
||||
/* @brief INTMUX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
|
||||
/* @brief IOCON availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOCON_COUNT (1)
|
||||
/* @brief IOMUXC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_COUNT (0)
|
||||
/* @brief IOMUXC_GPR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (0)
|
||||
/* @brief IOMUXC_LPSR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0)
|
||||
/* @brief IOMUXC_LPSR_GPR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0)
|
||||
/* @brief IOMUXC_SNVS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (0)
|
||||
/* @brief IPWM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IPWM_COUNT (0)
|
||||
/* @brief IRQ availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IRQ_COUNT (0)
|
||||
/* @brief IUART availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_IUART_COUNT (0)
|
||||
/* @brief KBI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_KBI_COUNT (0)
|
||||
/* @brief KPP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_KPP_COUNT (0)
|
||||
/* @brief L2CACHEC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0)
|
||||
/* @brief LCD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LCD_COUNT (0)
|
||||
/* @brief LCDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LCDC_COUNT (0)
|
||||
/* @brief LCDIF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LCDIF_COUNT (0)
|
||||
/* @brief LDO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LDO_COUNT (0)
|
||||
/* @brief LLWU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LLWU_COUNT (0)
|
||||
/* @brief LMEM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LMEM_COUNT (0)
|
||||
/* @brief LPADC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPADC_COUNT (0)
|
||||
/* @brief LPCMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPCMP_COUNT (0)
|
||||
/* @brief LPDAC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPDAC_COUNT (0)
|
||||
/* @brief LPI2C availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPI2C_COUNT (0)
|
||||
/* @brief LPIT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPIT_COUNT (0)
|
||||
/* @brief LPSCI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
|
||||
/* @brief LPSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPSPI_COUNT (0)
|
||||
/* @brief LPTMR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPTMR_COUNT (0)
|
||||
/* @brief LPTPM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
|
||||
/* @brief LPUART availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPUART_COUNT (0)
|
||||
/* @brief LTC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LTC_COUNT (0)
|
||||
/* @brief MAILBOX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
|
||||
/* @brief MC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MC_COUNT (0)
|
||||
/* @brief MCG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MCG_COUNT (0)
|
||||
/* @brief MCGLITE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
|
||||
/* @brief MCM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MCM_COUNT (0)
|
||||
/* @brief MIPI_CSI2 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0)
|
||||
/* @brief MIPI_DSI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0)
|
||||
/* @brief MIPI_DSI_HOST availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0)
|
||||
/* @brief MMAU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MMAU_COUNT (0)
|
||||
/* @brief MMCAU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
|
||||
/* @brief MMDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MMDC_COUNT (0)
|
||||
/* @brief MMDVSQ availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
|
||||
/* @brief MPU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MPU_COUNT (0)
|
||||
/* @brief MRT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MRT_COUNT (1)
|
||||
/* @brief MSCAN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
|
||||
/* @brief MSCM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MSCM_COUNT (0)
|
||||
/* @brief MTB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MTB_COUNT (0)
|
||||
/* @brief MTBDWT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
|
||||
/* @brief MU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MU_COUNT (0)
|
||||
/* @brief NFC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_NFC_COUNT (0)
|
||||
/* @brief OCOTP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OCOTP_COUNT (0)
|
||||
/* @brief OPAMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
|
||||
/* @brief OSC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OSC_COUNT (0)
|
||||
/* @brief OSC32 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OSC32_COUNT (0)
|
||||
/* @brief OTFAD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
|
||||
/* @brief PCC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PCC_COUNT (0)
|
||||
/* @brief PCIE_PHY_CMN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0)
|
||||
/* @brief PCIE_PHY_TRSV availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0)
|
||||
/* @brief PDB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PDB_COUNT (0)
|
||||
/* @brief PGA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PGA_COUNT (0)
|
||||
/* @brief PINT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PINT_COUNT (1)
|
||||
/* @brief PIT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PIT_COUNT (0)
|
||||
/* @brief PMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PMC_COUNT (0)
|
||||
/* @brief PMU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PMU_COUNT (0)
|
||||
/* @brief PORT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PORT_COUNT (0)
|
||||
/* @brief PROP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PROP_COUNT (0)
|
||||
/* @brief PWM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PWM_COUNT (0)
|
||||
/* @brief PWT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PWT_COUNT (0)
|
||||
/* @brief PXP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_PXP_COUNT (0)
|
||||
/* @brief QDEC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_QDEC_COUNT (0)
|
||||
/* @brief QuadSPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
|
||||
/* @brief RCM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RCM_COUNT (0)
|
||||
/* @brief RDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RDC_COUNT (0)
|
||||
/* @brief RDC_SEMAPHORE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0)
|
||||
/* @brief RFSYS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RFSYS_COUNT (0)
|
||||
/* @brief RFVBAT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
|
||||
/* @brief RIT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RIT_COUNT (1)
|
||||
/* @brief RNG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_LPC_RNG_COUNT (0)
|
||||
/* @brief RNGB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RNGB_COUNT (0)
|
||||
/* @brief ROM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ROM_COUNT (0)
|
||||
/* @brief ROMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ROMC_COUNT (0)
|
||||
/* @brief RSIM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RSIM_COUNT (0)
|
||||
/* @brief RTC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_RTC_COUNT (1)
|
||||
/* @brief SCG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SCG_COUNT (0)
|
||||
/* @brief SCI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SCI_COUNT (0)
|
||||
/* @brief SCT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SCT_COUNT (1)
|
||||
/* @brief SDHC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDHC_COUNT (0)
|
||||
/* @brief SDIF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDIF_COUNT (0)
|
||||
/* @brief SDIO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDIO_COUNT (0)
|
||||
/* @brief SDMA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDMA_COUNT (0)
|
||||
/* @brief SDMAARM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDMAARM_COUNT (0)
|
||||
/* @brief SDMABP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDMABP_COUNT (0)
|
||||
/* @brief SDMACORE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDMACORE_COUNT (0)
|
||||
/* @brief SDMCORE availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDMCORE_COUNT (0)
|
||||
/* @brief SDRAM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
|
||||
/* @brief SEMA4 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SEMA4_COUNT (0)
|
||||
/* @brief SEMA42 availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
|
||||
/* @brief SHA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SHA_COUNT (0)
|
||||
/* @brief SIM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SIM_COUNT (0)
|
||||
/* @brief SIMDGO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SIMDGO_COUNT (0)
|
||||
/* @brief SJC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SJC_COUNT (0)
|
||||
/* @brief SLCD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SLCD_COUNT (0)
|
||||
/* @brief SMARTCARD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0)
|
||||
/* @brief SMC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SMC_COUNT (0)
|
||||
/* @brief SNVS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SNVS_COUNT (0)
|
||||
/* @brief SPBA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPBA_COUNT (0)
|
||||
/* @brief SPDIF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPDIF_COUNT (0)
|
||||
/* @brief SPI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPI_COUNT (2)
|
||||
/* @brief SPIFI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPIFI_COUNT (0)
|
||||
/* @brief SPM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SPM_COUNT (0)
|
||||
/* @brief SRC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SRC_COUNT (0)
|
||||
/* @brief SYSCON availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
|
||||
/* @brief TEMPMON availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TEMPMON_COUNT (0)
|
||||
/* @brief TMR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TMR_COUNT (0)
|
||||
/* @brief TPM availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TPM_COUNT (0)
|
||||
/* @brief TRGMUX availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
|
||||
/* @brief TRIAMP availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
|
||||
/* @brief TRNG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TRNG_COUNT (0)
|
||||
/* @brief TSC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TSC_COUNT (0)
|
||||
/* @brief TSI availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TSI_COUNT (0)
|
||||
/* @brief TSTMR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
|
||||
/* @brief UART availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_UART_COUNT (0)
|
||||
/* @brief USART availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USART_COUNT (4)
|
||||
/* @brief USB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USB_COUNT (0)
|
||||
/* @brief USBHS availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBHS_COUNT (0)
|
||||
/* @brief USBDCD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
|
||||
/* @brief USBFSH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBFSH_COUNT (0)
|
||||
/* @brief USBHSD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBHSD_COUNT (0)
|
||||
/* @brief USBHSDCD availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
|
||||
/* @brief USBHSH availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBHSH_COUNT (0)
|
||||
/* @brief USBNC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBNC_COUNT (0)
|
||||
/* @brief USBPHY availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USBPHY_COUNT (0)
|
||||
/* @brief USB_HSIC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0)
|
||||
/* @brief USB_OTG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USB_OTG_COUNT (0)
|
||||
/* @brief USDHC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_USDHC_COUNT (0)
|
||||
/* @brief UTICK availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_UTICK_COUNT (1)
|
||||
/* @brief VIU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_VIU_COUNT (0)
|
||||
/* @brief VREF availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_VREF_COUNT (0)
|
||||
/* @brief VFIFO availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_VFIFO_COUNT (1)
|
||||
/* @brief WDOG availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_WDOG_COUNT (0)
|
||||
/* @brief WKPU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_WKPU_COUNT (0)
|
||||
/* @brief WWDT availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
|
||||
/* @brief XBAR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XBAR_COUNT (0)
|
||||
/* @brief XBARA availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XBARA_COUNT (0)
|
||||
/* @brief XBARB availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XBARB_COUNT (0)
|
||||
/* @brief XCVR availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XCVR_COUNT (0)
|
||||
/* @brief XRDC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XRDC_COUNT (0)
|
||||
/* @brief XTALOSC availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XTALOSC_COUNT (0)
|
||||
/* @brief XTALOSC24M availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (0)
|
||||
/* @brief ZLL availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_ZLL_COUNT (0)
|
||||
|
||||
/* ADC module features */
|
||||
|
||||
/* @brief Has input select (register INSEL). */
|
||||
#define FSL_FEATURE_ADC_HAS_NO_INSEL (1)
|
||||
|
||||
/* DMA module features */
|
||||
|
||||
/* @brief Number of channels */
|
||||
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (22)
|
||||
|
||||
/* PINT module features */
|
||||
|
||||
/* @brief Number of connected outputs */
|
||||
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
|
||||
|
||||
/* RTC module features */
|
||||
|
||||
/* @brief Has CTRL:RTC_OSC_PD Bit */
|
||||
#define FSL_FEATURE_RTC_HAS_NO_OSC_PD (1)
|
||||
|
||||
/* SCT module features */
|
||||
|
||||
/* @brief Number of events */
|
||||
#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (13)
|
||||
/* @brief Number of states */
|
||||
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (13)
|
||||
/* @brief Number of match capture */
|
||||
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (13)
|
||||
|
||||
/* SYSCON module features */
|
||||
|
||||
#if defined(CPU_LPC54102J256BD64_cm4) || defined(CPU_LPC54102J256UK49_cm4)
|
||||
/* @brief Pointer to ROM IAP entry functions */
|
||||
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
|
||||
/* @brief Flash page size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
|
||||
/* @brief Flash sector size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
|
||||
/* @brief Flash size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (262144)
|
||||
#elif defined(CPU_LPC54102J512BD64_cm4) || defined(CPU_LPC54102J512UK49_cm4)
|
||||
/* @brief Pointer to ROM IAP entry functions */
|
||||
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
|
||||
/* @brief Flash page size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256)
|
||||
/* @brief Flash sector size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
|
||||
/* @brief Flash size in bytes */
|
||||
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288)
|
||||
#endif /* defined(CPU_LPC54102J256BD64) || defined(CPU_LPC54102J256UK49) */
|
||||
|
||||
#endif /* _LPC54102_cm4_FEATURES_H_ */
|
||||
|
||||
218
Living_SDK/platform/mcu/lpc54102/RTE_Device.h
Normal file
218
Living_SDK/platform/mcu/lpc54102/RTE_Device.h
Normal file
|
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __RTE_DEVICE_H
|
||||
#define __RTE_DEVICE_H
|
||||
|
||||
/* UART Select, UART0-UART7. */
|
||||
/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins
|
||||
in the application for enabling according instance. */
|
||||
#define RTE_USART0 0
|
||||
#define RTE_USART0_DMA_EN 0
|
||||
#define RTE_USART1 0
|
||||
#define RTE_USART1_DMA_EN 0
|
||||
#define RTE_USART2 0
|
||||
#define RTE_USART2_DMA_EN 0
|
||||
#define RTE_USART3 0
|
||||
#define RTE_USART3_DMA_EN 0
|
||||
#define RTE_USART4 0
|
||||
#define RTE_USART4_DMA_EN 0
|
||||
#define RTE_USART5 0
|
||||
#define RTE_USART5_DMA_EN 0
|
||||
#define RTE_USART6 0
|
||||
#define RTE_USART6_DMA_EN 0
|
||||
#define RTE_USART7 0
|
||||
#define RTE_USART7_DMA_EN 0
|
||||
|
||||
/* USART configuration. */
|
||||
#define USART_RX_BUFFER_LEN 64
|
||||
#define USART0_RX_BUFFER_ENABLE 0
|
||||
#define USART1_RX_BUFFER_ENABLE 0
|
||||
#define USART2_RX_BUFFER_ENABLE 0
|
||||
#define USART3_RX_BUFFER_ENABLE 0
|
||||
#define USART4_RX_BUFFER_ENABLE 0
|
||||
#define USART5_RX_BUFFER_ENABLE 0
|
||||
#define USART6_RX_BUFFER_ENABLE 0
|
||||
#define USART7_RX_BUFFER_ENABLE 0
|
||||
|
||||
#define RTE_USART0_DMA_TX_CH 1
|
||||
#define RTE_USART0_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART0_DMA_RX_CH 0
|
||||
#define RTE_USART0_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART1_DMA_TX_CH 3
|
||||
#define RTE_USART1_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART1_DMA_RX_CH 2
|
||||
#define RTE_USART1_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART2_DMA_TX_CH 5
|
||||
#define RTE_USART2_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART2_DMA_RX_CH 4
|
||||
#define RTE_USART2_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART3_DMA_TX_CH 7
|
||||
#define RTE_USART3_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART3_DMA_RX_CH 6
|
||||
#define RTE_USART3_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART4_DMA_TX_CH 9
|
||||
#define RTE_USART4_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART4_DMA_RX_CH 8
|
||||
#define RTE_USART4_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART5_DMA_TX_CH 11
|
||||
#define RTE_USART5_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART5_DMA_RX_CH 10
|
||||
#define RTE_USART5_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART6_DMA_TX_CH 13
|
||||
#define RTE_USART6_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART6_DMA_RX_CH 12
|
||||
#define RTE_USART6_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART7_DMA_TX_CH 15
|
||||
#define RTE_USART7_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART7_DMA_RX_CH 14
|
||||
#define RTE_USART7_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
/* I2C Select, I2C0 -I2C7*/
|
||||
/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins
|
||||
in the application for enabling according instance. */
|
||||
#define RTE_I2C0 0
|
||||
#define RTE_I2C0_DMA_EN 0
|
||||
#define RTE_I2C1 0
|
||||
#define RTE_I2C1_DMA_EN 0
|
||||
#define RTE_I2C2 0
|
||||
#define RTE_I2C2_DMA_EN 0
|
||||
#define RTE_I2C3 0
|
||||
#define RTE_I2C3_DMA_EN 0
|
||||
#define RTE_I2C4 0
|
||||
#define RTE_I2C4_DMA_EN 0
|
||||
#define RTE_I2C5 0
|
||||
#define RTE_I2C5_DMA_EN 0
|
||||
#define RTE_I2C6 0
|
||||
#define RTE_I2C6_DMA_EN 0
|
||||
#define RTE_I2C7 0
|
||||
#define RTE_I2C7_DMA_EN 0
|
||||
|
||||
/*I2C configuration*/
|
||||
#define RTE_I2C0_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C0_Master_DMA_CH 1
|
||||
|
||||
#define RTE_I2C1_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C1_Master_DMA_CH 3
|
||||
|
||||
#define RTE_I2C2_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C2_Master_DMA_CH 5
|
||||
|
||||
#define RTE_I2C3_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C3_Master_DMA_CH 7
|
||||
|
||||
#define RTE_I2C4_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C4_Master_DMA_CH 9
|
||||
|
||||
#define RTE_I2C5_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C5_Master_DMA_CH 11
|
||||
|
||||
#define RTE_I2C6_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C6_Master_DMA_CH 13
|
||||
|
||||
#define RTE_I2C7_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C7_Master_DMA_CH 15
|
||||
|
||||
/* SPI select, SPI0 - SPI7.*/
|
||||
/* User needs to provide the implementation for XXX_GetFreq/XXX_InitPins/XXX_DeinitPins
|
||||
in the application for enabling according instance. */
|
||||
#define RTE_SPI0 0
|
||||
#define RTE_SPI0_DMA_EN 0
|
||||
#define RTE_SPI1 0
|
||||
#define RTE_SPI1_DMA_EN 0
|
||||
#define RTE_SPI2 0
|
||||
#define RTE_SPI2_DMA_EN 0
|
||||
#define RTE_SPI3 0
|
||||
#define RTE_SPI3_DMA_EN 0
|
||||
#define RTE_SPI4 0
|
||||
#define RTE_SPI4_DMA_EN 0
|
||||
#define RTE_SPI5 0
|
||||
#define RTE_SPI5_DMA_EN 0
|
||||
#define RTE_SPI6 0
|
||||
#define RTE_SPI6_DMA_EN 0
|
||||
#define RTE_SPI7 0
|
||||
#define RTE_SPI7_DMA_EN 0
|
||||
|
||||
/* SPI configuration. */
|
||||
#define RTE_SPI0_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI0_DMA_TX_CH 1
|
||||
#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI0_DMA_RX_CH 0
|
||||
#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI1_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI1_DMA_TX_CH 3
|
||||
#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI1_DMA_RX_CH 2
|
||||
#define RTE_SPI1_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI2_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI2_DMA_TX_CH 5
|
||||
#define RTE_SPI2_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI2_DMA_RX_CH 4
|
||||
#define RTE_SPI2_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI3_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI3_DMA_TX_CH 7
|
||||
#define RTE_SPI3_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI3_DMA_RX_CH 6
|
||||
#define RTE_SPI3_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI4_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI4_DMA_TX_CH 9
|
||||
#define RTE_SPI4_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI4_DMA_RX_CH 8
|
||||
#define RTE_SPI4_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI5_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI5_DMA_TX_CH 11
|
||||
#define RTE_SPI5_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI5_DMA_RX_CH 10
|
||||
#define RTE_SPI5_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI6_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI6_DMA_TX_CH 13
|
||||
#define RTE_SPI6_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI6_DMA_RX_CH 12
|
||||
#define RTE_SPI6_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI7_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI7_DMA_TX_CH 15
|
||||
#define RTE_SPI7_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI7_DMA_RX_CH 14
|
||||
#define RTE_SPI7_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#endif /* __RTE_DEVICE_H */
|
||||
195
Living_SDK/platform/mcu/lpc54102/aos/aos.c
Normal file
195
Living_SDK/platform/mcu/lpc54102/aos/aos.c
Normal file
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "fsl_debug_console.h"
|
||||
#include "fsl_gpio.h"
|
||||
|
||||
#include "pin_mux.h"
|
||||
|
||||
#include <aos/aos.h>
|
||||
#include <k_api.h>
|
||||
#include <aos/kernel.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "hal/wifi.h"
|
||||
#include "hal/ota.h"
|
||||
|
||||
#define AOS_START_STACK 1536
|
||||
|
||||
#define WIFI_PRODUCT_INFO_SIZE ES_WIFI_MAX_SSID_NAME_SIZE
|
||||
|
||||
ktask_t *g_aos_init;
|
||||
ktask_t *g_aos_app = NULL;
|
||||
extern int application_start(int argc, char **argv);
|
||||
extern int aos_framework_init(void);
|
||||
|
||||
extern hal_wifi_module_t qca_4002_wmi;
|
||||
|
||||
static int init_wifi()
|
||||
{
|
||||
int ret;
|
||||
PRINTF("Register WMI Wifi 0x%x", &qca_4002_wmi);
|
||||
hal_wifi_register_module(&qca_4002_wmi);
|
||||
ret = hal_wifi_init();
|
||||
PRINTF("hal_wifi_init return %d", ret);
|
||||
}
|
||||
|
||||
|
||||
extern void hw_start_hal(void);
|
||||
|
||||
static void sys_init(void)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
init_wifi();
|
||||
|
||||
#ifdef BOOTLOADER
|
||||
|
||||
#else
|
||||
#ifdef AOS_VFS
|
||||
vfs_init();
|
||||
vfs_device_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AOS_CLI
|
||||
aos_cli_init();
|
||||
#endif
|
||||
|
||||
#ifdef AOS_KV
|
||||
aos_kv_init();
|
||||
#endif
|
||||
|
||||
#ifdef WITH_SAL
|
||||
sal_device_init();
|
||||
#endif
|
||||
|
||||
#ifdef AOS_LOOP
|
||||
aos_loop_init();
|
||||
#endif
|
||||
|
||||
#ifdef AOS_FOTA
|
||||
ota_service_init();
|
||||
#endif
|
||||
|
||||
aos_framework_init();
|
||||
application_start(0, NULL);
|
||||
#endif
|
||||
}
|
||||
extern struct hal_ota_module_s hal_lpc54102_ota_module;
|
||||
static void platform_init(void)
|
||||
{
|
||||
uint32_t port_state = 0;
|
||||
|
||||
/* Define the init structure for the output LED pin*/
|
||||
gpio_pin_config_t led_config = {
|
||||
kGPIO_DigitalOutput, 0,
|
||||
};
|
||||
|
||||
/* Board pin, clock, debug console init */
|
||||
/* attach 12 MHz clock to USART0 (debug console) */
|
||||
CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
|
||||
/* enable clock for GPIO*/
|
||||
CLOCK_EnableClock(kCLOCK_Gpio0);
|
||||
CLOCK_EnableClock(kCLOCK_Gpio1);
|
||||
CLOCK_EnableClock(kCLOCK_Sram1);
|
||||
CLOCK_EnableClock(kCLOCK_Sram2);
|
||||
|
||||
|
||||
BOARD_InitPins();
|
||||
BOARD_BootClockPLL96M(); /* Rev B device can only support max core frequency to 96Mhz.
|
||||
Rev C device can support 100Mhz,use BOARD_BootClockPLL100M() to boot core to 100Mhz.
|
||||
DEVICE_ID1 register in SYSCON shows the device version.
|
||||
More details please refer to user manual and errata. */
|
||||
BOARD_InitDebugConsole();
|
||||
|
||||
#ifdef AOS_FOTA
|
||||
hal_ota_register_module(&hal_lpc54102_ota_module);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdbool.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <k_api.h>
|
||||
#include <aos/log.h>
|
||||
#include <hal/soc/soc.h>
|
||||
#include <hal/soc/timer.h>
|
||||
#include <hal/base.h>
|
||||
#include <hal/wifi.h>
|
||||
#include <hal/ota.h>
|
||||
|
||||
#define TAG "hw"
|
||||
|
||||
#define us2tick(us) \
|
||||
((us * RHINO_CONFIG_TICKS_PER_SECOND + 999999) / 1000000)
|
||||
|
||||
|
||||
void hal_reboot(void)
|
||||
{
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
static void _timer_cb(void *timer, void *arg)
|
||||
{
|
||||
timer_dev_t *tmr = arg;
|
||||
tmr->config.cb(tmr->config.arg);
|
||||
}
|
||||
|
||||
int32_t hal_timer_init(timer_dev_t *tim)
|
||||
{
|
||||
if (tim->config.reload_mode == TIMER_RELOAD_AUTO) {
|
||||
krhino_timer_dyn_create((ktimer_t **)&tim->priv, "hwtmr", _timer_cb,
|
||||
us2tick(tim->config.period), us2tick(tim->config.period), tim, 0);
|
||||
}
|
||||
else {
|
||||
krhino_timer_dyn_create((ktimer_t **)&tim->priv, "hwtmr", _timer_cb,
|
||||
us2tick(tim->config.period), 0, tim, 0);
|
||||
}
|
||||
}
|
||||
|
||||
int32_t hal_timer_start(timer_dev_t *tmr)
|
||||
{
|
||||
return krhino_timer_start(tmr->priv);
|
||||
}
|
||||
|
||||
|
||||
void hal_timer_stop(timer_dev_t *tmr)
|
||||
{
|
||||
krhino_timer_stop(tmr->priv);
|
||||
krhino_timer_dyn_del(tmr->priv);
|
||||
tmr->priv = NULL;
|
||||
}
|
||||
|
||||
|
||||
void hw_start_hal(void)
|
||||
{
|
||||
PRINTF("start-----------hal\n");
|
||||
}
|
||||
|
||||
|
||||
int main(void)
|
||||
{
|
||||
uint32_t core_frequency = 0;
|
||||
platform_init();
|
||||
|
||||
aos_init();
|
||||
krhino_task_dyn_create(&g_aos_app, "aos-init", 0, AOS_DEFAULT_APP_PRI, 0, AOS_START_STACK, (task_entry_t)sys_init, 1);
|
||||
core_frequency = CLOCK_GetCoreClkFreq();
|
||||
|
||||
SysTick_Config(core_frequency / 100); //10ms
|
||||
aos_start();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
118
Living_SDK/platform/mcu/lpc54102/aos/soc_impl.c
Normal file
118
Living_SDK/platform/mcu/lpc54102/aos/soc_impl.c
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
|
||||
*/
|
||||
|
||||
#include <k_api.h>
|
||||
#include <assert.h>
|
||||
|
||||
#if (RHINO_CONFIG_HW_COUNT > 0)
|
||||
void soc_hw_timer_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
hr_timer_t soc_hr_hw_cnt_get(void)
|
||||
{
|
||||
return 0;
|
||||
//return *(volatile uint64_t *)0xc0000120;
|
||||
}
|
||||
|
||||
lr_timer_t soc_lr_hw_cnt_get(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif /* RHINO_CONFIG_HW_COUNT */
|
||||
|
||||
#if (RHINO_CONFIG_INTRPT_GUARD > 0)
|
||||
void soc_intrpt_guard(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (RHINO_CONFIG_INTRPT_STACK_REMAIN_GET > 0)
|
||||
size_t soc_intrpt_stack_remain_get(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (RHINO_CONFIG_INTRPT_STACK_OVF_CHECK > 0)
|
||||
void soc_intrpt_stack_ovf_check(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if (RHINO_CONFIG_MM_LEAKCHECK > 0 )
|
||||
|
||||
extern int __bss_start__, __bss_end__, _sdata, _edata;
|
||||
|
||||
void aos_mm_leak_region_init(void)
|
||||
{
|
||||
#if (RHINO_CONFIG_MM_DEBUG > 0)
|
||||
krhino_mm_leak_region_init(&__bss_start__, &__bss_end__);
|
||||
krhino_mm_leak_region_init(&_sdata, &_edata);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#if (RHINO_CONFIG_TASK_STACK_CUR_CHECK > 0)
|
||||
size_t soc_get_cur_sp()
|
||||
{
|
||||
size_t sp = 0;
|
||||
asm volatile(
|
||||
"mov %0,sp\n"
|
||||
:"=r"(sp));
|
||||
return sp;
|
||||
}
|
||||
#endif
|
||||
static void soc_print_stack()
|
||||
{
|
||||
|
||||
uint32_t offset = 0;
|
||||
kstat_t rst = RHINO_SUCCESS;
|
||||
void *cur, *end;
|
||||
int i=0;
|
||||
int *p;
|
||||
|
||||
end = krhino_cur_task_get()->task_stack_base + krhino_cur_task_get()->stack_size;
|
||||
cur = (void*)soc_get_cur_sp();
|
||||
p = (int*)cur;
|
||||
while(p < (int*)end) {
|
||||
if(i%4==0) {
|
||||
printf("\r\n%08x:",(uint32_t)p);
|
||||
}
|
||||
printf("%08x ", *p);
|
||||
i++;
|
||||
p++;
|
||||
}
|
||||
printf("\r\n");
|
||||
return;
|
||||
}
|
||||
void soc_err_proc(kstat_t err)
|
||||
{
|
||||
(void)err;
|
||||
soc_print_stack();
|
||||
assert(0);
|
||||
}
|
||||
|
||||
krhino_err_proc_t g_err_proc = soc_err_proc;
|
||||
|
||||
#include "k_api.h"
|
||||
extern void *_pvHeapStart;
|
||||
extern void *_pvHeapLimit;
|
||||
extern uint8_t _vHeap2Base[];
|
||||
k_mm_region_t g_mm_region[] = {
|
||||
{
|
||||
(uint8_t *)&_pvHeapStart, (uint32_t)0xE800},
|
||||
{_vHeap2Base, 0x1800,},
|
||||
};
|
||||
|
||||
int g_region_num = sizeof(g_mm_region)/sizeof(k_mm_region_t);
|
||||
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
krhino_intrpt_enter();
|
||||
krhino_tick_proc();
|
||||
krhino_intrpt_exit();
|
||||
}
|
||||
316
Living_SDK/platform/mcu/lpc54102/drivers/fsl_adc.c
Normal file
316
Living_SDK/platform/mcu/lpc54102/drivers/fsl_adc.c
Normal file
|
|
@ -0,0 +1,316 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_adc.h"
|
||||
#include "fsl_clock.h"
|
||||
|
||||
static ADC_Type *const s_adcBases[] = ADC_BASE_PTRS;
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
static const clock_ip_name_t s_adcClocks[] = ADC_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
static uint32_t ADC_GetInstance(ADC_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_adcBases); instance++)
|
||||
{
|
||||
if (s_adcBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_adcBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void ADC_Init(ADC_Type *base, const adc_config_t *config)
|
||||
{
|
||||
assert(config != NULL);
|
||||
|
||||
uint32_t tmp32 = 0U;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable clock. */
|
||||
CLOCK_EnableClock(s_adcClocks[ADC_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Disable the interrupts. */
|
||||
base->INTEN = 0U; /* Quickly disable all the interrupts. */
|
||||
|
||||
/* Configure the ADC block. */
|
||||
tmp32 = ADC_CTRL_CLKDIV(config->clockDividerNumber);
|
||||
|
||||
/* Async or Sync clock mode. */
|
||||
switch (config->clockMode)
|
||||
{
|
||||
case kADC_ClockAsynchronousMode:
|
||||
tmp32 |= ADC_CTRL_ASYNMODE_MASK;
|
||||
break;
|
||||
default: /* kADC_ClockSynchronousMode */
|
||||
break;
|
||||
}
|
||||
|
||||
/* Resolution. */
|
||||
tmp32 |= ADC_CTRL_RESOL(config->resolution);
|
||||
|
||||
/* Bypass calibration. */
|
||||
if (config->enableBypassCalibration)
|
||||
{
|
||||
tmp32 |= ADC_CTRL_BYPASSCAL_MASK;
|
||||
}
|
||||
|
||||
/* Sample time clock count. */
|
||||
tmp32 |= ADC_CTRL_TSAMP(config->sampleTimeNumber);
|
||||
|
||||
base->CTRL = tmp32;
|
||||
}
|
||||
|
||||
void ADC_GetDefaultConfig(adc_config_t *config)
|
||||
{
|
||||
config->clockMode = kADC_ClockSynchronousMode;
|
||||
config->clockDividerNumber = 0U;
|
||||
config->resolution = kADC_Resolution12bit;
|
||||
config->enableBypassCalibration = false;
|
||||
config->sampleTimeNumber = 0U;
|
||||
}
|
||||
|
||||
void ADC_Deinit(ADC_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the clock. */
|
||||
CLOCK_DisableClock(s_adcClocks[ADC_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
bool ADC_DoSelfCalibration(ADC_Type *base)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
/* Enable the converter. */
|
||||
/* This bit acn only be set 1 by software. It is cleared automatically whenever the ADC is powered down.
|
||||
This bit should be set after at least 10 ms after the ADC is powered on. */
|
||||
base->STARTUP = ADC_STARTUP_ADC_ENA_MASK;
|
||||
for (i = 0U; i < 0x10; i++) /* Wait a few clocks to startup up. */
|
||||
{
|
||||
__ASM("NOP");
|
||||
}
|
||||
if (!(base->STARTUP & ADC_STARTUP_ADC_ENA_MASK))
|
||||
{
|
||||
return false; /* ADC is not powered up. */
|
||||
}
|
||||
|
||||
/* If not in by-pass mode, do the calibration. */
|
||||
if ((ADC_CALIB_CALREQD_MASK == (base->CALIB & ADC_CALIB_CALREQD_MASK)) &&
|
||||
(0U == (base->CTRL & ADC_CTRL_BYPASSCAL_MASK)))
|
||||
{
|
||||
/* Calibration is needed, do it now. */
|
||||
base->CALIB = ADC_CALIB_CALIB_MASK;
|
||||
i = 0xF0000;
|
||||
while ((ADC_CALIB_CALIB_MASK == (base->CALIB & ADC_CALIB_CALIB_MASK)) && (--i))
|
||||
{
|
||||
}
|
||||
if (i == 0U)
|
||||
{
|
||||
return false; /* Calibration timeout. */
|
||||
}
|
||||
}
|
||||
|
||||
/* A dummy conversion cycle will be performed. */
|
||||
base->STARTUP |= ADC_STARTUP_ADC_INIT_MASK;
|
||||
i = 0x7FFFF;
|
||||
while ((ADC_STARTUP_ADC_INIT_MASK == (base->STARTUP & ADC_STARTUP_ADC_INIT_MASK)) && (--i))
|
||||
{
|
||||
}
|
||||
if (i == 0U)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
|
||||
{
|
||||
assert(config != NULL);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask) /* Channel mask. */
|
||||
| ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
|
||||
|
||||
/* Polarity for tirgger signal. */
|
||||
switch (config->triggerPolarity)
|
||||
{
|
||||
case kADC_TriggerPolarityPositiveEdge:
|
||||
tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
|
||||
break;
|
||||
default: /* kADC_TriggerPolarityNegativeEdge */
|
||||
break;
|
||||
}
|
||||
|
||||
/* Bypass the clock Sync. */
|
||||
if (config->enableSyncBypass)
|
||||
{
|
||||
tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
|
||||
}
|
||||
|
||||
/* Interrupt point. */
|
||||
switch (config->interruptMode)
|
||||
{
|
||||
case kADC_InterruptForEachSequence:
|
||||
tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
|
||||
break;
|
||||
default: /* kADC_InterruptForEachConversion */
|
||||
break;
|
||||
}
|
||||
|
||||
/* One trigger for a conversion, or for a sequence. */
|
||||
if (config->enableSingleStep)
|
||||
{
|
||||
tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
|
||||
}
|
||||
|
||||
base->SEQ_CTRL[0] = tmp32;
|
||||
}
|
||||
|
||||
void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config)
|
||||
{
|
||||
assert(config != NULL);
|
||||
|
||||
uint32_t tmp32;
|
||||
|
||||
tmp32 = ADC_SEQ_CTRL_CHANNELS(config->channelMask) /* Channel mask. */
|
||||
| ADC_SEQ_CTRL_TRIGGER(config->triggerMask); /* Trigger mask. */
|
||||
|
||||
/* Polarity for tirgger signal. */
|
||||
switch (config->triggerPolarity)
|
||||
{
|
||||
case kADC_TriggerPolarityPositiveEdge:
|
||||
tmp32 |= ADC_SEQ_CTRL_TRIGPOL_MASK;
|
||||
break;
|
||||
default: /* kADC_TriggerPolarityPositiveEdge */
|
||||
break;
|
||||
}
|
||||
|
||||
/* Bypass the clock Sync. */
|
||||
if (config->enableSyncBypass)
|
||||
{
|
||||
tmp32 |= ADC_SEQ_CTRL_SYNCBYPASS_MASK;
|
||||
}
|
||||
|
||||
/* Interrupt point. */
|
||||
switch (config->interruptMode)
|
||||
{
|
||||
case kADC_InterruptForEachSequence:
|
||||
tmp32 |= ADC_SEQ_CTRL_MODE_MASK;
|
||||
break;
|
||||
default: /* kADC_InterruptForEachConversion */
|
||||
break;
|
||||
}
|
||||
|
||||
/* One trigger for a conversion, or for a sequence. */
|
||||
if (config->enableSingleStep)
|
||||
{
|
||||
tmp32 |= ADC_SEQ_CTRL_SINGLESTEP_MASK;
|
||||
}
|
||||
|
||||
base->SEQ_CTRL[1] = tmp32;
|
||||
}
|
||||
|
||||
bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
|
||||
{
|
||||
assert(info != NULL);
|
||||
|
||||
uint32_t tmp32 = base->SEQ_GDAT[0]; /* Read to clear the status. */
|
||||
|
||||
if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
|
||||
info->thresholdCompareStatus =
|
||||
(adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
|
||||
info->thresholdCorssingStatus =
|
||||
(adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
|
||||
info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
|
||||
info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info)
|
||||
{
|
||||
assert(info != NULL);
|
||||
|
||||
uint32_t tmp32 = base->SEQ_GDAT[1]; /* Read to clear the status. */
|
||||
|
||||
if (0U == (ADC_SEQ_GDAT_DATAVALID_MASK & tmp32))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
info->result = (tmp32 & ADC_SEQ_GDAT_RESULT_MASK) >> ADC_SEQ_GDAT_RESULT_SHIFT;
|
||||
info->thresholdCompareStatus =
|
||||
(adc_threshold_compare_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPRANGE_MASK) >> ADC_SEQ_GDAT_THCMPRANGE_SHIFT);
|
||||
info->thresholdCorssingStatus =
|
||||
(adc_threshold_crossing_status_t)((tmp32 & ADC_SEQ_GDAT_THCMPCROSS_MASK) >> ADC_SEQ_GDAT_THCMPCROSS_SHIFT);
|
||||
info->channelNumber = (tmp32 & ADC_SEQ_GDAT_CHN_MASK) >> ADC_SEQ_GDAT_CHN_SHIFT;
|
||||
info->overrunFlag = ((tmp32 & ADC_SEQ_GDAT_OVERRUN_MASK) == ADC_SEQ_GDAT_OVERRUN_MASK);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info)
|
||||
{
|
||||
assert(info != NULL);
|
||||
assert(channel < ADC_DAT_COUNT);
|
||||
|
||||
uint32_t tmp32 = base->DAT[channel]; /* Read to clear the status. */
|
||||
|
||||
if (0U == (ADC_DAT_DATAVALID_MASK & tmp32))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
info->result = (tmp32 & ADC_DAT_RESULT_MASK) >> ADC_DAT_RESULT_SHIFT;
|
||||
info->thresholdCompareStatus =
|
||||
(adc_threshold_compare_status_t)((tmp32 & ADC_DAT_THCMPRANGE_MASK) >> ADC_DAT_THCMPRANGE_SHIFT);
|
||||
info->thresholdCorssingStatus =
|
||||
(adc_threshold_crossing_status_t)((tmp32 & ADC_DAT_THCMPCROSS_MASK) >> ADC_DAT_THCMPCROSS_SHIFT);
|
||||
info->channelNumber = (tmp32 & ADC_DAT_CHANNEL_MASK) >> ADC_DAT_CHANNEL_SHIFT;
|
||||
info->overrunFlag = ((tmp32 & ADC_DAT_OVERRUN_MASK) == ADC_DAT_OVERRUN_MASK);
|
||||
|
||||
return true;
|
||||
}
|
||||
676
Living_SDK/platform/mcu/lpc54102/drivers/fsl_adc.h
Normal file
676
Living_SDK/platform/mcu/lpc54102/drivers/fsl_adc.h
Normal file
|
|
@ -0,0 +1,676 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __FSL_ADC_H__
|
||||
#define __FSL_ADC_H__
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup lpc_adc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief ADC driver version 2.1.0. */
|
||||
#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief Flags
|
||||
*/
|
||||
enum _adc_status_flags
|
||||
{
|
||||
kADC_ThresholdCompareFlagOnChn0 = 1U << 0U, /*!< Threshold comparison event on Channel 0. */
|
||||
kADC_ThresholdCompareFlagOnChn1 = 1U << 1U, /*!< Threshold comparison event on Channel 1. */
|
||||
kADC_ThresholdCompareFlagOnChn2 = 1U << 2U, /*!< Threshold comparison event on Channel 2. */
|
||||
kADC_ThresholdCompareFlagOnChn3 = 1U << 3U, /*!< Threshold comparison event on Channel 3. */
|
||||
kADC_ThresholdCompareFlagOnChn4 = 1U << 4U, /*!< Threshold comparison event on Channel 4. */
|
||||
kADC_ThresholdCompareFlagOnChn5 = 1U << 5U, /*!< Threshold comparison event on Channel 5. */
|
||||
kADC_ThresholdCompareFlagOnChn6 = 1U << 6U, /*!< Threshold comparison event on Channel 6. */
|
||||
kADC_ThresholdCompareFlagOnChn7 = 1U << 7U, /*!< Threshold comparison event on Channel 7. */
|
||||
kADC_ThresholdCompareFlagOnChn8 = 1U << 8U, /*!< Threshold comparison event on Channel 8. */
|
||||
kADC_ThresholdCompareFlagOnChn9 = 1U << 9U, /*!< Threshold comparison event on Channel 9. */
|
||||
kADC_ThresholdCompareFlagOnChn10 = 1U << 10U, /*!< Threshold comparison event on Channel 10. */
|
||||
kADC_ThresholdCompareFlagOnChn11 = 1U << 11U, /*!< Threshold comparison event on Channel 11. */
|
||||
kADC_OverrunFlagForChn0 =
|
||||
1U << 12U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 0. */
|
||||
kADC_OverrunFlagForChn1 =
|
||||
1U << 13U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 1. */
|
||||
kADC_OverrunFlagForChn2 =
|
||||
1U << 14U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 2. */
|
||||
kADC_OverrunFlagForChn3 =
|
||||
1U << 15U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 3. */
|
||||
kADC_OverrunFlagForChn4 =
|
||||
1U << 16U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 4. */
|
||||
kADC_OverrunFlagForChn5 =
|
||||
1U << 17U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 5. */
|
||||
kADC_OverrunFlagForChn6 =
|
||||
1U << 18U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 6. */
|
||||
kADC_OverrunFlagForChn7 =
|
||||
1U << 19U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 7. */
|
||||
kADC_OverrunFlagForChn8 =
|
||||
1U << 20U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 8. */
|
||||
kADC_OverrunFlagForChn9 =
|
||||
1U << 21U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 9. */
|
||||
kADC_OverrunFlagForChn10 =
|
||||
1U << 22U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 10. */
|
||||
kADC_OverrunFlagForChn11 =
|
||||
1U << 23U, /*!< Mirror the OVERRUN status flag from the result register for ADC channel 11. */
|
||||
kADC_GlobalOverrunFlagForSeqA = 1U << 24U, /*!< Mirror the glabal OVERRUN status flag for conversion sequence A. */
|
||||
kADC_GlobalOverrunFlagForSeqB = 1U << 25U, /*!< Mirror the global OVERRUN status flag for conversion sequence B. */
|
||||
kADC_ConvSeqAInterruptFlag = 1U << 28U, /*!< Sequence A interrupt/DMA trigger. */
|
||||
kADC_ConvSeqBInterruptFlag = 1U << 29U, /*!< Sequence B interrupt/DMA trigger. */
|
||||
kADC_ThresholdCompareInterruptFlag = 1U << 30U, /*!< Threshold comparision interrupt flag. */
|
||||
kADC_OverrunInterruptFlag = 1U << 31U, /*!< Overrun interrupt flag. */
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief Interrupts
|
||||
* @note Not all the interrupt options are listed here
|
||||
*/
|
||||
enum _adc_interrupt_enable
|
||||
{
|
||||
kADC_ConvSeqAInterruptEnable = ADC_INTEN_SEQA_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
|
||||
conversion in sequence A, or entire sequence. */
|
||||
kADC_ConvSeqBInterruptEnable = ADC_INTEN_SEQB_INTEN_MASK, /*!< Enable interrupt upon completion of each individual
|
||||
conversion in sequence B, or entire sequence. */
|
||||
kADC_OverrunInterruptEnable = ADC_INTEN_OVR_INTEN_MASK, /*!< Enable the detection of an overrun condition on any of
|
||||
the channel data registers will cause an overrun
|
||||
interrupt/DMA trigger. */
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief Define selection of clock mode.
|
||||
*/
|
||||
typedef enum _adc_clock_mode
|
||||
{
|
||||
kADC_ClockSynchronousMode =
|
||||
0U, /*!< The ADC clock would be derived from the system clock based on "clockDividerNumber". */
|
||||
kADC_ClockAsynchronousMode = 1U, /*!< The ADC clock would be based on the SYSCON block's divider. */
|
||||
} adc_clock_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Define selection of resolution.
|
||||
*/
|
||||
typedef enum _adc_resolution
|
||||
{
|
||||
kADC_Resolution6bit = 0U, /*!< 6-bit resolution. */
|
||||
kADC_Resolution8bit = 1U, /*!< 8-bit resolution. */
|
||||
kADC_Resolution10bit = 2U, /*!< 10-bit resolution. */
|
||||
kADC_Resolution12bit = 3U, /*!< 12-bit resolution. */
|
||||
} adc_resolution_t;
|
||||
|
||||
/*!
|
||||
* @brief Define selection of polarity of selected input trigger for conversion sequence.
|
||||
*/
|
||||
typedef enum _adc_trigger_polarity
|
||||
{
|
||||
kADC_TriggerPolarityNegativeEdge = 0U, /*!< A negative edge launches the conversion sequence on the trigger(s). */
|
||||
kADC_TriggerPolarityPositiveEdge = 1U, /*!< A positive edge launches the conversion sequence on the trigger(s). */
|
||||
} adc_trigger_polarity_t;
|
||||
|
||||
/*!
|
||||
* @brief Define selection of conversion sequence's priority.
|
||||
*/
|
||||
typedef enum _adc_priority
|
||||
{
|
||||
kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */
|
||||
kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when it is started. */
|
||||
} adc_priority_t;
|
||||
|
||||
/*!
|
||||
* @brief Define selection of conversion sequence's interrupt.
|
||||
*/
|
||||
typedef enum _adc_seq_interrupt_mode
|
||||
{
|
||||
kADC_InterruptForEachConversion = 0U, /*!< The sequence interrupt/DMA trigger will be set at the end of each
|
||||
individual ADC conversion inside this conversion sequence. */
|
||||
kADC_InterruptForEachSequence = 1U, /*!< The sequence interrupt/DMA trigger will be set when the entire set of
|
||||
this sequence conversions completes. */
|
||||
} adc_seq_interrupt_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Define status of threshold compare result.
|
||||
*/
|
||||
typedef enum _adc_threshold_compare_status
|
||||
{
|
||||
kADC_ThresholdCompareInRange = 0U, /*!< LOW threshold <= conversion value <= HIGH threshold. */
|
||||
kADC_ThresholdCompareBelowRange = 1U, /*!< conversion value < LOW threshold. */
|
||||
kADC_ThresholdCompareAboveRange = 2U, /*!< conversion value > HIGH threshold. */
|
||||
} adc_threshold_compare_status_t;
|
||||
|
||||
/*!
|
||||
* @brief Define status of threshold crossing detection result.
|
||||
*/
|
||||
typedef enum _adc_threshold_crossing_status
|
||||
{
|
||||
/* The conversion on this channel had the same relationship (above or below) to the threshold value established by
|
||||
* the designated LOW threshold value as did the previous conversion on this channel. */
|
||||
kADC_ThresholdCrossingNoDetected = 0U, /*!< No threshold Crossing detected. */
|
||||
|
||||
/* Indicates that a threshold crossing in the downward direction has occurred - i.e. the previous sample on this
|
||||
* channel was above the threshold value established by the designated LOW threshold value and the current sample is
|
||||
* below that threshold. */
|
||||
kADC_ThresholdCrossingDownward = 2U, /*!< Downward Threshold Crossing detected. */
|
||||
|
||||
/* Indicates that a thre shold crossing in the upward direction has occurred - i.e. the previous sample on this
|
||||
* channel was below the threshold value established by the designated LOW threshold value and the current sample is
|
||||
* above that threshold. */
|
||||
kADC_ThresholdCrossingUpward = 3U, /*!< Upward Threshold Crossing Detected. */
|
||||
} adc_threshold_crossing_status_t;
|
||||
|
||||
/*!
|
||||
* @brief Define interrupt mode for threshold compare event.
|
||||
*/
|
||||
typedef enum _adc_threshold_interrupt_mode
|
||||
{
|
||||
kADC_ThresholdInterruptDisabled = 0U, /*!< Threshold comparison interrupt is disabled. */
|
||||
kADC_ThresholdInterruptOnOutside = 1U, /*!< Threshold comparison interrupt is enabled on outside threshold. */
|
||||
kADC_ThresholdInterruptOnCrossing = 2U, /*!< Threshold comparison interrupt is enabled on crossing threshold. */
|
||||
} adc_threshold_interrupt_mode_t;
|
||||
|
||||
/*!
|
||||
* @brief Define structure for configuring the block.
|
||||
*/
|
||||
typedef struct _adc_config
|
||||
{
|
||||
adc_clock_mode_t clockMode; /*!< Select the clock mode for ADC converter. */
|
||||
uint32_t clockDividerNumber; /*!< This field is only available when using kADC_ClockSynchronousMode for "clockMode"
|
||||
field. The divider would be plused by 1 based on the value in this field. The
|
||||
available range is in 8 bits. */
|
||||
adc_resolution_t resolution; /*!< Select the conversion bits. */
|
||||
bool enableBypassCalibration; /*!< By default, a calibration cycle must be performed each time the chip is
|
||||
powered-up. Re-calibration may be warranted periodically - especially if
|
||||
operating conditions have changed. To enable this option would avoid the need to
|
||||
calibrate if offset error is not a concern in the application. */
|
||||
uint32_t sampleTimeNumber; /*!< By default, with value as "0U", the sample period would be 2.5 ADC clocks. Then,
|
||||
to plus the "sampleTimeNumber" value here. The available value range is in 3 bits.*/
|
||||
} adc_config_t;
|
||||
|
||||
/*!
|
||||
* @brief Define structure for configuring conversion sequence.
|
||||
*/
|
||||
typedef struct _adc_conv_seq_config
|
||||
{
|
||||
uint32_t channelMask; /*!< Selects which one or more of the ADC channels will be sampled and converted when this
|
||||
sequence is launched. The masked channels would be involved in current conversion
|
||||
sequence, beginning with the lowest-order. The available range is in 12-bit. */
|
||||
uint32_t triggerMask; /*!< Selects which one or more of the available hardware trigger sources will cause this
|
||||
conversion sequence to be initiated. The available range is 6-bit.*/
|
||||
adc_trigger_polarity_t triggerPolarity; /*!< Select the trigger to lauch conversion sequence. */
|
||||
bool enableSyncBypass; /*!< To enable this feature allows the hardware trigger input to bypass synchronization
|
||||
flip-flop stages and therefore shorten the time between the trigger input signal and the
|
||||
start of a conversion. */
|
||||
bool enableSingleStep; /*!< When enabling this feature, a trigger will launch a single conversion on the next
|
||||
channel in the sequence instead of the default response of launching an entire sequence
|
||||
of conversions. */
|
||||
adc_seq_interrupt_mode_t interruptMode; /*!< Select the interrpt/DMA trigger mode. */
|
||||
} adc_conv_seq_config_t;
|
||||
|
||||
/*!
|
||||
* @brief Define structure of keeping conversion result information.
|
||||
*/
|
||||
typedef struct _adc_result_info
|
||||
{
|
||||
uint32_t result; /*!< Keep the conversion data value. */
|
||||
adc_threshold_compare_status_t thresholdCompareStatus; /*!< Keep the threshold compare status. */
|
||||
adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */
|
||||
uint32_t channelNumber; /*!< Keep the channel number for this conversion. */
|
||||
bool overrunFlag; /*!< Keep the status whether the conversion is overrun or not. */
|
||||
/* The data available flag would be returned by the reading result API. */
|
||||
} adc_result_info_t;
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @name Initialization and Deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initialize the ADC module.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param config Pointer to configuration structure, see to #adc_config_t.
|
||||
*/
|
||||
void ADC_Init(ADC_Type *base, const adc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Deinitialize the ADC module.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
*/
|
||||
void ADC_Deinit(ADC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Gets an available pre-defined settings for initial configuration.
|
||||
*
|
||||
* This function initializes the initial configuration structure with an available settings. The default values are:
|
||||
* @code
|
||||
* config->clockMode = kADC_ClockSynchronousMode;
|
||||
* config->clockDividerNumber = 0U;
|
||||
* config->resolution = kADC_Resolution12bit;
|
||||
* config->enableBypassCalibration = false;
|
||||
* config->sampleTimeNumber = 0U;
|
||||
* @endcode
|
||||
* @param config Pointer to configuration structure.
|
||||
*/
|
||||
void ADC_GetDefaultConfig(adc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Do the self hardware calibration.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @retval true Calibration succeed.
|
||||
* @retval false Calibration failed.
|
||||
*/
|
||||
bool ADC_DoSelfCalibration(ADC_Type *base);
|
||||
|
||||
#if !(defined(FSL_FEATURE_ADC_HAS_NO_INSEL) && FSL_FEATURE_ADC_HAS_NO_INSEL)
|
||||
/*!
|
||||
* @brief Enable the internal temperature sensor measurement.
|
||||
*
|
||||
* When enabling the internal temperature sensor measurement, the channel 0 would be connected to internal sensor
|
||||
* instead of external pin.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param enable Switcher to enable the feature or not.
|
||||
*/
|
||||
static inline void ADC_EnableTemperatureSensor(ADC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0x3);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0);
|
||||
}
|
||||
}
|
||||
#endif /* FSL_FEATURE_ADC_HAS_NO_INSEL. */
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Control conversion sequence A.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enable the conversion sequence A.
|
||||
*
|
||||
* In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
|
||||
* sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
|
||||
* sequence during changing the sequence's setting.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param enable Switcher to enable the feature or not.
|
||||
*/
|
||||
static inline void ADC_EnableConvSeqA(ADC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Configure the conversion sequence A.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
|
||||
*/
|
||||
void ADC_SetConvSeqAConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Do trigger the sequence's conversion by software.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
*/
|
||||
static inline void ADC_DoSoftwareTriggerConvSeqA(ADC_Type *base)
|
||||
{
|
||||
base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_START_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the burst conversion of sequence A.
|
||||
*
|
||||
* Enable the burst mode would cause the conversion sequence to be cntinuously cycled through. Other triggers would be
|
||||
* ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
|
||||
* currently in process will be completed before cnversions are terminated.
|
||||
* Note that a new sequence could begin just before the burst mode is disabled.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param enable Switcher to enable this feature.
|
||||
*/
|
||||
static inline void ADC_EnableConvSeqABurstMode(ADC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_BURST_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_BURST_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set the high priority for conversion sequence A.
|
||||
*
|
||||
* @param base ADC peripheral bass address.
|
||||
*/
|
||||
static inline void ADC_SetConvSeqAHighPriority(ADC_Type *base)
|
||||
{
|
||||
base->SEQ_CTRL[0] |= ADC_SEQ_CTRL_LOWPRIO_MASK;
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Control conversion sequence B.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enable the conversion sequence B.
|
||||
*
|
||||
* In order to avoid spuriously triggering the sequence, the trigger to conversion sequence should be ready before the
|
||||
* sequence is ready. when the sequence is disabled, the trigger would be ignored. Also, it is suggested to disable the
|
||||
* sequence during changing the sequence's setting.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param enable Switcher to enable the feature or not.
|
||||
*/
|
||||
static inline void ADC_EnableConvSeqB(ADC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_SEQ_ENA_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_SEQ_ENA_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Configure the conversion sequence B.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param config Pointer to configuration structure, see to #adc_conv_seq_config_t.
|
||||
*/
|
||||
void ADC_SetConvSeqBConfig(ADC_Type *base, const adc_conv_seq_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Do trigger the sequence's conversion by software.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
*/
|
||||
static inline void ADC_DoSoftwareTriggerConvSeqB(ADC_Type *base)
|
||||
{
|
||||
base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_START_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the burst conversion of sequence B.
|
||||
*
|
||||
* Enable the burst mode would cause the conversion sequence to be continuously cycled through. Other triggers would be
|
||||
* ignored while this mode is enabled. Repeated conversions could be halted by disabling this mode. And the sequence
|
||||
* currently in process will be completed before cnversions are terminated.
|
||||
* Note that a new sequence could begin just before the burst mode is disabled.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param enable Switcher to enable this feature.
|
||||
*/
|
||||
static inline void ADC_EnableConvSeqBBurstMode(ADC_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->SEQ_CTRL[1] |= ADC_SEQ_CTRL_BURST_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->SEQ_CTRL[1] &= ~ADC_SEQ_CTRL_BURST_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set the high priority for conversion sequence B.
|
||||
*
|
||||
* @param base ADC peripheral bass address.
|
||||
*/
|
||||
static inline void ADC_SetConvSeqBHighPriority(ADC_Type *base)
|
||||
{
|
||||
base->SEQ_CTRL[0] &= ~ADC_SEQ_CTRL_LOWPRIO_MASK;
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Data result.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Get the global ADC conversion infomation of sequence A.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param info Pointer to information structure, see to #adc_result_info_t;
|
||||
* @retval true The conversion result is ready.
|
||||
* @retval false The conversion result is not ready yet.
|
||||
*/
|
||||
bool ADC_GetConvSeqAGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
|
||||
|
||||
/*!
|
||||
* @brief Get the global ADC conversion infomation of sequence B.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param info Pointer to information structure, see to #adc_result_info_t;
|
||||
* @retval true The conversion result is ready.
|
||||
* @retval false The conversion result is not ready yet.
|
||||
*/
|
||||
bool ADC_GetConvSeqBGlobalConversionResult(ADC_Type *base, adc_result_info_t *info);
|
||||
|
||||
/*!
|
||||
* @brief Get the channel's ADC conversion completed under each conversion sequence.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param channel The indicated channel number.
|
||||
* @param info Pointer to information structure, see to #adc_result_info_t;
|
||||
* @retval true The conversion result is ready.
|
||||
* @retval false The conversion result is not ready yet.
|
||||
*/
|
||||
bool ADC_GetChannelConversionResult(ADC_Type *base, uint32_t channel, adc_result_info_t *info);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Threshold function.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Set the threshhold pair 0 with low and high value.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param lowValue LOW threshold value.
|
||||
* @param highValue HIGH threshold value.
|
||||
*/
|
||||
static inline void ADC_SetThresholdPair0(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
|
||||
{
|
||||
base->THR0_LOW = ADC_THR0_LOW_THRLOW(lowValue);
|
||||
base->THR0_HIGH = ADC_THR0_HIGH_THRHIGH(highValue);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set the threshhold pair 1 with low and high value.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param lowValue LOW threshold value. The available value is with 12-bit.
|
||||
* @param highValue HIGH threshold value. The available value is with 12-bit.
|
||||
*/
|
||||
static inline void ADC_SetThresholdPair1(ADC_Type *base, uint32_t lowValue, uint32_t highValue)
|
||||
{
|
||||
base->THR1_LOW = ADC_THR1_LOW_THRLOW(lowValue);
|
||||
base->THR1_HIGH = ADC_THR1_HIGH_THRHIGH(highValue);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set given channels to apply the threshold pare 0.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param channelMask Indicated channels' mask.
|
||||
*/
|
||||
static inline void ADC_SetChannelWithThresholdPair0(ADC_Type *base, uint32_t channelMask)
|
||||
{
|
||||
base->CHAN_THRSEL &= ~(channelMask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set given channels to apply the threshold pare 1.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param channelMask Indicated channels' mask.
|
||||
*/
|
||||
static inline void ADC_SetChannelWithThresholdPair1(ADC_Type *base, uint32_t channelMask)
|
||||
{
|
||||
base->CHAN_THRSEL |= channelMask;
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Interrupts.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enable interrupts for conversion sequences.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param mask Mask of interrupt mask value for global block except each channal, see to #_adc_interrupt_enable.
|
||||
*/
|
||||
static inline void ADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTEN |= (0x7 & mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable interrupts for conversion sequence.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param mask Mask of interrupt mask value for global block except each channel, see to #_adc_interrupt_enable.
|
||||
*/
|
||||
static inline void ADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTEN &= ~(0x7 & mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the interrupt of threshold compare event for each channel.
|
||||
* @deprecated Do not use this function. It has been superceded by @ADC_EnableThresholdCompareInterrupt
|
||||
*/
|
||||
static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base,
|
||||
uint32_t channel,
|
||||
adc_threshold_interrupt_mode_t mode)
|
||||
{
|
||||
base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the interrupt of threshold compare event for each channel.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param channel Channel number.
|
||||
* @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t.
|
||||
*/
|
||||
static inline void ADC_EnableThresholdCompareInterrupt(ADC_Type *base,
|
||||
uint32_t channel,
|
||||
adc_threshold_interrupt_mode_t mode)
|
||||
{
|
||||
base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U));
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Status.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Get status flags of ADC module.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @return Mask of status flags of module, see to #_adc_status_flags.
|
||||
*/
|
||||
static inline uint32_t ADC_GetStatusFlags(ADC_Type *base)
|
||||
{
|
||||
return base->FLAGS;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear status flags of ADC module.
|
||||
*
|
||||
* @param base ADC peripheral base address.
|
||||
* @param mask Mask of status flags of module, see to #_adc_status_flags.
|
||||
*/
|
||||
static inline void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
|
||||
{
|
||||
base->FLAGS = mask; /* Write 1 to clear. */
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /* __FSL_ADC_H__ */
|
||||
1480
Living_SDK/platform/mcu/lpc54102/drivers/fsl_clock.c
Normal file
1480
Living_SDK/platform/mcu/lpc54102/drivers/fsl_clock.c
Normal file
File diff suppressed because it is too large
Load diff
771
Living_SDK/platform/mcu/lpc54102/drivers/fsl_clock.h
Normal file
771
Living_SDK/platform/mcu/lpc54102/drivers/fsl_clock.h
Normal file
|
|
@ -0,0 +1,771 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_CLOCK_H_
|
||||
#define _FSL_CLOCK_H_
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <assert.h>
|
||||
|
||||
/*! @addtogroup clock */
|
||||
/*! @{ */
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
*****************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief CLOCK driver version 2.0.1. */
|
||||
#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief User-defined the size of cache for CLOCK_PllGetConfig() function.
|
||||
*
|
||||
* Once define this MACRO to be non-zero value, CLOCK_PllGetConfig() function
|
||||
* would cache the recent calulation and accelerate the execution to get the
|
||||
* right settings.
|
||||
*/
|
||||
|
||||
/*! @brief Clock ip name array for ROM. */
|
||||
#define ROM_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Rom, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for SRAM. */
|
||||
#define SRAM_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Sram1, kCLOCK_Sram2, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for FLASH. */
|
||||
#define FLASH_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Flash, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for FMC. */
|
||||
#define FMC_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Fmc, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for INPUTMUX. */
|
||||
#define INPUTMUX_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_InputMux, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for IOCON. */
|
||||
#define IOCON_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Iocon, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for GPIO. */
|
||||
#define GPIO_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Gpio0, kCLOCK_Gpio1, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for PINT. */
|
||||
#define PINT_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Pint, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for GINT. */
|
||||
#define GINT_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Gint,kCLOCK_Gint \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for DMA. */
|
||||
#define DMA_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Dma, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for CRC. */
|
||||
#define CRC_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Crc, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for WWDT. */
|
||||
#define WWDT_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Wwdt, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for RTC. */
|
||||
#define RTC_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Rtc, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for MAILBOX. */
|
||||
#define MAILBOX_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Mailbox, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for ADC. */
|
||||
#define ADC_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Adc0, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for MRT. */
|
||||
#define MRT_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Mrt, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for RIT. */
|
||||
#define RIT_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Rit, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for SCT. */
|
||||
#define SCT_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Sct0, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for FIFO. */
|
||||
#define FIFO_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Fifo, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for UTICK. */
|
||||
#define UTICK_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Utick, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for CT32B. */
|
||||
#define CTIMER_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for USART. */
|
||||
#define USART_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Usart0, kCLOCK_Usart1, kCLOCK_Usart2, kCLOCK_Usart3, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for I2C. */
|
||||
#define I2C_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for SPI. */
|
||||
#define SPI_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Spi0, kCLOCK_Spi1, \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for FRG. */
|
||||
#define FRG_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Frg, \
|
||||
}
|
||||
|
||||
/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
|
||||
/*------------------------------------------------------------------------------
|
||||
clock_ip_name_t definition:
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
#define CLK_GATE_REG_OFFSET_SHIFT 8U
|
||||
#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
|
||||
#define CLK_GATE_BIT_SHIFT_SHIFT 0U
|
||||
#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
|
||||
|
||||
#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
|
||||
((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
|
||||
(((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
|
||||
|
||||
#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
|
||||
#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
|
||||
|
||||
#define AHB_CLK_CTRL0 0
|
||||
#define AHB_CLK_CTRL1 1
|
||||
#define ASYNC_CLK_CTRL0 2
|
||||
|
||||
/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
|
||||
typedef enum _clock_ip_name
|
||||
{
|
||||
/* AHBCLKCTRL0 */
|
||||
kCLOCK_IpInvalid = 0U,
|
||||
kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
|
||||
kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
|
||||
kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
|
||||
kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
|
||||
kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
|
||||
kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
|
||||
kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
|
||||
kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
|
||||
kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
|
||||
kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
|
||||
kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19),
|
||||
kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
|
||||
kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
|
||||
kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
|
||||
kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
|
||||
kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),
|
||||
kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
|
||||
/* AHBCLKCTRL1 */
|
||||
kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
|
||||
kCLOCK_Rit = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1),
|
||||
kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
|
||||
kCLOCK_Fifo = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 9),
|
||||
kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
|
||||
kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
|
||||
kCLOCK_Ct32b3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
|
||||
kCLOCK_Ct32b4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
|
||||
/* ASYNCPRESETCTRL */
|
||||
kCLOCK_Usart0 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 1),
|
||||
kCLOCK_Usart1 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 2),
|
||||
kCLOCK_Usart2 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 3),
|
||||
kCLOCK_Usart3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 4),
|
||||
kCLOCK_I2c0 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 5),
|
||||
kCLOCK_I2c1 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 6),
|
||||
kCLOCK_I2c2 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 7),
|
||||
kCLOCK_Spi0 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 9),
|
||||
kCLOCK_Spi1 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 10),
|
||||
kCLOCK_Ct32b0 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
|
||||
kCLOCK_Ct32b1 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14),
|
||||
kCLOCK_Frg = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 15),
|
||||
} clock_ip_name_t;
|
||||
|
||||
/*! @brief Clock name used to get clock frequency. */
|
||||
typedef enum _clock_name
|
||||
{
|
||||
kCLOCK_MainClk, /*!< Main clock */
|
||||
kCLOCK_CoreSysClk, /*!< Core/system clock */
|
||||
kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
|
||||
kCLOCK_Irc, /*!< Internal IRC */
|
||||
kCLOCK_ExtClk, /*!< External Clock */
|
||||
kCLOCK_PllOut, /*!< PLL Output */
|
||||
kClock_WdtOsc, /*!< Watchdog Oscillator */
|
||||
kCLOCK_FRG, /*!< Frg Clock */
|
||||
kCLOCK_AsyncApbClk, /*!< Async APB clock */
|
||||
kCLOCK_Adc, /*!< ADC clock */
|
||||
kCLOCK_ClockOut, /*!< Clockout clock */
|
||||
kCLOCK_Usart, /*!< USART clock */
|
||||
kCLOCK_Spi, /*!< SPI clock */
|
||||
kCLOCK_I2c, /*!< I2C clock */
|
||||
} clock_name_t;
|
||||
|
||||
/*! @brief Clock Mux Switches
|
||||
* The encoding is as follows each connection identified is 64bits wide
|
||||
* starting from LSB upwards
|
||||
*
|
||||
* [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]*
|
||||
*
|
||||
*/
|
||||
|
||||
#define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8))
|
||||
#define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20))
|
||||
#define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32))
|
||||
#define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44))
|
||||
#define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56))
|
||||
|
||||
#define CM_MAINCLKSELA 0
|
||||
#define CM_MAINCLKSELB 1
|
||||
#define CM_ADCCLKSEL 3
|
||||
#define CM_CLKOUTCLKSELA 5
|
||||
#define CM_CLKOUTCLKSELB 6
|
||||
#define CM_SYSPLLCLKSEL 8
|
||||
|
||||
#define CM_ASYNCAPA 30
|
||||
#define CM_ASYNCAPB 31
|
||||
|
||||
typedef enum _clock_attach_id
|
||||
{
|
||||
kIRC12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0),
|
||||
kCLKIN_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0),
|
||||
kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0),
|
||||
kSYS_PLL_IN_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 1),
|
||||
kSYS_PLL_OUT_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2),
|
||||
kRTC_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3),
|
||||
|
||||
kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCCLKSEL, 0),
|
||||
kSYS_PLL_OUT_to_ADC_CLK = MUX_A(CM_ADCCLKSEL, 1),
|
||||
kIRC12M_to_ADC_CLK = MUX_A(CM_ADCCLKSEL, 2),
|
||||
|
||||
kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0) | MUX_B(CM_CLKOUTCLKSELB, 0),
|
||||
kCLKIN_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1) | MUX_B(CM_CLKOUTCLKSELB, 0),
|
||||
kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2) | MUX_B(CM_CLKOUTCLKSELB, 0),
|
||||
kIRC12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3) | MUX_B(CM_CLKOUTCLKSELB, 0),
|
||||
kRTC_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELB, 3),
|
||||
|
||||
kIRC12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
|
||||
kCLKIN_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
|
||||
kRTC_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
|
||||
|
||||
kIRC12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPA, 0) | MUX_B(CM_ASYNCAPB, 3),
|
||||
kWDT_OSC_to_ASYNC_APB = MUX_A(CM_ASYNCAPA, 1) | MUX_B(CM_ASYNCAPB, 3),
|
||||
kMAIN_CLK_OUT_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
|
||||
kCLKIN_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
|
||||
kSYS_PLL_OUT_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
|
||||
|
||||
kIRC12M_to_USART = MUX_A(CM_ASYNCAPA, 0) | MUX_B(CM_ASYNCAPB, 3),
|
||||
kWDT_OSC_to_USART = MUX_A(CM_ASYNCAPA, 1) | MUX_B(CM_ASYNCAPB, 3),
|
||||
kMAIN_CLK_OUT_to_USART = MUX_A(CM_ASYNCAPB, 0),
|
||||
kCLKIN_to_USART = MUX_A(CM_ASYNCAPB, 1),
|
||||
kSYS_PLL_OUT_to_USART = MUX_A(CM_ASYNCAPB, 2),
|
||||
|
||||
kIRC12M_to_SPI = MUX_A(CM_ASYNCAPA, 0) | MUX_B(CM_ASYNCAPB, 3),
|
||||
kWDT_OSC_to_SPI = MUX_A(CM_ASYNCAPA, 1) | MUX_B(CM_ASYNCAPB, 3),
|
||||
kMAIN_CLK_OUT_to_SPI = MUX_A(CM_ASYNCAPB, 0),
|
||||
kCLKIN_to_SPI = MUX_A(CM_ASYNCAPB, 1),
|
||||
kSYS_PLL_OUT_to_SPI = MUX_A(CM_ASYNCAPB, 2),
|
||||
|
||||
kIRC12M_to_I2C = MUX_A(CM_ASYNCAPA, 0) | MUX_B(CM_ASYNCAPB, 3),
|
||||
kWDT_OSC_to_I2C = MUX_A(CM_ASYNCAPA, 1) | MUX_B(CM_ASYNCAPB, 3),
|
||||
kMAIN_CLK_OUT_to_I2C = MUX_A(CM_ASYNCAPB, 0),
|
||||
kCLKIN_to_I2C = MUX_A(CM_ASYNCAPB, 1),
|
||||
kSYS_PLL_OUT_to_I2C = MUX_A(CM_ASYNCAPB, 2),
|
||||
|
||||
kNONE_to_NONE = 0x80000000U,
|
||||
} clock_attach_id_t;
|
||||
|
||||
/* Clock dividers */
|
||||
typedef enum _clock_div_name
|
||||
{
|
||||
kCLOCK_DivSystickClk = 0,
|
||||
kCLOCK_DivAhbClk = 8,
|
||||
kCLOCK_DivAdcClk = 10,
|
||||
kCLOCK_DivClkOut = 11,
|
||||
} clock_div_name_t;
|
||||
|
||||
/**
|
||||
* @brief FLASH Access time definitions
|
||||
*/
|
||||
typedef enum _clock_flashtim
|
||||
{
|
||||
kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */
|
||||
kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */
|
||||
kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */
|
||||
kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */
|
||||
kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */
|
||||
kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */
|
||||
} clock_flashtim_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! @brief Set Asyc clock divider
|
||||
* @param divided_by_value : Asyc clock divider
|
||||
*/
|
||||
static inline void Clock_SetAsyncClkDiv(uint32_t divided_by_value)
|
||||
{
|
||||
ASYNC_SYSCON->ASYNCCLKDIV = divided_by_value; /* if divided_by_value is 0, clock will be disable*/
|
||||
}
|
||||
|
||||
/* @brief Enable the clock for specific IP.
|
||||
* @param name Which clock to enable, see clock_ip_name_t.
|
||||
*/
|
||||
static inline void CLOCK_EnableClock(clock_ip_name_t clk)
|
||||
{
|
||||
uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
|
||||
if (index < 2)
|
||||
{
|
||||
SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
|
||||
}
|
||||
else
|
||||
{
|
||||
ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
|
||||
}
|
||||
}
|
||||
|
||||
/* @brief Disable the clock for specific IP.
|
||||
* @param name Which clock to enable, see clock_ip_name_t.
|
||||
*/
|
||||
static inline void CLOCK_DisableClock(clock_ip_name_t clk)
|
||||
{
|
||||
uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
|
||||
if (index < 2)
|
||||
{
|
||||
SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
|
||||
}
|
||||
else
|
||||
{
|
||||
ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
|
||||
}
|
||||
}
|
||||
|
||||
/*! @brief Enables and disables PLL bypass mode
|
||||
* @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
|
||||
* @return System PLL output clock rate
|
||||
*/
|
||||
static inline void CLOCK_SetBypassPLL(bool bypass)
|
||||
{
|
||||
if (bypass)
|
||||
{
|
||||
SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
|
||||
}
|
||||
else
|
||||
{
|
||||
SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
|
||||
}
|
||||
}
|
||||
|
||||
/*! @brief Check if PLL is locked or not
|
||||
* @return true if the PLL is locked, false if not locked
|
||||
*/
|
||||
static inline bool CLOCK_IsSystemPLLLocked(void)
|
||||
{
|
||||
return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set FLASH memory access time in clocks
|
||||
* @param clks : Clock cycles for FLASH access
|
||||
* @return Nothing
|
||||
*/
|
||||
static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
|
||||
{
|
||||
uint32_t tmp;
|
||||
tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
|
||||
/* Don't alter lower bits */
|
||||
SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the clock selection muxes.
|
||||
* @param connection : Clock to be configured.
|
||||
* @return Nothing
|
||||
*/
|
||||
void CLOCK_AttachClk(clock_attach_id_t connection);
|
||||
|
||||
/**
|
||||
* @brief Setup peripheral clock dividers.
|
||||
* @param div_name : Clock divider name
|
||||
* @param divided_by_value: Value to be divided
|
||||
@param reset, not used
|
||||
* @return Nothing
|
||||
*/
|
||||
void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
|
||||
|
||||
/**
|
||||
* @brief Set the flash wait states for the input freuqency.
|
||||
* @param iFreq : Input frequency
|
||||
* @return Nothing
|
||||
*/
|
||||
void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
|
||||
|
||||
/*! @brief Return Frequency of Core clock
|
||||
* @return Frequency of Core clock
|
||||
*/
|
||||
uint32_t CLOCK_GetCoreClkFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of Bus clock
|
||||
* @return Frequency of Bus clock
|
||||
*/
|
||||
uint32_t CLOCK_GetBusClkFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of selected clock
|
||||
* @return Frequency of selected clock
|
||||
*/
|
||||
uint32_t CLOCK_GetFreq(clock_name_t clockName);
|
||||
|
||||
/*! @brief Return Frequency of External Clock
|
||||
* @return Frequency of External Clock. If no external clock is used returns 0.
|
||||
*/
|
||||
uint32_t CLOCK_GetExtClkFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of Watchdog Oscillator
|
||||
* @return Frequency of Watchdog Oscillator
|
||||
*/
|
||||
uint32_t CLOCK_GetWdtOscFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of PLL
|
||||
* @return Frequency of PLL
|
||||
*/
|
||||
uint32_t CLOCK_GetPllOutFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of 32kHz osc
|
||||
* @return Frequency of 32kHz osc
|
||||
*/
|
||||
uint32_t CLOCK_GetOsc32KFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of ADC
|
||||
* @return Frequency of ADC
|
||||
*/
|
||||
uint32_t CLOCK_GetAdcClkFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of clock out
|
||||
* @return Frequency of clock out
|
||||
*/
|
||||
uint32_t CLOCK_GetClockOutClkFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of IRC
|
||||
* @return Frequency of IRC
|
||||
*/
|
||||
uint32_t CLOCK_GetIrc12MFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of PLL input
|
||||
* @return Frequency of PLL input
|
||||
*/
|
||||
uint32_t CLOCK_GetPllInFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of Core System
|
||||
* @return Frequency of Core System
|
||||
*/
|
||||
uint32_t CLOCK_GetMainClkFreq(void);
|
||||
|
||||
/*! @brief Return Frequency of Asynchronous APB Clock
|
||||
* @return Frequency of Asynchronous APB Clock Clock
|
||||
*/
|
||||
uint32_t CLOCK_GetAsyncApbClkFreq(void);
|
||||
|
||||
/*! @brief Set Frequency of FRG
|
||||
* @return status of the setting, true: setting successful, false: setting fail
|
||||
*/
|
||||
bool CLOCK_SetFRGClock(uint32_t freq);
|
||||
|
||||
/*! @brief Return System PLL input clock rate
|
||||
* @return System PLL input clock rate
|
||||
*/
|
||||
uint32_t CLOCK_GetSystemPLLInClockRate(void);
|
||||
|
||||
/*! @brief Return System PLL output clock rate
|
||||
* @param recompute : Forces a PLL rate recomputation if true
|
||||
* @return System PLL output clock rate
|
||||
* @note The PLL rate is cached in the driver in a variable as
|
||||
* the rate computation function can take some time to perform. It
|
||||
* is recommended to use 'false' with the 'recompute' parameter.
|
||||
*/
|
||||
uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
|
||||
|
||||
/*! @brief Store the current PLL rate
|
||||
* @param rate: Current rate of the PLL
|
||||
* @return Nothing
|
||||
**/
|
||||
void CLOCK_SetStoredPLLClockRate(uint32_t rate);
|
||||
|
||||
/*! @brief PLL configuration structure flags for 'flags' field
|
||||
* These flags control how the PLL configuration function sets up the PLL setup structure.
|
||||
*
|
||||
* When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
|
||||
* configuration structure must be assigned with the expected PLL frequency. If the
|
||||
* PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
|
||||
* function and the driver will determine the PLL rate from the currently selected
|
||||
* PLL source. This flag might be used to configure the PLL input clock more accurately
|
||||
* when using the WDT oscillator or a more dyanmic CLKIN source.
|
||||
*
|
||||
* When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
|
||||
* automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
|
||||
* are not used
|
||||
*/
|
||||
#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */
|
||||
#define PLL_CONFIGFLAG_FORCENOFRACT \
|
||||
(1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or \
|
||||
\ \ \
|
||||
\ \ \ \ \
|
||||
\ \ \ \ \ \ \ \
|
||||
SS hardware */
|
||||
|
||||
/*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
|
||||
* See (MF) field in the SYSPLLSSCTRL1 register in the UM.
|
||||
*/
|
||||
typedef enum _ss_progmodfm
|
||||
{
|
||||
kSS_MF_512 = (0U << 20U), /*!< Nss = 512 (fm ?= 3.9 - 7.8 kHz) */
|
||||
kSS_MF_384 = (1U << 20U), /*!< Nss = 384 (fm ?= 5.2 - 10.4 kHz) */
|
||||
kSS_MF_256 = (2U << 20U), /*!< Nss = 256 (fm ?= 7.8 - 15.6 kHz) */
|
||||
kSS_MF_128 = (3U << 20U), /*!< Nss = 128 (fm ?= 15.6 - 31.3 kHz) */
|
||||
kSS_MF_64 = (4U << 20U), /*!< Nss = 64 (fm ?= 32.3 - 64.5 kHz) */
|
||||
kSS_MF_32 = (5U << 20U), /*!< Nss = 32 (fm ?= 62.5- 125 kHz) */
|
||||
kSS_MF_24 = (6U << 20U), /*!< Nss = 24 (fm ?= 83.3- 166.6 kHz) */
|
||||
kSS_MF_16 = (7U << 20U) /*!< Nss = 16 (fm ?= 125- 250 kHz) */
|
||||
} ss_progmodfm_t;
|
||||
|
||||
/*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
|
||||
* See (MR) field in the SYSPLLSSCTRL1 register in the UM.
|
||||
*/
|
||||
typedef enum _ss_progmoddp
|
||||
{
|
||||
kSS_MR_K0 = (0U << 23U), /*!< k = 0 (no spread spectrum) */
|
||||
kSS_MR_K1 = (1U << 23U), /*!< k = 1 */
|
||||
kSS_MR_K1_5 = (2U << 23U), /*!< k = 1.5 */
|
||||
kSS_MR_K2 = (3U << 23U), /*!< k = 2 */
|
||||
kSS_MR_K3 = (4U << 23U), /*!< k = 3 */
|
||||
kSS_MR_K4 = (5U << 23U), /*!< k = 4 */
|
||||
kSS_MR_K6 = (6U << 23U), /*!< k = 6 */
|
||||
kSS_MR_K8 = (7U << 23U) /*!< k = 8 */
|
||||
} ss_progmoddp_t;
|
||||
|
||||
/*! @brief PLL Spread Spectrum (SS) Modulation waveform control
|
||||
* See (MC) field in the SYSPLLSSCTRL1 register in the UM.<br>
|
||||
* Compensation for low pass filtering of the PLL to get a triangular
|
||||
* modulation at the output of the PLL, giving a flat frequency spectrum.
|
||||
*/
|
||||
typedef enum _ss_modwvctrl
|
||||
{
|
||||
kSS_MC_NOC = (0U << 26U), /*!< no compensation */
|
||||
kSS_MC_RECC = (2U << 26U), /*!< recommended setting */
|
||||
kSS_MC_MAXC = (3U << 26U), /*!< max. compensation */
|
||||
} ss_modwvctrl_t;
|
||||
|
||||
/*! @brief PLL configuration structure
|
||||
*
|
||||
* This structure can be used to configure the settings for a PLL
|
||||
* setup structure. Fill in the desired configuration for the PLL
|
||||
* and call the PLL setup function to fill in a PLL setup structure.
|
||||
*/
|
||||
typedef struct _pll_config
|
||||
{
|
||||
uint32_t desiredRate; /*!< Desired PLL rate in Hz */
|
||||
uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
|
||||
uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
|
||||
ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
|
||||
PLL_CONFIGFLAG_FORCENOFRACT flag */
|
||||
ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
|
||||
PLL_CONFIGFLAG_FORCENOFRACT flag */
|
||||
ss_modwvctrl_t
|
||||
ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
|
||||
bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
|
||||
PLL_CONFIGFLAG_FORCENOFRACT flag */
|
||||
|
||||
} pll_config_t;
|
||||
|
||||
/*! @brief PLL setup structure flags for 'flags' field
|
||||
* These flags control how the PLL setup function sets up the PLL
|
||||
*/
|
||||
#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */
|
||||
#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
|
||||
#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */
|
||||
#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */
|
||||
|
||||
/*! @brief PLL setup structure
|
||||
* This structure can be used to pre-build a PLL setup configuration
|
||||
* at run-time and quickly set the PLL to the configuration. It can be
|
||||
* populated with the PLL setup function. If powering up or waiting
|
||||
* for PLL lock, the PLL input clock source should be configured prior
|
||||
* to PLL setup.
|
||||
*/
|
||||
typedef struct _pll_setup
|
||||
{
|
||||
uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */
|
||||
uint32_t syspllndec; /*!< PLL NDEC register SYSPLLNDEC */
|
||||
uint32_t syspllpdec; /*!< PLL PDEC register SYSPLLPDEC */
|
||||
uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */
|
||||
uint32_t pllRate; /*!< Acutal PLL rate */
|
||||
uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
|
||||
} pll_setup_t;
|
||||
|
||||
/*! @brief PLL status definitions
|
||||
*/
|
||||
typedef enum _pll_error
|
||||
{
|
||||
kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
|
||||
kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
|
||||
kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
|
||||
kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
|
||||
kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
|
||||
kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */
|
||||
} pll_error_t;
|
||||
|
||||
/*! @brief Return System PLL output clock rate from setup structure
|
||||
* @param pSetup : Pointer to a PLL setup structure
|
||||
* @return System PLL output clock rate calculated from the setup structure
|
||||
*/
|
||||
uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
|
||||
|
||||
/*! @brief Set PLL output based on the passed PLL setup data
|
||||
* @param pControl : Pointer to populated PLL control structure to generate setup with
|
||||
* @param pSetup : Pointer to PLL setup structure to be filled
|
||||
* @return PLL_ERROR_SUCCESS on success, or PLL setup error code
|
||||
* @note Actual frequency for setup may vary from the desired frequency based on the
|
||||
* accuracy of input clocks, rounding, non-fractional PLL mode, etc.
|
||||
*/
|
||||
pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
|
||||
|
||||
/*! @brief Set PLL output from PLL setup structure (precise frequency)
|
||||
* @param pSetup : Pointer to populated PLL setup structure
|
||||
* @param flagcfg : Flag configuration for PLL config structure
|
||||
* @return PLL_ERROR_SUCCESS on success, or PLL setup error code
|
||||
* @note This function will power off the PLL, setup the PLL with the
|
||||
* new setup data, and then optionally powerup the PLL, wait for PLL lock,
|
||||
* and adjust system voltages to the new PLL rate. The function will not
|
||||
* alter any source clocks (ie, main systen clock) that may use the PLL,
|
||||
* so these should be setup prior to and after exiting the function.
|
||||
*/
|
||||
pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
|
||||
|
||||
/*! @brief Set PLL output from PLL setup structure (precise frequency)
|
||||
* @param pSetup : Pointer to populated PLL setup structure
|
||||
* @return kStatus_PLL_Success on success, or PLL setup error code
|
||||
* @note This function will power off the PLL, setup the PLL with the
|
||||
* new setup data, and then optionally powerup the PLL, wait for PLL lock,
|
||||
* and adjust system voltages to the new PLL rate. The function will not
|
||||
* alter any source clocks (ie, main systen clock) that may use the PLL,
|
||||
* so these should be setup prior to and after exiting the function.
|
||||
*/
|
||||
pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
|
||||
|
||||
/*! @brief Set PLL output based on the multiplier and input frequency
|
||||
* @param multiply_by : multiplier
|
||||
* @param input_freq : Clock input frequency of the PLL
|
||||
* @return Nothing
|
||||
* @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
|
||||
* function does not disable or enable PLL power, wait for PLL lock,
|
||||
* or adjust system voltages. These must be done in the application.
|
||||
* The function will not alter any source clocks (ie, main systen clock)
|
||||
* that may use the PLL, so these should be setup prior to and after
|
||||
* exiting the function.
|
||||
*/
|
||||
void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_CLOCK_H_ */
|
||||
122
Living_SDK/platform/mcu/lpc54102/drivers/fsl_common.c
Normal file
122
Living_SDK/platform/mcu/lpc54102/drivers/fsl_common.c
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
#ifndef __GIC_PRIO_BITS
|
||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
|
||||
{
|
||||
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
|
||||
#if defined(__CC_ARM)
|
||||
extern uint32_t Image$$VECTOR_ROM$$Base[];
|
||||
extern uint32_t Image$$VECTOR_RAM$$Base[];
|
||||
extern uint32_t Image$$RW_m_data$$Base[];
|
||||
|
||||
#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
|
||||
#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
|
||||
#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
|
||||
#elif defined(__ICCARM__)
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
#elif defined(__GNUC__)
|
||||
extern uint32_t __VECTOR_TABLE[];
|
||||
extern uint32_t __VECTOR_RAM[];
|
||||
extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
|
||||
uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
|
||||
#endif /* defined(__CC_ARM) */
|
||||
uint32_t n;
|
||||
uint32_t ret;
|
||||
uint32_t irqMaskValue;
|
||||
|
||||
irqMaskValue = DisableGlobalIRQ();
|
||||
if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
|
||||
{
|
||||
/* Copy the vector table from ROM to RAM */
|
||||
for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
|
||||
{
|
||||
__VECTOR_RAM[n] = __VECTOR_TABLE[n];
|
||||
}
|
||||
/* Point the VTOR to the position of vector table */
|
||||
SCB->VTOR = (uint32_t)__VECTOR_RAM;
|
||||
}
|
||||
|
||||
ret = __VECTOR_RAM[irq + 16];
|
||||
/* make sure the __VECTOR_RAM is noncachable */
|
||||
__VECTOR_RAM[irq + 16] = irqHandler;
|
||||
|
||||
EnableGlobalIRQ(irqMaskValue);
|
||||
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||
#endif /* __GIC_PRIO_BITS. */
|
||||
|
||||
#ifndef QN908XC_SERIES
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
SYSCON->STARTERSET[index] = 1u << intNumber;
|
||||
EnableIRQ(interrupt); /* also enable interrupt at NVIC */
|
||||
}
|
||||
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
uint32_t intNumber = (uint32_t)interrupt;
|
||||
while (intNumber >= 32u)
|
||||
{
|
||||
index++;
|
||||
intNumber -= 32u;
|
||||
}
|
||||
|
||||
DisableIRQ(interrupt); /* also disable interrupt at NVIC */
|
||||
SYSCON->STARTERCLR[index] = 1u << intNumber;
|
||||
}
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
#endif /* QN908XC_SERIES */
|
||||
512
Living_SDK/platform/mcu/lpc54102/drivers/fsl_common.h
Normal file
512
Living_SDK/platform/mcu/lpc54102/drivers/fsl_common.h
Normal file
|
|
@ -0,0 +1,512 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_COMMON_H_
|
||||
#define _FSL_COMMON_H_
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#include <stddef.h>
|
||||
#endif
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup ksdk_common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Construct a status code value from a group and code number. */
|
||||
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
|
||||
|
||||
/*! @brief Construct the version number for drivers. */
|
||||
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief common driver version 2.0.0. */
|
||||
#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/* Debug console type definition. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console base on LPUART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console base on LPSCI. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
|
||||
#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
|
||||
|
||||
/*! @brief Status group numbers. */
|
||||
enum _status_groups
|
||||
{
|
||||
kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */
|
||||
kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */
|
||||
kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */
|
||||
kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */
|
||||
kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */
|
||||
kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */
|
||||
kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */
|
||||
kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */
|
||||
kStatusGroup_UART = 10, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */
|
||||
kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */
|
||||
kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */
|
||||
kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/
|
||||
kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/
|
||||
kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/
|
||||
kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */
|
||||
kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */
|
||||
kStatusGroup_SAI = 19, /*!< Group number for SAI status code */
|
||||
kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */
|
||||
kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */
|
||||
kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */
|
||||
kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */
|
||||
kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */
|
||||
kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */
|
||||
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
|
||||
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
|
||||
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
|
||||
kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
|
||||
kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
|
||||
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
|
||||
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
|
||||
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
|
||||
kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */
|
||||
kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */
|
||||
kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */
|
||||
kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */
|
||||
kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */
|
||||
kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */
|
||||
kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */
|
||||
kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */
|
||||
kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */
|
||||
kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */
|
||||
kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */
|
||||
kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */
|
||||
kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */
|
||||
kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */
|
||||
kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/
|
||||
kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */
|
||||
kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */
|
||||
kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */
|
||||
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
|
||||
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
|
||||
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
|
||||
kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
|
||||
kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
|
||||
kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
|
||||
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
|
||||
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
|
||||
kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
|
||||
kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */
|
||||
kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
|
||||
kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
|
||||
kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
|
||||
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
|
||||
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
|
||||
kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
|
||||
kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
|
||||
};
|
||||
|
||||
/*! @brief Generic status return codes. */
|
||||
enum _generic_status
|
||||
{
|
||||
kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
|
||||
kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
|
||||
kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
|
||||
kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
|
||||
kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
|
||||
kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
|
||||
kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
|
||||
};
|
||||
|
||||
/*! @brief Type used for all status and error return values. */
|
||||
typedef int32_t status_t;
|
||||
|
||||
/*
|
||||
* The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
|
||||
* defined in previous of this file.
|
||||
*/
|
||||
#include "fsl_clock.h"
|
||||
|
||||
/*
|
||||
* Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
|
||||
*/
|
||||
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
||||
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
||||
#include "fsl_reset.h"
|
||||
#endif
|
||||
|
||||
/*! @name Min/max macros */
|
||||
/* @{ */
|
||||
#if !defined(MIN)
|
||||
#define MIN(a, b) ((a) < (b) ? (a) : (b))
|
||||
#endif
|
||||
|
||||
#if !defined(MAX)
|
||||
#define MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @brief Computes the number of elements in an array. */
|
||||
#if !defined(ARRAY_SIZE)
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#endif
|
||||
|
||||
/*! @name UINT16_MAX/UINT32_MAX value */
|
||||
/* @{ */
|
||||
#if !defined(UINT16_MAX)
|
||||
#define UINT16_MAX ((uint16_t)-1)
|
||||
#endif
|
||||
|
||||
#if !defined(UINT32_MAX)
|
||||
#define UINT32_MAX ((uint32_t)-1)
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*! @name Timer utilities */
|
||||
/* @{ */
|
||||
/*! Macro to convert a microsecond period to raw count value */
|
||||
#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U)
|
||||
/*! Macro to convert a raw count value to microsecond */
|
||||
#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
|
||||
|
||||
/*! Macro to convert a millisecond period to raw count value */
|
||||
#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
|
||||
/*! Macro to convert a raw count value to millisecond */
|
||||
#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
|
||||
/* @} */
|
||||
|
||||
/*! @name Alignment variable definition macros */
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
/**
|
||||
* Workaround to disable MISRA C message suppress warnings for IAR compiler.
|
||||
* http://supp.iar.com/Support/?note=24725
|
||||
*/
|
||||
_Pragma("diag_suppress=Pm120")
|
||||
#define SDK_PRAGMA(x) _Pragma(#x)
|
||||
_Pragma("diag_error=Pm120")
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
#elif defined(__ARMCC_VERSION)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) __align(alignbytes) var
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) __align(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) __align(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
|
||||
#endif
|
||||
#elif defined(__GNUC__)
|
||||
/*! Macro to define a variable with alignbytes alignment */
|
||||
#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
/*! Macro to define a variable with L1 d-cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
|
||||
#endif
|
||||
/*! Macro to define a variable with L2 cache line size alignment */
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
|
||||
#endif
|
||||
#else
|
||||
#error Toolchain not supported
|
||||
#define SDK_ALIGN(var, alignbytes) var
|
||||
#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
|
||||
#define SDK_L1DCACHE_ALIGN(var) var
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
|
||||
#define SDK_L2CACHE_ALIGN(var) var
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*! Macro to change a value to a given size aligned value */
|
||||
#define SDK_SIZEALIGN(var, alignbytes) \
|
||||
((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
|
||||
/* @} */
|
||||
|
||||
/*! @name Non-cacheable region definition macros */
|
||||
/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
|
||||
* "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
|
||||
* please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
|
||||
* will be initialized to zero in system startup.
|
||||
*/
|
||||
/* @{ */
|
||||
#if (defined(__ICCARM__))
|
||||
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
|
||||
#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
|
||||
#endif
|
||||
#elif(defined(__ARMCC_VERSION))
|
||||
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable"), zero_init)) __align(alignbytes) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable.init"))) __align(alignbytes) var
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __align(alignbytes) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __align(alignbytes) var
|
||||
#endif
|
||||
#elif(defined(__GNUC__))
|
||||
/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
|
||||
* in your projects to make sure the non-cacheable section variables will be initialized in system startup.
|
||||
*/
|
||||
#if defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
|
||||
#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
|
||||
__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
|
||||
#else
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
|
||||
#endif
|
||||
#else
|
||||
#error Toolchain not supported.
|
||||
#define AT_NONCACHEABLE_SECTION(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
|
||||
#define AT_NONCACHEABLE_SECTION_INIT(var) var
|
||||
#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
|
||||
#endif
|
||||
/* @} */
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Enable specific interrupt.
|
||||
*
|
||||
* Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt enabled successfully
|
||||
* @retval kStatus_Fail Failed to enable the interrupt
|
||||
*/
|
||||
static inline status_t EnableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_EnableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_EnableIRQ(interrupt);
|
||||
#endif
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt.
|
||||
*
|
||||
* Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
|
||||
* levels. For example, there are NVIC and intmux. Here the interrupts connected
|
||||
* to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
|
||||
* The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
|
||||
* to NVIC first then routed to core.
|
||||
*
|
||||
* This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
|
||||
* is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
* @retval kStatus_Success Interrupt disabled successfully
|
||||
* @retval kStatus_Fail Failed to disable the interrupt
|
||||
*/
|
||||
static inline status_t DisableIRQ(IRQn_Type interrupt)
|
||||
{
|
||||
if (NotAvail_IRQn == interrupt)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
|
||||
if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__GIC_PRIO_BITS)
|
||||
GIC_DisableIRQ(interrupt);
|
||||
#else
|
||||
NVIC_DisableIRQ(interrupt);
|
||||
#endif
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable the global IRQ
|
||||
*
|
||||
* Disable the global interrupt and return the current primask register. User is required to provided the primask
|
||||
* register for the EnableGlobalIRQ().
|
||||
*
|
||||
* @return Current primask value.
|
||||
*/
|
||||
static inline uint32_t DisableGlobalIRQ(void)
|
||||
{
|
||||
#if defined(CPSR_I_Msk)
|
||||
uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
|
||||
|
||||
__disable_irq();
|
||||
|
||||
return cpsr;
|
||||
#else
|
||||
uint32_t regPrimask = __get_PRIMASK();
|
||||
|
||||
__disable_irq();
|
||||
|
||||
return regPrimask;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enaable the global IRQ
|
||||
*
|
||||
* Set the primask register with the provided primask value but not just enable the primask. The idea is for the
|
||||
* convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
|
||||
* use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
|
||||
*
|
||||
* @param primask value of primask register to be restored. The primask value is supposed to be provided by the
|
||||
* DisableGlobalIRQ().
|
||||
*/
|
||||
static inline void EnableGlobalIRQ(uint32_t primask)
|
||||
{
|
||||
#if defined(CPSR_I_Msk)
|
||||
__set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
|
||||
#else
|
||||
__set_PRIMASK(primask);
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(ENABLE_RAM_VECTOR_TABLE)
|
||||
/*!
|
||||
* @brief install IRQ handler
|
||||
*
|
||||
* @param irq IRQ number
|
||||
* @param irqHandler IRQ handler address
|
||||
* @return The old IRQ handler address
|
||||
*/
|
||||
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
|
||||
#endif /* ENABLE_RAM_VECTOR_TABLE. */
|
||||
|
||||
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
|
||||
/*!
|
||||
* @brief Enable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Enable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void EnableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
|
||||
/*!
|
||||
* @brief Disable specific interrupt for wake-up from deep-sleep mode.
|
||||
*
|
||||
* Disable the interrupt for wake-up from deep sleep mode.
|
||||
* Some interrupts are typically used in sleep mode only and will not occur during
|
||||
* deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
|
||||
* those clocks (significantly increasing power consumption in the reduced power mode),
|
||||
* making these wake-ups possible.
|
||||
*
|
||||
* @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
|
||||
*
|
||||
* @param interrupt The IRQ number.
|
||||
*/
|
||||
void DisableDeepSleepIRQ(IRQn_Type interrupt);
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_COMMON_H_ */
|
||||
136
Living_SDK/platform/mcu/lpc54102/drivers/fsl_crc.c
Normal file
136
Living_SDK/platform/mcu/lpc54102/drivers/fsl_crc.c
Normal file
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include "fsl_crc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT) && CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT
|
||||
/* @brief Default user configuration structure for CRC-CCITT */
|
||||
#define CRC_DRIVER_DEFAULT_POLYNOMIAL kCRC_Polynomial_CRC_CCITT
|
||||
/*< CRC-CCIT polynomial x^16 + x^12 + x^5 + x^0 */
|
||||
#define CRC_DRIVER_DEFAULT_REVERSE_IN false
|
||||
/*< Default is no bit reverse */
|
||||
#define CRC_DRIVER_DEFAULT_COMPLEMENT_IN false
|
||||
/*< Default is without complement of written data */
|
||||
#define CRC_DRIVER_DEFAULT_REVERSE_OUT false
|
||||
/*< Default is no bit reverse */
|
||||
#define CRC_DRIVER_DEFAULT_COMPLEMENT_OUT false
|
||||
/*< Default is without complement of CRC data register read data */
|
||||
#define CRC_DRIVER_DEFAULT_SEED 0xFFFFU
|
||||
/*< Default initial checksum */
|
||||
#endif /* CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT */
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
void CRC_Init(CRC_Type *base, const crc_config_t *config)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* enable clock to CRC */
|
||||
CLOCK_EnableClock(kCLOCK_Crc);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* configure CRC module and write the seed */
|
||||
base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
|
||||
CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
|
||||
CRC_MODE_CMPL_SUM(config->complementOut);
|
||||
base->SEED = config->seed;
|
||||
}
|
||||
|
||||
void CRC_GetDefaultConfig(crc_config_t *config)
|
||||
{
|
||||
static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN,
|
||||
CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT,
|
||||
CRC_DRIVER_DEFAULT_COMPLEMENT_OUT, CRC_DRIVER_DEFAULT_SEED};
|
||||
|
||||
*config = default_config;
|
||||
}
|
||||
|
||||
void CRC_Reset(CRC_Type *base)
|
||||
{
|
||||
crc_config_t config;
|
||||
CRC_GetDefaultConfig(&config);
|
||||
CRC_Init(base, &config);
|
||||
}
|
||||
|
||||
void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
|
||||
{
|
||||
/* extract CRC mode settings */
|
||||
uint32_t mode = base->MODE;
|
||||
config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT);
|
||||
config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
|
||||
config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
|
||||
config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
|
||||
config->complementOut = (bool)(mode & CRC_MODE_CMPL_SUM_MASK);
|
||||
|
||||
/* reset CRC sum bit reverse and 1's complement setting, so its value can be used as a seed */
|
||||
base->MODE = mode & ~((1U << CRC_MODE_BIT_RVS_SUM_SHIFT) | (1U << CRC_MODE_CMPL_SUM_SHIFT));
|
||||
|
||||
/* now we can obtain intermediate raw CRC sum value */
|
||||
config->seed = base->SUM;
|
||||
|
||||
/* restore original CRC sum bit reverse and 1's complement setting */
|
||||
base->MODE = mode;
|
||||
}
|
||||
|
||||
void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
|
||||
{
|
||||
const uint32_t *data32;
|
||||
|
||||
/* 8-bit reads and writes till source address is aligned 4 bytes */
|
||||
while ((dataSize) && ((uint32_t)data & 3U))
|
||||
{
|
||||
*((__O uint8_t *)&(base->WR_DATA)) = *data;
|
||||
data++;
|
||||
dataSize--;
|
||||
}
|
||||
|
||||
/* use 32-bit reads and writes as long as possible */
|
||||
data32 = (const uint32_t *)data;
|
||||
while (dataSize >= sizeof(uint32_t))
|
||||
{
|
||||
*((__O uint32_t *)&(base->WR_DATA)) = *data32;
|
||||
data32++;
|
||||
dataSize -= sizeof(uint32_t);
|
||||
}
|
||||
|
||||
data = (const uint8_t *)data32;
|
||||
|
||||
/* 8-bit reads and writes till end of data buffer */
|
||||
while (dataSize)
|
||||
{
|
||||
*((__O uint8_t *)&(base->WR_DATA)) = *data;
|
||||
data++;
|
||||
dataSize--;
|
||||
}
|
||||
}
|
||||
203
Living_SDK/platform/mcu/lpc54102/drivers/fsl_crc.h
Normal file
203
Living_SDK/platform/mcu/lpc54102/drivers/fsl_crc.h
Normal file
|
|
@ -0,0 +1,203 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_CRC_H_
|
||||
#define _FSL_CRC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup crc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief CRC driver version. Version 2.0.1.
|
||||
*
|
||||
* Current version: 2.0.1
|
||||
*
|
||||
* Change log:
|
||||
* - Version 2.0.0
|
||||
* - initial version
|
||||
* - Version 2.0.1
|
||||
* - add explicit type cast when writing to WR_DATA
|
||||
*/
|
||||
#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
#ifndef CRC_DRIVER_CUSTOM_DEFAULTS
|
||||
/*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Uses CRC-16/CCITT-FALSE as default. */
|
||||
#define CRC_DRIVER_USE_CRC16_CCITT_FALSE_AS_DEFAULT 1
|
||||
#endif
|
||||
|
||||
/*! @brief CRC polynomials to use. */
|
||||
typedef enum _crc_polynomial
|
||||
{
|
||||
kCRC_Polynomial_CRC_CCITT = 0U, /*!< x^16+x^12+x^5+1 */
|
||||
kCRC_Polynomial_CRC_16 = 1U, /*!< x^16+x^15+x^2+1 */
|
||||
kCRC_Polynomial_CRC_32 = 2U /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 */
|
||||
} crc_polynomial_t;
|
||||
|
||||
/*!
|
||||
* @brief CRC protocol configuration.
|
||||
*
|
||||
* This structure holds the configuration for the CRC protocol.
|
||||
*
|
||||
*/
|
||||
typedef struct _crc_config
|
||||
{
|
||||
crc_polynomial_t polynomial; /*!< CRC polynomial. */
|
||||
bool reverseIn; /*!< Reverse bits on input. */
|
||||
bool complementIn; /*!< Perform 1's complement on input. */
|
||||
bool reverseOut; /*!< Reverse bits on output. */
|
||||
bool complementOut; /*!< Perform 1's complement on output. */
|
||||
uint32_t seed; /*!< Starting checksum value. */
|
||||
} crc_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Enables and configures the CRC peripheral module.
|
||||
*
|
||||
* This functions enables the CRC peripheral clock in the LPC SYSCON block.
|
||||
* It also configures the CRC engine and starts checksum computation by writing the seed.
|
||||
*
|
||||
* @param base CRC peripheral address.
|
||||
* @param config CRC module configuration structure.
|
||||
*/
|
||||
void CRC_Init(CRC_Type *base, const crc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Disables the CRC peripheral module.
|
||||
*
|
||||
* This functions disables the CRC peripheral clock in the LPC SYSCON block.
|
||||
*
|
||||
* @param base CRC peripheral address.
|
||||
*/
|
||||
static inline void CRC_Deinit(CRC_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* disable clock to CRC */
|
||||
CLOCK_DisableClock(kCLOCK_Crc);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief resets CRC peripheral module.
|
||||
*
|
||||
* @param base CRC peripheral address.
|
||||
*/
|
||||
void CRC_Reset(CRC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Loads default values to CRC protocol configuration structure.
|
||||
*
|
||||
* Loads default values to CRC protocol configuration structure. The default values are:
|
||||
* @code
|
||||
* config->polynomial = kCRC_Polynomial_CRC_CCITT;
|
||||
* config->reverseIn = false;
|
||||
* config->complementIn = false;
|
||||
* config->reverseOut = false;
|
||||
* config->complementOut = false;
|
||||
* config->seed = 0xFFFFU;
|
||||
* @endcode
|
||||
*
|
||||
* @param config CRC protocol configuration structure
|
||||
*/
|
||||
void CRC_GetDefaultConfig(crc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
|
||||
*
|
||||
* The values, including seed, can be used to resume CRC calculation later.
|
||||
|
||||
* @param base CRC peripheral address.
|
||||
* @param config CRC protocol configuration structure
|
||||
*/
|
||||
void CRC_GetConfig(CRC_Type *base, crc_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Writes data to the CRC module.
|
||||
*
|
||||
* Writes input data buffer bytes to CRC data register.
|
||||
*
|
||||
* @param base CRC peripheral address.
|
||||
* @param data Input data stream, MSByte in data[0].
|
||||
* @param dataSize Size of the input data buffer in bytes.
|
||||
*/
|
||||
void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize);
|
||||
|
||||
/*!
|
||||
* @brief Reads 32-bit checksum from the CRC module.
|
||||
*
|
||||
* Reads CRC data register.
|
||||
*
|
||||
* @param base CRC peripheral address.
|
||||
* @return final 32-bit checksum, after configured bit reverse and complement operations.
|
||||
*/
|
||||
static inline uint32_t CRC_Get32bitResult(CRC_Type *base)
|
||||
{
|
||||
return base->SUM;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads 16-bit checksum from the CRC module.
|
||||
*
|
||||
* Reads CRC data register.
|
||||
*
|
||||
* @param base CRC peripheral address.
|
||||
* @return final 16-bit checksum, after configured bit reverse and complement operations.
|
||||
*/
|
||||
static inline uint16_t CRC_Get16bitResult(CRC_Type *base)
|
||||
{
|
||||
return (uint16_t)base->SUM;
|
||||
}
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
*@}
|
||||
*/
|
||||
|
||||
#endif /* _FSL_CRC_H_ */
|
||||
386
Living_SDK/platform/mcu/lpc54102/drivers/fsl_ctimer.c
Normal file
386
Living_SDK/platform/mcu/lpc54102/drivers/fsl_ctimer.c
Normal file
|
|
@ -0,0 +1,386 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_ctimer.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Gets the instance from the base address
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
*
|
||||
* @return The Timer instance
|
||||
*/
|
||||
static uint32_t CTIMER_GetInstance(CTIMER_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to Timer bases for each instance. */
|
||||
static CTIMER_Type *const s_ctimerBases[] = CTIMER_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to Timer clocks for each instance. */
|
||||
static const clock_ip_name_t s_ctimerClocks[] = CTIMER_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*! @brief Pointers to Timer resets for each instance. */
|
||||
static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS;
|
||||
|
||||
/*! @brief Pointers real ISRs installed by drivers for each instance. */
|
||||
static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0};
|
||||
|
||||
/*! @brief Callback type installed by drivers for each instance. */
|
||||
static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback};
|
||||
|
||||
/*! @brief Array to map timer instance to IRQ number. */
|
||||
static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t CTIMER_GetInstance(CTIMER_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
uint32_t ctimerArrayCount = (sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0]));
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ctimerArrayCount; instance++)
|
||||
{
|
||||
if (s_ctimerBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ctimerArrayCount);
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the timer clock*/
|
||||
CLOCK_EnableClock(s_ctimerClocks[CTIMER_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Reset the module */
|
||||
RESET_PeripheralReset(s_ctimerResets[CTIMER_GetInstance(base)]);
|
||||
|
||||
/* Setup the cimer mode and count select */
|
||||
base->CTCR = CTIMER_CTCR_CTMODE(config->mode) | CTIMER_CTCR_CINSEL(config->input);
|
||||
|
||||
/* Setup the timer prescale value */
|
||||
base->PR = CTIMER_PR_PRVAL(config->prescale);
|
||||
}
|
||||
|
||||
void CTIMER_Deinit(CTIMER_Type *base)
|
||||
{
|
||||
uint32_t index = CTIMER_GetInstance(base);
|
||||
/* Stop the timer */
|
||||
base->TCR &= ~CTIMER_TCR_CEN_MASK;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the timer clock*/
|
||||
CLOCK_DisableClock(s_ctimerClocks[index]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Disable IRQ at NVIC Level */
|
||||
DisableIRQ(s_ctimerIRQ[index]);
|
||||
}
|
||||
|
||||
void CTIMER_GetDefaultConfig(ctimer_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
/* Run as a timer */
|
||||
config->mode = kCTIMER_TimerMode;
|
||||
/* This field is ignored when mode is timer */
|
||||
config->input = kCTIMER_Capture_0;
|
||||
/* Timer counter is incremented on every APB bus clock */
|
||||
config->prescale = 0;
|
||||
}
|
||||
|
||||
status_t CTIMER_SetupPwm(CTIMER_Type *base,
|
||||
ctimer_match_t matchChannel,
|
||||
uint8_t dutyCyclePercent,
|
||||
uint32_t pwmFreq_Hz,
|
||||
uint32_t srcClock_Hz,
|
||||
bool enableInt)
|
||||
{
|
||||
assert(pwmFreq_Hz > 0);
|
||||
|
||||
uint32_t reg;
|
||||
uint32_t period, pulsePeriod = 0;
|
||||
uint32_t timerClock = srcClock_Hz / (base->PR + 1);
|
||||
uint32_t index = CTIMER_GetInstance(base);
|
||||
|
||||
if (matchChannel == kCTIMER_Match_3)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Enable PWM mode on the channel */
|
||||
base->PWMC |= (1U << matchChannel);
|
||||
|
||||
/* Clear the stop, reset and interrupt bits for this channel */
|
||||
reg = base->MCR;
|
||||
reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
|
||||
|
||||
/* If call back function is valid then enable match interrupt for the channel */
|
||||
if (enableInt)
|
||||
{
|
||||
reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
|
||||
}
|
||||
|
||||
/* Reset the counter when match on channel 3 */
|
||||
reg |= CTIMER_MCR_MR3R_MASK;
|
||||
|
||||
base->MCR = reg;
|
||||
|
||||
/* Calculate PWM period match value */
|
||||
period = (timerClock / pwmFreq_Hz) - 1;
|
||||
|
||||
/* Calculate pulse width match value */
|
||||
if (dutyCyclePercent == 0)
|
||||
{
|
||||
pulsePeriod = period + 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
|
||||
}
|
||||
|
||||
/* Match on channel 3 will define the PWM period */
|
||||
base->MR[kCTIMER_Match_3] = period;
|
||||
|
||||
/* This will define the PWM pulse period */
|
||||
base->MR[matchChannel] = pulsePeriod;
|
||||
/* Clear status flags */
|
||||
CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
|
||||
/* If call back function is valid then enable interrupt and update the call back function */
|
||||
if (enableInt)
|
||||
{
|
||||
EnableIRQ(s_ctimerIRQ[index]);
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent)
|
||||
{
|
||||
uint32_t pulsePeriod = 0, period;
|
||||
|
||||
/* Match channel 3 defines the PWM period */
|
||||
period = base->MR[kCTIMER_Match_3];
|
||||
|
||||
/* Calculate pulse width match value */
|
||||
pulsePeriod = (period * dutyCyclePercent) / 100;
|
||||
|
||||
/* For 0% dutycyle, make pulse period greater than period so the event will never occur */
|
||||
if (dutyCyclePercent == 0)
|
||||
{
|
||||
pulsePeriod = period + 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
pulsePeriod = (period * (100 - dutyCyclePercent)) / 100;
|
||||
}
|
||||
|
||||
/* Update dutycycle */
|
||||
base->MR[matchChannel] = pulsePeriod;
|
||||
}
|
||||
|
||||
void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t index = CTIMER_GetInstance(base);
|
||||
|
||||
/* Set the counter operation when a match on this channel occurs */
|
||||
reg = base->MCR;
|
||||
reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3));
|
||||
reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3)));
|
||||
reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3)));
|
||||
reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3)));
|
||||
base->MCR = reg;
|
||||
|
||||
reg = base->EMR;
|
||||
/* Set the match output operation when a match on this channel occurs */
|
||||
reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2));
|
||||
reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2));
|
||||
|
||||
/* Set the initial state of the EM bit/output */
|
||||
reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel);
|
||||
reg |= (uint32_t)config->outPinInitState << matchChannel;
|
||||
base->EMR = reg;
|
||||
|
||||
/* Set the match value */
|
||||
base->MR[matchChannel] = config->matchValue;
|
||||
/* Clear status flags */
|
||||
CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel);
|
||||
/* If interrupt is enabled then enable interrupt and update the call back function */
|
||||
if (config->enableInterrupt)
|
||||
{
|
||||
EnableIRQ(s_ctimerIRQ[index]);
|
||||
}
|
||||
}
|
||||
|
||||
void CTIMER_SetupCapture(CTIMER_Type *base,
|
||||
ctimer_capture_channel_t capture,
|
||||
ctimer_capture_edge_t edge,
|
||||
bool enableInt)
|
||||
{
|
||||
uint32_t reg = base->CCR;
|
||||
uint32_t index = CTIMER_GetInstance(base);
|
||||
|
||||
/* Set the capture edge */
|
||||
reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3));
|
||||
reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3));
|
||||
/* Clear status flags */
|
||||
CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture));
|
||||
/* If call back function is valid then enable capture interrupt for the channel and update the call back function */
|
||||
if (enableInt)
|
||||
{
|
||||
reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3);
|
||||
EnableIRQ(s_ctimerIRQ[index]);
|
||||
}
|
||||
base->CCR = reg;
|
||||
}
|
||||
|
||||
void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type)
|
||||
{
|
||||
uint32_t index = CTIMER_GetInstance(base);
|
||||
s_ctimerCallback[index] = cb_func;
|
||||
ctimerCallbackType[index] = cb_type;
|
||||
}
|
||||
|
||||
void CTIMER_GenericIRQHandler(uint32_t index)
|
||||
{
|
||||
uint32_t int_stat, i, mask;
|
||||
/* Get Interrupt status flags */
|
||||
int_stat = CTIMER_GetStatusFlags(s_ctimerBases[index]);
|
||||
/* Clear the status flags that were set */
|
||||
CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat);
|
||||
if (ctimerCallbackType[index] == kCTIMER_SingleCallback)
|
||||
{
|
||||
if (s_ctimerCallback[index][0])
|
||||
{
|
||||
s_ctimerCallback[index][0](int_stat);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
|
||||
for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
|
||||
#else
|
||||
for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++)
|
||||
#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
|
||||
{
|
||||
mask = 0x01 << i;
|
||||
/* For each status flag bit that was set call the callback function if it is valid */
|
||||
if ((int_stat & mask) && (s_ctimerCallback[index][i]))
|
||||
{
|
||||
s_ctimerCallback[index][i](int_stat);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
|
||||
/* IRQ handler functions overloading weak symbols in the startup */
|
||||
#if defined(CTIMER0)
|
||||
void CTIMER0_DriverIRQHandler(void)
|
||||
{
|
||||
CTIMER_GenericIRQHandler(0);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CTIMER1)
|
||||
void CTIMER1_DriverIRQHandler(void)
|
||||
{
|
||||
CTIMER_GenericIRQHandler(1);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CTIMER2)
|
||||
void CTIMER2_DriverIRQHandler(void)
|
||||
{
|
||||
CTIMER_GenericIRQHandler(2);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CTIMER3)
|
||||
void CTIMER3_DriverIRQHandler(void)
|
||||
{
|
||||
CTIMER_GenericIRQHandler(3);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CTIMER4)
|
||||
void CTIMER4_DriverIRQHandler(void)
|
||||
{
|
||||
CTIMER_GenericIRQHandler(4);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
451
Living_SDK/platform/mcu/lpc54102/drivers/fsl_ctimer.h
Normal file
451
Living_SDK/platform/mcu/lpc54102/drivers/fsl_ctimer.h
Normal file
|
|
@ -0,0 +1,451 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_CTIMER_H_
|
||||
#define _FSL_CTIMER_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup ctimer
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
|
||||
/*@}*/
|
||||
|
||||
/*! @brief List of Timer capture channels */
|
||||
typedef enum _ctimer_capture_channel
|
||||
{
|
||||
kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
|
||||
kCTIMER_Capture_1, /*!< Timer capture channel 1 */
|
||||
kCTIMER_Capture_2, /*!< Timer capture channel 2 */
|
||||
#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
|
||||
kCTIMER_Capture_3 /*!< Timer capture channel 3 */
|
||||
#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
|
||||
} ctimer_capture_channel_t;
|
||||
|
||||
/*! @brief List of capture edge options */
|
||||
typedef enum _ctimer_capture_edge
|
||||
{
|
||||
kCTIMER_Capture_RiseEdge = 1U, /*!< Capture on rising edge */
|
||||
kCTIMER_Capture_FallEdge = 2U, /*!< Capture on falling edge */
|
||||
kCTIMER_Capture_BothEdge = 3U, /*!< Capture on rising and falling edge */
|
||||
} ctimer_capture_edge_t;
|
||||
|
||||
/*! @brief List of Timer match registers */
|
||||
typedef enum _ctimer_match
|
||||
{
|
||||
kCTIMER_Match_0 = 0U, /*!< Timer match register 0 */
|
||||
kCTIMER_Match_1, /*!< Timer match register 1 */
|
||||
kCTIMER_Match_2, /*!< Timer match register 2 */
|
||||
kCTIMER_Match_3 /*!< Timer match register 3 */
|
||||
} ctimer_match_t;
|
||||
|
||||
/*! @brief List of output control options */
|
||||
typedef enum _ctimer_match_output_control
|
||||
{
|
||||
kCTIMER_Output_NoAction = 0U, /*!< No action is taken */
|
||||
kCTIMER_Output_Clear, /*!< Clear the EM bit/output to 0 */
|
||||
kCTIMER_Output_Set, /*!< Set the EM bit/output to 1 */
|
||||
kCTIMER_Output_Toggle /*!< Toggle the EM bit/output */
|
||||
} ctimer_match_output_control_t;
|
||||
|
||||
/*! @brief List of Timer modes */
|
||||
typedef enum _ctimer_timer_mode
|
||||
{
|
||||
kCTIMER_TimerMode = 0U, /* TC is incremented every rising APB bus clock edge */
|
||||
kCTIMER_IncreaseOnRiseEdge, /* TC is incremented on rising edge of input signal */
|
||||
kCTIMER_IncreaseOnFallEdge, /* TC is incremented on falling edge of input signal */
|
||||
kCTIMER_IncreaseOnBothEdge /* TC is incremented on both edges of input signal */
|
||||
} ctimer_timer_mode_t;
|
||||
|
||||
/*! @brief List of Timer interrupts */
|
||||
typedef enum _ctimer_interrupt_enable
|
||||
{
|
||||
kCTIMER_Match0InterruptEnable = CTIMER_MCR_MR0I_MASK, /*!< Match 0 interrupt */
|
||||
kCTIMER_Match1InterruptEnable = CTIMER_MCR_MR1I_MASK, /*!< Match 1 interrupt */
|
||||
kCTIMER_Match2InterruptEnable = CTIMER_MCR_MR2I_MASK, /*!< Match 2 interrupt */
|
||||
kCTIMER_Match3InterruptEnable = CTIMER_MCR_MR3I_MASK, /*!< Match 3 interrupt */
|
||||
kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
|
||||
kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
|
||||
kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
|
||||
#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
|
||||
kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
|
||||
#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
|
||||
} ctimer_interrupt_enable_t;
|
||||
|
||||
/*! @brief List of Timer flags */
|
||||
typedef enum _ctimer_status_flags
|
||||
{
|
||||
kCTIMER_Match0Flag = CTIMER_IR_MR0INT_MASK, /*!< Match 0 interrupt flag */
|
||||
kCTIMER_Match1Flag = CTIMER_IR_MR1INT_MASK, /*!< Match 1 interrupt flag */
|
||||
kCTIMER_Match2Flag = CTIMER_IR_MR2INT_MASK, /*!< Match 2 interrupt flag */
|
||||
kCTIMER_Match3Flag = CTIMER_IR_MR3INT_MASK, /*!< Match 3 interrupt flag */
|
||||
kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
|
||||
kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
|
||||
kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
|
||||
#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
|
||||
kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
|
||||
#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
|
||||
} ctimer_status_flags_t;
|
||||
|
||||
typedef void (*ctimer_callback_t)(uint32_t flags);
|
||||
|
||||
/*! @brief Callback type when registering for a callback. When registering a callback
|
||||
* an array of function pointers is passed the size could be 1 or 8, the callback
|
||||
* type will tell that.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer.
|
||||
based on the status flags different channels needs to be handled differently */
|
||||
kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel.
|
||||
for both match/capture */
|
||||
} ctimer_callback_type_t;
|
||||
|
||||
/*!
|
||||
* @brief Match configuration
|
||||
*
|
||||
* This structure holds the configuration settings for each match register.
|
||||
*/
|
||||
typedef struct _ctimer_match_config
|
||||
{
|
||||
uint32_t matchValue; /*!< This is stored in the match register */
|
||||
bool enableCounterReset; /*!< true: Match will reset the counter
|
||||
false: Match will not reser the counter */
|
||||
bool enableCounterStop; /*!< true: Match will stop the counter
|
||||
false: Match will not stop the counter */
|
||||
ctimer_match_output_control_t outControl; /*!< Action to be taken on a match on the EM bit/output */
|
||||
bool outPinInitState; /*!< Initial value of the EM bit/output */
|
||||
bool enableInterrupt; /*!< true: Generate interrupt upon match
|
||||
false: Do not generate interrupt on match */
|
||||
|
||||
} ctimer_match_config_t;
|
||||
|
||||
/*!
|
||||
* @brief Timer configuration structure
|
||||
*
|
||||
* This structure holds the configuration settings for the Timer peripheral. To initialize this
|
||||
* structure to reasonable defaults, call the CTIMER_GetDefaultConfig() function and pass a
|
||||
* pointer to the configuration structure instance.
|
||||
*
|
||||
* The configuration structure can be made constant so as to reside in flash.
|
||||
*/
|
||||
typedef struct _ctimer_config
|
||||
{
|
||||
ctimer_timer_mode_t mode; /*!< Timer mode */
|
||||
ctimer_capture_channel_t input; /*!< Input channel to increment the timer, used only in timer
|
||||
modes that rely on this input signal to increment TC */
|
||||
uint32_t prescale; /*!< Prescale value */
|
||||
} ctimer_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Ungates the clock and configures the peripheral for basic operation.
|
||||
*
|
||||
* @note This API should be called at the beginning of the application before using the driver.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
* @param config Pointer to the user configuration structure.
|
||||
*/
|
||||
void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Gates the timer clock.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
*/
|
||||
void CTIMER_Deinit(CTIMER_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Fills in the timers configuration structure with the default settings.
|
||||
*
|
||||
* The default values are:
|
||||
* @code
|
||||
* config->mode = kCTIMER_TimerMode;
|
||||
* config->input = kCTIMER_Capture_0;
|
||||
* config->prescale = 0;
|
||||
* @endcode
|
||||
* @param config Pointer to the user configuration structure.
|
||||
*/
|
||||
void CTIMER_GetDefaultConfig(ctimer_config_t *config);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name PWM setup operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Configures the PWM signal parameters.
|
||||
*
|
||||
* Enables PWM mode on the match channel passed in and will then setup the match value
|
||||
* and other match parameters to generate a PWM signal.
|
||||
* This function will assign match channel 3 to set the PWM cycle.
|
||||
*
|
||||
* @note When setting PWM output from multiple output pins, all should use the same PWM
|
||||
* frequency
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
* @param matchChannel Match pin to be used to output the PWM signal
|
||||
* @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
|
||||
* @param pwmFreq_Hz PWM signal frequency in Hz
|
||||
* @param srcClock_Hz Timer counter clock in Hz
|
||||
* @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse,
|
||||
* if it is 0 then no interrupt is generated
|
||||
*
|
||||
* @return kStatus_Success on success
|
||||
* kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
|
||||
*/
|
||||
status_t CTIMER_SetupPwm(CTIMER_Type *base,
|
||||
ctimer_match_t matchChannel,
|
||||
uint8_t dutyCyclePercent,
|
||||
uint32_t pwmFreq_Hz,
|
||||
uint32_t srcClock_Hz,
|
||||
bool enableInt);
|
||||
|
||||
/*!
|
||||
* @brief Updates the duty cycle of an active PWM signal.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
* @param matchChannel Match pin to be used to output the PWM signal
|
||||
* @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
|
||||
*/
|
||||
void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @brief Setup the match register.
|
||||
*
|
||||
* User configuration is used to setup the match value and action to be taken when a match occurs.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
* @param matchChannel Match register to configure
|
||||
* @param config Pointer to the match configuration structure
|
||||
*/
|
||||
void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Setup the capture.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
* @param capture Capture channel to configure
|
||||
* @param edge Edge on the channel that will trigger a capture
|
||||
* @param enableInt Flag to enable channel interrupts, if enabled then the registered call back
|
||||
* is called upon capture
|
||||
*/
|
||||
void CTIMER_SetupCapture(CTIMER_Type *base,
|
||||
ctimer_capture_channel_t capture,
|
||||
ctimer_capture_edge_t edge,
|
||||
bool enableInt);
|
||||
|
||||
/*!
|
||||
* @brief Register callback.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
* @param cb_func callback function
|
||||
* @param cb_type callback function type, singular or multiple
|
||||
*/
|
||||
void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctimer_callback_type_t cb_type);
|
||||
|
||||
/*!
|
||||
* @name Interrupt Interface
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the selected Timer interrupts.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
* @param mask The interrupts to enable. This is a logical OR of members of the
|
||||
* enumeration ::ctimer_interrupt_enable_t
|
||||
*/
|
||||
static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
|
||||
{
|
||||
/* Enable match interrupts */
|
||||
base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
|
||||
|
||||
/* Enable capture interrupts */
|
||||
base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
|
||||
#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
|
||||
| CTIMER_CCR_CAP3I_MASK
|
||||
#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
|
||||
);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the selected Timer interrupts.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
* @param mask The interrupts to enable. This is a logical OR of members of the
|
||||
* enumeration ::ctimer_interrupt_enable_t
|
||||
*/
|
||||
static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
|
||||
{
|
||||
/* Disable match interrupts */
|
||||
base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK));
|
||||
|
||||
/* Disable capture interrupts */
|
||||
base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
|
||||
#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
|
||||
| CTIMER_CCR_CAP3I_MASK
|
||||
#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
|
||||
));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the enabled Timer interrupts.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
*
|
||||
* @return The enabled interrupts. This is the logical OR of members of the
|
||||
* enumeration ::ctimer_interrupt_enable_t
|
||||
*/
|
||||
static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)
|
||||
{
|
||||
uint32_t enabledIntrs = 0;
|
||||
|
||||
/* Get all the match interrupts enabled */
|
||||
enabledIntrs =
|
||||
base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
|
||||
|
||||
/* Get all the capture interrupts enabled */
|
||||
enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
|
||||
#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
|
||||
| CTIMER_CCR_CAP3I_MASK
|
||||
#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
|
||||
);
|
||||
|
||||
return enabledIntrs;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Status Interface
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the Timer status flags.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
*
|
||||
* @return The status flags. This is the logical OR of members of the
|
||||
* enumeration ::ctimer_status_flags_t
|
||||
*/
|
||||
static inline uint32_t CTIMER_GetStatusFlags(CTIMER_Type *base)
|
||||
{
|
||||
return base->IR;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the Timer status flags.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
* @param mask The status flags to clear. This is a logical OR of members of the
|
||||
* enumeration ::ctimer_status_flags_t
|
||||
*/
|
||||
static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask)
|
||||
{
|
||||
base->IR = mask;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Counter Start and Stop
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Starts the Timer counter.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
*/
|
||||
static inline void CTIMER_StartTimer(CTIMER_Type *base)
|
||||
{
|
||||
base->TCR |= CTIMER_TCR_CEN_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Stops the Timer counter.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
*/
|
||||
static inline void CTIMER_StopTimer(CTIMER_Type *base)
|
||||
{
|
||||
base->TCR &= ~CTIMER_TCR_CEN_MASK;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @brief Reset the counter.
|
||||
*
|
||||
* The timer counter and prescale counter are reset on the next positive edge of the APB clock.
|
||||
*
|
||||
* @param base Ctimer peripheral base address
|
||||
*/
|
||||
static inline void CTIMER_Reset(CTIMER_Type *base)
|
||||
{
|
||||
base->TCR |= CTIMER_TCR_CRST_MASK;
|
||||
base->TCR &= ~CTIMER_TCR_CRST_MASK;
|
||||
}
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_CTIMER_H_ */
|
||||
415
Living_SDK/platform/mcu/lpc54102/drivers/fsl_dma.c
Normal file
415
Living_SDK/platform/mcu/lpc54102/drivers/fsl_dma.c
Normal file
|
|
@ -0,0 +1,415 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_dma.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief Get instance number for DMA.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
*/
|
||||
static int32_t DMA_GetInstance(DMA_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Array to map DMA instance number to base pointer. */
|
||||
static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS;
|
||||
|
||||
/*! @brief Array to map DMA instance number to IRQ number. */
|
||||
static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS;
|
||||
|
||||
/*! @brief Pointers to transfer handle for each DMA channel. */
|
||||
static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS];
|
||||
|
||||
/*! @brief Static table of descriptors */
|
||||
#if defined(__ICCARM__)
|
||||
#pragma data_alignment = 512
|
||||
dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
|
||||
#elif defined(__CC_ARM)
|
||||
__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
|
||||
#elif defined(__GNUC__)
|
||||
__attribute__((aligned(512))) dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_DMA_NUMBER_OF_CHANNELS] = {0};
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static int32_t DMA_GetInstance(DMA_Type *base)
|
||||
{
|
||||
int32_t instance;
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++)
|
||||
{
|
||||
if (s_dmaBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
assert(instance < ARRAY_SIZE(s_dmaBases));
|
||||
return instance < ARRAY_SIZE(s_dmaBases) ? instance : -1;
|
||||
}
|
||||
|
||||
void DMA_Init(DMA_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* enable dma clock gate */
|
||||
CLOCK_EnableClock(kCLOCK_Dma);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
/* set descriptor table */
|
||||
base->SRAMBASE = (uint32_t)s_dma_descriptor_table;
|
||||
/* enable dma peripheral */
|
||||
base->CTRL |= DMA_CTRL_ENABLE_MASK;
|
||||
}
|
||||
|
||||
void DMA_Deinit(DMA_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable DMA peripheral */
|
||||
base->CTRL &= ~(DMA_CTRL_ENABLE_MASK);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger)
|
||||
{
|
||||
assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS) && (NULL != trigger));
|
||||
|
||||
uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
|
||||
DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK |
|
||||
DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK);
|
||||
tmp = base->CHANNEL[channel].CFG & (~tmp);
|
||||
tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
|
||||
base->CHANNEL[channel].CFG = tmp;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the remaining bytes of the current DMA descriptor transfer.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
* @return The number of bytes which have not been transferred yet.
|
||||
*/
|
||||
uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
|
||||
|
||||
/* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes
|
||||
* impossible to distinguish between:
|
||||
* - transfer finishes (represented by value '0x3FF')
|
||||
* - and remaining 1024 bytes to transfer (value 0x3FF)
|
||||
* for all descriptor in chain, except the last one.
|
||||
* If you decide to use this function, please use 1023 transfers as maximal value */
|
||||
|
||||
/* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */
|
||||
if ((!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) &&
|
||||
(0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >>
|
||||
DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)))
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
return base->CHANNEL[channel].XFERCFG + 1;
|
||||
}
|
||||
|
||||
static void DMA_SetupDescriptor(
|
||||
dma_descriptor_t *desc, uint32_t xfercfg, void *srcEndAddr, void *dstEndAddr, void *nextDesc)
|
||||
{
|
||||
desc->xfercfg = xfercfg;
|
||||
desc->srcEndAddr = srcEndAddr;
|
||||
desc->dstEndAddr = dstEndAddr;
|
||||
desc->linkToNextDesc = nextDesc;
|
||||
}
|
||||
|
||||
/* Verify and convert dma_xfercfg_t to XFERCFG register */
|
||||
static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr)
|
||||
{
|
||||
assert(xfercfg != NULL);
|
||||
/* check source increment */
|
||||
assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4));
|
||||
/* check destination increment */
|
||||
assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4));
|
||||
/* check data width */
|
||||
assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4));
|
||||
/* check transfer count */
|
||||
assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT);
|
||||
|
||||
uint32_t xfer = 0, tmp;
|
||||
/* set valid flag - descriptor is ready now */
|
||||
xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0);
|
||||
/* set reload - allow link to next descriptor */
|
||||
xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0);
|
||||
/* set swtrig flag - start transfer */
|
||||
xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig ? 1 : 0);
|
||||
/* set transfer count */
|
||||
xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig ? 1 : 0);
|
||||
/* set INTA */
|
||||
xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0);
|
||||
/* set INTB */
|
||||
xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0);
|
||||
/* set data width */
|
||||
tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1;
|
||||
xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp);
|
||||
/* set source increment value */
|
||||
tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc;
|
||||
xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp);
|
||||
/* set destination increment value */
|
||||
tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc;
|
||||
xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp);
|
||||
/* set transfer count */
|
||||
xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1);
|
||||
|
||||
/* store xferCFG */
|
||||
*xfercfg_addr = xfer;
|
||||
}
|
||||
|
||||
void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc)
|
||||
{
|
||||
uint32_t xfercfg_reg = 0;
|
||||
|
||||
assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg));
|
||||
assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth));
|
||||
assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth));
|
||||
assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16));
|
||||
|
||||
/* Setup channel configuration */
|
||||
DMA_SetupXferCFG(xfercfg, &xfercfg_reg);
|
||||
|
||||
/* Set descriptor structure */
|
||||
DMA_SetupDescriptor(
|
||||
desc, xfercfg_reg, (uint8_t *)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
|
||||
(uint8_t *)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), nextDesc);
|
||||
}
|
||||
|
||||
void DMA_AbortTransfer(dma_handle_t *handle)
|
||||
{
|
||||
assert(NULL != handle);
|
||||
|
||||
DMA_DisableChannel(handle->base, handle->channel);
|
||||
while (handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].BUSY & (1U << DMA_CHANNEL_INDEX(handle->channel)))
|
||||
{
|
||||
}
|
||||
handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].ABORT |= 1U << DMA_CHANNEL_INDEX(handle->channel);
|
||||
DMA_EnableChannel(handle->base, handle->channel);
|
||||
}
|
||||
|
||||
void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)
|
||||
{
|
||||
int32_t dmaInstance;
|
||||
assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS));
|
||||
|
||||
/* base address is invalid DMA instance */
|
||||
dmaInstance = DMA_GetInstance(base);
|
||||
|
||||
memset(handle, 0, sizeof(*handle));
|
||||
handle->base = base;
|
||||
handle->channel = channel;
|
||||
s_DMAHandle[channel] = handle;
|
||||
/* Enable NVIC interrupt */
|
||||
EnableIRQ(s_dmaIRQNumber[dmaInstance]);
|
||||
}
|
||||
|
||||
void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData)
|
||||
{
|
||||
assert(handle != NULL);
|
||||
|
||||
handle->callback = callback;
|
||||
handle->userData = userData;
|
||||
}
|
||||
|
||||
void DMA_PrepareTransfer(dma_transfer_config_t *config,
|
||||
void *srcAddr,
|
||||
void *dstAddr,
|
||||
uint32_t byteWidth,
|
||||
uint32_t transferBytes,
|
||||
dma_transfer_type_t type,
|
||||
void *nextDesc)
|
||||
{
|
||||
uint32_t xfer_count;
|
||||
assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr));
|
||||
assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4));
|
||||
|
||||
/* check max */
|
||||
xfer_count = transferBytes / byteWidth;
|
||||
assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth));
|
||||
|
||||
memset(config, 0, sizeof(*config));
|
||||
switch (type)
|
||||
{
|
||||
case kDMA_MemoryToMemory:
|
||||
config->xfercfg.srcInc = 1;
|
||||
config->xfercfg.dstInc = 1;
|
||||
config->isPeriph = false;
|
||||
break;
|
||||
case kDMA_PeripheralToMemory:
|
||||
/* Peripheral register - source doesn't increment */
|
||||
config->xfercfg.srcInc = 0;
|
||||
config->xfercfg.dstInc = 1;
|
||||
config->isPeriph = true;
|
||||
break;
|
||||
case kDMA_MemoryToPeripheral:
|
||||
/* Peripheral register - destination doesn't increment */
|
||||
config->xfercfg.srcInc = 1;
|
||||
config->xfercfg.dstInc = 0;
|
||||
config->isPeriph = true;
|
||||
break;
|
||||
case kDMA_StaticToStatic:
|
||||
config->xfercfg.srcInc = 0;
|
||||
config->xfercfg.dstInc = 0;
|
||||
config->isPeriph = true;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
config->dstAddr = (uint8_t *)dstAddr;
|
||||
config->srcAddr = (uint8_t *)srcAddr;
|
||||
config->nextDesc = (uint8_t *)nextDesc;
|
||||
config->xfercfg.transferCount = xfer_count;
|
||||
config->xfercfg.byteWidth = byteWidth;
|
||||
config->xfercfg.intA = true;
|
||||
config->xfercfg.reload = nextDesc != NULL;
|
||||
config->xfercfg.valid = true;
|
||||
}
|
||||
|
||||
status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
|
||||
{
|
||||
assert((NULL != handle) && (NULL != config));
|
||||
|
||||
/* Previous transfer has not finished */
|
||||
if (DMA_ChannelIsActive(handle->base, handle->channel))
|
||||
{
|
||||
return kStatus_DMA_Busy;
|
||||
}
|
||||
|
||||
/* enable/disable peripheral request */
|
||||
if (config->isPeriph)
|
||||
{
|
||||
DMA_EnableChannelPeriphRq(handle->base, handle->channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_DisableChannelPeriphRq(handle->base, handle->channel);
|
||||
}
|
||||
|
||||
DMA_CreateDescriptor(&s_dma_descriptor_table[handle->channel], &config->xfercfg, config->srcAddr, config->dstAddr,
|
||||
config->nextDesc);
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void DMA_StartTransfer(dma_handle_t *handle)
|
||||
{
|
||||
assert(NULL != handle);
|
||||
|
||||
/* Enable channel interrupt */
|
||||
handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(handle->channel);
|
||||
|
||||
/* If HW trigger is enabled - disable SW trigger */
|
||||
if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
|
||||
{
|
||||
s_dma_descriptor_table[handle->channel].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK);
|
||||
}
|
||||
/* Otherwise enable SW trigger */
|
||||
else
|
||||
{
|
||||
s_dma_descriptor_table[handle->channel].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
|
||||
}
|
||||
|
||||
/* Set channel XFERCFG register according first channel descriptor. */
|
||||
handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[handle->channel].xfercfg;
|
||||
/* At this moment, the channel ACTIVE bit is set and application cannot modify
|
||||
* or start another transfer using this channel. Channel ACTIVE bit is cleared by
|
||||
* 'AbortTransfer' function or when the transfer finishes */
|
||||
}
|
||||
|
||||
void DMA0_DriverIRQHandler(void)
|
||||
{
|
||||
dma_handle_t *handle;
|
||||
int32_t channel_group;
|
||||
int32_t channel_index;
|
||||
|
||||
/* Find channels that have completed transfer */
|
||||
for (int i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS; i++)
|
||||
{
|
||||
handle = s_DMAHandle[i];
|
||||
/* Handle is not present */
|
||||
if (NULL == handle)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
channel_group = DMA_CHANNEL_GROUP(handle->channel);
|
||||
channel_index = DMA_CHANNEL_INDEX(handle->channel);
|
||||
/* Channel uses INTA flag */
|
||||
if (handle->base->COMMON[channel_group].INTA & (1U << channel_index))
|
||||
{
|
||||
/* Clear INTA flag */
|
||||
handle->base->COMMON[channel_group].INTA = 1U << channel_index;
|
||||
if (handle->callback)
|
||||
{
|
||||
(handle->callback)(handle, handle->userData, true, kDMA_IntA);
|
||||
}
|
||||
}
|
||||
/* Channel uses INTB flag */
|
||||
if (handle->base->COMMON[channel_group].INTB & (1U << channel_index))
|
||||
{
|
||||
/* Clear INTB flag */
|
||||
handle->base->COMMON[channel_group].INTB = 1U << channel_index;
|
||||
if (handle->callback)
|
||||
{
|
||||
(handle->callback)(handle, handle->userData, true, kDMA_IntB);
|
||||
}
|
||||
}
|
||||
/* Error flag */
|
||||
if (handle->base->COMMON[channel_group].ERRINT & (1U << channel_index))
|
||||
{
|
||||
/* Clear error flag */
|
||||
handle->base->COMMON[channel_group].ERRINT = 1U << channel_index;
|
||||
if (handle->callback)
|
||||
{
|
||||
(handle->callback)(handle, handle->userData, false, kDMA_IntError);
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
493
Living_SDK/platform/mcu/lpc54102/drivers/fsl_dma.h
Normal file
493
Living_SDK/platform/mcu/lpc54102/drivers/fsl_dma.h
Normal file
|
|
@ -0,0 +1,493 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_DMA_H_
|
||||
#define _FSL_DMA_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup dma
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief DMA driver version */
|
||||
#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
/*@}*/
|
||||
|
||||
#define DMA_MAX_TRANSFER_COUNT 0x400
|
||||
|
||||
/* Channel group consists of 32 channels. channel_group = (channel / 32) */
|
||||
#define DMA_CHANNEL_GROUP(channel) (((uint8_t)channel) >> 5U)
|
||||
/* Channel index in channel group. channel_index = (channel % 32) */
|
||||
#define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F)
|
||||
|
||||
/*! @brief DMA descriptor structure */
|
||||
typedef struct _dma_descriptor
|
||||
{
|
||||
uint32_t xfercfg; /*!< Transfer configuration */
|
||||
void *srcEndAddr; /*!< Last source address of DMA transfer */
|
||||
void *dstEndAddr; /*!< Last destination address of DMA transfer */
|
||||
void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */
|
||||
} dma_descriptor_t;
|
||||
|
||||
/*! @brief DMA transfer configuration */
|
||||
typedef struct _dma_xfercfg
|
||||
{
|
||||
bool valid; /*!< Descriptor is ready to transfer */
|
||||
bool reload; /*!< Reload channel configuration register after
|
||||
current descriptor is exhausted */
|
||||
bool swtrig; /*!< Perform software trigger. Transfer if fired
|
||||
when 'valid' is set */
|
||||
bool clrtrig; /*!< Clear trigger */
|
||||
bool intA; /*!< Raises IRQ when transfer is done and set IRQA status register flag */
|
||||
bool intB; /*!< Raises IRQ when transfer is done and set IRQB status register flag */
|
||||
uint8_t byteWidth; /*!< Byte width of data to transfer */
|
||||
uint8_t srcInc; /*!< Increment source address by 'srcInc' x 'byteWidth' */
|
||||
uint8_t dstInc; /*!< Increment destination address by 'dstInc' x 'byteWidth' */
|
||||
uint16_t transferCount; /*!< Number of transfers */
|
||||
} dma_xfercfg_t;
|
||||
|
||||
/*! @brief DMA channel priority */
|
||||
typedef enum _dma_priority
|
||||
{
|
||||
kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */
|
||||
kDMA_ChannelPriority1, /*!< Channel priority 1 */
|
||||
kDMA_ChannelPriority2, /*!< Channel priority 2 */
|
||||
kDMA_ChannelPriority3, /*!< Channel priority 3 */
|
||||
kDMA_ChannelPriority4, /*!< Channel priority 4 */
|
||||
kDMA_ChannelPriority5, /*!< Channel priority 5 */
|
||||
kDMA_ChannelPriority6, /*!< Channel priority 6 */
|
||||
kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */
|
||||
} dma_priority_t;
|
||||
|
||||
/*! @brief DMA interrupt flags */
|
||||
typedef enum _dma_int
|
||||
{
|
||||
kDMA_IntA, /*!< DMA interrupt flag A */
|
||||
kDMA_IntB, /*!< DMA interrupt flag B */
|
||||
kDMA_IntError, /*!< DMA interrupt flag error */
|
||||
} dma_irq_t;
|
||||
|
||||
/*! @brief DMA trigger type*/
|
||||
typedef enum _dma_trigger_type
|
||||
{
|
||||
kDMA_NoTrigger = 0, /*!< Trigger is disabled */
|
||||
kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */
|
||||
kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) |
|
||||
DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
|
||||
kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */
|
||||
kDMA_RisingEdgeTrigger =
|
||||
DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
|
||||
} dma_trigger_type_t;
|
||||
|
||||
/*! @brief DMA trigger burst */
|
||||
typedef enum _dma_trigger_burst
|
||||
{
|
||||
kDMA_SingleTransfer = 0, /*!< Single transfer */
|
||||
kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */
|
||||
kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */
|
||||
kDMA_EdgeBurstTransfer2 =
|
||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */
|
||||
kDMA_EdgeBurstTransfer4 =
|
||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */
|
||||
kDMA_EdgeBurstTransfer8 =
|
||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */
|
||||
kDMA_EdgeBurstTransfer16 =
|
||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */
|
||||
kDMA_EdgeBurstTransfer32 =
|
||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */
|
||||
kDMA_EdgeBurstTransfer64 =
|
||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */
|
||||
kDMA_EdgeBurstTransfer128 =
|
||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */
|
||||
kDMA_EdgeBurstTransfer256 =
|
||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */
|
||||
kDMA_EdgeBurstTransfer512 =
|
||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */
|
||||
kDMA_EdgeBurstTransfer1024 =
|
||||
DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
|
||||
} dma_trigger_burst_t;
|
||||
|
||||
/*! @brief DMA burst wrapping */
|
||||
typedef enum _dma_burst_wrap
|
||||
{
|
||||
kDMA_NoWrap = 0, /*!< Wrapping is disabled */
|
||||
kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */
|
||||
kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */
|
||||
kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) |
|
||||
DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */
|
||||
} dma_burst_wrap_t;
|
||||
|
||||
/*! @brief DMA transfer type */
|
||||
typedef enum _dma_transfer_type
|
||||
{
|
||||
kDMA_MemoryToMemory = 0x0U, /*!< Transfer from memory to memory (increment source and destination) */
|
||||
kDMA_PeripheralToMemory, /*!< Transfer from peripheral to memory (increment only destination) */
|
||||
kDMA_MemoryToPeripheral, /*!< Transfer from memory to peripheral (increment only source)*/
|
||||
kDMA_StaticToStatic, /*!< Peripheral to static memory (do not increment source or destination) */
|
||||
} dma_transfer_type_t;
|
||||
|
||||
/*! @brief DMA channel trigger */
|
||||
typedef struct _dma_channel_trigger
|
||||
{
|
||||
dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */
|
||||
dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */
|
||||
dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */
|
||||
} dma_channel_trigger_t;
|
||||
|
||||
/*! @brief DMA transfer status */
|
||||
enum _dma_transfer_status
|
||||
{
|
||||
kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the
|
||||
transfer request. */
|
||||
};
|
||||
|
||||
/*! @brief DMA transfer configuration */
|
||||
typedef struct _dma_transfer_config
|
||||
{
|
||||
uint8_t *srcAddr; /*!< Source data address */
|
||||
uint8_t *dstAddr; /*!< Destination data address */
|
||||
uint8_t *nextDesc; /*!< Chain custom descriptor */
|
||||
dma_xfercfg_t xfercfg; /*!< Transfer options */
|
||||
bool isPeriph; /*!< DMA transfer is driven by peripheral */
|
||||
} dma_transfer_config_t;
|
||||
|
||||
/*! @brief Callback for DMA */
|
||||
struct _dma_handle;
|
||||
|
||||
/*! @brief Define Callback function for DMA. */
|
||||
typedef void (*dma_callback)(struct _dma_handle *handle, void *userData, bool transferDone, uint32_t intmode);
|
||||
|
||||
/*! @brief DMA transfer handle structure */
|
||||
typedef struct _dma_handle
|
||||
{
|
||||
dma_callback callback; /*!< Callback function. Invoked when transfer
|
||||
of descriptor with interrupt flag finishes */
|
||||
void *userData; /*!< Callback function parameter */
|
||||
DMA_Type *base; /*!< DMA peripheral base address */
|
||||
uint8_t channel; /*!< DMA channel number */
|
||||
} dma_handle_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* APIs
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*!
|
||||
* @name DMA initialization and De-initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes DMA peripheral.
|
||||
*
|
||||
* This function enable the DMA clock, set descriptor table and
|
||||
* enable DMA peripheral.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
*/
|
||||
void DMA_Init(DMA_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes DMA peripheral.
|
||||
*
|
||||
* This function gates the DMA clock.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
*/
|
||||
void DMA_Deinit(DMA_Type *base);
|
||||
|
||||
/* @} */
|
||||
/*!
|
||||
* @name DMA Channel Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Return whether DMA channel is processing transfer
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
* @return True for active state, false otherwise.
|
||||
*/
|
||||
static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
|
||||
return (base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables the interrupt source for the DMA transfer.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
*/
|
||||
static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
|
||||
base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENSET |= 1U << DMA_CHANNEL_INDEX(channel);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the interrupt source for the DMA transfer.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
*/
|
||||
static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
|
||||
base->COMMON[DMA_CHANNEL_GROUP(channel)].INTENCLR |= 1U << DMA_CHANNEL_INDEX(channel);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable DMA channel.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
*/
|
||||
static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
|
||||
base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLESET |= 1U << DMA_CHANNEL_INDEX(channel);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable DMA channel.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
*/
|
||||
static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
|
||||
base->COMMON[DMA_CHANNEL_GROUP(channel)].ENABLECLR |= 1U << DMA_CHANNEL_INDEX(channel);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set PERIPHREQEN of channel configuration register.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
*/
|
||||
static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
|
||||
base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get PERIPHREQEN value of channel configuration register.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
* @return True for enabled PeriphRq, false for disabled.
|
||||
*/
|
||||
static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
|
||||
base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set trigger settings of DMA channel.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
* @param trigger trigger configuration.
|
||||
*/
|
||||
void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger);
|
||||
|
||||
/*!
|
||||
* @brief Gets the remaining bytes of the current DMA descriptor transfer.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
* @return The number of bytes which have not been transferred yet.
|
||||
*/
|
||||
uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel);
|
||||
|
||||
/*!
|
||||
* @brief Set priority of channel configuration register.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
* @param priority Channel priority value.
|
||||
*/
|
||||
static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
|
||||
base->CHANNEL[channel].CFG =
|
||||
(base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get priority of channel configuration register.
|
||||
*
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
* @return Channel priority value.
|
||||
*/
|
||||
static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
|
||||
{
|
||||
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
|
||||
return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >>
|
||||
DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Create application specific DMA descriptor
|
||||
* to be used in a chain in transfer
|
||||
*
|
||||
* @param desc DMA descriptor address.
|
||||
* @param xfercfg Transfer configuration for DMA descriptor.
|
||||
* @param srcAddr Address of last item to transmit
|
||||
* @param dstAddr Address of last item to receive.
|
||||
* @param nextDesc Address of next descriptor in chain.
|
||||
*/
|
||||
void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name DMA Transactional Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Abort running transfer by handle.
|
||||
*
|
||||
* This function aborts DMA transfer specified by handle.
|
||||
*
|
||||
* @param handle DMA handle pointer.
|
||||
*/
|
||||
void DMA_AbortTransfer(dma_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Creates the DMA handle.
|
||||
*
|
||||
* This function is called if using transaction API for DMA. This function
|
||||
* initializes the internal state of DMA handle.
|
||||
*
|
||||
* @param handle DMA handle pointer. The DMA handle stores callback function and
|
||||
* parameters.
|
||||
* @param base DMA peripheral base address.
|
||||
* @param channel DMA channel number.
|
||||
*/
|
||||
void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel);
|
||||
|
||||
/*!
|
||||
* @brief Installs a callback function for the DMA transfer.
|
||||
*
|
||||
* This callback is called in DMA IRQ handler. Use the callback to do something after
|
||||
* the current major loop transfer completes.
|
||||
*
|
||||
* @param handle DMA handle pointer.
|
||||
* @param callback DMA callback function pointer.
|
||||
* @param userData Parameter for callback function.
|
||||
*/
|
||||
void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData);
|
||||
|
||||
/*!
|
||||
* @brief Prepares the DMA transfer structure.
|
||||
*
|
||||
* This function prepares the transfer configuration structure according to the user input.
|
||||
*
|
||||
* @param config The user configuration structure of type dma_transfer_t.
|
||||
* @param srcAddr DMA transfer source address.
|
||||
* @param dstAddr DMA transfer destination address.
|
||||
* @param byteWidth DMA transfer destination address width(bytes).
|
||||
* @param transferBytes DMA transfer bytes to be transferred.
|
||||
* @param type DMA transfer type.
|
||||
* @param nextDesc Chain custom descriptor to transfer.
|
||||
* @note The data address and the data width must be consistent. For example, if the SRC
|
||||
* is 4 bytes, so the source address must be 4 bytes aligned, or it shall result in
|
||||
* source address error(SAE).
|
||||
*/
|
||||
void DMA_PrepareTransfer(dma_transfer_config_t *config,
|
||||
void *srcAddr,
|
||||
void *dstAddr,
|
||||
uint32_t byteWidth,
|
||||
uint32_t transferBytes,
|
||||
dma_transfer_type_t type,
|
||||
void *nextDesc);
|
||||
|
||||
/*!
|
||||
* @brief Submits the DMA transfer request.
|
||||
*
|
||||
* This function submits the DMA transfer request according to the transfer configuration structure.
|
||||
* If the user submits the transfer request repeatedly, this function packs an unprocessed request as
|
||||
* a TCD and enables scatter/gather feature to process it in the next time.
|
||||
*
|
||||
* @param handle DMA handle pointer.
|
||||
* @param config Pointer to DMA transfer configuration structure.
|
||||
* @retval kStatus_DMA_Success It means submit transfer request succeed.
|
||||
* @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
|
||||
* @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
|
||||
*/
|
||||
status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief DMA start transfer.
|
||||
*
|
||||
* This function enables the channel request. User can call this function after submitting the transfer request
|
||||
* or before submitting the transfer request.
|
||||
*
|
||||
* @param handle DMA handle pointer.
|
||||
*/
|
||||
void DMA_StartTransfer(dma_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief DMA IRQ handler for descriptor transfer complete.
|
||||
*
|
||||
* This function clears the channel major interrupt flag and call
|
||||
* the callback function if it is not NULL.
|
||||
*/
|
||||
void DMA_HandleIRQ(void);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/* @} */
|
||||
|
||||
#endif /*_FSL_DMA_H_*/
|
||||
127
Living_SDK/platform/mcu/lpc54102/drivers/fsl_flashiap.c
Normal file
127
Living_SDK/platform/mcu/lpc54102/drivers/fsl_flashiap.c
Normal file
|
|
@ -0,0 +1,127 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_flashiap.h"
|
||||
|
||||
#define HZ_TO_KHZ_DIV 1000
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static status_t translate_iap_status(uint32_t status)
|
||||
{
|
||||
/* Translate IAP return code to sdk status code */
|
||||
if (status == kStatus_Success)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
else
|
||||
{
|
||||
return MAKE_STATUS(kStatusGroup_FLASHIAP, status);
|
||||
}
|
||||
}
|
||||
|
||||
status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector)
|
||||
{
|
||||
uint32_t command[5], result[4];
|
||||
|
||||
command[0] = kIapCmd_FLASHIAP_PrepareSectorforWrite;
|
||||
command[1] = startSector;
|
||||
command[2] = endSector;
|
||||
iap_entry(command, result);
|
||||
|
||||
return translate_iap_status(result[0]);
|
||||
}
|
||||
|
||||
status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock)
|
||||
{
|
||||
uint32_t command[5], result[4];
|
||||
|
||||
command[0] = kIapCmd_FLASHIAP_CopyRamToFlash;
|
||||
command[1] = dstAddr;
|
||||
command[2] = (uint32_t)srcAddr;
|
||||
command[3] = numOfBytes;
|
||||
command[4] = systemCoreClock / HZ_TO_KHZ_DIV;
|
||||
iap_entry(command, result);
|
||||
|
||||
return translate_iap_status(result[0]);
|
||||
}
|
||||
|
||||
status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock)
|
||||
{
|
||||
uint32_t command[5], result[4];
|
||||
|
||||
command[0] = kIapCmd_FLASHIAP_EraseSector;
|
||||
command[1] = startSector;
|
||||
command[2] = endSector;
|
||||
command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
|
||||
iap_entry(command, result);
|
||||
|
||||
return translate_iap_status(result[0]);
|
||||
}
|
||||
|
||||
status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock)
|
||||
{
|
||||
uint32_t command[5], result[4];
|
||||
|
||||
command[0] = kIapCmd_FLASHIAP_ErasePage;
|
||||
command[1] = startPage;
|
||||
command[2] = endPage;
|
||||
command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
|
||||
iap_entry(command, result);
|
||||
|
||||
return translate_iap_status(result[0]);
|
||||
}
|
||||
|
||||
status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector)
|
||||
{
|
||||
uint32_t command[5], result[4];
|
||||
|
||||
command[0] = kIapCmd_FLASHIAP_BlankCheckSector;
|
||||
command[1] = startSector;
|
||||
command[2] = endSector;
|
||||
iap_entry(command, result);
|
||||
|
||||
return translate_iap_status(result[0]);
|
||||
}
|
||||
|
||||
status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes)
|
||||
{
|
||||
uint32_t command[5], result[4];
|
||||
|
||||
command[0] = kIapCmd_FLASHIAP_Compare;
|
||||
command[1] = dstAddr;
|
||||
command[2] = (uint32_t)srcAddr;
|
||||
command[3] = numOfBytes;
|
||||
iap_entry(command, result);
|
||||
|
||||
return translate_iap_status(result[0]);
|
||||
}
|
||||
264
Living_SDK/platform/mcu/lpc54102/drivers/fsl_flashiap.h
Normal file
264
Living_SDK/platform/mcu/lpc54102/drivers/fsl_flashiap.h
Normal file
|
|
@ -0,0 +1,264 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_FLASHIAP_H_
|
||||
#define _FSL_FLASHIAP_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup flashiap_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_FLASHIAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief Flashiap status codes.
|
||||
*/
|
||||
enum _flashiap_status
|
||||
{
|
||||
kStatus_FLASHIAP_Success = kStatus_Success, /*!< Api is executed successfully */
|
||||
kStatus_FLASHIAP_InvalidCommand = MAKE_STATUS(kStatusGroup_FLASHIAP, 1U), /*!< Invalid command */
|
||||
kStatus_FLASHIAP_SrcAddrError =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 2U), /*!< Source address is not on word boundary */
|
||||
kStatus_FLASHIAP_DstAddrError =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 3U), /*!< Destination address is not on a correct boundary */
|
||||
kStatus_FLASHIAP_SrcAddrNotMapped =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 4U), /*!< Source address is not mapped in the memory map */
|
||||
kStatus_FLASHIAP_DstAddrNotMapped =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 5U), /*!< Destination address is not mapped in the memory map */
|
||||
kStatus_FLASHIAP_CountError =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 6U), /*!< Byte count is not multiple of 4 or is not a permitted value */
|
||||
kStatus_FLASHIAP_InvalidSector =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP,
|
||||
7), /*!< Sector number is invalid or end sector number is greater than start sector number */
|
||||
kStatus_FLASHIAP_SectorNotblank = MAKE_STATUS(kStatusGroup_FLASHIAP, 8U), /*!< One or more sectors are not blank */
|
||||
kStatus_FLASHIAP_NotPrepared =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 9U), /*!< Command to prepare sector for write operation was not executed */
|
||||
kStatus_FLASHIAP_CompareError =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 10U), /*!< Destination and source memory contents do not match */
|
||||
kStatus_FLASHIAP_Busy =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 11U), /*!< Flash programming hardware interface is busy */
|
||||
kStatus_FLASHIAP_ParamError =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 12U), /*!< Insufficient number of parameters or invalid parameter */
|
||||
kStatus_FLASHIAP_AddrError = MAKE_STATUS(kStatusGroup_FLASHIAP, 13U), /*!< Address is not on word boundary */
|
||||
kStatus_FLASHIAP_AddrNotMapped =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 14U), /*!< Address is not mapped in the memory map */
|
||||
kStatus_FLASHIAP_NoPower = MAKE_STATUS(kStatusGroup_FLASHIAP, 24U), /*!< Flash memory block is powered down */
|
||||
kStatus_FLASHIAP_NoClock =
|
||||
MAKE_STATUS(kStatusGroup_FLASHIAP, 27U), /*!< Flash memory block or controller is not clocked */
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief Flashiap command codes.
|
||||
*/
|
||||
enum _flashiap_commands
|
||||
{
|
||||
kIapCmd_FLASHIAP_PrepareSectorforWrite = 50U, /*!< Prepare Sector for write */
|
||||
kIapCmd_FLASHIAP_CopyRamToFlash = 51U, /*!< Copy RAM to flash */
|
||||
kIapCmd_FLASHIAP_EraseSector = 52U, /*!< Erase Sector */
|
||||
kIapCmd_FLASHIAP_BlankCheckSector = 53U, /*!< Blank check sector */
|
||||
kIapCmd_FLASHIAP_ReadPartId = 54U, /*!< Read part id */
|
||||
kIapCmd_FLASHIAP_Read_BootromVersion = 55U, /*!< Read bootrom version */
|
||||
kIapCmd_FLASHIAP_Compare = 56U, /*!< Compare */
|
||||
kIapCmd_FLASHIAP_ReinvokeISP = 57U, /*!< Reinvoke ISP */
|
||||
kIapCmd_FLASHIAP_ReadUid = 58U, /*!< Read Uid isp */
|
||||
kIapCmd_FLASHIAP_ErasePage = 59U, /*!< Erase Page */
|
||||
kIapCmd_FLASHIAP_ReadMisr = 70U, /*!< Read Misr */
|
||||
kIapCmd_FLASHIAP_ReinvokeI2cSpiISP = 71U /*!< Reinvoke I2C/SPI isp */
|
||||
};
|
||||
|
||||
/*! @brief IAP_ENTRY API function type */
|
||||
typedef void (*IAP_ENTRY_T)(uint32_t cmd[5], uint32_t stat[4]);
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief IAP_ENTRY API function type
|
||||
*
|
||||
* Wrapper for rom iap call
|
||||
*
|
||||
* @param cmd_param IAP command and relevant parameter array.
|
||||
* @param status_result IAP status result array.
|
||||
*
|
||||
* @retval None. Status/Result is returned via status_result array.
|
||||
*/
|
||||
static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result)
|
||||
{
|
||||
((IAP_ENTRY_T)FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(cmd_param, status_result);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Prepare sector for write operation
|
||||
|
||||
* This function prepares sector(s) for write/erase operation. This function must be
|
||||
* called before calling the FLASHIAP_CopyRamToFlash() or FLASHIAP_EraseSector() or
|
||||
* FLASHIAP_ErasePage() function. The end sector must be greater than or equal to
|
||||
* start sector number.
|
||||
*
|
||||
* @param startSector Start sector number.
|
||||
* @param endSector End sector number.
|
||||
*
|
||||
* @retval #kStatus_FLASHIAP_Success Api was executed successfully.
|
||||
* @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
|
||||
* @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
|
||||
* @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number
|
||||
* is greater than start sector number.
|
||||
* @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
|
||||
*/
|
||||
status_t FLASHIAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector);
|
||||
|
||||
/*!
|
||||
* @brief Copy RAM to flash.
|
||||
|
||||
* This function programs the flash memory. Corresponding sectors must be prepared
|
||||
* via FLASHIAP_PrepareSectorForWrite before calling calling this function. The addresses
|
||||
* should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096.
|
||||
*
|
||||
* @param dstAddr Destination flash address where data bytes are to be written.
|
||||
* @param srcAddr Source ram address from where data bytes are to be read.
|
||||
* @param numOfBytes Number of bytes to be written.
|
||||
* @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
|
||||
* rom IAP function.
|
||||
*
|
||||
* @retval #kStatus_FLASHIAP_Success Api was executed successfully.
|
||||
* @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
|
||||
* @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
|
||||
* @retval #kStatus_FLASHIAP_SrcAddrError Source address is not on word boundary.
|
||||
* @retval #kStatus_FLASHIAP_DstAddrError Destination address is not on a correct boundary.
|
||||
* @retval #kStatus_FLASHIAP_SrcAddrNotMapped Source address is not mapped in the memory map.
|
||||
* @retval #kStatus_FLASHIAP_DstAddrNotMapped Destination address is not mapped in the memory map.
|
||||
* @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value.
|
||||
* @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
|
||||
* @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
|
||||
*/
|
||||
status_t FLASHIAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock);
|
||||
|
||||
/*!
|
||||
* @brief Erase sector
|
||||
|
||||
* This function erases sector(s). The end sector must be greater than or equal to
|
||||
* start sector number. FLASHIAP_PrepareSectorForWrite must be called before
|
||||
* calling this function.
|
||||
*
|
||||
* @param startSector Start sector number.
|
||||
* @param endSector End sector number.
|
||||
* @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
|
||||
* rom IAP function.
|
||||
*
|
||||
* @retval #kStatus_FLASHIAP_Success Api was executed successfully.
|
||||
* @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
|
||||
* @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
|
||||
* @retval #kStatus_FLASHIAP_InvalidSector Sector number is invalid or end sector number
|
||||
* is greater than start sector number.
|
||||
* @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
|
||||
* @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
|
||||
*/
|
||||
status_t FLASHIAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock);
|
||||
|
||||
/*!
|
||||
|
||||
* This function erases page(s). The end page must be greater than or equal to
|
||||
* start page number. Corresponding sectors must be prepared via FLASHIAP_PrepareSectorForWrite
|
||||
* before calling calling this function.
|
||||
*
|
||||
* @param startPage Start page number
|
||||
* @param endPage End page number
|
||||
* @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
|
||||
* rom IAP function.
|
||||
*
|
||||
* @retval #kStatus_FLASHIAP_Success Api was executed successfully.
|
||||
* @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
|
||||
* @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
|
||||
* @retval #kStatus_FLASHIAP_InvalidSector Page number is invalid or end page number
|
||||
* is greater than start page number
|
||||
* @retval #kStatus_FLASHIAP_NotPrepared Command to prepare sector for write operation was not executed.
|
||||
* @retval #kStatus_FLASHIAP_Busy Flash programming hardware interface is busy.
|
||||
*/
|
||||
status_t FLASHIAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock);
|
||||
|
||||
/*!
|
||||
* @brief Blank check sector(s)
|
||||
*
|
||||
* Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to
|
||||
* start sector number. It can be used to verify the sector eraseure after FLASHIAP_EraseSector call.
|
||||
*
|
||||
* @param startSector : Start sector number. Must be greater than or equal to start sector number
|
||||
* @param endSector : End sector number
|
||||
* @retval #kStatus_FLASHIAP_Success One or more sectors are in erased state.
|
||||
* @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
|
||||
* @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
|
||||
* @retval #kStatus_FLASHIAP_SectorNotblank One or more sectors are not blank.
|
||||
*/
|
||||
status_t FLASHIAP_BlankCheckSector(uint32_t startSector, uint32_t endSector);
|
||||
|
||||
/*!
|
||||
* @brief Compare memory contents of flash with ram.
|
||||
|
||||
* This function compares the contents of flash and ram. It can be used to verify the flash
|
||||
* memory contents after FLASHIAP_CopyRamToFlash call.
|
||||
*
|
||||
* @param dstAddr Destination flash address.
|
||||
* @param srcAddr Source ram address.
|
||||
* @param numOfBytes Number of bytes to be compared.
|
||||
*
|
||||
* @retval #kStatus_FLASHIAP_Success Contents of flash and ram match.
|
||||
* @retval #kStatus_FLASHIAP_NoPower Flash memory block is powered down.
|
||||
* @retval #kStatus_FLASHIAP_NoClock Flash memory block or controller is not clocked.
|
||||
* @retval #kStatus_FLASHIAP_AddrError Address is not on word boundary.
|
||||
* @retval #kStatus_FLASHIAP_AddrNotMapped Address is not mapped in the memory map.
|
||||
* @retval #kStatus_FLASHIAP_CountError Byte count is not multiple of 4 or is not a permitted value.
|
||||
* @retval #kStatus_FLASHIAP_CompareError Destination and source memory contents do not match.
|
||||
*/
|
||||
status_t FLASHIAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _FSL_FLASHIAP_H_ */
|
||||
61
Living_SDK/platform/mcu/lpc54102/drivers/fsl_fmeas.c
Normal file
61
Living_SDK/platform/mcu/lpc54102/drivers/fsl_fmeas.c
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_fmeas.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*! @brief Target clock counter value.
|
||||
* According to user manual, 2 has to be subtracted from captured value (CAPVAL). */
|
||||
#define TARGET_CLOCK_COUNT(base) \
|
||||
((uint32_t)( \
|
||||
((((SYSCON_Type *)base)->FREQMECTRL & SYSCON_FREQMECTRL_CAPVAL_MASK) >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) - 2))
|
||||
|
||||
/*! @brief Reference clock counter value. */
|
||||
#define REFERENCE_CLOCK_COUNT ((uint32_t)((SYSCON_FREQMECTRL_CAPVAL_MASK >> SYSCON_FREQMECTRL_CAPVAL_SHIFT) + 1))
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate)
|
||||
{
|
||||
uint32_t targetClockCount = TARGET_CLOCK_COUNT(base);
|
||||
uint64_t clkrate = 0;
|
||||
|
||||
if (targetClockCount > 0)
|
||||
{
|
||||
clkrate = (((uint64_t)targetClockCount) * (uint64_t)refClockRate) / REFERENCE_CLOCK_COUNT;
|
||||
}
|
||||
|
||||
return (uint32_t)clkrate;
|
||||
}
|
||||
110
Living_SDK/platform/mcu/lpc54102/drivers/fsl_fmeas.h
Normal file
110
Living_SDK/platform/mcu/lpc54102/drivers/fsl_fmeas.h
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_FMEAS_H_
|
||||
#define _FSL_FMEAS_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup fmeas
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief Defines LPC Frequency Measure driver version 2.0.0.
|
||||
*
|
||||
* Change log:
|
||||
* - Version 2.0.0
|
||||
* - initial version
|
||||
*/
|
||||
#define FSL_FMEAS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
*******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*!
|
||||
* @name FMEAS Functional Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Starts a frequency measurement cycle.
|
||||
*
|
||||
* @param base : SYSCON peripheral base address.
|
||||
*/
|
||||
static inline void FMEAS_StartMeasure(SYSCON_Type *base)
|
||||
{
|
||||
base->FREQMECTRL = 0;
|
||||
base->FREQMECTRL = (1UL << 31);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Indicates when a frequency measurement cycle is complete.
|
||||
*
|
||||
* @param base : SYSCON peripheral base address.
|
||||
* @return true if a measurement cycle is active, otherwise false.
|
||||
*/
|
||||
static inline bool FMEAS_IsMeasureComplete(SYSCON_Type *base)
|
||||
{
|
||||
return (bool)((base->FREQMECTRL & (1UL << 31)) == 0);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Returns the computed value for a frequency measurement cycle
|
||||
*
|
||||
* @param base : SYSCON peripheral base address.
|
||||
* @param refClockRate : Reference clock rate used during the frequency measurement cycle.
|
||||
*
|
||||
* @return Frequency in Hz.
|
||||
*/
|
||||
uint32_t FMEAS_GetFrequency(SYSCON_Type *base, uint32_t refClockRate);
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_FMEAS_H_ */
|
||||
311
Living_SDK/platform/mcu/lpc54102/drivers/fsl_gint.c
Normal file
311
Living_SDK/platform/mcu/lpc54102/drivers/fsl_gint.c
Normal file
|
|
@ -0,0 +1,311 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_gint.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to GINT bases for each instance. */
|
||||
static GINT_Type *const s_gintBases[FSL_FEATURE_SOC_GINT_COUNT] = GINT_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Clocks for each instance. */
|
||||
static const clock_ip_name_t s_gintClocks[FSL_FEATURE_SOC_GINT_COUNT] = GINT_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*! @brief Resets for each instance. */
|
||||
static const reset_ip_name_t s_gintResets[FSL_FEATURE_SOC_GINT_COUNT] = GINT_RSTS;
|
||||
|
||||
/* @brief Irq number for each instance */
|
||||
static const IRQn_Type s_gintIRQ[FSL_FEATURE_SOC_GINT_COUNT] = GINT_IRQS;
|
||||
|
||||
/*! @brief Callback function array for GINT(s). */
|
||||
static gint_cb_t s_gintCallback[FSL_FEATURE_SOC_GINT_COUNT];
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static uint32_t GINT_GetInstance(GINT_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_gintBases); instance++)
|
||||
{
|
||||
if (s_gintBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_gintBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void GINT_Init(GINT_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
instance = GINT_GetInstance(base);
|
||||
|
||||
s_gintCallback[instance] = NULL;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the peripheral clock */
|
||||
CLOCK_EnableClock(s_gintClocks[instance]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Reset the peripheral */
|
||||
RESET_PeripheralReset(s_gintResets[instance]);
|
||||
}
|
||||
|
||||
void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
instance = GINT_GetInstance(base);
|
||||
|
||||
base->CTRL = (GINT_CTRL_COMB(comb) | GINT_CTRL_TRIG(trig));
|
||||
|
||||
/* Save callback pointer */
|
||||
s_gintCallback[instance] = callback;
|
||||
}
|
||||
|
||||
void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
instance = GINT_GetInstance(base);
|
||||
|
||||
*comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT);
|
||||
*trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT);
|
||||
*callback = s_gintCallback[instance];
|
||||
}
|
||||
|
||||
void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask)
|
||||
{
|
||||
base->PORT_POL[port] = polarityMask;
|
||||
base->PORT_ENA[port] = enableMask;
|
||||
}
|
||||
|
||||
void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask)
|
||||
{
|
||||
*polarityMask = base->PORT_POL[port];
|
||||
*enableMask = base->PORT_ENA[port];
|
||||
}
|
||||
|
||||
void GINT_EnableCallback(GINT_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
instance = GINT_GetInstance(base);
|
||||
/* If GINT is configured in "AND" mode a spurious interrupt is generated.
|
||||
Clear status and pending interrupt before enabling the irq in NVIC. */
|
||||
GINT_ClrStatus(base);
|
||||
NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
|
||||
EnableIRQ(s_gintIRQ[instance]);
|
||||
}
|
||||
|
||||
void GINT_DisableCallback(GINT_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
instance = GINT_GetInstance(base);
|
||||
DisableIRQ(s_gintIRQ[instance]);
|
||||
GINT_ClrStatus(base);
|
||||
NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
|
||||
}
|
||||
|
||||
void GINT_Deinit(GINT_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
instance = GINT_GetInstance(base);
|
||||
|
||||
/* Cleanup */
|
||||
GINT_DisableCallback(base);
|
||||
s_gintCallback[instance] = NULL;
|
||||
|
||||
/* Reset the peripheral */
|
||||
RESET_PeripheralReset(s_gintResets[instance]);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the peripheral clock */
|
||||
CLOCK_DisableClock(s_gintClocks[instance]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
/* IRQ handler functions overloading weak symbols in the startup */
|
||||
#if defined(GINT0)
|
||||
void GINT0_DriverIRQHandler(void)
|
||||
{
|
||||
/* Clear interrupt before callback */
|
||||
s_gintBases[0]->CTRL |= GINT_CTRL_INT_MASK;
|
||||
/* Call user function */
|
||||
if (s_gintCallback[0] != NULL)
|
||||
{
|
||||
s_gintCallback[0]();
|
||||
}
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(GINT1)
|
||||
void GINT1_DriverIRQHandler(void)
|
||||
{
|
||||
/* Clear interrupt before callback */
|
||||
s_gintBases[1]->CTRL |= GINT_CTRL_INT_MASK;
|
||||
/* Call user function */
|
||||
if (s_gintCallback[1] != NULL)
|
||||
{
|
||||
s_gintCallback[1]();
|
||||
}
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(GINT2)
|
||||
void GINT2_DriverIRQHandler(void)
|
||||
{
|
||||
/* Clear interrupt before callback */
|
||||
s_gintBases[2]->CTRL |= GINT_CTRL_INT_MASK;
|
||||
/* Call user function */
|
||||
if (s_gintCallback[2] != NULL)
|
||||
{
|
||||
s_gintCallback[2]();
|
||||
}
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(GINT3)
|
||||
void GINT3_DriverIRQHandler(void)
|
||||
{
|
||||
/* Clear interrupt before callback */
|
||||
s_gintBases[3]->CTRL |= GINT_CTRL_INT_MASK;
|
||||
/* Call user function */
|
||||
if (s_gintCallback[3] != NULL)
|
||||
{
|
||||
s_gintCallback[3]();
|
||||
}
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(GINT4)
|
||||
void GINT4_DriverIRQHandler(void)
|
||||
{
|
||||
/* Clear interrupt before callback */
|
||||
s_gintBases[4]->CTRL |= GINT_CTRL_INT_MASK;
|
||||
/* Call user function */
|
||||
if (s_gintCallback[4] != NULL)
|
||||
{
|
||||
s_gintCallback[4]();
|
||||
}
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(GINT5)
|
||||
void GINT5_DriverIRQHandler(void)
|
||||
{
|
||||
/* Clear interrupt before callback */
|
||||
s_gintBases[5]->CTRL |= GINT_CTRL_INT_MASK;
|
||||
/* Call user function */
|
||||
if (s_gintCallback[5] != NULL)
|
||||
{
|
||||
s_gintCallback[5]();
|
||||
}
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(GINT6)
|
||||
void GINT6_DriverIRQHandler(void)
|
||||
{
|
||||
/* Clear interrupt before callback */
|
||||
s_gintBases[6]->CTRL |= GINT_CTRL_INT_MASK;
|
||||
/* Call user function */
|
||||
if (s_gintCallback[6] != NULL)
|
||||
{
|
||||
s_gintCallback[6]();
|
||||
}
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(GINT7)
|
||||
void GINT7_DriverIRQHandler(void)
|
||||
{
|
||||
/* Clear interrupt before callback */
|
||||
s_gintBases[7]->CTRL |= GINT_CTRL_INT_MASK;
|
||||
/* Call user function */
|
||||
if (s_gintCallback[7] != NULL)
|
||||
{
|
||||
s_gintCallback[7]();
|
||||
}
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
244
Living_SDK/platform/mcu/lpc54102/drivers/fsl_gint.h
Normal file
244
Living_SDK/platform/mcu/lpc54102/drivers/fsl_gint.h
Normal file
|
|
@ -0,0 +1,244 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_GINT_H_
|
||||
#define _FSL_GINT_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup gint_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
/*@}*/
|
||||
|
||||
/*! @brief GINT combine inputs type */
|
||||
typedef enum _gint_comb
|
||||
{
|
||||
kGINT_CombineOr = 0U, /*!< A grouped interrupt is generated when any one of the enabled inputs is active */
|
||||
kGINT_CombineAnd = 1U /*!< A grouped interrupt is generated when all enabled inputs are active */
|
||||
} gint_comb_t;
|
||||
|
||||
/*! @brief GINT trigger type */
|
||||
typedef enum _gint_trig
|
||||
{
|
||||
kGINT_TrigEdge = 0U, /*!< Edge triggered based on polarity */
|
||||
kGINT_TrigLevel = 1U /*!< Level triggered based on polarity */
|
||||
} gint_trig_t;
|
||||
|
||||
/* @brief GINT port type */
|
||||
typedef enum _gint_port
|
||||
{
|
||||
kGINT_Port0 = 0U,
|
||||
kGINT_Port1 = 1U,
|
||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 2U)
|
||||
kGINT_Port2 = 2U,
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 3U)
|
||||
kGINT_Port3 = 3U,
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 4U)
|
||||
kGINT_Port4 = 4U,
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 5U)
|
||||
kGINT_Port5 = 5U,
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 6U)
|
||||
kGINT_Port6 = 6U,
|
||||
#endif
|
||||
#if defined(FSL_FEATURE_GINT_PORT_COUNT) && (FSL_FEATURE_GINT_PORT_COUNT > 7U)
|
||||
kGINT_Port7 = 7U,
|
||||
#endif
|
||||
} gint_port_t;
|
||||
|
||||
/*! @brief GINT Callback function. */
|
||||
typedef void (*gint_cb_t)(void);
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Initialize GINT peripheral.
|
||||
|
||||
* This function initializes the GINT peripheral and enables the clock.
|
||||
*
|
||||
* @param base Base address of the GINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void GINT_Init(GINT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Setup GINT peripheral control parameters.
|
||||
|
||||
* This function sets the control parameters of GINT peripheral.
|
||||
*
|
||||
* @param base Base address of the GINT peripheral.
|
||||
* @param comb Controls if the enabled inputs are logically ORed or ANDed for interrupt generation.
|
||||
* @param trig Controls if the enabled inputs are level or edge sensitive based on polarity.
|
||||
* @param callback This function is called when configured group interrupt is generated.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t callback);
|
||||
|
||||
/*!
|
||||
* @brief Get GINT peripheral control parameters.
|
||||
|
||||
* This function returns the control parameters of GINT peripheral.
|
||||
*
|
||||
* @param base Base address of the GINT peripheral.
|
||||
* @param comb Pointer to store combine input value.
|
||||
* @param trig Pointer to store trigger value.
|
||||
* @param callback Pointer to store callback function.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback);
|
||||
|
||||
/*!
|
||||
* @brief Configure GINT peripheral pins.
|
||||
|
||||
* This function enables and controls the polarity of enabled pin(s) of a given port.
|
||||
*
|
||||
* @param base Base address of the GINT peripheral.
|
||||
* @param port Port number.
|
||||
* @param polarityMask Each bit position selects the polarity of the corresponding enabled pin.
|
||||
* 0 = The pin is active LOW. 1 = The pin is active HIGH.
|
||||
* @param enableMask Each bit position selects if the corresponding pin is enabled or not.
|
||||
* 0 = The pin is disabled. 1 = The pin is enabled.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void GINT_ConfigPins(GINT_Type *base, gint_port_t port, uint32_t polarityMask, uint32_t enableMask);
|
||||
|
||||
/*!
|
||||
* @brief Get GINT peripheral pin configuration.
|
||||
|
||||
* This function returns the pin configuration of a given port.
|
||||
*
|
||||
* @param base Base address of the GINT peripheral.
|
||||
* @param port Port number.
|
||||
* @param polarityMask Pointer to store the polarity mask Each bit position indicates the polarity of the corresponding
|
||||
enabled pin.
|
||||
* 0 = The pin is active LOW. 1 = The pin is active HIGH.
|
||||
* @param enableMask Pointer to store the enable mask. Each bit position indicates if the corresponding pin is enabled
|
||||
or not.
|
||||
* 0 = The pin is disabled. 1 = The pin is enabled.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void GINT_GetConfigPins(GINT_Type *base, gint_port_t port, uint32_t *polarityMask, uint32_t *enableMask);
|
||||
|
||||
/*!
|
||||
* @brief Enable callback.
|
||||
|
||||
* This function enables the interrupt for the selected GINT peripheral. Although the pin(s) are monitored
|
||||
* as soon as they are enabled, the callback function is not enabled until this function is called.
|
||||
*
|
||||
* @param base Base address of the GINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void GINT_EnableCallback(GINT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Disable callback.
|
||||
|
||||
* This function disables the interrupt for the selected GINT peripheral. Although the pins are still
|
||||
* being monitored but the callback function is not called.
|
||||
*
|
||||
* @param base Base address of the peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void GINT_DisableCallback(GINT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Clear GINT status.
|
||||
|
||||
* This function clears the GINT status bit.
|
||||
*
|
||||
* @param base Base address of the GINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void GINT_ClrStatus(GINT_Type *base)
|
||||
{
|
||||
base->CTRL |= GINT_CTRL_INT_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get GINT status.
|
||||
|
||||
* This function returns the GINT status.
|
||||
*
|
||||
* @param base Base address of the GINT peripheral.
|
||||
*
|
||||
* @retval status = 0 No group interrupt request. = 1 Group interrupt request active.
|
||||
*/
|
||||
static inline uint32_t GINT_GetStatus(GINT_Type *base)
|
||||
{
|
||||
return (base->CTRL & GINT_CTRL_INT_MASK);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Deinitialize GINT peripheral.
|
||||
|
||||
* This function disables the GINT clock.
|
||||
*
|
||||
* @param base Base address of the GINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void GINT_Deinit(GINT_Type *base);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _FSL_GINT_H_ */
|
||||
77
Living_SDK/platform/mcu/lpc54102/drivers/fsl_gpio.c
Normal file
77
Living_SDK/platform/mcu/lpc54102/drivers/fsl_gpio.c
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_gpio.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Array to map FGPIO instance number to clock name. */
|
||||
static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
************ ******************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
void GPIO_PortInit(GPIO_Type *base, uint32_t port)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
assert(port < ARRAY_SIZE(s_gpioClockName));
|
||||
|
||||
/* Upgate the GPIO clock */
|
||||
CLOCK_EnableClock(s_gpioClockName[port]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
|
||||
{
|
||||
if (config->pinDirection == kGPIO_DigitalInput)
|
||||
{
|
||||
base->DIR[port] &= ~(1U << pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set default output value */
|
||||
if (config->outputLogic == 0U)
|
||||
{
|
||||
base->CLR[port] = (1U << pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->SET[port] = (1U << pin);
|
||||
}
|
||||
/* Set pin direction */
|
||||
base->DIR[port] |= 1U << pin;
|
||||
}
|
||||
}
|
||||
351
Living_SDK/platform/mcu/lpc54102/drivers/fsl_gpio.h
Normal file
351
Living_SDK/platform/mcu/lpc54102/drivers/fsl_gpio.h
Normal file
|
|
@ -0,0 +1,351 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _LPC_GPIO_H_
|
||||
#define _LPC_GPIO_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup lpc_gpio
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief LPC GPIO driver version 2.1.1. */
|
||||
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief LPC GPIO direction definition */
|
||||
typedef enum _gpio_pin_direction
|
||||
{
|
||||
kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
|
||||
kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
|
||||
} gpio_pin_direction_t;
|
||||
|
||||
/*!
|
||||
* @brief The GPIO pin configuration structure.
|
||||
*
|
||||
* Every pin can only be configured as either output pin or input pin at a time.
|
||||
* If configured as a input pin, then leave the outputConfig unused.
|
||||
*/
|
||||
typedef struct _gpio_pin_config
|
||||
{
|
||||
gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
|
||||
/* Output configurations, please ignore if configured as a input one */
|
||||
uint8_t outputLogic; /*!< Set default output logic, no use in input */
|
||||
} gpio_pin_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*! @name GPIO Configuration */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the GPIO peripheral.
|
||||
*
|
||||
* This function ungates the GPIO clock.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer.
|
||||
* @param port GPIO port number.
|
||||
*/
|
||||
void GPIO_PortInit(GPIO_Type *base, uint32_t port);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the GPIO peripheral.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortInit.
|
||||
*/
|
||||
static inline void GPIO_Init(GPIO_Type *base, uint32_t port)
|
||||
{
|
||||
GPIO_PortInit(base, port);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Initializes a GPIO pin used by the board.
|
||||
*
|
||||
* To initialize the GPIO, define a pin configuration, either input or output, in the user file.
|
||||
* Then, call the GPIO_PinInit() function.
|
||||
*
|
||||
* This is an example to define an input pin or output pin configuration:
|
||||
* @code
|
||||
* // Define a digital input pin configuration,
|
||||
* gpio_pin_config_t config =
|
||||
* {
|
||||
* kGPIO_DigitalInput,
|
||||
* 0,
|
||||
* }
|
||||
* //Define a digital output pin configuration,
|
||||
* gpio_pin_config_t config =
|
||||
* {
|
||||
* kGPIO_DigitalOutput,
|
||||
* 0,
|
||||
* }
|
||||
* @endcode
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
||||
* @param port GPIO port number
|
||||
* @param pin GPIO pin number
|
||||
* @param config GPIO pin configuration pointer
|
||||
*/
|
||||
void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
|
||||
|
||||
/*@}*/
|
||||
|
||||
/*! @name GPIO Output Operations */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
||||
* @param port GPIO port number
|
||||
* @param pin GPIO pin number
|
||||
* @param output GPIO pin output logic level.
|
||||
* - 0: corresponding pin output low-logic level.
|
||||
* - 1: corresponding pin output high-logic level.
|
||||
*/
|
||||
static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
|
||||
{
|
||||
base->B[port][pin] = output;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite.
|
||||
*/
|
||||
static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
|
||||
{
|
||||
base->B[port][pin] = output;
|
||||
}
|
||||
/*@}*/
|
||||
/*! @name GPIO Input Operations */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Reads the current input value of the GPIO PIN.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
||||
* @param port GPIO port number
|
||||
* @param pin GPIO pin number
|
||||
* @retval GPIO port input value
|
||||
* - 0: corresponding pin input low-logic level.
|
||||
* - 1: corresponding pin input high-logic level.
|
||||
*/
|
||||
static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)
|
||||
{
|
||||
return (uint32_t)base->B[port][pin];
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads the current input value of the GPIO PIN.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead.
|
||||
*/
|
||||
static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin)
|
||||
{
|
||||
return GPIO_PinRead(base, port, pin);
|
||||
}
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 1.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
||||
* @param port GPIO port number
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
|
||||
{
|
||||
base->SET[port] = mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 1.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet.
|
||||
*/
|
||||
static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
|
||||
{
|
||||
GPIO_PortSet(base, port, mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 0.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
||||
* @param port GPIO port number
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
|
||||
{
|
||||
base->CLR[port] = mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the multiple GPIO pins to the logic 0.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear.
|
||||
*/
|
||||
static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
|
||||
{
|
||||
GPIO_PortClear(base, port, mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reverses current output logic of the multiple GPIO pins.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
||||
* @param port GPIO port number
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
|
||||
{
|
||||
base->NOT[port] = mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reverses current output logic of the multiple GPIO pins.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortToggle.
|
||||
*/
|
||||
static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
|
||||
{
|
||||
GPIO_PortToggle(base, port, mask);
|
||||
}
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief Reads the current input value of the whole GPIO port.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
||||
* @param port GPIO port number
|
||||
*/
|
||||
static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)
|
||||
{
|
||||
return (uint32_t)base->PIN[port];
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads the current input value of the whole GPIO port.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortRead
|
||||
*/
|
||||
static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port)
|
||||
{
|
||||
return GPIO_PortRead(base, port);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
/*! @name GPIO Mask Operations */
|
||||
/*@{*/
|
||||
|
||||
/*!
|
||||
* @brief Sets port mask, 0 - enable pin, 1 - disable pin.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
||||
* @param port GPIO port number
|
||||
* @param mask GPIO pin number macro
|
||||
*/
|
||||
static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)
|
||||
{
|
||||
base->MASK[port] = mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets port mask, 0 - enable pin, 1 - disable pin.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedSet.
|
||||
*/
|
||||
static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask)
|
||||
{
|
||||
GPIO_PortMaskedSet(base, port, mask);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
||||
* @param port GPIO port number
|
||||
* @param output GPIO port output value.
|
||||
*/
|
||||
static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)
|
||||
{
|
||||
base->MPIN[port] = output;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedWrite.
|
||||
*/
|
||||
static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output)
|
||||
{
|
||||
GPIO_PortMaskedWrite(base, port, output);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
|
||||
* affected.
|
||||
*
|
||||
* @param base GPIO peripheral base pointer(Typically GPIO)
|
||||
* @param port GPIO port number
|
||||
* @retval masked GPIO port value
|
||||
*/
|
||||
static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
|
||||
{
|
||||
return (uint32_t)base->MPIN[port];
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
|
||||
* affected.
|
||||
* @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedRead.
|
||||
*/
|
||||
static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port)
|
||||
{
|
||||
return GPIO_PortMaskedRead(base, port);
|
||||
}
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* _LPC_GPIO_H_*/
|
||||
1561
Living_SDK/platform/mcu/lpc54102/drivers/fsl_i2c.c
Normal file
1561
Living_SDK/platform/mcu/lpc54102/drivers/fsl_i2c.c
Normal file
File diff suppressed because it is too large
Load diff
1052
Living_SDK/platform/mcu/lpc54102/drivers/fsl_i2c.h
Normal file
1052
Living_SDK/platform/mcu/lpc54102/drivers/fsl_i2c.h
Normal file
File diff suppressed because it is too large
Load diff
589
Living_SDK/platform/mcu/lpc54102/drivers/fsl_i2c_dma.c
Normal file
589
Living_SDK/platform/mcu/lpc54102/drivers/fsl_i2c_dma.c
Normal file
|
|
@ -0,0 +1,589 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_i2c_dma.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*<! @brief Structure definition for i2c_master_dma_handle_t. The structure is private. */
|
||||
typedef struct _i2c_master_dma_private_handle
|
||||
{
|
||||
I2C_Type *base;
|
||||
i2c_master_dma_handle_t *handle;
|
||||
} i2c_master_dma_private_handle_t;
|
||||
|
||||
/*! @brief Typedef for interrupt handler. */
|
||||
typedef void (*i2c_isr_t)(I2C_Type *base, void *i2cHandle);
|
||||
|
||||
extern i2c_isr_t s_i2cMasterIsr;
|
||||
extern void *s_i2cHandle[FSL_FEATURE_SOC_I2C_COUNT];
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief DMA callback for I2C master DMA driver.
|
||||
*
|
||||
* @param handle DMA handler for I2C master DMA driver
|
||||
* @param userData user param passed to the callback function
|
||||
*/
|
||||
static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData);
|
||||
|
||||
/*!
|
||||
* @brief Set up master transfer, send slave address and sub address(if any), wait until the
|
||||
* wait until address sent status return.
|
||||
*
|
||||
* @param base I2C peripheral base address.
|
||||
* @param handle pointer to i2c_master_dma_handle_t structure which stores the transfer state.
|
||||
* @param xfer pointer to i2c_master_transfer_t structure.
|
||||
*/
|
||||
static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
|
||||
i2c_master_dma_handle_t *handle,
|
||||
i2c_master_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Get the I2C instance from peripheral base address.
|
||||
*
|
||||
* @param base I2C peripheral base address.
|
||||
* @return I2C instance.
|
||||
*/
|
||||
extern uint32_t I2C_GetInstance(I2C_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*<! Private handle only used for internally. */
|
||||
static i2c_master_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_I2C_COUNT];
|
||||
|
||||
/*! @brief IRQ name array */
|
||||
static const IRQn_Type s_i2cIRQ[] = I2C_IRQS;
|
||||
/*******************************************************************************
|
||||
* Codes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief Prepares the transfer state machine and fills in the command buffer.
|
||||
* @param handle Master nonblocking driver handle.
|
||||
*/
|
||||
static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base,
|
||||
i2c_master_dma_handle_t *handle,
|
||||
i2c_master_transfer_t *xfer)
|
||||
{
|
||||
struct _i2c_master_transfer *transfer;
|
||||
|
||||
handle->transfer = *xfer;
|
||||
transfer = &(handle->transfer);
|
||||
|
||||
handle->transferCount = 0;
|
||||
handle->remainingBytesDMA = 0;
|
||||
handle->buf = (uint8_t *)transfer->data;
|
||||
handle->remainingSubaddr = 0;
|
||||
|
||||
if (transfer->flags & kI2C_TransferNoStartFlag)
|
||||
{
|
||||
/* Start condition shall be ommited, switch directly to next phase */
|
||||
if (transfer->dataSize == 0)
|
||||
{
|
||||
handle->state = kStopState;
|
||||
}
|
||||
else if (handle->transfer.direction == kI2C_Write)
|
||||
{
|
||||
handle->state = xfer->dataSize = kTransmitDataState;
|
||||
}
|
||||
else if (handle->transfer.direction == kI2C_Read)
|
||||
{
|
||||
handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState;
|
||||
}
|
||||
else
|
||||
{
|
||||
return kStatus_I2C_InvalidParameter;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (transfer->subaddressSize != 0)
|
||||
{
|
||||
int i;
|
||||
uint32_t subaddress;
|
||||
|
||||
if (transfer->subaddressSize > sizeof(handle->subaddrBuf))
|
||||
{
|
||||
return kStatus_I2C_InvalidParameter;
|
||||
}
|
||||
|
||||
/* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */
|
||||
subaddress = xfer->subaddress;
|
||||
for (i = xfer->subaddressSize - 1; i >= 0; i--)
|
||||
{
|
||||
handle->subaddrBuf[i] = subaddress & 0xff;
|
||||
subaddress >>= 8;
|
||||
}
|
||||
handle->remainingSubaddr = transfer->subaddressSize;
|
||||
}
|
||||
|
||||
handle->state = kStartState;
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle)
|
||||
{
|
||||
int transfer_size;
|
||||
dma_transfer_config_t xferConfig;
|
||||
|
||||
/* Update transfer count */
|
||||
handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data;
|
||||
|
||||
/* Check if there is anything to be transferred at all */
|
||||
if (handle->remainingBytesDMA == 0)
|
||||
{
|
||||
/* No data to be transferrred, disable DMA */
|
||||
base->MSTCTL = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/* Calculate transfer size */
|
||||
transfer_size = handle->remainingBytesDMA;
|
||||
if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT)
|
||||
{
|
||||
transfer_size = I2C_MAX_DMA_TRANSFER_COUNT;
|
||||
}
|
||||
|
||||
switch (handle->transfer.direction)
|
||||
{
|
||||
case kI2C_Write:
|
||||
DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size,
|
||||
kDMA_MemoryToPeripheral, NULL);
|
||||
break;
|
||||
|
||||
case kI2C_Read:
|
||||
DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size,
|
||||
kDMA_PeripheralToMemory, NULL);
|
||||
break;
|
||||
|
||||
default:
|
||||
/* This should never happen */
|
||||
assert(0);
|
||||
break;
|
||||
}
|
||||
|
||||
DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
|
||||
DMA_StartTransfer(handle->dmaHandle);
|
||||
|
||||
handle->remainingBytesDMA -= transfer_size;
|
||||
handle->buf += transfer_size;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Execute states until the transfer is done.
|
||||
* @param handle Master nonblocking driver handle.
|
||||
* @param[out] isDone Set to true if the transfer has completed.
|
||||
* @retval #kStatus_Success
|
||||
* @retval #kStatus_I2C_ArbitrationLost
|
||||
* @retval #kStatus_I2C_Nak
|
||||
*/
|
||||
static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone)
|
||||
{
|
||||
uint32_t status;
|
||||
uint32_t master_state;
|
||||
struct _i2c_master_transfer *transfer;
|
||||
dma_transfer_config_t xferConfig;
|
||||
status_t err;
|
||||
uint32_t start_flag = 0;
|
||||
|
||||
transfer = &(handle->transfer);
|
||||
|
||||
*isDone = false;
|
||||
|
||||
status = I2C_GetStatusFlags(base);
|
||||
|
||||
if (status & I2C_STAT_MSTARBLOSS_MASK)
|
||||
{
|
||||
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK);
|
||||
DMA_AbortTransfer(handle->dmaHandle);
|
||||
base->MSTCTL = 0;
|
||||
return kStatus_I2C_ArbitrationLost;
|
||||
}
|
||||
|
||||
if (status & I2C_STAT_MSTSTSTPERR_MASK)
|
||||
{
|
||||
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK);
|
||||
DMA_AbortTransfer(handle->dmaHandle);
|
||||
base->MSTCTL = 0;
|
||||
return kStatus_I2C_StartStopError;
|
||||
}
|
||||
|
||||
if ((status & I2C_STAT_MSTPENDING_MASK) == 0)
|
||||
{
|
||||
return kStatus_I2C_Busy;
|
||||
}
|
||||
|
||||
/* Get the state of the I2C module */
|
||||
master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
|
||||
|
||||
if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT))
|
||||
{
|
||||
/* Slave NACKed last byte, issue stop and return error */
|
||||
DMA_AbortTransfer(handle->dmaHandle);
|
||||
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
|
||||
handle->state = kWaitForCompletionState;
|
||||
return kStatus_I2C_Nak;
|
||||
}
|
||||
|
||||
err = kStatus_Success;
|
||||
|
||||
if (handle->state == kStartState)
|
||||
{
|
||||
/* set start flag for later use */
|
||||
start_flag = I2C_MSTCTL_MSTSTART_MASK;
|
||||
|
||||
if (handle->remainingSubaddr)
|
||||
{
|
||||
base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
|
||||
handle->state = kTransmitSubaddrState;
|
||||
}
|
||||
else if (transfer->direction == kI2C_Write)
|
||||
{
|
||||
base->MSTDAT = (uint32_t)transfer->slaveAddress << 1;
|
||||
if (transfer->dataSize == 0)
|
||||
{
|
||||
/* No data to be transferred, initiate start and schedule stop */
|
||||
base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
|
||||
handle->state = kStopState;
|
||||
return err;
|
||||
}
|
||||
handle->state = kTransmitDataState;
|
||||
}
|
||||
else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0))
|
||||
{
|
||||
base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u;
|
||||
if (transfer->dataSize == 1)
|
||||
{
|
||||
/* The very last byte is always received by means of SW */
|
||||
base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK;
|
||||
handle->state = kReceiveLastDataState;
|
||||
return err;
|
||||
}
|
||||
handle->state = kReceiveDataState;
|
||||
}
|
||||
else
|
||||
{
|
||||
handle->state = kIdleState;
|
||||
err = kStatus_I2C_UnexpectedState;
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
switch (handle->state)
|
||||
{
|
||||
case kTransmitSubaddrState:
|
||||
if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
|
||||
{
|
||||
return kStatus_I2C_UnexpectedState;
|
||||
}
|
||||
|
||||
base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
|
||||
|
||||
/* Prepare and submit DMA transfer. */
|
||||
DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t),
|
||||
handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL);
|
||||
DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
|
||||
DMA_StartTransfer(handle->dmaHandle);
|
||||
handle->remainingSubaddr = 0;
|
||||
if (transfer->dataSize)
|
||||
{
|
||||
/* There is data to be transferred, if there is write to read turnaround it is necessary to perform
|
||||
* repeated start */
|
||||
handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No more data, schedule stop condition */
|
||||
handle->state = kStopState;
|
||||
}
|
||||
break;
|
||||
|
||||
case kTransmitDataState:
|
||||
if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag))
|
||||
{
|
||||
return kStatus_I2C_UnexpectedState;
|
||||
}
|
||||
|
||||
base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
|
||||
handle->remainingBytesDMA = handle->transfer.dataSize;
|
||||
|
||||
I2C_RunDMATransfer(base, handle);
|
||||
|
||||
/* Schedule stop condition */
|
||||
handle->state = kStopState;
|
||||
break;
|
||||
|
||||
case kReceiveDataState:
|
||||
if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag))
|
||||
{
|
||||
return kStatus_I2C_UnexpectedState;
|
||||
}
|
||||
|
||||
base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK;
|
||||
handle->remainingBytesDMA = handle->transfer.dataSize - 1;
|
||||
|
||||
I2C_RunDMATransfer(base, handle);
|
||||
|
||||
/* Schedule reception of last data byte */
|
||||
handle->state = kReceiveLastDataState;
|
||||
break;
|
||||
|
||||
case kReceiveLastDataState:
|
||||
if (master_state != I2C_STAT_MSTCODE_RXREADY)
|
||||
{
|
||||
return kStatus_I2C_UnexpectedState;
|
||||
}
|
||||
|
||||
((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT;
|
||||
handle->transferCount++;
|
||||
|
||||
/* No more data expected, issue NACK and STOP right away */
|
||||
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
|
||||
handle->state = kWaitForCompletionState;
|
||||
break;
|
||||
|
||||
case kStopState:
|
||||
if (transfer->flags & kI2C_TransferNoStopFlag)
|
||||
{
|
||||
/* Stop condition is omitted, we are done */
|
||||
*isDone = true;
|
||||
handle->state = kIdleState;
|
||||
break;
|
||||
}
|
||||
/* Send stop condition */
|
||||
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
|
||||
handle->state = kWaitForCompletionState;
|
||||
break;
|
||||
|
||||
case kWaitForCompletionState:
|
||||
*isDone = true;
|
||||
handle->state = kIdleState;
|
||||
break;
|
||||
|
||||
case kStartState:
|
||||
case kIdleState:
|
||||
default:
|
||||
/* State machine shall not be invoked again once it enters the idle state */
|
||||
err = kStatus_I2C_UnexpectedState;
|
||||
break;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, void *i2cHandle)
|
||||
{
|
||||
assert(i2cHandle);
|
||||
|
||||
bool isDone;
|
||||
status_t result;
|
||||
i2c_master_dma_handle_t *handle = (i2c_master_dma_handle_t *)i2cHandle;
|
||||
|
||||
/* Don't do anything if we don't have a valid handle. */
|
||||
if (!handle)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
result = I2C_RunTransferStateMachineDMA(base, handle, &isDone);
|
||||
|
||||
if (isDone || (result != kStatus_Success))
|
||||
{
|
||||
/* Disable internal IRQ enables. */
|
||||
I2C_DisableInterrupts(base,
|
||||
I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
|
||||
|
||||
/* Invoke callback. */
|
||||
if (handle->completionCallback)
|
||||
{
|
||||
handle->completionCallback(base, handle, result, handle->userData);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData)
|
||||
{
|
||||
i2c_master_dma_private_handle_t *dmaPrivateHandle;
|
||||
|
||||
/* Don't do anything if we don't have a valid handle. */
|
||||
if (!handle)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
dmaPrivateHandle = (i2c_master_dma_private_handle_t *)userData;
|
||||
I2C_RunDMATransfer(dmaPrivateHandle->base, dmaPrivateHandle->handle);
|
||||
}
|
||||
|
||||
void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
|
||||
i2c_master_dma_handle_t *handle,
|
||||
i2c_master_dma_transfer_callback_t callback,
|
||||
void *userData,
|
||||
dma_handle_t *dmaHandle)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
assert(handle);
|
||||
assert(dmaHandle);
|
||||
|
||||
/* Zero handle. */
|
||||
memset(handle, 0, sizeof(*handle));
|
||||
|
||||
/* Look up instance number */
|
||||
instance = I2C_GetInstance(base);
|
||||
|
||||
/* Set the user callback and userData. */
|
||||
handle->completionCallback = callback;
|
||||
handle->userData = userData;
|
||||
|
||||
/* Save the context in global variables to support the double weak mechanism. */
|
||||
s_i2cHandle[instance] = handle;
|
||||
|
||||
/* Save master interrupt handler. */
|
||||
s_i2cMasterIsr = I2C_MasterTransferDMAHandleIRQ;
|
||||
|
||||
/* Clear internal IRQ enables and enable NVIC IRQ. */
|
||||
I2C_DisableInterrupts(base,
|
||||
I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
|
||||
EnableIRQ(s_i2cIRQ[instance]);
|
||||
|
||||
/* Set the handle for DMA. */
|
||||
handle->dmaHandle = dmaHandle;
|
||||
|
||||
s_dmaPrivateHandle[instance].base = base;
|
||||
s_dmaPrivateHandle[instance].handle = handle;
|
||||
|
||||
DMA_SetCallback(dmaHandle, (dma_callback)(uintptr_t)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]);
|
||||
}
|
||||
|
||||
status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer)
|
||||
{
|
||||
status_t result;
|
||||
|
||||
assert(handle);
|
||||
assert(xfer);
|
||||
assert(xfer->subaddressSize <= sizeof(xfer->subaddress));
|
||||
|
||||
/* Return busy if another transaction is in progress. */
|
||||
if (handle->state != kIdleState)
|
||||
{
|
||||
return kStatus_I2C_Busy;
|
||||
}
|
||||
|
||||
/* Prepare transfer state machine. */
|
||||
result = I2C_InitTransferStateMachineDMA(base, handle, xfer);
|
||||
|
||||
/* Clear error flags. */
|
||||
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
|
||||
|
||||
/* Enable I2C internal IRQ sources */
|
||||
I2C_EnableInterrupts(base,
|
||||
I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count)
|
||||
{
|
||||
assert(handle);
|
||||
|
||||
if (!count)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
/* Catch when there is not an active transfer. */
|
||||
if (handle->state == kIdleState)
|
||||
{
|
||||
*count = 0;
|
||||
return kStatus_NoTransferInProgress;
|
||||
}
|
||||
|
||||
/* There is no necessity to disable interrupts as we read a single integer value */
|
||||
*count = handle->transferCount;
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle)
|
||||
{
|
||||
uint32_t status;
|
||||
uint32_t master_state;
|
||||
|
||||
if (handle->state != kIdleState)
|
||||
{
|
||||
DMA_AbortTransfer(handle->dmaHandle);
|
||||
|
||||
/* Disable DMA */
|
||||
base->MSTCTL = 0;
|
||||
|
||||
/* Disable internal IRQ enables. */
|
||||
I2C_DisableInterrupts(base,
|
||||
I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK);
|
||||
|
||||
/* Wait until module is ready */
|
||||
do
|
||||
{
|
||||
status = I2C_GetStatusFlags(base);
|
||||
} while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
|
||||
|
||||
/* Clear controller state. */
|
||||
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
|
||||
|
||||
/* Get the state of the I2C module */
|
||||
master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
|
||||
|
||||
if (master_state != I2C_STAT_MSTCODE_IDLE)
|
||||
{
|
||||
/* Send a stop command to finalize the transfer. */
|
||||
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
|
||||
|
||||
/* Wait until module is ready */
|
||||
do
|
||||
{
|
||||
status = I2C_GetStatusFlags(base);
|
||||
} while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
|
||||
|
||||
/* Clear controller state. */
|
||||
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
|
||||
}
|
||||
|
||||
/* Reset the state to idle. */
|
||||
handle->state = kIdleState;
|
||||
}
|
||||
}
|
||||
136
Living_SDK/platform/mcu/lpc54102/drivers/fsl_i2c_dma.h
Normal file
136
Living_SDK/platform/mcu/lpc54102/drivers/fsl_i2c_dma.h
Normal file
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_I2C_DMA_H_
|
||||
#define _FSL_I2C_DMA_H_
|
||||
|
||||
#include "fsl_i2c.h"
|
||||
#include "fsl_dma.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup i2c_dma_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */
|
||||
#define I2C_MAX_DMA_TRANSFER_COUNT 1024
|
||||
|
||||
/*! @brief I2C master dma handle typedef. */
|
||||
typedef struct _i2c_master_dma_handle i2c_master_dma_handle_t;
|
||||
|
||||
/*! @brief I2C master dma transfer callback typedef. */
|
||||
typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base,
|
||||
i2c_master_dma_handle_t *handle,
|
||||
status_t status,
|
||||
void *userData);
|
||||
|
||||
/*! @brief I2C master dma transfer structure. */
|
||||
struct _i2c_master_dma_handle
|
||||
{
|
||||
uint8_t state; /*!< Transfer state machine current state. */
|
||||
uint32_t transferCount; /*!< Indicates progress of the transfer */
|
||||
uint32_t remainingBytesDMA; /*!< Remaining byte count to be transferred using DMA. */
|
||||
uint8_t *buf; /*!< Buffer pointer for current state. */
|
||||
uint32_t remainingSubaddr;
|
||||
uint8_t subaddrBuf[4];
|
||||
dma_handle_t *dmaHandle; /*!< The DMA handler used. */
|
||||
i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */
|
||||
i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */
|
||||
void *userData; /*!< Callback parameter passed to callback function. */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /*_cplusplus. */
|
||||
|
||||
/*!
|
||||
* @name I2C Block DMA Transfer Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Init the I2C handle which is used in transcational functions
|
||||
*
|
||||
* @param base I2C peripheral base address
|
||||
* @param handle pointer to i2c_master_dma_handle_t structure
|
||||
* @param callback pointer to user callback function
|
||||
* @param userData user param passed to the callback function
|
||||
* @param dmaHandle DMA handle pointer
|
||||
*/
|
||||
void I2C_MasterTransferCreateHandleDMA(I2C_Type *base,
|
||||
i2c_master_dma_handle_t *handle,
|
||||
i2c_master_dma_transfer_callback_t callback,
|
||||
void *userData,
|
||||
dma_handle_t *dmaHandle);
|
||||
|
||||
/*!
|
||||
* @brief Performs a master dma non-blocking transfer on the I2C bus
|
||||
*
|
||||
* @param base I2C peripheral base address
|
||||
* @param handle pointer to i2c_master_dma_handle_t structure
|
||||
* @param xfer pointer to transfer structure of i2c_master_transfer_t
|
||||
* @retval kStatus_Success Sucessully complete the data transmission.
|
||||
* @retval kStatus_I2C_Busy Previous transmission still not finished.
|
||||
* @retval kStatus_I2C_Timeout Transfer error, wait signal timeout.
|
||||
* @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost.
|
||||
* @retval kStataus_I2C_Nak Transfer error, receive Nak during transfer.
|
||||
*/
|
||||
status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Get master transfer status during a dma non-blocking transfer
|
||||
*
|
||||
* @param base I2C peripheral base address
|
||||
* @param handle pointer to i2c_master_dma_handle_t structure
|
||||
* @param count Number of bytes transferred so far by the non-blocking transaction.
|
||||
*/
|
||||
status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count);
|
||||
|
||||
/*!
|
||||
* @brief Abort a master dma non-blocking transfer in a early time
|
||||
*
|
||||
* @param base I2C peripheral base address
|
||||
* @param handle pointer to i2c_master_dma_handle_t structure
|
||||
*/
|
||||
void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle);
|
||||
|
||||
/* @} */
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /*_cplusplus. */
|
||||
/*@}*/
|
||||
#endif /*_FSL_I2C_DMA_H_*/
|
||||
66
Living_SDK/platform/mcu/lpc54102/drivers/fsl_inputmux.c
Normal file
66
Living_SDK/platform/mcu/lpc54102/drivers/fsl_inputmux.c
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_inputmux.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
void INPUTMUX_Init(INPUTMUX_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
CLOCK_EnableClock(kCLOCK_InputMux);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection)
|
||||
{
|
||||
uint32_t pmux_id;
|
||||
uint32_t output_id;
|
||||
|
||||
/* extract pmux to be used */
|
||||
pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
|
||||
/* extract function number */
|
||||
output_id = ((uint32_t)(connection)) & 0xffffU;
|
||||
/* programm signal */
|
||||
*(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id;
|
||||
}
|
||||
|
||||
void INPUTMUX_Deinit(INPUTMUX_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
CLOCK_DisableClock(kCLOCK_InputMux);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
104
Living_SDK/platform/mcu/lpc54102/drivers/fsl_inputmux.h
Normal file
104
Living_SDK/platform/mcu/lpc54102/drivers/fsl_inputmux.h
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_INPUTMUX_H_
|
||||
#define _FSL_INPUTMUX_H_
|
||||
|
||||
#include "fsl_inputmux_connections.h"
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup inputmux_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
/*! @file fsl_inputmux_connections.h */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief Group interrupt driver version for SDK */
|
||||
#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
|
||||
/*@}*/
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Initialize INPUTMUX peripheral.
|
||||
|
||||
* This function enables the INPUTMUX clock.
|
||||
*
|
||||
* @param base Base address of the INPUTMUX peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void INPUTMUX_Init(INPUTMUX_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Attaches a signal
|
||||
*
|
||||
* This function gates the INPUTPMUX clock.
|
||||
*
|
||||
* @param base Base address of the INPUTMUX peripheral.
|
||||
* @param index Destination peripheral to attach the signal to.
|
||||
* @param connection Selects connection.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connection_t connection);
|
||||
|
||||
/*!
|
||||
* @brief Deinitialize INPUTMUX peripheral.
|
||||
|
||||
* This function disables the INPUTMUX clock.
|
||||
*
|
||||
* @param base Base address of the INPUTMUX peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void INPUTMUX_Deinit(INPUTMUX_Type *base);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _FSL_INPUTMUX_H_ */
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_INPUTMUX_CONNECTIONS_
|
||||
#define _FSL_INPUTMUX_CONNECTIONS_
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @addtogroup inputmux_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief Periphinmux IDs */
|
||||
#define PINTSEL_PMUX_ID 0xC0U
|
||||
#define DMA_TRIG0_PMUX_ID 0xE0U
|
||||
#define DMA_OTRIG_PMUX_ID 0x140U
|
||||
#define FREQMEAS_PMUX_ID 0x160U
|
||||
#define PMUX_SHIFT 20U
|
||||
|
||||
/*! @brief INPUTMUX connections type */
|
||||
typedef enum _inputmux_connection_t
|
||||
{
|
||||
/*!< Frequency measure. */
|
||||
kINPUTMUX_ClockInToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Irc12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_WdtOscToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_32KhzOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_MainClkToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin4ToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin20ToFreqmeas = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin24ToFreqmeas = 7U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin4ToFreqmeas = 8U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
|
||||
/*!< Pin Interrupt. */
|
||||
kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
|
||||
/*!< DMA ITRIG. */
|
||||
kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Adc0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Ctimer32B0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Ctimer32B0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Ctimer32B1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Ctimer32B2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Ctimer32B2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Ctimer32B3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Ctimer32B4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Ctimer32B4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
|
||||
/*!< DMA OTRIG. */
|
||||
kINPUTMUX_DmaUsart0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaUsart0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaUsart1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaUsart1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaUsart2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaUsart2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaUsart3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaUsart3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaSpi0RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaSpi0TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaSpi1RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaSpi1TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaI2c0SlaveTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaI2c0MasterTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaI2c1SlaveTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaI2c1MasterTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaI2c2SlaveTrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaI2c2MasterTrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaI2c0MonitorTrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaI2c1MonitorTrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
kINPUTMUX_DmaI2c2MonitorTrigoutToTriginChannels = 20U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
|
||||
} inputmux_connection_t;
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
|
||||
178
Living_SDK/platform/mcu/lpc54102/drivers/fsl_iocon.h
Normal file
178
Living_SDK/platform/mcu/lpc54102/drivers/fsl_iocon.h
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_IOCON_H_
|
||||
#define _FSL_IOCON_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup lpc_iocon
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief IOCON driver version 2.0.0. */
|
||||
#define LPC_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/**
|
||||
* @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
|
||||
*/
|
||||
typedef struct _iocon_group
|
||||
{
|
||||
uint32_t port : 8; /* Pin port */
|
||||
uint32_t pin : 8; /* Pin number */
|
||||
uint32_t modefunc : 16; /* Function and mode */
|
||||
} iocon_group_t;
|
||||
|
||||
/**
|
||||
* @brief IOCON function and mode selection definitions
|
||||
* @note See the User Manual for specific modes and functions supported by the various pins.
|
||||
*/
|
||||
#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4)
|
||||
#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
|
||||
#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
|
||||
#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
|
||||
#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
|
||||
#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
|
||||
#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
|
||||
#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
|
||||
#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
|
||||
#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */
|
||||
#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */
|
||||
#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */
|
||||
#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */
|
||||
#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */
|
||||
#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */
|
||||
#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */
|
||||
#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */
|
||||
#define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */
|
||||
#define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */
|
||||
#define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */
|
||||
#define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */
|
||||
#define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */
|
||||
#define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */
|
||||
#define IOCON_I2C_SLEW (0x0 << 6) /*!< I2C Slew Rate Control */
|
||||
#define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */
|
||||
#define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */
|
||||
#define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */
|
||||
#define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */
|
||||
#define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */
|
||||
#define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */
|
||||
#define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */
|
||||
#define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */
|
||||
#define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */
|
||||
#define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */
|
||||
#define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */
|
||||
#define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */
|
||||
#define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */
|
||||
#define IOCON_CLKDIV(div) \
|
||||
((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
|
||||
#else
|
||||
#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
|
||||
#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
|
||||
#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
|
||||
#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
|
||||
#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
|
||||
#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
|
||||
#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
|
||||
#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
|
||||
#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */
|
||||
#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */
|
||||
#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */
|
||||
#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */
|
||||
#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */
|
||||
#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */
|
||||
#define IOCON_I2C_SLEW (0x0 << 5) /*!< I2C Slew Rate Control */
|
||||
#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */
|
||||
#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */
|
||||
#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */
|
||||
#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */
|
||||
#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */
|
||||
#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */
|
||||
#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */
|
||||
#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */
|
||||
#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */
|
||||
#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */
|
||||
#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */
|
||||
#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */
|
||||
#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */
|
||||
#define IOCON_CLKDIV(div) \
|
||||
((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
|
||||
#endif
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Sets I/O Control pin mux
|
||||
* @param base : The base of IOCON peripheral on the chip
|
||||
* @param port : GPIO port to mux
|
||||
* @param pin : GPIO pin to mux
|
||||
* @param modefunc : OR'ed values of type IOCON_*
|
||||
* @return Nothing
|
||||
*/
|
||||
__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
|
||||
{
|
||||
base->PIO[port][pin] = modefunc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set all I/O Control pin muxing
|
||||
* @param base : The base of IOCON peripheral on the chip
|
||||
* @param pinArray : Pointer to array of pin mux selections
|
||||
* @param arrayLength : Number of entries in pinArray
|
||||
* @return Nothing
|
||||
*/
|
||||
__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < arrayLength; i++)
|
||||
{
|
||||
IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
|
||||
}
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FSL_IOCON_H_ */
|
||||
200
Living_SDK/platform/mcu/lpc54102/drivers/fsl_mailbox.h
Normal file
200
Living_SDK/platform/mcu/lpc54102/drivers/fsl_mailbox.h
Normal file
|
|
@ -0,0 +1,200 @@
|
|||
/*
|
||||
* Copyright(C) NXP Semiconductors, 2014
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_MAILBOX_H_
|
||||
#define _FSL_MAILBOX_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup mailbox
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/******************************************************************************
|
||||
* Definitions
|
||||
*****************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief MAILBOX driver version 2.0.0. */
|
||||
#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief CPU ID.
|
||||
*/
|
||||
typedef enum _mailbox_cpu_id
|
||||
{
|
||||
kMAILBOX_CM0Plus = 0,
|
||||
kMAILBOX_CM4
|
||||
} mailbox_cpu_id_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name MAILBOX initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the MAILBOX module.
|
||||
*
|
||||
* This function enables the MAILBOX clock only.
|
||||
*
|
||||
* @param base MAILBOX peripheral base address.
|
||||
*/
|
||||
static inline void MAILBOX_Init(MAILBOX_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
CLOCK_EnableClock(kCLOCK_Mailbox);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief De-initializes the MAILBOX module.
|
||||
*
|
||||
* This function disables the MAILBOX clock only.
|
||||
*
|
||||
* @param base MAILBOX peripheral base address.
|
||||
*/
|
||||
static inline void MAILBOX_Deinit(MAILBOX_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
CLOCK_DisableClock(kCLOCK_Mailbox);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @brief Set data value in the mailbox based on the CPU ID.
|
||||
*
|
||||
* @param base MAILBOX peripheral base address.
|
||||
* @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4.
|
||||
* @param mboxData Data to send in the mailbox.
|
||||
*
|
||||
* @note Sets a data value to send via the MAILBOX to the other core.
|
||||
*/
|
||||
static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxData)
|
||||
{
|
||||
assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
|
||||
base->MBOXIRQ[cpu_id].IRQ = mboxData;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get data in the mailbox based on the CPU ID.
|
||||
*
|
||||
* @param base MAILBOX peripheral base address.
|
||||
* @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4.
|
||||
*
|
||||
* @return Current mailbox data.
|
||||
*/
|
||||
static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id)
|
||||
{
|
||||
assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
|
||||
return base->MBOXIRQ[cpu_id].IRQ;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set data bits in the mailbox based on the CPU ID.
|
||||
*
|
||||
* @param base MAILBOX peripheral base address.
|
||||
* @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4.
|
||||
* @param mboxSetBits Data bits to set in the mailbox.
|
||||
*
|
||||
* @note Sets data bits to send via the MAILBOX to the other core. A value of 0 will
|
||||
* do nothing. Only sets bits selected with a 1 in it's bit position.
|
||||
*/
|
||||
static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxSetBits)
|
||||
{
|
||||
assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
|
||||
base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear data bits in the mailbox based on the CPU ID.
|
||||
*
|
||||
* @param base MAILBOX peripheral base address.
|
||||
* @param cpu_id CPU id, kMAILBOX_CM0Plus is M0+ or kMAILBOX_CM4 is M4.
|
||||
* @param mboxClrBits Data bits to clear in the mailbox.
|
||||
*
|
||||
* @note Clear data bits to send via the MAILBOX to the other core. A value of 0 will
|
||||
* do nothing. Only clears bits selected with a 1 in it's bit position.
|
||||
*/
|
||||
static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, uint32_t mboxClrBits)
|
||||
{
|
||||
assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
|
||||
base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get MUTEX state and lock mutex
|
||||
*
|
||||
* @param base MAILBOX peripheral base address.
|
||||
*
|
||||
* @return See note
|
||||
*
|
||||
* @note Returns '1' if the mutex was taken or '0' if another resources has the
|
||||
* mutex locked. Once a mutex is taken, it can be returned with the MAILBOX_SetMutex()
|
||||
* function.
|
||||
*/
|
||||
static inline uint32_t MAILBOX_GetMutex(MAILBOX_Type *base)
|
||||
{
|
||||
return (base->MUTEX & MAILBOX_MUTEX_EX_MASK);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set MUTEX state
|
||||
*
|
||||
* @param base MAILBOX peripheral base address.
|
||||
*
|
||||
* @note Sets mutex state to '1' and allows other resources to get the mutex.
|
||||
*/
|
||||
static inline void MAILBOX_SetMutex(MAILBOX_Type *base)
|
||||
{
|
||||
base->MUTEX = MAILBOX_MUTEX_EX_MASK;
|
||||
}
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /*_cplusplus*/
|
||||
/*@}*/
|
||||
|
||||
#endif /* _FSL_MAILBOX_H_ */
|
||||
122
Living_SDK/platform/mcu/lpc54102/drivers/fsl_mrt.c
Normal file
122
Living_SDK/platform/mcu/lpc54102/drivers/fsl_mrt.c
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_mrt.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Gets the instance from the base address
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
*
|
||||
* @return The MRT instance
|
||||
*/
|
||||
static uint32_t MRT_GetInstance(MRT_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to MRT bases for each instance. */
|
||||
static MRT_Type *const s_mrtBases[] = MRT_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to MRT clocks for each instance. */
|
||||
static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*! @brief Pointers to MRT resets for each instance. */
|
||||
static const reset_ip_name_t s_mrtResets[] = MRT_RSTS;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t MRT_GetInstance(MRT_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
uint32_t mrtArrayCount = (sizeof(s_mrtBases) / sizeof(s_mrtBases[0]));
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < mrtArrayCount; instance++)
|
||||
{
|
||||
if (s_mrtBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < mrtArrayCount);
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void MRT_Init(MRT_Type *base, const mrt_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Ungate the MRT clock */
|
||||
CLOCK_EnableClock(s_mrtClocks[MRT_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Reset the module */
|
||||
RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]);
|
||||
|
||||
/* Set timer operating mode */
|
||||
base->MODCFG = MRT_MODCFG_MULTITASK(config->enableMultiTask);
|
||||
}
|
||||
|
||||
void MRT_Deinit(MRT_Type *base)
|
||||
{
|
||||
/* Stop all the timers */
|
||||
MRT_StopTimer(base, kMRT_Channel_0);
|
||||
MRT_StopTimer(base, kMRT_Channel_1);
|
||||
MRT_StopTimer(base, kMRT_Channel_2);
|
||||
MRT_StopTimer(base, kMRT_Channel_3);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Gate the MRT clock*/
|
||||
CLOCK_DisableClock(s_mrtClocks[MRT_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad)
|
||||
{
|
||||
uint32_t newValue = count;
|
||||
if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad))
|
||||
{
|
||||
/* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */
|
||||
newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK;
|
||||
}
|
||||
|
||||
/* Update the timer interval value */
|
||||
base->CHANNEL[channel].INTVAL = newValue;
|
||||
}
|
||||
371
Living_SDK/platform/mcu/lpc54102/drivers/fsl_mrt.h
Normal file
371
Living_SDK/platform/mcu/lpc54102/drivers/fsl_mrt.h
Normal file
|
|
@ -0,0 +1,371 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_MRT_H_
|
||||
#define _FSL_MRT_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup mrt
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
|
||||
/*@}*/
|
||||
|
||||
/*! @brief List of MRT channels */
|
||||
typedef enum _mrt_chnl
|
||||
{
|
||||
kMRT_Channel_0 = 0U, /*!< MRT channel number 0*/
|
||||
kMRT_Channel_1, /*!< MRT channel number 1 */
|
||||
kMRT_Channel_2, /*!< MRT channel number 2 */
|
||||
kMRT_Channel_3 /*!< MRT channel number 3 */
|
||||
} mrt_chnl_t;
|
||||
|
||||
/*! @brief List of MRT timer modes */
|
||||
typedef enum _mrt_timer_mode
|
||||
{
|
||||
kMRT_RepeatMode = (0 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< Repeat Interrupt mode */
|
||||
kMRT_OneShotMode = (1 << MRT_CHANNEL_CTRL_MODE_SHIFT), /*!< One-shot Interrupt mode */
|
||||
kMRT_OneShotStallMode = (2 << MRT_CHANNEL_CTRL_MODE_SHIFT) /*!< One-shot stall mode */
|
||||
} mrt_timer_mode_t;
|
||||
|
||||
/*! @brief List of MRT interrupts */
|
||||
typedef enum _mrt_interrupt_enable
|
||||
{
|
||||
kMRT_TimerInterruptEnable = MRT_CHANNEL_CTRL_INTEN_MASK /*!< Timer interrupt enable*/
|
||||
} mrt_interrupt_enable_t;
|
||||
|
||||
/*! @brief List of MRT status flags */
|
||||
typedef enum _mrt_status_flags
|
||||
{
|
||||
kMRT_TimerInterruptFlag = MRT_CHANNEL_STAT_INTFLAG_MASK, /*!< Timer interrupt flag */
|
||||
kMRT_TimerRunFlag = MRT_CHANNEL_STAT_RUN_MASK, /*!< Indicates state of the timer */
|
||||
} mrt_status_flags_t;
|
||||
|
||||
/*!
|
||||
* @brief MRT configuration structure
|
||||
*
|
||||
* This structure holds the configuration settings for the MRT peripheral. To initialize this
|
||||
* structure to reasonable defaults, call the MRT_GetDefaultConfig() function and pass a
|
||||
* pointer to your config structure instance.
|
||||
*
|
||||
* The config struct can be made const so it resides in flash
|
||||
*/
|
||||
typedef struct _mrt_config
|
||||
{
|
||||
bool enableMultiTask; /*!< true: Timers run in multi-task mode; false: Timers run in hardware status mode */
|
||||
} mrt_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Ungates the MRT clock and configures the peripheral for basic operation.
|
||||
*
|
||||
* @note This API should be called at the beginning of the application using the MRT driver.
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param config Pointer to user's MRT config structure
|
||||
*/
|
||||
void MRT_Init(MRT_Type *base, const mrt_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Gate the MRT clock
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
*/
|
||||
void MRT_Deinit(MRT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Fill in the MRT config struct with the default settings
|
||||
*
|
||||
* The default values are:
|
||||
* @code
|
||||
* config->enableMultiTask = false;
|
||||
* @endcode
|
||||
* @param config Pointer to user's MRT config structure.
|
||||
*/
|
||||
static inline void MRT_GetDefaultConfig(mrt_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
/* Use hardware status operating mode */
|
||||
config->enableMultiTask = false;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets up an MRT channel mode.
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Channel that is being configured.
|
||||
* @param mode Timer mode to use for the channel.
|
||||
*/
|
||||
static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode)
|
||||
{
|
||||
uint32_t reg = base->CHANNEL[channel].CTRL;
|
||||
|
||||
/* Clear old value */
|
||||
reg &= ~MRT_CHANNEL_CTRL_MODE_MASK;
|
||||
/* Add the new mode */
|
||||
reg |= mode;
|
||||
|
||||
base->CHANNEL[channel].CTRL = reg;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Interrupt Interface
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the MRT interrupt.
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Timer channel number
|
||||
* @param mask The interrupts to enable. This is a logical OR of members of the
|
||||
* enumeration ::mrt_interrupt_enable_t
|
||||
*/
|
||||
static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
|
||||
{
|
||||
base->CHANNEL[channel].CTRL |= mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the selected MRT interrupt.
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Timer channel number
|
||||
* @param mask The interrupts to disable. This is a logical OR of members of the
|
||||
* enumeration ::mrt_interrupt_enable_t
|
||||
*/
|
||||
static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
|
||||
{
|
||||
base->CHANNEL[channel].CTRL &= ~mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the enabled MRT interrupts.
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Timer channel number
|
||||
*
|
||||
* @return The enabled interrupts. This is the logical OR of members of the
|
||||
* enumeration ::mrt_interrupt_enable_t
|
||||
*/
|
||||
static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel)
|
||||
{
|
||||
return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK);
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Status Interface
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the MRT status flags
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Timer channel number
|
||||
*
|
||||
* @return The status flags. This is the logical OR of members of the
|
||||
* enumeration ::mrt_status_flags_t
|
||||
*/
|
||||
static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel)
|
||||
{
|
||||
return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the MRT status flags.
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Timer channel number
|
||||
* @param mask The status flags to clear. This is a logical OR of members of the
|
||||
* enumeration ::mrt_status_flags_t
|
||||
*/
|
||||
static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
|
||||
{
|
||||
base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK);
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Read and Write the timer period
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Used to update the timer period in units of count.
|
||||
*
|
||||
* The new value will be immediately loaded or will be loaded at the end of the current time
|
||||
* interval. For one-shot interrupt mode the new value will be immediately loaded.
|
||||
*
|
||||
* @note User can call the utility macros provided in fsl_common.h to convert to ticks
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Timer channel number
|
||||
* @param count Timer period in units of ticks
|
||||
* @param immediateLoad true: Load the new value immediately into the TIMER register;
|
||||
* false: Load the new value at the end of current timer interval
|
||||
*/
|
||||
void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad);
|
||||
|
||||
/*!
|
||||
* @brief Reads the current timer counting value.
|
||||
*
|
||||
* This function returns the real-time timer counting value, in a range from 0 to a
|
||||
* timer period.
|
||||
*
|
||||
* @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Timer channel number
|
||||
*
|
||||
* @return Current timer counting value in ticks
|
||||
*/
|
||||
static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel)
|
||||
{
|
||||
return base->CHANNEL[channel].TIMER;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Timer Start and Stop
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Starts the timer counting.
|
||||
*
|
||||
* After calling this function, timers load period value, counts down to 0 and
|
||||
* depending on the timer mode it will either load the respective start value again or stop.
|
||||
*
|
||||
* @note User can call the utility macros provided in fsl_common.h to convert to ticks
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Timer channel number.
|
||||
* @param count Timer period in units of ticks
|
||||
*/
|
||||
static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count)
|
||||
{
|
||||
/* Write the timer interval value */
|
||||
base->CHANNEL[channel].INTVAL = count;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Stops the timer counting.
|
||||
*
|
||||
* This function stops the timer from counting.
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Timer channel number.
|
||||
*/
|
||||
static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel)
|
||||
{
|
||||
/* Stop the timer immediately */
|
||||
base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Get & release channel
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Find the available channel.
|
||||
*
|
||||
* This function returns the lowest available channel number.
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
*/
|
||||
static inline uint32_t MRT_GetIdleChannel(MRT_Type *base)
|
||||
{
|
||||
return base->IDLE_CH;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Release the channel when the timer is using the multi-task mode.
|
||||
*
|
||||
* In multi-task mode, the INUSE flags allow more control over when MRT channels are released for
|
||||
* further use. The user can hold on to a channel acquired by calling MRT_GetIdleChannel() for as
|
||||
* long as it is needed and release it by calling this function. This removes the need to ask for
|
||||
* an available channel for every use.
|
||||
*
|
||||
* @param base Multi-Rate timer peripheral base address
|
||||
* @param channel Timer channel number.
|
||||
*/
|
||||
static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel)
|
||||
{
|
||||
uint32_t reg = base->CHANNEL[channel].STAT;
|
||||
|
||||
/* Clear flag bits to prevent accidentally clearing anything when writing back */
|
||||
reg = ~MRT_CHANNEL_STAT_INTFLAG_MASK;
|
||||
reg |= MRT_CHANNEL_STAT_INUSE_MASK;
|
||||
|
||||
base->CHANNEL[channel].STAT = reg;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_MRT_H_ */
|
||||
467
Living_SDK/platform/mcu/lpc54102/drivers/fsl_pint.c
Normal file
467
Living_SDK/platform/mcu/lpc54102/drivers/fsl_pint.c
Normal file
|
|
@ -0,0 +1,467 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_pint.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Irq number array */
|
||||
static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
|
||||
|
||||
/*! @brief Callback function array for PINT(s). */
|
||||
static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
void PINT_Init(PINT_Type *base)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t pmcfg;
|
||||
|
||||
assert(base);
|
||||
|
||||
pmcfg = 0;
|
||||
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
||||
{
|
||||
s_pintCallback[i] = NULL;
|
||||
}
|
||||
|
||||
/* Disable all bit slices */
|
||||
for (i = 0; i < PINT_PIN_INT_COUNT; i++)
|
||||
{
|
||||
pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
|
||||
}
|
||||
|
||||
/* Enable the peripheral clock */
|
||||
CLOCK_EnableClock(kCLOCK_Pint);
|
||||
|
||||
/* Reset the peripheral */
|
||||
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
|
||||
|
||||
/* Disable all pattern match bit slices */
|
||||
base->PMCFG = pmcfg;
|
||||
}
|
||||
|
||||
void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback)
|
||||
{
|
||||
assert(base);
|
||||
|
||||
/* Clear Rise and Fall flags first */
|
||||
PINT_PinInterruptClrRiseFlag(base, intr);
|
||||
PINT_PinInterruptClrFallFlag(base, intr);
|
||||
|
||||
/* select level or edge sensitive */
|
||||
base->ISEL = (base->ISEL & ~(1U << intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1U << intr) : 0U);
|
||||
|
||||
/* enable rising or level interrupt */
|
||||
if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE))
|
||||
{
|
||||
base->SIENR = 1U << intr;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CIENR = 1U << intr;
|
||||
}
|
||||
|
||||
/* Enable falling or select high level */
|
||||
if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
|
||||
{
|
||||
base->SIENF = 1U << intr;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CIENF = 1U << intr;
|
||||
}
|
||||
|
||||
s_pintCallback[intr] = callback;
|
||||
}
|
||||
|
||||
void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback)
|
||||
{
|
||||
uint32_t mask;
|
||||
bool level;
|
||||
|
||||
assert(base);
|
||||
|
||||
*enable = kPINT_PinIntEnableNone;
|
||||
level = false;
|
||||
|
||||
mask = 1U << pintr;
|
||||
if (base->ISEL & mask)
|
||||
{
|
||||
/* Pin interrupt is level sensitive */
|
||||
level = true;
|
||||
}
|
||||
|
||||
if (base->IENR & mask)
|
||||
{
|
||||
if (level)
|
||||
{
|
||||
/* Level interrupt is enabled */
|
||||
*enable = kPINT_PinIntEnableLowLevel;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Rising edge interrupt */
|
||||
*enable = kPINT_PinIntEnableRiseEdge;
|
||||
}
|
||||
}
|
||||
|
||||
if (base->IENF & mask)
|
||||
{
|
||||
if (level)
|
||||
{
|
||||
/* Level interrupt is active high */
|
||||
*enable = kPINT_PinIntEnableHighLevel;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Either falling or both edge */
|
||||
if (*enable == kPINT_PinIntEnableRiseEdge)
|
||||
{
|
||||
/* Rising and faling edge */
|
||||
*enable = kPINT_PinIntEnableBothEdges;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Falling edge */
|
||||
*enable = kPINT_PinIntEnableFallEdge;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
*callback = s_pintCallback[pintr];
|
||||
}
|
||||
|
||||
void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
|
||||
{
|
||||
uint32_t src_shift;
|
||||
uint32_t cfg_shift;
|
||||
uint32_t pmcfg;
|
||||
|
||||
assert(base);
|
||||
|
||||
src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
|
||||
cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
|
||||
|
||||
/* Input source selection for selected bit slice */
|
||||
base->PMSRC = (base->PMSRC & ~(PININT_BITSLICE_SRC_MASK << src_shift)) | (cfg->bs_src << src_shift);
|
||||
|
||||
/* Bit slice configuration */
|
||||
pmcfg = base->PMCFG;
|
||||
pmcfg = (pmcfg & ~(PININT_BITSLICE_CFG_MASK << cfg_shift)) | (cfg->bs_cfg << cfg_shift);
|
||||
|
||||
/* If end point is true, enable the bits */
|
||||
if (bslice != 7U)
|
||||
{
|
||||
if (cfg->end_point)
|
||||
{
|
||||
pmcfg |= (0x1U << bslice);
|
||||
}
|
||||
else
|
||||
{
|
||||
pmcfg &= ~(0x1U << bslice);
|
||||
}
|
||||
}
|
||||
|
||||
base->PMCFG = pmcfg;
|
||||
|
||||
/* Save callback pointer */
|
||||
s_pintCallback[bslice] = cfg->callback;
|
||||
}
|
||||
|
||||
void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg)
|
||||
{
|
||||
uint32_t src_shift;
|
||||
uint32_t cfg_shift;
|
||||
|
||||
assert(base);
|
||||
|
||||
src_shift = PININT_BITSLICE_SRC_START + (bslice * 3U);
|
||||
cfg_shift = PININT_BITSLICE_CFG_START + (bslice * 3U);
|
||||
|
||||
cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (PININT_BITSLICE_SRC_MASK << src_shift)) >> src_shift);
|
||||
cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (PININT_BITSLICE_CFG_MASK << cfg_shift)) >> cfg_shift);
|
||||
|
||||
if (bslice == 7U)
|
||||
{
|
||||
cfg->end_point = true;
|
||||
}
|
||||
else
|
||||
{
|
||||
cfg->end_point = (base->PMCFG & (0x1U << bslice)) >> bslice;
|
||||
}
|
||||
cfg->callback = s_pintCallback[bslice];
|
||||
}
|
||||
|
||||
uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
|
||||
{
|
||||
uint32_t pmctrl;
|
||||
uint32_t pmstatus;
|
||||
uint32_t pmsrc;
|
||||
|
||||
pmctrl = PINT->PMCTRL;
|
||||
pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
|
||||
if (pmstatus)
|
||||
{
|
||||
/* Reset Pattern match engine detection logic */
|
||||
pmsrc = base->PMSRC;
|
||||
base->PMSRC = pmsrc;
|
||||
}
|
||||
return (pmstatus);
|
||||
}
|
||||
|
||||
void PINT_EnableCallback(PINT_Type *base)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
assert(base);
|
||||
|
||||
PINT_PinInterruptClrStatusAll(base);
|
||||
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(s_pintIRQ[i]);
|
||||
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
|
||||
EnableIRQ(s_pintIRQ[i]);
|
||||
}
|
||||
}
|
||||
|
||||
void PINT_DisableCallback(PINT_Type *base)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
assert(base);
|
||||
|
||||
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
||||
{
|
||||
DisableIRQ(s_pintIRQ[i]);
|
||||
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i);
|
||||
NVIC_ClearPendingIRQ(s_pintIRQ[i]);
|
||||
}
|
||||
}
|
||||
|
||||
void PINT_Deinit(PINT_Type *base)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
assert(base);
|
||||
|
||||
/* Cleanup */
|
||||
PINT_DisableCallback(base);
|
||||
for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
|
||||
{
|
||||
s_pintCallback[i] = NULL;
|
||||
}
|
||||
|
||||
/* Reset the peripheral */
|
||||
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
|
||||
|
||||
/* Disable the peripheral clock */
|
||||
CLOCK_DisableClock(kCLOCK_Pint);
|
||||
}
|
||||
|
||||
/* IRQ handler functions overloading weak symbols in the startup */
|
||||
void PIN_INT0_DriverIRQHandler(void)
|
||||
{
|
||||
uint32_t pmstatus;
|
||||
|
||||
/* Reset pattern match detection */
|
||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||||
/* Call user function */
|
||||
if (s_pintCallback[kPINT_PinInt0] != NULL)
|
||||
{
|
||||
s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
|
||||
}
|
||||
/* Clear Pin interrupt after callback */
|
||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
|
||||
void PIN_INT1_DriverIRQHandler(void)
|
||||
{
|
||||
uint32_t pmstatus;
|
||||
|
||||
/* Reset pattern match detection */
|
||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||||
/* Call user function */
|
||||
if (s_pintCallback[kPINT_PinInt1] != NULL)
|
||||
{
|
||||
s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
|
||||
}
|
||||
/* Clear Pin interrupt after callback */
|
||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
|
||||
void PIN_INT2_DriverIRQHandler(void)
|
||||
{
|
||||
uint32_t pmstatus;
|
||||
|
||||
/* Reset pattern match detection */
|
||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||||
/* Call user function */
|
||||
if (s_pintCallback[kPINT_PinInt2] != NULL)
|
||||
{
|
||||
s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
|
||||
}
|
||||
/* Clear Pin interrupt after callback */
|
||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
|
||||
void PIN_INT3_DriverIRQHandler(void)
|
||||
{
|
||||
uint32_t pmstatus;
|
||||
|
||||
/* Reset pattern match detection */
|
||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||||
/* Call user function */
|
||||
if (s_pintCallback[kPINT_PinInt3] != NULL)
|
||||
{
|
||||
s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
|
||||
}
|
||||
/* Clear Pin interrupt after callback */
|
||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
|
||||
void PIN_INT4_DriverIRQHandler(void)
|
||||
{
|
||||
uint32_t pmstatus;
|
||||
|
||||
/* Reset pattern match detection */
|
||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||||
/* Call user function */
|
||||
if (s_pintCallback[kPINT_PinInt4] != NULL)
|
||||
{
|
||||
s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
|
||||
}
|
||||
/* Clear Pin interrupt after callback */
|
||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
|
||||
void PIN_INT5_DriverIRQHandler(void)
|
||||
{
|
||||
uint32_t pmstatus;
|
||||
|
||||
/* Reset pattern match detection */
|
||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||||
/* Call user function */
|
||||
if (s_pintCallback[kPINT_PinInt5] != NULL)
|
||||
{
|
||||
s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
|
||||
}
|
||||
/* Clear Pin interrupt after callback */
|
||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
|
||||
void PIN_INT6_DriverIRQHandler(void)
|
||||
{
|
||||
uint32_t pmstatus;
|
||||
|
||||
/* Reset pattern match detection */
|
||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||||
/* Call user function */
|
||||
if (s_pintCallback[kPINT_PinInt6] != NULL)
|
||||
{
|
||||
s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
|
||||
}
|
||||
/* Clear Pin interrupt after callback */
|
||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
|
||||
void PIN_INT7_DriverIRQHandler(void)
|
||||
{
|
||||
uint32_t pmstatus;
|
||||
|
||||
/* Reset pattern match detection */
|
||||
pmstatus = PINT_PatternMatchResetDetectLogic(PINT);
|
||||
/* Call user function */
|
||||
if (s_pintCallback[kPINT_PinInt7] != NULL)
|
||||
{
|
||||
s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
|
||||
}
|
||||
/* Clear Pin interrupt after callback */
|
||||
PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
568
Living_SDK/platform/mcu/lpc54102/drivers/fsl_pint.h
Normal file
568
Living_SDK/platform/mcu/lpc54102/drivers/fsl_pint.h
Normal file
|
|
@ -0,0 +1,568 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_PINT_H_
|
||||
#define _FSL_PINT_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup pint_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
|
||||
/*@}*/
|
||||
|
||||
/* Number of interrupt line supported by PINT */
|
||||
#define PINT_PIN_INT_COUNT 8U
|
||||
|
||||
/* Number of input sources supported by PINT */
|
||||
#define PINT_INPUT_COUNT 8U
|
||||
|
||||
/* PININT Bit slice source register bits */
|
||||
#define PININT_BITSLICE_SRC_START 8U
|
||||
#define PININT_BITSLICE_SRC_MASK 7U
|
||||
|
||||
/* PININT Bit slice configuration register bits */
|
||||
#define PININT_BITSLICE_CFG_START 8U
|
||||
#define PININT_BITSLICE_CFG_MASK 7U
|
||||
#define PININT_BITSLICE_ENDP_MASK 7U
|
||||
|
||||
#define PINT_PIN_INT_LEVEL 0x10U
|
||||
#define PINT_PIN_INT_EDGE 0x00U
|
||||
#define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U
|
||||
#define PINT_PIN_INT_RISE 0x01U
|
||||
#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE)
|
||||
#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
|
||||
#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
|
||||
#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL)
|
||||
#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL)
|
||||
|
||||
/*! @brief PINT Pin Interrupt enable type */
|
||||
typedef enum _pint_pin_enable
|
||||
{
|
||||
kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */
|
||||
kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */
|
||||
kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */
|
||||
kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */
|
||||
kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */
|
||||
kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */
|
||||
} pint_pin_enable_t;
|
||||
|
||||
/*! @brief PINT Pin Interrupt type */
|
||||
typedef enum _pint_int
|
||||
{
|
||||
kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
|
||||
kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
|
||||
kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
|
||||
kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
|
||||
kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
|
||||
kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
|
||||
kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
|
||||
kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */
|
||||
#endif
|
||||
} pint_pin_int_t;
|
||||
|
||||
/*! @brief PINT Pattern Match bit slice input source type */
|
||||
typedef enum _pint_pmatch_input_src
|
||||
{
|
||||
kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */
|
||||
kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */
|
||||
kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */
|
||||
kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */
|
||||
kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */
|
||||
kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */
|
||||
kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */
|
||||
kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */
|
||||
} pint_pmatch_input_src_t;
|
||||
|
||||
/*! @brief PINT Pattern Match bit slice type */
|
||||
typedef enum _pint_pmatch_bslice
|
||||
{
|
||||
kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
|
||||
kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U)
|
||||
kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U)
|
||||
kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U)
|
||||
kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U)
|
||||
kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U)
|
||||
kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */
|
||||
#endif
|
||||
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
|
||||
kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */
|
||||
#endif
|
||||
} pint_pmatch_bslice_t;
|
||||
|
||||
/*! @brief PINT Pattern Match configuration type */
|
||||
typedef enum _pint_pmatch_bslice_cfg
|
||||
{
|
||||
kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */
|
||||
kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */
|
||||
kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */
|
||||
kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */
|
||||
kPINT_PatternMatchHigh = 4U, /*!< High level */
|
||||
kPINT_PatternMatchLow = 5U, /*!< Low level */
|
||||
kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */
|
||||
kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */
|
||||
} pint_pmatch_bslice_cfg_t;
|
||||
|
||||
/*! @brief PINT Callback function. */
|
||||
typedef void (*pint_cb_t)(pint_pin_int_t pintr, uint32_t pmatch_status);
|
||||
|
||||
typedef struct _pint_pmatch_cfg
|
||||
{
|
||||
pint_pmatch_input_src_t bs_src;
|
||||
pint_pmatch_bslice_cfg_t bs_cfg;
|
||||
bool end_point;
|
||||
pint_cb_t callback;
|
||||
} pint_pmatch_cfg_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Initialize PINT peripheral.
|
||||
|
||||
* This function initializes the PINT peripheral and enables the clock.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void PINT_Init(PINT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Configure PINT peripheral pin interrupt.
|
||||
|
||||
* This function configures a given pin interrupt.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param intr Pin interrupt.
|
||||
* @param enable Selects detection logic.
|
||||
* @param callback Callback.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback);
|
||||
|
||||
/*!
|
||||
* @brief Get PINT peripheral pin interrupt configuration.
|
||||
|
||||
* This function returns the configuration of a given pin interrupt.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param pintr Pin interrupt.
|
||||
* @param enable Pointer to store the detection logic.
|
||||
* @param callback Callback.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_enable_t *enable, pint_cb_t *callback);
|
||||
|
||||
/*!
|
||||
* @brief Clear Selected pin interrupt status.
|
||||
|
||||
* This function clears the selected pin interrupt status.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param pintr Pin interrupt.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void PINT_PinInterruptClrStatus(PINT_Type *base, pint_pin_int_t pintr)
|
||||
{
|
||||
base->IST = (1U << pintr);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get Selected pin interrupt status.
|
||||
|
||||
* This function returns the selected pin interrupt status.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param pintr Pin interrupt.
|
||||
*
|
||||
* @retval status = 0 No pin interrupt request. = 1 Selected Pin interrupt request active.
|
||||
*/
|
||||
static inline uint32_t PINT_PinInterruptGetStatus(PINT_Type *base, pint_pin_int_t pintr)
|
||||
{
|
||||
return ((base->IST & (1U << pintr)) ? 1U : 0U);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear all pin interrupts status.
|
||||
|
||||
* This function clears the status of all pin interrupts.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void PINT_PinInterruptClrStatusAll(PINT_Type *base)
|
||||
{
|
||||
base->IST = PINT_IST_PSTAT_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get all pin interrupts status.
|
||||
|
||||
* This function returns the status of all pin interrupts.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval status Each bit position indicates the status of corresponding pin interrupt.
|
||||
* = 0 No pin interrupt request. = 1 Pin interrupt request active.
|
||||
*/
|
||||
static inline uint32_t PINT_PinInterruptGetStatusAll(PINT_Type *base)
|
||||
{
|
||||
return (base->IST);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear Selected pin interrupt fall flag.
|
||||
|
||||
* This function clears the selected pin interrupt fall flag.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param pintr Pin interrupt.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void PINT_PinInterruptClrFallFlag(PINT_Type *base, pint_pin_int_t pintr)
|
||||
{
|
||||
base->FALL = (1U << pintr);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get selected pin interrupt fall flag.
|
||||
|
||||
* This function returns the selected pin interrupt fall flag.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param pintr Pin interrupt.
|
||||
*
|
||||
* @retval flag = 0 Falling edge has not been detected. = 1 Falling edge has been detected.
|
||||
*/
|
||||
static inline uint32_t PINT_PinInterruptGetFallFlag(PINT_Type *base, pint_pin_int_t pintr)
|
||||
{
|
||||
return ((base->FALL & (1U << pintr)) ? 1U : 0U);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear all pin interrupt fall flags.
|
||||
|
||||
* This function clears the fall flag for all pin interrupts.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void PINT_PinInterruptClrFallFlagAll(PINT_Type *base)
|
||||
{
|
||||
base->FALL = PINT_FALL_FDET_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get all pin interrupt fall flags.
|
||||
|
||||
* This function returns the fall flag of all pin interrupts.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval flags Each bit position indicates the falling edge detection of the corresponding pin interrupt.
|
||||
* 0 Falling edge has not been detected. = 1 Falling edge has been detected.
|
||||
*/
|
||||
static inline uint32_t PINT_PinInterruptGetFallFlagAll(PINT_Type *base)
|
||||
{
|
||||
return (base->FALL);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear Selected pin interrupt rise flag.
|
||||
|
||||
* This function clears the selected pin interrupt rise flag.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param pintr Pin interrupt.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void PINT_PinInterruptClrRiseFlag(PINT_Type *base, pint_pin_int_t pintr)
|
||||
{
|
||||
base->RISE = (1U << pintr);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get selected pin interrupt rise flag.
|
||||
|
||||
* This function returns the selected pin interrupt rise flag.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param pintr Pin interrupt.
|
||||
*
|
||||
* @retval flag = 0 Rising edge has not been detected. = 1 Rising edge has been detected.
|
||||
*/
|
||||
static inline uint32_t PINT_PinInterruptGetRiseFlag(PINT_Type *base, pint_pin_int_t pintr)
|
||||
{
|
||||
return ((base->RISE & (1U << pintr)) ? 1U : 0U);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear all pin interrupt rise flags.
|
||||
|
||||
* This function clears the rise flag for all pin interrupts.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void PINT_PinInterruptClrRiseFlagAll(PINT_Type *base)
|
||||
{
|
||||
base->RISE = PINT_RISE_RDET_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get all pin interrupt rise flags.
|
||||
|
||||
* This function returns the rise flag of all pin interrupts.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval flags Each bit position indicates the rising edge detection of the corresponding pin interrupt.
|
||||
* 0 Rising edge has not been detected. = 1 Rising edge has been detected.
|
||||
*/
|
||||
static inline uint32_t PINT_PinInterruptGetRiseFlagAll(PINT_Type *base)
|
||||
{
|
||||
return (base->RISE);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Configure PINT pattern match.
|
||||
|
||||
* This function configures a given pattern match bit slice.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param bslice Pattern match bit slice number.
|
||||
* @param cfg Pointer to bit slice configuration.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg);
|
||||
|
||||
/*!
|
||||
* @brief Get PINT pattern match configuration.
|
||||
|
||||
* This function returns the configuration of a given pattern match bit slice.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param bslice Pattern match bit slice number.
|
||||
* @param cfg Pointer to bit slice configuration.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_pmatch_cfg_t *cfg);
|
||||
|
||||
/*!
|
||||
* @brief Get pattern match bit slice status.
|
||||
|
||||
* This function returns the status of selected bit slice.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
* @param bslice Pattern match bit slice number.
|
||||
*
|
||||
* @retval status = 0 Match has not been detected. = 1 Match has been detected.
|
||||
*/
|
||||
static inline uint32_t PINT_PatternMatchGetStatus(PINT_Type *base, pint_pmatch_bslice_t bslice)
|
||||
{
|
||||
return ((base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT) & (0x1U << bslice)) >> bslice;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get status of all pattern match bit slices.
|
||||
|
||||
* This function returns the status of all bit slices.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval status Each bit position indicates the match status of corresponding bit slice.
|
||||
* = 0 Match has not been detected. = 1 Match has been detected.
|
||||
*/
|
||||
static inline uint32_t PINT_PatternMatchGetStatusAll(PINT_Type *base)
|
||||
{
|
||||
return base->PMCTRL >> PINT_PMCTRL_PMAT_SHIFT;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Reset pattern match detection logic.
|
||||
|
||||
* This function resets the pattern match detection logic if any of the product term is matching.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval pmstatus Each bit position indicates the match status of corresponding bit slice.
|
||||
* = 0 Match was detected. = 1 Match was not detected.
|
||||
*/
|
||||
uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Enable pattern match function.
|
||||
|
||||
* This function enables the pattern match function.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void PINT_PatternMatchEnable(PINT_Type *base)
|
||||
{
|
||||
base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) | PINT_PMCTRL_SEL_PMATCH_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable pattern match function.
|
||||
|
||||
* This function disables the pattern match function.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void PINT_PatternMatchDisable(PINT_Type *base)
|
||||
{
|
||||
base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_ENA_RXEV_MASK) & ~PINT_PMCTRL_SEL_PMATCH_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable RXEV output.
|
||||
|
||||
* This function enables the pattern match RXEV output.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void PINT_PatternMatchEnableRXEV(PINT_Type *base)
|
||||
{
|
||||
base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) | PINT_PMCTRL_ENA_RXEV_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disable RXEV output.
|
||||
|
||||
* This function disables the pattern match RXEV output.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
static inline void PINT_PatternMatchDisableRXEV(PINT_Type *base)
|
||||
{
|
||||
base->PMCTRL = (base->PMCTRL & PINT_PMCTRL_SEL_PMATCH_MASK) & ~PINT_PMCTRL_ENA_RXEV_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable callback.
|
||||
|
||||
* This function enables the interrupt for the selected PINT peripheral. Although the pin(s) are monitored
|
||||
* as soon as they are enabled, the callback function is not enabled until this function is called.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void PINT_EnableCallback(PINT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Disable callback.
|
||||
|
||||
* This function disables the interrupt for the selected PINT peripheral. Although the pins are still
|
||||
* being monitored but the callback function is not called.
|
||||
*
|
||||
* @param base Base address of the peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void PINT_DisableCallback(PINT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Deinitialize PINT peripheral.
|
||||
|
||||
* This function disables the PINT clock.
|
||||
*
|
||||
* @param base Base address of the PINT peripheral.
|
||||
*
|
||||
* @retval None.
|
||||
*/
|
||||
void PINT_Deinit(PINT_Type *base);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _FSL_PINT_H_ */
|
||||
36
Living_SDK/platform/mcu/lpc54102/drivers/fsl_power.c
Normal file
36
Living_SDK/platform/mcu/lpc54102/drivers/fsl_power.c
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_power.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
/* Empty file since implementation is in header file and power library */
|
||||
239
Living_SDK/platform/mcu/lpc54102/drivers/fsl_power.h
Normal file
239
Living_SDK/platform/mcu/lpc54102/drivers/fsl_power.h
Normal file
|
|
@ -0,0 +1,239 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_POWER_H_
|
||||
#define _FSL_POWER_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @addtogroup power */
|
||||
/*! @{ */
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief power driver version 2.0.0. */
|
||||
#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot)
|
||||
#define PDRCFG0 0x0U
|
||||
|
||||
typedef enum pd_bits
|
||||
{
|
||||
kPDRUNCFG_PD_IRC_OSC = MAKE_PD_BITS(PDRCFG0, 3U),
|
||||
kPDRUNCFG_PD_IRC = MAKE_PD_BITS(PDRCFG0, 4U),
|
||||
kPDRUNCFG_PD_FLASH = MAKE_PD_BITS(PDRCFG0, 5U),
|
||||
kPDRUNCFG_PD_BOD_RST = MAKE_PD_BITS(PDRCFG0, 7U),
|
||||
kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
|
||||
kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
|
||||
kPDRUNCFG_PD_SRAM0A = MAKE_PD_BITS(PDRCFG0, 13U),
|
||||
kPDRUNCFG_PD_SRAM0B = MAKE_PD_BITS(PDRCFG0, 14U),
|
||||
kPDRUNCFG_PD_SRAM1 = MAKE_PD_BITS(PDRCFG0, 15U),
|
||||
kPDRUNCFG_PD_SRAM2 = MAKE_PD_BITS(PDRCFG0, 16U),
|
||||
kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
|
||||
kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
|
||||
kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
|
||||
kPDRUNCFG_PD_SYS_PLL = MAKE_PD_BITS(PDRCFG0, 22U),
|
||||
kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
|
||||
kPDRUNCFG_PD_32K_OSC = MAKE_PD_BITS(PDRCFG0, 24U),
|
||||
kPDRUNCFG_ForceUnsigned = 0x80000000U
|
||||
|
||||
} pd_bit_t;
|
||||
|
||||
/* Power mode configuration API parameter */
|
||||
typedef enum _power_mode_config
|
||||
{
|
||||
kPmu_Sleep = 0U,
|
||||
kPmu_Deep_Sleep = 1U,
|
||||
kPmu_Power_Down = 2U,
|
||||
kPmu_Deep_PowerDown = 3U,
|
||||
} power_mode_cfg_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Power Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
|
||||
*
|
||||
* @param en peripheral for which to enable the PDRUNCFG bit
|
||||
* @return none
|
||||
*/
|
||||
static inline void POWER_EnablePD(pd_bit_t en)
|
||||
{
|
||||
/* PDRUNCFGSET */
|
||||
SYSCON->PDRUNCFGSET = (1UL << (en & 0xffU));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
|
||||
*
|
||||
* @param en peripheral for which to disable the PDRUNCFG bit
|
||||
* @return none
|
||||
*/
|
||||
static inline void POWER_DisablePD(pd_bit_t en)
|
||||
{
|
||||
/* PDRUNCFGCLR */
|
||||
SYSCON->PDRUNCFGCLR = (1UL << (en & 0xffU));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief API to enable deep sleep bit in the ARM Core.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static inline void POWER_EnableDeepSleep(void)
|
||||
{
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief API to disable deep sleep bit in the ARM Core.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static inline void POWER_DisableDeepSleep(void)
|
||||
{
|
||||
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief API in power lib to power down flash.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void Chip_POWER_SetFLASHPower(uint32_t new_power_mode);
|
||||
|
||||
/*!
|
||||
* @brief API to power down flash controller.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static inline void POWER_PowerDownFlash(void)
|
||||
{
|
||||
Chip_POWER_SetFLASHPower(0U);
|
||||
/* TURN OFF clock for Flash Controller (only needed for FLASH programming, will be turned on by ROM API) */
|
||||
CLOCK_DisableClock(kCLOCK_Flash);
|
||||
|
||||
/* TURN OFF clock for Flash Accelerator */
|
||||
CLOCK_DisableClock(kCLOCK_Fmc);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief API to power up flash controller.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static inline void POWER_PowerUpFlash(void)
|
||||
{
|
||||
Chip_POWER_SetFLASHPower(1U);
|
||||
/* TURN ON clock for flash controller */
|
||||
CLOCK_EnableClock(kCLOCK_Fmc);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Power Library API to enter different power mode.
|
||||
*
|
||||
* @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
|
||||
* @return none
|
||||
*/
|
||||
void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
|
||||
|
||||
/*!
|
||||
* @brief Power Library API to enter sleep mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void POWER_EnterSleep(void);
|
||||
|
||||
/*!
|
||||
* @brief Power Library API to enter deep sleep mode.
|
||||
*
|
||||
* @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
|
||||
* @return none
|
||||
*/
|
||||
void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
|
||||
|
||||
/*!
|
||||
* @brief Power Library API to enter power down mode.
|
||||
*
|
||||
* @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep sleep
|
||||
* @return none
|
||||
*/
|
||||
void POWER_EnterPowerDown(uint64_t exclude_from_pd);
|
||||
|
||||
/*!
|
||||
* @brief Power Library API to enter deep power down mode.
|
||||
*
|
||||
* @param exclude_from_pd Bit mask of the PDRUNCFG bits that needs to be powered on during deep power down mode,
|
||||
* but this is has no effect as the voltages are cut off.
|
||||
* @return none
|
||||
*/
|
||||
void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
|
||||
|
||||
/*!
|
||||
* @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
|
||||
*
|
||||
* @param freq - The desired frequency at which the part would like to operate,
|
||||
* note that the voltage and flash wait states should be set before changing frequency
|
||||
* @return none
|
||||
*/
|
||||
void POWER_SetVoltageForFreq(uint32_t freq);
|
||||
|
||||
|
||||
/*!
|
||||
* @brief Power Library API to return the library version.
|
||||
*
|
||||
* @return version number of the power library
|
||||
*/
|
||||
uint32_t POWER_GetLibVersion(void);
|
||||
|
||||
/* @} */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_POWER_H_ */
|
||||
168
Living_SDK/platform/mcu/lpc54102/drivers/fsl_reset.c
Normal file
168
Living_SDK/platform/mcu/lpc54102/drivers/fsl_reset.c
Normal file
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_reset.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
|
||||
(defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
|
||||
|
||||
void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
|
||||
{
|
||||
const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
|
||||
const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
|
||||
const uint32_t bitMask = 1u << bitPos;
|
||||
|
||||
assert(bitPos < 32u);
|
||||
|
||||
/* ASYNC_SYSCON registers have offset 1024 */
|
||||
if (regIndex >= SYSCON_PRESETCTRL_COUNT)
|
||||
{
|
||||
/* reset register is in ASYNC_SYSCON */
|
||||
|
||||
/* set bit */
|
||||
ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;
|
||||
/* wait until it reads 0b1 */
|
||||
while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* reset register is in SYSCON */
|
||||
|
||||
/* set bit */
|
||||
SYSCON->PRESETCTRLSET[regIndex] = bitMask;
|
||||
/* wait until it reads 0b1 */
|
||||
while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask))
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
|
||||
{
|
||||
const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
|
||||
const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
|
||||
const uint32_t bitMask = 1u << bitPos;
|
||||
|
||||
assert(bitPos < 32u);
|
||||
|
||||
/* ASYNC_SYSCON registers have offset 1024 */
|
||||
if (regIndex >= SYSCON_PRESETCTRL_COUNT)
|
||||
{
|
||||
/* reset register is in ASYNC_SYSCON */
|
||||
|
||||
/* clear bit */
|
||||
ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;
|
||||
/* wait until it reads 0b0 */
|
||||
while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* reset register is in SYSCON */
|
||||
|
||||
/* clear bit */
|
||||
SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
|
||||
/* wait until it reads 0b0 */
|
||||
while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask))
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void RESET_PeripheralReset(reset_ip_name_t peripheral)
|
||||
{
|
||||
RESET_SetPeripheralReset(peripheral);
|
||||
RESET_ClearPeripheralReset(peripheral);
|
||||
}
|
||||
|
||||
void RESET_SetSlaveCoreReset(void)
|
||||
{
|
||||
uint32_t cpuctrl = (SYSCON->CPUCTRL & ~0x7F80U) | 0xC0C48000U;
|
||||
|
||||
/* CM4 is the master. */
|
||||
if (cpuctrl & SYSCON_CPUCTRL_MASTERCPU_MASK)
|
||||
{
|
||||
SYSCON->CPUCTRL = cpuctrl | SYSCON_CPUCTRL_CM0RSTEN_MASK;
|
||||
}
|
||||
/* CM0 is the master. */
|
||||
else
|
||||
{
|
||||
SYSCON->CPUCTRL = cpuctrl | SYSCON_CPUCTRL_CM4RSTEN_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
void RESET_ClearSlaveCoreReset(void)
|
||||
{
|
||||
uint32_t cpuctrl = (SYSCON->CPUCTRL & ~0x7F80U) | 0xC0C48000U;
|
||||
|
||||
/* CM4 is the master. */
|
||||
if (cpuctrl & SYSCON_CPUCTRL_MASTERCPU_MASK)
|
||||
{
|
||||
SYSCON->CPUCTRL = cpuctrl & ~SYSCON_CPUCTRL_CM0RSTEN_MASK;
|
||||
}
|
||||
/* CM0 is the master. */
|
||||
else
|
||||
{
|
||||
SYSCON->CPUCTRL = cpuctrl & ~SYSCON_CPUCTRL_CM4RSTEN_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
void RESET_SlaveCoreReset(uint32_t bootAddr, uint32_t bootStackPointer)
|
||||
{
|
||||
volatile uint32_t i = 10U;
|
||||
|
||||
SYSCON->CPSTACK = bootStackPointer;
|
||||
SYSCON->CPBOOT = bootAddr;
|
||||
|
||||
RESET_SetSlaveCoreReset();
|
||||
while(i--){}
|
||||
RESET_ClearSlaveCoreReset();
|
||||
}
|
||||
|
||||
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */
|
||||
243
Living_SDK/platform/mcu/lpc54102/drivers/fsl_reset.h
Normal file
243
Living_SDK/platform/mcu/lpc54102/drivers/fsl_reset.h
Normal file
|
|
@ -0,0 +1,243 @@
|
|||
/*
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef _FSL_RESET_H_
|
||||
#define _FSL_RESET_H_
|
||||
|
||||
#include <assert.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include "fsl_device_registers.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup ksdk_common
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief reset driver version 2.0.0. */
|
||||
#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/*!
|
||||
* @brief Enumeration for peripheral reset control bits
|
||||
*
|
||||
* Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
|
||||
*/
|
||||
typedef enum _SYSCON_RSTn
|
||||
{
|
||||
kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */
|
||||
kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */
|
||||
kMUX_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux reset control */
|
||||
kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */
|
||||
kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */
|
||||
kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */
|
||||
kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */
|
||||
kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */
|
||||
kDMA_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */
|
||||
kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */
|
||||
kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */
|
||||
kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */
|
||||
|
||||
kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
|
||||
kRIT_RST_SHIFT_RSTn = 65536 | 1U, /**< Repetitive interrupt timer (RIT) reset control */
|
||||
kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */
|
||||
kFIFO_RST_SHIFT_RSTn = 65536 | 9U, /**< System FIFO reset control */
|
||||
kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
|
||||
kCT32B2_RST_SHIFT_RSTn = 65536 | 22U, /**< CT32B2 reset control */
|
||||
kCT32B3_RST_SHIFT_RSTn = 65536 | 26U, /**< CT32B3 reset control */
|
||||
kCT32B4_RST_SHIFT_RSTn = 65536 | 27U, /**< CT32B4 reset control */
|
||||
|
||||
kUSART0_RST_SHIFT_RSTn = 67108864 | 1U, /**< USART0 reset control */
|
||||
kUSART1_RST_SHIFT_RSTn = 67108864 | 2U, /**< USART1 reset control */
|
||||
kUSART2_RST_SHIFT_RSTn = 67108864 | 3U, /**< USART2 reset control */
|
||||
kUSART3_RST_SHIFT_RSTn = 67108864 | 4U, /**< USART3 reset control */
|
||||
|
||||
kI2C0_RST_SHIFT_RSTn = 67108864 | 5U, /**< I2C0 reset control */
|
||||
kI2C1_RST_SHIFT_RSTn = 67108864 | 6U, /**< I2C1 reset control */
|
||||
kI2C2_RST_SHIFT_RSTn = 67108864 | 7U, /**< I2C2 reset control */
|
||||
|
||||
kSPI0_RST_SHIFT_RSTn = 67108864 | 9U, /**< SPI0 reset control */
|
||||
kSPI1_RST_SHIFT_RSTn = 67108864 | 10U, /**< SPI1 reset control */
|
||||
|
||||
kCT32B0_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B0 reset control */
|
||||
kCT32B1_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B1 reset control */
|
||||
kFRG0_RST_SHIFT_RSTn = 67108864 | 15U, /**< FRG0 reset control */
|
||||
|
||||
} SYSCON_RSTn_t;
|
||||
|
||||
/** Array initializers with peripheral reset bits **/
|
||||
#define ADC_RSTS \
|
||||
{ \
|
||||
kADC0_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for ADC peripheral */
|
||||
#define CRC_RSTS \
|
||||
{ \
|
||||
kCRC_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for CRC peripheral */
|
||||
#define DMA_RSTS \
|
||||
{ \
|
||||
kDMA_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for DMA peripheral */
|
||||
#define GINT_RSTS \
|
||||
{ \
|
||||
kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
|
||||
#define GPIO_RSTS \
|
||||
{ \
|
||||
kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for GPIO peripheral */
|
||||
#define INPUTMUX_RSTS \
|
||||
{ \
|
||||
kMUX_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for INPUTMUX peripheral */
|
||||
#define IOCON_RSTS \
|
||||
{ \
|
||||
kIOCON_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for IOCON peripheral */
|
||||
#define FLASH_RSTS \
|
||||
{ \
|
||||
kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for Flash peripheral */
|
||||
#define MRT_RSTS \
|
||||
{ \
|
||||
kMRT_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for MRT peripheral */
|
||||
#define RIT_RSTS \
|
||||
{ \
|
||||
kRIT_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for RIT peripheral */
|
||||
#define PINT_RSTS \
|
||||
{ \
|
||||
kPINT_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for PINT peripheral */
|
||||
#define SCT_RSTS \
|
||||
{ \
|
||||
kSCT0_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for SCT peripheral */
|
||||
#define FIFO_RSTS \
|
||||
{ \
|
||||
kFIFO_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for FIFO peripheral */
|
||||
#define CTIMER_RSTS \
|
||||
{ \
|
||||
kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
|
||||
kCT32B4_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for TIMER peripheral */
|
||||
#define UTICK_RSTS \
|
||||
{ \
|
||||
kUTICK_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for UTICK peripheral */
|
||||
#define WWDT_RSTS \
|
||||
{ \
|
||||
kWWDT_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for WWDT peripheral */
|
||||
#define USART_RSTS \
|
||||
{ \
|
||||
kUSART0_RST_SHIFT_RSTn, kUSART1_RST_SHIFT_RSTn, kUSART2_RST_SHIFT_RSTn kUSART3_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for USART peripheral */
|
||||
#define I2C_RSTS \
|
||||
{ \
|
||||
kI2C0_RST_SHIFT_RSTn, kI2C1_RST_SHIFT_RSTn, kI2C2_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for I2C peripheral */
|
||||
#define SPI_RSTS \
|
||||
{ \
|
||||
kSPI0_RST_SHIFT_RSTn, kSPI0_RST_SHIFT_RSTn, \
|
||||
} /* Reset bits for SPI peripheral */
|
||||
#define FRG_RSTS \
|
||||
{ \
|
||||
kFRG0_RST_SHIFT_RSTn \
|
||||
} /* Reset bits for WWDT peripheral */
|
||||
typedef SYSCON_RSTn_t reset_ip_name_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Assert reset to peripheral.
|
||||
*
|
||||
* Asserts reset signal to specified peripheral module.
|
||||
*
|
||||
* @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
|
||||
* and reset bit position in the reset register.
|
||||
*/
|
||||
void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
|
||||
|
||||
/*!
|
||||
* @brief Clear reset to peripheral.
|
||||
*
|
||||
* Clears reset signal to specified peripheral module, allows it to operate.
|
||||
*
|
||||
* @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
|
||||
* and reset bit position in the reset register.
|
||||
*/
|
||||
void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
|
||||
|
||||
/*!
|
||||
* @brief Reset peripheral module.
|
||||
*
|
||||
* Reset peripheral module.
|
||||
*
|
||||
* @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
|
||||
* and reset bit position in the reset register.
|
||||
*/
|
||||
void RESET_PeripheralReset(reset_ip_name_t peripheral);
|
||||
|
||||
/*!
|
||||
* @brief Set slave core to reset state and hold.
|
||||
*/
|
||||
void RESET_SetSlaveCoreReset(void);
|
||||
|
||||
/*!
|
||||
* @brief Release slave core from reset state.
|
||||
*/
|
||||
void RESET_ClearSlaveCoreReset(void);
|
||||
|
||||
/*!
|
||||
* @brief Reset slave core with the boot entry.
|
||||
*/
|
||||
void RESET_SlaveCoreReset(uint32_t bootAddr, uint32_t bootStackPointer);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_RESET_H_ */
|
||||
165
Living_SDK/platform/mcu/lpc54102/drivers/fsl_rit.c
Normal file
165
Living_SDK/platform/mcu/lpc54102/drivers/fsl_rit.c
Normal file
|
|
@ -0,0 +1,165 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_rit.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Gets the instance from the base address to be used to gate or ungate the module clock
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
*
|
||||
* @return The RIT instance
|
||||
*/
|
||||
static uint32_t RIT_GetInstance(RIT_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to RIT bases for each instance. */
|
||||
static RIT_Type *const s_ritBases[] = RIT_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to PIT clocks for each instance. */
|
||||
static const clock_ip_name_t s_ritClocks[] = RIT_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t RIT_GetInstance(RIT_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_ritBases); instance++)
|
||||
{
|
||||
if (s_ritBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_ritBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void RIT_GetDefaultConfig(rit_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
/* Timer operation are no effect in Debug mode */
|
||||
config->enableRunInDebug = false;
|
||||
}
|
||||
|
||||
void RIT_Init(RIT_Type *base, const rit_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Ungate the RIT clock*/
|
||||
CLOCK_EnableClock(s_ritClocks[RIT_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Enable RIT timers */
|
||||
base->CTRL &= ~RIT_CTRL_RITEN_MASK;
|
||||
|
||||
/* Config timer operation is no effect in debug mode */
|
||||
if (!config->enableRunInDebug)
|
||||
{
|
||||
base->CTRL &= ~RIT_CTRL_RITENBR_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CTRL |= RIT_CTRL_RITENBR_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
void RIT_Deinit(RIT_Type *base)
|
||||
{
|
||||
/* Disable RIT timers */
|
||||
base->CTRL |= ~RIT_CTRL_RITEN_MASK;
|
||||
#ifdef FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
|
||||
/* Gate the RIT clock*/
|
||||
CLOCK_DisableClock(s_ritClocks[RIT_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void RIT_SetTimerCompare(RIT_Type *base, uint64_t count)
|
||||
{
|
||||
/* Disable RIT timers */
|
||||
base->CTRL &= ~RIT_CTRL_RITEN_MASK;
|
||||
base->COMPVAL = (uint32_t)count;
|
||||
base->COMPVAL_H = (uint16_t)(count >> 32U);
|
||||
}
|
||||
|
||||
void RIT_SetMaskBit(RIT_Type *base, uint64_t count)
|
||||
{
|
||||
base->MASK = (uint32_t)count;
|
||||
base->MASK_H = (uint16_t)(count >> 32U);
|
||||
}
|
||||
|
||||
uint64_t RIT_GetCompareTimerCount(RIT_Type *base)
|
||||
{
|
||||
uint16_t valueH = 0U;
|
||||
uint32_t valueL = 0U;
|
||||
|
||||
/* COMPVAL_H should be read before COMPVAL */
|
||||
valueH = base->COMPVAL_H;
|
||||
valueL = base->COMPVAL;
|
||||
|
||||
return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
|
||||
}
|
||||
|
||||
uint64_t RIT_GetCounterTimerCount(RIT_Type *base)
|
||||
{
|
||||
uint16_t valueH = 0U;
|
||||
uint32_t valueL = 0U;
|
||||
|
||||
/* COUNTER_H should be read before COUNTER */
|
||||
valueH = base->COUNTER_H;
|
||||
valueL = base->COUNTER;
|
||||
|
||||
return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
|
||||
}
|
||||
|
||||
uint64_t RIT_GetMaskTimerCount(RIT_Type *base)
|
||||
{
|
||||
uint16_t valueH = 0U;
|
||||
uint32_t valueL = 0U;
|
||||
|
||||
/* MASK_H should be read before MASK */
|
||||
valueH = base->MASK_H;
|
||||
valueL = base->MASK;
|
||||
|
||||
return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
|
||||
}
|
||||
276
Living_SDK/platform/mcu/lpc54102/drivers/fsl_rit.h
Normal file
276
Living_SDK/platform/mcu/lpc54102/drivers/fsl_rit.h
Normal file
|
|
@ -0,0 +1,276 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_RIT_H_
|
||||
#define _FSL_RIT_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup rit
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_RIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
|
||||
/*@}*/
|
||||
|
||||
/*! @brief List of RIT status flags */
|
||||
typedef enum _rit_status_flags
|
||||
{
|
||||
kRIT_TimerFlag = RIT_CTRL_RITINT_MASK, /*!< Timer flag */
|
||||
} rit_status_flags_t;
|
||||
|
||||
/*!
|
||||
* @brief RIT config structure
|
||||
*
|
||||
* This structure holds the configuration settings for the RIT peripheral. To initialize this
|
||||
* structure to reasonable defaults, call the RIT_GetDefaultConfig() function and pass a
|
||||
* pointer to your config structure instance.
|
||||
*
|
||||
* The config struct can be made const so it resides in flash
|
||||
*/
|
||||
typedef struct _rit_config
|
||||
{
|
||||
bool enableRunInDebug; /*!< true: The timer is halted when the processor is halted for debugging.; false: Debug has
|
||||
no effect on the timer operation. */
|
||||
} rit_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Ungates the RIT clock, enables the RIT module, and configures the peripheral for basic operations.
|
||||
*
|
||||
* @note This API should be called at the beginning of the application using the RIT driver.
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
* @param config Pointer to the user's RIT config structure
|
||||
*/
|
||||
void RIT_Init(RIT_Type *base, const rit_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Gates the RIT clock and disables the RIT module.
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
*/
|
||||
void RIT_Deinit(RIT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Fills in the RIT configuration structure with the default settings.
|
||||
*
|
||||
* The default values are as follows.
|
||||
* @code
|
||||
* config->enableRunInDebug = false;
|
||||
* @endcode
|
||||
* @param config Pointer to the onfiguration structure.
|
||||
*/
|
||||
void RIT_GetDefaultConfig(rit_config_t *config);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Status Interface
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the RIT status flags.
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
*
|
||||
* @return The status flags. This is the logical OR of members of the
|
||||
* enumeration ::rit_status_flags_t
|
||||
*/
|
||||
static inline uint32_t RIT_GetStatusFlags(RIT_Type *base)
|
||||
{
|
||||
return (base->CTRL);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the RIT status flags.
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
* @param mask The status flags to clear. This is a logical OR of members of the
|
||||
* enumeration ::rit_status_flags_t
|
||||
*/
|
||||
static inline void RIT_ClearStatusFlags(RIT_Type *base, uint32_t mask)
|
||||
{
|
||||
base->CTRL |= mask;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Read and Write the timer period
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the timer period in units of count.
|
||||
*
|
||||
* Timers begin counting from the value set by this function until it XXXXXXX,
|
||||
* then it counting the value again.
|
||||
* Software must stop the counter before reloading it with a new value..
|
||||
*
|
||||
* @note Users can call the utility macros provided in fsl_common.h to convert to ticks
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
* @param count Timer period in units of ticks
|
||||
*/
|
||||
void RIT_SetTimerCompare(RIT_Type *base, uint64_t count);
|
||||
|
||||
/*!
|
||||
* @brief Sets the mask bit of count compare.
|
||||
*
|
||||
* Timers begin counting from the value set by this function until it XXXXXXX,
|
||||
* then it counting the value again.
|
||||
* Software must stop the counter before reloading it with a new value..
|
||||
*
|
||||
* @note Users can call the utility macros provided in fsl_common.h to convert to ticks
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
* @param count Timer period in units of ticks
|
||||
*/
|
||||
void RIT_SetMaskBit(RIT_Type *base, uint64_t count);
|
||||
|
||||
/*!
|
||||
* @brief Reads the current timer counting value of compare register.
|
||||
*
|
||||
* This function returns the real-time timer counting value, in a range from 0 to a
|
||||
* timer period.
|
||||
*
|
||||
* @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
*
|
||||
* @return Current timer counting value in ticks
|
||||
*/
|
||||
uint64_t RIT_GetCompareTimerCount(RIT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Reads the current timer counting value of counter register.
|
||||
*
|
||||
* This function returns the real-time timer counting value, in a range from 0 to a
|
||||
* timer period.
|
||||
*
|
||||
* @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
*
|
||||
* @return Current timer counting value in ticks
|
||||
*/
|
||||
uint64_t RIT_GetCounterTimerCount(RIT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Reads the current timer counting value of mask register.
|
||||
*
|
||||
* This function returns the real-time timer counting value, in a range from 0 to a
|
||||
* timer period.
|
||||
*
|
||||
* @note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
*
|
||||
* @return Current timer counting value in ticks
|
||||
*/
|
||||
uint64_t RIT_GetMaskTimerCount(RIT_Type *base);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Timer Start and Stop
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Starts the timer counting.
|
||||
*
|
||||
* After calling this function, timers load initial value(0U), count up to desired value or over-flow
|
||||
* then the counter will count up again. Each time a timer reaches desired value,
|
||||
* it generates a XXXXXXX and sets XXXXXXX.
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
*/
|
||||
static inline void RIT_StartTimer(RIT_Type *base)
|
||||
{
|
||||
base->CTRL |= RIT_CTRL_RITEN_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Stops the timer counting.
|
||||
*
|
||||
* This function stop timer counting. Timer reload their new value
|
||||
* after the next time they call the RIT_StartTimer.
|
||||
*
|
||||
* @param base RIT peripheral base address
|
||||
* @param channel Timer channel number.
|
||||
*/
|
||||
static inline void RIT_StopTimer(RIT_Type *base)
|
||||
{
|
||||
/* Disable RIT timers */
|
||||
base->CTRL &= ~RIT_CTRL_RITEN_MASK;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
static inline void RIT_ClearCounter(RIT_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CTRL |= RIT_CTRL_RITENCLR_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CTRL &= ~RIT_CTRL_RITENCLR_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_RIT_H_ */
|
||||
290
Living_SDK/platform/mcu/lpc54102/drivers/fsl_rtc.c
Normal file
290
Living_SDK/platform/mcu/lpc54102/drivers/fsl_rtc.c
Normal file
|
|
@ -0,0 +1,290 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_rtc.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define SECONDS_IN_A_DAY (86400U)
|
||||
#define SECONDS_IN_A_HOUR (3600U)
|
||||
#define SECONDS_IN_A_MINUTE (60U)
|
||||
#define DAYS_IN_A_YEAR (365U)
|
||||
#define YEAR_RANGE_START (1970U)
|
||||
#define YEAR_RANGE_END (2099U)
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Checks whether the date and time passed in is valid
|
||||
*
|
||||
* @param datetime Pointer to structure where the date and time details are stored
|
||||
*
|
||||
* @return Returns false if the date & time details are out of range; true if in range
|
||||
*/
|
||||
static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime);
|
||||
|
||||
/*!
|
||||
* @brief Converts time data from datetime to seconds
|
||||
*
|
||||
* @param datetime Pointer to datetime structure where the date and time details are stored
|
||||
*
|
||||
* @return The result of the conversion in seconds
|
||||
*/
|
||||
static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime);
|
||||
|
||||
/*!
|
||||
* @brief Converts time data from seconds to a datetime structure
|
||||
*
|
||||
* @param seconds Seconds value that needs to be converted to datetime format
|
||||
* @param datetime Pointer to the datetime structure where the result of the conversion is stored
|
||||
*/
|
||||
static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime);
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
|
||||
{
|
||||
assert(datetime);
|
||||
|
||||
/* Table of days in a month for a non leap year. First entry in the table is not used,
|
||||
* valid months start from 1
|
||||
*/
|
||||
uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
|
||||
|
||||
/* Check year, month, hour, minute, seconds */
|
||||
if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) ||
|
||||
(datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U))
|
||||
{
|
||||
/* If not correct then error*/
|
||||
return false;
|
||||
}
|
||||
|
||||
/* Adjust the days in February for a leap year */
|
||||
if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0))
|
||||
{
|
||||
daysPerMonth[2] = 29U;
|
||||
}
|
||||
|
||||
/* Check the validity of the day */
|
||||
if ((datetime->day > daysPerMonth[datetime->month]) || (datetime->day < 1U))
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
|
||||
{
|
||||
assert(datetime);
|
||||
|
||||
/* Number of days from begin of the non Leap-year*/
|
||||
/* Number of days from begin of the non Leap-year*/
|
||||
uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U};
|
||||
uint32_t seconds;
|
||||
|
||||
/* Compute number of days from 1970 till given year*/
|
||||
seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR;
|
||||
/* Add leap year days */
|
||||
seconds += ((datetime->year / 4) - (1970U / 4));
|
||||
/* Add number of days till given month*/
|
||||
seconds += monthDays[datetime->month];
|
||||
/* Add days in given month. We subtract the current day as it is
|
||||
* represented in the hours, minutes and seconds field*/
|
||||
seconds += (datetime->day - 1);
|
||||
/* For leap year if month less than or equal to Febraury, decrement day counter*/
|
||||
if ((!(datetime->year & 3U)) && (datetime->month <= 2U))
|
||||
{
|
||||
seconds--;
|
||||
}
|
||||
|
||||
seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) +
|
||||
(datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second;
|
||||
|
||||
return seconds;
|
||||
}
|
||||
|
||||
static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime)
|
||||
{
|
||||
assert(datetime);
|
||||
|
||||
uint32_t x;
|
||||
uint32_t secondsRemaining, days;
|
||||
uint16_t daysInYear;
|
||||
/* Table of days in a month for a non leap year. First entry in the table is not used,
|
||||
* valid months start from 1
|
||||
*/
|
||||
uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
|
||||
|
||||
/* Start with the seconds value that is passed in to be converted to date time format */
|
||||
secondsRemaining = seconds;
|
||||
|
||||
/* Calcuate the number of days, we add 1 for the current day which is represented in the
|
||||
* hours and seconds field
|
||||
*/
|
||||
days = secondsRemaining / SECONDS_IN_A_DAY + 1;
|
||||
|
||||
/* Update seconds left*/
|
||||
secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY;
|
||||
|
||||
/* Calculate the datetime hour, minute and second fields */
|
||||
datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR;
|
||||
secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR;
|
||||
datetime->minute = secondsRemaining / 60U;
|
||||
datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE;
|
||||
|
||||
/* Calculate year */
|
||||
daysInYear = DAYS_IN_A_YEAR;
|
||||
datetime->year = YEAR_RANGE_START;
|
||||
while (days > daysInYear)
|
||||
{
|
||||
/* Decrease day count by a year and increment year by 1 */
|
||||
days -= daysInYear;
|
||||
datetime->year++;
|
||||
|
||||
/* Adjust the number of days for a leap year */
|
||||
if (datetime->year & 3U)
|
||||
{
|
||||
daysInYear = DAYS_IN_A_YEAR;
|
||||
}
|
||||
else
|
||||
{
|
||||
daysInYear = DAYS_IN_A_YEAR + 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Adjust the days in February for a leap year */
|
||||
if (!(datetime->year & 3U))
|
||||
{
|
||||
daysPerMonth[2] = 29U;
|
||||
}
|
||||
|
||||
for (x = 1U; x <= 12U; x++)
|
||||
{
|
||||
if (days <= daysPerMonth[x])
|
||||
{
|
||||
datetime->month = x;
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
days -= daysPerMonth[x];
|
||||
}
|
||||
}
|
||||
|
||||
datetime->day = days;
|
||||
}
|
||||
|
||||
void RTC_Init(RTC_Type *base)
|
||||
{
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the RTC peripheral clock */
|
||||
CLOCK_EnableClock(kCLOCK_Rtc);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Make sure the reset bit is cleared */
|
||||
base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
|
||||
|
||||
#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD)
|
||||
/* Make sure the RTC OSC is powered up */
|
||||
base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK;
|
||||
#endif
|
||||
}
|
||||
|
||||
status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime)
|
||||
{
|
||||
assert(datetime);
|
||||
|
||||
/* Return error if the time provided is not valid */
|
||||
if (!(RTC_CheckDatetimeFormat(datetime)))
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
/* Set time in seconds */
|
||||
base->COUNT = RTC_ConvertDatetimeToSeconds(datetime);
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime)
|
||||
{
|
||||
assert(datetime);
|
||||
|
||||
uint32_t seconds = 0;
|
||||
|
||||
seconds = base->COUNT;
|
||||
RTC_ConvertSecondsToDatetime(seconds, datetime);
|
||||
}
|
||||
|
||||
status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime)
|
||||
{
|
||||
assert(alarmTime);
|
||||
|
||||
uint32_t alarmSeconds = 0;
|
||||
uint32_t currSeconds = 0;
|
||||
|
||||
/* Return error if the alarm time provided is not valid */
|
||||
if (!(RTC_CheckDatetimeFormat(alarmTime)))
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime);
|
||||
|
||||
/* Get the current time */
|
||||
currSeconds = base->COUNT;
|
||||
|
||||
/* Return error if the alarm time has passed */
|
||||
if (alarmSeconds < currSeconds)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Set alarm in seconds*/
|
||||
base->MATCH = alarmSeconds;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime)
|
||||
{
|
||||
assert(datetime);
|
||||
|
||||
uint32_t alarmSeconds = 0;
|
||||
|
||||
/* Get alarm in seconds */
|
||||
alarmSeconds = base->MATCH;
|
||||
|
||||
RTC_ConvertSecondsToDatetime(alarmSeconds, datetime);
|
||||
}
|
||||
340
Living_SDK/platform/mcu/lpc54102/drivers/fsl_rtc.h
Normal file
340
Living_SDK/platform/mcu/lpc54102/drivers/fsl_rtc.h
Normal file
|
|
@ -0,0 +1,340 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_RTC_H_
|
||||
#define _FSL_RTC_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup rtc
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
|
||||
/*@}*/
|
||||
|
||||
/*! @brief List of RTC interrupts */
|
||||
typedef enum _rtc_interrupt_enable
|
||||
{
|
||||
kRTC_AlarmInterruptEnable = RTC_CTRL_ALARMDPD_EN_MASK, /*!< Alarm interrupt.*/
|
||||
kRTC_WakeupInterruptEnable = RTC_CTRL_WAKEDPD_EN_MASK /*!< Wake-up interrupt.*/
|
||||
} rtc_interrupt_enable_t;
|
||||
|
||||
/*! @brief List of RTC flags */
|
||||
typedef enum _rtc_status_flags
|
||||
{
|
||||
kRTC_AlarmFlag = RTC_CTRL_ALARM1HZ_MASK, /*!< Alarm flag*/
|
||||
kRTC_WakeupFlag = RTC_CTRL_WAKE1KHZ_MASK /*!< 1kHz wake-up timer flag*/
|
||||
} rtc_status_flags_t;
|
||||
|
||||
/*! @brief Structure is used to hold the date and time */
|
||||
typedef struct _rtc_datetime
|
||||
{
|
||||
uint16_t year; /*!< Range from 1970 to 2099.*/
|
||||
uint8_t month; /*!< Range from 1 to 12.*/
|
||||
uint8_t day; /*!< Range from 1 to 31 (depending on month).*/
|
||||
uint8_t hour; /*!< Range from 0 to 23.*/
|
||||
uint8_t minute; /*!< Range from 0 to 59.*/
|
||||
uint8_t second; /*!< Range from 0 to 59.*/
|
||||
} rtc_datetime_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Ungates the RTC clock and enables the RTC oscillator.
|
||||
*
|
||||
* @note This API should be called at the beginning of the application using the RTC driver.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
*/
|
||||
void RTC_Init(RTC_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Stop the timer and gate the RTC clock
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
*/
|
||||
static inline void RTC_Deinit(RTC_Type *base)
|
||||
{
|
||||
/* Stop the RTC timer */
|
||||
base->CTRL &= ~RTC_CTRL_RTC_EN_MASK;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Gate the module clock */
|
||||
CLOCK_DisableClock(kCLOCK_Rtc);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Current Time & Alarm
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the RTC date and time according to the given time structure.
|
||||
*
|
||||
* The RTC counter must be stopped prior to calling this function as writes to the RTC
|
||||
* seconds register will fail if the RTC counter is running.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
* @param datetime Pointer to structure where the date and time details to set are stored
|
||||
*
|
||||
* @return kStatus_Success: Success in setting the time and starting the RTC
|
||||
* kStatus_InvalidArgument: Error because the datetime format is incorrect
|
||||
*/
|
||||
status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime);
|
||||
|
||||
/*!
|
||||
* @brief Gets the RTC time and stores it in the given time structure.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
* @param datetime Pointer to structure where the date and time details are stored.
|
||||
*/
|
||||
void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime);
|
||||
|
||||
/*!
|
||||
* @brief Sets the RTC alarm time
|
||||
*
|
||||
* The function checks whether the specified alarm time is greater than the present
|
||||
* time. If not, the function does not set the alarm and returns an error.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
* @param alarmTime Pointer to structure where the alarm time is stored.
|
||||
*
|
||||
* @return kStatus_Success: success in setting the RTC alarm
|
||||
* kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
|
||||
* kStatus_Fail: Error because the alarm time has already passed
|
||||
*/
|
||||
status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime);
|
||||
|
||||
/*!
|
||||
* @brief Returns the RTC alarm time.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
* @param datetime Pointer to structure where the alarm date and time details are stored.
|
||||
*/
|
||||
void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @brief Enable the RTC high resolution timer and set the wake-up time.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
* @param wakeupValue The value to be loaded into the RTC WAKE register
|
||||
*/
|
||||
static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue)
|
||||
{
|
||||
/* Enable the 1kHz RTC timer */
|
||||
base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK;
|
||||
|
||||
/* Set the start count value into the wake-up timer */
|
||||
base->WAKE = wakeupValue;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Read actual RTC counter value.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
*/
|
||||
static inline uint16_t RTC_GetWakeupCount(RTC_Type *base)
|
||||
{
|
||||
/* Read wake-up counter */
|
||||
return RTC_WAKE_VAL(base->WAKE);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @name Interrupt Interface
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the selected RTC interrupts.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
* @param mask The interrupts to enable. This is a logical OR of members of the
|
||||
* enumeration ::rtc_interrupt_enable_t
|
||||
*/
|
||||
static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask)
|
||||
{
|
||||
uint32_t reg = base->CTRL;
|
||||
|
||||
/* Clear flag bits to prevent accidentally clearing anything when writing back */
|
||||
reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK);
|
||||
reg |= mask;
|
||||
|
||||
base->CTRL = reg;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the selected RTC interrupts.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
* @param mask The interrupts to enable. This is a logical OR of members of the
|
||||
* enumeration ::rtc_interrupt_enable_t
|
||||
*/
|
||||
static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask)
|
||||
{
|
||||
uint32_t reg = base->CTRL;
|
||||
|
||||
/* Clear flag bits to prevent accidentally clearing anything when writing back */
|
||||
reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK | mask);
|
||||
|
||||
base->CTRL = reg;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the enabled RTC interrupts.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
*
|
||||
* @return The enabled interrupts. This is the logical OR of members of the
|
||||
* enumeration ::rtc_interrupt_enable_t
|
||||
*/
|
||||
static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)
|
||||
{
|
||||
return (base->CTRL & (RTC_CTRL_ALARMDPD_EN_MASK | RTC_CTRL_WAKEDPD_EN_MASK));
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Status Interface
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the RTC status flags
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
*
|
||||
* @return The status flags. This is the logical OR of members of the
|
||||
* enumeration ::rtc_status_flags_t
|
||||
*/
|
||||
static inline uint32_t RTC_GetStatusFlags(RTC_Type *base)
|
||||
{
|
||||
return (base->CTRL & (RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the RTC status flags.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
* @param mask The status flags to clear. This is a logical OR of members of the
|
||||
* enumeration ::rtc_status_flags_t
|
||||
*/
|
||||
static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
|
||||
{
|
||||
uint32_t reg = base->CTRL;
|
||||
|
||||
/* Clear flag bits to prevent accidentally clearing anything when writing back */
|
||||
reg &= ~(RTC_CTRL_ALARM1HZ_MASK | RTC_CTRL_WAKE1KHZ_MASK);
|
||||
|
||||
/* Write 1 to the flags we wish to clear */
|
||||
reg |= mask;
|
||||
|
||||
base->CTRL = reg;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Timer Start and Stop
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Starts the RTC time counter.
|
||||
*
|
||||
* After calling this function, the timer counter increments once a second provided SR[TOF] or
|
||||
* SR[TIF] are not set.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
*/
|
||||
static inline void RTC_StartTimer(RTC_Type *base)
|
||||
{
|
||||
base->CTRL |= RTC_CTRL_RTC_EN_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Stops the RTC time counter.
|
||||
*
|
||||
* RTC's seconds register can be written to only when the timer is stopped.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
*/
|
||||
static inline void RTC_StopTimer(RTC_Type *base)
|
||||
{
|
||||
base->CTRL &= ~RTC_CTRL_RTC_EN_MASK;
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @brief Performs a software reset on the RTC module.
|
||||
*
|
||||
* This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it.
|
||||
*
|
||||
* @param base RTC peripheral base address
|
||||
*/
|
||||
static inline void RTC_Reset(RTC_Type *base)
|
||||
{
|
||||
base->CTRL |= RTC_CTRL_SWRESET_MASK;
|
||||
base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
|
||||
}
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_RTC_H_ */
|
||||
540
Living_SDK/platform/mcu/lpc54102/drivers/fsl_sctimer.c
Normal file
540
Living_SDK/platform/mcu/lpc54102/drivers/fsl_sctimer.c
Normal file
|
|
@ -0,0 +1,540 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_sctimer.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
/*! @brief Typedef for interrupt handler. */
|
||||
typedef void (*sctimer_isr_t)(SCT_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Gets the instance from the base address
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
*
|
||||
* @return The SCTimer instance
|
||||
*/
|
||||
static uint32_t SCTIMER_GetInstance(SCT_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to SCT bases for each instance. */
|
||||
static SCT_Type *const s_sctBases[] = SCT_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to SCT clocks for each instance. */
|
||||
static const clock_ip_name_t s_sctClocks[] = SCT_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*! @brief Pointers to SCT resets for each instance. */
|
||||
static const reset_ip_name_t s_sctResets[] = SCT_RSTS;
|
||||
|
||||
/*!< @brief SCTimer event Callback function. */
|
||||
static sctimer_event_callback_t s_eventCallback[FSL_FEATURE_SCT_NUMBER_OF_EVENTS];
|
||||
|
||||
/*!< @brief Keep track of SCTimer event number */
|
||||
static uint32_t s_currentEvent;
|
||||
|
||||
/*!< @brief Keep track of SCTimer state number */
|
||||
static uint32_t s_currentState;
|
||||
|
||||
/*!< @brief Keep track of SCTimer match/capture register number */
|
||||
static uint32_t s_currentMatch;
|
||||
|
||||
/*! @brief Pointer to SCTimer IRQ handler */
|
||||
static sctimer_isr_t s_sctimerIsr;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t SCTIMER_GetInstance(SCT_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
uint32_t sctArrayCount = (sizeof(s_sctBases) / sizeof(s_sctBases[0]));
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < sctArrayCount; instance++)
|
||||
{
|
||||
if (s_sctBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < sctArrayCount);
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
uint32_t i;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the SCTimer clock*/
|
||||
CLOCK_EnableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Reset the module */
|
||||
RESET_PeripheralReset(s_sctResets[SCTIMER_GetInstance(base)]);
|
||||
|
||||
/* Setup the counter operation */
|
||||
base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) |
|
||||
SCT_CONFIG_UNIFY(config->enableCounterUnify);
|
||||
|
||||
/* Write to the control register, clear the counter and keep the counters halted */
|
||||
base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) |
|
||||
SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK;
|
||||
|
||||
if (!(config->enableCounterUnify))
|
||||
{
|
||||
base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) |
|
||||
SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK;
|
||||
}
|
||||
|
||||
/* Initial state of channel output */
|
||||
base->OUTPUT = config->outInitState;
|
||||
|
||||
/* Clear the global variables */
|
||||
s_currentEvent = 0;
|
||||
s_currentState = 0;
|
||||
s_currentMatch = 0;
|
||||
|
||||
/* Clear the callback array */
|
||||
for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++)
|
||||
{
|
||||
s_eventCallback[i] = NULL;
|
||||
}
|
||||
|
||||
/* Save interrupt handler */
|
||||
s_sctimerIsr = SCTIMER_EventHandleIRQ;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void SCTIMER_Deinit(SCT_Type *base)
|
||||
{
|
||||
/* Halt the counters */
|
||||
base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the SCTimer clock*/
|
||||
CLOCK_DisableClock(s_sctClocks[SCTIMER_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void SCTIMER_GetDefaultConfig(sctimer_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
/* SCT operates as a unified 32-bit counter */
|
||||
config->enableCounterUnify = true;
|
||||
/* System clock clocks the entire SCT module */
|
||||
config->clockMode = kSCTIMER_System_ClockMode;
|
||||
/* This is used only by certain clock modes */
|
||||
config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
|
||||
/* Up count mode only for the unified counter */
|
||||
config->enableBidirection_l = false;
|
||||
/* Up count mode only for Counte_H */
|
||||
config->enableBidirection_h = false;
|
||||
/* Prescale factor of 1 */
|
||||
config->prescale_l = 0;
|
||||
/* Prescale factor of 1 for Counter_H*/
|
||||
config->prescale_h = 0;
|
||||
/* Clear outputs */
|
||||
config->outInitState = 0;
|
||||
}
|
||||
|
||||
status_t SCTIMER_SetupPwm(SCT_Type *base,
|
||||
const sctimer_pwm_signal_param_t *pwmParams,
|
||||
sctimer_pwm_mode_t mode,
|
||||
uint32_t pwmFreq_Hz,
|
||||
uint32_t srcClock_Hz,
|
||||
uint32_t *event)
|
||||
{
|
||||
assert(pwmParams);
|
||||
assert(srcClock_Hz);
|
||||
assert(pwmFreq_Hz);
|
||||
|
||||
uint32_t period, pulsePeriod = 0;
|
||||
uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1);
|
||||
uint32_t periodEvent, pulseEvent;
|
||||
uint32_t reg;
|
||||
|
||||
/* This function will create 2 events, return an error if we do not have enough events available */
|
||||
if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
if (pwmParams->dutyCyclePercent == 0)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Set unify bit to operate in 32-bit counter mode */
|
||||
base->CONFIG |= SCT_CONFIG_UNIFY_MASK;
|
||||
|
||||
/* Use bi-directional mode for center-aligned PWM */
|
||||
if (mode == kSCTIMER_CenterAlignedPwm)
|
||||
{
|
||||
base->CTRL |= SCT_CTRL_BIDIR_L_MASK;
|
||||
}
|
||||
|
||||
/* Calculate PWM period match value */
|
||||
if (mode == kSCTIMER_EdgeAlignedPwm)
|
||||
{
|
||||
period = (sctClock / pwmFreq_Hz) - 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
period = sctClock / (pwmFreq_Hz * 2);
|
||||
}
|
||||
|
||||
/* Calculate pulse width match value */
|
||||
pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100;
|
||||
|
||||
/* For 100% dutycyle, make pulse period greater than period so the event will never occur */
|
||||
if (pwmParams->dutyCyclePercent >= 100)
|
||||
{
|
||||
pulsePeriod = period + 2;
|
||||
}
|
||||
|
||||
/* Schedule an event when we reach the PWM period */
|
||||
SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent);
|
||||
|
||||
/* Schedule an event when we reach the pulse width */
|
||||
SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent);
|
||||
|
||||
/* Reset the counter when we reach the PWM period */
|
||||
SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent);
|
||||
|
||||
/* Return the period event to the user */
|
||||
*event = periodEvent;
|
||||
|
||||
/* For high-true level */
|
||||
if (pwmParams->level == kSCTIMER_HighTrue)
|
||||
{
|
||||
/* Set the initial output level to low which is the inactive state */
|
||||
base->OUTPUT &= ~(1U << pwmParams->output);
|
||||
|
||||
if (mode == kSCTIMER_EdgeAlignedPwm)
|
||||
{
|
||||
/* Set the output when we reach the PWM period */
|
||||
SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent);
|
||||
/* Clear the output when we reach the PWM pulse value */
|
||||
SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the output when we reach the PWM pulse event */
|
||||
SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent);
|
||||
/* Reverse output when down counting */
|
||||
reg = base->OUTPUTDIRCTRL;
|
||||
reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
|
||||
reg |= (1U << (2 * pwmParams->output));
|
||||
base->OUTPUTDIRCTRL = reg;
|
||||
}
|
||||
}
|
||||
/* For low-true level */
|
||||
else
|
||||
{
|
||||
/* Set the initial output level to high which is the inactive state */
|
||||
base->OUTPUT |= (1U << pwmParams->output);
|
||||
|
||||
if (mode == kSCTIMER_EdgeAlignedPwm)
|
||||
{
|
||||
/* Clear the output when we reach the PWM period */
|
||||
SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent);
|
||||
/* Set the output when we reach the PWM pulse value */
|
||||
SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the output when we reach the PWM pulse event */
|
||||
SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent);
|
||||
/* Reverse output when down counting */
|
||||
reg = base->OUTPUTDIRCTRL;
|
||||
reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output));
|
||||
reg |= (1U << (2 * pwmParams->output));
|
||||
base->OUTPUTDIRCTRL = reg;
|
||||
}
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event)
|
||||
|
||||
{
|
||||
assert(dutyCyclePercent > 0);
|
||||
|
||||
uint32_t periodMatchReg, pulseMatchReg;
|
||||
uint32_t pulsePeriod = 0, period;
|
||||
|
||||
/* Retrieve the match register number for the PWM period */
|
||||
periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
|
||||
|
||||
/* Retrieve the match register number for the PWM pulse period */
|
||||
pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK;
|
||||
|
||||
period = base->SCTMATCH[periodMatchReg];
|
||||
|
||||
/* Calculate pulse width match value */
|
||||
pulsePeriod = (period * dutyCyclePercent) / 100;
|
||||
|
||||
/* For 100% dutycyle, make pulse period greater than period so the event will never occur */
|
||||
if (dutyCyclePercent >= 100)
|
||||
{
|
||||
pulsePeriod = period + 2;
|
||||
}
|
||||
|
||||
/* Stop the counter before updating match register */
|
||||
SCTIMER_StopTimer(base, kSCTIMER_Counter_L);
|
||||
|
||||
/* Update dutycycle */
|
||||
base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod);
|
||||
base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod);
|
||||
|
||||
/* Restart the counter */
|
||||
SCTIMER_StartTimer(base, kSCTIMER_Counter_L);
|
||||
}
|
||||
|
||||
status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
|
||||
sctimer_event_t howToMonitor,
|
||||
uint32_t matchValue,
|
||||
uint32_t whichIO,
|
||||
sctimer_counter_t whichCounter,
|
||||
uint32_t *event)
|
||||
{
|
||||
uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT);
|
||||
uint32_t currentCtrlVal = howToMonitor;
|
||||
|
||||
/* Return an error if we have hit the limit in terms of number of events created */
|
||||
if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* IO only mode */
|
||||
if (combMode == 0x2U)
|
||||
{
|
||||
base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO);
|
||||
}
|
||||
/* Match mode only */
|
||||
else if (combMode == 0x1U)
|
||||
{
|
||||
/* Return an error if we have hit the limit in terms of number of number of match registers */
|
||||
if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch);
|
||||
/* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
|
||||
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
|
||||
{
|
||||
base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
|
||||
base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Select the counter, no need for this if operating in 32-bit mode */
|
||||
currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
|
||||
base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
|
||||
base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
|
||||
}
|
||||
base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
|
||||
/* Increment the match register number */
|
||||
s_currentMatch++;
|
||||
}
|
||||
/* Use both Match & IO */
|
||||
else
|
||||
{
|
||||
/* Return an error if we have hit the limit in terms of number of number of match registers */
|
||||
if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO);
|
||||
/* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
|
||||
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
|
||||
{
|
||||
base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue);
|
||||
base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Select the counter, no need for this if operating in 32-bit mode */
|
||||
currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter);
|
||||
base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue);
|
||||
base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue);
|
||||
}
|
||||
base->EVENT[s_currentEvent].CTRL = currentCtrlVal;
|
||||
/* Increment the match register number */
|
||||
s_currentMatch++;
|
||||
}
|
||||
|
||||
/* Enable the event in the current state */
|
||||
base->EVENT[s_currentEvent].STATE = (1U << s_currentState);
|
||||
|
||||
/* Return the event number */
|
||||
*event = s_currentEvent;
|
||||
|
||||
/* Increment the event number */
|
||||
s_currentEvent++;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event)
|
||||
{
|
||||
/* Enable event in the current state */
|
||||
base->EVENT[event].STATE |= (1U << s_currentState);
|
||||
}
|
||||
|
||||
status_t SCTIMER_IncreaseState(SCT_Type *base)
|
||||
{
|
||||
/* Return an error if we have hit the limit in terms of states used */
|
||||
if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
s_currentState++;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
uint32_t SCTIMER_GetCurrentState(SCT_Type *base)
|
||||
{
|
||||
return s_currentState;
|
||||
}
|
||||
|
||||
void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
/* Set the same event to set and clear the output */
|
||||
base->OUT[whichIO].CLR |= (1U << event);
|
||||
base->OUT[whichIO].SET |= (1U << event);
|
||||
|
||||
/* Set the conflict resolution to toggle output */
|
||||
reg = base->RES;
|
||||
reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO));
|
||||
reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO));
|
||||
base->RES = reg;
|
||||
}
|
||||
|
||||
status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
|
||||
sctimer_counter_t whichCounter,
|
||||
uint32_t *captureRegister,
|
||||
uint32_t event)
|
||||
{
|
||||
/* Return an error if we have hit the limit in terms of number of capture/match registers used */
|
||||
if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE)
|
||||
{
|
||||
return kStatus_Fail;
|
||||
}
|
||||
|
||||
/* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
|
||||
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
|
||||
{
|
||||
/* Set the bit to enable event */
|
||||
base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event);
|
||||
|
||||
/* Set this resource to be a capture rather than match */
|
||||
base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set bit to enable event */
|
||||
base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event);
|
||||
|
||||
/* Set this resource to be a capture rather than match */
|
||||
base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch);
|
||||
}
|
||||
|
||||
/* Return the match register number */
|
||||
*captureRegister = s_currentMatch;
|
||||
|
||||
/* Increase the match register number */
|
||||
s_currentMatch++;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event)
|
||||
{
|
||||
s_eventCallback[event] = callback;
|
||||
}
|
||||
|
||||
void SCTIMER_EventHandleIRQ(SCT_Type *base)
|
||||
{
|
||||
uint32_t eventFlag = SCT0->EVFLAG;
|
||||
/* Only clear the flags whose interrupt field is enabled */
|
||||
uint32_t clearFlag = (eventFlag & SCT0->EVEN);
|
||||
uint32_t mask = eventFlag;
|
||||
int i = 0;
|
||||
|
||||
/* Invoke the callback for certain events */
|
||||
for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++)
|
||||
{
|
||||
if (mask & 0x1)
|
||||
{
|
||||
if (s_eventCallback[i] != NULL)
|
||||
{
|
||||
s_eventCallback[i]();
|
||||
}
|
||||
}
|
||||
mask >>= 1;
|
||||
}
|
||||
|
||||
/* Clear event interrupt flag */
|
||||
SCT0->EVFLAG = clearFlag;
|
||||
}
|
||||
|
||||
void SCT0_IRQHandler(void)
|
||||
{
|
||||
s_sctimerIsr(SCT0);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
822
Living_SDK/platform/mcu/lpc54102/drivers/fsl_sctimer.h
Normal file
822
Living_SDK/platform/mcu/lpc54102/drivers/fsl_sctimer.h
Normal file
|
|
@ -0,0 +1,822 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_SCTIMER_H_
|
||||
#define _FSL_SCTIMER_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup sctimer
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
|
||||
/*@}*/
|
||||
|
||||
/*! @brief SCTimer PWM operation modes */
|
||||
typedef enum _sctimer_pwm_mode
|
||||
{
|
||||
kSCTIMER_EdgeAlignedPwm = 0U, /*!< Edge-aligned PWM */
|
||||
kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */
|
||||
} sctimer_pwm_mode_t;
|
||||
|
||||
/*! @brief SCTimer counters when working as two independent 16-bit counters */
|
||||
typedef enum _sctimer_counter
|
||||
{
|
||||
kSCTIMER_Counter_L = 0U, /*!< Counter L */
|
||||
kSCTIMER_Counter_H /*!< Counter H */
|
||||
} sctimer_counter_t;
|
||||
|
||||
/*! @brief List of SCTimer input pins */
|
||||
typedef enum _sctimer_input
|
||||
{
|
||||
kSCTIMER_Input_0 = 0U, /*!< SCTIMER input 0 */
|
||||
kSCTIMER_Input_1, /*!< SCTIMER input 1 */
|
||||
kSCTIMER_Input_2, /*!< SCTIMER input 2 */
|
||||
kSCTIMER_Input_3, /*!< SCTIMER input 3 */
|
||||
kSCTIMER_Input_4, /*!< SCTIMER input 4 */
|
||||
kSCTIMER_Input_5, /*!< SCTIMER input 5 */
|
||||
kSCTIMER_Input_6, /*!< SCTIMER input 6 */
|
||||
kSCTIMER_Input_7 /*!< SCTIMER input 7 */
|
||||
} sctimer_input_t;
|
||||
|
||||
/*! @brief List of SCTimer output pins */
|
||||
typedef enum _sctimer_out
|
||||
{
|
||||
kSCTIMER_Out_0 = 0U, /*!< SCTIMER output 0*/
|
||||
kSCTIMER_Out_1, /*!< SCTIMER output 1 */
|
||||
kSCTIMER_Out_2, /*!< SCTIMER output 2 */
|
||||
kSCTIMER_Out_3, /*!< SCTIMER output 3 */
|
||||
kSCTIMER_Out_4, /*!< SCTIMER output 4 */
|
||||
kSCTIMER_Out_5, /*!< SCTIMER output 5 */
|
||||
kSCTIMER_Out_6, /*!< SCTIMER output 6 */
|
||||
kSCTIMER_Out_7 /*!< SCTIMER output 7 */
|
||||
} sctimer_out_t;
|
||||
|
||||
/*! @brief SCTimer PWM output pulse mode: high-true, low-true or no output */
|
||||
typedef enum _sctimer_pwm_level_select
|
||||
{
|
||||
kSCTIMER_LowTrue = 0U, /*!< Low true pulses */
|
||||
kSCTIMER_HighTrue /*!< High true pulses */
|
||||
} sctimer_pwm_level_select_t;
|
||||
|
||||
/*! @brief Options to configure a SCTimer PWM signal */
|
||||
typedef struct _sctimer_pwm_signal_param
|
||||
{
|
||||
sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */
|
||||
sctimer_pwm_level_select_t level; /*!< PWM output active level select. */
|
||||
uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 1 to 100
|
||||
100 = always active signal (100% duty cycle).*/
|
||||
} sctimer_pwm_signal_param_t;
|
||||
|
||||
/*! @brief SCTimer clock mode options */
|
||||
typedef enum _sctimer_clock_mode
|
||||
{
|
||||
kSCTIMER_System_ClockMode = 0U, /*!< System Clock Mode */
|
||||
kSCTIMER_Sampled_ClockMode, /*!< Sampled System Clock Mode */
|
||||
kSCTIMER_Input_ClockMode, /*!< SCT Input Clock Mode */
|
||||
kSCTIMER_Asynchronous_ClockMode /*!< Asynchronous Mode */
|
||||
} sctimer_clock_mode_t;
|
||||
|
||||
/*! @brief SCTimer clock select options */
|
||||
typedef enum _sctimer_clock_select
|
||||
{
|
||||
kSCTIMER_Clock_On_Rise_Input_0 = 0U, /*!< Rising edges on input 0 */
|
||||
kSCTIMER_Clock_On_Fall_Input_0, /*!< Falling edges on input 0 */
|
||||
kSCTIMER_Clock_On_Rise_Input_1, /*!< Rising edges on input 1 */
|
||||
kSCTIMER_Clock_On_Fall_Input_1, /*!< Falling edges on input 1 */
|
||||
kSCTIMER_Clock_On_Rise_Input_2, /*!< Rising edges on input 2 */
|
||||
kSCTIMER_Clock_On_Fall_Input_2, /*!< Falling edges on input 2 */
|
||||
kSCTIMER_Clock_On_Rise_Input_3, /*!< Rising edges on input 3 */
|
||||
kSCTIMER_Clock_On_Fall_Input_3, /*!< Falling edges on input 3 */
|
||||
kSCTIMER_Clock_On_Rise_Input_4, /*!< Rising edges on input 4 */
|
||||
kSCTIMER_Clock_On_Fall_Input_4, /*!< Falling edges on input 4 */
|
||||
kSCTIMER_Clock_On_Rise_Input_5, /*!< Rising edges on input 5 */
|
||||
kSCTIMER_Clock_On_Fall_Input_5, /*!< Falling edges on input 5 */
|
||||
kSCTIMER_Clock_On_Rise_Input_6, /*!< Rising edges on input 6 */
|
||||
kSCTIMER_Clock_On_Fall_Input_6, /*!< Falling edges on input 6 */
|
||||
kSCTIMER_Clock_On_Rise_Input_7, /*!< Rising edges on input 7 */
|
||||
kSCTIMER_Clock_On_Fall_Input_7 /*!< Falling edges on input 7 */
|
||||
} sctimer_clock_select_t;
|
||||
|
||||
/*!
|
||||
* @brief SCTimer output conflict resolution options.
|
||||
*
|
||||
* Specifies what action should be taken if multiple events dictate that a given output should be
|
||||
* both set and cleared at the same time
|
||||
*/
|
||||
typedef enum _sctimer_conflict_resolution
|
||||
{
|
||||
kSCTIMER_ResolveNone = 0U, /*!< No change */
|
||||
kSCTIMER_ResolveSet, /*!< Set output */
|
||||
kSCTIMER_ResolveClear, /*!< Clear output */
|
||||
kSCTIMER_ResolveToggle /*!< Toggle output */
|
||||
} sctimer_conflict_resolution_t;
|
||||
|
||||
/*! @brief List of SCTimer event types */
|
||||
typedef enum _sctimer_event
|
||||
{
|
||||
kSCTIMER_InputLowOrMatchEvent =
|
||||
(0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_InputRiseOrMatchEvent =
|
||||
(0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_InputFallOrMatchEvent =
|
||||
(0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_InputHighOrMatchEvent =
|
||||
(0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
|
||||
kSCTIMER_MatchEventOnly =
|
||||
(1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
|
||||
kSCTIMER_InputLowEvent =
|
||||
(2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_InputRiseEvent =
|
||||
(2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_InputFallEvent =
|
||||
(2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_InputHighEvent =
|
||||
(2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
|
||||
kSCTIMER_InputLowAndMatchEvent =
|
||||
(3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_InputRiseAndMatchEvent =
|
||||
(3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_InputFallAndMatchEvent =
|
||||
(3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_InputHighAndMatchEvent =
|
||||
(3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
|
||||
kSCTIMER_OutputLowOrMatchEvent =
|
||||
(0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_OutputRiseOrMatchEvent =
|
||||
(0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_OutputFallOrMatchEvent =
|
||||
(0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_OutputHighOrMatchEvent =
|
||||
(0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
|
||||
kSCTIMER_OutputLowEvent =
|
||||
(2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_OutputRiseEvent =
|
||||
(2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_OutputFallEvent =
|
||||
(2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_OutputHighEvent =
|
||||
(2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
|
||||
kSCTIMER_OutputLowAndMatchEvent =
|
||||
(3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_OutputRiseAndMatchEvent =
|
||||
(3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_OutputFallAndMatchEvent =
|
||||
(3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT),
|
||||
kSCTIMER_OutputHighAndMatchEvent =
|
||||
(3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT)
|
||||
} sctimer_event_t;
|
||||
|
||||
/*! @brief SCTimer callback typedef. */
|
||||
typedef void (*sctimer_event_callback_t)(void);
|
||||
|
||||
/*! @brief List of SCTimer interrupts */
|
||||
typedef enum _sctimer_interrupt_enable
|
||||
{
|
||||
kSCTIMER_Event0InterruptEnable = (1U << 0), /*!< Event 0 interrupt */
|
||||
kSCTIMER_Event1InterruptEnable = (1U << 1), /*!< Event 1 interrupt */
|
||||
kSCTIMER_Event2InterruptEnable = (1U << 2), /*!< Event 2 interrupt */
|
||||
kSCTIMER_Event3InterruptEnable = (1U << 3), /*!< Event 3 interrupt */
|
||||
kSCTIMER_Event4InterruptEnable = (1U << 4), /*!< Event 4 interrupt */
|
||||
kSCTIMER_Event5InterruptEnable = (1U << 5), /*!< Event 5 interrupt */
|
||||
kSCTIMER_Event6InterruptEnable = (1U << 6), /*!< Event 6 interrupt */
|
||||
kSCTIMER_Event7InterruptEnable = (1U << 7), /*!< Event 7 interrupt */
|
||||
kSCTIMER_Event8InterruptEnable = (1U << 8), /*!< Event 8 interrupt */
|
||||
kSCTIMER_Event9InterruptEnable = (1U << 9), /*!< Event 9 interrupt */
|
||||
kSCTIMER_Event10InterruptEnable = (1U << 10), /*!< Event 10 interrupt */
|
||||
kSCTIMER_Event11InterruptEnable = (1U << 11), /*!< Event 11 interrupt */
|
||||
kSCTIMER_Event12InterruptEnable = (1U << 12), /*!< Event 12 interrupt */
|
||||
} sctimer_interrupt_enable_t;
|
||||
|
||||
/*! @brief List of SCTimer flags */
|
||||
typedef enum _sctimer_status_flags
|
||||
{
|
||||
kSCTIMER_Event0Flag = (1U << 0), /*!< Event 0 Flag */
|
||||
kSCTIMER_Event1Flag = (1U << 1), /*!< Event 1 Flag */
|
||||
kSCTIMER_Event2Flag = (1U << 2), /*!< Event 2 Flag */
|
||||
kSCTIMER_Event3Flag = (1U << 3), /*!< Event 3 Flag */
|
||||
kSCTIMER_Event4Flag = (1U << 4), /*!< Event 4 Flag */
|
||||
kSCTIMER_Event5Flag = (1U << 5), /*!< Event 5 Flag */
|
||||
kSCTIMER_Event6Flag = (1U << 6), /*!< Event 6 Flag */
|
||||
kSCTIMER_Event7Flag = (1U << 7), /*!< Event 7 Flag */
|
||||
kSCTIMER_Event8Flag = (1U << 8), /*!< Event 8 Flag */
|
||||
kSCTIMER_Event9Flag = (1U << 9), /*!< Event 9 Flag */
|
||||
kSCTIMER_Event10Flag = (1U << 10), /*!< Event 10 Flag */
|
||||
kSCTIMER_Event11Flag = (1U << 11), /*!< Event 11 Flag */
|
||||
kSCTIMER_Event12Flag = (1U << 12), /*!< Event 12 Flag */
|
||||
kSCTIMER_BusErrorLFlag =
|
||||
(1U << SCT_CONFLAG_BUSERRL_SHIFT), /*!< Bus error due to write when L counter was not halted */
|
||||
kSCTIMER_BusErrorHFlag =
|
||||
(1U << SCT_CONFLAG_BUSERRH_SHIFT) /*!< Bus error due to write when H counter was not halted */
|
||||
} sctimer_status_flags_t;
|
||||
|
||||
/*!
|
||||
* @brief SCTimer configuration structure
|
||||
*
|
||||
* This structure holds the configuration settings for the SCTimer peripheral. To initialize this
|
||||
* structure to reasonable defaults, call the SCTMR_GetDefaultConfig() function and pass a
|
||||
* pointer to the configuration structure instance.
|
||||
*
|
||||
* The configuration structure can be made constant so as to reside in flash.
|
||||
*/
|
||||
typedef struct _sctimer_config
|
||||
{
|
||||
bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter;
|
||||
false: SCT operates as two 16-bit counters */
|
||||
sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */
|
||||
sctimer_clock_select_t clockSelect; /*!< SCT clock select value */
|
||||
bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter
|
||||
false: Up count mode only for the L or unified counter */
|
||||
bool enableBidirection_h; /*!< true: Up-down count mode for the H or unified counter
|
||||
false: Up count mode only for the H or unified counter.
|
||||
This field is used only if the enableCounterUnify is set
|
||||
to false */
|
||||
uint8_t prescale_l; /*!< Prescale value to produce the L or unified counter clock */
|
||||
uint8_t prescale_h; /*!< Prescale value to produce the H counter clock.
|
||||
This field is used only if the enableCounterUnify is set
|
||||
to false */
|
||||
uint8_t outInitState; /*!< Defines the initial output value */
|
||||
} sctimer_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Ungates the SCTimer clock and configures the peripheral for basic operation.
|
||||
*
|
||||
* @note This API should be called at the beginning of the application using the SCTimer driver.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param config Pointer to the user configuration structure.
|
||||
*
|
||||
* @return kStatus_Success indicates success; Else indicates failure.
|
||||
*/
|
||||
status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Gates the SCTimer clock.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
*/
|
||||
void SCTIMER_Deinit(SCT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Fills in the SCTimer configuration structure with the default settings.
|
||||
*
|
||||
* The default values are:
|
||||
* @code
|
||||
* config->enableCounterUnify = true;
|
||||
* config->clockMode = kSCTIMER_System_ClockMode;
|
||||
* config->clockSelect = kSCTIMER_Clock_On_Rise_Input_0;
|
||||
* config->enableBidirection_l = false;
|
||||
* config->enableBidirection_h = false;
|
||||
* config->prescale_l = 0;
|
||||
* config->prescale_h = 0;
|
||||
* config->outInitState = 0;
|
||||
* @endcode
|
||||
* @param config Pointer to the user configuration structure.
|
||||
*/
|
||||
void SCTIMER_GetDefaultConfig(sctimer_config_t *config);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name PWM setup operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Configures the PWM signal parameters.
|
||||
*
|
||||
* Call this function to configure the PWM signal period, mode, duty cycle, and edge. This
|
||||
* function will create 2 events; one of the events will trigger on match with the pulse value
|
||||
* and the other will trigger when the counter matches the PWM period. The PWM period event is
|
||||
* also used as a limit event to reset the counter or change direction. Both events are enabled
|
||||
* for the same state. The state number can be retrieved by calling the function
|
||||
* SCTIMER_GetCurrentStateNumber().
|
||||
* The counter is set to operate as one 32-bit counter (unify bit is set to 1).
|
||||
* The counter operates in bi-directional mode when generating a center-aligned PWM.
|
||||
*
|
||||
* @note When setting PWM output from multiple output pins, they all should use the same PWM mode
|
||||
* i.e all PWM's should be either edge-aligned or center-aligned.
|
||||
* When using this API, the PWM signal frequency of all the initialized channels must be the same.
|
||||
* Otherwise all the initialized channels' PWM signal frequency is equal to the last call to the
|
||||
* API's pwmFreq_Hz.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param pwmParams PWM parameters to configure the output
|
||||
* @param mode PWM operation mode, options available in enumeration ::sctimer_pwm_mode_t
|
||||
* @param pwmFreq_Hz PWM signal frequency in Hz
|
||||
* @param srcClock_Hz SCTimer counter clock in Hz
|
||||
* @param event Pointer to a variable where the PWM period event number is stored
|
||||
*
|
||||
* @return kStatus_Success on success
|
||||
* kStatus_Fail If we have hit the limit in terms of number of events created or if
|
||||
* an incorrect PWM dutycylce is passed in.
|
||||
*/
|
||||
status_t SCTIMER_SetupPwm(SCT_Type *base,
|
||||
const sctimer_pwm_signal_param_t *pwmParams,
|
||||
sctimer_pwm_mode_t mode,
|
||||
uint32_t pwmFreq_Hz,
|
||||
uint32_t srcClock_Hz,
|
||||
uint32_t *event);
|
||||
|
||||
/*!
|
||||
* @brief Updates the duty cycle of an active PWM signal.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param output The output to configure
|
||||
* @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100
|
||||
* @param event Event number associated with this PWM signal. This was returned to the user by the
|
||||
* function SCTIMER_SetupPwm().
|
||||
*/
|
||||
void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event);
|
||||
|
||||
/*!
|
||||
* @name Interrupt Interface
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the selected SCTimer interrupts.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param mask The interrupts to enable. This is a logical OR of members of the
|
||||
* enumeration ::sctimer_interrupt_enable_t
|
||||
*/
|
||||
static inline void SCTIMER_EnableInterrupts(SCT_Type *base, uint32_t mask)
|
||||
{
|
||||
base->EVEN |= mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the selected SCTimer interrupts.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param mask The interrupts to enable. This is a logical OR of members of the
|
||||
* enumeration ::sctimer_interrupt_enable_t
|
||||
*/
|
||||
static inline void SCTIMER_DisableInterrupts(SCT_Type *base, uint32_t mask)
|
||||
{
|
||||
base->EVEN &= ~mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the enabled SCTimer interrupts.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
*
|
||||
* @return The enabled interrupts. This is the logical OR of members of the
|
||||
* enumeration ::sctimer_interrupt_enable_t
|
||||
*/
|
||||
static inline uint32_t SCTIMER_GetEnabledInterrupts(SCT_Type *base)
|
||||
{
|
||||
return (base->EVEN & 0xFFFFU);
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Status Interface
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the SCTimer status flags.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
*
|
||||
* @return The status flags. This is the logical OR of members of the
|
||||
* enumeration ::sctimer_status_flags_t
|
||||
*/
|
||||
static inline uint32_t SCTIMER_GetStatusFlags(SCT_Type *base)
|
||||
{
|
||||
uint32_t statusFlags = 0;
|
||||
|
||||
/* Add the recorded events */
|
||||
statusFlags = (base->EVFLAG & 0xFFFFU);
|
||||
|
||||
/* Add bus error flags */
|
||||
statusFlags |= (base->CONFLAG & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK));
|
||||
|
||||
return statusFlags;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clears the SCTimer status flags.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param mask The status flags to clear. This is a logical OR of members of the
|
||||
* enumeration ::sctimer_status_flags_t
|
||||
*/
|
||||
static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask)
|
||||
{
|
||||
/* Write to the flag registers */
|
||||
base->EVFLAG = (mask & 0xFFFFU);
|
||||
base->CONFLAG = (mask & (SCT_CONFLAG_BUSERRL_MASK | SCT_CONFLAG_BUSERRH_MASK));
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Counter Start and Stop
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Starts the SCTimer counter.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param countertoStart SCTimer counter to start; if unify mode is set then function always
|
||||
* writes to HALT_L bit
|
||||
*/
|
||||
static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart)
|
||||
{
|
||||
/* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */
|
||||
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L))
|
||||
{
|
||||
base->CTRL &= ~(SCT_CTRL_HALT_L_MASK);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Start H counter */
|
||||
base->CTRL &= ~(SCT_CTRL_HALT_H_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Halts the SCTimer counter.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param countertoStop SCTimer counter to stop; if unify mode is set then function always
|
||||
* writes to HALT_L bit
|
||||
*/
|
||||
static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop)
|
||||
{
|
||||
/* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */
|
||||
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L))
|
||||
{
|
||||
base->CTRL |= (SCT_CTRL_HALT_L_MASK);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Stop H counter */
|
||||
base->CTRL |= (SCT_CTRL_HALT_H_MASK);
|
||||
}
|
||||
}
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Functions to create a new event and manage the state logic
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Create an event that is triggered on a match or IO and schedule in current state.
|
||||
*
|
||||
* This function will configure an event using the options provided by the user. If the event type uses
|
||||
* the counter match, then the function will set the user provided match value into a match register
|
||||
* and put this match register number into the event control register.
|
||||
* The event is enabled for the current state and the event number is increased by one at the end.
|
||||
* The function returns the event number; this event number can be used to configure actions to be
|
||||
* done when this event is triggered.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t
|
||||
* @param matchValue The match value that will be programmed to a match register
|
||||
* @param whichIO The input or output that will be involved in event triggering. This field
|
||||
* is ignored if the event type is "match only"
|
||||
* @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
|
||||
* field has no meaning as we have only 1 unified counter; hence ignored.
|
||||
* @param event Pointer to a variable where the new event number is stored
|
||||
*
|
||||
* @return kStatus_Success on success
|
||||
* kStatus_Error if we have hit the limit in terms of number of events created or
|
||||
if we have reached the limit in terms of number of match registers
|
||||
*/
|
||||
status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base,
|
||||
sctimer_event_t howToMonitor,
|
||||
uint32_t matchValue,
|
||||
uint32_t whichIO,
|
||||
sctimer_counter_t whichCounter,
|
||||
uint32_t *event);
|
||||
|
||||
/*!
|
||||
* @brief Enable an event in the current state.
|
||||
*
|
||||
* This function will allow the event passed in to trigger in the current state. The event must
|
||||
* be created earlier by either calling the function SCTIMER_SetupPwm() or function
|
||||
* SCTIMER_CreateAndScheduleEvent() .
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param event Event number to enable in the current state
|
||||
*
|
||||
*/
|
||||
void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event);
|
||||
|
||||
/*!
|
||||
* @brief Increase the state by 1
|
||||
*
|
||||
* All future events created by calling the function SCTIMER_ScheduleEvent() will be enabled in this new
|
||||
* state.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
*
|
||||
* @return kStatus_Success on success
|
||||
* kStatus_Error if we have hit the limit in terms of states used
|
||||
|
||||
*/
|
||||
status_t SCTIMER_IncreaseState(SCT_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Provides the current state
|
||||
*
|
||||
* User can use this to set the next state by calling the function SCTIMER_SetupNextStateAction().
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
*
|
||||
* @return The current state
|
||||
*/
|
||||
uint32_t SCTIMER_GetCurrentState(SCT_Type *base);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
/*!
|
||||
* @name Actions to take in response to an event
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Setup capture of the counter value on trigger of a selected event
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
|
||||
* field has no meaning as only the Counter_L bits are used.
|
||||
* @param captureRegister Pointer to a variable where the capture register number will be returned. User
|
||||
* can read the captured value from this register when the specified event is triggered.
|
||||
* @param event Event number that will trigger the capture
|
||||
*
|
||||
* @return kStatus_Success on success
|
||||
* kStatus_Error if we have hit the limit in terms of number of match/capture registers available
|
||||
*/
|
||||
status_t SCTIMER_SetupCaptureAction(SCT_Type *base,
|
||||
sctimer_counter_t whichCounter,
|
||||
uint32_t *captureRegister,
|
||||
uint32_t event);
|
||||
|
||||
/*!
|
||||
* @brief Receive noticification when the event trigger an interrupt.
|
||||
*
|
||||
* If the interrupt for the event is enabled by the user, then a callback can be registered
|
||||
* which will be invoked when the event is triggered
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param event Event number that will trigger the interrupt
|
||||
* @param callback Function to invoke when the event is triggered
|
||||
*/
|
||||
|
||||
void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event);
|
||||
|
||||
/*!
|
||||
* @brief Transition to the specified state.
|
||||
*
|
||||
* This transition will be triggered by the event number that is passed in by the user.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param nextState The next state SCTimer will transition to
|
||||
* @param event Event number that will trigger the state transition
|
||||
*/
|
||||
static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event)
|
||||
{
|
||||
uint32_t reg = base->EVENT[event].CTRL;
|
||||
|
||||
reg &= ~(SCT_EVENT_CTRL_STATEV_MASK);
|
||||
/* Load the STATEV value when the event occurs to be the next state */
|
||||
reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK;
|
||||
|
||||
base->EVENT[event].CTRL = reg;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set the Output.
|
||||
*
|
||||
* This output will be set when the event number that is passed in by the user is triggered.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param whichIO The output to set
|
||||
* @param event Event number that will trigger the output change
|
||||
*/
|
||||
static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
|
||||
{
|
||||
base->OUT[whichIO].SET |= (1U << event);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear the Output.
|
||||
*
|
||||
* This output will be cleared when the event number that is passed in by the user is triggered.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param whichIO The output to clear
|
||||
* @param event Event number that will trigger the output change
|
||||
*/
|
||||
static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event)
|
||||
{
|
||||
base->OUT[whichIO].CLR |= (1U << event);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Toggle the output level.
|
||||
*
|
||||
* This change in the output level is triggered by the event number that is passed in by the user.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param whichIO The output to toggle
|
||||
* @param event Event number that will trigger the output change
|
||||
*/
|
||||
void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event);
|
||||
|
||||
/*!
|
||||
* @brief Limit the running counter.
|
||||
*
|
||||
* The counter is limited when the event number that is passed in by the user is triggered.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
|
||||
* field has no meaning as only the Counter_L bits are used.
|
||||
* @param event Event number that will trigger the counter to be limited
|
||||
*/
|
||||
static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
|
||||
{
|
||||
/* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
|
||||
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
|
||||
{
|
||||
base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event);
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Stop the running counter.
|
||||
*
|
||||
* The counter is stopped when the event number that is passed in by the user is triggered.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
|
||||
* field has no meaning as only the Counter_L bits are used.
|
||||
* @param event Event number that will trigger the counter to be stopped
|
||||
*/
|
||||
static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
|
||||
{
|
||||
/* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
|
||||
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
|
||||
{
|
||||
base->STOP |= SCT_STOP_STOPMSK_L(1U << event);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->STOP |= SCT_STOP_STOPMSK_H(1U << event);
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Re-start the stopped counter.
|
||||
*
|
||||
* The counter will re-start when the event number that is passed in by the user is triggered.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
|
||||
* field has no meaning as only the Counter_L bits are used.
|
||||
* @param event Event number that will trigger the counter to re-start
|
||||
*/
|
||||
static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
|
||||
{
|
||||
/* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
|
||||
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
|
||||
{
|
||||
base->START |= SCT_START_STARTMSK_L(1U << event);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->START |= SCT_START_STARTMSK_H(1U << event);
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Halt the running counter.
|
||||
*
|
||||
* The counter is disabled (halted) when the event number that is passed in by the user is
|
||||
* triggered. When the counter is halted, all further events are disabled. The HALT condition
|
||||
* can only be removed by calling the SCTIMER_StartTimer() function.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this
|
||||
* field has no meaning as only the Counter_L bits are used.
|
||||
* @param event Event number that will trigger the counter to be halted
|
||||
*/
|
||||
static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event)
|
||||
{
|
||||
/* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */
|
||||
if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L))
|
||||
{
|
||||
base->HALT |= SCT_HALT_HALTMSK_L(1U << event);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->HALT |= SCT_HALT_HALTMSK_H(1U << event);
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Generate a DMA request.
|
||||
*
|
||||
* DMA request will be triggered by the event number that is passed in by the user.
|
||||
*
|
||||
* @param base SCTimer peripheral base address
|
||||
* @param dmaNumber The DMA request to generate
|
||||
* @param event Event number that will trigger the DMA request
|
||||
*/
|
||||
static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event)
|
||||
{
|
||||
if (dmaNumber == 0)
|
||||
{
|
||||
base->DMA0REQUEST |= (1U << event);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->DMA1REQUEST |= (1U << event);
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief SCTimer interrupt handler.
|
||||
*
|
||||
* @param base SCTimer peripheral base address.
|
||||
*/
|
||||
void SCTIMER_EventHandleIRQ(SCT_Type *base);
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_SCTIMER_H_ */
|
||||
1307
Living_SDK/platform/mcu/lpc54102/drivers/fsl_spi.c
Normal file
1307
Living_SDK/platform/mcu/lpc54102/drivers/fsl_spi.c
Normal file
File diff suppressed because it is too large
Load diff
833
Living_SDK/platform/mcu/lpc54102/drivers/fsl_spi.h
Normal file
833
Living_SDK/platform/mcu/lpc54102/drivers/fsl_spi.h
Normal file
|
|
@ -0,0 +1,833 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NXP Semiconductors, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_SPI_H_
|
||||
#define _FSL_SPI_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup spi_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief USART driver version 2.0.0. */
|
||||
#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
#ifndef SPI_DUMMYDATA
|
||||
/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */
|
||||
#define SPI_DUMMYDATA (0xFFU)
|
||||
#endif
|
||||
|
||||
#define SPI_ASSERT_SSELNUM(n) ((~(1U << ((n) + 16))) & 0xF0000)
|
||||
#define SPI_DEASSERT_SSELNUM(n) (1U << ((n) + 16))
|
||||
#define SPI_DEASSERT_ALL (0xF0000)
|
||||
|
||||
#define SPI_FIFO_GETRXTHRESHOLD(base) \
|
||||
((SPI0 == base) ? \
|
||||
((VFIFO->SPI[0].CFGSPI & VFIFO_SPI_CFGSPI_RXTHRESHOLD_MASK) >> VFIFO_SPI_CFGSPI_RXTHRESHOLD_SHIFT) : \
|
||||
((VFIFO->SPI[1].CFGSPI & VFIFO_SPI_CFGSPI_RXTHRESHOLD_MASK) >> VFIFO_SPI_CFGSPI_RXTHRESHOLD_SHIFT))
|
||||
#define SPI_FIFO_GETTXTHRESHOLD(base) \
|
||||
((SPI0 == base) ? \
|
||||
((VFIFO->SPI[0].CFGSPI & VFIFO_SPI_CFGSPI_TXTHRESHOLD_MASK) >> VFIFO_SPI_CFGSPI_TXTHRESHOLD_SHIFT) : \
|
||||
((VFIFO->SPI[1].CFGSPI & VFIFO_SPI_CFGSPI_TXTHRESHOLD_MASK) >> VFIFO_SPI_CFGSPI_TXTHRESHOLD_SHIFT))
|
||||
|
||||
/*! @brief SPI transfer option.*/
|
||||
typedef enum _spi_xfer_option
|
||||
{
|
||||
kSPI_FrameDelay = (SPI_TXDATCTL_EOF_MASK), /*!< Delay chip select */
|
||||
kSPI_FrameAssert = (SPI_TXDATCTL_EOT_MASK), /*!< When transfer ends, assert chip select */
|
||||
kSPI_ReceiveIgnore = (SPI_TXDATCTL_RXIGNORE_MASK), /*!< Ignore the receive data. */
|
||||
} spi_xfer_option_t;
|
||||
|
||||
/*! @brief SPI data shifter direction options.*/
|
||||
typedef enum _spi_shift_direction
|
||||
{
|
||||
kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */
|
||||
kSPI_LsbFirst = 1U, /*!< Data transfers start with least significant bit. */
|
||||
} spi_shift_direction_t;
|
||||
|
||||
/*! @brief SPI clock polarity configuration.*/
|
||||
typedef enum _spi_clock_polarity
|
||||
{
|
||||
kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
|
||||
kSPI_ClockPolarityActiveLow = 0x1U, /*!< Active-low SPI clock (idles high). */
|
||||
} spi_clock_polarity_t;
|
||||
|
||||
/*! @brief SPI clock phase configuration.*/
|
||||
typedef enum _spi_clock_phase
|
||||
{
|
||||
kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first
|
||||
* cycle of a data transfer. */
|
||||
kSPI_ClockPhaseSecondEdge = 0x1U, /*!< First edge on SCK occurs at the start of the
|
||||
* first cycle of a data transfer. */
|
||||
} spi_clock_phase_t;
|
||||
|
||||
/*! @brief SPI FIFO driection. */
|
||||
typedef enum _spi_fifo_direction
|
||||
{
|
||||
kSPI_FifoTx = 1U, /*!< FIFO direction for transmit. */
|
||||
kSPI_FifoRx = 2U, /*!< FIFO direction for receive. */
|
||||
} spi_fifo_direction_t;
|
||||
|
||||
/*! @brief Transfer data width */
|
||||
typedef enum _spi_data_width
|
||||
{
|
||||
kSPI_Data1Bits = 0, /*!< 1 bits data width,when LEN = 0, the underrun status is not meaningful. */
|
||||
kSPI_Data2Bits = 1, /*!< 2 bits data width */
|
||||
kSPI_Data3Bits = 2, /*!< 3 bits data width */
|
||||
kSPI_Data4Bits = 3, /*!< 4 bits data width */
|
||||
kSPI_Data5Bits = 4, /*!< 5 bits data width */
|
||||
kSPI_Data6Bits = 5, /*!< 6 bits data width */
|
||||
kSPI_Data7Bits = 6, /*!< 7 bits data width */
|
||||
kSPI_Data8Bits = 7, /*!< 8 bits data width */
|
||||
kSPI_Data9Bits = 8, /*!< 9 bits data width */
|
||||
kSPI_Data10Bits = 9, /*!< 10 bits data width */
|
||||
kSPI_Data11Bits = 10, /*!< 11 bits data width */
|
||||
kSPI_Data12Bits = 11, /*!< 12 bits data width */
|
||||
kSPI_Data13Bits = 12, /*!< 13 bits data width */
|
||||
kSPI_Data14Bits = 13, /*!< 14 bits data width */
|
||||
kSPI_Data15Bits = 14, /*!< 15 bits data width */
|
||||
kSPI_Data16Bits = 15, /*!< 16 bits data width */
|
||||
} spi_data_width_t;
|
||||
|
||||
/*! @brief Slave select */
|
||||
typedef enum _spi_ssel
|
||||
{
|
||||
kSPI_Ssel0 = 0, /*!< Slave select 0 */
|
||||
kSPI_Ssel1 = 1, /*!< Slave select 1 */
|
||||
kSPI_Ssel2 = 2, /*!< Slave select 2 */
|
||||
kSPI_Ssel3 = 3, /*!< Slave select 3 */
|
||||
} spi_ssel_t;
|
||||
|
||||
/*! @brief ssel polarity */
|
||||
typedef enum _spi_spol
|
||||
{
|
||||
kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1),
|
||||
kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1),
|
||||
kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1),
|
||||
kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1),
|
||||
kSPI_SpolActiveAllHigh =
|
||||
(kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh),
|
||||
kSPI_SpolActiveAllLow = 0,
|
||||
} spi_spol_t;
|
||||
|
||||
/*! @brief SPI fifo user configure structure.*/
|
||||
typedef struct _spi_fifo_config
|
||||
{
|
||||
bool enableTxFifo; /*!< Enable transmit FIFO */
|
||||
bool enableRxFifo; /*!< Enable receive FIFO */
|
||||
uint8_t txFifoSize; /*!< Configure txFIFO size */
|
||||
uint8_t rxFifoSize; /*!< Configure rxFIFO size */
|
||||
uint8_t txFifoThreshold; /*!< txFIFO threshold */
|
||||
uint8_t rxFifoThreshold; /*!< rxFIFO threshold */
|
||||
} spi_fifo_config_t;
|
||||
|
||||
/*! @brief SPI delay time configure structure.*/
|
||||
typedef struct _spi_delay_config
|
||||
{
|
||||
uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */
|
||||
uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */
|
||||
uint8_t frameDelay; /*!< Delay between frame to frame. */
|
||||
uint8_t transferDelay; /*!< Delay between transfer to transfer. */
|
||||
} spi_delay_config_t;
|
||||
|
||||
/*! @brief SPI master user configure structure.*/
|
||||
typedef struct _spi_master_config
|
||||
{
|
||||
bool enableLoopback; /*!< Enable loopback for test purpose */
|
||||
bool enableMaster; /*!< Enable SPI at initialization time */
|
||||
spi_clock_polarity_t polarity; /*!< Clock polarity */
|
||||
spi_clock_phase_t phase; /*!< Clock phase */
|
||||
spi_shift_direction_t direction; /*!< MSB or LSB */
|
||||
uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */
|
||||
spi_data_width_t dataWidth; /*!< Width of the data */
|
||||
spi_ssel_t sselNum; /*!< Slave select number */
|
||||
spi_spol_t sselPol; /*!< Configure active CS polarity */
|
||||
spi_fifo_config_t fifoConfig; /*!< Configure for fifo. */
|
||||
spi_delay_config_t delayConfig; /*!< Configure for delay time. */
|
||||
} spi_master_config_t;
|
||||
|
||||
/*! @brief SPI slave user configure structure.*/
|
||||
typedef struct _spi_slave_config
|
||||
{
|
||||
bool enableSlave; /*!< Enable SPI at initialization time */
|
||||
spi_clock_polarity_t polarity; /*!< Clock polarity */
|
||||
spi_clock_phase_t phase; /*!< Clock phase */
|
||||
spi_shift_direction_t direction; /*!< MSB or LSB */
|
||||
spi_data_width_t dataWidth; /*!< Width of the data */
|
||||
spi_spol_t sselPol; /*!< Configure active CS polarity */
|
||||
spi_fifo_config_t fifoConfig; /*!< Configure for fifo. */
|
||||
} spi_slave_config_t;
|
||||
|
||||
/*! @brief SPI transfer status.*/
|
||||
enum _spi_status
|
||||
{
|
||||
kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */
|
||||
kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */
|
||||
kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */
|
||||
kStatus_SPI_BaudrateNotSupport =
|
||||
MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */
|
||||
};
|
||||
|
||||
/*! @brief SPI interrupt sources.*/
|
||||
enum _spi_interrupt_enable
|
||||
{
|
||||
kSPI_RxReadyInterruptEnable = SPI_INTENSET_RXRDYEN_MASK, /*!< Rx ready interrupt */
|
||||
kSPI_TxReadyInterruptEnable = SPI_INTENSET_TXRDYEN_MASK, /*!< Tx ready interrupt */
|
||||
kSPI_RxOverrunInterruptEnable = SPI_INTENSET_RXOVEN_MASK, /*!< Rx overrun interrupt */
|
||||
kSPI_TxUnderrunInterruptEnable = SPI_INTENSET_TXUREN_MASK, /*!< Tx underrun interrupt */
|
||||
kSPI_SlaveSelectAssertInterruptEnable = SPI_INTENSET_SSAEN_MASK, /*!< Slave select assert interrupt */
|
||||
kSPI_SlaveSelectDeassertInterruptEnable = SPI_INTENSET_SSDEN_MASK, /*!< Slave select deassert interrupt */
|
||||
kSPI_MasterIdleInterruptEnable = SPI_INTENSET_MSTIDLEEN_MASK, /*!< Master idle interrupt */
|
||||
kSPI_AllInterruptEnable =
|
||||
(SPI_INTENSET_RXRDYEN_MASK | SPI_INTENSET_TXRDYEN_MASK | SPI_INTENSET_RXOVEN_MASK | SPI_INTENSET_TXUREN_MASK |
|
||||
SPI_INTENSET_SSAEN_MASK | SPI_INTENSET_SSDEN_MASK | SPI_INTENSET_MSTIDLEEN_MASK)
|
||||
};
|
||||
|
||||
/*! @brief SPI FIFO interrupt sources.*/
|
||||
enum _spi_fifo_interrupt_enable
|
||||
{
|
||||
kSPI_RxFifoThresholdInterruptEnable =
|
||||
VFIFO_SPI_CTLSETSPI_RXTHINTEN_MASK, /*!< Rx FIFO reach the threshold interrupt */
|
||||
kSPI_TxFifoThresholdInterruptEnable =
|
||||
VFIFO_SPI_CTLSETSPI_TXTHINTEN_MASK, /*!< Tx FIFO reach the threshold interrupt */
|
||||
kSPI_RxFifoTimeoutInterruptEnable = VFIFO_SPI_CTLSETSPI_RXTIMEOUTINTEN_MASK, /*!< Rx FIfo timeout interrupt */
|
||||
kSPI_AllFifoInterruptEnable = (VFIFO_SPI_CTLSETSPI_RXTHINTEN_MASK | VFIFO_SPI_CTLSETSPI_TXTHINTEN_MASK |
|
||||
VFIFO_SPI_CTLSETSPI_RXTIMEOUTINTEN_MASK)
|
||||
};
|
||||
|
||||
/*! @brief SPI status flags.*/
|
||||
enum _spi_status_flags
|
||||
{
|
||||
kSPI_RxReadyFlag = SPI_STAT_RXRDY_MASK, /*!< Receive ready flag. */
|
||||
kSPI_TxReadyFlag = SPI_STAT_TXRDY_MASK, /*!< Transmit ready flag. */
|
||||
kSPI_RxOverrunFlag = SPI_STAT_RXOV_MASK, /*!< Receive overrun flag. */
|
||||
kSPI_TxUnderrunFlag = SPI_STAT_TXUR_MASK, /*!< Transmit underrun flag. */
|
||||
kSPI_SlaveSelectAssertFlag = SPI_STAT_SSA_MASK, /*!< Slave select assert flag. */
|
||||
kSPI_SlaveSelectDeassertFlag = SPI_STAT_SSD_MASK, /*!< slave select deassert flag. */
|
||||
kSPI_StallFlag = SPI_STAT_STALLED_MASK, /*!< Stall flag. */
|
||||
kSPI_EndTransferFlag = SPI_STAT_ENDTRANSFER_MASK, /*!< End transfer bit. */
|
||||
kSPI_MasterIdleFlag = SPI_STAT_MSTIDLE_MASK, /*!< Master in idle status flag. */
|
||||
};
|
||||
|
||||
/*! @brief SPI FIFO status flags.*/
|
||||
enum _spi_fifo_status_flags
|
||||
{
|
||||
kSPI_RxFifoThresholdFlag = (VFIFO_SPI_STATSPI_RXTH_MASK), /*!< Receive FIFO threshold reached flag. */
|
||||
kSPI_TxFifoThresholdFlag = (VFIFO_SPI_STATSPI_TXTH_MASK), /*!< Transmit FIFO threshold reached flag. */
|
||||
kSPI_RxFifoTimeOutFlag = (VFIFO_SPI_STATSPI_RXTIMEOUT_MASK), /*!< Receive time out flag. */
|
||||
kSPI_FifoBusErrorFlag = (VFIFO_SPI_STATSPI_BUSERR_MASK), /*!< FIFO bus error flag. */
|
||||
kSPI_RxFifoEmptyFlag = (VFIFO_SPI_STATSPI_RXEMPTY_MASK), /*!< Receive fifo buffer empty flag. */
|
||||
kSPI_TxFifoEmptyFlag = (VFIFO_SPI_STATSPI_TXEMPTY_MASK), /*!< transmit fifo buffer empty flag. */
|
||||
};
|
||||
|
||||
/*! @brief SPI transfer structure */
|
||||
typedef struct _spi_transfer
|
||||
{
|
||||
uint8_t *txData; /*!< Send buffer */
|
||||
uint8_t *rxData; /*!< Receive buffer */
|
||||
uint32_t configFlags; /*!< Additional option to control transfer */
|
||||
size_t dataSize; /*!< Transfer bytes */
|
||||
} spi_transfer_t;
|
||||
|
||||
/*! @brief SPI half-duplex(master only) transfer structure */
|
||||
typedef struct _spi_half_duplex_transfer
|
||||
{
|
||||
uint8_t *txData; /*!< Send buffer */
|
||||
uint8_t *rxData; /*!< Receive buffer */
|
||||
size_t txDataSize; /*!< Transfer bytes for transmit */
|
||||
size_t rxDataSize; /*!< Transfer bytes */
|
||||
uint32_t configFlags; /*!< Transfer configuration flags; set from _dspi_transfer_config_flag_for_master. */
|
||||
bool isPcsAssertInTransfer; /*!< If Pcs pin keep assert between transmit and receive. true for assert and false for
|
||||
deassert. */
|
||||
bool isTransmitFirst; /*!< True for transmit first and false for receive first. */
|
||||
} spi_half_duplex_transfer_t;
|
||||
|
||||
/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */
|
||||
typedef struct _spi_config
|
||||
{
|
||||
spi_data_width_t dataWidth;
|
||||
spi_ssel_t sselNum;
|
||||
} spi_config_t;
|
||||
|
||||
/*! @brief Master handle type */
|
||||
typedef struct _spi_master_handle spi_master_handle_t;
|
||||
|
||||
/*! @brief Slave handle type */
|
||||
typedef spi_master_handle_t spi_slave_handle_t;
|
||||
|
||||
/*! @brief SPI master callback for finished transmit */
|
||||
typedef void (*spi_master_callback_t)(SPI_Type *base, spi_master_handle_t *handle, status_t status, void *userData);
|
||||
|
||||
/*! @brief SPI slave callback for finished transmit */
|
||||
typedef void (*spi_slave_callback_t)(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData);
|
||||
|
||||
/*! @brief SPI transfer handle structure */
|
||||
struct _spi_master_handle
|
||||
{
|
||||
uint8_t *volatile txData; /*!< Transfer buffer */
|
||||
uint8_t *volatile rxData; /*!< Receive buffer */
|
||||
volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */
|
||||
volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */
|
||||
size_t totalByteCount; /*!< A number of transfer bytes */
|
||||
volatile uint32_t state; /*!< SPI internal state */
|
||||
spi_master_callback_t callback; /*!< SPI callback */
|
||||
void *userData; /*!< Callback parameter */
|
||||
uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */
|
||||
uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */
|
||||
uint32_t configFlags; /*!< Additional option to control transfer */
|
||||
bool isTxFifoEnabled; /*!< Is transmit FIFO enabled. */
|
||||
bool isRxFifoEnabled; /*!< Is receive FIFO enabled. */
|
||||
uint8_t txFifoThreshold; /*!< txFIFO threshold */
|
||||
uint8_t rxFifoThreshold; /*!< rxFIFO threshold */
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
/*! @brief Returns instance number for SPI peripheral base address. */
|
||||
uint32_t SPI_GetInstance(SPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Sets the SPI master configuration structure to default values.
|
||||
*
|
||||
* The purpose of this API is to get the configuration structure initialized for use in SPI_MasterInit().
|
||||
* User may use the initialized structure unchanged in SPI_MasterInit(), or modify
|
||||
* some fields of the structure before calling SPI_MasterInit(). After calling this API,
|
||||
* the master is ready to transfer.
|
||||
* Example:
|
||||
@code
|
||||
spi_master_config_t config;
|
||||
SPI_MasterGetDefaultConfig(&config);
|
||||
@endcode
|
||||
*
|
||||
* @param config pointer to master config structure
|
||||
*/
|
||||
void SPI_MasterGetDefaultConfig(spi_master_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the SPI with master configuration.
|
||||
*
|
||||
* The configuration structure can be filled by user from scratch, or be set with default
|
||||
* values by SPI_MasterGetDefaultConfig(). After calling this API, the slave is ready to transfer.
|
||||
* Example
|
||||
@code
|
||||
spi_master_config_t config = {
|
||||
.baudRate_Bps = 500000,
|
||||
...
|
||||
};
|
||||
SPI_MasterInit(SPI0, &config);
|
||||
@endcode
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param config pointer to master configuration structure
|
||||
* @param srcClock_Hz Source clock frequency.
|
||||
*/
|
||||
status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Sets the SPI slave configuration structure to default values.
|
||||
*
|
||||
* The purpose of this API is to get the configuration structure initialized for use in SPI_SlaveInit().
|
||||
* Modify some fields of the structure before calling SPI_SlaveInit().
|
||||
* Example:
|
||||
@code
|
||||
spi_slave_config_t config;
|
||||
SPI_SlaveGetDefaultConfig(&config);
|
||||
@endcode
|
||||
*
|
||||
* @param config pointer to slave configuration structure
|
||||
*/
|
||||
void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the SPI with slave configuration.
|
||||
*
|
||||
* The configuration structure can be filled by user from scratch or be set with
|
||||
* default values by SPI_SlaveGetDefaultConfig().
|
||||
* After calling this API, the slave is ready to transfer.
|
||||
* Example
|
||||
@code
|
||||
spi_slave_config_t config = {
|
||||
.polarity = kSPI_ClockPolarityActiveHigh;
|
||||
.phase = kSPI_ClockPhaseFirstEdge;
|
||||
.direction = kSPI_MsbFirst;
|
||||
...
|
||||
};
|
||||
SPI_SlaveInit(SPI0, &config);
|
||||
@endcode
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param config pointer to slave configuration structure
|
||||
*/
|
||||
status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief De-initializes the SPI.
|
||||
*
|
||||
* Calling this API resets the SPI module, gates the SPI clock.
|
||||
* Disable the fifo if enabled.
|
||||
* The SPI module can't work unless calling the SPI_MasterInit/SPI_SlaveInit to initialize module.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
*/
|
||||
void SPI_Deinit(SPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Enable or disable the SPI Master or Slave
|
||||
* @param base SPI base pointer
|
||||
* @param enable or disable ( true = enable, false = disable)
|
||||
*/
|
||||
static inline void SPI_Enable(SPI_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
base->CFG |= SPI_CFG_ENABLE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CFG &= ~SPI_CFG_ENABLE_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* @name Status
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Gets the status flag.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @return SPI Status, use status flag to AND @ref _spi_status_flags could get the related status.
|
||||
*/
|
||||
static inline uint32_t SPI_GetStatusFlags(SPI_Type *base)
|
||||
{
|
||||
assert(NULL != base);
|
||||
return base->STAT;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the FIFO status flag for SPI transfer.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @return SPI Status, use status flag to AND @ref _spi_fifo_status_flags could get the related status.
|
||||
*/
|
||||
uint32_t SPI_GetFifoStatusFlags(SPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Clear the FIFO status flag for SPI transfer.
|
||||
* Only kSPI_RxFifoTimeOutFlag and kSPI_FifoBusErrorFlag can be cleared.
|
||||
* @param base SPI base pointer
|
||||
* @param mask use status flag to AND @ref _spi_status_flags could get the related status.
|
||||
*/
|
||||
void SPI_ClearFifoStatusFlags(SPI_Type *base, uint32_t mask);
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* @name Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the interrupt for the SPI.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param irqs SPI interrupt source. The parameter can be any combination of the following values:
|
||||
* @arg kSPI_RxReadyInterruptEnable
|
||||
* @arg kSPI_TxReadyInterruptEnable
|
||||
*/
|
||||
static inline void SPI_EnableInterrupts(SPI_Type *base, uint32_t irqs)
|
||||
{
|
||||
assert(NULL != base);
|
||||
base->INTENSET = irqs;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the interrupt for the SPI.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param irqs SPI interrupt source. The parameter can be any combination of the following values:
|
||||
* @arg kSPI_RxReadyInterruptEnable
|
||||
* @arg kSPI_TxReadyInterruptEnable
|
||||
*/
|
||||
static inline void SPI_DisableInterrupts(SPI_Type *base, uint32_t irqs)
|
||||
{
|
||||
assert(NULL != base);
|
||||
base->INTENCLR = irqs;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables the FIFO interrupt for the SPI.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param irqs SPI interrupt source. The parameter can be any combination of the following values:
|
||||
* @arg kSPI_RxFifoThresholdInterruptEnable
|
||||
* @arg kSPI_TxFifoThresholdInterruptEnable
|
||||
*/
|
||||
void SPI_EnableFifoInterrupts(SPI_Type *base, uint32_t irqs);
|
||||
|
||||
/*!
|
||||
* @brief Disables the FIFO interrupt for the SPI.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param irqs SPI interrupt source. The parameter can be any combination of the following values:
|
||||
* @arg kSPI_RxFifoThresholdInterruptEnable
|
||||
* @arg kSPI_TxFifoThresholdInterruptEnable
|
||||
*/
|
||||
void SPI_DisableFifoInterrupts(SPI_Type *base, uint32_t irqs);
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* @name Bus Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Returns whether the SPI module is in master mode.
|
||||
*
|
||||
* @param base SPI peripheral address.
|
||||
* @return Returns true if the module is in master mode or false if the module is in slave mode.
|
||||
*/
|
||||
static inline bool SPI_IsMaster(SPI_Type *base)
|
||||
{
|
||||
return (bool)(((base->CFG) & SPI_CFG_MASTER_MASK) >> SPI_CFG_MASTER_SHIFT);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Returns the configurations.
|
||||
*
|
||||
* @param base SPI peripheral address.
|
||||
* @return return configurations which contain datawidth and SSEL numbers.
|
||||
* return data type is a pointer of spi_config_t.
|
||||
*/
|
||||
void *SPI_GetConfig(SPI_Type *base);
|
||||
/*!
|
||||
* @brief Sets the baud rate for SPI transfer. This is only used in master.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param baudrate_Bps baud rate needed in Hz.
|
||||
* @param srcClock_Hz SPI source clock frequency in Hz.
|
||||
*/
|
||||
status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Writes a data into the SPI data register.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param data needs to be write.
|
||||
* @param configFlags transfer configuration options @ref spi_xfer_option_t
|
||||
*/
|
||||
void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags);
|
||||
|
||||
/*!
|
||||
* @brief Gets a data from the SPI data register.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @return Data in the register.
|
||||
*/
|
||||
uint32_t SPI_ReadData(SPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Set delay time for transfer.
|
||||
* the delay uint is SPI clock time, maximum value is 0xF.
|
||||
* @param base SPI base pointer
|
||||
* @param config configuration for delay option @ref spi_delay_config_t.
|
||||
*/
|
||||
void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Set up the dummy data.
|
||||
*
|
||||
* @param base SPI peripheral address.
|
||||
* @param dummyData Data to be transferred when tx buffer is NULL.
|
||||
*/
|
||||
void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
|
||||
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* @name FIFO Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enable FIFO for SPI.
|
||||
*
|
||||
* This function will enable the FIFO for SPI according to pointer of the configure struct.
|
||||
* Note: If this API is called, please reset the baudrate to adapt your demand after this API
|
||||
* was called.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param config pointer to FIFO configuration structure.
|
||||
*/
|
||||
void SPI_EnableFifo(SPI_Type *base, const spi_fifo_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Disable FIFO for SPI.
|
||||
*
|
||||
* This function will Disable the FIFO for SPI transfer.
|
||||
* disable interrupts, clear status flags, disable the TX/RX FIFO, set fifo size to zero.
|
||||
* But will not disable the system FIFO, because other instance like USART may using the FIFO.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param config pointer to FIFO configuration structure.
|
||||
*/
|
||||
void SPI_DisableFifo(SPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Is TX FIFO enabled.
|
||||
*
|
||||
* This function will return status if the transmit fifo is enabled. true for enabled and false for not enabled.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @return true for enabled and false for not enabled.
|
||||
*/
|
||||
bool SPI_IsTxFifoEnabled(SPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Is RX FIFO enabled.
|
||||
*
|
||||
* This function will return status if the receive fifo is enabled. true for enabled and false for not enabled.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @return true for enabled and false for not enabled.
|
||||
*/
|
||||
bool SPI_IsRxFifoEnabled(SPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Flush the FIFO buffer.
|
||||
*
|
||||
* This function will Flush tHE fifo buffer.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param direction the fifo direction need to flushed, Tx FIFO or Rx FIFO.
|
||||
*/
|
||||
void SPI_FifoFlush(SPI_Type *base, uint32_t direction);
|
||||
/*! @} */
|
||||
|
||||
/*!
|
||||
* @name Transactional
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the SPI master handle.
|
||||
*
|
||||
* This function initializes the SPI master handle which can be used for other SPI master transactional APIs. Usually,
|
||||
* for a specified SPI instance, call this API once to get the initialized handle.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle SPI handle pointer.
|
||||
* @param callback Callback function.
|
||||
* @param userData User data.
|
||||
*/
|
||||
status_t SPI_MasterTransferCreateHandle(SPI_Type *base,
|
||||
spi_master_handle_t *handle,
|
||||
spi_master_callback_t callback,
|
||||
void *userData);
|
||||
|
||||
/*!
|
||||
* @brief Transfers a block of data using a polling method.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param xfer pointer to spi_xfer_config_t structure
|
||||
* @retval kStatus_Success Successfully start a transfer.
|
||||
* @retval kStatus_InvalidArgument Input argument is invalid.
|
||||
*/
|
||||
status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Performs a non-blocking SPI interrupt transfer.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle pointer to spi_master_handle_t structure which stores the transfer state
|
||||
* @param xfer pointer to spi_xfer_config_t structure
|
||||
* @retval kStatus_Success Successfully start a transfer.
|
||||
* @retval kStatus_InvalidArgument Input argument is invalid.
|
||||
* @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
|
||||
*/
|
||||
status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Transfers a block of data using a polling method.
|
||||
*
|
||||
* This function will do a half-duplex transfer for SPI master, This is a blocking function,
|
||||
* which does not retuen until all transfer have been completed. And data transfer will be half-duplex,
|
||||
* users can set transmit first or receive first.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param xfer pointer to spi_half_duplex_transfer_t structure
|
||||
* @return status of status_t.
|
||||
*/
|
||||
status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Performs a non-blocking SPI interrupt transfer.
|
||||
*
|
||||
* This function using polling way to do the first half transimission and using interrupts to
|
||||
* do the srcond half transimission, the transfer mechanism is half-duplex.
|
||||
* When do the second half transimission, code will return right away. When all data is transferred,
|
||||
* the callback function is called.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle pointer to spi_master_handle_t structure which stores the transfer state
|
||||
* @param xfer pointer to spi_half_duplex_transfer_t structure
|
||||
* @return status of status_t.
|
||||
*/
|
||||
status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base,
|
||||
spi_master_handle_t *handle,
|
||||
spi_half_duplex_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Gets the master transfer count.
|
||||
*
|
||||
* This function gets the master transfer count.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
|
||||
* @param count The number of bytes transferred by using the non-blocking transaction.
|
||||
* @return status of status_t.
|
||||
*/
|
||||
status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count);
|
||||
|
||||
/*!
|
||||
* @brief SPI master aborts a transfer using an interrupt.
|
||||
*
|
||||
* This function aborts a transfer using an interrupt.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
|
||||
*/
|
||||
void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Interrupts the handler for the SPI.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle pointer to spi_master_handle_t structure which stores the transfer state.
|
||||
*/
|
||||
void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the SPI slave handle.
|
||||
*
|
||||
* This function initializes the SPI slave handle which can be used for other SPI slave transactional APIs. Usually,
|
||||
* for a specified SPI instance, call this API once to get the initialized handle.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle SPI handle pointer.
|
||||
* @param callback Callback function.
|
||||
* @param userData User data.
|
||||
*/
|
||||
status_t SPI_SlaveTransferCreateHandle(SPI_Type *base,
|
||||
spi_slave_handle_t *handle,
|
||||
spi_slave_callback_t callback,
|
||||
void *userData);
|
||||
|
||||
/*!
|
||||
* @brief Performs a non-blocking SPI slave interrupt transfer.
|
||||
*
|
||||
* @note The API returns immediately after the transfer initialization is finished.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle pointer to spi_master_handle_t structure which stores the transfer state
|
||||
* @param xfer pointer to spi_xfer_config_t structure
|
||||
* @retval kStatus_Success Successfully start a transfer.
|
||||
* @retval kStatus_InvalidArgument Input argument is invalid.
|
||||
* @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
|
||||
*/
|
||||
status_t SPI_SlaveTransferNonBlocking(SPI_Type *base, spi_slave_handle_t *handle, spi_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Gets the slave transfer count.
|
||||
*
|
||||
* This function gets the slave transfer count.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle Pointer to the spi_master_handle_t structure which stores the transfer state.
|
||||
* @param count The number of bytes transferred by using the non-blocking transaction.
|
||||
* @return status of status_t.
|
||||
*/
|
||||
static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
|
||||
{
|
||||
return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief SPI slave aborts a transfer using an interrupt.
|
||||
*
|
||||
* This function aborts a transfer using an interrupt.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle Pointer to the spi_slave_handle_t structure which stores the transfer state.
|
||||
*/
|
||||
static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
|
||||
{
|
||||
SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Interrupts a handler for the SPI slave.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle pointer to spi_slave_handle_t structure which stores the transfer state
|
||||
*/
|
||||
void SPI_SlaveTransferHandleIRQ(SPI_Type *base, spi_slave_handle_t *handle);
|
||||
|
||||
/*! @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_SPI_H_*/
|
||||
615
Living_SDK/platform/mcu/lpc54102/drivers/fsl_spi_dma.c
Normal file
615
Living_SDK/platform/mcu/lpc54102/drivers/fsl_spi_dma.c
Normal file
|
|
@ -0,0 +1,615 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NXP Semiconductors, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_spi_dma.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitons
|
||||
******************************************************************************/
|
||||
/*<! Structure definition for spi_dma_private_handle_t. The structure is private. */
|
||||
typedef struct _spi_dma_private_handle
|
||||
{
|
||||
SPI_Type *base;
|
||||
spi_dma_handle_t *handle;
|
||||
} spi_dma_private_handle_t;
|
||||
|
||||
/*! @brief SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
|
||||
enum _spi_dma_states_t
|
||||
{
|
||||
kSPI_Idle = 0x0, /*!< SPI is idle state */
|
||||
kSPI_Busy /*!< SPI is busy tranferring data. */
|
||||
};
|
||||
|
||||
typedef struct _spi_dma_txdummy
|
||||
{
|
||||
uint32_t lastWord;
|
||||
uint32_t word;
|
||||
} spi_dma_txdummy_t;
|
||||
|
||||
/*<! Private handle only used for internally. */
|
||||
static spi_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_SPI_COUNT];
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief SPI private function to return SPI configuration
|
||||
*
|
||||
* @param base SPI base address.
|
||||
*/
|
||||
void *SPI_GetConfig(SPI_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief DMA callback function for SPI send transfer.
|
||||
*
|
||||
* @param handle DMA handle pointer.
|
||||
* @param userData User data for DMA callback function.
|
||||
*/
|
||||
static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
|
||||
|
||||
/*!
|
||||
* @brief DMA callback function for SPI receive transfer.
|
||||
*
|
||||
* @param handle DMA handle pointer.
|
||||
* @param userData User data for DMA callback function.
|
||||
*/
|
||||
static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
#if defined(__ICCARM__)
|
||||
#pragma data_alignment = 4
|
||||
static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
|
||||
#elif defined(__CC_ARM)
|
||||
__attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
|
||||
#elif defined(__GNUC__)
|
||||
__attribute__((aligned(4))) static spi_dma_txdummy_t s_txDummy[FSL_FEATURE_SOC_SPI_COUNT] = {0};
|
||||
#endif
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma data_alignment = 4
|
||||
static uint16_t s_rxDummy;
|
||||
static uint32_t s_txLastData[FSL_FEATURE_SOC_SPI_COUNT];
|
||||
#elif defined(__CC_ARM)
|
||||
__attribute__((aligned(4))) static uint16_t s_rxDummy;
|
||||
__attribute__((aligned(4))) static uint32_t s_txLastData[FSL_FEATURE_SOC_SPI_COUNT];
|
||||
#elif defined(__GNUC__)
|
||||
__attribute__((aligned(4))) static uint16_t s_rxDummy;
|
||||
__attribute__((aligned(4))) static uint32_t s_txLastData[FSL_FEATURE_SOC_SPI_COUNT];
|
||||
#endif
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
#pragma data_alignment = 16
|
||||
static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
|
||||
#elif defined(__CC_ARM)
|
||||
__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
|
||||
#elif defined(__GNUC__)
|
||||
__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
|
||||
#endif
|
||||
|
||||
/*! @brief Global variable for dummy data value setting. */
|
||||
extern volatile uint8_t s_dummyData[];
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
static void XferToFifoWR(spi_transfer_t *xfer, uint32_t *fifowr)
|
||||
{
|
||||
*fifowr |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
|
||||
*fifowr |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
|
||||
*fifowr |= (xfer->configFlags & (uint32_t)kSPI_ReceiveIgnore) ? (uint32_t)kSPI_ReceiveIgnore : 0;
|
||||
}
|
||||
|
||||
static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr)
|
||||
{
|
||||
*fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERT_SSELNUM(config->sselNum)));
|
||||
/* set width of data - range asserted at entry */
|
||||
*fifowr |= SPI_TXDATCTL_LEN(config->dataWidth);
|
||||
}
|
||||
|
||||
static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p)
|
||||
{
|
||||
uint32_t instance = SPI_GetInstance(base);
|
||||
dummy->word = ((uint32_t)s_dummyData[instance] << 8U) | s_dummyData[instance];
|
||||
XferToFifoWR(xfer, &dummy->word);
|
||||
SpiConfigToFifoWR(spi_config_p, &dummy->word);
|
||||
if ((xfer->configFlags & kSPI_FrameAssert) &&
|
||||
((spi_config_p->dataWidth > 7U) ? (xfer->dataSize > 2) : (xfer->dataSize > 1)))
|
||||
{
|
||||
dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U) | s_dummyData[instance];
|
||||
XferToFifoWR(xfer, &dummy->lastWord);
|
||||
SpiConfigToFifoWR(spi_config_p, &dummy->lastWord);
|
||||
dummy->word &= (uint32_t)(~kSPI_FrameAssert);
|
||||
}
|
||||
}
|
||||
|
||||
status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
|
||||
spi_dma_handle_t *handle,
|
||||
spi_dma_callback_t callback,
|
||||
void *userData,
|
||||
dma_handle_t *txHandle,
|
||||
dma_handle_t *rxHandle)
|
||||
{
|
||||
int32_t instance = 0;
|
||||
|
||||
/* check 'base' */
|
||||
assert(!(NULL == base));
|
||||
if (NULL == base)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
/* check 'handle' */
|
||||
assert(!(NULL == handle));
|
||||
if (NULL == handle)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
instance = SPI_GetInstance(base);
|
||||
|
||||
memset(handle, 0, sizeof(*handle));
|
||||
/* Set spi base to handle */
|
||||
handle->txHandle = txHandle;
|
||||
handle->rxHandle = rxHandle;
|
||||
handle->callback = callback;
|
||||
handle->userData = userData;
|
||||
|
||||
/* Set SPI state to idle */
|
||||
handle->state = kSPI_Idle;
|
||||
|
||||
/* Set handle to global state */
|
||||
s_dmaPrivateHandle[instance].base = base;
|
||||
s_dmaPrivateHandle[instance].handle = handle;
|
||||
|
||||
/* Install callback for Tx dma channel */
|
||||
DMA_SetCallback(handle->txHandle, SPI_TxDMACallback, &s_dmaPrivateHandle[instance]);
|
||||
DMA_SetCallback(handle->rxHandle, SPI_RxDMACallback, &s_dmaPrivateHandle[instance]);
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
|
||||
{
|
||||
int32_t instance;
|
||||
status_t result = kStatus_Success;
|
||||
spi_config_t *spi_config_p;
|
||||
|
||||
assert(!((NULL == handle) || (NULL == xfer)));
|
||||
if ((NULL == handle) || (NULL == xfer))
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
/* byte size is zero. */
|
||||
assert(!(xfer->dataSize == 0));
|
||||
if (xfer->dataSize == 0)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
/* cannot get instance from base address */
|
||||
instance = SPI_GetInstance(base);
|
||||
assert(!(instance < 0));
|
||||
if (instance < 0)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
/* Check if the device is busy */
|
||||
if (handle->state == kSPI_Busy)
|
||||
{
|
||||
return kStatus_SPI_Busy;
|
||||
}
|
||||
else
|
||||
{
|
||||
uint32_t tmp;
|
||||
dma_transfer_config_t xferConfig = {0};
|
||||
spi_config_p = (spi_config_t *)SPI_GetConfig(base);
|
||||
|
||||
handle->state = kStatus_SPI_Busy;
|
||||
handle->transferSize = xfer->dataSize;
|
||||
|
||||
/* Receive */
|
||||
if (xfer->rxData)
|
||||
{
|
||||
if (SPI_IsRxFifoEnabled(base))
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, (void *)&VFIFO->SPI[instance].RXDATSPI, xfer->rxData,
|
||||
((spi_config_p->dataWidth > 7U) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
|
||||
xfer->dataSize, kDMA_PeripheralToMemory, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, (void *)&base->RXDAT, xfer->rxData,
|
||||
((spi_config_p->dataWidth > 7U) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
|
||||
xfer->dataSize, kDMA_PeripheralToMemory, NULL);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (SPI_IsRxFifoEnabled(base))
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, (void *)&VFIFO->SPI[instance].RXDATSPI, &s_rxDummy,
|
||||
((spi_config_p->dataWidth > 7U) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
|
||||
xfer->dataSize, kDMA_StaticToStatic, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, (void *)&base->RXDAT, &s_rxDummy,
|
||||
((spi_config_p->dataWidth > 7U) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
|
||||
xfer->dataSize, kDMA_StaticToStatic, NULL);
|
||||
}
|
||||
}
|
||||
DMA_SubmitTransfer(handle->rxHandle, &xferConfig);
|
||||
handle->rxInProgress = true;
|
||||
DMA_StartTransfer(handle->rxHandle);
|
||||
|
||||
/* Transmit */
|
||||
tmp = 0;
|
||||
XferToFifoWR(xfer, &tmp);
|
||||
SpiConfigToFifoWR(spi_config_p, &tmp);
|
||||
|
||||
if ((xfer->configFlags & kSPI_FrameAssert) &&
|
||||
((spi_config_p->dataWidth > 7U) ? (xfer->dataSize > 2) : (xfer->dataSize > 1)))
|
||||
{
|
||||
if (spi_config_p->dataWidth > 7U)
|
||||
{
|
||||
s_txLastData[instance] =
|
||||
tmp | ((uint32_t)(xfer->txData[xfer->dataSize - 1]) << 8U) | (xfer->txData[xfer->dataSize - 2]);
|
||||
}
|
||||
else
|
||||
{
|
||||
s_txLastData[instance] = tmp | (xfer->txData[xfer->dataSize - 1]);
|
||||
}
|
||||
|
||||
/* If not the last data, clear the end of transfer control bit. */
|
||||
tmp &= ~((uint32_t)(kSPI_FrameAssert));
|
||||
}
|
||||
|
||||
if (xfer->txData)
|
||||
{
|
||||
if (SPI_IsTxFifoEnabled(base))
|
||||
{
|
||||
if ((xfer->configFlags & kSPI_FrameAssert) &&
|
||||
((spi_config_p->dataWidth > 7U) ? (xfer->dataSize > 2) : (xfer->dataSize > 1)))
|
||||
{
|
||||
dma_xfercfg_t tmp_xfercfg = {0};
|
||||
tmp_xfercfg.valid = true;
|
||||
tmp_xfercfg.swtrig = true;
|
||||
tmp_xfercfg.intA = true;
|
||||
tmp_xfercfg.byteWidth = sizeof(uint32_t);
|
||||
tmp_xfercfg.srcInc = 0;
|
||||
tmp_xfercfg.dstInc = 0;
|
||||
tmp_xfercfg.transferCount = 1;
|
||||
/* create chained descriptor to transmit last word */
|
||||
DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastData[instance],
|
||||
(uint32_t *)&VFIFO->SPI[instance].TXDATSPI, NULL);
|
||||
if (spi_config_p->dataWidth > 7U)
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, (xfer->txData), (void *)&VFIFO->SPI[instance].TXDATSPI,
|
||||
sizeof(uint16_t), (xfer->dataSize - 2), kDMA_MemoryToPeripheral,
|
||||
&s_spi_descriptor_table[instance]);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&VFIFO->SPI[instance].TXDATSPI,
|
||||
sizeof(uint8_t), (xfer->dataSize - 1), kDMA_MemoryToPeripheral,
|
||||
&s_spi_descriptor_table[instance]);
|
||||
}
|
||||
|
||||
/* Disable interrupts for first descriptor to avoid calling callback twice */
|
||||
xferConfig.xfercfg.intA = false;
|
||||
xferConfig.xfercfg.intB = false;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (spi_config_p->dataWidth > 7U)
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, (xfer->txData), (void *)&VFIFO->SPI[instance].TXDATSPI,
|
||||
sizeof(uint16_t), (xfer->dataSize), kDMA_MemoryToPeripheral, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&VFIFO->SPI[instance].TXDATSPI,
|
||||
sizeof(uint8_t), (xfer->dataSize), kDMA_MemoryToPeripheral, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((xfer->configFlags & kSPI_FrameAssert) &&
|
||||
((spi_config_p->dataWidth > 7U) ? (xfer->dataSize > 2) : (xfer->dataSize > 1)))
|
||||
{
|
||||
dma_xfercfg_t tmp_xfercfg = {0};
|
||||
tmp_xfercfg.valid = true;
|
||||
tmp_xfercfg.swtrig = true;
|
||||
tmp_xfercfg.intA = true;
|
||||
tmp_xfercfg.byteWidth = sizeof(uint32_t);
|
||||
tmp_xfercfg.srcInc = 0;
|
||||
tmp_xfercfg.dstInc = 0;
|
||||
tmp_xfercfg.transferCount = 1;
|
||||
/* Create chained descriptor to transmit last word */
|
||||
DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastData[instance],
|
||||
(uint32_t *)&base->TXDATCTL, NULL);
|
||||
if (spi_config_p->dataWidth > 7U)
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->TXDAT, sizeof(uint16_t),
|
||||
(xfer->dataSize - 2), kDMA_MemoryToPeripheral,
|
||||
&s_spi_descriptor_table[instance]);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->TXDAT, sizeof(uint8_t),
|
||||
(xfer->dataSize - 1), kDMA_MemoryToPeripheral,
|
||||
&s_spi_descriptor_table[instance]);
|
||||
}
|
||||
/* disable interrupts for first descriptor to avoid calling callback twice */
|
||||
xferConfig.xfercfg.intA = false;
|
||||
xferConfig.xfercfg.intB = false;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (spi_config_p->dataWidth > 7U)
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->TXDAT, sizeof(uint16_t),
|
||||
(xfer->dataSize), kDMA_MemoryToPeripheral, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->TXDAT, sizeof(uint8_t),
|
||||
(xfer->dataSize), kDMA_MemoryToPeripheral, NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
|
||||
if (result != kStatus_Success)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Create chained descriptor to transmit dummy word. */
|
||||
SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p);
|
||||
|
||||
if ((xfer->configFlags & kSPI_FrameAssert) &&
|
||||
((spi_config_p->dataWidth > 7U) ? (xfer->dataSize > 2) : (xfer->dataSize > 1)))
|
||||
{
|
||||
dma_xfercfg_t tmp_xfercfg = {0};
|
||||
tmp_xfercfg.valid = true;
|
||||
tmp_xfercfg.swtrig = true;
|
||||
tmp_xfercfg.intA = true;
|
||||
tmp_xfercfg.byteWidth = sizeof(uint32_t);
|
||||
tmp_xfercfg.srcInc = 0;
|
||||
tmp_xfercfg.dstInc = 0;
|
||||
tmp_xfercfg.transferCount = 1;
|
||||
|
||||
if (SPI_IsTxFifoEnabled(base))
|
||||
{
|
||||
DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord,
|
||||
(uint32_t *)&VFIFO->SPI[instance].TXDATSPI, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord,
|
||||
(uint32_t *)&base->TXDATCTL, NULL);
|
||||
}
|
||||
|
||||
if (SPI_IsTxFifoEnabled(base))
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&VFIFO->SPI[instance].TXDATSPI,
|
||||
((spi_config_p->dataWidth > 7U) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
|
||||
((spi_config_p->dataWidth > 7U) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)),
|
||||
kDMA_StaticToStatic, &s_spi_descriptor_table[instance]);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->TXDATCTL,
|
||||
((spi_config_p->dataWidth > 7U) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
|
||||
((spi_config_p->dataWidth > 7U) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)),
|
||||
kDMA_StaticToStatic, &s_spi_descriptor_table[instance]);
|
||||
}
|
||||
/* Disable interrupts for first descriptor to avoid calling callback twice */
|
||||
xferConfig.xfercfg.intA = false;
|
||||
xferConfig.xfercfg.intB = false;
|
||||
result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
|
||||
if (result != kStatus_Success)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (SPI_IsTxFifoEnabled(base))
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&VFIFO->SPI[instance].TXDATSPI,
|
||||
((spi_config_p->dataWidth > 7U) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
|
||||
(xfer->dataSize), kDMA_StaticToStatic, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->TXDAT,
|
||||
((spi_config_p->dataWidth > 7U) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
|
||||
(xfer->dataSize), kDMA_StaticToStatic, NULL);
|
||||
}
|
||||
result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
|
||||
if (result != kStatus_Success)
|
||||
{
|
||||
return result;
|
||||
}
|
||||
}
|
||||
}
|
||||
handle->txInProgress = true;
|
||||
/* Setup the control information. */
|
||||
if (SPI_IsTxFifoEnabled(base))
|
||||
{
|
||||
*((uint16_t *)&(VFIFO->SPI[instance].TXDATSPI) + 1) = (tmp >> 16U);
|
||||
}
|
||||
else
|
||||
{
|
||||
base->TXCTL = tmp;
|
||||
}
|
||||
DMA_StartTransfer(handle->txHandle);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer)
|
||||
{
|
||||
assert(xfer);
|
||||
assert(handle);
|
||||
spi_transfer_t tempXfer = {0};
|
||||
status_t status;
|
||||
|
||||
if (xfer->isTransmitFirst)
|
||||
{
|
||||
tempXfer.txData = xfer->txData;
|
||||
tempXfer.rxData = NULL;
|
||||
tempXfer.dataSize = xfer->txDataSize;
|
||||
}
|
||||
else
|
||||
{
|
||||
tempXfer.txData = NULL;
|
||||
tempXfer.rxData = xfer->rxData;
|
||||
tempXfer.dataSize = xfer->rxDataSize;
|
||||
}
|
||||
/* If the pcs pin keep assert between transmit and receive. */
|
||||
if (xfer->isPcsAssertInTransfer)
|
||||
{
|
||||
tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert);
|
||||
}
|
||||
else
|
||||
{
|
||||
tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert;
|
||||
}
|
||||
|
||||
status = SPI_MasterTransferBlocking(base, &tempXfer);
|
||||
if (status != kStatus_Success)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
||||
if (xfer->isTransmitFirst)
|
||||
{
|
||||
tempXfer.txData = NULL;
|
||||
tempXfer.rxData = xfer->rxData;
|
||||
tempXfer.dataSize = xfer->rxDataSize;
|
||||
}
|
||||
else
|
||||
{
|
||||
tempXfer.txData = xfer->txData;
|
||||
tempXfer.rxData = NULL;
|
||||
tempXfer.dataSize = xfer->txDataSize;
|
||||
}
|
||||
tempXfer.configFlags = xfer->configFlags;
|
||||
|
||||
status = SPI_MasterTransferDMA(base, handle, &tempXfer);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
|
||||
{
|
||||
spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
|
||||
spi_dma_handle_t *spiHandle = privHandle->handle;
|
||||
SPI_Type *base = privHandle->base;
|
||||
|
||||
/* change the state */
|
||||
spiHandle->rxInProgress = false;
|
||||
|
||||
/* All finished, call the callback */
|
||||
if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
|
||||
{
|
||||
spiHandle->state = kSPI_Idle;
|
||||
if (spiHandle->callback)
|
||||
{
|
||||
(spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
|
||||
{
|
||||
spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
|
||||
spi_dma_handle_t *spiHandle = privHandle->handle;
|
||||
SPI_Type *base = privHandle->base;
|
||||
/* change the state */
|
||||
spiHandle->txInProgress = false;
|
||||
/* All finished, call the callback */
|
||||
if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false))
|
||||
{
|
||||
spiHandle->state = kSPI_Idle;
|
||||
if (spiHandle->callback)
|
||||
{
|
||||
(spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
|
||||
{
|
||||
assert(NULL != handle);
|
||||
|
||||
/* Stop tx transfer first */
|
||||
DMA_AbortTransfer(handle->txHandle);
|
||||
/* Then rx transfer */
|
||||
DMA_AbortTransfer(handle->rxHandle);
|
||||
|
||||
/* Set the handle state */
|
||||
handle->txInProgress = false;
|
||||
handle->rxInProgress = false;
|
||||
handle->state = kSPI_Idle;
|
||||
}
|
||||
|
||||
status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
|
||||
{
|
||||
assert(handle);
|
||||
|
||||
if (!count)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
/* Catch when there is not an active transfer. */
|
||||
if (handle->state != kSPI_Busy)
|
||||
{
|
||||
*count = 0;
|
||||
return kStatus_NoTransferInProgress;
|
||||
}
|
||||
|
||||
size_t bytes;
|
||||
|
||||
bytes = DMA_GetRemainingBytes(handle->rxHandle->base, handle->rxHandle->channel);
|
||||
|
||||
*count = handle->transferSize - bytes;
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
224
Living_SDK/platform/mcu/lpc54102/drivers/fsl_spi_dma.h
Normal file
224
Living_SDK/platform/mcu/lpc54102/drivers/fsl_spi_dma.h
Normal file
|
|
@ -0,0 +1,224 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NXP Semiconductors, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_SPI_DMA_H_
|
||||
#define _FSL_SPI_DMA_H_
|
||||
|
||||
#include "fsl_dma.h"
|
||||
#include "fsl_spi.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup spi_dma_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
typedef struct _spi_dma_handle spi_dma_handle_t;
|
||||
|
||||
/*! @brief SPI DMA callback called at the end of transfer. */
|
||||
typedef void (*spi_dma_callback_t)(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData);
|
||||
|
||||
/*! @brief SPI DMA transfer handle, users should not touch the content of the handle.*/
|
||||
struct _spi_dma_handle
|
||||
{
|
||||
volatile bool txInProgress; /*!< Send transfer finished */
|
||||
volatile bool rxInProgress; /*!< Receive transfer finished */
|
||||
dma_handle_t *txHandle; /*!< DMA handler for SPI send */
|
||||
dma_handle_t *rxHandle; /*!< DMA handler for SPI receive */
|
||||
uint8_t bytesPerFrame; /*!< Bytes in a frame for SPI tranfer */
|
||||
spi_dma_callback_t callback; /*!< Callback for SPI DMA transfer */
|
||||
void *userData; /*!< User Data for SPI DMA callback */
|
||||
uint32_t state; /*!< Internal state of SPI DMA transfer */
|
||||
size_t transferSize; /*!< Bytes need to be transfer */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* APIs
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @name DMA Transactional
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initialize the SPI master DMA handle.
|
||||
*
|
||||
* This function initializes the SPI master DMA handle which can be used for other SPI master transactional APIs.
|
||||
* Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle SPI handle pointer.
|
||||
* @param callback User callback function called at the end of a transfer.
|
||||
* @param userData User data for callback.
|
||||
* @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
|
||||
* @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
|
||||
*/
|
||||
status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
|
||||
spi_dma_handle_t *handle,
|
||||
spi_dma_callback_t callback,
|
||||
void *userData,
|
||||
dma_handle_t *txHandle,
|
||||
dma_handle_t *rxHandle);
|
||||
|
||||
/*!
|
||||
* @brief Perform a non-blocking SPI transfer using DMA.
|
||||
*
|
||||
* @note This interface returned immediately after transfer initiates, users should call
|
||||
* SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle SPI DMA handle pointer.
|
||||
* @param xfer Pointer to dma transfer structure.
|
||||
* @retval kStatus_Success Successfully start a transfer.
|
||||
* @retval kStatus_InvalidArgument Input argument is invalid.
|
||||
* @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
|
||||
*/
|
||||
status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Transfers a block of data using a DMA method.
|
||||
*
|
||||
* This function using polling way to do the first half transimission and using DMA way to
|
||||
* do the srcond half transimission, the transfer mechanism is half-duplex.
|
||||
* When do the second half transimission, code will return right away. When all data is transferred,
|
||||
* the callback function is called.
|
||||
*
|
||||
* @param base SPI base pointer
|
||||
* @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state.
|
||||
* @param transfer A pointer to the spi_half_duplex_transfer_t structure.
|
||||
* @return status of status_t.
|
||||
*/
|
||||
status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Initialize the SPI slave DMA handle.
|
||||
*
|
||||
* This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs.
|
||||
* Usually, for a specified SPI instance, user need only call this API once to get the initialized handle.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle SPI handle pointer.
|
||||
* @param callback User callback function called at the end of a transfer.
|
||||
* @param userData User data for callback.
|
||||
* @param txHandle DMA handle pointer for SPI Tx, the handle shall be static allocated by users.
|
||||
* @param rxHandle DMA handle pointer for SPI Rx, the handle shall be static allocated by users.
|
||||
*/
|
||||
static inline status_t SPI_SlaveTransferCreateHandleDMA(SPI_Type *base,
|
||||
spi_dma_handle_t *handle,
|
||||
spi_dma_callback_t callback,
|
||||
void *userData,
|
||||
dma_handle_t *txHandle,
|
||||
dma_handle_t *rxHandle)
|
||||
{
|
||||
return SPI_MasterTransferCreateHandleDMA(base, handle, callback, userData, txHandle, rxHandle);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Perform a non-blocking SPI transfer using DMA.
|
||||
*
|
||||
* @note This interface returned immediately after transfer initiates, users should call
|
||||
* SPI_GetTransferStatus to poll the transfer status to check whether SPI transfer finished.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle SPI DMA handle pointer.
|
||||
* @param xfer Pointer to dma transfer structure.
|
||||
* @retval kStatus_Success Successfully start a transfer.
|
||||
* @retval kStatus_InvalidArgument Input argument is invalid.
|
||||
* @retval kStatus_SPI_Busy SPI is not idle, is running another transfer.
|
||||
*/
|
||||
static inline status_t SPI_SlaveTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer)
|
||||
{
|
||||
return SPI_MasterTransferDMA(base, handle, xfer);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Abort a SPI transfer using DMA.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle SPI DMA handle pointer.
|
||||
*/
|
||||
void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Gets the master DMA transfer remaining bytes.
|
||||
*
|
||||
* This function gets the master DMA transfer remaining bytes.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state.
|
||||
* @param count A number of bytes transferred by the non-blocking transaction.
|
||||
* @return status of status_t.
|
||||
*/
|
||||
status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count);
|
||||
|
||||
/*!
|
||||
* @brief Abort a SPI transfer using DMA.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle SPI DMA handle pointer.
|
||||
*/
|
||||
static inline void SPI_SlaveTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle)
|
||||
{
|
||||
SPI_MasterTransferAbortDMA(base, handle);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the slave DMA transfer remaining bytes.
|
||||
*
|
||||
* This function gets the slave DMA transfer remaining bytes.
|
||||
*
|
||||
* @param base SPI peripheral base address.
|
||||
* @param handle A pointer to the spi_dma_handle_t structure which stores the transfer state.
|
||||
* @param count A number of bytes transferred by the non-blocking transaction.
|
||||
* @return status of status_t.
|
||||
*/
|
||||
static inline status_t SPI_SlaveTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count)
|
||||
{
|
||||
return SPI_MasterTransferGetCountDMA(base, handle, count);
|
||||
}
|
||||
|
||||
/*! @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @} */
|
||||
|
||||
#endif /* _FSL_SPI_DMA_H_*/
|
||||
1252
Living_SDK/platform/mcu/lpc54102/drivers/fsl_usart.c
Normal file
1252
Living_SDK/platform/mcu/lpc54102/drivers/fsl_usart.c
Normal file
File diff suppressed because it is too large
Load diff
852
Living_SDK/platform/mcu/lpc54102/drivers/fsl_usart.h
Normal file
852
Living_SDK/platform/mcu/lpc54102/drivers/fsl_usart.h
Normal file
|
|
@ -0,0 +1,852 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NXP Semiconductors, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_USART_H_
|
||||
#define _FSL_USART_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup usart_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief USART driver version 2.0.0. */
|
||||
#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief Error codes for the USART driver. */
|
||||
enum _usart_status
|
||||
{
|
||||
kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */
|
||||
kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */
|
||||
kStatus_USART_TxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 2), /*!< USART transmitter is idle. */
|
||||
kStatus_USART_RxIdle = MAKE_STATUS(kStatusGroup_LPC_USART, 3), /*!< USART receiver is idle. */
|
||||
kStatus_USART_TxError = MAKE_STATUS(kStatusGroup_LPC_USART, 7), /*!< Error happens on txFIFO. */
|
||||
kStatus_USART_RxError = MAKE_STATUS(kStatusGroup_LPC_USART, 9), /*!< Error happens on rxFIFO. */
|
||||
kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8), /*!< Error happens on rx ring buffer */
|
||||
kStatus_USART_NoiseError = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */
|
||||
kStatus_USART_FramingError = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */
|
||||
kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */
|
||||
kStatus_USART_HardwareOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< USART hardware over flow. */
|
||||
kStatus_USART_FifoBusError = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART fifo bus error. */
|
||||
kStatus_USART_BaudrateNotSupport =
|
||||
MAKE_STATUS(kStatusGroup_LPC_USART, 15), /*!< Baudrate is not support in current clock source */
|
||||
};
|
||||
|
||||
/*! @brief USART parity mode. */
|
||||
typedef enum _usart_parity_mode
|
||||
{
|
||||
kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */
|
||||
kUSART_ParityEven = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
|
||||
kUSART_ParityOdd = 0x3U, /*!< Parity enabled, type odd, bit setting: PE|PT = 11 */
|
||||
} usart_parity_mode_t;
|
||||
|
||||
/*! @brief USART stop bit count. */
|
||||
typedef enum _usart_stop_bit_count
|
||||
{
|
||||
kUSART_OneStopBit = 0U, /*!< One stop bit */
|
||||
kUSART_TwoStopBit = 1U, /*!< Two stop bits */
|
||||
} usart_stop_bit_count_t;
|
||||
|
||||
/*! @brief USART data size. */
|
||||
typedef enum _usart_data_len
|
||||
{
|
||||
kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */
|
||||
kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */
|
||||
} usart_data_len_t;
|
||||
|
||||
/*! @brief USART FIFO driection. */
|
||||
typedef enum _usart_fifo_direction
|
||||
{
|
||||
kUSART_FifoTx = 1U, /*!< FIFO direction for transmit. */
|
||||
kUSART_FifoRx = 2U, /*!< FIFO direction for receive. */
|
||||
} usart_fifo_direction_t;
|
||||
|
||||
/*!
|
||||
* @brief USART interrupt configuration structure, default settings all disabled.
|
||||
*/
|
||||
enum _usart_interrupt_enable
|
||||
{
|
||||
kUSART_RxReadyInterruptEnable = (USART_INTENSET_RXRDYEN_MASK), /*!< Receive ready interrupt. */
|
||||
kUSART_TxReadyInterruptEnable = (USART_INTENSET_TXRDYEN_MASK), /*!< Transmit ready interrupt. */
|
||||
kUSART_TxIdleInterruptEnable = (USART_INTENSET_TXIDLEEN_MASK), /*!< Transmit idle interrupt. */
|
||||
kUSART_DeltaCtsInterruptEnable = (USART_INTENSET_DELTACTSEN_MASK), /*!< Cts pin change interrupt. */
|
||||
kUSART_TxDisableInterruptEnable = (USART_INTENSET_TXDISEN_MASK), /*!< Transmit disable interrupt. */
|
||||
kUSART_HardwareOverRunInterruptEnable = (USART_INTENSET_OVERRUNEN_MASK), /*!< hardware ove run interrupt. */
|
||||
kUSART_RxBreakInterruptEnable = (USART_INTENSET_DELTARXBRKEN_MASK), /*!< Receive break interrupt. */
|
||||
kUSART_RxStartInterruptEnable = (USART_INTENSET_STARTEN_MASK), /*!< Receive ready interrupt. */
|
||||
kUSART_FramErrorInterruptEnable = (USART_INTENSET_FRAMERREN_MASK), /*!< Receive start interrupt. */
|
||||
kUSART_ParityErrorInterruptEnable = (USART_INTENSET_PARITYERREN_MASK), /*!< Receive frame error interrupt. */
|
||||
kUSART_RxNoiseInterruptEnable = (USART_INTENSET_RXNOISEEN_MASK), /*!< Receive noise error interrupt. */
|
||||
kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK), /*!< Receive auto baud error interrupt. */
|
||||
kUSART_AllInterruptEnable =
|
||||
(USART_INTENSET_RXRDYEN_MASK | USART_INTENSET_TXRDYEN_MASK | USART_INTENSET_TXIDLEEN_MASK |
|
||||
USART_INTENSET_DELTACTSEN_MASK | USART_INTENSET_TXDISEN_MASK | USART_INTENSET_OVERRUNEN_MASK |
|
||||
USART_INTENSET_DELTARXBRKEN_MASK | USART_INTENSET_STARTEN_MASK | USART_INTENSET_FRAMERREN_MASK |
|
||||
USART_INTENSET_PARITYERREN_MASK | USART_INTENSET_RXNOISEEN_MASK |
|
||||
USART_INTENSET_ABERREN_MASK), /*!< All interrupt. */
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief System FIFO interrupt configuration structure for USART, default settings all disabled.
|
||||
*/
|
||||
enum _usart_fifo_interrupt_enable
|
||||
{
|
||||
kUSART_RxFifoThresholdInterruptEnable =
|
||||
(VFIFO_USART_CTLSETUSART_RXTHINTEN_MASK), /*!< Receive FIFO threshold interrupt. */
|
||||
kUSART_TxFifoThresholdInterruptEnable =
|
||||
(VFIFO_USART_CTLSETUSART_TXTHINTEN_MASK), /*!< Transmit FIFO threshold interrupt. */
|
||||
kUSART_RxFifoTimeOutInterruptEnable =
|
||||
(VFIFO_USART_CTLSETUSART_RXTIMEOUTINTEN_MASK), /*!< Receive FIFO timeout interrupt. */
|
||||
kUSART_FifoAllinterruptEnable = (VFIFO_USART_CTLSETUSART_RXTHINTEN_MASK | VFIFO_USART_CTLSETUSART_TXTHINTEN_MASK |
|
||||
VFIFO_USART_CTLSETUSART_RXTIMEOUTINTEN_MASK), /*!< All FIFO interrupt. */
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief USART status flags.
|
||||
*
|
||||
* This provides constants for the USART status flags for use in the USART functions.
|
||||
*/
|
||||
enum _usart_flags
|
||||
{
|
||||
kUSART_RxReady = (USART_STAT_RXRDY_MASK), /*!< Receive ready flag. */
|
||||
kUSART_RxIdleFlag = (USART_STAT_RXIDLE_MASK), /*!< Receive IDLE flag. */
|
||||
kUSART_TxReady = (USART_STAT_TXRDY_MASK), /*!< Transmit ready flag. */
|
||||
kUSART_TxIdleFlag = (USART_STAT_TXIDLE_MASK), /*!< Transmit idle flag. */
|
||||
kUSART_CtsState = (USART_STAT_CTS_MASK), /*!< Cts pin status. */
|
||||
kUSART_DeltaCtsFlag = (USART_STAT_DELTACTS_MASK), /*!< Cts pin change flag. */
|
||||
kUSART_TxDisableFlag = (USART_STAT_TXDISSTAT_MASK), /*!< Transmit disable flag. */
|
||||
kUSART_HardwareOverrunFlag = (USART_STAT_OVERRUNINT_MASK), /*!< Hardware over run flag. */
|
||||
kUSART_RxBreakFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Receive break flag. */
|
||||
kUSART_RxStartFlag = (USART_STAT_START_MASK), /*!< receive start flag. */
|
||||
kUSART_FramErrorFlag = (USART_STAT_FRAMERRINT_MASK), /*!< Frame error flag. */
|
||||
kUSART_ParityErrorFlag = (USART_STAT_PARITYERRINT_MASK), /*!< Parity error flag. */
|
||||
kUSART_RxNoiseFlag = (USART_STAT_RXNOISEINT_MASK), /*!< Receive noise flag. */
|
||||
kUSART_AutoBaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baud error flag. */
|
||||
};
|
||||
|
||||
/*!
|
||||
* @brief System FIFO status flags for USART.
|
||||
*
|
||||
* This provides constants for the USART status flags for use in the USART functions.
|
||||
*/
|
||||
enum _usart_fifo_flags
|
||||
{
|
||||
kUSART_RxFifoThresholdFlag = (VFIFO_USART_STATUSART_RXTH_MASK), /*!< Receive FIFO threshold reached flag. */
|
||||
kUSART_TxFifoThresholdFlag = (VFIFO_USART_STATUSART_TXTH_MASK), /*!< Transmit FIFO threshold reached flag. */
|
||||
kUSART_RxFifoTimeOutFlag = (VFIFO_USART_STATUSART_RXTIMEOUT_MASK), /*!< Receive time out flag. */
|
||||
kUSART_FifoBusErrorFlag = (VFIFO_USART_STATUSART_BUSERR_MASK), /*!< FIFO bus error flag. */
|
||||
kUSART_RxFifoEmptyFlag = (VFIFO_USART_STATUSART_RXEMPTY_MASK), /*!< Receive fifo buffer empty flag. */
|
||||
kUSART_TxFifoEmptyFlag = (VFIFO_USART_STATUSART_TXEMPTY_MASK), /*!< transmit fifo buffer empty flag. */
|
||||
};
|
||||
|
||||
/*! @brief USART FIFO configuration structure. */
|
||||
typedef struct _usart_fifo_config
|
||||
{
|
||||
bool enableTxFifo; /*!< Transmit FIFO enable */
|
||||
bool enableRxFifo; /*!< Receive FIFO enable */
|
||||
uint8_t txFifoSize; /*!< Transmit FIFO buffer size */
|
||||
uint8_t rxFifoSize; /*!< Receive FIFO buffer size */
|
||||
uint8_t txFifoThreshold; /*!< txFIFO threshold */
|
||||
uint8_t rxFifoThreshold; /*!< rxFIFO threshold */
|
||||
} usart_fifo_config_t;
|
||||
|
||||
/*! @brief USART configuration structure. */
|
||||
typedef struct _usart_config
|
||||
{
|
||||
uint32_t baudRate_Bps; /*!< USART baud rate */
|
||||
bool enableRx; /*!< USART receive enable. */
|
||||
bool enableTx; /*!< USART transmit enable. */
|
||||
usart_parity_mode_t parityMode; /*!< Parity mode, disabled (default), even, odd */
|
||||
usart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits */
|
||||
usart_data_len_t bitCountPerChar; /*!< Data length - 7 bit, 8 bit */
|
||||
bool loopback; /*!< Enable peripheral loopback */
|
||||
usart_fifo_config_t fifoConfig; /*!< FIFO configuration for USART. */
|
||||
} usart_config_t;
|
||||
|
||||
/*! @brief USART transfer structure. */
|
||||
typedef struct _usart_transfer
|
||||
{
|
||||
uint8_t *data; /*!< The buffer of data to be transfer.*/
|
||||
size_t dataSize; /*!< The byte count to be transfer. */
|
||||
} usart_transfer_t;
|
||||
|
||||
/* Forward declaration of the handle typedef. */
|
||||
typedef struct _usart_handle usart_handle_t;
|
||||
|
||||
/*! @brief USART transfer callback function. */
|
||||
typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);
|
||||
|
||||
/*! @brief USART handle structure. */
|
||||
struct _usart_handle
|
||||
{
|
||||
uint8_t *volatile txData; /*!< Address of remaining data to send. */
|
||||
volatile size_t txDataSize; /*!< Size of the remaining data to send. */
|
||||
size_t txDataSizeAll; /*!< Size of the data to send out. */
|
||||
uint8_t *volatile rxData; /*!< Address of remaining data to receive. */
|
||||
volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
|
||||
size_t rxDataSizeAll; /*!< Size of the data to receive. */
|
||||
|
||||
uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */
|
||||
size_t rxRingBufferSize; /*!< Size of the ring buffer. */
|
||||
volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
|
||||
volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
|
||||
|
||||
usart_transfer_callback_t callback; /*!< Callback function. */
|
||||
void *userData; /*!< USART callback function parameter.*/
|
||||
|
||||
volatile uint8_t txState; /*!< TX transfer state. */
|
||||
volatile uint8_t rxState; /*!< RX transfer state */
|
||||
|
||||
bool isTxFifoEnabled; /*!< TX transfer FIFO enabled. */
|
||||
bool isRxFifoEnabled; /*!< RX transfer FIFO enabled. */
|
||||
uint8_t txFifoThreshold; /*!< txFIFO threshold */
|
||||
uint8_t rxFifoThreshold; /*!< rxFIFO threshold */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
/*!
|
||||
* @name Get the instance of USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @brief Returns instance number for USART peripheral base address. */
|
||||
uint32_t USART_GetInstance(USART_Type *base);
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes a USART instance with user configuration structure and peripheral clock.
|
||||
*
|
||||
* This function configures the USART module with the user-defined settings. The user can configure the configuration
|
||||
* structure and also get the default configuration by using the USART_GetDefaultConfig() function.
|
||||
* Example below shows how to use this API to configure USART.
|
||||
* @code
|
||||
* usart_config_t usartConfig;
|
||||
* usartConfig.baudRate_Bps = 115200U;
|
||||
* usartConfig.parityMode = kUSART_ParityDisabled;
|
||||
* usartConfig.stopBitCount = kUSART_OneStopBit;
|
||||
* USART_Init(USART1, &usartConfig, 20000000U);
|
||||
* @endcode
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param config Pointer to user-defined configuration structure.
|
||||
* @param srcClock_Hz USART clock source frequency in HZ.
|
||||
* @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
|
||||
* @retval kStatus_InvalidArgument USART base address is not valid
|
||||
* @retval kStatus_Success Status USART initialize succeed
|
||||
*/
|
||||
status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes a USART instance.
|
||||
*
|
||||
* This function waits for TX complete, disables USART and FIFO if used, and disables the USART clock and FIFO clock if
|
||||
* used.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
*/
|
||||
void USART_Deinit(USART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Gets the default configuration structure.
|
||||
*
|
||||
* This function initializes the USART configuration structure to a default value. The default
|
||||
* values are:
|
||||
* usartConfig->baudRate_Bps = 115200U;
|
||||
* usartConfig->parityMode = kUSART_ParityDisabled;
|
||||
* usartConfig->stopBitCount = kUSART_OneStopBit;
|
||||
* usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
|
||||
* usartConfig->loopback = false;
|
||||
* usartConfig->enableTx = false;
|
||||
* usartConfig->enableRx = false;
|
||||
* ...
|
||||
* @param config Pointer to configuration structure.
|
||||
*/
|
||||
void USART_GetDefaultConfig(usart_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Sets the USART instance baud rate.
|
||||
*
|
||||
* This function configures the USART module baud rate. This function is used to update
|
||||
* the USART module baud rate after the USART module is initialized by the USART_Init.
|
||||
* @code
|
||||
* USART_SetBaudRate(USART1, 115200U, 20000000U);
|
||||
* @endcode
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param baudrate_Bps USART baudrate to be set.
|
||||
* @param srcClock_Hz USART clock source freqency in HZ.
|
||||
* @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
|
||||
* @retval kStatus_Success Set baudrate succeed.
|
||||
* @retval kStatus_InvalidArgument One or more arguments are invalid.
|
||||
*/
|
||||
status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Status
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Get USART status flags.
|
||||
*
|
||||
* This function get all USART status flags, the flags are returned as the logical
|
||||
* OR value of the enumerators @ref _usart_flags. To check a specific status,
|
||||
* compare the return value with enumerators in @ref _usart_flags.
|
||||
* For example, to check whether the RX is ready:
|
||||
* @code
|
||||
* if (kUSART_RxReady & USART_GetStatusFlags(USART1))
|
||||
* {
|
||||
* ...
|
||||
* }
|
||||
* @endcode
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @return USART status flags which are ORed by the enumerators in the _usart_flags.
|
||||
*/
|
||||
static inline uint32_t USART_GetStatusFlags(USART_Type *base)
|
||||
{
|
||||
return base->STAT;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear USART status flags.
|
||||
*
|
||||
* This function clear supported USART status flags
|
||||
* For example:
|
||||
* @code
|
||||
* USART_ClearStatusFlags(USART1, kUSART_HardwareOverrunFlag)
|
||||
* @endcode
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param mask status flags to be cleared.
|
||||
*/
|
||||
static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
|
||||
{
|
||||
base->STAT = mask;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get system FIFO status flags for USART.
|
||||
*
|
||||
* This function get all system FIFO status flags for USART, the flags are returned as the logical
|
||||
* OR value of the enumerators @ref _usart_fifo_flags. To check a specific status,
|
||||
* compare the return value with enumerators in @ref _usart_fifo_flags.
|
||||
* For example, to check whether the TX FIFO is empty:
|
||||
* @code
|
||||
* if (kUSART_TxFifoEmptyFlag & USART_GetFifoStatusFlags(USART1))
|
||||
* {
|
||||
* ...
|
||||
* }
|
||||
* @endcode
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @return USART status flags which are ORed by the enumerators in the _usart_fifo_flags.
|
||||
*/
|
||||
uint32_t USART_GetFifoStatusFlags(USART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Clear FIFO status flag for USART.
|
||||
*
|
||||
* This function clear supported USART status flags
|
||||
* Flags that can be cleared or set are:
|
||||
* kUSART_FifoBusErrorFlag
|
||||
* For example:
|
||||
* @code
|
||||
* USART_ClearFifoStatusFlags(USART0, kUSART_FifoBusErrorFlag)
|
||||
* @endcode
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param mask status flags to be cleared.
|
||||
*/
|
||||
void USART_ClearFifoStatusFlags(USART_Type *base, uint32_t mask);
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables USART interrupts according to the provided mask.
|
||||
*
|
||||
* This function enables the USART interrupts according to the provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
|
||||
* For example, to enable TX ready interrupt and RX ready interrupt:
|
||||
* @code
|
||||
* USART_EnableInterrupts(USART1, kUSART_RxReadyInterruptEnable | kUSART_TxReadyInterruptEnable);
|
||||
* @endcode
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
|
||||
*/
|
||||
static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTENSET = mask & 0x1FF;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables USART interrupts according to a provided mask.
|
||||
*
|
||||
* This function disables the USART interrupts according to a provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
|
||||
* This example shows how to disable the TX ready interrupt and RX ready interrupt:
|
||||
* @code
|
||||
* USART_DisableInterrupts(USART1, kUSART_TxReadyInterruptEnable | kUSART_RxReadyInterruptEnable);
|
||||
* @endcode
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.
|
||||
*/
|
||||
static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
|
||||
{
|
||||
base->INTENCLR = mask & 0x1FF;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Returns enabled USART interrupts.
|
||||
*
|
||||
* This function returns the enabled USART interrupts.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
*/
|
||||
static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base)
|
||||
{
|
||||
return base->INTENSET;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables FIFO interrupts for USART according to the provided mask.
|
||||
*
|
||||
* This function enables the USART FIFO interrupts according to the provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
|
||||
* For example, to enable TX threshold interrupt and RX threshold interrupt:
|
||||
* @code
|
||||
* USART_EnableInterrupts(USART0, kUSART_RxFifoThresholdInterruptEnable | kUSART_RxFifoThresholdInterruptEnable);
|
||||
* @endcode
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
|
||||
*/
|
||||
void USART_EnableFifoInterrupts(USART_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Disables FIFO interrupts for USART according to a provided mask.
|
||||
*
|
||||
* This function disables the USART FIFO interrupts according to a provided mask. The mask
|
||||
* is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
|
||||
* This example shows how to disable the TX threshold interrupt and RX threshold interrupt:
|
||||
* @code
|
||||
* USART_DisableInterrupts(USART1, kUSART_RxFifoThresholdInterruptEnable | kUSART_RxFifoThresholdInterruptEnable);
|
||||
* @endcode
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param mask The interrupts to disable. Logical OR of @ref _usart_fifo_interrupt_enable.
|
||||
*/
|
||||
void USART_DisableFifoInterrupts(USART_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Returns enabled USART FIFO interrupts.
|
||||
*
|
||||
* This function returns the enabled USART FIFO interrupts.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
*/
|
||||
uint32_t USART_GetEnabledFifoInterrupts(USART_Type *base);
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name FIFO Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enable FIFO.
|
||||
*
|
||||
* This function will configure the FIFOs according to the config struct.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param config Pointer to user-defined configuration structure.
|
||||
*/
|
||||
void USART_EnableFifo(USART_Type *base, const usart_fifo_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Disable FIFO.
|
||||
*
|
||||
* This function will disable the FIFO.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
*/
|
||||
void USART_DisableFifo(USART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Is TX FIFO enabled.
|
||||
*
|
||||
* This function will return status if the transmit fifo is enabled. true for enabled and false for not enabled.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param direction the fifo direction need to be check, Tx FIFO or Rx FIFO.
|
||||
* @return true for enabled and false for not enabled.
|
||||
*/
|
||||
bool USART_IsTxFifoEnable(USART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Is RX FIFO enabled.
|
||||
*
|
||||
* This function will return status if the receive fifo is enabled. true for enabled and false for not enabled.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param direction the fifo direction need to be check, Tx FIFO or Rx FIFK.
|
||||
* @return true for enabled and false for not enabled.
|
||||
*/
|
||||
bool USART_IsRxFifoEnable(USART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Flush the FIFO buffer.
|
||||
*
|
||||
* This function will Flush tHE fifo buffer.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param direction the fifo direction need to flushed, Tx FIFO or Rx FIFO.
|
||||
*/
|
||||
void USART_FifoFlush(USART_Type *base, uint32_t direction);
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Bus Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enable the USART transmit.
|
||||
*
|
||||
* This function will enable or disable the USART transmit.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param enable true for enable and false for disable.
|
||||
*/
|
||||
static inline void USART_EnableTx(USART_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
/* Make sure the USART module is enabled. */
|
||||
base->CFG |= USART_CFG_ENABLE_MASK;
|
||||
base->CTL &= ~USART_CTL_TXDIS_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
base->CTL |= USART_CTL_TXDIS_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enable the USART receive.
|
||||
*
|
||||
* This function will enable or disable the USART receive.
|
||||
* Note: if the transmit is enabled, the receive will not be disabled.
|
||||
* @param base USART peripheral base address.
|
||||
* @param enable true for enable and false for disable.
|
||||
*/
|
||||
static inline void USART_EnableRx(USART_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
/* Make sure the USART module is enabled. */
|
||||
base->CFG |= USART_CFG_ENABLE_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If the transmit is disabled too. */
|
||||
if (base->CTL & USART_CTL_TXDIS_MASK)
|
||||
{
|
||||
base->CFG &= ~USART_CFG_ENABLE_MASK;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Writes to the FIFO TXDATUSART register or TXDAT register.
|
||||
*
|
||||
* This function will writes data to the txFIFO register or TXDAT automatly, which depend
|
||||
* on if the system FIFO is enabled.The upper layer must ensure
|
||||
* that txFIFO has space for data to write before calling this function.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param data The byte to write.
|
||||
*/
|
||||
void USART_WriteByte(USART_Type *base, uint8_t data);
|
||||
|
||||
/*!
|
||||
* @brief Reads the FIFO RXDATUSART register or RXDAT directly.
|
||||
*
|
||||
* This function reads data from the FIFO RXDATUSART register or RXDAT automatly. which depend
|
||||
* on if the system FIFO is enabled for USART. The upper layer must
|
||||
* ensure that the rxFIFO is not empty before calling this function.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @return The byte read from USART data register.
|
||||
*/
|
||||
uint8_t USART_ReadByte(USART_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Writes to the TX register using a blocking method.
|
||||
*
|
||||
* This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
|
||||
* to have room and writes data to the TX buffer.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param data Start address of the data to write.
|
||||
* @param length Size of the data to write.
|
||||
*/
|
||||
void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
|
||||
|
||||
/*!
|
||||
* @brief Read RX data register using a blocking method.
|
||||
*
|
||||
* This function polls the RX register, waits for the RX register to be full or for RX FIFO to
|
||||
* have data and read data from the TX register.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param data Start address of the buffer to store the received data.
|
||||
* @param length Size of the buffer.
|
||||
* @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
|
||||
* @retval kStatus_USART_ParityError Noise error happened while receiving data.
|
||||
* @retval kStatus_USART_NoiseError Framing error happened while receiving data.
|
||||
* @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
|
||||
* @retval kStatus_Success Successfully received all data.
|
||||
*/
|
||||
status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name Transactional
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the USART handle.
|
||||
*
|
||||
* This function initializes the USART handle which can be used for other USART
|
||||
* transactional APIs. Usually, for a specified USART instance,
|
||||
* call this API once to get the initialized handle.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
* @param callback The callback function.
|
||||
* @param userData The parameter of the callback function.
|
||||
*/
|
||||
status_t USART_TransferCreateHandle(USART_Type *base,
|
||||
usart_handle_t *handle,
|
||||
usart_transfer_callback_t callback,
|
||||
void *userData);
|
||||
|
||||
/*!
|
||||
* @brief Transmits a buffer of data using the interrupt method.
|
||||
*
|
||||
* This function sends data using an interrupt method. This is a non-blocking function, which
|
||||
* returns directly without waiting for all data to be written to the TX register. When
|
||||
* all data is written to the TX register in the IRQ handler, the USART driver calls the callback
|
||||
* function and passes the @ref kStatus_USART_TxIdle as status parameter.
|
||||
*
|
||||
* @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
|
||||
* to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
|
||||
* check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
* @param xfer USART transfer structure. See #usart_transfer_t.
|
||||
* @retval kStatus_Success Successfully start the data transmission.
|
||||
* @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
*/
|
||||
status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Sets up the RX ring buffer.
|
||||
*
|
||||
* This function sets up the RX ring buffer to a specific USART handle.
|
||||
*
|
||||
* When the RX ring buffer is used, data received are stored into the ring buffer even when the
|
||||
* user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
|
||||
* in the ring buffer, the user can get the received data from the ring buffer directly.
|
||||
*
|
||||
* @note When using the RX ring buffer, one byte is reserved for internal use. In other
|
||||
* words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
* @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
|
||||
* @param ringBufferSize size of the ring buffer.
|
||||
*/
|
||||
void USART_TransferStartRingBuffer(USART_Type *base,
|
||||
usart_handle_t *handle,
|
||||
uint8_t *ringBuffer,
|
||||
size_t ringBufferSize);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the background transfer and uninstalls the ring buffer.
|
||||
*
|
||||
* This function aborts the background transfer and uninstalls the ring buffer.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
*/
|
||||
void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Get the length of received data in RX ring buffer.
|
||||
*
|
||||
* @param handle USART handle pointer.
|
||||
* @return Length of received data in RX ring buffer.
|
||||
*/
|
||||
size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data transmit.
|
||||
*
|
||||
* This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
|
||||
* how many bytes are still not sent out.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
*/
|
||||
void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Get the number of bytes that have been written to USART TX register.
|
||||
*
|
||||
* This function gets the number of bytes that have been written to USART TX
|
||||
* register by interrupt method.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
* @param count Send bytes count.
|
||||
* @retval kStatus_NoTransferInProgress No send in progress.
|
||||
* @retval kStatus_InvalidArgument Parameter is invalid.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count;
|
||||
*/
|
||||
status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
|
||||
|
||||
/*!
|
||||
* @brief Receives a buffer of data using an interrupt method.
|
||||
*
|
||||
* This function receives data using an interrupt method. This is a non-blocking function, which
|
||||
* returns without waiting for all data to be received.
|
||||
* If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
|
||||
* the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
|
||||
* After copying, if the data in the ring buffer is not enough to read, the receive
|
||||
* request is saved by the USART driver. When the new data arrives, the receive request
|
||||
* is serviced first. When all data is received, the USART driver notifies the upper layer
|
||||
* through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.
|
||||
* For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
|
||||
* The 5 bytes are copied to the xfer->data and this function returns with the
|
||||
* parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
|
||||
* saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
|
||||
* If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
|
||||
* to receive data to the xfer->data. When all data is received, the upper layer is notified.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
* @param xfer USART transfer structure, see #usart_transfer_t.
|
||||
* @param receivedBytes Bytes received from the ring buffer directly.
|
||||
* @retval kStatus_Success Successfully queue the transfer into transmit queue.
|
||||
* @retval kStatus_USART_RxBusy Previous receive request is not finished.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
*/
|
||||
status_t USART_TransferReceiveNonBlocking(USART_Type *base,
|
||||
usart_handle_t *handle,
|
||||
usart_transfer_t *xfer,
|
||||
size_t *receivedBytes);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the interrupt-driven data receiving.
|
||||
*
|
||||
* This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
|
||||
* how many bytes not received yet.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
*/
|
||||
void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Get the number of bytes that have been received.
|
||||
*
|
||||
* This function gets the number of bytes that have been received.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
* @param count Receive bytes count.
|
||||
* @retval kStatus_NoTransferInProgress No receive in progress.
|
||||
* @retval kStatus_InvalidArgument Parameter is invalid.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count;
|
||||
*/
|
||||
status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
|
||||
|
||||
/*!
|
||||
* @brief USART IRQ handle function.
|
||||
*
|
||||
* This function handles the USART transmit and receive IRQ request.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
*/
|
||||
void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_USART_H_ */
|
||||
271
Living_SDK/platform/mcu/lpc54102/drivers/fsl_usart_dma.c
Normal file
271
Living_SDK/platform/mcu/lpc54102/drivers/fsl_usart_dma.c
Normal file
|
|
@ -0,0 +1,271 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NXP Semiconductors, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_usart.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "fsl_dma.h"
|
||||
#include "fsl_usart_dma.h"
|
||||
|
||||
/*<! Structure definition for uart_dma_handle_t. The structure is private. */
|
||||
typedef struct _usart_dma_private_handle
|
||||
{
|
||||
USART_Type *base;
|
||||
usart_dma_handle_t *handle;
|
||||
} usart_dma_private_handle_t;
|
||||
|
||||
enum _usart_transfer_states
|
||||
{
|
||||
kUSART_TxIdle, /* TX idle. */
|
||||
kUSART_TxBusy, /* TX busy. */
|
||||
kUSART_RxIdle, /* RX idle. */
|
||||
kUSART_RxBusy /* RX busy. */
|
||||
};
|
||||
|
||||
/*<! Private handle only used for internally. */
|
||||
static usart_dma_private_handle_t s_dmaPrivateHandle[FSL_FEATURE_SOC_USART_COUNT];
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
static void USART_TransferSendDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
|
||||
{
|
||||
assert(handle);
|
||||
assert(param);
|
||||
|
||||
usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
|
||||
|
||||
/* Wait for the transmit is complete, disable UART TX DMA. */
|
||||
while (!(kUSART_TxIdleFlag & USART_GetStatusFlags(usartPrivateHandle->base)))
|
||||
{
|
||||
}
|
||||
|
||||
usartPrivateHandle->handle->txState = kUSART_TxIdle;
|
||||
|
||||
if (usartPrivateHandle->handle->callback)
|
||||
{
|
||||
usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle,
|
||||
usartPrivateHandle->handle->userData);
|
||||
}
|
||||
}
|
||||
|
||||
static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode)
|
||||
{
|
||||
assert(handle);
|
||||
assert(param);
|
||||
|
||||
usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param;
|
||||
|
||||
usartPrivateHandle->handle->rxState = kUSART_RxIdle;
|
||||
|
||||
if (usartPrivateHandle->handle->callback)
|
||||
{
|
||||
usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle,
|
||||
usartPrivateHandle->handle->userData);
|
||||
}
|
||||
}
|
||||
|
||||
status_t USART_TransferCreateHandleDMA(USART_Type *base,
|
||||
usart_dma_handle_t *handle,
|
||||
usart_dma_transfer_callback_t callback,
|
||||
void *userData,
|
||||
dma_handle_t *txDmaHandle,
|
||||
dma_handle_t *rxDmaHandle)
|
||||
{
|
||||
int32_t instance = 0;
|
||||
|
||||
/* check 'base' */
|
||||
assert(!(NULL == base));
|
||||
if (NULL == base)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
/* check 'handle' */
|
||||
assert(!(NULL == handle));
|
||||
if (NULL == handle)
|
||||
{
|
||||
return kStatus_InvalidArgument;
|
||||
}
|
||||
|
||||
instance = USART_GetInstance(base);
|
||||
|
||||
memset(handle, 0, sizeof(*handle));
|
||||
/* assign 'base' and 'handle' */
|
||||
s_dmaPrivateHandle[instance].base = base;
|
||||
s_dmaPrivateHandle[instance].handle = handle;
|
||||
|
||||
/* set tx/rx 'idle' state */
|
||||
handle->rxState = kUSART_RxIdle;
|
||||
handle->txState = kUSART_TxIdle;
|
||||
|
||||
handle->callback = callback;
|
||||
handle->userData = userData;
|
||||
|
||||
handle->rxDmaHandle = rxDmaHandle;
|
||||
handle->txDmaHandle = txDmaHandle;
|
||||
|
||||
/* Configure TX. */
|
||||
if (txDmaHandle)
|
||||
{
|
||||
DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]);
|
||||
}
|
||||
|
||||
/* Configure RX. */
|
||||
if (rxDmaHandle)
|
||||
{
|
||||
DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]);
|
||||
}
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
|
||||
status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
|
||||
{
|
||||
assert(handle);
|
||||
assert(handle->txDmaHandle);
|
||||
assert(xfer);
|
||||
assert(xfer->data);
|
||||
assert(xfer->dataSize);
|
||||
|
||||
dma_transfer_config_t xferConfig;
|
||||
status_t status;
|
||||
uint32_t instance = USART_GetInstance(base);
|
||||
|
||||
/* If previous TX not finished. */
|
||||
if (kUSART_TxBusy == handle->txState)
|
||||
{
|
||||
status = kStatus_USART_TxBusy;
|
||||
}
|
||||
else
|
||||
{
|
||||
handle->txState = kUSART_TxBusy;
|
||||
handle->txDataSizeAll = xfer->dataSize;
|
||||
|
||||
if (!USART_IsTxFifoEnable(base))
|
||||
{
|
||||
/* Prepare transfer. */
|
||||
DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)&base->TXDAT, sizeof(uint8_t), xfer->dataSize,
|
||||
kDMA_MemoryToPeripheral, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Prepare transfer. */
|
||||
DMA_PrepareTransfer(&xferConfig, xfer->data, (void *)&VFIFO->USART[instance].TXDATUSART, sizeof(uint8_t),
|
||||
xfer->dataSize, kDMA_MemoryToPeripheral, NULL);
|
||||
}
|
||||
/* Submit transfer. */
|
||||
DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
|
||||
DMA_StartTransfer(handle->txDmaHandle);
|
||||
|
||||
status = kStatus_Success;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer)
|
||||
{
|
||||
assert(handle);
|
||||
assert(handle->rxDmaHandle);
|
||||
assert(xfer);
|
||||
assert(xfer->data);
|
||||
assert(xfer->dataSize);
|
||||
|
||||
dma_transfer_config_t xferConfig;
|
||||
status_t status;
|
||||
uint32_t instance = USART_GetInstance(base);
|
||||
|
||||
/* If previous RX not finished. */
|
||||
if (kUSART_RxBusy == handle->rxState)
|
||||
{
|
||||
status = kStatus_USART_RxBusy;
|
||||
}
|
||||
else
|
||||
{
|
||||
handle->rxState = kUSART_RxBusy;
|
||||
handle->rxDataSizeAll = xfer->dataSize;
|
||||
|
||||
if (!USART_IsRxFifoEnable(base))
|
||||
{
|
||||
/* Prepare transfer. */
|
||||
DMA_PrepareTransfer(&xferConfig, (void *)&base->RXDAT, xfer->data, sizeof(uint8_t), xfer->dataSize,
|
||||
kDMA_PeripheralToMemory, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Prepare transfer. */
|
||||
DMA_PrepareTransfer(&xferConfig, (void *)&VFIFO->USART[instance].RXDATUSART, xfer->data, sizeof(uint8_t),
|
||||
xfer->dataSize, kDMA_PeripheralToMemory, NULL);
|
||||
}
|
||||
/* Submit transfer. */
|
||||
DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
|
||||
DMA_StartTransfer(handle->rxDmaHandle);
|
||||
|
||||
status = kStatus_Success;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle)
|
||||
{
|
||||
assert(NULL != handle);
|
||||
assert(NULL != handle->txDmaHandle);
|
||||
|
||||
/* Stop transfer. */
|
||||
DMA_AbortTransfer(handle->txDmaHandle);
|
||||
handle->txState = kUSART_TxIdle;
|
||||
}
|
||||
|
||||
void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle)
|
||||
{
|
||||
assert(NULL != handle);
|
||||
assert(NULL != handle->rxDmaHandle);
|
||||
|
||||
/* Stop transfer. */
|
||||
DMA_AbortTransfer(handle->rxDmaHandle);
|
||||
handle->rxState = kUSART_RxIdle;
|
||||
}
|
||||
|
||||
status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count)
|
||||
{
|
||||
assert(handle);
|
||||
assert(handle->rxDmaHandle);
|
||||
assert(count);
|
||||
|
||||
if (kUSART_RxIdle == handle->rxState)
|
||||
{
|
||||
return kStatus_NoTransferInProgress;
|
||||
}
|
||||
|
||||
*count = handle->rxDataSizeAll - DMA_GetRemainingBytes(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
|
||||
|
||||
return kStatus_Success;
|
||||
}
|
||||
177
Living_SDK/platform/mcu/lpc54102/drivers/fsl_usart_dma.h
Normal file
177
Living_SDK/platform/mcu/lpc54102/drivers/fsl_usart_dma.h
Normal file
|
|
@ -0,0 +1,177 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NXP Semiconductors, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_USART_DMA_H_
|
||||
#define _FSL_USART_DMA_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_dma.h"
|
||||
#include "fsl_usart.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup usart_dma_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Forward declaration of the handle typedef. */
|
||||
typedef struct _usart_dma_handle usart_dma_handle_t;
|
||||
|
||||
/*! @brief UART transfer callback function. */
|
||||
typedef void (*usart_dma_transfer_callback_t)(USART_Type *base,
|
||||
usart_dma_handle_t *handle,
|
||||
status_t status,
|
||||
void *userData);
|
||||
|
||||
/*!
|
||||
* @brief UART DMA handle
|
||||
*/
|
||||
struct _usart_dma_handle
|
||||
{
|
||||
USART_Type *base; /*!< UART peripheral base address. */
|
||||
|
||||
usart_dma_transfer_callback_t callback; /*!< Callback function. */
|
||||
void *userData; /*!< UART callback function parameter.*/
|
||||
size_t rxDataSizeAll; /*!< Size of the data to receive. */
|
||||
size_t txDataSizeAll; /*!< Size of the data to send out. */
|
||||
|
||||
dma_handle_t *txDmaHandle; /*!< The DMA TX channel used. */
|
||||
dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */
|
||||
|
||||
volatile uint8_t txState; /*!< TX transfer state. */
|
||||
volatile uint8_t rxState; /*!< RX transfer state */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
/*!
|
||||
* @name DMA transactional
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the USART handle which is used in transactional functions.
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle Pointer to usart_dma_handle_t structure.
|
||||
* @param callback Callback function.
|
||||
* @param userData User data.
|
||||
* @param txDmaHandle User-requested DMA handle for TX DMA transfer.
|
||||
* @param rxDmaHandle User-requested DMA handle for RX DMA transfer.
|
||||
*/
|
||||
status_t USART_TransferCreateHandleDMA(USART_Type *base,
|
||||
usart_dma_handle_t *handle,
|
||||
usart_dma_transfer_callback_t callback,
|
||||
void *userData,
|
||||
dma_handle_t *txDmaHandle,
|
||||
dma_handle_t *rxDmaHandle);
|
||||
|
||||
/*!
|
||||
* @brief Sends data using DMA.
|
||||
*
|
||||
* This function sends data using DMA. This is a non-blocking function, which returns
|
||||
* right away. When all data is sent, the send callback function is called.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
* @param xfer USART DMA transfer structure. See #usart_transfer_t.
|
||||
* @retval kStatus_Success if succeed, others failed.
|
||||
* @retval kStatus_USART_TxBusy Previous transfer on going.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
*/
|
||||
status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Receives data using DMA.
|
||||
*
|
||||
* This function receives data using DMA. This is a non-blocking function, which returns
|
||||
* right away. When all data is received, the receive callback function is called.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle Pointer to usart_dma_handle_t structure.
|
||||
* @param xfer USART DMA transfer structure. See #usart_transfer_t.
|
||||
* @retval kStatus_Success if succeed, others failed.
|
||||
* @retval kStatus_USART_RxBusy Previous transfer on going.
|
||||
* @retval kStatus_InvalidArgument Invalid argument.
|
||||
*/
|
||||
status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the sent data using DMA.
|
||||
*
|
||||
* This function aborts send data using DMA.
|
||||
*
|
||||
* @param base USART peripheral base address
|
||||
* @param handle Pointer to usart_dma_handle_t structure
|
||||
*/
|
||||
void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Aborts the received data using DMA.
|
||||
*
|
||||
* This function aborts the received data using DMA.
|
||||
*
|
||||
* @param base USART peripheral base address
|
||||
* @param handle Pointer to usart_dma_handle_t structure
|
||||
*/
|
||||
void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle);
|
||||
|
||||
/*!
|
||||
* @brief Get the number of bytes that have been received.
|
||||
*
|
||||
* This function gets the number of bytes that have been received.
|
||||
*
|
||||
* @param base USART peripheral base address.
|
||||
* @param handle USART handle pointer.
|
||||
* @param count Receive bytes count.
|
||||
* @retval kStatus_NoTransferInProgress No receive in progress.
|
||||
* @retval kStatus_InvalidArgument Parameter is invalid.
|
||||
* @retval kStatus_Success Get successfully through the parameter \p count;
|
||||
*/
|
||||
status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_USART_DMA_H_ */
|
||||
170
Living_SDK/platform/mcu/lpc54102/drivers/fsl_utick.c
Normal file
170
Living_SDK/platform/mcu/lpc54102/drivers/fsl_utick.c
Normal file
|
|
@ -0,0 +1,170 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_utick.h"
|
||||
#include "fsl_power.h"
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/* Typedef for interrupt handler. */
|
||||
typedef void (*utick_isr_t)(UTICK_Type *base, utick_callback_t cb);
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
/*!
|
||||
* @brief Gets the instance from the base address
|
||||
*
|
||||
* @param base UTICK peripheral base address
|
||||
*
|
||||
* @return The UTICK instance
|
||||
*/
|
||||
static uint32_t UTICK_GetInstance(UTICK_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/* Array of UTICK handle. */
|
||||
static utick_callback_t s_utickHandle[FSL_FEATURE_SOC_UTICK_COUNT];
|
||||
/* Array of UTICK peripheral base address. */
|
||||
static UTICK_Type *const s_utickBases[] = UTICK_BASE_PTRS;
|
||||
/* Array of UTICK IRQ number. */
|
||||
static const IRQn_Type s_utickIRQ[] = UTICK_IRQS;
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Array of UTICK clock name. */
|
||||
static const clock_ip_name_t s_utickClock[] = UTICK_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
/* UTICK ISR for transactional APIs. */
|
||||
static utick_isr_t s_utickIsr;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t UTICK_GetInstance(UTICK_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < ARRAY_SIZE(s_utickBases); instance++)
|
||||
{
|
||||
if (s_utickBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < ARRAY_SIZE(s_utickBases));
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb)
|
||||
{
|
||||
uint32_t instance;
|
||||
|
||||
/* Get instance from peripheral base address. */
|
||||
instance = UTICK_GetInstance(base);
|
||||
|
||||
/* Save the handle in global variables to support the double weak mechanism. */
|
||||
s_utickHandle[instance] = cb;
|
||||
EnableDeepSleepIRQ(s_utickIRQ[instance]);
|
||||
base->CTRL = count | UTICK_CTRL_REPEAT(mode);
|
||||
}
|
||||
|
||||
void UTICK_Init(UTICK_Type *base)
|
||||
{
|
||||
/* Enable utick clock */
|
||||
CLOCK_EnableClock(s_utickClock[UTICK_GetInstance(base)]);
|
||||
/* Power up Watchdog oscillator*/
|
||||
POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC);
|
||||
s_utickIsr = UTICK_HandleIRQ;
|
||||
}
|
||||
|
||||
void UTICK_Deinit(UTICK_Type *base)
|
||||
{
|
||||
/* Turn off utick */
|
||||
base->CTRL = 0;
|
||||
/* Disable utick clock */
|
||||
CLOCK_DisableClock(s_utickClock[UTICK_GetInstance(base)]);
|
||||
}
|
||||
|
||||
uint32_t UTICK_GetStatusFlags(UTICK_Type *base)
|
||||
{
|
||||
return (base->STAT);
|
||||
}
|
||||
|
||||
void UTICK_ClearStatusFlags(UTICK_Type *base)
|
||||
{
|
||||
base->STAT = UTICK_STAT_INTR_MASK;
|
||||
}
|
||||
|
||||
void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb)
|
||||
{
|
||||
UTICK_ClearStatusFlags(base);
|
||||
if (cb)
|
||||
{
|
||||
cb();
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(UTICK0)
|
||||
void UTICK0_DriverIRQHandler(void)
|
||||
{
|
||||
s_utickIsr(UTICK0, s_utickHandle[0]);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#if defined(UTICK1)
|
||||
void UTICK1_DriverIRQHandler(void)
|
||||
{
|
||||
s_utickIsr(UTICK1, s_utickHandle[1]);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#if defined(UTICK2)
|
||||
void UTICK2_DriverIRQHandler(void)
|
||||
{
|
||||
s_utickIsr(UTICK2, s_utickHandle[2]);
|
||||
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
||||
exception return operation might vector to incorrect interrupt */
|
||||
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
||||
__DSB();
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
140
Living_SDK/platform/mcu/lpc54102/drivers/fsl_utick.h
Normal file
140
Living_SDK/platform/mcu/lpc54102/drivers/fsl_utick.h
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_UTICK_H_
|
||||
#define _FSL_UTICK_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
/*!
|
||||
* @addtogroup utick
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief UTICK driver version 2.0.0. */
|
||||
#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief UTICK timer operational mode. */
|
||||
typedef enum _utick_mode
|
||||
{
|
||||
kUTICK_Onetime = 0x0U, /*!< Trigger once*/
|
||||
kUTICK_Repeat = 0x1U, /*!< Trigger repeatedly */
|
||||
} utick_mode_t;
|
||||
|
||||
/*! @brief UTICK callback function. */
|
||||
typedef void (*utick_callback_t)(void);
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes an UTICK by turning its bus clock on
|
||||
*
|
||||
*/
|
||||
void UTICK_Init(UTICK_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes a UTICK instance.
|
||||
*
|
||||
* This function shuts down Utick bus clock
|
||||
*
|
||||
* @param base UTICK peripheral base address.
|
||||
*/
|
||||
void UTICK_Deinit(UTICK_Type *base);
|
||||
/*!
|
||||
* @brief Get Status Flags.
|
||||
*
|
||||
* This returns the status flag
|
||||
*
|
||||
* @param base UTICK peripheral base address.
|
||||
* @return status register value
|
||||
*/
|
||||
uint32_t UTICK_GetStatusFlags(UTICK_Type *base);
|
||||
/*!
|
||||
* @brief Clear Status Interrupt Flags.
|
||||
*
|
||||
* This clears intr status flag
|
||||
*
|
||||
* @param base UTICK peripheral base address.
|
||||
* @return none
|
||||
*/
|
||||
void UTICK_ClearStatusFlags(UTICK_Type *base);
|
||||
|
||||
/*!
|
||||
* @brief Starts UTICK.
|
||||
*
|
||||
* This function starts a repeat/onetime countdown with an optional callback
|
||||
*
|
||||
* @param base UTICK peripheral base address.
|
||||
* @param mode UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)
|
||||
* @param count UTICK timer mode (ie kUTICK_onetime or kUTICK_repeat)
|
||||
* @param cb UTICK callback (can be left as NULL if none, otherwise should be a void func(void))
|
||||
* @return none
|
||||
*/
|
||||
void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_callback_t cb);
|
||||
/*!
|
||||
* @brief UTICK Interrupt Service Handler.
|
||||
*
|
||||
* This function handles the interrupt and refers to the callback array in the driver to callback user (as per request
|
||||
* in UTICK_SetTick()).
|
||||
* if no user callback is scheduled, the interrupt will simply be cleared.
|
||||
*
|
||||
* @param base UTICK peripheral base address.
|
||||
* @param cb callback scheduled for this instance of UTICK
|
||||
* @return none
|
||||
*/
|
||||
void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_UTICK_H_ */
|
||||
168
Living_SDK/platform/mcu/lpc54102/drivers/fsl_wwdt.c
Normal file
168
Living_SDK/platform/mcu/lpc54102/drivers/fsl_wwdt.c
Normal file
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_wwdt.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Prototypes
|
||||
******************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief Gets the instance from the base address
|
||||
*
|
||||
* @param base WWDT peripheral base address
|
||||
*
|
||||
* @return The WWDT instance
|
||||
*/
|
||||
static uint32_t WWDT_GetInstance(WWDT_Type *base);
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
/*! @brief Pointers to WWDT bases for each instance. */
|
||||
static WWDT_Type *const s_wwdtBases[] = WWDT_BASE_PTRS;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/*! @brief Pointers to WWDT clocks for each instance. */
|
||||
static const clock_ip_name_t s_wwdtClocks[] = WWDT_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*! @brief Pointers to WWDT resets for each instance. */
|
||||
static const reset_ip_name_t s_wwdtResets[] = WWDT_RSTS;
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
static uint32_t WWDT_GetInstance(WWDT_Type *base)
|
||||
{
|
||||
uint32_t instance;
|
||||
uint32_t wwdtArrayCount = (sizeof(s_wwdtBases) / sizeof(s_wwdtBases[0]));
|
||||
|
||||
/* Find the instance index from base address mappings. */
|
||||
for (instance = 0; instance < wwdtArrayCount; instance++)
|
||||
{
|
||||
if (s_wwdtBases[instance] == base)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(instance < wwdtArrayCount);
|
||||
|
||||
return instance;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
|
||||
void WWDT_GetDefaultConfig(wwdt_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
/* Enable the watch dog */
|
||||
config->enableWwdt = true;
|
||||
/* Disable the watchdog timeout reset */
|
||||
config->enableWatchdogReset = false;
|
||||
/* Disable the watchdog protection for updating the timeout value */
|
||||
config->enableWatchdogProtect = false;
|
||||
/* Do not lock the watchdog oscillator */
|
||||
config->enableLockOscillator = false;
|
||||
/* Windowing is not in effect */
|
||||
config->windowValue = 0xFFFFFFU;
|
||||
/* Set the timeout value to the max */
|
||||
config->timeoutValue = 0xFFFFFFU;
|
||||
/* No warning is provided */
|
||||
config->warningValue = 0;
|
||||
}
|
||||
|
||||
void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
|
||||
uint32_t value = 0U;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Enable the WWDT clock */
|
||||
CLOCK_EnableClock(s_wwdtClocks[WWDT_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Reset the WWDT module */
|
||||
RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]);
|
||||
|
||||
value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) |
|
||||
WWDT_MOD_WDPROTECT(config->enableWatchdogProtect) | WWDT_MOD_LOCK(config->enableLockOscillator);
|
||||
/* Set configruation */
|
||||
base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue);
|
||||
base->TC = WWDT_TC_COUNT(config->timeoutValue);
|
||||
base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue);
|
||||
base->MOD = value;
|
||||
}
|
||||
|
||||
void WWDT_Deinit(WWDT_Type *base)
|
||||
{
|
||||
WWDT_Disable(base);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Disable the WWDT clock */
|
||||
CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void WWDT_Refresh(WWDT_Type *base)
|
||||
{
|
||||
uint32_t primaskValue = 0U;
|
||||
|
||||
/* Disable the global interrupt to protect refresh sequence */
|
||||
primaskValue = DisableGlobalIRQ();
|
||||
base->FEED = WWDT_FIRST_WORD_OF_REFRESH;
|
||||
base->FEED = WWDT_SECOND_WORD_OF_REFRESH;
|
||||
EnableGlobalIRQ(primaskValue);
|
||||
}
|
||||
|
||||
void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask)
|
||||
{
|
||||
/* Clear the WDINT bit so that we don't accidentally clear it */
|
||||
uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK));
|
||||
|
||||
/* Clear timeout by writing a zero */
|
||||
if (mask & kWWDT_TimeoutFlag)
|
||||
{
|
||||
reg &= ~WWDT_MOD_WDTOF_MASK;
|
||||
}
|
||||
|
||||
/* Clear warning interrupt flag by writing a one */
|
||||
if (mask & kWWDT_WarningFlag)
|
||||
{
|
||||
reg |= WWDT_MOD_WDINT_MASK;
|
||||
}
|
||||
|
||||
base->MOD = reg;
|
||||
}
|
||||
283
Living_SDK/platform/mcu/lpc54102/drivers/fsl_wwdt.h
Normal file
283
Living_SDK/platform/mcu/lpc54102/drivers/fsl_wwdt.h
Normal file
|
|
@ -0,0 +1,283 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_WWDT_H_
|
||||
#define _FSL_WWDT_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup wwdt
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @file */
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
*******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief Defines WWDT driver version 2.0.0. */
|
||||
#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
|
||||
/*@}*/
|
||||
|
||||
/*! @name Refresh sequence */
|
||||
/*@{*/
|
||||
#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */
|
||||
#define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */
|
||||
/*@}*/
|
||||
|
||||
/*! @brief Describes WWDT configuration structure. */
|
||||
typedef struct _wwdt_config
|
||||
{
|
||||
bool enableWwdt; /*!< Enables or disables WWDT */
|
||||
bool enableWatchdogReset; /*!< true: Watchdog timeout will cause a chip reset
|
||||
false: Watchdog timeout will not cause a chip reset */
|
||||
bool enableWatchdogProtect; /*!< true: Enable watchdog protect i.e timeout value can only be
|
||||
changed after counter is below warning & window values
|
||||
false: Disable watchdog protect; timeout value can be changed
|
||||
at any time */
|
||||
bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented
|
||||
Once set, this bit can only be cleared by a reset
|
||||
false: Do not lock oscillator */
|
||||
uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */
|
||||
uint32_t timeoutValue; /*!< Timeout value */
|
||||
uint32_t warningValue; /*!< Watchdog time counter value that will generate a
|
||||
warning interrupt. Set this to 0 for no warning */
|
||||
|
||||
} wwdt_config_t;
|
||||
|
||||
/*!
|
||||
* @brief WWDT status flags.
|
||||
*
|
||||
* This structure contains the WWDT status flags for use in the WWDT functions.
|
||||
*/
|
||||
enum _wwdt_status_flags_t
|
||||
{
|
||||
kWWDT_TimeoutFlag = WWDT_MOD_WDTOF_MASK, /*!< Time-out flag, set when the timer times out */
|
||||
kWWDT_WarningFlag = WWDT_MOD_WDINT_MASK /*!< Warning interrupt flag, set when timer is below the value WDWARNINT */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
*******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*!
|
||||
* @name WWDT Initialization and De-initialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes WWDT configure sturcture.
|
||||
*
|
||||
* This function initializes the WWDT configure structure to default value. The default
|
||||
* value are:
|
||||
* @code
|
||||
* config->enableWwdt = true;
|
||||
* config->enableWatchdogReset = false;
|
||||
* config->enableWatchdogProtect = false;
|
||||
* config->enableLockOscillator = false;
|
||||
* config->windowValue = 0xFFFFFFU;
|
||||
* config->timeoutValue = 0xFFFFFFU;
|
||||
* config->warningValue = 0;
|
||||
* @endcode
|
||||
*
|
||||
* @param config Pointer to WWDT config structure.
|
||||
* @see wwdt_config_t
|
||||
*/
|
||||
void WWDT_GetDefaultConfig(wwdt_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Initializes the WWDT.
|
||||
*
|
||||
* This function initializes the WWDT. When called, the WWDT runs according to the configuration.
|
||||
*
|
||||
* Example:
|
||||
* @code
|
||||
* wwdt_config_t config;
|
||||
* WWDT_GetDefaultConfig(&config);
|
||||
* config.timeoutValue = 0x7ffU;
|
||||
* WWDT_Init(wwdt_base,&config);
|
||||
* @endcode
|
||||
*
|
||||
* @param base WWDT peripheral base address
|
||||
* @param config The configuration of WWDT
|
||||
*/
|
||||
void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Shuts down the WWDT.
|
||||
*
|
||||
* This function shuts down the WWDT.
|
||||
*
|
||||
* @param base WWDT peripheral base address
|
||||
*/
|
||||
void WWDT_Deinit(WWDT_Type *base);
|
||||
|
||||
/* @} */
|
||||
|
||||
/*!
|
||||
* @name WWDT Functional Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables the WWDT module.
|
||||
*
|
||||
* This function write value into WWDT_MOD register to enable the WWDT, it is a write-once bit;
|
||||
* once this bit is set to one and a watchdog feed is performed, the watchdog timer will run
|
||||
* permanently.
|
||||
*
|
||||
* @param base WWDT peripheral base address
|
||||
*/
|
||||
static inline void WWDT_Enable(WWDT_Type *base)
|
||||
{
|
||||
base->MOD |= WWDT_MOD_WDEN_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Disables the WWDT module.
|
||||
*
|
||||
* This function write value into WWDT_MOD register to disable the WWDT.
|
||||
*
|
||||
* @param base WWDT peripheral base address
|
||||
*/
|
||||
static inline void WWDT_Disable(WWDT_Type *base)
|
||||
{
|
||||
base->MOD &= ~WWDT_MOD_WDEN_MASK;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets all WWDT status flags.
|
||||
*
|
||||
* This function gets all status flags.
|
||||
*
|
||||
* Example for getting Timeout Flag:
|
||||
* @code
|
||||
* uint32_t status;
|
||||
* status = WWDT_GetStatusFlags(wwdt_base) & kWWDT_TimeoutFlag;
|
||||
* @endcode
|
||||
* @param base WWDT peripheral base address
|
||||
* @return The status flags. This is the logical OR of members of the
|
||||
* enumeration ::_wwdt_status_flags_t
|
||||
*/
|
||||
static inline uint32_t WWDT_GetStatusFlags(WWDT_Type *base)
|
||||
{
|
||||
return (base->MOD & (WWDT_MOD_WDTOF_MASK | WWDT_MOD_WDINT_MASK));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Clear WWDT flag.
|
||||
*
|
||||
* This function clears WWDT status flag.
|
||||
*
|
||||
* Example for clearing warning flag:
|
||||
* @code
|
||||
* WWDT_ClearStatusFlags(wwdt_base, kWWDT_WarningFlag);
|
||||
* @endcode
|
||||
* @param base WWDT peripheral base address
|
||||
* @param mask The status flags to clear. This is a logical OR of members of the
|
||||
* enumeration ::_wwdt_status_flags_t
|
||||
*/
|
||||
void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask);
|
||||
|
||||
/*!
|
||||
* @brief Set the WWDT warning value.
|
||||
*
|
||||
* The WDWARNINT register determines the watchdog timer counter value that will generate a watchdog
|
||||
* interrupt. When the watchdog timer counter is no longer greater than the value defined by
|
||||
* WARNINT, an interrupt will be generated after the subsequent WDCLK.
|
||||
*
|
||||
* @param base WWDT peripheral base address
|
||||
* @param warningValue WWDT warning value.
|
||||
*/
|
||||
static inline void WWDT_SetWarningValue(WWDT_Type *base, uint32_t warningValue)
|
||||
{
|
||||
base->WARNINT = WWDT_WARNINT_WARNINT(warningValue);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Set the WWDT timeout value.
|
||||
*
|
||||
* This function sets the timeout value. Every time a feed sequence occurs the value in the TC
|
||||
* register is loaded into the Watchdog timer. Writing a value below 0xFF will cause 0xFF to be
|
||||
* loaded into the TC register. Thus the minimum time-out interval is TWDCLK*256*4.
|
||||
* If enableWatchdogProtect flag is true in wwdt_config_t config structure, any attempt to change
|
||||
* the timeout value before the watchdog counter is below the warning and window values
|
||||
* will cause a watchdog reset and set the WDTOF flag.
|
||||
*
|
||||
* @param base WWDT peripheral base address
|
||||
* @param timeoutCount WWDT timeout value, count of WWDT clock tick.
|
||||
*/
|
||||
static inline void WWDT_SetTimeoutValue(WWDT_Type *base, uint32_t timeoutCount)
|
||||
{
|
||||
base->TC = WWDT_TC_COUNT(timeoutCount);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Sets the WWDT window value.
|
||||
*
|
||||
* The WINDOW register determines the highest TV value allowed when a watchdog feed is performed.
|
||||
* If a feed sequence occurs when timer value is greater than the value in WINDOW, a watchdog
|
||||
* event will occur. To disable windowing, set windowValue to 0xFFFFFF (maximum possible timer
|
||||
* value) so windowing is not in effect.
|
||||
*
|
||||
* @param base WWDT peripheral base address
|
||||
* @param windowValue WWDT window value.
|
||||
*/
|
||||
static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue)
|
||||
{
|
||||
base->WINDOW = WWDT_WINDOW_WINDOW(windowValue);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Refreshes the WWDT timer.
|
||||
*
|
||||
* This function feeds the WWDT.
|
||||
* This function should be called before WWDT timer is in timeout. Otherwise, a reset is asserted.
|
||||
*
|
||||
* @param base WWDT peripheral base address
|
||||
*/
|
||||
void WWDT_Refresh(WWDT_Type *base);
|
||||
|
||||
/*@}*/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_WWDT_H_ */
|
||||
67
Living_SDK/platform/mcu/lpc54102/fsl_device_registers.h
Normal file
67
Living_SDK/platform/mcu/lpc54102/fsl_device_registers.h
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright 2014-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __FSL_DEVICE_REGISTERS_H__
|
||||
#define __FSL_DEVICE_REGISTERS_H__
|
||||
|
||||
/*
|
||||
* Include the cpu specific register header files.
|
||||
*
|
||||
* The CPU macro should be declared in the project or makefile.
|
||||
*/
|
||||
#if (defined(CPU_LPC54102J256BD64_cm4) || defined(CPU_LPC54102J256UK49_cm4) || defined(CPU_LPC54102J512BD64_cm4) || \
|
||||
defined(CPU_LPC54102J512UK49_cm4))
|
||||
|
||||
#define LPC54102_cm4_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "LPC54102_cm4.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "LPC54102_cm4_features.h"
|
||||
|
||||
#elif (defined(CPU_LPC54102J256BD64_cm0plus) || defined(CPU_LPC54102J256UK49_cm0plus) || defined(CPU_LPC54102J512BD64_cm0plus) || \
|
||||
defined(CPU_LPC54102J512UK49_cm0plus))
|
||||
|
||||
#define LPC54102_cm0plus_SERIES
|
||||
|
||||
/* CMSIS-style register definitions */
|
||||
#include "LPC54102_cm0plus.h"
|
||||
/* CPU specific feature definitions */
|
||||
#include "LPC54102_cm0plus_features.h"
|
||||
|
||||
#else
|
||||
#error "No valid CPU defined!"
|
||||
#endif
|
||||
|
||||
#endif /* __FSL_DEVICE_REGISTERS_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF
|
||||
******************************************************************************/
|
||||
104
Living_SDK/platform/mcu/lpc54102/hal/csp_log.c
Normal file
104
Living_SDK/platform/mcu/lpc54102/hal/csp_log.c
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* POSIX getopt for Windows
|
||||
* Code given out at the 1985 UNIFORUM conference in Dallas.
|
||||
*
|
||||
* From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985
|
||||
* Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET
|
||||
* Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP
|
||||
* Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix
|
||||
* From: std-unix@ut-sally.UUCP (Moderator, John Quarterman)
|
||||
* Newsgroups: mod.std.unix
|
||||
* Subject: public domain AT&T getopt source
|
||||
* Message-ID: <3352@ut-sally.UUCP>
|
||||
* Date: 3 Nov 85 19:34:15 GMT
|
||||
* Date-Received: 4 Nov 85 12:25:09 GMT
|
||||
* Organization: IEEE/P1003 Portable Operating System Environment Committee
|
||||
* Lines: 91
|
||||
* Approved: jsq@ut-sally.UUC
|
||||
* Here's something you've all been waiting for: the AT&T public domain
|
||||
* source for getopt(3). It is the code which was given out at the 1985
|
||||
* UNIFORUM conference in Dallas. I obtained it by electronic mail
|
||||
* directly from AT&T. The people there assure me that it is indeed
|
||||
* in the public domain
|
||||
* There is no manual page. That is because the one they gave out at
|
||||
* UNIFORUM was slightly different from the current System V Release 2
|
||||
* manual page. The difference apparently involved a note about the
|
||||
* famous rules 5 and 6, recommending using white space between an option
|
||||
* and its first argument, and not grouping options that have arguments.
|
||||
* Getopt itself is currently lenient about both of these things White
|
||||
* space is allowed, but not mandatory, and the last option in a group can
|
||||
* have an argument. That particular version of the man page evidently
|
||||
* has no official existence, and my source at AT&T did not send a copy.
|
||||
* The current SVR2 man page reflects the actual behavor of this getopt.
|
||||
* However, I am not about to post a copy of anything licensed by AT&T.
|
||||
*/
|
||||
#include <stdarg.h>
|
||||
#include <stdio.h>
|
||||
#include "fsl_str.h"
|
||||
#if SDK_DEBUGCONSOLE
|
||||
#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN 128u
|
||||
static void DbgConsole_RelocateLog(char *buf, int32_t *indicator, char val, int len)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < len; i++)
|
||||
{
|
||||
if ((*indicator + 1) >= DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN)
|
||||
{
|
||||
LOG_Push((uint8_t *)buf, *indicator);
|
||||
*indicator = 0U;
|
||||
}
|
||||
|
||||
buf[*indicator] = val;
|
||||
(*indicator)++;
|
||||
}
|
||||
}
|
||||
|
||||
int csp_printf(const char *fmt_s, ...)
|
||||
{
|
||||
va_list ap;
|
||||
int logLength = 0U, result = 0U;
|
||||
char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {0U};
|
||||
|
||||
va_start(ap, fmt_s);
|
||||
/* format print log first */
|
||||
logLength = StrFormatPrintf(fmt_s, ap, printBuf, DbgConsole_RelocateLog);
|
||||
/* print log */
|
||||
result = LOG_Push((uint8_t *)printBuf, logLength);
|
||||
|
||||
va_end(ap);
|
||||
|
||||
return result;
|
||||
}
|
||||
#else
|
||||
int csp_printf(const char *fmt, ...){return 0;}
|
||||
#endif
|
||||
|
||||
553
Living_SDK/platform/mcu/lpc54102/hal/hal_flash.c
Normal file
553
Living_SDK/platform/mcu/lpc54102/hal/hal_flash.c
Normal file
|
|
@ -0,0 +1,553 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* POSIX getopt for Windows
|
||||
* Code given out at the 1985 UNIFORUM conference in Dallas.
|
||||
*
|
||||
* From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985
|
||||
* Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET
|
||||
* Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP
|
||||
* Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix
|
||||
* From: std-unix@ut-sally.UUCP (Moderator, John Quarterman)
|
||||
* Newsgroups: mod.std.unix
|
||||
* Subject: public domain AT&T getopt source
|
||||
* Message-ID: <3352@ut-sally.UUCP>
|
||||
* Date: 3 Nov 85 19:34:15 GMT
|
||||
* Date-Received: 4 Nov 85 12:25:09 GMT
|
||||
* Organization: IEEE/P1003 Portable Operating System Environment Committee
|
||||
* Lines: 91
|
||||
* Approved: jsq@ut-sally.UUC
|
||||
* Here's something you've all been waiting for: the AT&T public domain
|
||||
* source for getopt(3). It is the code which was given out at the 1985
|
||||
* UNIFORUM conference in Dallas. I obtained it by electronic mail
|
||||
* directly from AT&T. The people there assure me that it is indeed
|
||||
* in the public domain
|
||||
* There is no manual page. That is because the one they gave out at
|
||||
* UNIFORUM was slightly different from the current System V Release 2
|
||||
* manual page. The difference apparently involved a note about the
|
||||
* famous rules 5 and 6, recommending using white space between an option
|
||||
* and its first argument, and not grouping options that have arguments.
|
||||
* Getopt itself is currently lenient about both of these things White
|
||||
* space is allowed, but not mandatory, and the last option in a group can
|
||||
* have an argument. That particular version of the man page evidently
|
||||
* has no official existence, and my source at AT&T did not send a copy.
|
||||
* The current SVR2 man page reflects the actual behavor of this getopt.
|
||||
* However, I am not about to post a copy of anything licensed by AT&T.
|
||||
*/
|
||||
#include <stdarg.h>
|
||||
#include <stdio.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "fsl_device_registers.h"
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "fsl_power.h"
|
||||
#include "hal/soc/flash.h"
|
||||
#include "fsl_flashiap.h"
|
||||
|
||||
|
||||
typedef int32_t (*flash_device_erase)(uint32_t phy_address, uint32_t size);
|
||||
typedef int32_t (*flash_device_write)(uint32_t phy_address, const void *data, uint32_t size);
|
||||
typedef int32_t (*flash_device_read)(uint32_t phy_address, void *data, uint32_t size);
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t start_address;
|
||||
uint32_t disk_size;
|
||||
uint32_t page_size;
|
||||
uint32_t sector_size;
|
||||
flash_device_erase erase;
|
||||
flash_device_write write;
|
||||
flash_device_read read;
|
||||
} flash_device_t;
|
||||
|
||||
|
||||
//static uint8_t page_buffer[FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES];
|
||||
|
||||
static int32_t embedded_flash_erase(uint32_t phy_address, uint32_t size)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
uint32_t system_clock = 0;
|
||||
status_t status = 0;
|
||||
|
||||
uint32_t start_sector = 0;
|
||||
uint32_t end_sector = 0;
|
||||
uint32_t sectors_to_erase = 0;
|
||||
uint32_t start_page = 0;
|
||||
uint32_t end_page = 0;
|
||||
uint32_t pages_to_erase = 0;
|
||||
|
||||
uint32_t write_step1_size = 0;
|
||||
uint32_t write_step2_size = 0;
|
||||
uint32_t residue = size;
|
||||
|
||||
/* FLASH Controller Clock should be enabled firstly */
|
||||
CLOCK_EnableClock(kCLOCK_Flash);
|
||||
|
||||
system_clock = CLOCK_GetMainClkFreq();
|
||||
/* Step 1, Erase flash until sector boundary or end */
|
||||
if (phy_address % FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES != 0) // Not at sector boundary
|
||||
{
|
||||
write_step1_size = FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES -
|
||||
phy_address % FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES;
|
||||
if (size < write_step1_size)
|
||||
{
|
||||
write_step1_size = size;
|
||||
}
|
||||
|
||||
if((phy_address % FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES) != 0)
|
||||
{
|
||||
ret = -EIO; //Not supported yet
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if((write_step1_size % FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES) != 0)
|
||||
{
|
||||
ret = -EIO;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
start_sector = phy_address/FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES;
|
||||
start_page = phy_address / FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES;
|
||||
|
||||
__disable_irq();
|
||||
status = FLASHIAP_PrepareSectorForWrite(start_sector, start_sector);
|
||||
if (status != kStatus_FLASHIAP_Success) {
|
||||
__enable_irq();
|
||||
ret = -EIO; //Check status flag for detail error
|
||||
goto exit;
|
||||
}
|
||||
pages_to_erase = write_step1_size / FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES;
|
||||
end_page = start_page + pages_to_erase - 1;
|
||||
|
||||
status = FLASHIAP_ErasePage(start_page, end_page, system_clock);
|
||||
if (status != kStatus_FLASHIAP_Success) {
|
||||
__enable_irq();
|
||||
ret = -EIO; //Check status flag for detail error
|
||||
goto exit;
|
||||
}
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
residue = size - write_step1_size;
|
||||
|
||||
sectors_to_erase = residue / FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES;
|
||||
|
||||
/* Step 2, sector erasing */
|
||||
if(sectors_to_erase > 0) { /* More than one sector to erase */
|
||||
start_sector = (phy_address + write_step1_size) / FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES;
|
||||
end_sector = start_sector + sectors_to_erase - 1;
|
||||
__disable_irq();
|
||||
status = FLASHIAP_PrepareSectorForWrite(start_sector, end_sector);
|
||||
if (status != kStatus_FLASHIAP_Success) {
|
||||
__enable_irq();
|
||||
ret = -EIO; //Check status flag for detailed error
|
||||
goto exit;
|
||||
}
|
||||
status = FLASHIAP_EraseSector(start_sector, end_sector, system_clock);
|
||||
if (status != kStatus_FLASHIAP_Success) {
|
||||
__enable_irq();
|
||||
ret = -EIO; //Check status flag for detailed error
|
||||
goto exit;
|
||||
}
|
||||
__enable_irq();
|
||||
write_step2_size = FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES * sectors_to_erase;
|
||||
}
|
||||
|
||||
residue = size - write_step1_size - write_step2_size;
|
||||
/* Step 3, erasing residues */
|
||||
if (residue > 0)
|
||||
{
|
||||
if (residue % FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES != 0)
|
||||
{
|
||||
ret = -EIO; //Check status flag for detailed error
|
||||
goto exit;
|
||||
}
|
||||
start_sector = (phy_address + write_step1_size + write_step2_size) / FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES;
|
||||
start_page = (phy_address + write_step1_size + write_step2_size) / FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES;
|
||||
|
||||
__disable_irq();
|
||||
status = FLASHIAP_PrepareSectorForWrite(start_sector, start_sector);
|
||||
if (status != kStatus_FLASHIAP_Success)
|
||||
{
|
||||
__enable_irq();
|
||||
ret = -EIO;
|
||||
goto exit;
|
||||
}
|
||||
pages_to_erase = residue / FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES;
|
||||
end_page = start_page + pages_to_erase - 1;
|
||||
|
||||
status = FLASHIAP_ErasePage(start_page, end_page, system_clock);
|
||||
if (status != kStatus_FLASHIAP_Success) {
|
||||
__enable_irq();
|
||||
ret = -EIO; //Check status flag for detail error
|
||||
goto exit;
|
||||
}
|
||||
__enable_irq();
|
||||
}
|
||||
exit:
|
||||
CLOCK_DisableClock(kCLOCK_Flash);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int32_t embedded_flash_write(uint32_t phy_address, const void *data, uint32_t size)
|
||||
{
|
||||
int32_t ret = 0;
|
||||
uint32_t system_clock = 0;
|
||||
status_t status = 0;
|
||||
|
||||
uint32_t start_sector = 0;
|
||||
uint32_t end_sector = 0;
|
||||
|
||||
/* FLASH Program size 256 | 512 | 1024 | 4096 */
|
||||
uint16_t write_size_option[4] = {256, 512, 1024, 4096};
|
||||
uint8_t option = 0;
|
||||
uint32_t offset = 0;
|
||||
|
||||
|
||||
/* FLASH Controller Clock should be enabled firstly */
|
||||
CLOCK_EnableClock(kCLOCK_Flash);
|
||||
system_clock = CLOCK_GetMainClkFreq();
|
||||
if (phy_address % FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES != 0)
|
||||
{
|
||||
ret = -EIO; // Not Support yet
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (size % FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES != 0)
|
||||
{
|
||||
ret = -EIO;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
while (offset < size) {
|
||||
start_sector = (phy_address + offset)/FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES;
|
||||
option = sizeof(write_size_option)/sizeof(write_size_option[0]) - 1;
|
||||
while(option >= 0)
|
||||
{
|
||||
if ((option == 0) || ((size - offset) / write_size_option[option] != 0 &&
|
||||
(phy_address + offset + write_size_option[option]) <= (start_sector + 1) * FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES))
|
||||
break;
|
||||
option--;
|
||||
}
|
||||
|
||||
end_sector = start_sector;
|
||||
__disable_irq();
|
||||
status = FLASHIAP_PrepareSectorForWrite(start_sector, end_sector);
|
||||
if (status != kStatus_FLASHIAP_Success) {
|
||||
__enable_irq();
|
||||
ret = -EIO; //Check status flag for detail error
|
||||
goto exit;
|
||||
}
|
||||
|
||||
status = FLASHIAP_CopyRamToFlash(phy_address + offset, ((uint32_t *)data) + (offset >> 2), write_size_option[option], system_clock);
|
||||
if (status != kStatus_FLASHIAP_Success) {
|
||||
__enable_irq();
|
||||
ret = -EIO; //Check status flag for detail error
|
||||
goto exit;
|
||||
}
|
||||
__enable_irq();
|
||||
offset += write_size_option[option];
|
||||
}
|
||||
|
||||
exit:
|
||||
CLOCK_DisableClock(kCLOCK_Flash);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int32_t embedded_flash_read(uint32_t phy_address, void *data, uint32_t size)
|
||||
{
|
||||
/* Use Address to access embeded FLASH, it is on the memory map */
|
||||
/* Do NOT use this method */
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
static flash_device_t flash_device[HAL_FLASH_MAX] =
|
||||
{
|
||||
{
|
||||
.start_address = 0,
|
||||
.disk_size = 0x80000,
|
||||
.page_size = 0x100,
|
||||
.sector_size = 0x8000,
|
||||
embedded_flash_erase,
|
||||
embedded_flash_write,
|
||||
embedded_flash_read,
|
||||
},
|
||||
{ 0, 0, 0, 0, NULL, NULL, NULL },
|
||||
{ 0, 0, 0, 0, NULL, NULL, NULL }
|
||||
};
|
||||
|
||||
|
||||
hal_logic_partition_t hal_logic_partition[HAL_PARTITION_MAX] =
|
||||
{
|
||||
{ HAL_FLASH_EMBEDDED, "Bootloader", 0, 0, PAR_OPT_WRITE_DIS|PAR_OPT_READ_DIS},
|
||||
{ HAL_FLASH_EMBEDDED, "Application", 0x40000, 0x40000, PAR_OPT_WRITE_EN|PAR_OPT_READ_EN},
|
||||
{ HAL_FLASH_NONE, NULL, 0, 0, PAR_OPT_WRITE_DIS|PAR_OPT_READ_DIS},
|
||||
{ HAL_FLASH_NONE, NULL, 0, 0, PAR_OPT_WRITE_DIS|PAR_OPT_READ_DIS},
|
||||
{ HAL_FLASH_NONE, NULL, 0, 0, PAR_OPT_WRITE_DIS|PAR_OPT_READ_DIS},
|
||||
{ HAL_FLASH_NONE, NULL, 0, 0, PAR_OPT_WRITE_DIS|PAR_OPT_READ_DIS},
|
||||
{ HAL_FLASH_NONE, NULL, 0, 0, PAR_OPT_WRITE_DIS|PAR_OPT_READ_DIS},
|
||||
{ HAL_FLASH_NONE, NULL, 0, 0, PAR_OPT_WRITE_DIS|PAR_OPT_READ_DIS},
|
||||
{ HAL_FLASH_NONE, NULL, 0, 0, PAR_OPT_WRITE_DIS|PAR_OPT_READ_DIS},
|
||||
{ HAL_FLASH_NONE, NULL, 0, 0, PAR_OPT_WRITE_DIS|PAR_OPT_READ_DIS},
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* Get the infomation of the specified flash area
|
||||
*
|
||||
* @param[in] in_partition The target flash logical partition which should be erased
|
||||
*
|
||||
* @return HAL_logi_partition struct
|
||||
*/
|
||||
/* FIXME: Return value should be a CONST */
|
||||
hal_logic_partition_t *hal_flash_get_info(hal_partition_t in_partition)
|
||||
{
|
||||
hal_logic_partition_t *p_logic_partition = NULL;
|
||||
|
||||
if (in_partition >= HAL_PARTITION_MAX) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
switch (in_partition)
|
||||
{
|
||||
case HAL_PARTITION_APPLICATION:
|
||||
p_logic_partition = &hal_logic_partition[in_partition];
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return p_logic_partition;
|
||||
}
|
||||
|
||||
/**
|
||||
* Erase an area on a Flash logical partition
|
||||
*
|
||||
* @note Erase on an address will erase all data on a sector that the
|
||||
* address is belonged to, this function does not save data that
|
||||
* beyond the address area but in the affected sector, the data
|
||||
* will be lost.
|
||||
*
|
||||
* @param[in] in_partition The target flash logical partition which should be erased
|
||||
* @param[in] off_set Start address of the erased flash area
|
||||
* @param[in] size Size of the erased flash area
|
||||
*
|
||||
* @return 0 : On success, EIO : If an error occurred with any step
|
||||
*/
|
||||
int32_t hal_flash_erase(hal_partition_t in_partition, uint32_t off_set, uint32_t size)
|
||||
{
|
||||
hal_logic_partition_t *p_logic_partition = NULL;
|
||||
uint32_t start_addr_phy = 0;
|
||||
flash_device_t *device = NULL;
|
||||
int32_t ret = 0;
|
||||
|
||||
p_logic_partition = hal_flash_get_info(in_partition);
|
||||
if ((p_logic_partition == NULL) || (p_logic_partition->partition_owner == HAL_FLASH_NONE))
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
device = &flash_device[p_logic_partition->partition_owner];
|
||||
|
||||
start_addr_phy = off_set + device->start_address;
|
||||
if (start_addr_phy + size > device->disk_size)
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ret = device->erase(start_addr_phy, size);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write data to an area on a flash logical partition without erase
|
||||
*
|
||||
* @param[in] in_partition The target flash logical partition which should be read which should be written
|
||||
* @param[in] off_set Point to the start address that the data is written to, and
|
||||
* point to the last unwritten address after this function is
|
||||
* returned, so you can call this function serval times without
|
||||
* update this start address.
|
||||
* @param[in] inBuffer point to the data buffer that will be written to flash
|
||||
* @param[in] inBufferLength The length of the buffer
|
||||
*
|
||||
* @return 0 : On success, EIO : If an error occurred with any step
|
||||
*/
|
||||
int32_t hal_flash_write(hal_partition_t in_partition, uint32_t *off_set,
|
||||
const void *in_buf, uint32_t in_buf_len)
|
||||
{
|
||||
hal_logic_partition_t *p_logic_partition = NULL;
|
||||
uint32_t start_addr_phy = 0;
|
||||
flash_device_t *device = NULL;
|
||||
int32_t ret = 0;
|
||||
|
||||
p_logic_partition = hal_flash_get_info(in_partition);
|
||||
if ((p_logic_partition == NULL) || (p_logic_partition->partition_owner == HAL_FLASH_NONE))
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
device = &flash_device[p_logic_partition->partition_owner];
|
||||
|
||||
start_addr_phy = *off_set + device->start_address;
|
||||
if ((uint32_t)start_addr_phy + in_buf_len > device->disk_size)
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ret = device->write(start_addr_phy, in_buf, in_buf_len);
|
||||
*off_set += in_buf_len;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Write data to an area on a flash logical partition with erase first
|
||||
*
|
||||
* @param[in] in_partition The target flash logical partition which should be read which should be written
|
||||
* @param[in] off_set Point to the start address that the data is written to, and
|
||||
* point to the last unwritten address after this function is
|
||||
* returned, so you can call this function serval times without
|
||||
* update this start address.
|
||||
* @param[in] inBuffer point to the data buffer that will be written to flash
|
||||
* @param[in] inBufferLength The length of the buffer
|
||||
*
|
||||
* @return 0 : On success, EIO : If an error occurred with any step
|
||||
*/
|
||||
int32_t hal_flash_erase_write(hal_partition_t in_partition, uint32_t *off_set,
|
||||
const void *in_buf, uint32_t in_buf_len)
|
||||
{
|
||||
hal_logic_partition_t *p_logic_partition = NULL;
|
||||
uint32_t start_addr_phy = 0;
|
||||
flash_device_t *device = NULL;
|
||||
int32_t ret = 0;
|
||||
|
||||
p_logic_partition = hal_flash_get_info(in_partition);
|
||||
if ((p_logic_partition == NULL) || (p_logic_partition->partition_owner == HAL_FLASH_NONE))
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
device = &flash_device[p_logic_partition->partition_owner];
|
||||
|
||||
start_addr_phy = *off_set + device->start_address + p_logic_partition->partition_start_addr;
|
||||
if (start_addr_phy + in_buf_len > device->disk_size)
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ret = device->erase(start_addr_phy, in_buf_len);
|
||||
if (ret < 0)
|
||||
{
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = device->write(start_addr_phy, in_buf, in_buf_len);
|
||||
|
||||
*off_set += in_buf_len;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Read data from an area on a Flash to data buffer in RAM
|
||||
*
|
||||
* @param[in] in_partition The target flash logical partition which should be read
|
||||
* @param[in] off_set Point to the start address that the data is read, and
|
||||
* point to the last unread address after this function is
|
||||
* returned, so you can call this function serval times without
|
||||
* update this start address.
|
||||
* @param[in] outBuffer Point to the data buffer that stores the data read from flash
|
||||
* @param[in] inBufferLength The length of the buffer
|
||||
*
|
||||
* @return 0 : On success, EIO : If an error occurred with any step
|
||||
*/
|
||||
int32_t hal_flash_read(hal_partition_t in_partition, uint32_t *off_set,
|
||||
void *out_buf, uint32_t in_buf_len)
|
||||
{
|
||||
hal_logic_partition_t *p_logic_partition = NULL;
|
||||
uint32_t start_addr_phy = 0;
|
||||
flash_device_t *device = NULL;
|
||||
int32_t ret = 0;
|
||||
|
||||
p_logic_partition = hal_flash_get_info(in_partition);
|
||||
if ((p_logic_partition == NULL) || (p_logic_partition->partition_owner == HAL_FLASH_NONE))
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
device = &flash_device[p_logic_partition->partition_owner];
|
||||
|
||||
start_addr_phy = *off_set + device->start_address;
|
||||
if (start_addr_phy + in_buf_len > device->disk_size)
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ret = device->read(start_addr_phy, out_buf, in_buf_len);
|
||||
|
||||
*off_set += in_buf_len;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set security options on a logical partition
|
||||
*
|
||||
* @param[in] partition The target flash logical partition
|
||||
* @param[in] offset Point to the start address that the data is read, and
|
||||
* point to the last unread address after this function is
|
||||
* returned, so you can call this function serval times without
|
||||
* update this start address.
|
||||
* @param[in] size Size of enabled flash area
|
||||
*
|
||||
* @return 0 : On success, EIO : If an error occurred with any step
|
||||
*/
|
||||
int32_t hal_flash_enable_secure(hal_partition_t partition, uint32_t off_set, uint32_t size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Disable security options on a logical partition
|
||||
*
|
||||
* @param[in] partition The target flash logical partition
|
||||
* @param[in] offset Point to the start address that the data is read, and
|
||||
* point to the last unread address after this function is
|
||||
* returned, so you can call this function serval times without
|
||||
* update this start address.
|
||||
* @param[in] size Size of disabled flash area
|
||||
*
|
||||
* @return 0 : On success, EIO : If an error occurred with any step
|
||||
*/
|
||||
int32_t hal_flash_dis_secure(hal_partition_t partition, uint32_t off_set, uint32_t size)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
84
Living_SDK/platform/mcu/lpc54102/hal/hal_ota.c
Normal file
84
Living_SDK/platform/mcu/lpc54102/hal/hal_ota.c
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* POSIX getopt for Windows
|
||||
* Code given out at the 1985 UNIFORUM conference in Dallas.
|
||||
*
|
||||
* From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985
|
||||
* Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET
|
||||
* Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP
|
||||
* Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix
|
||||
* From: std-unix@ut-sally.UUCP (Moderator, John Quarterman)
|
||||
* Newsgroups: mod.std.unix
|
||||
* Subject: public domain AT&T getopt source
|
||||
* Message-ID: <3352@ut-sally.UUCP>
|
||||
* Date: 3 Nov 85 19:34:15 GMT
|
||||
* Date-Received: 4 Nov 85 12:25:09 GMT
|
||||
* Organization: IEEE/P1003 Portable Operating System Environment Committee
|
||||
* Lines: 91
|
||||
* Approved: jsq@ut-sally.UUC
|
||||
* Here's something you've all been waiting for: the AT&T public domain
|
||||
* source for getopt(3). It is the code which was given out at the 1985
|
||||
* UNIFORUM conference in Dallas. I obtained it by electronic mail
|
||||
* directly from AT&T. The people there assure me that it is indeed
|
||||
* in the public domain
|
||||
* There is no manual page. That is because the one they gave out at
|
||||
* UNIFORUM was slightly different from the current System V Release 2
|
||||
* manual page. The difference apparently involved a note about the
|
||||
* famous rules 5 and 6, recommending using white space between an option
|
||||
* and its first argument, and not grouping options that have arguments.
|
||||
* Getopt itself is currently lenient about both of these things White
|
||||
* space is allowed, but not mandatory, and the last option in a group can
|
||||
* have an argument. That particular version of the man page evidently
|
||||
* has no official existence, and my source at AT&T did not send a copy.
|
||||
* The current SVR2 man page reflects the actual behavor of this getopt.
|
||||
* However, I am not about to post a copy of anything licensed by AT&T.
|
||||
*/
|
||||
#include "hal/ota.h"
|
||||
#include "hal/soc/flash.h"
|
||||
#include "fsl_debug_console.h"
|
||||
|
||||
int lpc54102_ota_init(hal_ota_module_t *m, void *something)
|
||||
{
|
||||
PRINTF("lpc54102_ota_init\r\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
int lpc54102_ota_write(hal_ota_module_t *m, volatile uint32_t *off_set,
|
||||
uint8_t *in_buf , uint32_t in_buf_len)
|
||||
{
|
||||
PRINTF("lpc54102_ota_write\r\n");
|
||||
return hal_flash_erase_write(HAL_PARTITION_APPLICATION, (uint32_t *)off_set, in_buf, in_buf_len);
|
||||
}
|
||||
|
||||
int lpc54102_ota_read(hal_ota_module_t *m, volatile uint32_t *off_set,
|
||||
uint8_t *out_buf , uint32_t out_buf_len)
|
||||
{
|
||||
PRINTF("lpc54102_ota_read\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
int lpc54102_ota_set_boot(hal_ota_module_t *m, void *something)
|
||||
{
|
||||
PRINTF("lpc54102_ota_set_boot\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
struct hal_ota_module_s hal_lpc54102_ota_module = {
|
||||
.init = lpc54102_ota_init,
|
||||
.ota_write = lpc54102_ota_write,
|
||||
.ota_read = lpc54102_ota_read,
|
||||
.ota_set_boot = lpc54102_ota_set_boot,
|
||||
};
|
||||
|
||||
|
||||
295
Living_SDK/platform/mcu/lpc54102/hal/hal_uart.c
Normal file
295
Living_SDK/platform/mcu/lpc54102/hal/hal_uart.c
Normal file
|
|
@ -0,0 +1,295 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* POSIX getopt for Windows
|
||||
* Code given out at the 1985 UNIFORUM conference in Dallas.
|
||||
*
|
||||
* From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985
|
||||
* Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET
|
||||
* Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP
|
||||
* Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix
|
||||
* From: std-unix@ut-sally.UUCP (Moderator, John Quarterman)
|
||||
* Newsgroups: mod.std.unix
|
||||
* Subject: public domain AT&T getopt source
|
||||
* Message-ID: <3352@ut-sally.UUCP>
|
||||
* Date: 3 Nov 85 19:34:15 GMT
|
||||
* Date-Received: 4 Nov 85 12:25:09 GMT
|
||||
* Organization: IEEE/P1003 Portable Operating System Environment Committee
|
||||
* Lines: 91
|
||||
* Approved: jsq@ut-sally.UUC
|
||||
* Here's something you've all been waiting for: the AT&T public domain
|
||||
* source for getopt(3). It is the code which was given out at the 1985
|
||||
* UNIFORUM conference in Dallas. I obtained it by electronic mail
|
||||
* directly from AT&T. The people there assure me that it is indeed
|
||||
* in the public domain
|
||||
* There is no manual page. That is because the one they gave out at
|
||||
* UNIFORUM was slightly different from the current System V Release 2
|
||||
* manual page. The difference apparently involved a note about the
|
||||
* famous rules 5 and 6, recommending using white space between an option
|
||||
* and its first argument, and not grouping options that have arguments.
|
||||
* Getopt itself is currently lenient about both of these things White
|
||||
* space is allowed, but not mandatory, and the last option in a group can
|
||||
* have an argument. That particular version of the man page evidently
|
||||
* has no official existence, and my source at AT&T did not send a copy.
|
||||
* The current SVR2 man page reflects the actual behavor of this getopt.
|
||||
* However, I am not about to post a copy of anything licensed by AT&T.
|
||||
*/
|
||||
#include <stdarg.h>
|
||||
#include <stdio.h>
|
||||
#include <errno.h>
|
||||
#include "hal/soc/soc.h"
|
||||
#include "fsl_device_registers.h"
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_clock.h"
|
||||
#include "fsl_usart.h"
|
||||
|
||||
#include "fsl_debug_console.h"
|
||||
|
||||
|
||||
static const uint32_t s_uartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;
|
||||
|
||||
/* Global Variable for VFS DEBUG Output */
|
||||
uart_dev_t uart_0 = {
|
||||
.port = 0, /* uart port */
|
||||
.config = {115200, DATA_WIDTH_8BIT, NO_PARITY, STOP_BITS_1, FLOW_CONTROL_DISABLED}, /* uart config */
|
||||
.priv = NULL /* priv data */
|
||||
};
|
||||
|
||||
uart_dev_t uart_1 = {
|
||||
.port = 1, /* uart port */
|
||||
.config = {115200, DATA_WIDTH_8BIT, NO_PARITY, STOP_BITS_1, FLOW_CONTROL_DISABLED}, /* uart config */
|
||||
.priv = NULL /* priv data */
|
||||
};
|
||||
|
||||
uart_dev_t uart_2 = {
|
||||
.port = 2, /* uart port */
|
||||
.config = {115200, DATA_WIDTH_8BIT, NO_PARITY, STOP_BITS_1, FLOW_CONTROL_DISABLED}, /* uart config */
|
||||
.priv = NULL /* priv data */
|
||||
};
|
||||
|
||||
uart_dev_t uart_3 = {
|
||||
.port = 3, /* uart port */
|
||||
.config = {115200, DATA_WIDTH_8BIT, NO_PARITY, STOP_BITS_1, FLOW_CONTROL_DISABLED}, /* uart config */
|
||||
.priv = NULL /* priv data */
|
||||
};
|
||||
|
||||
uart_dev_t uart_4 = {
|
||||
.port = 4, /* uart port */
|
||||
.config = {115200, DATA_WIDTH_8BIT, NO_PARITY, STOP_BITS_1, FLOW_CONTROL_DISABLED}, /* uart config */
|
||||
.priv = NULL /* priv data */
|
||||
};
|
||||
/**
|
||||
* Initialises a UART interface
|
||||
*
|
||||
*
|
||||
* @param[in] uart the interface which should be initialised
|
||||
*
|
||||
* @return 0 : on success, EIO : if an error occurred with any step
|
||||
*/
|
||||
int32_t hal_uart_init(uart_dev_t *uart)
|
||||
{
|
||||
usart_config_t config = {0};
|
||||
status_t status;
|
||||
|
||||
config.baudRate_Bps = uart->config.baud_rate;
|
||||
config.enableRx = true;
|
||||
config.enableTx = true;
|
||||
config.loopback = false;
|
||||
config.fifoConfig.enableTxFifo = false;
|
||||
config.fifoConfig.enableRxFifo = false;
|
||||
|
||||
switch(uart->config.parity)
|
||||
{
|
||||
case NO_PARITY:
|
||||
config.parityMode = kUSART_ParityDisabled;
|
||||
break;
|
||||
case ODD_PARITY:
|
||||
config.parityMode = kUSART_ParityOdd;
|
||||
break;
|
||||
case EVEN_PARITY:
|
||||
config.parityMode = kUSART_ParityEven;
|
||||
break;
|
||||
default:
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
switch(uart->config.data_width)
|
||||
{
|
||||
case DATA_WIDTH_7BIT:
|
||||
config.bitCountPerChar = kUSART_7BitsPerChar;
|
||||
break;
|
||||
case DATA_WIDTH_8BIT:
|
||||
config.bitCountPerChar = kUSART_8BitsPerChar;
|
||||
break;
|
||||
default:
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
switch(uart->config.stop_bits)
|
||||
{
|
||||
case STOP_BITS_1:
|
||||
config.stopBitCount = kUSART_OneStopBit;
|
||||
break;
|
||||
case STOP_BITS_2:
|
||||
config.stopBitCount = kUSART_TwoStopBit;
|
||||
break;
|
||||
default:
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
status = USART_Init((USART_Type *)s_uartBaseAddrs[uart->port], &config, CLOCK_GetFreq(kCLOCK_Usart));
|
||||
|
||||
if(kStatus_Success != status)
|
||||
return -EIO;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Transmit data on a UART interface
|
||||
*
|
||||
* @param[in] uart the UART interface
|
||||
* @param[in] data pointer to the start of data
|
||||
* @param[in] size number of bytes to transmit
|
||||
*
|
||||
* @return 0 : on success, EIO : if an error occurred with any step
|
||||
*/
|
||||
int32_t hal_uart_send(uart_dev_t *uart, const void *data, uint32_t size, uint32_t timeout)
|
||||
{
|
||||
USART_WriteBlocking((USART_Type *)s_uartBaseAddrs[uart->port], data, size);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Receive data on a UART interface
|
||||
*
|
||||
* @param[in] uart the UART interface
|
||||
* @param[out] data pointer to the buffer which will store incoming data
|
||||
* @param[in] expect_size number of bytes to receive
|
||||
* @param[out] recv_size number of bytes received
|
||||
* @param[in] timeout timeout in milisecond
|
||||
*
|
||||
* @return 0 : on success, EIO : if an error occurred with any step
|
||||
*/
|
||||
int32_t hal_uart_recv_II(uart_dev_t *uart, void *data, uint32_t expect_size, uint32_t *recv_size, uint32_t timeout)
|
||||
{
|
||||
USART_Type *base = (USART_Type *)s_uartBaseAddrs[uart->port];
|
||||
uint8_t *data8 = (uint8_t *)data;
|
||||
uint32_t status;
|
||||
uint32_t count = 0;
|
||||
uint32_t instance = 0U;
|
||||
|
||||
if(recv_size != NULL)
|
||||
*recv_size = 0;
|
||||
|
||||
instance = USART_GetInstance(base);
|
||||
|
||||
for (; expect_size > 0; expect_size--)
|
||||
{
|
||||
if (USART_IsRxFifoEnable(base))
|
||||
{
|
||||
if((VFIFO->USART[instance].STATUSART & VFIFO_USART_STATUSART_RXEMPTY_MASK))
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
status = VFIFO->USART[instance].STATUSART;
|
||||
if (status & VFIFO_USART_STATUSART_BUSERR_MASK)
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
status = VFIFO->USART[instance].RXDATSTATUSART;
|
||||
if (status & VFIFO_USART_RXDATSTATUSART_FRAMERR_MASK)
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
if (status & VFIFO_USART_RXDATSTATUSART_PARITYERR_MASK)
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
if (status & VFIFO_USART_RXDATSTATUSART_RXNOISE_MASK)
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
*data8 = (status & VFIFO_USART_RXDATSTATUSART_RXDAT_MASK);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (!(base->STAT & USART_STAT_RXRDY_MASK))
|
||||
{
|
||||
return -EIO;
|
||||
}
|
||||
/* Check receive status */
|
||||
status = base->STAT;
|
||||
|
||||
if (status & USART_STAT_FRAMERRINT_MASK)
|
||||
{
|
||||
base->STAT |= USART_STAT_FRAMERRINT_MASK;
|
||||
return -EIO;
|
||||
}
|
||||
if (status & USART_STAT_PARITYERRINT_MASK)
|
||||
{
|
||||
base->STAT |= USART_STAT_PARITYERRINT_MASK;
|
||||
return -EIO;
|
||||
}
|
||||
if (status & USART_STAT_RXNOISEINT_MASK)
|
||||
{
|
||||
base->STAT |= USART_STAT_RXNOISEINT_MASK;
|
||||
return -EIO;
|
||||
}
|
||||
if (base->STAT & USART_STAT_OVERRUNINT_MASK)
|
||||
{
|
||||
base->STAT |= USART_STAT_OVERRUNINT_MASK;
|
||||
return -EIO;
|
||||
}
|
||||
*data8 = base->RXDAT;
|
||||
}
|
||||
data8++;
|
||||
count++;
|
||||
if(recv_size != NULL)
|
||||
*recv_size = count;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Deinitialises a UART interface
|
||||
*
|
||||
* @param[in] uart the interface which should be deinitialised
|
||||
*
|
||||
* @return 0 : on success, EIO : if an error occurred with any step
|
||||
*/
|
||||
int32_t hal_uart_finalize(uart_dev_t *uart)
|
||||
{
|
||||
USART_Deinit((USART_Type *)s_uartBaseAddrs[uart->port]);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
587
Living_SDK/platform/mcu/lpc54102/hal/hal_wifi_wmi.c
Normal file
587
Living_SDK/platform/mcu/lpc54102/hal/hal_wifi_wmi.c
Normal file
|
|
@ -0,0 +1,587 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* POSIX getopt for Windows
|
||||
* Code given out at the 1985 UNIFORUM conference in Dallas.
|
||||
*
|
||||
* From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985
|
||||
* Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET
|
||||
* Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP
|
||||
* Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix
|
||||
* From: std-unix@ut-sally.UUCP (Moderator, John Quarterman)
|
||||
* Newsgroups: mod.std.unix
|
||||
* Subject: public domain AT&T getopt source
|
||||
* Message-ID: <3352@ut-sally.UUCP>
|
||||
* Date: 3 Nov 85 19:34:15 GMT
|
||||
* Date-Received: 4 Nov 85 12:25:09 GMT
|
||||
* Organization: IEEE/P1003 Portable Operating System Environment Committee
|
||||
* Lines: 91
|
||||
* Approved: jsq@ut-sally.UUC
|
||||
* Here's something you've all been waiting for: the AT&T public domain
|
||||
* source for getopt(3). It is the code which was given out at the 1985
|
||||
* UNIFORUM conference in Dallas. I obtained it by electronic mail
|
||||
* directly from AT&T. The people there assure me that it is indeed
|
||||
* in the public domain
|
||||
* There is no manual page. That is because the one they gave out at
|
||||
* UNIFORUM was slightly different from the current System V Release 2
|
||||
* manual page. The difference apparently involved a note about the
|
||||
* famous rules 5 and 6, recommending using white space between an option
|
||||
* and its first argument, and not grouping options that have arguments.
|
||||
* Getopt itself is currently lenient about both of these things White
|
||||
* space is allowed, but not mandatory, and the last option in a group can
|
||||
* have an argument. That particular version of the man page evidently
|
||||
* has no official existence, and my source at AT&T did not send a copy.
|
||||
* The current SVR2 man page reflects the actual behavor of this getopt.
|
||||
* However, I am not about to post a copy of anything licensed by AT&T.
|
||||
*/
|
||||
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <k_api.h>
|
||||
#include "hal/wifi.h"
|
||||
#include "qcom_api.h"
|
||||
#include "fsl_debug_console.h"
|
||||
|
||||
#define WIFI_CONNECT_TIMEOUT_MS 20000 //20s
|
||||
#define WIFI_DHCP_RETRY_TIME 20
|
||||
static int8_t _traceQcomApi = 1;
|
||||
|
||||
static volatile int32_t devId = 0;
|
||||
static volatile int8_t _isConnected = 0;
|
||||
static ksem_t wifi_event_sem;
|
||||
|
||||
|
||||
#define UINT32_IPADDR_TO_CSV_BYTES(a) (((a) >> 24) & 0xFF), (((a) >> 16) & 0xFF), (((a) >> 8) & 0xFF), ((a)&0xFF)
|
||||
static void parseIPv4(char *in, uint8_t *addr)
|
||||
{
|
||||
int8_t i, j;
|
||||
for (i = 3; i >= 0; i--) {
|
||||
for (j = 0; j < 3; j++) {
|
||||
if(('0' <= in[j]) && (in[j] <= '9')) {
|
||||
addr[i] *= 10;
|
||||
addr[i] += (in[j] - 0x30);
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
in += (j + 1);
|
||||
}
|
||||
}
|
||||
|
||||
static void printError(uint32_t value, const char *funcName)
|
||||
{
|
||||
PRINTF("ERROR: %s() returned %d\r\n", funcName, value);
|
||||
}
|
||||
|
||||
static int isQcomError(A_STATUS status, const char *funcName)
|
||||
{
|
||||
if (status != A_OK)
|
||||
{
|
||||
printError(status, funcName);
|
||||
}
|
||||
else if (_traceQcomApi)
|
||||
{
|
||||
PRINTF("%s() OK\r\n", funcName);
|
||||
}
|
||||
return (status != A_OK);
|
||||
}
|
||||
|
||||
static void hal_wifi_onConnect(uint8_t event, uint8_t devId, char *bssid, uint8_t bssConn)
|
||||
{
|
||||
switch (event)
|
||||
{
|
||||
case 1:
|
||||
if (devId == 0)
|
||||
{
|
||||
PRINTF("%s connected\r\n", bssConn ? "AP" : "CLIENT");
|
||||
}
|
||||
else
|
||||
{
|
||||
PRINTF("Connected\r\n");
|
||||
}
|
||||
_isConnected = 1;
|
||||
// NOTE that station is not fully connected until PEER_FIRST_NODE_JOIN_EVENT
|
||||
krhino_sem_give(&wifi_event_sem);
|
||||
break;
|
||||
case 0:
|
||||
_isConnected = 0;
|
||||
if (devId == 0)
|
||||
{
|
||||
PRINTF("%s disconnect\r\n", bssConn ? "AP" : "CLIENT");
|
||||
}
|
||||
krhino_sem_give(&wifi_event_sem);
|
||||
break;
|
||||
case INVALID_PROFILE:
|
||||
// this event is used to indicate RSNA failure
|
||||
_isConnected = 0;
|
||||
PRINTF("4 way handshake failure for device=%d n", devId);
|
||||
break;
|
||||
case PEER_FIRST_NODE_JOIN_EVENT:
|
||||
// this event is used to RSNA success
|
||||
PRINTF("4 way handshake success for device=%d\r\n", devId);
|
||||
break;
|
||||
default:
|
||||
PRINTF("code %d\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void hal_dhcps_cb(void)
|
||||
{
|
||||
PRINTF("DHCP Setup Event\r\n");
|
||||
krhino_sem_give(&wifi_event_sem);
|
||||
}
|
||||
|
||||
|
||||
static int wifi_init(hal_wifi_module_t *m)
|
||||
{
|
||||
A_STATUS status = A_OK;
|
||||
PRINTF("WIFI_Init\r\n");
|
||||
|
||||
status = WIFISHIELD_Init();
|
||||
PRINTF("WIFISHIELD_Init return %d\r\n", status);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
status = wlan_driver_start();
|
||||
PRINTF("wlan_driver_start return %d\r\n", status);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
krhino_sem_create(&wifi_event_sem, "wifi_event_sem", 0);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static void wifi_get_mac_addr(hal_wifi_module_t *m, uint8_t *mac)
|
||||
{
|
||||
mac[0] = 0x84; mac[1] = 0x5D; mac[2] = 0xD7; mac[3] = 0x68; mac[4] = 0x3B; mac[5] = 0x91;
|
||||
PRINTF("wifi_get_mac_addr\r\n");
|
||||
}
|
||||
|
||||
|
||||
static A_STATUS wifi_start_station(hal_wifi_init_type_t *init_para)
|
||||
{
|
||||
A_STATUS status;
|
||||
QCOM_SSID q_ssid;
|
||||
QCOM_PASSPHRASE q_passphrase;
|
||||
WLAN_CRYPT_TYPE crypto_mode = WLAN_CRYPT_AES_CRYPT;
|
||||
WLAN_AUTH_MODE authen_mode = WLAN_AUTH_WPA2_PSK;
|
||||
|
||||
// Set station mode to station (0) or AP (1)
|
||||
status = qcom_op_set_mode(devId, QCOM_WLAN_DEV_MODE_STATION);
|
||||
if(isQcomError(status, "qcom_op_set_mode"))
|
||||
return status;
|
||||
|
||||
memcpy(q_ssid.ssid, init_para->wifi_ssid, 33);
|
||||
// NOTE: qcom API requires to first set a valid SSID (before auth, cipher and passphrase)
|
||||
status = qcom_set_ssid(devId, &q_ssid);
|
||||
if(isQcomError(status, "qcom_set_ssid"))
|
||||
return status;
|
||||
|
||||
status = qcom_sec_set_encrypt_mode(devId, crypto_mode);
|
||||
if(isQcomError(status, "qcom_sec_set_encrypt_mode"))
|
||||
return status;
|
||||
|
||||
// Note that only 4 of all modes listed in QCA 80-Y9106-1 are supported!
|
||||
// The modes are: WLAN_AUTH_NONE, WLAN_AUTH_WPA_PSK, WLAN_AUTH_WPA2_PSK, WLAN_AUTH_WEP
|
||||
status = qcom_sec_set_auth_mode(devId, WLAN_AUTH_WPA2_PSK);
|
||||
if(isQcomError(status, "qcom_sec_set_auth_mode"))
|
||||
return status;
|
||||
|
||||
memcpy(q_passphrase.passphrase, init_para->wifi_key, 65);
|
||||
// NOTE: The driver insists that the SSID is configured *before* the passphrase
|
||||
status = qcom_sec_set_passphrase(devId, &q_passphrase);
|
||||
if(isQcomError(status, "qcom_sec_set_passphrase"))
|
||||
return status;
|
||||
|
||||
// The connect callback is actually used for four different callbacks:
|
||||
// onConnect(1 (TRUE), uint8_t devId, uint8_t *ssid, uint8_t bssMac[6]);
|
||||
// onDisconnect(status, uint8_t devId, uint8_t *ssid, uint8_t bssMac[6]);
|
||||
// where status = 0x10 (INVALID_PROFILE) on ?
|
||||
// = 0 on normal disconnect
|
||||
// onRSNASuccessEvent(uint8_t code, uint8_t devId, NULL, 0)
|
||||
// onBitRateEvent_tx(wmi_rateTable[rateIndex][0], devId, NULL, 0);
|
||||
// It is not possible to discern the onBitRateEvent_tx event from the others
|
||||
status = qcom_set_connect_callback(devId, (void *)hal_wifi_onConnect);
|
||||
if(isQcomError(status, "qcom_set_connect_callback"))
|
||||
return status;
|
||||
|
||||
status = qcom_commit(devId);
|
||||
isQcomError(status, "qcom_commit");
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static A_STATUS wifi_start_softAP(hal_wifi_init_type_t *init_para)
|
||||
{
|
||||
A_STATUS status = A_OK;
|
||||
uint32_t ap_addr = 0;
|
||||
uint32_t ap_mask = 0;
|
||||
uint32_t ap_gateway = 0;
|
||||
|
||||
status = qcom_op_set_mode(devId, QCOM_WLAN_DEV_MODE_AP);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Set SSID */
|
||||
status = qcom_set_ssid(devId, (QCOM_SSID*)"HomeWifi");
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Set encryption mode */
|
||||
status = qcom_sec_set_encrypt_mode(devId, WLAN_CRYPT_NONE);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Set auth mode */
|
||||
status = qcom_sec_set_auth_mode(devId, WLAN_AUTH_NONE);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Set password */
|
||||
status = qcom_sec_set_passphrase(devId, (QCOM_PASSPHRASE*)"");
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
status = qcom_set_connect_callback(devId, (void *)hal_wifi_onConnect);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
status = qcom_commit(devId);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
parseIPv4(init_para->local_ip_addr, &ap_addr);
|
||||
parseIPv4(init_para->net_mask, &ap_mask);
|
||||
parseIPv4(init_para->gateway_ip_addr, &ap_gateway);
|
||||
|
||||
PRINTF("Configure AP IP:0x%x, MASK:0x%x, GW:0x%x\r\n", ap_addr, ap_mask, ap_gateway);
|
||||
status = qcom_ipconfig(devId, QCOM_IPCONFIG_STATIC, &ap_addr, &ap_mask, &ap_gateway);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
return A_OK;
|
||||
}
|
||||
|
||||
static int wifi_get_ip_stat(hal_wifi_module_t *m, hal_wifi_ip_stat_t *out_net_para, hal_wifi_type_t wifi_type);
|
||||
static int wifi_start(hal_wifi_module_t *m, hal_wifi_init_type_t *init_para)
|
||||
{
|
||||
A_STATUS status;
|
||||
uint32_t retry = 0;
|
||||
kstat_t wifi_sem_state;
|
||||
uint32_t q_addr = 0, q_mask = 0, q_gateway = 0;
|
||||
uint32_t dnsServers[3];
|
||||
uint32_t dnsnum = 0;
|
||||
hal_wifi_ip_stat_t ip_stat;
|
||||
|
||||
PRINTF("wifi_start parameter: Mode - %d\r\n", init_para->wifi_mode);
|
||||
PRINTF("wifi_start parameter: SSID - %s\r\n", init_para->wifi_ssid);
|
||||
PRINTF("wifi_start parameter: PASSWORD - %s\r\n", init_para->wifi_key);
|
||||
|
||||
if(init_para->wifi_mode == STATION)
|
||||
{
|
||||
status = wifi_start_station(init_para);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
|
||||
wifi_sem_state = krhino_sem_take(&wifi_event_sem, krhino_ms_to_ticks(WIFI_CONNECT_TIMEOUT_MS));
|
||||
if (!((RHINO_SUCCESS == wifi_sem_state) && _isConnected)) {
|
||||
PRINTF("krhino_sem_take state = %d, isConnected = %d\r\n", wifi_sem_state, _isConnected);
|
||||
return A_TIMEOUT;
|
||||
}
|
||||
|
||||
if (init_para->dhcp_mode == DHCP_DISABLE) {
|
||||
parseIPv4(init_para->local_ip_addr, &q_addr);
|
||||
parseIPv4(init_para->net_mask, &q_mask);
|
||||
parseIPv4(init_para->gateway_ip_addr, &q_gateway);
|
||||
}
|
||||
do {
|
||||
if (init_para->dhcp_mode == DHCP_CLIENT) {
|
||||
status = qcom_ipconfig(devId, QCOM_IPCONFIG_DHCP, &q_addr, &q_mask, &q_gateway);
|
||||
} else if (init_para->dhcp_mode == DHCP_DISABLE) {
|
||||
status = qcom_ipconfig(devId, QCOM_IPCONFIG_STATIC, &q_addr, &q_mask, &q_gateway);
|
||||
}
|
||||
A_MDELAY(50);
|
||||
q_addr = q_mask = q_gateway = 0;
|
||||
status = qcom_ipconfig(devId, QCOM_IPCONFIG_QUERY, &q_addr, &q_mask, &q_gateway);
|
||||
if (q_addr != 0)
|
||||
break;
|
||||
} while(retry < WIFI_DHCP_RETRY_TIME);
|
||||
|
||||
if (init_para->dhcp_mode == DHCP_CLIENT)
|
||||
{
|
||||
sprintf(init_para->local_ip_addr,"%d.%d.%d.%d", UINT32_IPADDR_TO_CSV_BYTES(q_addr));
|
||||
sprintf(init_para->net_mask,"%d.%d.%d.%d", UINT32_IPADDR_TO_CSV_BYTES(q_mask));
|
||||
sprintf(init_para->gateway_ip_addr,"%d.%d.%d.%d", UINT32_IPADDR_TO_CSV_BYTES(q_gateway));
|
||||
init_para->local_ip_addr[15] = 0;
|
||||
init_para->net_mask[15] = 0;
|
||||
init_para->gateway_ip_addr[15] = 0;
|
||||
}
|
||||
|
||||
PRINTF("IP: %d.%d.%d.%d\r\n", UINT32_IPADDR_TO_CSV_BYTES(q_addr));
|
||||
PRINTF("GATEWAY: %d.%d.%d.%d\r\n",UINT32_IPADDR_TO_CSV_BYTES(q_gateway));
|
||||
PRINTF("MASK: %d.%d.%d.%d\r\n", UINT32_IPADDR_TO_CSV_BYTES(q_mask));
|
||||
|
||||
status = qcom_dns_server_address_get(dnsServers, &dnsnum);
|
||||
if (isQcomError(status, "qcom_dns_server_address_get"))
|
||||
{
|
||||
PRINTF("WARNING: No DNS servers returned by DHCP\r\n");
|
||||
PRINTF(" You will NOT be able to resolve domain names\r\n");
|
||||
return status;
|
||||
}
|
||||
|
||||
for (int i = 0; i < dnsnum; i++)
|
||||
{
|
||||
PRINTF("DNS %d: %d.%d.%d.%d\r\n", i, UINT32_IPADDR_TO_CSV_BYTES(dnsServers[i]));
|
||||
}
|
||||
}
|
||||
else /* WIFI Mode SOFT_AP */
|
||||
{
|
||||
status = wifi_start_softAP(init_para);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
wifi_sem_state = krhino_sem_take(&wifi_event_sem, krhino_ms_to_ticks(WIFI_CONNECT_TIMEOUT_MS));
|
||||
if (!((RHINO_SUCCESS == wifi_sem_state) && _isConnected)) {
|
||||
return A_TIMEOUT;
|
||||
}
|
||||
#define WIFI_SOFTAP_DHCP_BEGIN 0xc0a80164 //192.168.1.100
|
||||
#define WIFI_SOFTAP_DHCP_END 0xc0a80196 //192.168.1.150
|
||||
#define WIFI_SOFTAP_DHCP_LEASE_TIME (3600)
|
||||
status = qcom_dhcps_set_pool(devId, WIFI_SOFTAP_DHCP_BEGIN, WIFI_SOFTAP_DHCP_END, WIFI_SOFTAP_DHCP_LEASE_TIME);
|
||||
if (status != A_OK) {
|
||||
return status;
|
||||
}
|
||||
qcom_dhcps_register_cb(devId, hal_dhcps_cb);
|
||||
|
||||
wifi_sem_state = krhino_sem_take(&wifi_event_sem, RHINO_WAIT_FOREVER);
|
||||
if (!(RHINO_SUCCESS == wifi_sem_state)) {
|
||||
return A_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
if (m->ev_cb && m->ev_cb->ip_got) {
|
||||
PRINTF("m->ev_cb->ip_got \r\n");
|
||||
wifi_get_ip_stat(m, &ip_stat, STATION);
|
||||
m->ev_cb->ip_got(m, &ip_stat, NULL);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
static int wifi_start_adv(hal_wifi_module_t *m,hal_wifi_init_type_adv_t *init_para_adv)
|
||||
{
|
||||
PRINTF("wifi_start_adv\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wifi_get_ip_stat(hal_wifi_module_t *m, hal_wifi_ip_stat_t *out_net_para, hal_wifi_type_t wifi_type)
|
||||
{
|
||||
uint32_t q_addr = 0, q_mask = 0, q_gateway = 0;
|
||||
A_STATUS status;
|
||||
|
||||
q_addr = q_mask = q_gateway = 0;
|
||||
status = qcom_ipconfig(devId, QCOM_IPCONFIG_QUERY, &q_addr, &q_mask, &q_gateway);
|
||||
|
||||
sprintf(out_net_para->ip,"%d.%d.%d.%d", UINT32_IPADDR_TO_CSV_BYTES(q_addr));
|
||||
sprintf(out_net_para->mask,"%d.%d.%d.%d", UINT32_IPADDR_TO_CSV_BYTES(q_mask));
|
||||
sprintf(out_net_para->gate,"%d.%d.%d.%d", UINT32_IPADDR_TO_CSV_BYTES(q_gateway));
|
||||
|
||||
PRINTF("IP %s \r\n", out_net_para->ip);
|
||||
PRINTF("GATEWAY %s\r\n", out_net_para->gate);
|
||||
PRINTF("MASK %s\r\n", out_net_para->mask);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wifi_get_link_stat(hal_wifi_module_t *m, hal_wifi_link_stat_t *out_stat)
|
||||
{
|
||||
PRINTF("wifi_get_link_stat\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void wifi_start_scan(hal_wifi_module_t *m)
|
||||
{
|
||||
A_STATUS status;
|
||||
QCOM_BSS_SCAN_INFO *scanResult;
|
||||
int16_t scanNumResults = 0;
|
||||
hal_wifi_scan_result_t scan_result;
|
||||
ap_list_t scan_list[12] = {0};
|
||||
PRINTF("wifi_start_scan\r\n");
|
||||
|
||||
status = qcom_set_scan(devId, NULL);
|
||||
isQcomError(status, "qcom_set_scan");
|
||||
|
||||
// NOTE: calling qcom_get_scan() before qcom_set_scan() is the same as suspending for 5s,
|
||||
// i.e. nothing happens for 5s where after 0 is returned
|
||||
// NOTE: A maximum of 12 results are returned
|
||||
status = qcom_get_scan(devId, &scanResult, &scanNumResults);
|
||||
isQcomError(status, "qcom_get_scan");
|
||||
|
||||
scan_result.ap_num = scanNumResults;
|
||||
scan_result.ap_list = &scan_list;
|
||||
|
||||
for (int i = 0; i < scanNumResults; i++)
|
||||
{
|
||||
QCOM_BSS_SCAN_INFO *scr = &scanResult[i];
|
||||
int ssidLen = scr->ssid_len;
|
||||
scr->ssid[ssidLen] = 0;
|
||||
|
||||
PRINTF("%2d %2d %4d %02x:%02x:%02x:%02x:%02x:%02x %s\r\n", i, scr->channel, scr->rssi, scr->bssid[0],
|
||||
scr->bssid[1], scr->bssid[2], scr->bssid[3], scr->bssid[4], scr->bssid[5], scr->ssid);
|
||||
memcpy(scan_list[i].ssid, scr->ssid, scr->ssid_len);
|
||||
scan_list[i].ap_power = scr->preamble;
|
||||
}
|
||||
|
||||
if (m->ev_cb && m->ev_cb->scan_compeleted) {
|
||||
PRINTF("m->ev_cb->scan_compeleted\r\n");
|
||||
m->ev_cb->scan_compeleted(m, &scan_result, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
static void wifi_start_scan_adv(hal_wifi_module_t *m)
|
||||
{
|
||||
A_STATUS status;
|
||||
QCOM_BSS_SCAN_INFO *scanResult;
|
||||
int16_t scanNumResults = 0;
|
||||
hal_wifi_scan_result_adv_t scan_adv_result;
|
||||
ap_list_adv_t scan_adv_list[12] = {0};
|
||||
|
||||
status = qcom_set_scan(devId, NULL);
|
||||
isQcomError(status, "qcom_set_scan");
|
||||
|
||||
// NOTE: calling qcom_get_scan() before qcom_set_scan() is the same as suspending for 5s,
|
||||
// i.e. nothing happens for 5s where after 0 is returned
|
||||
// NOTE: A maximum of 12 results are returned
|
||||
status = qcom_get_scan(devId, &scanResult, &scanNumResults);
|
||||
isQcomError(status, "qcom_get_scan");
|
||||
|
||||
scan_adv_result.ap_num = scanNumResults;
|
||||
scan_adv_result.ap_list = &scan_adv_list;
|
||||
|
||||
for (int i = 0; i < scanNumResults; i++)
|
||||
{
|
||||
QCOM_BSS_SCAN_INFO *scr = &scanResult[i];
|
||||
int ssidLen = scr->ssid_len;
|
||||
scr->ssid[ssidLen] = 0;
|
||||
|
||||
PRINTF("%2d %2d %4d %02x:%02x:%02x:%02x:%02x:%02x %s\r\n", i, scr->channel, scr->rssi, scr->bssid[0],
|
||||
scr->bssid[1], scr->bssid[2], scr->bssid[3], scr->bssid[4], scr->bssid[5], scr->ssid);
|
||||
memcpy(scan_adv_list[i].ssid, scr->ssid, scr->ssid_len);
|
||||
memcpy(scan_adv_list[i].bssid, scr->bssid, 6);
|
||||
scan_adv_list[i].ap_power = scr->preamble;
|
||||
scan_adv_list[i].channel = scr->channel;
|
||||
}
|
||||
|
||||
if (m->ev_cb && m->ev_cb->scan_adv_compeleted) {
|
||||
PRINTF("m->ev_cb->scan_adv_compeleted\r\n");
|
||||
m->ev_cb->scan_adv_compeleted(m, &scan_adv_list, NULL);
|
||||
}
|
||||
}
|
||||
|
||||
static int wifi_power_off(hal_wifi_module_t *m)
|
||||
{
|
||||
PRINTF("wifi_power_off NOT Implemented");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wifi_power_on(hal_wifi_module_t *m)
|
||||
{
|
||||
PRINTF("wifi_power_on NOT Implemented");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wifi_suspend(hal_wifi_module_t *m)
|
||||
{
|
||||
PRINTF("wifi_suspend NOT Implemented");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wifi_suspend_station(hal_wifi_module_t *m)
|
||||
{
|
||||
PRINTF("wifi_suspend_station NOT Implemented");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wifi_suspend_soft_ap(hal_wifi_module_t *m)
|
||||
{
|
||||
PRINTF("wifi_suspend_soft_ap NOT Implemented");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int wifi_set_channel(hal_wifi_module_t *m, int ch)
|
||||
{
|
||||
PRINTF("wifi_set_channel NOT Implemented");
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void wifi_start_monitor(hal_wifi_module_t *m)
|
||||
{
|
||||
PRINTF("wifi_start_monitor NOT Implemented");
|
||||
}
|
||||
|
||||
static void wifi_stop_monitor(hal_wifi_module_t *m)
|
||||
{
|
||||
PRINTF("wifi_stop_monitor NOT Implemented");
|
||||
}
|
||||
|
||||
static void wifi_register_monitor_cb(hal_wifi_module_t *m, monitor_data_cb_t fn)
|
||||
{
|
||||
PRINTF("wifi_register_monitor_cb NOT Implemented");
|
||||
}
|
||||
|
||||
static void wifi_register_wlan_mgnt_monitor_cb(hal_wifi_module_t *m, monitor_data_cb_t fn)
|
||||
{
|
||||
PRINTF("wifi_register_wlan_mgnt_monitor_cb NOT Implemented");
|
||||
}
|
||||
|
||||
static int wifi_wlan_send_80211_raw_frame(hal_wifi_module_t *m, uint8_t *buf, int len)
|
||||
{
|
||||
PRINTF("wifi_wlan_send_80211_raw_frame NOT Implemented");
|
||||
return 0;
|
||||
}
|
||||
|
||||
hal_wifi_module_t qca_4002_wmi = {
|
||||
.base.name = "qca_4002_wmi",
|
||||
.ev_cb = NULL,
|
||||
.init = wifi_init,
|
||||
.get_mac_addr = wifi_get_mac_addr,
|
||||
.start = wifi_start,
|
||||
.start_adv = wifi_start_adv,
|
||||
.get_ip_stat = wifi_get_ip_stat,
|
||||
.get_link_stat = wifi_get_link_stat,
|
||||
.start_scan = wifi_start_scan,
|
||||
.start_scan_adv = wifi_start_scan_adv,
|
||||
.power_off = wifi_power_off,
|
||||
.power_on = wifi_power_on,
|
||||
.suspend = wifi_suspend,
|
||||
.suspend_station = wifi_suspend_station,
|
||||
.suspend_soft_ap = wifi_suspend_soft_ap,
|
||||
.set_channel = wifi_set_channel,
|
||||
.start_monitor = wifi_start_monitor,
|
||||
.stop_monitor = wifi_stop_monitor,
|
||||
.register_monitor_cb = wifi_register_monitor_cb,
|
||||
.register_wlan_mgnt_monitor_cb = wifi_register_wlan_mgnt_monitor_cb,
|
||||
.wlan_send_80211_raw_frame = wifi_wlan_send_80211_raw_frame
|
||||
};
|
||||
|
||||
|
||||
27
Living_SDK/platform/mcu/lpc54102/hal/hook_impl.c
Normal file
27
Living_SDK/platform/mcu/lpc54102/hal/hook_impl.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
|
||||
*/
|
||||
|
||||
#include <k_api.h>
|
||||
#include "fsl_debug_console.h"
|
||||
|
||||
void _mytrace_event_create(ktask_t *task, kevent_t *event, const name_t *name, uint32_t flags_init)
|
||||
{
|
||||
PRINTF("_mytrace_event_create TASK 0x%x, event 0x%x, name = %s, %d\r\n", task, event, name, flags_init);
|
||||
}
|
||||
void _mytrace_event_get(ktask_t *task, kevent_t *event)
|
||||
{
|
||||
PRINTF("_mytrace_event_get TASK 0x%x, event 0x%x\r\n", task, event);
|
||||
}
|
||||
void _mytrace_event_get_blk(ktask_t *task, kevent_t *event, tick_t wait_option)
|
||||
{
|
||||
PRINTF("_mytrace_event_get_blk TASK 0x%x, event 0x%x, wait_option %d\r\n", task, event, wait_option);
|
||||
}
|
||||
void _mytrace_event_task_wake(ktask_t *task, ktask_t *task_waked_up, kevent_t *event)
|
||||
{
|
||||
PRINTF("_mytrace_event_task_wake TASK 0x%x, WKTASK 0x%x, EVENT 0x%x\r\n", task, task_waked_up, event);
|
||||
}
|
||||
void _mytrace_event_del(ktask_t *task, kevent_t *event)
|
||||
{
|
||||
PRINTF("_mytrace_event_del TASK 0x%x, EVENT 0x%x\r\n", task, event);
|
||||
}
|
||||
158
Living_SDK/platform/mcu/lpc54102/lpc54102.mk
Normal file
158
Living_SDK/platform/mcu/lpc54102/lpc54102.mk
Normal file
|
|
@ -0,0 +1,158 @@
|
|||
HOST_OPENOCD := LPC54102
|
||||
NAME := lpc54102impl
|
||||
|
||||
$(NAME)_TYPE := kernel
|
||||
|
||||
$(NAME)_COMPONENTS += platform/arch/arm/armv7m
|
||||
$(NAME)_COMPONENTS += libc rhino hal netmgr framework.common mbedtls cjson cli digest_algorithm sal
|
||||
|
||||
sal ?= 1
|
||||
module ?= wifi.gt202
|
||||
|
||||
GLOBAL_CFLAGS += -DCORE_M4
|
||||
GLOBAL_CFLAGS += -fmessage-length=0
|
||||
GLOBAL_CFLAGS += -fno-builtin -ffunction-sections -fdata-sections -fno-common -std=gnu99 -nostdlib -DSDK_DEBUGCONSOLE=1
|
||||
#GLOBAL_CFLAGS += $(CPU_CFLAGS) -mlittle-endian
|
||||
GLOBAL_CFLAGS += -mcpu=cortex-m4 -mlittle-endian -mthumb -mthumb-interwork -march=armv7e-m
|
||||
|
||||
GLOBAL_CFLAGS += -DRHINO_CONFIG_TASK_STACK_CUR_CHECK=1
|
||||
GLOBAL_ASMFLAGS += -D__MULTICORE_MASTER -D__MULTICORE_M0SLAVE -DMULTICORE_MASTER_SLAVE_M0SLAVE
|
||||
|
||||
GLOBAL_INCLUDES += ../../arch/arm/armv7m/gcc/m4/
|
||||
|
||||
#GLOBAL_LDFLAGS += -mcpu=cortex-m4 -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -march=armv7e-m -mlittle-endian -mthumb-interwork -nostartfiles
|
||||
GLOBAL_LDFLAGS += -mcpu=cortex-m4 \
|
||||
-mthumb -mthumb-interwork \
|
||||
-mlittle-endian \
|
||||
-nostartfiles \
|
||||
$(CLIB_LDFLAGS_NANO_FLOAT)
|
||||
|
||||
GLOBAL_LDFLAGS += -L$(SOURCE_ROOT)platform/mcu/lpc54102/mcuxpresso
|
||||
ifeq ($(HOST_ARCH),Cortex-M4F)
|
||||
GLOBAL_LDFLAGS += -lfsl_power_cm4_hard
|
||||
else ifeq ($(HOST_ARCH),Cortex-M4)
|
||||
GLOBAL_LDFLAGS += -lfsl_power_lib_cm4
|
||||
endif
|
||||
$(NAME)_CFLAGS += -Wall -Werror -Wno-unused-variable -Wno-unused-parameter -Wno-implicit-function-declaration
|
||||
$(NAME)_CFLAGS += -Wno-type-limits -Wno-sign-compare -Wno-pointer-sign -Wno-uninitialized
|
||||
$(NAME)_CFLAGS += -Wno-return-type -Wno-unused-function -Wno-unused-but-set-variable
|
||||
$(NAME)_CFLAGS += -Wno-unused-value -Wno-strict-aliasing
|
||||
GLOBAL_CFLAGS += -Wno-format -Wno-incompatible-pointer-types
|
||||
$(NAME)_SOURCES :=
|
||||
|
||||
#$(NAME)_SOURCES += ../../arch/arm/armv7m/gcc/m4/port_c.c
|
||||
#$(NAME)_SOURCES += ../../arch/arm/armv7m/gcc/m4/port_s.S
|
||||
|
||||
$(NAME)_SOURCES += ./drivers/fsl_adc.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_clock.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_common.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_crc.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_ctimer.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_dma.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_flashiap.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_fmeas.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_gint.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_gpio.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_i2c.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_i2c_dma.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_inputmux.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_mrt.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_pint.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_power.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_reset.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_rit.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_rtc.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_sctimer.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_spi.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_spi_dma.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_usart.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_usart_dma.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_utick.c
|
||||
$(NAME)_SOURCES += ./drivers/fsl_wwdt.c
|
||||
$(NAME)_SOURCES += ./system_LPC54102_cm4.c
|
||||
$(NAME)_SOURCES += ./utilities/log/fsl_log.c
|
||||
$(NAME)_SOURCES += ./utilities/str/fsl_str.c
|
||||
$(NAME)_SOURCES += ./utilities/io/fsl_io.c
|
||||
$(NAME)_SOURCES += ./utilities/fsl_debug_console.c
|
||||
$(NAME)_SOURCES += ./mcuxpresso/startup_lpc5410x.c
|
||||
$(NAME)_SOURCES += ./hal/hal_uart.c
|
||||
$(NAME)_SOURCES += ./hal/csp_log.c
|
||||
$(NAME)_SOURCES += ./hal/hal_flash.c
|
||||
$(NAME)_SOURCES += ./hal/hal_wifi_wmi.c
|
||||
$(NAME)_SOURCES += ./hal/hal_ota.c
|
||||
$(NAME)_SOURCES += ./aos/aos.c
|
||||
$(NAME)_SOURCES += ./aos/soc_impl.c
|
||||
$(NAME)_SOURCES += ./hal/hook_impl.c
|
||||
|
||||
|
||||
GLOBAL_CFLAGS += -DA_LITTLE_ENDIAN
|
||||
|
||||
GLOBAL_INCLUDES += ./wifi_qca/common_src/include
|
||||
GLOBAL_INCLUDES += ./wifi_qca/common_src/hcd
|
||||
GLOBAL_INCLUDES += ./wifi_qca/common_src/stack_common
|
||||
GLOBAL_INCLUDES += ./wifi_qca/common_src/wmi
|
||||
GLOBAL_INCLUDES += ./wifi_qca/custom_src/include
|
||||
GLOBAL_INCLUDES += ./wifi_qca/custom_src/stack_custom
|
||||
GLOBAL_INCLUDES += ./wifi_qca/port/boards/lpcxpresso54102/alios/gt202
|
||||
GLOBAL_INCLUDES += ./wifi_qca/port/boards/lpcxpresso54102/alios
|
||||
GLOBAL_INCLUDES += ./wifi_qca/port/drivers/spi_alios
|
||||
GLOBAL_INCLUDES += ./wifi_qca/port/shields
|
||||
GLOBAL_INCLUDES += ./wifi_qca/port/env/alios
|
||||
GLOBAL_INCLUDES += ./wifi_qca/port
|
||||
GLOBAL_INCLUDES += ./wifi_qca/include
|
||||
GLOBAL_INCLUDES += ./wifi_qca/include/AR6002/hw2.0/hw
|
||||
GLOBAL_INCLUDES += ./wifi_qca/include/AR6002
|
||||
GLOBAL_INCLUDES += ./wifi_qca
|
||||
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/api_interface/api_init.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/api_interface/api_ioctl.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/api_interface/api_txrx.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/api_interface/api_wmi_rx.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/bmi/bmi.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/driver/driver_diag.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/driver/driver_init.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/driver/driver_main.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/driver/driver_netbuf.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/driver/driver_txrx.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/htc/htc.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/hcd/spi_hcd.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/hw_interface/hw_api.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/stack_common/api_stack_offload.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/qapi/qcom_api.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/qapi/qcom_legacy.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/reorder/rcv_aggr.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/storerecall/dset_api.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/storerecall/dset.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/storerecall/storerecall.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/util/util.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/common_src/wmi/wmi.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/custom_src/api_interface/cust_api_init.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/custom_src/api_interface/cust_api_ioctl.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/custom_src/api_interface/cust_api_txrx.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/custom_src/api_interface/cust_api_wmi_rx.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/custom_src/driver/cust_driver_main.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/custom_src/driver/cust_driver_netbuf.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/custom_src/hw_interface/cust_spi_hcd.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/custom_src/qapi/custom_qcom_api.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/custom_src/stack_custom/cust_api_stack_offload.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/custom_src/stack_custom/cust_api_stack_txrx.c
|
||||
|
||||
$(NAME)_SOURCES += ./wifi_qca/port/boards/lpcxpresso54102/alios/wifi_shield.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/port/boards/lpcxpresso54102/alios/wlan_qca400x.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/port/env/alios/wifi_env.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/port/drivers/spi_alios/wifi_spi.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/port/drivers/spi_alios/wifi_driver_main.c
|
||||
$(NAME)_SOURCES += ./wifi_qca/port/pin_mux.c
|
||||
|
||||
|
||||
|
||||
ifndef OVERRIDE_LD_FILE
|
||||
GLOBAL_LDFLAGS += -T platform/mcu/lpc54102/lpc54102_flash_96K.ld
|
||||
endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
194
Living_SDK/platform/mcu/lpc54102/lpc54102_flash_96K.ld
Normal file
194
Living_SDK/platform/mcu/lpc54102/lpc54102_flash_96K.ld
Normal file
|
|
@ -0,0 +1,194 @@
|
|||
/*
|
||||
* GENERATED FILE - DO NOT EDIT
|
||||
* (c) Code Red Technologies Ltd, 2008-2013
|
||||
* (c) NXP Semiconductors 2013-2017
|
||||
* Generated linker script file for LPC54102J512
|
||||
* Created from linkscript.ldt by FMCreateLinkLibraries
|
||||
* Using Freemarker v2.3.23
|
||||
* MCUXpresso IDE Debug Build on Oct 16, 2017 4:42:58 PM
|
||||
*/
|
||||
|
||||
GROUP (
|
||||
libgcc.a
|
||||
libc.a
|
||||
libg.a
|
||||
libm.a
|
||||
libnosys.a
|
||||
)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Define each memory region */
|
||||
PROGRAM_FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
|
||||
SRAM0 (rwx) : ORIGIN = 0x2000000, LENGTH = 0x18000 /* 96K bytes (alias RAM) */
|
||||
SRAM2 (rwx) : ORIGIN = 0x3400000, LENGTH = 0x2000 /* 8K bytes (alias RAM3) */
|
||||
}
|
||||
|
||||
/* Define a symbol for the top of each memory region */
|
||||
__base_PROGRAM_FLASH = 0x0 ; /* PROGRAM_FLASH */
|
||||
__base_Flash = 0x0 ; /* Flash */
|
||||
__top_PROGRAM_FLASH = 0x0 + 0x80000 ; /* 512K bytes */
|
||||
__top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
|
||||
__base_SRAM0 = 0x2000000 ; /* SRAM0 */
|
||||
__top_SRAM0 = 0x2000000 + 0x18000 ; /* 96K bytes */
|
||||
__base_SRAM2 = 0x3400000 ; /* SRAM2 */
|
||||
__top_SRAM2 = 0x3400000 + 0x2000 ; /* 8K bytes */
|
||||
|
||||
ENTRY(ResetISR)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* MAIN TEXT SECTION */
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
__vectors_start__ = ABSOLUTE(.) ;
|
||||
KEEP(*(.isr_vector))
|
||||
/* Global Section Table */
|
||||
. = ALIGN(4) ;
|
||||
__section_table_start = .;
|
||||
__data_section_table = .;
|
||||
LONG(LOADADDR(.data));
|
||||
LONG( ADDR(.data));
|
||||
LONG( SIZEOF(.data));
|
||||
LONG(LOADADDR(.data_RAM3));
|
||||
LONG( ADDR(.data_RAM3));
|
||||
LONG( SIZEOF(.data_RAM3));
|
||||
__data_section_table_end = .;
|
||||
__bss_section_table = .;
|
||||
LONG( ADDR(.bss));
|
||||
LONG( SIZEOF(.bss));
|
||||
LONG( ADDR(.bss_RAM3));
|
||||
LONG( SIZEOF(.bss_RAM3));
|
||||
__bss_section_table_end = .;
|
||||
__section_table_end = . ;
|
||||
/* End of Global Section Table */
|
||||
|
||||
*(.after_vectors*)
|
||||
|
||||
|
||||
|
||||
} >PROGRAM_FLASH
|
||||
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
*(.text*)
|
||||
*(.rodata .rodata.* .constdata .constdata.*)
|
||||
. = ALIGN(4);
|
||||
} > PROGRAM_FLASH
|
||||
/*
|
||||
* for exception handling/unwind - some Newlib functions (in common
|
||||
* with C++ and STDC++) use this.
|
||||
*/
|
||||
.ARM.extab : ALIGN(4)
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > PROGRAM_FLASH
|
||||
__exidx_start = .;
|
||||
|
||||
.ARM.exidx : ALIGN(4)
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > PROGRAM_FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
_etext = .;
|
||||
|
||||
/* DATA section for SRAM2 */
|
||||
.data_RAM3 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
PROVIDE(__start_data_RAM3 = .) ;
|
||||
*(.ramfunc.$RAM3)
|
||||
*(.ramfunc.$SRAM2)
|
||||
*(.data.$RAM3*)
|
||||
*(.data.$SRAM2*)
|
||||
. = ALIGN(4) ;
|
||||
PROVIDE(__end_data_RAM3 = .) ;
|
||||
} > SRAM2 AT>PROGRAM_FLASH
|
||||
|
||||
/* MAIN DATA SECTION */
|
||||
.uninit_RESERVED : ALIGN(4)
|
||||
{
|
||||
KEEP(*(.bss.$RESERVED*))
|
||||
. = ALIGN(4) ;
|
||||
_end_uninit_RESERVED = .;
|
||||
} > SRAM0
|
||||
/* Main DATA section (SRAM0) */
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
_data = . ;
|
||||
*(vtable)
|
||||
*(.ramfunc*)
|
||||
*(.data*)
|
||||
. = ALIGN(4) ;
|
||||
_edata = . ;
|
||||
} > SRAM0 AT>PROGRAM_FLASH
|
||||
/* BSS section for SRAM2 */
|
||||
.bss_RAM3 : ALIGN(4)
|
||||
{
|
||||
PROVIDE(__start_bss_RAM3 = .) ;
|
||||
*(.bss.$RAM3*)
|
||||
*(.bss.$SRAM2*)
|
||||
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||
PROVIDE(__end_bss_RAM3 = .) ;
|
||||
} > SRAM2
|
||||
/* MAIN BSS SECTION */
|
||||
.bss : ALIGN(4)
|
||||
{
|
||||
_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4) ;
|
||||
_ebss = .;
|
||||
PROVIDE(end = .);
|
||||
} > SRAM0
|
||||
/* NOINIT section for SRAM2 */
|
||||
.noinit_RAM3 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM3*)
|
||||
*(.noinit.$SRAM2*)
|
||||
. = ALIGN(4) ;
|
||||
} > SRAM2
|
||||
/* DEFAULT NOINIT SECTION */
|
||||
.noinit (NOLOAD): ALIGN(4)
|
||||
{
|
||||
_noinit = .;
|
||||
*(.noinit*)
|
||||
. = ALIGN(4) ;
|
||||
_end_noinit = .;
|
||||
} > SRAM0
|
||||
.heap : ALIGN(4)
|
||||
{
|
||||
PROVIDE(_pvHeapStart = .);
|
||||
. += 0xE800;
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_pvHeapLimit = .);
|
||||
} > SRAM0
|
||||
/*
|
||||
.heap2stackfill :
|
||||
{
|
||||
. += 0x1000;
|
||||
} > SRAM2
|
||||
*/
|
||||
.stack ORIGIN(SRAM2) : ALIGN(4)
|
||||
{
|
||||
_vStackBase = .;
|
||||
. = ALIGN(4);
|
||||
. += 0x800;
|
||||
_vStackTop = .;
|
||||
_vHeap2Base = .;
|
||||
. += 0x1800;
|
||||
} > SRAM2
|
||||
|
||||
/* ## Create checksum value (used in startup) ## */
|
||||
|
||||
PROVIDE(__valid_user_code_checksum = 0 -
|
||||
(_vStackTop
|
||||
+ (ResetISR + 1)
|
||||
+ (( DEFINED(NMI_Handler) ? NMI_Handler : M0_NMI_Handler ) + 1)
|
||||
+ (( DEFINED(HardFault_Handler) ? HardFault_Handler : M0_HardFault_Handler ) + 1)
|
||||
)
|
||||
);
|
||||
}
|
||||
BIN
Living_SDK/platform/mcu/lpc54102/mcuxpresso/LPC5410x_256K.cfx
Normal file
BIN
Living_SDK/platform/mcu/lpc54102/mcuxpresso/LPC5410x_256K.cfx
Normal file
Binary file not shown.
BIN
Living_SDK/platform/mcu/lpc54102/mcuxpresso/LPC5410x_512K.cfx
Normal file
BIN
Living_SDK/platform/mcu/lpc54102/mcuxpresso/LPC5410x_512K.cfx
Normal file
Binary file not shown.
85
Living_SDK/platform/mcu/lpc54102/mcuxpresso/NXP/crp.h
Normal file
85
Living_SDK/platform/mcu/lpc54102/mcuxpresso/NXP/crp.h
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
/****************************************************************************
|
||||
* Description:
|
||||
* Code Read Protection macros
|
||||
****************************************************************************
|
||||
* Software that is described herein is for illustrative purposes only
|
||||
* which provides customers with programming information regarding the
|
||||
* products. This software is supplied "AS IS" without any warranties.
|
||||
* NXP Semiconductors assumes no responsibility or liability for the
|
||||
* use of the software, conveys no license or title under any patent,
|
||||
* copyright, or mask work right to the product. NXP Semiconductors
|
||||
* reserves the right to make changes in the software without
|
||||
* notification. NXP Semiconductors also make no representation or
|
||||
* warranty that such application will be suitable for the specified
|
||||
* use without further testing or modification.
|
||||
****************************************************************************/
|
||||
#ifndef _CRP_H_INCLUDED_
|
||||
#define _CRP_H_INCLUDED_
|
||||
|
||||
// A macro for placing data into the Code Read Protect (CRP) section,
|
||||
// which is then located at the correct address for the selected MCU
|
||||
// by the automatically generated linker script. The CRP section should
|
||||
// contain a single 32-bit value which is the CRP value. See appropriate
|
||||
// documentation for the MCU to determine CRP values.
|
||||
//
|
||||
// This feature is only available for NXP MCU targets with the Code Read
|
||||
// Protect Feature
|
||||
//
|
||||
// Example:
|
||||
// __CRP const uint32_t CRP_WORD = CRP_NO_CRP ;
|
||||
//
|
||||
#define __CRP __attribute__ ((used,section(".crp")))
|
||||
|
||||
#define CRP_NO_CRP 0xFFFFFFFF
|
||||
|
||||
// Disables UART and USB In System Programming (reads and writes)
|
||||
// Leaves SWD debugging, with reads and writes, enabled
|
||||
#define CRP_NO_ISP 0x4E697370
|
||||
|
||||
// Disables SWD debugging & JTAG, leaves ISP with with reads and writes enabled
|
||||
// You will need UART connectivity and FlashMagic (flashmagictool.com) to reverse
|
||||
// this. Don't even try this without these tools; most likely the SWD flash
|
||||
// programming will not even complete.
|
||||
// Allows reads and writes only to RAM above 0x10000300 and flash other than
|
||||
// sector 0 (the first 4 kB). Full erase also allowed- again only through UART
|
||||
// and FlashMagic (NO JTAG/SWD)
|
||||
#define CRP_CRP1 0x12345678
|
||||
|
||||
// Disables SWD debugging & JTAG, leaves UART ISP with with only full erase
|
||||
// enabled. You must have UART access and FlashMagic before setting this
|
||||
// option.
|
||||
// Don't even try this without these tools; most likely the SWD flash
|
||||
// programming will not even complete.
|
||||
#define CRP_CRP2 0x87654321
|
||||
|
||||
/************************************************************/
|
||||
/**** DANGER CRP3 WILL LOCK PART TO ALL READS and WRITES ****/
|
||||
#define CRP_CRP3_CONSUME_PART 0x43218765
|
||||
/************************************************************/
|
||||
|
||||
#if CONFIG_CRP_SETTING_NO_CRP == 1
|
||||
#define CURRENT_CRP_SETTING CRP_NO_CRP
|
||||
#endif
|
||||
|
||||
#if CONFIG_CRP_SETTING_NOISP == 1
|
||||
#define CURRENT_CRP_SETTING CRP_NO_ISP
|
||||
#endif
|
||||
|
||||
#if CONFIG_CRP_SETTING_CRP1 == 1
|
||||
#define CURRENT_CRP_SETTING CRP_CRP1
|
||||
#endif
|
||||
|
||||
#if CONFIG_CRP_SETTING_CRP2 == 1
|
||||
#define CURRENT_CRP_SETTING CRP_CRP2
|
||||
#endif
|
||||
|
||||
#if CONFIG_CRP_SETTING_CRP3_CONSUME_PART == 1
|
||||
#define CURRENT_CRP_SETTING CRP_CRP3_CONSUME_PART
|
||||
#endif
|
||||
|
||||
#ifndef CURRENT_CRP_SETTING
|
||||
#define CURRENT_CRP_SETTING CRP_NO_CRP
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _CRP_H_INCLUDED_ */
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright (c) 2016 - 2017 , NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#if defined(__MULTICORE_MASTER_SLAVE_M0SLAVE) || defined(__MULTICORE_MASTER_SLAVE_M4SLAVE)
|
||||
#if defined(__USE_LPCOPEN)
|
||||
#include "chip.h"
|
||||
#else
|
||||
#include <stdint.h>
|
||||
#define SYSCON_BASE ((uint32_t)0x40000000)
|
||||
#if defined(__LPC5410X__)
|
||||
#define CPBOOT (((volatile uint32_t *)(SYSCON_BASE + 0x304)))
|
||||
#define CPSTACK (((volatile uint32_t *)(SYSCON_BASE + 0x308)))
|
||||
#define CPUCTRL (((volatile uint32_t *)(SYSCON_BASE + 0x300)))
|
||||
#elif defined(__LPC5411X__)
|
||||
#define CPBOOT (((volatile uint32_t *)(SYSCON_BASE + 0x804)))
|
||||
#define CPSTACK (((volatile uint32_t *)(SYSCON_BASE + 0x808)))
|
||||
#define CPUCTRL (((volatile uint32_t *)(SYSCON_BASE + 0x800)))
|
||||
#else
|
||||
#error Unrecognised MCU - cannot resolve Dual-CPU related registers
|
||||
#endif
|
||||
#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16))
|
||||
#define CM4_CLK_ENA (1 << 2)
|
||||
#define CM0_CLK_ENA (1 << 3)
|
||||
#define CM4_RESET_ENA (1 << 4)
|
||||
#define CM0_RESET_ENA (1 << 5)
|
||||
#define CM4_SLEEPCON (1 << 6)
|
||||
|
||||
#if defined(CORE_M4)
|
||||
void Chip_CPU_CM0Boot(uint32_t *coentry, uint32_t *costackptr)
|
||||
{
|
||||
volatile uint32_t *u32REG, u32Val;
|
||||
|
||||
*CPSTACK = (uint32_t)costackptr;
|
||||
*CPBOOT = (uint32_t)coentry;
|
||||
|
||||
u32REG = (uint32_t *)CPUCTRL;
|
||||
u32Val = *u32REG;
|
||||
|
||||
// Enable slave clock and reset
|
||||
u32Val |= (CPUCTRL_KEY | ((CM0_CLK_ENA | CM0_RESET_ENA) & 0x7F));
|
||||
*u32REG = u32Val;
|
||||
|
||||
// Clear slave reset
|
||||
u32Val &= ~CM0_RESET_ENA;
|
||||
*u32REG = u32Val;
|
||||
}
|
||||
#else // !defined CORE_M4
|
||||
void Chip_CPU_CM4Boot(uint32_t *coentry, uint32_t *costackptr)
|
||||
{
|
||||
volatile uint32_t *u32REG, u32Val;
|
||||
|
||||
*CPSTACK = (uint32_t)costackptr;
|
||||
*CPBOOT = (uint32_t)coentry;
|
||||
|
||||
u32REG = (uint32_t *)CPUCTRL;
|
||||
u32Val = *u32REG;
|
||||
|
||||
// Enable slave clock and reset
|
||||
u32Val |= (CPUCTRL_KEY | ((CM4_CLK_ENA | CM4_RESET_ENA) & 0x7F));
|
||||
*u32REG = u32Val;
|
||||
|
||||
// Clear slave reset
|
||||
u32Val &= ~CM0_RESET_ENA;
|
||||
*u32REG = u32Val;
|
||||
}
|
||||
#endif // defined CORE_M4
|
||||
#endif // __USE_LPCOPEN
|
||||
|
||||
#if defined(CORE_M4)
|
||||
extern uint8_t __core_m0slave_START__;
|
||||
#else
|
||||
extern uint8_t __core_m4slave_START__;
|
||||
#endif
|
||||
|
||||
void boot_multicore_slave(void)
|
||||
{
|
||||
#if defined(CORE_M4)
|
||||
unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m0slave_START__;
|
||||
#else
|
||||
unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m4slave_START__;
|
||||
#endif
|
||||
|
||||
volatile unsigned int resetaddr;
|
||||
volatile unsigned int spaddr;
|
||||
spaddr = *slavevectortable_ptr;
|
||||
resetaddr = *(slavevectortable_ptr + 1);
|
||||
|
||||
#if defined(CORE_M4)
|
||||
Chip_CPU_CM0Boot((uint32_t *)resetaddr, (uint32_t *)spaddr);
|
||||
#else
|
||||
Chip_CPU_CM4Boot((uint32_t *)resetaddr, (uint32_t *)spaddr);
|
||||
#endif
|
||||
}
|
||||
#endif // defined (__MULTICORE_MASTER_SLAVE_M0SLAVE) ||
|
||||
// (__MULTICORE_MASTER_SLAVE_M4SLAVE)
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright (c) 2016 - 2017 , NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef BOOT_MULTICORE_SLAVE_H_
|
||||
#define BOOT_MULTICORE_SLAVE_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void boot_multicore_slave(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* BOOT_MULTICORE_SLAVE_H_ */
|
||||
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