rel_1.6.0 init

Living_SDK/platform/mcu/esp8266/aos/heap_private.h

@@ -0,0 +1,54 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include <stdlib.h>
+#include <stdint.h>
+
+#include "espos_spinlock.h"
+#include <soc/soc_memory_layout.h>
+#include "multi_heap.h"
+#include "rom/queue.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Some common heap registration data structures used
+   for heap_caps_init.c to share heap information with heap_caps.c
+*/
+
+/* Type for describing each registered heap */
+typedef struct heap_t_ {
+    uint32_t caps[SOC_MEMORY_TYPE_NO_PRIOS]; ///< Capabilities for the type of memory in this heap (as a prioritised set). Copied from soc_memory_types so it's in RAM not flash.
+    intptr_t start;
+    intptr_t end;
+    espos_spinlock_t heap_mux;
+    multi_heap_handle_t heap;
+    SLIST_ENTRY(heap_t_) next;
+} heap_t;
+
+/* All registered heaps.
+
+   Forms a single linked list, even though most entries are contiguous.
+   This means at the expense of 4 bytes per heap, new heaps can be
+   added at runtime in a fast & thread-safe way.
+*/
+extern SLIST_HEAD(registered_heap_ll, heap_t_) registered_heaps;
+
+bool heap_caps_match(const heap_t *heap, uint32_t caps);
+
+#ifdef __cplusplus
+}
+#endif

Living_SDK/platform/mcu/esp8266/aos/heap_wrapper.c

@@ -0,0 +1,28 @@
+#include "esp_attr.h"
+#include "k_api.h"
+
+IRAM_ATTR void *heap_caps_malloc(size_t size, uint32_t caps)
+{
+    (void)caps;
+    return krhino_mm_alloc(size);
+}
+
+IRAM_ATTR void heap_caps_free( void *ptr)
+{
+    krhino_mm_free(ptr);
+}
+
+IRAM_ATTR void *heap_caps_realloc( void *ptr, size_t size, int caps)
+{
+    return krhino_mm_realloc(ptr, size);
+}
+
+
+void heap_caps_enable_nonos_stack_heaps()
+{
+}
+
+int heap_caps_get_free_size(void)
+{
+    return 0;
+}

Living_SDK/platform/mcu/esp8266/aos/hook_impl.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2015-2017 Alibaba Group Holding Limited
+ */
+
+#include <k_api.h>
+#include "frxt/xtensa_config.h"
+#include "rec_hal.h"
+
+#define WDT_TIMEOUT_MS  20000
+void soc_hw_timer_init()
+{
+}
+
+#if (RHINO_CONFIG_USER_HOOK > 0)
+void krhino_idle_pre_hook(void)
+{
+    rec_wdt_init(WDT_TIMEOUT_MS);
+}
+
+void krhino_idle_hook(void)
+{
+    extern void vApplicationIdleHook(void);
+
+    rec_wdt_feed();
+    vApplicationIdleHook();
+}
+
+void krhino_init_hook(void)
+{
+#if (RHINO_CONFIG_HW_COUNT > 0)
+    soc_hw_timer_init();
+#endif
+}
+#endif
+
+void krhino_start_hook(void)
+{
+#if (RHINO_CONFIG_TASK_SCHED_STATS > 0)
+    krhino_task_sched_stats_reset();
+#endif
+}
+
+void krhino_task_create_hook(ktask_t *task)
+{
+#if XCHAL_CP_NUM > 0
+    krhino_task_info_set(task, 0, (void *)((uint32_t)task->task_stack + XT_STK_FRMSZ));
+#endif
+}
+
+void krhino_task_del_hook(ktask_t *task, res_free_t *arg)
+{
+}
+
+void krhino_task_switch_hook(ktask_t *orgin, ktask_t *dest)
+{
+    (void)orgin;
+    (void)dest;
+}
+
+void krhino_tick_hook(void)
+{
+}
+
+void krhino_task_abort_hook(ktask_t *task)
+{
+    (void)task;
+}
+
+void krhino_mm_alloc_hook(void *mem, size_t size)
+{
+    (void)mem;
+    (void)size;
+}
+

Living_SDK/platform/mcu/esp8266/aos/soc_impl.c

@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2015-2017 Alibaba Group Holding Limited
+ */
+
+#include <k_api.h>
+#include <assert.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+size_t soc_get_cur_sp()
+{
+    volatile size_t dummy = (size_t)&dummy;
+    return dummy;
+}
+
+#if (RHINO_CONFIG_HW_COUNT > 0)
+hr_timer_t soc_hr_hw_cnt_get(void)
+{
+    return 0;
+}
+#endif
+
+/* iram use as memory heap: */
+#define IRAM_AS_HEAP_ADDR   ((void*)0x40108000)
+#define IRAM_AS_HEAP_LEN    0x4000
+
+extern uint8_t _heap_start, _heap_size;
+const k_mm_region_t g_mm_region[] = {
+    {&_heap_start, (uint32_t)&_heap_size},
+    //{IRAM_AS_HEAP_ADDR, IRAM_AS_HEAP_LEN}
+};
+int g_region_num  = sizeof(g_mm_region)/sizeof(k_mm_region_t);
+
+void soc_err_proc(kstat_t err)
+{
+    // printf("kernel panic,err %d!\n",err);
+    // assert(0);
+}
+
+krhino_err_proc_t g_err_proc = soc_err_proc;
+

Living_SDK/platform/mcu/esp8266/aos/trace_impl.c

@@ -0,0 +1,233 @@
+/*
+ * Copyright (C) 2015-2017 Alibaba Group Holding Limited
+ */
+
+#include <k_api.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <aos/network.h>
+#include <hal/trace.h>
+#include <aos/aos.h>
+
+/* CLI Support */
+#ifdef CONFIG_AOS_CLI
+/* Trace Open*/
+#if (RHINO_CONFIG_TRACE > 0)
+#define TRACE_TASK_STACK_SIZE 512
+
+extern struct k_fifo trace_fifo;
+extern int32_t set_filter_task(const char * task_name);
+extern void set_event_mask(const uint32_t mask);
+extern void trace_deinit(void);
+static ktask_t *trace_task;
+static uint32_t trace_buf[1024];
+static volatile int trace_is_started;
+static char *filter_task;
+static char *ip_addr;
+static uint16_t ip_port = 8000;
+static int sockfd;
+
+void *trace_hal_init()
+{
+    int fd;
+    struct sockaddr_in servaddr;
+
+    TRACE_INIT();
+
+    if ((fd = socket(AF_INET, SOCK_STREAM, 0)) < 0) {
+        aos_cli_printf("create socket (%s:%u) error: %s(errno: %d)\r\n", ip_addr, ip_port, strerror(errno),errno);
+        return 0;
+    }
+
+    memset(&servaddr, 0, sizeof(servaddr));
+    servaddr.sin_family = AF_INET;
+    servaddr.sin_port = htons(ip_port);
+    inet_aton(ip_addr, &servaddr.sin_addr);
+
+    if (connect(fd, (struct sockaddr*)&servaddr, sizeof(servaddr)) < 0) {
+        aos_cli_printf("connect (%s:%u) error: %s(errno: %d)\r\n", ip_addr, ip_port, strerror(errno),errno);
+        close(fd);
+        return 0;
+    }
+    aos_cli_printf("connected on (%s:%u)\r\n", ip_addr, ip_port);
+
+    return (void *)fd;
+}
+
+
+ssize_t trace_hal_send(void *handle, void *buf, size_t len)
+{
+    int len_send = 0;
+    int len_total_send = 0;
+
+    while (1) {
+        len_send = send((int)handle, (buf + len_total_send) , len, 0);
+        if (len_send < 0) {
+            aos_cli_printf("send (%s:%u) msg error: %s(errno: %d)\r\n", ip_addr, ip_port, strerror(errno), errno);
+            return 0;
+        }
+
+        len_total_send += len_send;
+        len -= len_send;
+        if (len == 0) {
+            break;
+        }
+    }
+
+    return len_send;
+}
+
+ssize_t trace_hal_recv(void *handle, void *buf)
+{
+    return 0;
+}
+
+void trace_hal_deinit(void *handle)
+{
+    int fd;
+
+    fd = (int)handle;
+    close(fd);
+    *(int *)handle = -1;
+    sockfd = -1;
+}
+
+void trace_stop(void)
+{
+    set_filter_task(NULL);
+    set_event_mask(0);
+
+    trace_deinit();
+
+    trace_hal_deinit((void *)sockfd);
+
+    aos_cli_printf("trace (%s:%u) stop....\r\n", ip_addr, ip_port);
+
+    if (ip_addr) {
+        aos_free(ip_addr);
+        ip_addr = NULL;
+    }
+
+    if (filter_task){
+        aos_free(filter_task);
+        filter_task = NULL;
+    }
+}
+
+static void trace_entry(void *arg)
+{
+    uint32_t len;
+    while (1) {
+        if (trace_is_started == 0 ){
+            if (sockfd > 0) {
+                trace_stop();
+            }
+
+            krhino_task_sleep(200);
+        } else {
+            if (sockfd <= 0) {
+                sockfd = (int)trace_hal_init();
+            }
+
+            if (sockfd > 0) {
+                len = fifo_out_all(&trace_fifo, trace_buf);
+                if (len > 0) {
+                    trace_hal_send((void *)sockfd, trace_buf, len);
+                }
+            }
+
+            krhino_task_sleep(20);
+        }
+    }
+}
+
+static void handle_trace_cmd(char *pwbuf, int blen, int argc, char **argv)
+{
+    const char *rtype = argc > 1 ? argv[1] : "";
+    int ret = 0;
+
+    if (strcmp(rtype, "start") == 0) {
+        trace_is_started = 1;
+
+        if (argc == 3 || argc == 4) {
+            if (ip_addr == NULL) {
+                ip_addr = (char *) aos_malloc(strlen(argv[2])+1);
+                if (ip_addr == NULL) {
+                    k_err_proc(RHINO_NO_MEM);
+                }
+
+                strncpy(ip_addr, argv[2], strlen(argv[2]));
+                ip_addr[strlen(argv[2])] = '\0';
+            }
+
+            if (argc ==4){
+                ip_port = atoi(argv[3]);
+            }
+        } else {
+            aos_cli_printf("trace must specify the host ip (port)... \r\n");
+            return ;
+        }
+
+        if (trace_task == NULL && krhino_task_dyn_create(&trace_task, "trace_task", NULL, 3,
+            0, TRACE_TASK_STACK_SIZE, trace_entry, 1) != RHINO_SUCCESS) {
+                 aos_cli_printf("trace task creat fail \r\n");
+        }
+    } else if (strcmp(rtype, "task") == 0) {
+        if (argc != 3) {
+            return;
+        }
+        if (filter_task) {
+            aos_free(filter_task);
+        }
+
+        filter_task = (char *) aos_malloc(strlen(argv[2])+1);
+        if (filter_task == NULL) {
+            k_err_proc(RHINO_NO_MEM);
+        }
+
+        strncpy(filter_task, argv[2], strlen(argv[2]));
+        filter_task[strlen(argv[2])] = '\0';
+
+        set_filter_task(filter_task);
+    } else if (strcmp(rtype, "event") == 0) {
+        if (argc != 3) {
+            return;
+        }
+
+        set_event_mask(atoi(argv[2]));
+    } else if (strcmp(rtype, "stop") == 0) {
+        trace_is_started = 0;
+    }
+}
+
+static struct cli_command ncmd = {
+    .name = "trace",
+    .help = "trace [start ip (port) | task task_name| event event_id| stop]",
+    .function = handle_trace_cmd,
+};
+
+void trace_start(void)
+{
+    aos_cli_register_command(&ncmd);
+}
+#else
+void trace_start(void)
+{
+    printf("trace config close!!!\r\n");
+}
+#endif /* Trace end*/
+#else
+void trace_start(void)
+{
+    printf("trace should have cli to control!!!\r\n");
+}
+#endif /*Cli end*/
+
+
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/.gitlab-ci.yml

@@ -0,0 +1,34 @@
+stages:
+  - build
+
+.build_template: &build_template
+  stage: build
+  image: ci_test
+  tags:
+    - build
+
+  variables:
+    GIT_STRATEGY: clone
+
+  before_script:
+    - mkdir -p ~/.ssh
+    - chmod 700 ~/.ssh
+    - echo -n $GITLAB_KEY >> ~/.ssh/id_rsa_base64
+    - base64 --decode --ignore-garbage ~/.ssh/id_rsa_base64 > ~/.ssh/id_rsa
+    - chmod 600 ~/.ssh/id_rsa
+    - echo -e "Host gitlab.espressif.cn\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
+
+
+build_ssc:
+  <<: *build_template
+  artifacts:
+    paths:
+      - ./SSC/ssc_bin
+    expire_in: 6 mos
+  script:
+    - git clone $GITLAB_SSH_SERVER/yinling/SSC.git
+    - cd SSC
+    # try checkout same branch
+    - git checkout ${CI_BUILD_REF_NAME} || echo "Using default branch..."
+    - chmod +x gen_misc_rtos.sh
+    - ./gen_misc_rtos.sh

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/LICENSE

@@ -0,0 +1,63 @@
+ESPRSSIF MIT License
+
+Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+
+Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+it is free of charge, to any person obtaining a copy of this software and associated
+documentation files (the “Software”), to deal in the Software without restriction,
+including without limitation the rights to use, copy, modify, merge, publish, distribute,
+sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all copies or
+substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
+INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE
+FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE SOFTWARE.
+
+
+乐鑫 MIT 许可证
+
+版权 (c) 2015  <乐鑫信息科技（上海）有限公司>
+
+该许可证授权仅限于乐鑫信息科技 ESP8266 产品的应用开发。在此情况下，该许可证免费授权任何获得该
+软件及其相关文档（统称为“软件”）的人无限制地经营该软件，包括无限制的使用、复制、修改、合并、
+出版发行、散布、再授权、及贩售软件及软件副本的权利。被授权人在享受这些权利的同时，需服从下面
+的条件：
+
+在软件和软件的所有副本中都必须包含以上的版权声明和授权声明。
+
+该软件按本来的样子提供，没有任何明确或暗含的担保，包括但不仅限于关于试销性、适合某一特定用途
+和非侵权的保证。作者和版权持有人在任何情况下均不就由软件或软件使用引起的以合同形式、民事侵权
+或其它方式提出的任何索赔、损害或其它责任负责。
+
+Exception vectors include code relicensed from the following:
+Original vector contents Copyright (C) 2014-2015 Espressif Systems
+Additions Copyright (C) Superhouse Automation Pty Ltd and Angus Gratton
+Redistribution and use in source and binary forms, with or without modification, are
+permitted provided that the following conditions are met:
+
+1. Redistributions of source code must retain the above copyright notice, this list of
+conditions and the following disclaimer.
+
+2. Redistributions in binary form must reproduce the above copyright notice, this list
+of conditions and the following disclaimer in the documentation and/or other materials
+provided with the distribution.
+
+3. Neither the name of the copyright holder nor the names of its contributors may be used
+to endorse or promote products derived from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
+OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
+IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/Makefile

@@ -0,0 +1,428 @@
+#  copyright (c) 2010 Espressif System
+#
+ifndef PDIR
+
+endif
+
+ifeq ($(COMPILE), xcc)
+    AR = xt-ar
+	CC = xt-xcc
+	NM = xt-nm
+	CPP = xt-xt++
+	OBJCOPY = xt-objcopy
+	OBJDUMP = xt-objdump
+else
+	AR = xtensa-lx106-elf-ar
+	CC = xtensa-lx106-elf-gcc
+	NM = xtensa-lx106-elf-nm
+	CPP = xtensa-lx106-elf-g++
+	OBJCOPY = xtensa-lx106-elf-objcopy
+	OBJDUMP = xtensa-lx106-elf-objdump
+endif
+
+BOOT?=none
+APP?=0
+SPI_SPEED?=40
+SPI_MODE?=QIO
+SPI_SIZE_MAP?=0
+
+ifeq ($(BOOT), new)
+    boot = new
+else
+    ifeq ($(BOOT), old)
+        boot = old
+    else
+        boot = none
+    endif
+endif
+
+ifeq ($(APP), 1)
+    app = 1
+else
+    ifeq ($(APP), 2)
+        app = 2
+    else
+        app = 0
+    endif
+endif
+
+ifeq ($(SPI_SPEED), 26.7)
+    freqdiv = 1
+else
+    ifeq ($(SPI_SPEED), 20)
+        freqdiv = 2
+    else
+        ifeq ($(SPI_SPEED), 80)
+            freqdiv = 15
+        else
+            freqdiv = 0
+        endif
+    endif
+endif
+
+
+ifeq ($(SPI_MODE), QOUT)
+    mode = 1
+else
+    ifeq ($(SPI_MODE), DIO)
+        mode = 2
+    else
+        ifeq ($(SPI_MODE), DOUT)
+            mode = 3
+        else
+            mode = 0
+        endif
+    endif
+endif
+
+addr = 0x01000
+
+ifeq ($(SPI_SIZE_MAP), 1)
+  size_map = 1
+  flash = 256
+else
+  ifeq ($(SPI_SIZE_MAP), 2)
+    size_map = 2
+    flash = 1024
+    ifeq ($(app), 2)
+      addr = 0x81000
+    endif
+  else
+    ifeq ($(SPI_SIZE_MAP), 3)
+      size_map = 3
+      flash = 2048
+      ifeq ($(app), 2)
+        addr = 0x81000
+      endif
+    else
+      ifeq ($(SPI_SIZE_MAP), 4)
+        size_map = 4
+        flash = 4096
+        ifeq ($(app), 2)
+          addr = 0x81000
+        endif
+      else
+        ifeq ($(SPI_SIZE_MAP), 5)
+          size_map = 5
+          flash = 2048
+          ifeq ($(app), 2)
+            addr = 0x101000
+          endif
+        else
+          ifeq ($(SPI_SIZE_MAP), 6)
+            size_map = 6
+            flash = 4096
+            ifeq ($(app), 2)
+              addr = 0x101000
+            endif
+          else
+            ifeq ($(SPI_SIZE_MAP), 8)
+              size_map = 8
+              flash = 8192
+              ifeq ($(app), 2)
+                addr = 0x101000
+              endif
+            else
+              ifeq ($(SPI_SIZE_MAP), 9)
+                size_map = 9
+                flash = 16384
+                ifeq ($(app), 2)
+                  addr = 0x101000
+                endif
+              else
+                size_map = 0
+                flash = 512
+                ifeq ($(app), 2)
+                addr = 0x41000
+                endif
+              endif
+            endif
+          endif
+        endif
+      endif
+    endif
+  endif
+endif
+
+LD_FILE = $(LDDIR)/eagle.app.v6.ld
+
+ifneq ($(boot), none)
+ifneq ($(app),0)
+    ifneq ($(findstring $(size_map),  6  8  9),)
+      LD_FILE = $(LDDIR)/eagle.app.v6.$(boot).2048.ld
+    else
+      ifeq ($(size_map), 5)
+        LD_FILE = $(LDDIR)/eagle.app.v6.$(boot).2048.ld
+      else
+        ifeq ($(size_map), 4)
+          LD_FILE = $(LDDIR)/eagle.app.v6.$(boot).1024.app$(app).ld
+        else
+          ifeq ($(size_map), 3)
+            LD_FILE = $(LDDIR)/eagle.app.v6.$(boot).1024.app$(app).ld
+          else
+            ifeq ($(size_map), 2)
+              LD_FILE = $(LDDIR)/eagle.app.v6.$(boot).1024.app$(app).ld
+            else
+              ifeq ($(size_map), 0)
+                LD_FILE = $(LDDIR)/eagle.app.v6.$(boot).512.app$(app).ld
+              endif
+            endif
+          endif
+        endif
+      endif
+    endif
+    BIN_NAME = user$(app).$(flash).$(boot).$(size_map)
+endif
+else
+    app = 0
+endif
+
+CSRCS ?= $(wildcard *.c)
+CPPSRCS ?= $(wildcard *.cpp)
+ASRCs ?= $(wildcard *.s)
+ASRCS ?= $(wildcard *.S)
+SUBDIRS ?= $(patsubst %/,%,$(dir $(wildcard */Makefile)))
+
+ODIR := .output
+OBJODIR := $(ODIR)/$(TARGET)/$(FLAVOR)/obj
+
+OBJS := $(CSRCS:%.c=$(OBJODIR)/%.o) \
+        $(CPPSRCS:%.cpp=$(OBJODIR)/%.o) \
+        $(ASRCs:%.s=$(OBJODIR)/%.o) \
+        $(ASRCS:%.S=$(OBJODIR)/%.o)
+
+DEPS := $(CSRCS:%.c=$(OBJODIR)/%.d) \
+        $(CPPSRCS:%.cpp=$(OBJODIR)/%.d) \
+        $(ASRCs:%.s=$(OBJODIR)/%.d) \
+        $(ASRCS:%.S=$(OBJODIR)/%.d)
+
+LIBODIR := $(ODIR)/$(TARGET)/$(FLAVOR)/lib
+OLIBS := $(GEN_LIBS:%=$(LIBODIR)/%)
+
+IMAGEODIR := $(ODIR)/$(TARGET)/$(FLAVOR)/image
+OIMAGES := $(GEN_IMAGES:%=$(IMAGEODIR)/%)
+
+BINODIR := $(ODIR)/$(TARGET)/$(FLAVOR)/bin
+OBINS := $(GEN_BINS:%=$(BINODIR)/%)
+
+CCFLAGS += 			\
+	-g			\
+	-Wpointer-arith		\
+	-Wundef			\
+	-Werror			\
+	-Wl,-EL			\
+	-fno-inline-functions	\
+	-nostdlib       \
+	-mlongcalls	\
+	-mtext-section-literals \
+	-ffunction-sections \
+	-fdata-sections	\
+	-fno-builtin-printf	\
+	-fno-jump-tables
+#	-Wall			
+
+CFLAGS = $(CCFLAGS) $(DEFINES) $(EXTRA_CCFLAGS) $(INCLUDES)
+DFLAGS = $(CCFLAGS) $(DDEFINES) $(EXTRA_CCFLAGS) $(INCLUDES)
+
+
+#############################################################
+# Functions
+#
+
+define ShortcutRule
+$(1): .subdirs $(2)/$(1)
+endef
+
+define MakeLibrary
+DEP_LIBS_$(1) = $$(foreach lib,$$(filter %.a,$$(COMPONENTS_$(1))),$$(dir $$(lib))$$(LIBODIR)/$$(notdir $$(lib)))
+DEP_OBJS_$(1) = $$(foreach obj,$$(filter %.o,$$(COMPONENTS_$(1))),$$(dir $$(obj))$$(OBJODIR)/$$(notdir $$(obj)))
+$$(LIBODIR)/$(1).a: $$(OBJS) $$(DEP_OBJS_$(1)) $$(DEP_LIBS_$(1)) $$(DEPENDS_$(1))
+	@mkdir -p $$(LIBODIR)
+	$$(if $$(filter %.a,$$?),mkdir -p $$(EXTRACT_DIR)_$(1))
+	$$(if $$(filter %.a,$$?),cd $$(EXTRACT_DIR)_$(1); $$(foreach lib,$$(filter %.a,$$?),$$(AR) xo $$(UP_EXTRACT_DIR)/$$(lib);))
+	$$(AR) ru $$@ $$(filter %.o,$$?) $$(if $$(filter %.a,$$?),$$(EXTRACT_DIR)_$(1)/*.o)
+	$$(if $$(filter %.a,$$?),$$(RM) -r $$(EXTRACT_DIR)_$(1))
+endef
+
+define MakeImage
+DEP_LIBS_$(1) = $$(foreach lib,$$(filter %.a,$$(COMPONENTS_$(1))),$$(dir $$(lib))$$(LIBODIR)/$$(notdir $$(lib)))
+DEP_OBJS_$(1) = $$(foreach obj,$$(filter %.o,$$(COMPONENTS_$(1))),$$(dir $$(obj))$$(OBJODIR)/$$(notdir $$(obj)))
+$$(IMAGEODIR)/$(1).out: $$(OBJS) $$(DEP_OBJS_$(1)) $$(DEP_LIBS_$(1)) $$(DEPENDS_$(1))
+	@mkdir -p $$(IMAGEODIR)
+	$$(CC) $$(LDFLAGS) $$(if $$(LINKFLAGS_$(1)),$$(LINKFLAGS_$(1)),$$(LINKFLAGS_DEFAULT) $$(OBJS) $$(DEP_OBJS_$(1)) $$(DEP_LIBS_$(1))) -o $$@ 
+endef
+
+$(BINODIR)/%.bin: $(IMAGEODIR)/%.out
+	@mkdir -p $(BIN_PATH)
+	@mkdir -p $(BINODIR)
+	
+ifeq ($(APP), 0)
+	@$(RM) -r $(BIN_PATH)/eagle.S $(BIN_PATH)/eagle.dump
+	@$(OBJDUMP) -x -s $< > $(BIN_PATH)/eagle.dump
+	@$(OBJDUMP) -S $< > $(BIN_PATH)/eagle.S
+else
+	@mkdir -p $(BIN_PATH)/upgrade
+	@$(RM) -r $(BIN_PATH)/upgrade/$(BIN_NAME).S $(BIN_PATH)/upgrade/$(BIN_NAME).dump
+	@$(OBJDUMP) -x -s $< > $(BIN_PATH)/upgrade/$(BIN_NAME).dump
+	@$(OBJDUMP) -S $< > $(BIN_PATH)/upgrade/$(BIN_NAME).S
+endif
+
+	@$(OBJCOPY) --only-section .text -O binary $< eagle.app.v6.text.bin
+	@$(OBJCOPY) --only-section .data -O binary $< eagle.app.v6.data.bin
+	@$(OBJCOPY) --only-section .rodata -O binary $< eagle.app.v6.rodata.bin
+	@$(OBJCOPY) --only-section .irom0.text -O binary $< eagle.app.v6.irom0text.bin
+
+	@echo ""
+	@echo "!!!"
+	@echo "SDK_PATH: $(SDK_PATH)"
+	
+ifeq ($(app), 0)
+	@python $(SDK_PATH)/tools/gen_appbin.py $< 0 $(mode) $(freqdiv) $(size_map)
+	@mv eagle.app.flash.bin $(BIN_PATH)/eagle.flash.bin
+	@mv eagle.app.v6.irom0text.bin $(BIN_PATH)/eagle.irom0text.bin
+	@rm eagle.app.v6.*
+	@echo "BIN_PATH: $(BIN_PATH)"
+	@echo ""
+	@echo "No boot needed."
+	@echo "Generate eagle.flash.bin and eagle.irom0text.bin successully in BIN_PATH"
+	@echo "eagle.flash.bin-------->0x00000"
+	@echo "eagle.irom0text.bin---->0x20000"
+else
+	@echo "BIN_PATH: $(BIN_PATH)/upgrade"
+	@echo ""
+
+    ifneq ($(boot), new)
+		@python $(SDK_PATH)/tools/gen_appbin.py $< 1 $(mode) $(freqdiv) $(size_map)
+		@echo "Support boot_v1.1 and +"
+    else
+		@python $(SDK_PATH)/tools/gen_appbin.py $< 2 $(mode) $(freqdiv) $(size_map)
+
+    	ifeq ($(size_map), 6)
+		@echo "Support boot_v1.4 and +"
+        else
+            ifeq ($(size_map), 5)
+		@echo "Support boot_v1.4 and +"
+            else
+		@echo "Support boot_v1.2 and +"
+            endif
+        endif
+    endif
+
+	@mv eagle.app.flash.bin $(BIN_PATH)/upgrade/$(BIN_NAME).bin
+	@rm eagle.app.v6.*
+	@echo "Generate $(BIN_NAME).bin successully in BIN_PATH"
+	@echo "boot.bin------------>0x00000"
+	@echo "$(BIN_NAME).bin--->$(addr)"
+endif
+
+	@echo "!!!"
+
+#############################################################
+# Rules base
+# Should be done in top-level makefile only
+#
+
+all:	.subdirs $(OBJS) $(OLIBS) $(OIMAGES) $(OBINS) $(SPECIAL_MKTARGETS)
+
+clean:
+	$(foreach d, $(SUBDIRS), $(MAKE) -C $(d) clean;)
+	$(RM) -r $(ODIR)/$(TARGET)/$(FLAVOR)
+
+clobber: $(SPECIAL_CLOBBER)
+	$(foreach d, $(SUBDIRS), $(MAKE) -C $(d) clobber;)
+	$(RM) -r $(ODIR)
+
+.subdirs:
+	@set -e; $(foreach d, $(SUBDIRS), $(MAKE) -C $(d);)
+
+#.subdirs:
+#	$(foreach d, $(SUBDIRS), $(MAKE) -C $(d))
+
+ifneq ($(MAKECMDGOALS),clean)
+ifneq ($(MAKECMDGOALS),clobber)
+ifdef DEPS
+sinclude $(DEPS)
+endif
+endif
+endif
+
+$(OBJODIR)/%.o: %.c
+	@mkdir -p $(OBJODIR);
+	$(CC) $(if $(findstring $<,$(DSRCS)),$(DFLAGS),$(CFLAGS)) $(COPTS_$(*F)) -o $@ -c $<
+
+$(OBJODIR)/%.d: %.c
+	@mkdir -p $(OBJODIR);
+	@echo DEPEND: $(CC) -M $(CFLAGS) $<
+	@set -e; rm -f $@; \
+	$(CC) -M $(CFLAGS) $< > $@.$$$$; \
+	sed 's,\($*\.o\)[ :]*,$(OBJODIR)/\1 $@ : ,g' < $@.$$$$ > $@; \
+	rm -f $@.$$$$
+	
+$(OBJODIR)/%.o: %.cpp
+	@mkdir -p $(OBJODIR);
+	$(CPP) $(if $(findstring $<,$(DSRCS)),$(DFLAGS),$(CFLAGS)) $(COPTS_$(*F)) -o $@ -c $<
+
+$(OBJODIR)/%.d: %.cpp
+	@mkdir -p $(OBJODIR);
+	@echo DEPEND: $(CPP) -M $(CFLAGS) $<
+	@set -e; rm -f $@; \
+	$(CPP) -M $(CFLAGS) $< > $@.$$$$; \
+	sed 's,\($*\.o\)[ :]*,$(OBJODIR)/\1 $@ : ,g' < $@.$$$$ > $@; \
+	rm -f $@.$$$$
+
+$(OBJODIR)/%.o: %.s
+	@mkdir -p $(OBJODIR);
+	$(CC) $(CFLAGS) -o $@ -c $<
+
+$(OBJODIR)/%.d: %.s
+	@mkdir -p $(OBJODIR); \
+	set -e; rm -f $@; \
+	$(CC) -M $(CFLAGS) $< > $@.$$$$; \
+	sed 's,\($*\.o\)[ :]*,$(OBJODIR)/\1 $@ : ,g' < $@.$$$$ > $@; \
+	rm -f $@.$$$$
+
+$(OBJODIR)/%.o: %.S
+	@mkdir -p $(OBJODIR);
+	$(CC) $(CFLAGS) -D__ASSEMBLER__ -o $@ -c $<
+
+$(OBJODIR)/%.d: %.S
+	@mkdir -p $(OBJODIR); \
+	set -e; rm -f $@; \
+	$(CC) -M $(CFLAGS) $< > $@.$$$$; \
+	sed 's,\($*\.o\)[ :]*,$(OBJODIR)/\1 $@ : ,g' < $@.$$$$ > $@; \
+	rm -f $@.$$$$
+
+$(foreach lib,$(GEN_LIBS),$(eval $(call ShortcutRule,$(lib),$(LIBODIR))))
+
+$(foreach image,$(GEN_IMAGES),$(eval $(call ShortcutRule,$(image),$(IMAGEODIR))))
+
+$(foreach bin,$(GEN_BINS),$(eval $(call ShortcutRule,$(bin),$(BINODIR))))
+
+$(foreach lib,$(GEN_LIBS),$(eval $(call MakeLibrary,$(basename $(lib)))))
+
+$(foreach image,$(GEN_IMAGES),$(eval $(call MakeImage,$(basename $(image)))))
+
+#############################################################
+# Recursion Magic - Don't touch this!!
+#
+# Each subtree potentially has an include directory
+#   corresponding to the common APIs applicable to modules
+#   rooted at that subtree. Accordingly, the INCLUDE PATH
+#   of a module can only contain the include directories up
+#   its parent path, and not its siblings
+#
+# Required for each makefile to inherit from the parent
+#
+
+INCLUDES := $(INCLUDES) -I $(SDK_PATH)/include -I $(SDK_PATH)/extra_include
+INCLUDES += -I $(SDK_PATH)/driver_lib/include
+INCLUDES += -I $(SDK_PATH)/include/espressif
+INCLUDES += -I $(SDK_PATH)/include/lwip
+INCLUDES += -I $(SDK_PATH)/include/lwip/ipv4
+INCLUDES += -I $(SDK_PATH)/include/lwip/ipv6
+INCLUDES += -I $(SDK_PATH)/include/nopoll
+INCLUDES += -I $(SDK_PATH)/include/spiffs
+INCLUDES += -I $(SDK_PATH)/include/ssl
+INCLUDES += -I $(SDK_PATH)/include/json
+INCLUDES += -I $(SDK_PATH)/include/openssl
+INCLUDES += -I $(SDK_PATH)/include/espos

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/README.md

@@ -0,0 +1,55 @@
+# ESP8266_RTOS_SDK #
+
+----------
+
+ESP8266 SDK based on FreeRTOS.
+   
+## Note ##
+
+APIs of "ESP8266_RTOS_SDK" are same as "ESP8266_NONOS_SDK"
+
+More details in "Wiki" !
+
+## Requrements ##
+
+You can use both xcc and gcc to compile your project, gcc is recommended.
+For gcc, please refer to [esp-open-sdk](https://github.com/pfalcon/esp-open-sdk).
+
+  
+## Compile ##
+
+Clone ESP8266_RTOS_SDK, e.g., to ~/ESP8266_RTOS_SDK.
+
+    $git clone https://github.com/espressif/ESP8266_RTOS_SDK.git
+
+Modify gen_misc.sh or gen_misc.bat:
+For Linux:
+
+    $export SDK_PATH=~/ESP8266_RTOS_SDK
+    $export BIN_PATH=~/ESP8266_BIN
+
+For Windows:
+
+    set SDK_PATH=/c/ESP8266_RTOS_SDK
+    set BIN_PATH=/c/ESP8266_BIN
+
+ESP8266_RTOS_SDK/examples/project_template is a project template, you can copy this to anywhere, e.g., to ~/workspace/project_template.
+
+Generate bin: 
+For Linux:
+
+    ./gen_misc.sh
+
+For Windows:
+
+    gen_misc.bat
+   
+Just follow the tips and steps.
+
+## Download ##
+
+eagle.app.v6.flash.bin, downloads to flash 0x00000
+
+eagle.app.v6.irom0text.bin, downloads to flash 0x40000
+
+blank.bin, downloads to flash 0x7E000

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/VERSION

@@ -0,0 +1,19 @@
+gwen:
+    crypto:     52dbf63
+    espnow:     52dbf63
+    main:       d01afb5
+    minic:      52dbf63
+    net80211:   d01afb5
+    pp:         94fab61
+    pwm:        52dbf63
+    smartconfig:016fc33
+    wpa:        bac4751
+    wps:        52dbf63
+
+gitlab:
+    espconn:    3a998034
+    freertos:   ac047746
+    lwip:       bfdb6ec2
+    driver:     7bee5263
+    mbedtls:    1ac9f1f4
+    ssl:        eefb383a

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/cacheasm.h

@@ -0,0 +1,807 @@
+/*
+ * xtensa/cacheasm.h -- assembler-specific cache related definitions
+ *			that depend on CORE configuration
+ *
+ *  This file is logically part of xtensa/coreasm.h ,
+ *  but is kept separate for modularity / compilation-performance.
+ */
+
+/*
+ * Copyright (c) 2001-2002, 2006 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_CACHEASM_H
+#define XTENSA_CACHEASM_H
+
+#include <xtensa/coreasm.h>
+#include <xtensa/xtensa-xer.h>
+
+/*
+ *  This header file defines assembler macros of the form:
+ *	<x>cache_<func>
+ *  where <x> is 'i' or 'd' for instruction and data caches,
+ *  and <func> indicates the function of the macro.
+ *
+ *  The following functions <func> are defined,
+ *  and apply only to the specified cache (I or D):
+ *
+ *  reset
+ *	Resets the cache.
+ *
+ *  sync
+ *	Makes sure any previous cache instructions have been completed;
+ *	ie. makes sure any previous cache control operations
+ *	have had full effect and been synchronized to memory.
+ *	Eg. any invalidate completed [so as not to generate a hit],
+ *	any writebacks or other pipelined writes written to memory, etc.
+ *
+ *  invalidate_line		(single cache line)
+ *  invalidate_region		(specified memory range)
+ *  invalidate_all		(entire cache)
+ *	Invalidates all cache entries that cache
+ *	data from the specified memory range.
+ *	NOTE: locked entries are not invalidated.
+ *
+ *  writeback_line		(single cache line)
+ *  writeback_region		(specified memory range)
+ *  writeback_all		(entire cache)
+ *	Writes back to memory all dirty cache entries
+ *	that cache data from the specified memory range,
+ *	and marks these entries as clean.
+ *	NOTE: on some future implementations, this might
+ *		also invalidate.
+ *	NOTE: locked entries are written back, but never invalidated.
+ *	NOTE: instruction caches never implement writeback.
+ *
+ *  writeback_inv_line		(single cache line)
+ *  writeback_inv_region	(specified memory range)
+ *  writeback_inv_all		(entire cache)
+ *	Writes back to memory all dirty cache entries
+ *	that cache data from the specified memory range,
+ *	and invalidates these entries (including all clean
+ *	cache entries that cache data from that range).
+ *	NOTE: locked entries are written back but not invalidated.
+ *	NOTE: instruction caches never implement writeback.
+ *
+ *  lock_line			(single cache line)
+ *  lock_region			(specified memory range)
+ *	Prefetch and lock the specified memory range into cache.
+ *	NOTE:  if any part of the specified memory range cannot
+ *	be locked, a Load/Store Error (for dcache) or Instruction
+ *	Fetch Error (for icache) exception occurs.  These macros don't
+ *	do anything special (yet anyway) to handle this situation.
+ *
+ *  unlock_line			(single cache line)
+ *  unlock_region		(specified memory range)
+ *  unlock_all			(entire cache)
+ *	Unlock cache entries that cache the specified memory range.
+ *	Entries not already locked are unaffected.
+ *
+ *  coherence_on
+ *  coherence_off
+ *      Turn off and on cache coherence
+ *
+ */
+
+
+
+/***************************   GENERIC -- ALL CACHES   ***************************/
+
+
+/*
+ *  The following macros assume the following cache size/parameter limits
+ *  in the current Xtensa core implementation:
+ *	cache size:	1024 bytes minimum
+ *	line size:	16 - 64 bytes
+ *	way count:	1 - 4
+ *
+ *  Minimum entries per way (ie. per associativity) = 1024 / 64 / 4 = 4
+ *  Hence the assumption that each loop can execute four cache instructions.
+ *
+ *  Correspondingly, the offset range of instructions is assumed able to cover
+ *  four lines, ie. offsets {0,1,2,3} * line_size are assumed valid for
+ *  both hit and indexed cache instructions.  Ie. these offsets are all
+ *  valid:  0, 16, 32, 48, 64, 96, 128, 192 (for line sizes 16, 32, 64).
+ *  This is true of all original cache instructions
+ *  (dhi, ihi, dhwb, dhwbi, dii, iii) which have offsets
+ *  of 0 to 1020 in multiples of 4 (ie. 8 bits shifted by 2).
+ *  This is also true of subsequent cache instructions
+ *  (dhu, ihu, diu, iiu, diwb, diwbi, dpfl, ipfl) which have offsets
+ *  of 0 to 240 in multiples of 16 (ie. 4 bits shifted by 4).
+ *
+ *  (Maximum cache size, currently 32k, doesn't affect the following macros.
+ *  Cache ways > MMU min page size cause aliasing but that's another matter.)
+ */
+
+
+
+/*
+ *  Macro to apply an 'indexed' cache instruction to the entire cache.
+ *
+ *  Parameters:
+ *	cainst		instruction/ that takes an address register parameter
+ *			and an offset parameter (in range 0 .. 3*linesize).
+ *	size		size of cache in bytes
+ *	linesize	size of cache line in bytes (always power-of-2)
+ *	assoc_or1	number of associativities (ways/sets) in cache
+ *			if all sets affected by cainst,
+ *			or 1 if only one set (or not all sets) of the cache
+ *			is affected by cainst (eg. DIWB or DIWBI [not yet ISA defined]).
+ *	aa, ab		unique address registers (temporaries)
+ *	loopokay	1 (default) allows use of zero-overhead loops, 0 does not
+ *	immrange	range (max value) of cainst's immediate offset parameter, in bytes
+ *			(NOTE: macro assumes immrange allows power-of-2 number of lines)
+ */
+
+	.macro	cache_index_all		cainst, size, linesize, assoc_or1, aa, ab, loopokay=1, maxofs=240
+
+	//  Number of indices in cache (lines per way):
+	.set	.Lindices, (\size / (\linesize * \assoc_or1))
+	//  Number of indices processed per loop iteration (max 4):
+	.set	.Lperloop, .Lindices
+	.ifgt	.Lperloop - 4
+	 .set	.Lperloop, 4
+	.endif
+	//  Also limit instructions per loop if cache line size exceeds immediate range:
+	.set	.Lmaxperloop, (\maxofs / \linesize) + 1
+	.ifgt	.Lperloop - .Lmaxperloop
+	 .set	.Lperloop, .Lmaxperloop
+	.endif
+	//  Avoid addi of 128 which takes two instructions (addmi,addi):
+	.ifeq	.Lperloop*\linesize - 128
+	 .ifgt	.Lperloop - 1
+	  .set	.Lperloop, .Lperloop / 2
+	 .endif
+	.endif
+
+	//  \size byte cache, \linesize byte lines, \assoc_or1 way(s) affected by each \cainst.
+	.ifne	(\loopokay & XCHAL_HAVE_LOOPS)
+
+	movi	\aa, .Lindices / .Lperloop		// number of loop iterations
+	// Possible improvement: need only loop if \aa > 1 ;
+	// however \aa == 1 is highly unlikely.
+	movi	\ab, 0		// to iterate over cache
+	loop		\aa, .Lend_cachex\@
+	.set	.Li, 0 ;     .rept .Lperloop
+	  \cainst	\ab, .Li*\linesize
+	.set	.Li, .Li+1 ; .endr
+	addi		\ab, \ab, .Lperloop*\linesize	// move to next line
+.Lend_cachex\@:
+
+	.else
+
+	movi	\aa, (\size / \assoc_or1)
+	// Possible improvement: need only loop if \aa > 1 ;
+	// however \aa == 1 is highly unlikely.
+	movi	\ab, 0		// to iterate over cache
+.Lstart_cachex\@:
+	.set	.Li, 0 ;     .rept .Lperloop
+	  \cainst	\ab, .Li*\linesize
+	.set	.Li, .Li+1 ; .endr
+	addi		\ab, \ab, .Lperloop*\linesize	// move to next line
+	bltu		\ab, \aa, .Lstart_cachex\@
+
+	.endif
+
+	.endm
+
+
+/*
+ *  Macro to apply a 'hit' cache instruction to a memory region,
+ *  ie. to any cache entries that cache a specified portion (region) of memory.
+ *  Takes care of the unaligned cases, ie. may apply to one
+ *  more cache line than $asize / lineSize if $aaddr is not aligned.
+ *
+ *
+ *  Parameters are:
+ *	cainst	instruction/macro that takes an address register parameter
+ *		and an offset parameter (currently always zero)
+ *		and generates a cache instruction (eg. "dhi", "dhwb", "ihi", etc.)
+ *	linesize_log2	log2(size of cache line in bytes)
+ *	addr	register containing start address of region (clobbered)
+ *	asize	register containing size of the region in bytes (clobbered)
+ *	askew	unique register used as temporary
+ *
+ *  Note: A possible optimization to this macro is to apply the operation
+ *  to the entire cache if the region exceeds the size of the cache
+ *  by some empirically determined amount or factor.  Some experimentation
+ *  is required to determine the appropriate factors, which also need
+ *  to be tunable if required.
+ */
+
+	.macro	cache_hit_region	cainst, linesize_log2, addr, asize, askew
+
+	//  Make \asize the number of iterations:
+	extui	\askew, \addr, 0, \linesize_log2	// get unalignment amount of \addr
+	add	\asize, \asize, \askew			// ... and add it to \asize
+	addi	\asize, \asize, (1 << \linesize_log2) - 1	// round up!
+	srli	\asize, \asize, \linesize_log2
+
+	//  Iterate over region:
+	floopnez	\asize, cacheh\@
+	\cainst		\addr, 0
+	addi		\addr, \addr, (1 << \linesize_log2)	// move to next line
+	floopend	\asize, cacheh\@
+
+	.endm
+
+
+
+
+
+/***************************   INSTRUCTION CACHE   ***************************/
+
+
+/*
+ *  Reset/initialize the instruction cache by simply invalidating it:
+ *  (need to unlock first also, if cache locking implemented):
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	icache_reset	aa, ab, loopokay=0
+	icache_unlock_all	\aa, \ab, \loopokay
+	icache_invalidate_all	\aa, \ab, \loopokay
+	.endm
+
+
+/*
+ * Synchronize after an instruction cache operation,
+ * to be sure everything is in sync with memory as to be
+ * expected following any previous instruction cache control operations.
+ *
+ * Even if a config doesn't have caches, an isync is still needed
+ * when instructions in any memory are modified, whether by a loader
+ * or self-modifying code.  Therefore, this macro always produces
+ * an isync, whether or not an icache is present.
+ *
+ * Parameters are:
+ *	ar	an address register (temporary) (currently unused, but may be used in future)
+ */
+	.macro	icache_sync	ar
+	isync
+	.endm
+
+
+
+/*
+ *  Invalidate a single line of the instruction cache.
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to invalidate
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	(optional) offset to add to \ar to compute effective address to invalidate
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	icache_invalidate_line	ar, offset
+#if XCHAL_ICACHE_SIZE > 0
+	ihi	\ar, \offset		// invalidate icache line
+	/*
+	 *  NOTE:  in some early version of a test chip silicon (SiChip1),
+	 *  'ihi' didn't work, so software had to replace it with
+	 *  the much more draconian 'iii'
+	 *  (which would just invalidate more than it should,
+	 *  which should be okay other than the performance hit
+	 *  because cache locking did not exist in that version,
+	 *  unless user somehow relies on something being cached).
+	 *
+	 *  #if ... targeting this ancient, now non-existent, test chip silicon ...
+	 *	iii	\ar, \offset
+	 *  #endif
+	 */
+	icache_sync	\ar
+#endif
+	.endm
+
+
+
+
+/*
+ *  Invalidate instruction  cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	icache_invalidate_region	astart, asize, ac
+#if XCHAL_ICACHE_SIZE > 0
+	//  Instruction cache region invalidation:
+	cache_hit_region	ihi, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
+	icache_sync	\ac
+	//  End of instruction cache region invalidation
+#endif
+	.endm
+
+
+
+/*
+ *  Invalidate entire instruction cache.
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	icache_invalidate_all	aa, ab, loopokay=1
+#if XCHAL_ICACHE_SIZE > 0
+	//  Instruction cache invalidation:
+	cache_index_all		iii, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, XCHAL_ICACHE_WAYS, \aa, \ab, \loopokay, 1020
+	icache_sync	\aa
+	//  End of instruction cache invalidation
+#endif
+	.endm
+
+
+
+/*
+ *  Lock (prefetch & lock) a single line of the instruction cache.
+ *
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to lock
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to lock
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	icache_lock_line	ar, offset
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+	ipfl	\ar, \offset	/* prefetch and lock icache line */
+	icache_sync	\ar
+#endif
+	.endm
+
+
+
+/*
+ *  Lock (prefetch & lock) a specified portion of memory into the instruction cache.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	icache_lock_region	astart, asize, ac
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+	//  Instruction cache region lock:
+	cache_hit_region	ipfl, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
+	icache_sync	\ac
+	//  End of instruction cache region lock
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock a single line of the instruction cache.
+ *
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to unlock
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to unlock
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	icache_unlock_line	ar, offset
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+	ihu	\ar, \offset	/* unlock icache line */
+	icache_sync	\ar
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock a specified portion of memory from the instruction cache.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	icache_unlock_region	astart, asize, ac
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+	//  Instruction cache region unlock:
+	cache_hit_region	ihu, XCHAL_ICACHE_LINEWIDTH, \astart, \asize, \ac
+	icache_sync	\ac
+	//  End of instruction cache region unlock
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock entire instruction cache.
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	icache_unlock_all	aa, ab, loopokay=1
+#if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
+	//  Instruction cache unlock:
+	cache_index_all		iiu, XCHAL_ICACHE_SIZE, XCHAL_ICACHE_LINESIZE, 1, \aa, \ab, \loopokay
+	icache_sync	\aa
+	//  End of instruction cache unlock
+#endif
+	.endm
+
+
+
+
+
+/***************************   DATA CACHE   ***************************/
+
+
+
+/*
+ *  Reset/initialize the data cache by simply invalidating it
+ *  (need to unlock first also, if cache locking implemented):
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	dcache_reset	aa, ab, loopokay=0
+	dcache_unlock_all	\aa, \ab, \loopokay
+	dcache_invalidate_all	\aa, \ab, \loopokay
+	.endm
+
+
+
+
+/*
+ * Synchronize after a data cache operation,
+ * to be sure everything is in sync with memory as to be
+ * expected following any previous data cache control operations.
+ *
+ * Parameters are:
+ *	ar	an address register (temporary) (currently unused, but may be used in future)
+ */
+	.macro	dcache_sync	ar
+#if XCHAL_DCACHE_SIZE > 0
+	//  This previous sequence errs on the conservative side (too much so); a DSYNC should be sufficient:
+	//memw		// synchronize data cache changes relative to subsequent memory accesses
+	//isync		// be conservative and ISYNC as well (just to be sure)
+
+	dsync
+#endif
+	.endm
+
+
+
+/*
+ * Opt into cache coherence.
+ *
+ * Parameters are:
+ *	ar,at	two scratch address registers (both clobbered)
+ */
+	.macro	cache_coherence_on	ar at
+#if XCHAL_HAVE_EXTERN_REGS && XCHAL_DCACHE_IS_COHERENT
+	movi	\ar, 1
+	movi	\at, XER_CCON
+	wer	\ar, \at
+	extw
+# endif
+	.endm
+
+
+
+/*
+ * Opt out of cache coherence.
+ * NOTE:  this is generally preceded by emptying the cache;
+ * see xthal_cache_coherence_optout() in hal/coherence.c for details.
+ *
+ * Parameters are:
+ *	ar,at	two scratch address registers (both clobbered)
+ */
+	.macro	cache_coherence_off	ar at
+#if XCHAL_HAVE_EXTERN_REGS && XCHAL_DCACHE_IS_COHERENT
+	extw
+	movi	\at, 0
+	movi	\ar, XER_CCON
+	wer	\at, \ar
+	extw
+#endif
+	.endm
+
+
+
+/*
+ * Synchronize after a data store operation,
+ * to be sure the stored data is completely off the processor
+ * (and assuming there is no buffering outside the processor,
+ *  that the data is in memory).  This may be required to
+ * ensure that the processor's write buffers are emptied.
+ * A MEMW followed by a read guarantees this, by definition.
+ * We also try to make sure the read itself completes.
+ *
+ * Parameters are:
+ *	ar	an address register (temporary)
+ */
+	.macro	write_sync	ar
+	memw			// ensure previous memory accesses are complete prior to subsequent memory accesses
+	l32i	\ar, sp, 0	// completing this read ensures any previous write has completed, because of MEMW
+	//slot
+	add	\ar, \ar, \ar	// use the result of the read to help ensure the read completes (in future architectures)
+	.endm
+
+
+/*
+ *  Invalidate a single line of the data cache.
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to invalidate
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	(optional) offset to add to \ar to compute effective address to invalidate
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	dcache_invalidate_line	ar, offset
+#if XCHAL_DCACHE_SIZE > 0
+	dhi	\ar, \offset
+	dcache_sync	\ar
+#endif
+	.endm
+
+
+
+
+
+/*
+ *  Invalidate data cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	dcache_invalidate_region	astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0
+	//  Data cache region invalidation:
+	cache_hit_region	dhi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+	dcache_sync	\ac
+	//  End of data cache region invalidation
+#endif
+	.endm
+
+
+
+#if 0
+/*
+ *  This is a work-around for a bug in SiChip1.
+ *  To enable the work-around, uncomment this and replace 'dii'
+ *  with 'dii_s1' everywhere, eg. in the dcache_invalidate_all
+ *  macro below.
+ */
+	.macro	dii_s1	ar, offset
+	dii	\ar, \offset
+	or	\ar, \ar, \ar
+	or	\ar, \ar, \ar
+	or	\ar, \ar, \ar
+	or	\ar, \ar, \ar
+	.endm
+#endif
+
+
+/*
+ *  Invalidate entire data cache.
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	dcache_invalidate_all	aa, ab, loopokay=1
+#if XCHAL_DCACHE_SIZE > 0
+	//  Data cache invalidation:
+	cache_index_all		dii, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, XCHAL_DCACHE_WAYS, \aa, \ab, \loopokay, 1020
+	dcache_sync	\aa
+	//  End of data cache invalidation
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback a single line of the data cache.
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to writeback
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to writeback
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	dcache_writeback_line	ar, offset
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
+	dhwb	\ar, \offset
+	dcache_sync	\ar
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback dirty data cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	dcache_writeback_region		astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
+	//  Data cache region writeback:
+	cache_hit_region	dhwb, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+	dcache_sync	\ac
+	//  End of data cache region writeback
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback entire data cache.
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	dcache_writeback_all	aa, ab, loopokay=1
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_IS_WRITEBACK
+	//  Data cache writeback:
+	cache_index_all		diwb, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay
+	dcache_sync	\aa
+	//  End of data cache writeback
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback and invalidate a single line of the data cache.
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to writeback and invalidate
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to writeback and invalidate
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	dcache_writeback_inv_line	ar, offset
+#if XCHAL_DCACHE_SIZE > 0
+	dhwbi	\ar, \offset	/* writeback and invalidate dcache line */
+	dcache_sync	\ar
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback and invalidate data cache entries that cache a specified portion of memory.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	dcache_writeback_inv_region	astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0
+	//  Data cache region writeback and invalidate:
+	cache_hit_region	dhwbi, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+	dcache_sync	\ac
+	//  End of data cache region writeback and invalidate
+#endif
+	.endm
+
+
+
+/*
+ *  Writeback and invalidate entire data cache.
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	dcache_writeback_inv_all	aa, ab, loopokay=1
+#if XCHAL_DCACHE_SIZE > 0
+	//  Data cache writeback and invalidate:
+#if XCHAL_DCACHE_IS_WRITEBACK
+	cache_index_all		diwbi, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay
+	dcache_sync	\aa
+#else /*writeback*/
+	//  Data cache does not support writeback, so just invalidate: */
+	dcache_invalidate_all	\aa, \ab, \loopokay
+#endif /*writeback*/
+	//  End of data cache writeback and invalidate
+#endif
+	.endm
+
+
+
+
+/*
+ *  Lock (prefetch & lock) a single line of the data cache.
+ *
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to lock
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to lock
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	dcache_lock_line	ar, offset
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+	dpfl	\ar, \offset	/* prefetch and lock dcache line */
+	dcache_sync	\ar
+#endif
+	.endm
+
+
+
+/*
+ *  Lock (prefetch & lock) a specified portion of memory into the data cache.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	dcache_lock_region	astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+	//  Data cache region lock:
+	cache_hit_region	dpfl, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+	dcache_sync	\ac
+	//  End of data cache region lock
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock a single line of the data cache.
+ *
+ *  Parameters are:
+ *	ar	address register that contains (virtual) address to unlock
+ *		(may get clobbered in a future implementation, but not currently)
+ *	offset	offset to add to \ar to compute effective address to unlock
+ *		(note: some number of lsbits are ignored)
+ */
+	.macro	dcache_unlock_line	ar, offset
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+	dhu	\ar, \offset	/* unlock dcache line */
+	dcache_sync	\ar
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock a specified portion of memory from the data cache.
+ *  Parameters are:
+ *	astart	start address (register gets clobbered)
+ *	asize	size of the region in bytes (register gets clobbered)
+ *	ac	unique register used as temporary
+ */
+	.macro	dcache_unlock_region	astart, asize, ac
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+	//  Data cache region unlock:
+	cache_hit_region	dhu, XCHAL_DCACHE_LINEWIDTH, \astart, \asize, \ac
+	dcache_sync	\ac
+	//  End of data cache region unlock
+#endif
+	.endm
+
+
+
+/*
+ *  Unlock entire data cache.
+ *
+ *  Parameters:
+ *	aa, ab		unique address registers (temporaries)
+ */
+	.macro	dcache_unlock_all	aa, ab, loopokay=1
+#if XCHAL_DCACHE_SIZE > 0 && XCHAL_DCACHE_LINE_LOCKABLE
+	//  Data cache unlock:
+	cache_index_all		diu, XCHAL_DCACHE_SIZE, XCHAL_DCACHE_LINESIZE, 1, \aa, \ab, \loopokay
+	dcache_sync	\aa
+	//  End of data cache unlock
+#endif
+	.endm
+
+
+#endif /*XTENSA_CACHEASM_H*/
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/cacheattrasm.h

@@ -0,0 +1,436 @@
+/*
+ * xtensa/cacheattrasm.h -- assembler-specific CACHEATTR register related definitions
+ *			that depend on CORE configuration
+ *
+ *  This file is logically part of xtensa/coreasm.h (or perhaps xtensa/cacheasm.h),
+ *  but is kept separate for modularity / compilation-performance.
+ */
+
+/*
+ * Copyright (c) 2001-2009 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_CACHEATTRASM_H
+#define XTENSA_CACHEATTRASM_H
+
+#include <xtensa/coreasm.h>
+
+/*  Determine whether cache attributes are controlled using eight 512MB entries:  */
+#define XCHAL_CA_8X512	(XCHAL_HAVE_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR \
+	|| (XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY))
+
+
+/*
+ *  This header file defines assembler macros of the form:
+ *	<x>cacheattr_<func>
+ *  where:
+ *	<x> is 'i', 'd' or absent for instruction, data
+ *		or both caches; and
+ *	<func> indicates the function of the macro.
+ *
+ *  The following functions are defined:
+ *
+ *  icacheattr_get
+ *	Reads I-cache CACHEATTR into a2 (clobbers a3-a5).
+ *
+ *  dcacheattr_get
+ *	Reads D-cache CACHEATTR into a2 (clobbers a3-a5).
+ *	(Note:  for configs with a real CACHEATTR register, the
+ *	 above two macros are identical.)
+ *
+ *  cacheattr_set
+ *	Writes both I-cache and D-cache CACHEATTRs from a2 (a3-a8 clobbered).
+ *	Works even when changing one's own code's attributes.
+ *
+ *  icacheattr_is_enabled  label
+ *	Branches to \label if I-cache appears to have been enabled
+ *	(eg. if CACHEATTR contains a cache-enabled attribute).
+ *	(clobbers a2-a5,SAR)
+ *
+ *  dcacheattr_is_enabled  label
+ *	Branches to \label if D-cache appears to have been enabled
+ *	(eg. if CACHEATTR contains a cache-enabled attribute).
+ *	(clobbers a2-a5,SAR)
+ *
+ *  cacheattr_is_enabled  label
+ *	Branches to \label if either I-cache or D-cache appears to have been enabled
+ *	(eg. if CACHEATTR contains a cache-enabled attribute).
+ *	(clobbers a2-a5,SAR)
+ *
+ *  The following macros are only defined under certain conditions:
+ *
+ *  icacheattr_set	(if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
+ *	Writes I-cache CACHEATTR from a2 (a3-a8 clobbered).
+ *
+ *  dcacheattr_set	(if XCHAL_HAVE_MIMIC_CACHEATTR || XCHAL_HAVE_XLT_CACHEATTR)
+ *	Writes D-cache CACHEATTR from a2 (a3-a8 clobbered).
+ */
+
+
+
+/***************************   GENERIC -- ALL CACHES   ***************************/
+
+/*
+ *  _cacheattr_get
+ *
+ *  (Internal macro.)
+ *  Returns value of CACHEATTR register (or closest equivalent) in a2.
+ *  
+ *  Entry:
+ *	(none)
+ *  Exit:
+ *	a2	value read from CACHEATTR
+ *	a3-a5	clobbered (temporaries)
+ */
+	.macro	_cacheattr_get	tlb
+#if XCHAL_HAVE_CACHEATTR
+	rsr	a2, CACHEATTR
+#elif XCHAL_CA_8X512
+	//  We have a config that "mimics" CACHEATTR using a simplified
+	//  "MMU" composed of a single statically-mapped way.
+	//  DTLB and ITLB are independent, so there's no single
+	//  cache attribute that can describe both.  So for now
+	//  just return the DTLB state.
+	movi	a5, 0xE0000000
+	movi	a2, 0
+	movi	a3, XCHAL_SPANNING_WAY
+1:	add	a3, a3, a5	// next segment
+	r&tlb&1	a4, a3		// get PPN+CA of segment at 0xE0000000, 0xC0000000, ..., 0
+	dsync	// interlock???
+	slli	a2, a2, 4
+	extui	a4, a4, 0, 4	// extract CA
+	or	a2, a2, a4
+	bgeui	a3, 16, 1b
+#else
+	//  This macro isn't applicable to arbitrary MMU configurations.
+	//  Just return zero.
+	movi	a2, 0
+#endif
+	.endm
+
+	.macro	icacheattr_get
+	_cacheattr_get	itlb
+	.endm
+
+	.macro	dcacheattr_get
+	_cacheattr_get	dtlb
+	.endm
+
+
+/* Default (powerup/reset) value of CACHEATTR,
+   all BYPASS mode (ie. disabled/bypassed caches): */
+#if XCHAL_HAVE_PTP_MMU
+# define XCHAL_CACHEATTR_ALL_BYPASS	0x33333333
+#else
+# define XCHAL_CACHEATTR_ALL_BYPASS	0x22222222
+#endif
+
+#if XCHAL_CA_8X512
+
+#if XCHAL_HAVE_PTP_MMU
+# define XCHAL_FCA_ENAMASK	0x0AA0	/* bitmap of fetch attributes that require enabled icache */
+# define XCHAL_LCA_ENAMASK	0x0FF0	/* bitmap of load  attributes that require enabled dcache */
+# define XCHAL_SCA_ENAMASK	0x0CC0	/* bitmap of store attributes that require enabled dcache */
+#else
+# define XCHAL_FCA_ENAMASK	0x003A	/* bitmap of fetch attributes that require enabled icache */
+# define XCHAL_LCA_ENAMASK	0x0033	/* bitmap of load  attributes that require enabled dcache */
+# define XCHAL_SCA_ENAMASK	0x0033	/* bitmap of store attributes that require enabled dcache */
+#endif
+#define XCHAL_LSCA_ENAMASK	(XCHAL_LCA_ENAMASK|XCHAL_SCA_ENAMASK)	/* l/s attrs requiring enabled dcache */
+#define XCHAL_ALLCA_ENAMASK	(XCHAL_FCA_ENAMASK|XCHAL_LSCA_ENAMASK)	/* all attrs requiring enabled caches */
+
+/*
+ *  _cacheattr_is_enabled
+ *
+ *  (Internal macro.)
+ *  Branches to \label if CACHEATTR in a2 indicates an enabled
+ *  cache, using mask in a3.
+ *
+ *  Parameters:
+ *	label	where to branch to if cache is enabled
+ *  Entry:
+ *	a2	contains CACHEATTR value used to determine whether
+ *		caches are enabled
+ *	a3	16-bit constant where each bit correspond to
+ *		one of the 16 possible CA values (in a CACHEATTR mask);
+ *		CA values that indicate the cache is enabled
+ *		have their corresponding bit set in this mask
+ *		(eg. use XCHAL_xCA_ENAMASK , above)
+ *  Exit:
+ *	a2,a4,a5	clobbered
+ *	SAR		clobbered
+ */
+	.macro	_cacheattr_is_enabled	label
+	movi	a4, 8		// loop 8 times
+.Lcaife\@:
+	extui	a5, a2, 0, 4	// get CA nibble
+	ssr	a5		// index into mask according to CA...
+	srl	a5, a3		// ...and get CA's mask bit in a5 bit 0
+	bbsi.l	a5, 0, \label	// if CA indicates cache enabled, jump to label
+	srli	a2, a2, 4	// next nibble
+	addi	a4, a4, -1
+	bnez	a4, .Lcaife\@	// loop for each nibble
+	.endm
+
+#else /* XCHAL_CA_8X512 */
+	.macro	_cacheattr_is_enabled	label
+	j	\label		// macro not applicable, assume caches always enabled
+	.endm
+#endif /* XCHAL_CA_8X512 */
+
+
+
+/*
+ *  icacheattr_is_enabled
+ *
+ *  Branches to \label if I-cache is enabled.
+ *
+ *  Parameters:
+ *	label	where to branch to if icache is enabled
+ *  Entry:
+ *	(none)
+ *  Exit:
+ *	a2-a5, SAR	clobbered (temporaries)
+ */
+	.macro	icacheattr_is_enabled	label
+#if XCHAL_CA_8X512
+	icacheattr_get
+	movi	a3, XCHAL_FCA_ENAMASK
+#endif
+	_cacheattr_is_enabled	\label
+	.endm
+
+/*
+ *  dcacheattr_is_enabled
+ *
+ *  Branches to \label if D-cache is enabled.
+ *
+ *  Parameters:
+ *	label	where to branch to if dcache is enabled
+ *  Entry:
+ *	(none)
+ *  Exit:
+ *	a2-a5, SAR	clobbered (temporaries)
+ */
+	.macro	dcacheattr_is_enabled	label
+#if XCHAL_CA_8X512
+	dcacheattr_get
+	movi	a3, XCHAL_LSCA_ENAMASK
+#endif
+	_cacheattr_is_enabled	\label
+	.endm
+
+/*
+ *  cacheattr_is_enabled
+ *
+ *  Branches to \label if either I-cache or D-cache is enabled.
+ *
+ *  Parameters:
+ *	label	where to branch to if a cache is enabled
+ *  Entry:
+ *	(none)
+ *  Exit:
+ *	a2-a5, SAR	clobbered (temporaries)
+ */
+	.macro	cacheattr_is_enabled	label
+#if XCHAL_HAVE_CACHEATTR
+	rsr	a2, CACHEATTR
+	movi	a3, XCHAL_ALLCA_ENAMASK
+#elif XCHAL_CA_8X512
+	icacheattr_get
+	movi	a3, XCHAL_FCA_ENAMASK
+	_cacheattr_is_enabled	\label
+	dcacheattr_get
+	movi	a3, XCHAL_LSCA_ENAMASK
+#endif
+	_cacheattr_is_enabled	\label
+	.endm
+
+
+
+/*
+ *  The ISA does not have a defined way to change the
+ *  instruction cache attributes of the running code,
+ *  ie. of the memory area that encloses the current PC.
+ *  However, each micro-architecture (or class of
+ *  configurations within a micro-architecture)
+ *  provides a way to deal with this issue.
+ *
+ *  Here are a few macros used to implement the relevant
+ *  approach taken.
+ */
+
+#if XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR
+	//  We have a config that "mimics" CACHEATTR using a simplified
+	//  "MMU" composed of a single statically-mapped way.
+
+/*
+ *  icacheattr_set
+ *
+ *  Entry:
+ *	a2		cacheattr value to set
+ *  Exit:
+ *	a2		unchanged
+ *	a3-a8		clobbered (temporaries)
+ */
+	.macro	icacheattr_set
+
+	movi	a5, 0xE0000000	// mask of upper 3 bits
+	movi	a6, 3f		// PC where ITLB is set
+	movi	a3, XCHAL_SPANNING_WAY	// start at region 0 (0 .. 7)
+	mov	a7, a2		// copy a2 so it doesn't get clobbered
+	and	a6, a6, a5	// upper 3 bits of local PC area
+	j	3f
+
+	//  Use micro-architecture specific method.
+	//  The following 4-instruction sequence is aligned such that
+	//  it all fits within a single I-cache line.  Sixteen byte
+	//  alignment is sufficient for this (using XCHAL_ICACHE_LINESIZE
+	//  actually causes problems because that can be greater than
+	//  the alignment of the reset vector, where this macro is often
+	//  invoked, which would cause the linker to align the reset
+	//  vector code away from the reset vector!!).
+	.begin	no-transform
+	.align	16 /*XCHAL_ICACHE_LINESIZE*/
+1:	witlb	a4, a3		// write wired PTE (CA, no PPN) of 512MB segment to ITLB
+	isync
+	.end	no-transform
+	nop
+	nop
+
+	sub	a3, a3, a5	// next segment (add 0x20000000)
+	bltui	a3, 16, 4f	// done?
+
+	//  Note that in the WITLB loop, we don't do any load/stores
+	//  (may not be an issue here, but it is important in the DTLB case).
+2:	srli	a7, a7, 4	// next CA
+3:
+# if XCHAL_HAVE_MIMIC_CACHEATTR
+	extui	a4, a7, 0, 4	// extract CA to set
+# else	/* have translation, preserve it: */
+	ritlb1	a8, a3		// get current PPN+CA of segment
+	//dsync	// interlock???
+	extui	a4, a7, 0, 4	// extract CA to set
+	srli	a8, a8, 4	// clear CA but keep PPN ...
+	slli	a8, a8, 4	// ...
+	add	a4, a4, a8	// combine new CA with PPN to preserve
+# endif
+	beq	a3, a6, 1b	// current PC's region? if so, do it in a safe way
+	witlb	a4, a3		// write wired PTE (CA [+PPN]) of 512MB segment to ITLB
+	sub	a3, a3, a5	// next segment (add 0x20000000)
+	bgeui	a3, 16, 2b
+	isync			// make sure all ifetch changes take effect
+4:
+	.endm	// icacheattr_set
+
+
+/*
+ *  dcacheattr_set
+ *
+ *  Entry:
+ *	a2		cacheattr value to set
+ *  Exit:
+ *	a2		unchanged
+ *	a3-a8		clobbered (temporaries)
+ */
+
+	.macro	dcacheattr_set
+
+	movi	a5, 0xE0000000	// mask of upper 3 bits
+	movi	a3, XCHAL_SPANNING_WAY	// start at region 0 (0 .. 7)
+	mov	a7, a2		// copy a2 so it doesn't get clobbered
+	//  Note that in the WDTLB loop, we don't do any load/stores
+2:	//  (including implicit l32r via movi) because it isn't safe.
+# if XCHAL_HAVE_MIMIC_CACHEATTR
+	extui	a4, a7, 0, 4	// extract CA to set
+# else	/* have translation, preserve it: */
+	rdtlb1	a8, a3		// get current PPN+CA of segment
+	//dsync	// interlock???
+	extui	a4, a7, 0, 4	// extract CA to set
+	srli	a8, a8, 4	// clear CA but keep PPN ...
+	slli	a8, a8, 4	// ...
+	add	a4, a4, a8	// combine new CA with PPN to preserve
+# endif
+	wdtlb	a4, a3		// write wired PTE (CA [+PPN]) of 512MB segment to DTLB
+	sub	a3, a3, a5	// next segment (add 0x20000000)
+	srli	a7, a7, 4	// next CA
+	bgeui	a3, 16, 2b
+	dsync			// make sure all data path changes take effect
+	.endm	// dcacheattr_set
+
+#endif /* XCHAL_CA_8X512 && !XCHAL_HAVE_CACHEATTR */
+
+
+
+/*
+ *  cacheattr_set
+ *
+ *  Macro that sets the current CACHEATTR safely
+ *  (both i and d) according to the current contents of a2.
+ *  It works even when changing the cache attributes of
+ *  the currently running code.
+ *
+ *  Entry:
+ *	a2		cacheattr value to set
+ *  Exit:
+ *	a2		unchanged
+ *	a3-a8		clobbered (temporaries)
+ */
+	.macro	cacheattr_set
+
+#if XCHAL_HAVE_CACHEATTR
+# if XCHAL_ICACHE_LINESIZE < 4
+	//  No i-cache, so can always safely write to CACHEATTR:
+	wsr	a2, CACHEATTR
+# else
+	//  The Athens micro-architecture, when using the old
+	//  exception architecture option (ie. with the CACHEATTR register)
+	//  allows changing the cache attributes of the running code
+	//  using the following exact sequence aligned to be within
+	//  an instruction cache line.  (NOTE: using XCHAL_ICACHE_LINESIZE
+	//  alignment actually causes problems because that can be greater
+	//  than the alignment of the reset vector, where this macro is often
+	//  invoked, which would cause the linker to align the reset
+	//  vector code away from the reset vector!!).
+	j	1f
+	.begin	no-transform
+	.align	16 /*XCHAL_ICACHE_LINESIZE*/	// align to within an I-cache line
+1:	wsr	a2, CACHEATTR
+	isync
+	.end	no-transform
+	nop
+	nop
+# endif
+#elif XCHAL_CA_8X512
+	//  DTLB and ITLB are independent, but to keep semantics
+	//  of this macro we simply write to both.
+	icacheattr_set
+	dcacheattr_set
+#else
+	//  This macro isn't applicable to arbitrary MMU configurations.
+	//  Do nothing in this case.
+#endif
+	.endm
+
+
+#endif /*XTENSA_CACHEATTRASM_H*/
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/config/core-isa.h

@@ -0,0 +1,459 @@
+/* 
+ * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
+ *				processor CORE configuration
+ *
+ *  See <xtensa/config/core.h>, which includes this file, for more details.
+ */
+
+/* Xtensa processor core configuration information.
+
+   Customer ID=7011; Build=0x2b6f6; Copyright (c) 1999-2010 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef _XTENSA_CORE_CONFIGURATION_H
+#define _XTENSA_CORE_CONFIGURATION_H
+
+
+/****************************************************************************
+	    Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/*
+ *  Note:  Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
+ *  configured, and a value of 0 otherwise.  These macros are always defined.
+ */
+
+
+/*----------------------------------------------------------------------
+				ISA
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_BE			0	/* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED		0	/* windowed registers option */
+#define XCHAL_NUM_AREGS			16	/* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2		4	/* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE	3	/* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG		1	/* debug option */
+#define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS		0	/* zero-overhead loops */
+#define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX		0	/* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT			0	/* SEXT instruction */
+#define XCHAL_HAVE_CLAMPS		0	/* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16		1	/* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32		1	/* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH		0	/* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32		0	/* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R			1	/* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS	1	/* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16		0	/* CONST16 instruction */
+#define XCHAL_HAVE_ADDX			1	/* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES	0	/* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES	0	/* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12		0	/* (obsolete option) */
+#define XCHAL_HAVE_ABS			1	/* ABS instruction */
+/*#define XCHAL_HAVE_POPC		0*/	/* POPC instruction */
+/*#define XCHAL_HAVE_CRC		0*/	/* CRC instruction */
+#define XCHAL_HAVE_RELEASE_SYNC		0	/* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I		0	/* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION		0	/* speculation */
+#define XCHAL_HAVE_FULL_RESET		1	/* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS		1	/* */
+#define XCHAL_NUM_MISC_REGS		0	/* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID			1	/* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
+#define XCHAL_HAVE_MP_INTERRUPTS	0	/* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL		0	/* core RunStall control port */
+#define XCHAL_HAVE_THREADPTR		0	/* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS		0	/* boolean registers */
+#define XCHAL_HAVE_CP			0	/* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG			0	/* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16		0	/* MAC16 package */
+#define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
+#define XCHAL_HAVE_FP			0	/* floating point pkg */
+#define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
+#define XCHAL_HAVE_DFP_accel		0	/* double precision FP acceleration pkg */
+#define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
+#define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
+#define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2		0	/* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
+
+
+/*----------------------------------------------------------------------
+				MISC
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES	1	/* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH		4	/* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH		4	/* data width in bytes */
+/*  In T1050, applies to selected core load and store instructions (see ISA): */
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
+
+#define XCHAL_SW_VERSION		800001	/* sw version of this header */
+
+#define XCHAL_CORE_ID			"lx106"	/* alphanum core name
+						   (CoreID) set in the Xtensa
+						   Processor Generator */
+
+#define XCHAL_BUILD_UNIQUE_ID		0x0002B6F6	/* 22-bit sw build ID */
+
+/*
+ *  These definitions describe the hardware targeted by this software.
+ */
+#define XCHAL_HW_CONFIGID0		0xC28CDAFA	/* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1		0x1082B6F6	/* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME		"LX3.0.1"	/* full version name */
+#define XCHAL_HW_VERSION_MAJOR		2300	/* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR		1	/* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION		230001	/* major*100+minor */
+#define XCHAL_HW_REL_LX3		1
+#define XCHAL_HW_REL_LX3_0		1
+#define XCHAL_HW_REL_LX3_0_1		1
+#define XCHAL_HW_CONFIGID_RELIABLE	1
+/*  If software targets a *range* of hardware versions, these are the bounds: */
+#define XCHAL_HW_MIN_VERSION_MAJOR	2300	/* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR	1	/* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION		230001	/* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR	2300	/* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR	1	/* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION		230001	/* latest targeted hw */
+
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_ICACHE_LINESIZE		4	/* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE		4	/* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH		2	/* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH		2	/* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE		0	/* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE		0	/* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK	0	/* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT	0	/* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
+
+
+
+
+/****************************************************************************
+    Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+				CACHE
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_PIF			1	/* any outbound PIF present */
+
+/*  If present, cache size in bytes == (ways * 2^(linewidth + setwidth)).  */
+
+/*  Number of cache sets in log2(lines per way):  */
+#define XCHAL_ICACHE_SETWIDTH		0
+#define XCHAL_DCACHE_SETWIDTH		0
+
+/*  Cache set associativity (number of ways):  */
+#define XCHAL_ICACHE_WAYS		1
+#define XCHAL_DCACHE_WAYS		1
+
+/*  Cache features:  */
+#define XCHAL_ICACHE_LINE_LOCKABLE	0
+#define XCHAL_DCACHE_LINE_LOCKABLE	0
+#define XCHAL_ICACHE_ECC_PARITY		0
+#define XCHAL_DCACHE_ECC_PARITY		0
+
+/*  Cache access size in bytes (affects operation of SICW instruction):  */
+#define XCHAL_ICACHE_ACCESS_SIZE	1
+#define XCHAL_DCACHE_ACCESS_SIZE	1
+
+/*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
+#define XCHAL_CA_BITS			4
+
+
+/*----------------------------------------------------------------------
+			INTERNAL I/D RAM/ROMs and XLMI
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_NUM_INSTROM		1	/* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM		2	/* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM		1	/* number of core data ROMs */
+#define XCHAL_NUM_DATARAM		2	/* number of core data RAMs */
+#define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI			1	/* number of core XLMI ports */
+
+/*  Instruction ROM 0:  */
+#define XCHAL_INSTROM0_VADDR		0x40200000
+#define XCHAL_INSTROM0_PADDR		0x40200000
+#define XCHAL_INSTROM0_SIZE		1048576
+#define XCHAL_INSTROM0_ECC_PARITY	0
+
+/*  Instruction RAM 0:  */
+#define XCHAL_INSTRAM0_VADDR		0x40000000
+#define XCHAL_INSTRAM0_PADDR		0x40000000
+#define XCHAL_INSTRAM0_SIZE		1048576
+#define XCHAL_INSTRAM0_ECC_PARITY	0
+
+/*  Instruction RAM 1:  */
+#define XCHAL_INSTRAM1_VADDR		0x40100000
+#define XCHAL_INSTRAM1_PADDR		0x40100000
+#define XCHAL_INSTRAM1_SIZE		1048576
+#define XCHAL_INSTRAM1_ECC_PARITY	0
+
+/*  Data ROM 0:  */
+#define XCHAL_DATAROM0_VADDR		0x3FF40000
+#define XCHAL_DATAROM0_PADDR		0x3FF40000
+#define XCHAL_DATAROM0_SIZE		262144
+#define XCHAL_DATAROM0_ECC_PARITY	0
+
+/*  Data RAM 0:  */
+#define XCHAL_DATARAM0_VADDR		0x3FFC0000
+#define XCHAL_DATARAM0_PADDR		0x3FFC0000
+#define XCHAL_DATARAM0_SIZE		262144
+#define XCHAL_DATARAM0_ECC_PARITY	0
+
+/*  Data RAM 1:  */
+#define XCHAL_DATARAM1_VADDR		0x3FF80000
+#define XCHAL_DATARAM1_PADDR		0x3FF80000
+#define XCHAL_DATARAM1_SIZE		262144
+#define XCHAL_DATARAM1_ECC_PARITY	0
+
+/*  XLMI Port 0:  */
+#define XCHAL_XLMI0_VADDR		0x3FF00000
+#define XCHAL_XLMI0_PADDR		0x3FF00000
+#define XCHAL_XLMI0_SIZE		262144
+#define XCHAL_XLMI0_ECC_PARITY	0
+
+
+/*----------------------------------------------------------------------
+			INTERRUPTS and TIMERS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_INTERRUPTS		1	/* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS	1	/* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI			1	/* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT		1	/* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS		1	/* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS		15	/* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2	4	/* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS		13	/* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS		2	/* number of interrupt levels
+						   (not including level zero) */
+#define XCHAL_EXCM_LEVEL		1	/* level masked by PS.EXCM */
+	/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/*  Masks of interrupts at each interrupt level:  */
+#define XCHAL_INTLEVEL1_MASK		0x00003FFF
+#define XCHAL_INTLEVEL2_MASK		0x00000000
+#define XCHAL_INTLEVEL3_MASK		0x00004000
+#define XCHAL_INTLEVEL4_MASK		0x00000000
+#define XCHAL_INTLEVEL5_MASK		0x00000000
+#define XCHAL_INTLEVEL6_MASK		0x00000000
+#define XCHAL_INTLEVEL7_MASK		0x00000000
+
+/*  Masks of interrupts at each range 1..n of interrupt levels:  */
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK	0x00003FFF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK	0x00003FFF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK	0x00007FFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK	0x00007FFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK	0x00007FFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK	0x00007FFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK	0x00007FFF
+
+/*  Level of each interrupt:  */
+#define XCHAL_INT0_LEVEL		1
+#define XCHAL_INT1_LEVEL		1
+#define XCHAL_INT2_LEVEL		1
+#define XCHAL_INT3_LEVEL		1
+#define XCHAL_INT4_LEVEL		1
+#define XCHAL_INT5_LEVEL		1
+#define XCHAL_INT6_LEVEL		1
+#define XCHAL_INT7_LEVEL		1
+#define XCHAL_INT8_LEVEL		1
+#define XCHAL_INT9_LEVEL		1
+#define XCHAL_INT10_LEVEL		1
+#define XCHAL_INT11_LEVEL		1
+#define XCHAL_INT12_LEVEL		1
+#define XCHAL_INT13_LEVEL		1
+#define XCHAL_INT14_LEVEL		3
+#define XCHAL_DEBUGLEVEL		2	/* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT	1	/* OCD external db interrupt */
+#define XCHAL_NMILEVEL			3	/* NMI "level" (for use with
+						   EXCSAVE/EPS/EPC_n, RFI n) */
+
+/*  Type of each interrupt:  */
+#define XCHAL_INT0_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE 	XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE 	XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE 	XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT9_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT10_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT11_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT12_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT13_TYPE 	XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT14_TYPE 	XTHAL_INTTYPE_NMI
+
+/*  Masks of interrupts for each type of interrupt:  */
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED	0xFFFF8000
+#define XCHAL_INTTYPE_MASK_SOFTWARE	0x00000080
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE	0x00003F00
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL	0x0000003F
+#define XCHAL_INTTYPE_MASK_TIMER	0x00000040
+#define XCHAL_INTTYPE_MASK_NMI		0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
+
+/*  Interrupt numbers assigned to specific interrupt sources:  */
+#define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_TIMER2_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_TIMER3_INTERRUPT		XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT		14	/* non-maskable interrupt */
+
+/*  Interrupt numbers for levels at which only one interrupt is configured:  */
+#define XCHAL_INTLEVEL3_NUM		14
+/*  (There are many interrupts each at level(s) 1.)  */
+
+
+/*
+ *  External interrupt vectors/levels.
+ *  These macros describe how Xtensa processor interrupt numbers
+ *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ *  map to external BInterrupt<n> pins, for those interrupts
+ *  configured as external (level-triggered, edge-triggered, or NMI).
+ *  See the Xtensa processor databook for more details.
+ */
+
+/*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
+#define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM		3	/* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM		4	/* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM		5	/* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM		8	/* (intlevel 1) */
+#define XCHAL_EXTINT7_NUM		9	/* (intlevel 1) */
+#define XCHAL_EXTINT8_NUM		10	/* (intlevel 1) */
+#define XCHAL_EXTINT9_NUM		11	/* (intlevel 1) */
+#define XCHAL_EXTINT10_NUM		12	/* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM		13	/* (intlevel 1) */
+#define XCHAL_EXTINT12_NUM		14	/* (intlevel 3) */
+
+
+/*----------------------------------------------------------------------
+			EXCEPTIONS and VECTORS
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
+						   number: 1 == XEA1 (old)
+							   2 == XEA2 (new)
+							   0 == XEAX (extern) */
+#define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
+#define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
+#define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR	0x40000000  /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR	0x40000000
+#define XCHAL_RESET_VECBASE_OVERLAP	0
+
+#define XCHAL_RESET_VECTOR0_VADDR	0x50000000
+#define XCHAL_RESET_VECTOR0_PADDR	0x50000000
+#define XCHAL_RESET_VECTOR1_VADDR	0x40000080
+#define XCHAL_RESET_VECTOR1_PADDR	0x40000080
+#define XCHAL_RESET_VECTOR_VADDR	0x50000000
+#define XCHAL_RESET_VECTOR_PADDR	0x50000000
+#define XCHAL_USER_VECOFS		0x00000050
+#define XCHAL_USER_VECTOR_VADDR		0x40000050
+#define XCHAL_USER_VECTOR_PADDR		0x40000050
+#define XCHAL_KERNEL_VECOFS		0x00000030
+#define XCHAL_KERNEL_VECTOR_VADDR	0x40000030
+#define XCHAL_KERNEL_VECTOR_PADDR	0x40000030
+#define XCHAL_DOUBLEEXC_VECOFS		0x00000070
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR	0x40000070
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR	0x40000070
+#define XCHAL_INTLEVEL2_VECOFS		0x00000010
+#define XCHAL_INTLEVEL2_VECTOR_VADDR	0x40000010
+#define XCHAL_INTLEVEL2_VECTOR_PADDR	0x40000010
+#define XCHAL_DEBUG_VECOFS		XCHAL_INTLEVEL2_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR	XCHAL_INTLEVEL2_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR	XCHAL_INTLEVEL2_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS		0x00000020
+#define XCHAL_NMI_VECTOR_VADDR		0x40000020
+#define XCHAL_NMI_VECTOR_PADDR		0x40000020
+#define XCHAL_INTLEVEL3_VECOFS		XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL3_VECTOR_VADDR	XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL3_VECTOR_PADDR	XCHAL_NMI_VECTOR_PADDR
+
+
+/*----------------------------------------------------------------------
+				DEBUG
+  ----------------------------------------------------------------------*/
+
+#define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
+#define XCHAL_NUM_IBREAK		1	/* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK		1	/* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option */
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*  See core-matmap.h header file for more details.  */
+
+#define XCHAL_HAVE_TLBS			1	/* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY		1	/* one way maps I+D 4GB vaddr */
+#define XCHAL_SPANNING_WAY		0	/* TLB spanning way number */
+#define XCHAL_HAVE_IDENTITY_MAP		1	/* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR		0	/* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR	1	/* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR	0	/* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU		0	/* full MMU (with page table
+						   [autorefill] and protection)
+						   usable for an MMU-based OS */
+/*  If none of the above last 4 are set, it's a custom TLB configuration.  */
+
+#define XCHAL_MMU_ASID_BITS		0	/* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS			1	/* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS		0	/* num of bits in RING field */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+#endif /* _XTENSA_CORE_CONFIGURATION_H */
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/config/core-matmap.h

@@ -0,0 +1,316 @@
+/* 
+ * xtensa/config/core-matmap.h -- Memory access and translation mapping
+ *	parameters (CHAL) of the Xtensa processor core configuration.
+ *
+ *  If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
+ *  this file) for more details.
+ *
+ *  In the Xtensa processor products released to date, all parameters
+ *  defined in this file are derivable (at least in theory) from
+ *  information contained in the core-isa.h header file.
+ *  In particular, the following core configuration parameters are relevant:
+ *	XCHAL_HAVE_CACHEATTR
+ *	XCHAL_HAVE_MIMIC_CACHEATTR
+ *	XCHAL_HAVE_XLT_CACHEATTR
+ *	XCHAL_HAVE_PTP_MMU
+ *	XCHAL_ITLB_ARF_ENTRIES_LOG2
+ *	XCHAL_DTLB_ARF_ENTRIES_LOG2
+ *	XCHAL_DCACHE_IS_WRITEBACK
+ *	XCHAL_ICACHE_SIZE		(presence of I-cache)
+ *	XCHAL_DCACHE_SIZE		(presence of D-cache)
+ *	XCHAL_HW_VERSION_MAJOR
+ *	XCHAL_HW_VERSION_MINOR
+ */
+
+/* Customer ID=7011; Build=0x2b6f6; Copyright (c) 1999-2010 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+
+#ifndef XTENSA_CONFIG_CORE_MATMAP_H
+#define XTENSA_CONFIG_CORE_MATMAP_H
+
+
+/*----------------------------------------------------------------------
+			CACHE (MEMORY ACCESS) ATTRIBUTES
+  ----------------------------------------------------------------------*/
+
+
+/*  Cache Attribute encodings -- lists of access modes for each cache attribute:  */
+#define XCHAL_FCA_LIST		XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_BYPASS	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_FAM_EXCEPTION
+#define XCHAL_LCA_LIST		XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_LAM_BYPASSG	XCHAL_SEP \
+				XTHAL_LAM_EXCEPTION
+#define XCHAL_SCA_LIST		XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION	XCHAL_SEP \
+				XTHAL_SAM_BYPASS	XCHAL_SEP \
+				XTHAL_SAM_EXCEPTION
+
+
+/*
+ *  Specific encoded cache attribute values of general interest.
+ *  If a specific cache mode is not available, the closest available
+ *  one is returned instead (eg. writethru instead of writeback,
+ *  bypass instead of writethru).
+ */
+#define XCHAL_CA_BYPASS  		2	/* cache disabled (bypassed) mode */
+#define XCHAL_CA_WRITETHRU		2	/* cache enabled (write-through) mode */
+#define XCHAL_CA_WRITEBACK		2	/* cache enabled (write-back) mode */
+#define XCHAL_CA_WRITEBACK_NOALLOC	2	/* cache enabled (write-back no-allocate) mode */
+#define XCHAL_CA_BYPASS_RW  		0	/* cache disabled (bypassed) mode (no exec) */
+#define XCHAL_CA_WRITETHRU_RW		0	/* cache enabled (write-through) mode (no exec) */
+#define XCHAL_CA_WRITEBACK_RW		0	/* cache enabled (write-back) mode (no exec) */
+#define XCHAL_CA_WRITEBACK_NOALLOC_RW	0	/* cache enabled (write-back no-allocate) mode (no exec) */
+#define XCHAL_CA_ILLEGAL		15	/* no access allowed (all cause exceptions) mode */
+#define XCHAL_CA_ISOLATE		0	/* cache isolate (accesses go to cache not memory) mode */
+
+
+/*----------------------------------------------------------------------
+				MMU
+  ----------------------------------------------------------------------*/
+
+/*
+ *  General notes on MMU parameters.
+ *
+ *  Terminology:
+ *	ASID = address-space ID (acts as an "extension" of virtual addresses)
+ *	VPN  = virtual page number
+ *	PPN  = physical page number
+ *	CA   = encoded cache attribute (access modes)
+ *	TLB  = translation look-aside buffer (term is stretched somewhat here)
+ *	I    = instruction (fetch accesses)
+ *	D    = data (load and store accesses)
+ *	way  = each TLB (ITLB and DTLB) consists of a number of "ways"
+ *		that simultaneously match the virtual address of an access;
+ *		a TLB successfully translates a virtual address if exactly
+ *		one way matches the vaddr; if none match, it is a miss;
+ *		if multiple match, one gets a "multihit" exception;
+ *		each way can be independently configured in terms of number of
+ *		entries, page sizes, which fields are writable or constant, etc.
+ *	set  = group of contiguous ways with exactly identical parameters
+ *	ARF  = auto-refill; hardware services a 1st-level miss by loading a PTE
+ *		from the page table and storing it in one of the auto-refill ways;
+ *		if this PTE load also misses, a miss exception is posted for s/w.
+ *	min-wired = a "min-wired" way can be used to map a single (minimum-sized)
+ * 		page arbitrarily under program control; it has a single entry,
+ *		is non-auto-refill (some other way(s) must be auto-refill),
+ *		all its fields (VPN, PPN, ASID, CA) are all writable, and it
+ *		supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
+ *		restriction is that this be the only page size it supports).
+ *
+ *  TLB way entries are virtually indexed.
+ *  TLB ways that support multiple page sizes:
+ *	- must have all writable VPN and PPN fields;
+ *	- can only use one page size at any given time (eg. setup at startup),
+ *	  selected by the respective ITLBCFG or DTLBCFG special register,
+ *	  whose bits n*4+3 .. n*4 index the list of page sizes for way n
+ *	  (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
+ *	  this list may be sparse for auto-refill ways because auto-refill
+ *	  ways have independent lists of supported page sizes sharing a
+ *	  common encoding with PTE entries; the encoding is the index into
+ *	  this list; unsupported sizes for a given way are zero in the list;
+ *	  selecting unsupported sizes results in undefined hardware behaviour;
+ *	- is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
+ */
+
+#define XCHAL_MMU_ASID_INVALID		0	/* ASID value indicating invalid address space */
+#define XCHAL_MMU_ASID_KERNEL		0	/* ASID value indicating kernel (ring 0) address space */
+#define XCHAL_MMU_SR_BITS		0	/* number of size-restriction bits supported */
+#define XCHAL_MMU_CA_BITS		4	/* number of bits needed to hold cache attribute encoding */
+#define XCHAL_MMU_MAX_PTE_PAGE_SIZE	29	/* max page size in a PTE structure (log2) */
+#define XCHAL_MMU_MIN_PTE_PAGE_SIZE	29	/* min page size in a PTE structure (log2) */
+
+
+/***  Instruction TLB:  ***/
+
+#define XCHAL_ITLB_WAY_BITS		0	/* number of bits holding the ways */
+#define XCHAL_ITLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
+#define XCHAL_ITLB_ARF_WAYS		0	/* number of auto-refill ways */
+#define XCHAL_ITLB_SETS			1	/* number of sets (groups of ways with identical settings) */
+
+/*  Way set to which each way belongs:  */
+#define XCHAL_ITLB_WAY0_SET		0
+
+/*  Ways sets that are used by hardware auto-refill (ARF):  */
+#define XCHAL_ITLB_ARF_SETS		0	/* number of auto-refill sets */
+
+/*  Way sets that are "min-wired" (see terminology comment above):  */
+#define XCHAL_ITLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
+
+
+/*  ITLB way set 0 (group of ways 0 thru 0):  */
+#define XCHAL_ITLB_SET0_WAY			0	/* index of first way in this way set */
+#define XCHAL_ITLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
+#define XCHAL_ITLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
+#define XCHAL_ITLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
+#define XCHAL_ITLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_ITLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
+#define XCHAL_ITLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
+#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
+							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_ITLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
+#define XCHAL_ITLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_ITLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
+/*  Constant VPN values for each entry of ITLB way set 0 (because VPN_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET0_E0_VPN_CONST		0x00000000
+#define XCHAL_ITLB_SET0_E1_VPN_CONST		0x20000000
+#define XCHAL_ITLB_SET0_E2_VPN_CONST		0x40000000
+#define XCHAL_ITLB_SET0_E3_VPN_CONST		0x60000000
+#define XCHAL_ITLB_SET0_E4_VPN_CONST		0x80000000
+#define XCHAL_ITLB_SET0_E5_VPN_CONST		0xA0000000
+#define XCHAL_ITLB_SET0_E6_VPN_CONST		0xC0000000
+#define XCHAL_ITLB_SET0_E7_VPN_CONST		0xE0000000
+/*  Constant PPN values for each entry of ITLB way set 0 (because PPN_CONSTMASK is non-zero):  */
+#define XCHAL_ITLB_SET0_E0_PPN_CONST		0x00000000
+#define XCHAL_ITLB_SET0_E1_PPN_CONST		0x20000000
+#define XCHAL_ITLB_SET0_E2_PPN_CONST		0x40000000
+#define XCHAL_ITLB_SET0_E3_PPN_CONST		0x60000000
+#define XCHAL_ITLB_SET0_E4_PPN_CONST		0x80000000
+#define XCHAL_ITLB_SET0_E5_PPN_CONST		0xA0000000
+#define XCHAL_ITLB_SET0_E6_PPN_CONST		0xC0000000
+#define XCHAL_ITLB_SET0_E7_PPN_CONST		0xE0000000
+/*  Reset CA values for each entry of ITLB way set 0 (because SET0_CA_RESET is non-zero):  */
+#define XCHAL_ITLB_SET0_E0_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E1_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E2_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E3_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E4_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E5_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E6_CA_RESET		0x02
+#define XCHAL_ITLB_SET0_E7_CA_RESET		0x02
+
+
+/***  Data TLB:  ***/
+
+#define XCHAL_DTLB_WAY_BITS		0	/* number of bits holding the ways */
+#define XCHAL_DTLB_WAYS			1	/* number of ways (n-way set-associative TLB) */
+#define XCHAL_DTLB_ARF_WAYS		0	/* number of auto-refill ways */
+#define XCHAL_DTLB_SETS			1	/* number of sets (groups of ways with identical settings) */
+
+/*  Way set to which each way belongs:  */
+#define XCHAL_DTLB_WAY0_SET		0
+
+/*  Ways sets that are used by hardware auto-refill (ARF):  */
+#define XCHAL_DTLB_ARF_SETS		0	/* number of auto-refill sets */
+
+/*  Way sets that are "min-wired" (see terminology comment above):  */
+#define XCHAL_DTLB_MINWIRED_SETS	0	/* number of "min-wired" sets */
+
+
+/*  DTLB way set 0 (group of ways 0 thru 0):  */
+#define XCHAL_DTLB_SET0_WAY			0	/* index of first way in this way set */
+#define XCHAL_DTLB_SET0_WAYS			1	/* number of (contiguous) ways in this way set */
+#define XCHAL_DTLB_SET0_ENTRIES_LOG2		3	/* log2(number of entries in this way) */
+#define XCHAL_DTLB_SET0_ENTRIES			8	/* number of entries in this way (always a power of 2) */
+#define XCHAL_DTLB_SET0_ARF			0	/* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
+#define XCHAL_DTLB_SET0_PAGESIZES		1	/* number of supported page sizes in this way */
+#define XCHAL_DTLB_SET0_PAGESZ_BITS		0	/* number of bits to encode the page size */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN		29	/* log2(minimum supported page size) */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX		29	/* log2(maximum supported page size) */
+#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST	29	/* list of log2(page size)s, separated by XCHAL_SEP;
+							   2^PAGESZ_BITS entries in list, unsupported entries are zero */
+#define XCHAL_DTLB_SET0_ASID_CONSTMASK		0	/* constant ASID bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_VPN_CONSTMASK		0x00000000	/* constant VPN bits, not including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_PPN_CONSTMASK		0xE0000000	/* constant PPN bits, including entry index bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_CA_CONSTMASK		0	/* constant CA bits; 0 if all writable */
+#define XCHAL_DTLB_SET0_ASID_RESET		0	/* 1 if ASID reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_VPN_RESET		0	/* 1 if VPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_PPN_RESET		0	/* 1 if PPN reset values defined (and all writable); 0 otherwise */
+#define XCHAL_DTLB_SET0_CA_RESET		1	/* 1 if CA reset values defined (and all writable); 0 otherwise */
+/*  Constant VPN values for each entry of DTLB way set 0 (because VPN_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET0_E0_VPN_CONST		0x00000000
+#define XCHAL_DTLB_SET0_E1_VPN_CONST		0x20000000
+#define XCHAL_DTLB_SET0_E2_VPN_CONST		0x40000000
+#define XCHAL_DTLB_SET0_E3_VPN_CONST		0x60000000
+#define XCHAL_DTLB_SET0_E4_VPN_CONST		0x80000000
+#define XCHAL_DTLB_SET0_E5_VPN_CONST		0xA0000000
+#define XCHAL_DTLB_SET0_E6_VPN_CONST		0xC0000000
+#define XCHAL_DTLB_SET0_E7_VPN_CONST		0xE0000000
+/*  Constant PPN values for each entry of DTLB way set 0 (because PPN_CONSTMASK is non-zero):  */
+#define XCHAL_DTLB_SET0_E0_PPN_CONST		0x00000000
+#define XCHAL_DTLB_SET0_E1_PPN_CONST		0x20000000
+#define XCHAL_DTLB_SET0_E2_PPN_CONST		0x40000000
+#define XCHAL_DTLB_SET0_E3_PPN_CONST		0x60000000
+#define XCHAL_DTLB_SET0_E4_PPN_CONST		0x80000000
+#define XCHAL_DTLB_SET0_E5_PPN_CONST		0xA0000000
+#define XCHAL_DTLB_SET0_E6_PPN_CONST		0xC0000000
+#define XCHAL_DTLB_SET0_E7_PPN_CONST		0xE0000000
+/*  Reset CA values for each entry of DTLB way set 0 (because SET0_CA_RESET is non-zero):  */
+#define XCHAL_DTLB_SET0_E0_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E1_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E2_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E3_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E4_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E5_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E6_CA_RESET		0x02
+#define XCHAL_DTLB_SET0_E7_CA_RESET		0x02
+
+
+
+
+#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/config/defs.h

@@ -0,0 +1,37 @@
+/* Definitions for Xtensa instructions, types, and protos. */
+
+/* Customer ID=7011; Build=0x2b6f6; Copyright (c) 2003-2004 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+/* NOTE: This file exists only for backward compatibility with T1050
+   and earlier Xtensa releases.  It includes only a subset of the
+   available header files.  */
+
+#ifndef _XTENSA_BASE_HEADER
+#define _XTENSA_BASE_HEADER
+
+#ifdef __XTENSA__
+
+#include <xtensa/tie/xt_core.h>
+#include <xtensa/tie/xt_misc.h>
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_BASE_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/config/specreg.h

@@ -0,0 +1,80 @@
+/*
+ * Xtensa Special Register symbolic names
+ */
+
+/* $Id: //depot/rel/Boreal/Xtensa/SWConfig/hal/specreg.h.tpp#2 $ */
+
+/* Customer ID=7011; Build=0x2b6f6; Copyright (c) 1998-2002 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef XTENSA_SPECREG_H
+#define XTENSA_SPECREG_H
+
+/*  Include these special register bitfield definitions, for historical reasons:  */
+#include <xtensa/corebits.h>
+
+
+/*  Special registers:  */
+#define SAR		3
+#define LITBASE		5
+#define IBREAKENABLE	96
+#define DDR		104
+#define IBREAKA_0	128
+#define DBREAKA_0	144
+#define DBREAKC_0	160
+#define EPC_1		177
+#define EPC_2		178
+#define EPC_3		179
+#define DEPC		192
+#define EPS_2		194
+#define EPS_3		195
+#define EXCSAVE_1	209
+#define EXCSAVE_2	210
+#define EXCSAVE_3	211
+#define INTERRUPT	226
+#define INTENABLE	228
+#define PS		230
+#define VECBASE		231
+#define EXCCAUSE	232
+#define DEBUGCAUSE	233
+#define CCOUNT		234
+#define PRID		235
+#define ICOUNT		236
+#define ICOUNTLEVEL	237
+#define EXCVADDR	238
+#define CCOMPARE_0	240
+
+/*  Special cases (bases of special register series):  */
+#define IBREAKA		128
+#define DBREAKA		144
+#define DBREAKC		160
+#define EPC		176
+#define EPS		192
+#define EXCSAVE		208
+#define CCOMPARE	240
+
+/*  Special names for read-only and write-only interrupt registers:  */
+#define INTREAD		226
+#define INTSET		226
+#define INTCLEAR	227
+
+#endif /* XTENSA_SPECREG_H */
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/config/system.h

@@ -0,0 +1,252 @@
+/* 
+ * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
+ *
+ *  NOTE: The location and contents of this file are highly subject to change.
+ *
+ *  Source for configuration-independent binaries (which link in a
+ *  configuration-specific HAL library) must NEVER include this file.
+ *  The HAL itself has historically included this file in some instances,
+ *  but this is not appropriate either, because the HAL is meant to be
+ *  core-specific but system independent.
+ */
+
+/* Customer ID=7011; Build=0x2b6f6; Copyright (c) 2000-2007 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+
+#ifndef XTENSA_CONFIG_SYSTEM_H
+#define XTENSA_CONFIG_SYSTEM_H
+
+/*#include <xtensa/hal.h>*/
+
+
+
+/*----------------------------------------------------------------------
+				CONFIGURED SOFTWARE OPTIONS
+  ----------------------------------------------------------------------*/
+
+#define XSHAL_USE_ABSOLUTE_LITERALS	0	/* (sw-only option, whether software uses absolute literals) */
+
+#define XSHAL_ABI			XTHAL_ABI_CALL0	/* (sw-only option, selected ABI) */
+/*  The above maps to one of the following constants:  */
+#define XTHAL_ABI_WINDOWED		0
+#define XTHAL_ABI_CALL0			1
+/*  Alternatives:  */
+/*#define XSHAL_WINDOWED_ABI		0*/	/* set if windowed ABI selected */
+/*#define XSHAL_CALL0_ABI		1*/	/* set if call0 ABI selected */
+
+#define XSHAL_CLIB			XTHAL_CLIB_NEWLIB	/* (sw-only option, selected C library) */
+/*  The above maps to one of the following constants:  */
+#define XTHAL_CLIB_NEWLIB		0
+#define XTHAL_CLIB_UCLIBC		1
+/*  Alternatives:  */
+/*#define XSHAL_NEWLIB			1*/	/* set if newlib C library selected */
+/*#define XSHAL_UCLIBC			0*/	/* set if uCLibC C library selected */
+
+#define XSHAL_USE_FLOATING_POINT	1
+
+/*----------------------------------------------------------------------
+				DEVICE ADDRESSES
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Strange place to find these, but the configuration GUI
+ *  allows moving these around to account for various core
+ *  configurations.  Specific boards (and their BSP software)
+ *  will have specific meanings for these components.
+ */
+
+/*  I/O Block areas:  */
+#define XSHAL_IOBLOCK_CACHED_VADDR	0x70000000
+#define XSHAL_IOBLOCK_CACHED_PADDR	0x70000000
+#define XSHAL_IOBLOCK_CACHED_SIZE	0x0E000000
+
+#define XSHAL_IOBLOCK_BYPASS_VADDR	0x90000000
+#define XSHAL_IOBLOCK_BYPASS_PADDR	0x90000000
+#define XSHAL_IOBLOCK_BYPASS_SIZE	0x0E000000
+
+/*  System ROM:  */
+#define XSHAL_ROM_VADDR		0x50000000
+#define XSHAL_ROM_PADDR		0x50000000
+#define XSHAL_ROM_SIZE		0x01000000
+/*  Largest available area (free of vectors):  */
+#define XSHAL_ROM_AVAIL_VADDR	0x50000300
+#define XSHAL_ROM_AVAIL_VSIZE	0x00FFFD00
+
+/*  System RAM:  */
+#define XSHAL_RAM_VADDR		0x60000000
+#define XSHAL_RAM_PADDR		0x60000000
+#define XSHAL_RAM_VSIZE		0x04000000
+#define XSHAL_RAM_PSIZE		0x04000000
+#define XSHAL_RAM_SIZE		XSHAL_RAM_PSIZE
+/*  Largest available area (free of vectors):  */
+#define XSHAL_RAM_AVAIL_VADDR	0x60000000
+#define XSHAL_RAM_AVAIL_VSIZE	0x04000000
+
+/*
+ *  Shadow system RAM (same device as system RAM, at different address).
+ *  (Emulation boards need this for the SONIC Ethernet driver
+ *   when data caches are configured for writeback mode.)
+ *  NOTE: on full MMU configs, this points to the BYPASS virtual address
+ *  of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
+ *  addresses are viewed through the BYPASS static map rather than
+ *  the CACHED static map.
+ */
+#define XSHAL_RAM_BYPASS_VADDR		0xA0000000
+#define XSHAL_RAM_BYPASS_PADDR		0xA0000000
+#define XSHAL_RAM_BYPASS_PSIZE		0x04000000
+
+/*  Alternate system RAM (different device than system RAM):  */
+/*#define XSHAL_ALTRAM_[VP]ADDR		...not configured...*/
+/*#define XSHAL_ALTRAM_SIZE		...not configured...*/
+
+/*  Some available location in which to place devices in a simulation (eg. XTMP):  */
+#define XSHAL_SIMIO_CACHED_VADDR	0xC0000000
+#define XSHAL_SIMIO_BYPASS_VADDR	0xC0000000
+#define XSHAL_SIMIO_PADDR		0xC0000000
+#define XSHAL_SIMIO_SIZE		0x20000000
+
+
+/*----------------------------------------------------------------------
+ *			DEVICE-ADDRESS DEPENDENT...
+ *
+ *  Values written to CACHEATTR special register (or its equivalent)
+ *  to enable and disable caches in various modes.
+ *----------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------
+			BACKWARD COMPATIBILITY ...
+  ----------------------------------------------------------------------*/
+
+/*
+ *  NOTE:  the following two macros are DEPRECATED.  Use the latter
+ *  board-specific macros instead, which are specially tuned for the
+ *  particular target environments' memory maps.
+ */
+#define XSHAL_CACHEATTR_BYPASS		XSHAL_XT2000_CACHEATTR_BYPASS	/* disable caches in bypass mode */
+#define XSHAL_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_DEFAULT	/* default setting to enable caches (no writeback!) */
+
+/*----------------------------------------------------------------------
+				GENERIC
+  ----------------------------------------------------------------------*/
+
+/*  For the following, a 512MB region is used if it contains a system (PIF) RAM,
+ *  system (PIF) ROM, local memory, or XLMI.  */
+
+/*  These set any unused 512MB region to cache-BYPASS attribute:  */
+#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK	0x22221112	/* enable caches in write-back mode */
+#define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC	0x22221112	/* enable caches in write-allocate mode */
+#define XSHAL_ALLVALID_CACHEATTR_WRITETHRU	0x22221112	/* enable caches in write-through mode */
+#define XSHAL_ALLVALID_CACHEATTR_BYPASS		0x22222222	/* disable caches in bypass mode */
+#define XSHAL_ALLVALID_CACHEATTR_DEFAULT	XSHAL_ALLVALID_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+/*  These set any unused 512MB region to ILLEGAL attribute:  */
+#define XSHAL_STRICT_CACHEATTR_WRITEBACK	0xFFFF111F	/* enable caches in write-back mode */
+#define XSHAL_STRICT_CACHEATTR_WRITEALLOC	0xFFFF111F	/* enable caches in write-allocate mode */
+#define XSHAL_STRICT_CACHEATTR_WRITETHRU	0xFFFF111F	/* enable caches in write-through mode */
+#define XSHAL_STRICT_CACHEATTR_BYPASS		0xFFFF222F	/* disable caches in bypass mode */
+#define XSHAL_STRICT_CACHEATTR_DEFAULT		XSHAL_STRICT_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+/*  These set the first 512MB, if unused, to ILLEGAL attribute to help catch
+ *  NULL-pointer dereference bugs; all other unused 512MB regions are set
+ *  to cache-BYPASS attribute:  */
+#define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	0x2222111F	/* enable caches in write-back mode */
+#define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC	0x2222111F	/* enable caches in write-allocate mode */
+#define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU	0x2222111F	/* enable caches in write-through mode */
+#define XSHAL_TRAPNULL_CACHEATTR_BYPASS		0x2222222F	/* disable caches in bypass mode */
+#define XSHAL_TRAPNULL_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+/*----------------------------------------------------------------------
+			ISS (Instruction Set Simulator) SPECIFIC ...
+  ----------------------------------------------------------------------*/
+
+/*  For now, ISS defaults to the TRAPNULL settings:  */
+#define XSHAL_ISS_CACHEATTR_WRITEBACK	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
+#define XSHAL_ISS_CACHEATTR_WRITEALLOC	XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC
+#define XSHAL_ISS_CACHEATTR_WRITETHRU	XSHAL_TRAPNULL_CACHEATTR_WRITETHRU
+#define XSHAL_ISS_CACHEATTR_BYPASS	XSHAL_TRAPNULL_CACHEATTR_BYPASS
+#define XSHAL_ISS_CACHEATTR_DEFAULT	XSHAL_TRAPNULL_CACHEATTR_WRITEBACK
+
+#define XSHAL_ISS_PIPE_REGIONS	0
+#define XSHAL_ISS_SDRAM_REGIONS	0
+
+
+/*----------------------------------------------------------------------
+			XT2000 BOARD SPECIFIC ...
+  ----------------------------------------------------------------------*/
+
+/*  For the following, a 512MB region is used if it contains any system RAM,
+ *  system ROM, local memory, XLMI, or other XT2000 board device or memory.
+ *  Regions containing devices are forced to cache-BYPASS mode regardless
+ *  of whether the macro is _WRITEBACK vs. _BYPASS etc.  */
+
+/*  These set any 512MB region unused on the XT2000 to ILLEGAL attribute:  */
+#define XSHAL_XT2000_CACHEATTR_WRITEBACK	0xFF22111F	/* enable caches in write-back mode */
+#define XSHAL_XT2000_CACHEATTR_WRITEALLOC	0xFF22111F	/* enable caches in write-allocate mode */
+#define XSHAL_XT2000_CACHEATTR_WRITETHRU	0xFF22111F	/* enable caches in write-through mode */
+#define XSHAL_XT2000_CACHEATTR_BYPASS		0xFF22222F	/* disable caches in bypass mode */
+#define XSHAL_XT2000_CACHEATTR_DEFAULT		XSHAL_XT2000_CACHEATTR_WRITEBACK	/* default setting to enable caches */
+
+#define XSHAL_XT2000_PIPE_REGIONS	0x00000000	/* BusInt pipeline regions */
+#define XSHAL_XT2000_SDRAM_REGIONS	0x00000440	/* BusInt SDRAM regions */
+
+
+/*----------------------------------------------------------------------
+				VECTOR INFO AND SIZES
+  ----------------------------------------------------------------------*/
+
+#define XSHAL_VECTORS_PACKED		0
+#define XSHAL_STATIC_VECTOR_SELECT	0
+#define XSHAL_RESET_VECTOR_VADDR	0x50000000
+#define XSHAL_RESET_VECTOR_PADDR	0x50000000
+
+/*
+ *  Sizes allocated to vectors by the system (memory map) configuration.
+ *  These sizes are constrained by core configuration (eg. one vector's
+ *  code cannot overflow into another vector) but are dependent on the
+ *  system or board (or LSP) memory map configuration.
+ *
+ *  Whether or not each vector happens to be in a system ROM is also
+ *  a system configuration matter, sometimes useful, included here also:
+ */
+#define XSHAL_RESET_VECTOR_SIZE	0x00000300
+#define XSHAL_RESET_VECTOR_ISROM	1
+#define XSHAL_USER_VECTOR_SIZE	0x0000001C
+#define XSHAL_USER_VECTOR_ISROM	0
+#define XSHAL_PROGRAMEXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_USEREXC_VECTOR_SIZE	XSHAL_USER_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_KERNEL_VECTOR_SIZE	0x0000001C
+#define XSHAL_KERNEL_VECTOR_ISROM	0
+#define XSHAL_STACKEDEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_KERNELEXC_VECTOR_SIZE	XSHAL_KERNEL_VECTOR_SIZE	/* for backward compatibility */
+#define XSHAL_DOUBLEEXC_VECTOR_SIZE	0x00000010
+#define XSHAL_DOUBLEEXC_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL2_VECTOR_SIZE	0x0000000C
+#define XSHAL_INTLEVEL2_VECTOR_ISROM	0
+#define XSHAL_DEBUG_VECTOR_SIZE		XSHAL_INTLEVEL2_VECTOR_SIZE
+#define XSHAL_DEBUG_VECTOR_ISROM	XSHAL_INTLEVEL2_VECTOR_ISROM
+#define XSHAL_NMI_VECTOR_SIZE	0x0000000C
+#define XSHAL_NMI_VECTOR_ISROM	0
+#define XSHAL_INTLEVEL3_VECTOR_SIZE	XSHAL_NMI_VECTOR_SIZE
+
+
+#endif /*XTENSA_CONFIG_SYSTEM_H*/
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/config/tie-asm.h

@@ -0,0 +1,77 @@
+/* 
+ * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE
+ *
+ *  NOTE:  This header file is not meant to be included directly.
+ */
+
+/* This header file contains assembly-language definitions (assembly
+   macros, etc.) for this specific Xtensa processor's TIE extensions
+   and options.  It is customized to this Xtensa processor configuration.
+
+   Customer ID=7011; Build=0x2b6f6; Copyright (c) 1999-2010 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef _XTENSA_CORE_TIE_ASM_H
+#define _XTENSA_CORE_TIE_ASM_H
+
+/*  Selection parameter values for save-area save/restore macros:  */
+/*  Option vs. TIE:  */
+#define XTHAL_SAS_TIE	0x0001	/* custom extension or coprocessor */
+#define XTHAL_SAS_OPT	0x0002	/* optional (and not a coprocessor) */
+/*  Whether used automatically by compiler:  */
+#define XTHAL_SAS_NOCC	0x0004	/* not used by compiler w/o special opts/code */
+#define XTHAL_SAS_CC	0x0008	/* used by compiler without special opts/code */
+/*  ABI handling across function calls:  */
+#define XTHAL_SAS_CALR	0x0010	/* caller-saved */
+#define XTHAL_SAS_CALE	0x0020	/* callee-saved */
+#define XTHAL_SAS_GLOB	0x0040	/* global across function calls (in thread) */
+/*  Misc  */
+#define XTHAL_SAS_ALL	0xFFFF	/* include all default NCP contents */
+
+
+
+/* Macro to save all non-coprocessor (extra) custom TIE and optional state
+ * (not including zero-overhead loop registers).
+ * Save area ptr (clobbered):  ptr  (1 byte aligned)
+ * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_NCP_NUM_ATMPS needed)
+ */
+	.macro xchal_ncp_store  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
+	xchal_sa_start	\continue, \ofs
+	.endm	// xchal_ncp_store
+
+/* Macro to save all non-coprocessor (extra) custom TIE and optional state
+ * (not including zero-overhead loop registers).
+ * Save area ptr (clobbered):  ptr  (1 byte aligned)
+ * Scratch regs  (clobbered):  at1..at4  (only first XCHAL_NCP_NUM_ATMPS needed)
+ */
+	.macro xchal_ncp_load  ptr at1 at2 at3 at4  continue=0 ofs=-1 select=XTHAL_SAS_ALL
+	xchal_sa_start	\continue, \ofs
+	.endm	// xchal_ncp_load
+
+
+
+#define XCHAL_NCP_NUM_ATMPS	0
+
+
+#define XCHAL_SA_NUM_ATMPS	0
+
+#endif /*_XTENSA_CORE_TIE_ASM_H*/
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/config/tie.h

@@ -0,0 +1,119 @@
+/* 
+ * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration
+ *
+ *  NOTE:  This header file is not meant to be included directly.
+ */
+
+/* This header file describes this specific Xtensa processor's TIE extensions
+   that extend basic Xtensa core functionality.  It is customized to this
+   Xtensa processor configuration.
+
+   Customer ID=7011; Build=0x2b6f6; Copyright (c) 1999-2010 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef _XTENSA_CORE_TIE_H
+#define _XTENSA_CORE_TIE_H
+
+#define XCHAL_CP_NUM			0	/* number of coprocessors */
+#define XCHAL_CP_MAX			0	/* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK			0x00	/* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK		0x00	/* bitmask of only port CPs */
+
+/*  Save area for non-coprocessor optional and custom (TIE) state:  */
+#define XCHAL_NCP_SA_SIZE		0
+#define XCHAL_NCP_SA_ALIGN		1
+
+/*  Total save area for optional and custom state (NCP + CPn):  */
+#define XCHAL_TOTAL_SA_SIZE		0	/* with 16-byte align padding */
+#define XCHAL_TOTAL_SA_ALIGN		1	/* actual minimum alignment */
+
+/*
+ * Detailed contents of save areas.
+ * NOTE:  caller must define the XCHAL_SA_REG macro (not defined here)
+ * before expanding the XCHAL_xxx_SA_LIST() macros.
+ *
+ * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
+ *		dbnum,base,regnum,bitsz,gapsz,reset,x...)
+ *
+ *	s = passed from XCHAL_*_LIST(s), eg. to select how to expand
+ *	ccused = set if used by compiler without special options or code
+ *	abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
+ *	kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
+ *	opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
+ *	name = lowercase reg name (no quotes)
+ *	galign = group byte alignment (power of 2) (galign >= align)
+ *	align = register byte alignment (power of 2)
+ *	asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
+ *	  (not including any pad bytes required to galign this or next reg)
+ *	dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
+ *	base = reg shortname w/o index (or sr=special, ur=TIE user reg)
+ *	regnum = reg index in regfile, or special/TIE-user reg number
+ *	bitsz = number of significant bits (regfile width, or ur/sr mask bits)
+ *	gapsz = intervening bits, if bitsz bits not stored contiguously
+ *	(padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
+ *	reset = register reset value (or 0 if undefined at reset)
+ *	x = reserved for future use (0 until then)
+ *
+ *  To filter out certain registers, e.g. to expand only the non-global
+ *  registers used by the compiler, you can do something like this:
+ *
+ *  #define XCHAL_SA_REG(s,ccused,p...)	SELCC##ccused(p)
+ *  #define SELCC0(p...)
+ *  #define SELCC1(abikind,p...)	SELAK##abikind(p)
+ *  #define SELAK0(p...)		REG(p)
+ *  #define SELAK1(p...)		REG(p)
+ *  #define SELAK2(p...)
+ *  #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
+ *		...what you want to expand...
+ */
+
+#define XCHAL_NCP_SA_NUM	0
+#define XCHAL_NCP_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP0_SA_NUM	0
+#define XCHAL_CP0_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP1_SA_NUM	0
+#define XCHAL_CP1_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP2_SA_NUM	0
+#define XCHAL_CP2_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP3_SA_NUM	0
+#define XCHAL_CP3_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP4_SA_NUM	0
+#define XCHAL_CP4_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP5_SA_NUM	0
+#define XCHAL_CP5_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP6_SA_NUM	0
+#define XCHAL_CP6_SA_LIST(s)	/* empty */
+
+#define XCHAL_CP7_SA_NUM	0
+#define XCHAL_CP7_SA_LIST(s)	/* empty */
+
+/* Byte length of instruction from its first nibble (op0 field), per FLIX.  */
+#define XCHAL_OP0_FORMAT_LENGTHS	3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
+
+#endif /*_XTENSA_CORE_TIE_H*/
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/coreasm.h

@@ -0,0 +1,914 @@
+/*
+ * xtensa/coreasm.h -- assembler-specific definitions that depend on CORE configuration
+ *
+ *  Source for configuration-independent binaries (which link in a
+ *  configuration-specific HAL library) must NEVER include this file.
+ *  It is perfectly normal, however, for the HAL itself to include this file.
+ *
+ *  This file must NOT include xtensa/config/system.h.  Any assembler
+ *  header file that depends on system information should likely go
+ *  in a new systemasm.h (or sysasm.h) header file.
+ *
+ *  NOTE: macro beqi32 is NOT configuration-dependent, and is placed
+ *        here until we have a proper configuration-independent header file.
+ */
+
+/* $Id: //depot/rel/Boreal/Xtensa/OS/include/xtensa/coreasm.h#2 $ */
+
+/*
+ * Copyright (c) 2000-2007 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_COREASM_H
+#define XTENSA_COREASM_H
+
+/*
+ *  Tell header files this is assembly source, so they can avoid non-assembler
+ *  definitions (eg. C types etc):
+ */
+#ifndef _ASMLANGUAGE	/* conditionalize to avoid cpp warnings (3rd parties might use same macro) */
+#define _ASMLANGUAGE
+#endif
+
+#include <xtensa/config/core.h>
+#include <xtensa/config/specreg.h>
+
+/*
+ *  Assembly-language specific definitions (assembly macros, etc.).
+ */
+
+/*----------------------------------------------------------------------
+ *  find_ms_setbit
+ *
+ *  This macro finds the most significant bit that is set in <as>
+ *  and return its index + <base> in <ad>, or <base> - 1 if <as> is zero.
+ *  The index counts starting at zero for the lsbit, so the return
+ *  value ranges from <base>-1 (no bit set) to <base>+31 (msbit set).
+ *
+ *  Parameters:
+ *	<ad>	destination address register (any register)
+ *	<as>	source address register
+ *	<at>	temporary address register (must be different than <as>)
+ *	<base>	constant value added to result (usually 0 or 1)
+ *  On entry:
+ *	<ad> = undefined if different than <as>
+ *	<as> = value whose most significant set bit is to be found
+ *	<at> = undefined
+ *	no other registers are used by this macro.
+ *  On exit:
+ *	<ad> = <base> + index of msbit set in original <as>,
+ *	     = <base> - 1 if original <as> was zero.
+ *	<as> clobbered (if not <ad>)
+ *	<at> clobbered (if not <ad>)
+ *  Example:
+ *	find_ms_setbit a0, a4, a0, 0		-- return in a0 index of msbit set in a4
+ */
+
+	.macro	find_ms_setbit ad, as, at, base
+#if XCHAL_HAVE_NSA
+	movi	\at, 31+\base
+	nsau	\as, \as	// get index of \as, numbered from msbit (32 if absent)
+	sub	\ad, \at, \as	// get numbering from lsbit (0..31, -1 if absent)
+#else /* XCHAL_HAVE_NSA */
+	movi	\at, \base	// start with result of 0 (point to lsbit of 32)
+
+	beqz	\as, 2f		// special case for zero argument: return -1
+	bltui	\as, 0x10000, 1f	// is it one of the 16 lsbits? (if so, check lower 16 bits)
+	addi	\at, \at, 16	// no, increment result to upper 16 bits (of 32)
+	//srli	\as, \as, 16	// check upper half (shift right 16 bits)
+	extui	\as, \as, 16, 16	// check upper half (shift right 16 bits)
+1:	bltui	\as, 0x100, 1f	// is it one of the 8 lsbits? (if so, check lower 8 bits)
+	addi	\at, \at, 8	// no, increment result to upper 8 bits (of 16)
+	srli	\as, \as, 8	// shift right to check upper 8 bits
+1:	bltui	\as, 0x10, 1f	// is it one of the 4 lsbits? (if so, check lower 4 bits)
+	addi	\at, \at, 4	// no, increment result to upper 4 bits (of 8)
+	srli	\as, \as, 4	// shift right 4 bits to check upper half
+1:	bltui	\as, 0x4, 1f	// is it one of the 2 lsbits? (if so, check lower 2 bits)
+	addi	\at, \at, 2	// no, increment result to upper 2 bits (of 4)
+	srli	\as, \as, 2	// shift right 2 bits to check upper half
+1:	bltui	\as, 0x2, 1f	// is it the lsbit?
+	addi	\at, \at, 2	// no, increment result to upper bit (of 2)
+2:	addi	\at, \at, -1	// (from just above: add 1;  from beqz: return -1)
+	//srli	\as, \as, 1
+1:				// done! \at contains index of msbit set (or -1 if none set)
+	.if	0x\ad - 0x\at	// destination different than \at ? (works because regs are a0-a15)
+	mov	\ad, \at	// then move result to \ad
+	.endif
+#endif /* XCHAL_HAVE_NSA */
+	.endm	// find_ms_setbit
+
+/*----------------------------------------------------------------------
+ *  find_ls_setbit
+ *
+ *  This macro finds the least significant bit that is set in <as>,
+ *  and return its index in <ad>.
+ *  Usage is the same as for the find_ms_setbit macro.
+ *  Example:
+ *	find_ls_setbit a0, a4, a0, 0	-- return in a0 index of lsbit set in a4
+ */
+
+	.macro	find_ls_setbit ad, as, at, base
+	neg	\at, \as	// keep only the least-significant bit that is set...
+	and	\as, \at, \as	// ... in \as
+	find_ms_setbit	\ad, \as, \at, \base
+	.endm	// find_ls_setbit
+
+/*----------------------------------------------------------------------
+ *  find_ls_one
+ *
+ *  Same as find_ls_setbit with base zero.
+ *  Source (as) and destination (ad) registers must be different.
+ *  Provided for backward compatibility.
+ */
+
+	.macro	find_ls_one ad, as
+	find_ls_setbit	\ad, \as, \ad, 0
+	.endm	// find_ls_one
+
+/*----------------------------------------------------------------------
+ *  floop, floopnez, floopgtz, floopend
+ *
+ *  These macros are used for fast inner loops that
+ *  work whether or not the Loops options is configured.
+ *  If the Loops option is configured, they simply use
+ *  the zero-overhead LOOP instructions; otherwise
+ *  they use explicit decrement and branch instructions.
+ *
+ *  They are used in pairs, with floop, floopnez or floopgtz
+ *  at the beginning of the loop, and floopend at the end.
+ *
+ *  Each pair of loop macro calls must be given the loop count
+ *  address register and a unique label for that loop.
+ *
+ *  Example:
+ *
+ *	movi	 a3, 16     // loop 16 times
+ *	floop    a3, myloop1
+ *	:
+ *	bnez     a7, end1	// exit loop if a7 != 0
+ *	:
+ *	floopend a3, myloop1
+ *  end1:
+ *
+ *  Like the LOOP instructions, these macros cannot be
+ *  nested, must include at least one instruction,
+ *  cannot call functions inside the loop, etc.
+ *  The loop can be exited by jumping to the instruction
+ *  following floopend (or elsewhere outside the loop),
+ *  or continued by jumping to a NOP instruction placed
+ *  immediately before floopend.
+ *
+ *  Unlike LOOP instructions, the register passed to floop*
+ *  cannot be used inside the loop, because it is used as
+ *  the loop counter if the Loops option is not configured.
+ *  And its value is undefined after exiting the loop.
+ *  And because the loop counter register is active inside
+ *  the loop, you can't easily use this construct to loop
+ *  across a register file using ROTW as you might with LOOP
+ *  instructions, unless you copy the loop register along.
+ */
+
+	/*  Named label version of the macros:  */
+
+	.macro	floop		ar, endlabel
+	floop_		\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+	.endm
+
+	.macro	floopnez	ar, endlabel
+	floopnez_	\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+	.endm
+
+	.macro	floopgtz	ar, endlabel
+	floopgtz_	\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+	.endm
+
+	.macro	floopend	ar, endlabel
+	floopend_	\ar, .Lfloopstart_\endlabel, .Lfloopend_\endlabel
+	.endm
+
+	/*  Numbered local label version of the macros:  */
+#if 0 /*UNTESTED*/
+	.macro	floop89		ar
+	floop_		\ar, 8, 9f
+	.endm
+
+	.macro	floopnez89	ar
+	floopnez_	\ar, 8, 9f
+	.endm
+
+	.macro	floopgtz89	ar
+	floopgtz_	\ar, 8, 9f
+	.endm
+
+	.macro	floopend89	ar
+	floopend_	\ar, 8b, 9
+	.endm
+#endif /*0*/
+
+	/*  Underlying version of the macros:  */
+
+	.macro	floop_	ar, startlabel, endlabelref
+	.ifdef	_infloop_
+	.if	_infloop_
+	.err	// Error: floop cannot be nested
+	.endif
+	.endif
+	.set	_infloop_, 1
+#if XCHAL_HAVE_LOOPS
+	loop	\ar, \endlabelref
+#else /* XCHAL_HAVE_LOOPS */
+\startlabel:
+	addi	\ar, \ar, -1
+#endif /* XCHAL_HAVE_LOOPS */
+	.endm	// floop_
+
+	.macro	floopnez_	ar, startlabel, endlabelref
+	.ifdef	_infloop_
+	.if	_infloop_
+	.err	// Error: floopnez cannot be nested
+	.endif
+	.endif
+	.set	_infloop_, 1
+#if XCHAL_HAVE_LOOPS
+	loopnez	\ar, \endlabelref
+#else /* XCHAL_HAVE_LOOPS */
+	beqz	\ar, \endlabelref
+\startlabel:
+	addi	\ar, \ar, -1
+#endif /* XCHAL_HAVE_LOOPS */
+	.endm	// floopnez_
+
+	.macro	floopgtz_	ar, startlabel, endlabelref
+	.ifdef	_infloop_
+	.if	_infloop_
+	.err	// Error: floopgtz cannot be nested
+	.endif
+	.endif
+	.set	_infloop_, 1
+#if XCHAL_HAVE_LOOPS
+	loopgtz	\ar, \endlabelref
+#else /* XCHAL_HAVE_LOOPS */
+	bltz	\ar, \endlabelref
+	beqz	\ar, \endlabelref
+\startlabel:
+	addi	\ar, \ar, -1
+#endif /* XCHAL_HAVE_LOOPS */
+	.endm	// floopgtz_
+
+
+	.macro	floopend_	ar, startlabelref, endlabel
+	.ifndef	_infloop_
+	.err	// Error: floopend without matching floopXXX
+	.endif
+	.ifeq	_infloop_
+	.err	// Error: floopend without matching floopXXX
+	.endif
+	.set	_infloop_, 0
+#if ! XCHAL_HAVE_LOOPS
+	bnez	\ar, \startlabelref
+#endif /* XCHAL_HAVE_LOOPS */
+\endlabel:
+	.endm	// floopend_
+
+/*----------------------------------------------------------------------
+ *  crsil  --  conditional RSIL (read/set interrupt level)
+ *
+ *  Executes the RSIL instruction if it exists, else just reads PS.
+ *  The RSIL instruction does not exist in the new exception architecture
+ *  if the interrupt option is not selected.
+ */
+
+	.macro	crsil	ar, newlevel
+#if XCHAL_HAVE_OLD_EXC_ARCH || XCHAL_HAVE_INTERRUPTS
+	rsil	\ar, \newlevel
+#else
+	rsr	\ar, PS
+#endif
+	.endm	// crsil
+
+/*----------------------------------------------------------------------
+ *  safe_movi_a0  --  move constant into a0 when L32R is not safe
+ *
+ *  This macro is typically used by interrupt/exception handlers.
+ *  Loads a 32-bit constant in a0, without using any other register,
+ *  and without corrupting the LITBASE register, even when the
+ *  value of the LITBASE register is unknown (eg. when application
+ *  code and interrupt/exception handling code are built independently,
+ *  and thus with independent values of the LITBASE register;
+ *  debug monitors are one example of this).
+ *
+ *  Worst-case size of resulting code:  17 bytes.
+ */
+
+	.macro	safe_movi_a0	constant
+#if XCHAL_HAVE_ABSOLUTE_LITERALS
+	/*  Contort a PC-relative literal load even though we may be in litbase-relative mode: */
+	j	1f
+	.begin	no-transform			// ensure what follows is assembled exactly as-is
+	.align	4				// ensure constant and call0 target ...
+	.byte	0				// ... are 4-byte aligned (call0 instruction is 3 bytes long)
+1:	call0	2f				// read PC (that follows call0) in a0
+	.long	\constant			// 32-bit constant to load into a0
+2:
+	.end	no-transform
+	l32i	a0, a0, 0			// load constant
+#else
+	movi	a0, \constant			// no LITBASE, can assume PC-relative L32R
+#endif
+	.endm
+
+
+
+
+/*----------------------------------------------------------------------
+ *  window_spill{4,8,12}
+ *
+ *  These macros spill callers' register windows to the stack.
+ *  They work for both privileged and non-privileged tasks.
+ *  Must be called from a windowed ABI context, eg. within
+ *  a windowed ABI function (ie. valid stack frame, window
+ *  exceptions enabled, not in exception mode, etc).
+ *
+ *  This macro requires a single invocation of the window_spill_common
+ *  macro in the same assembly unit and section.
+ *
+ *  Note that using window_spill{4,8,12} macros is more efficient
+ *  than calling a function implemented using window_spill_function,
+ *  because the latter needs extra code to figure out the size of
+ *  the call to the spilling function.
+ *
+ *  Example usage:
+ *	
+ *		.text
+ *		.align	4
+ *		.global	some_function
+ *		.type	some_function,@function
+ *	some_function:
+ *		entry	a1, 16
+ *		:
+ *		:
+ *
+ *		window_spill4	// Spill windows of some_function's callers; preserves a0..a3 only;
+ *				// to use window_spill{8,12} in this example function we'd have
+ *				// to increase space allocated by the entry instruction, because
+ *				// 16 bytes only allows call4; 32 or 48 bytes (+locals) are needed
+ *				// for call8/window_spill8 or call12/window_spill12 respectively.
+ *
+ *		:
+ *
+ *		retw
+ *
+ *		window_spill_common	// instantiates code used by window_spill4
+ *
+ *
+ *  On entry:
+ *	none (if window_spill4)
+ *	stack frame has enough space allocated for call8 (if window_spill8)
+ *	stack frame has enough space allocated for call12 (if window_spill12)
+ *  On exit:
+ *	 a4..a15 clobbered (if window_spill4)
+ *	 a8..a15 clobbered (if window_spill8)
+ *	a12..a15 clobbered (if window_spill12)
+ *	no caller windows are in live registers
+ */
+
+	.macro	window_spill4
+#if XCHAL_HAVE_WINDOWED
+# if XCHAL_NUM_AREGS == 16
+	movi	a15, 0			// for 16-register files, no need to call to reach the end
+# elif XCHAL_NUM_AREGS == 32
+	call4	.L__wdwspill_assist28	// call deep enough to clear out any live callers
+# elif XCHAL_NUM_AREGS == 64
+	call4	.L__wdwspill_assist60	// call deep enough to clear out any live callers
+# endif
+#endif
+	.endm	// window_spill4
+
+	.macro	window_spill8
+#if XCHAL_HAVE_WINDOWED
+# if XCHAL_NUM_AREGS == 16
+	movi	a15, 0			// for 16-register files, no need to call to reach the end
+# elif XCHAL_NUM_AREGS == 32
+	call8	.L__wdwspill_assist24	// call deep enough to clear out any live callers
+# elif XCHAL_NUM_AREGS == 64
+	call8	.L__wdwspill_assist56	// call deep enough to clear out any live callers
+# endif
+#endif
+	.endm	// window_spill8
+
+	.macro	window_spill12
+#if XCHAL_HAVE_WINDOWED
+# if XCHAL_NUM_AREGS == 16
+	movi	a15, 0			// for 16-register files, no need to call to reach the end
+# elif XCHAL_NUM_AREGS == 32
+	call12	.L__wdwspill_assist20	// call deep enough to clear out any live callers
+# elif XCHAL_NUM_AREGS == 64
+	call12	.L__wdwspill_assist52	// call deep enough to clear out any live callers
+# endif
+#endif
+	.endm	// window_spill12
+
+
+/*----------------------------------------------------------------------
+ *  window_spill_function
+ *
+ *  This macro outputs a function that will spill its caller's callers'
+ *  register windows to the stack.  Eg. it could be used to implement
+ *  a version of xthal_window_spill() that works in non-privileged tasks.
+ *  This works for both privileged and non-privileged tasks.
+ *
+ *  Typical usage:
+ *
+ *		.text
+ *		.align	4
+ *		.global	my_spill_function
+ *		.type	my_spill_function,@function
+ *	my_spill_function:
+ *		window_spill_function
+ *
+ *  On entry to resulting function:
+ *	none
+ *  On exit from resulting function:
+ *	none (no caller windows are in live registers)
+ */
+
+	.macro	window_spill_function
+#if XCHAL_HAVE_WINDOWED
+#  if XCHAL_NUM_AREGS == 32
+	entry	sp, 48
+	bbci.l	a0, 31, 1f		// branch if called with call4
+	bbsi.l	a0, 30, 2f		// branch if called with call12
+	call8	.L__wdwspill_assist16	// called with call8, only need another 8
+	retw
+1:	call12	.L__wdwspill_assist16	// called with call4, only need another 12
+	retw
+2:	call4	.L__wdwspill_assist16	// called with call12, only need another 4
+	retw
+#  elif XCHAL_NUM_AREGS == 64
+	entry	sp, 48
+	bbci.l	a0, 31, 1f		// branch if called with call4
+	bbsi.l	a0, 30, 2f		// branch if called with call12
+	call4	.L__wdwspill_assist52	// called with call8, only need a call4
+	retw
+1:	call8	.L__wdwspill_assist52	// called with call4, only need a call8
+	retw
+2:	call12	.L__wdwspill_assist40	// called with call12, can skip a call12
+	retw
+#  elif XCHAL_NUM_AREGS == 16
+	entry	sp, 16
+	bbci.l	a0, 31, 1f	// branch if called with call4
+	bbsi.l	a0, 30, 2f	// branch if called with call12
+	movi	a7, 0		// called with call8
+	retw
+1:	movi	a11, 0		// called with call4
+2:	retw			// if called with call12, everything already spilled
+
+//	movi	a15, 0		// trick to spill all but the direct caller
+//	j	1f
+//	//  The entry instruction is magical in the assembler (gets auto-aligned)
+//	//  so we have to jump to it to avoid falling through the padding.
+//	//  We need entry/retw to know where to return.
+//1:	entry	sp, 16
+//	retw
+#  else
+#   error "unrecognized address register file size"
+#  endif
+
+#endif /* XCHAL_HAVE_WINDOWED */
+	window_spill_common
+	.endm	// window_spill_function
+
+/*----------------------------------------------------------------------
+ *  window_spill_common
+ *
+ *  Common code used by any number of invocations of the window_spill##
+ *  and window_spill_function macros.
+ *
+ *  Must be instantiated exactly once within a given assembly unit,
+ *  within call/j range of and same section as window_spill##
+ *  macro invocations for that assembly unit.
+ *  (Is automatically instantiated by the window_spill_function macro.)
+ */
+
+	.macro	window_spill_common
+#if XCHAL_HAVE_WINDOWED && (XCHAL_NUM_AREGS == 32 || XCHAL_NUM_AREGS == 64)
+	.ifndef	.L__wdwspill_defined
+#  if XCHAL_NUM_AREGS >= 64
+.L__wdwspill_assist60:
+	entry	sp, 32
+	call8	.L__wdwspill_assist52
+	retw
+.L__wdwspill_assist56:
+	entry	sp, 16
+	call4	.L__wdwspill_assist52
+	retw
+.L__wdwspill_assist52:
+	entry	sp, 48
+	call12	.L__wdwspill_assist40
+	retw
+.L__wdwspill_assist40:
+	entry	sp, 48
+	call12	.L__wdwspill_assist28
+	retw
+#  endif
+.L__wdwspill_assist28:
+	entry	sp, 48
+	call12	.L__wdwspill_assist16
+	retw
+.L__wdwspill_assist24:
+	entry	sp, 32
+	call8	.L__wdwspill_assist16
+	retw
+.L__wdwspill_assist20:
+	entry	sp, 16
+	call4	.L__wdwspill_assist16
+	retw
+.L__wdwspill_assist16:
+	entry	sp, 16
+	movi	a15, 0
+	retw
+	.set	.L__wdwspill_defined, 1
+	.endif
+#endif /* XCHAL_HAVE_WINDOWED with 32 or 64 aregs */
+	.endm	// window_spill_common
+
+/*----------------------------------------------------------------------
+ *  beqi32
+ *
+ *  macro implements version of beqi for arbitrary 32-bit immediate value
+ *
+ *     beqi32 ax, ay, imm32, label
+ * 
+ *  Compares value in register ax with imm32 value and jumps to label if
+ *  equal. Clobbers register ay if needed
+ *
+ */
+   .macro beqi32	ax, ay, imm, label
+    .ifeq ((\imm-1) & ~7)	// 1..8 ?
+		beqi	\ax, \imm, \label
+    .else
+      .ifeq (\imm+1)		// -1 ?
+		beqi	\ax, \imm, \label
+      .else
+        .ifeq (\imm)		// 0 ?
+		beqz	\ax, \label
+        .else
+		//  We could also handle immediates 10,12,16,32,64,128,256 
+		//  but it would be a long macro...
+		movi	\ay, \imm
+		beq	\ax, \ay, \label
+        .endif
+      .endif
+    .endif
+   .endm // beqi32
+
+/*----------------------------------------------------------------------
+ *  isync_retw_nop
+ *
+ *  This macro must be invoked immediately after ISYNC if ISYNC
+ *  would otherwise be immediately followed by RETW (or other instruction
+ *  modifying WindowBase or WindowStart), in a context where
+ *  kernel vector mode may be selected, and level-one interrupts
+ *  and window overflows may be enabled, on an XEA1 configuration.
+ *
+ *  On hardware with erratum "XEA1KWIN" (see <xtensa/core.h> for details),
+ *  XEA1 code must have at least one instruction between ISYNC and RETW if
+ *  run in kernel vector mode with interrupts and window overflows enabled.
+ */
+	.macro	isync_retw_nop
+#if XCHAL_MAYHAVE_ERRATUM_XEA1KWIN
+	nop
+#endif
+	.endm
+
+
+
+/*----------------------------------------------------------------------
+ *  abs
+ *
+ *  implements abs on machines that do not have it configured
+ */
+	
+#if !XCHAL_HAVE_ABS
+	.macro abs arr, ars
+	.ifc \arr, \ars
+	//src equal dest is less efficient
+	bgez \arr, 1f
+	neg \arr, \arr
+1:	
+	.else
+	neg \arr, \ars
+	movgez \arr, \ars, \ars
+	.endif
+	.endm
+#endif /* !XCHAL_HAVE_ABS */
+
+
+/*----------------------------------------------------------------------
+ *  addx2
+ *  
+ *  implements addx2 on machines that do not have it configured
+ *     
+ */
+
+#if !XCHAL_HAVE_ADDX
+	.macro addx2 arr, ars, art
+	.ifc \arr, \art
+	.ifc \arr, \ars
+	// addx2 a, a, a     (not common)
+	.err
+	.else
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	.endif
+	.else
+	//addx2 a, b, c
+	//addx2 a, a, b
+	//addx2 a, b, b
+	slli \arr, \ars, 1
+	add  \arr, \arr, \art
+	.endif
+	.endm
+#endif /* !XCHAL_HAVE_ADDX */
+	
+/*----------------------------------------------------------------------
+ *  addx4
+ * 
+ *  implements addx4 on machines that do not have it configured
+ *
+ */
+	
+#if !XCHAL_HAVE_ADDX
+	.macro addx4 arr, ars, art
+	.ifc \arr, \art
+	.ifc \arr, \ars
+	// addx4 a, a, a     (not common)
+	 .err
+	 .else
+	//# addx4 a, b, a
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	.endif
+	.else
+	//addx4 a, b, c
+	//addx4 a, a, b
+	//addx4 a, b, b
+	slli \arr, \ars, 2
+	add  \arr, \arr, \art
+	.endif
+	.endm
+#endif /* !XCHAL_HAVE_ADDX */
+
+/*----------------------------------------------------------------------
+ *  addx8
+ * 
+ *  implements addx8 on machines that do not have it configured
+ * 
+ */
+
+#if !XCHAL_HAVE_ADDX
+	.macro addx8 arr, ars, art
+	.ifc \arr, \art
+	.ifc \arr, \ars
+	//addx8 a, a, a     (not common)
+	.err
+	.else
+	//addx8 a, b, a
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	add \arr, \ars, \art
+	.endif
+	.else
+	//addx8 a, b, c
+	//addx8 a, a, b
+	//addx8 a, b, b
+	slli \arr, \ars, 3
+	add  \arr, \arr, \art
+	.endif
+	.endm
+#endif /* !XCHAL_HAVE_ADDX */
+
+
+/*----------------------------------------------------------------------
+ *  rfe_rfue
+ * 
+ *  Maps to RFUE on XEA1, and RFE on XEA2.  No mapping on XEAX.
+ */
+
+#if XCHAL_HAVE_XEA1
+	.macro	rfe_rfue
+	rfue
+	.endm
+#elif XCHAL_HAVE_XEA2
+	.macro	rfe_rfue
+	rfe
+	.endm
+#endif
+ 
+
+/*----------------------------------------------------------------------
+ *  abi_entry
+ * 
+ *  Generate proper function entry sequence for the current ABI
+ *  (windowed or call0).  Takes care of allocating stack space (up to 1kB)
+ *  and saving the return PC, if necessary.  The corresponding abi_return
+ *  macro does the corresponding stack deallocation and restoring return PC.
+ *
+ *  Parameters are:
+ *
+ *	locsize		Number of bytes to allocate on the stack
+ *			for local variables (and for args to pass to
+ *			callees, if any calls are made).  Defaults to zero.
+ *			The macro rounds this up to a multiple of 16.
+ *			NOTE:  large values are allowed (e.g. up to 1 GB).
+ *
+ *	callsize	Maximum call size made by this function.
+ *			Leave zero (default) for leaf functions, i.e. if
+ *			this function makes no calls to other functions.
+ *			Otherwise must be set to 4, 8, or 12 according
+ *			to whether the "largest" call made is a call[x]4,
+ *			call[x]8, or call[x]12 (for call0 ABI, it makes
+ *			no difference whether this is set to 4, 8 or 12,
+ *			but it must be set to one of these values).
+ *
+ *  NOTE:  It is up to the caller to align the entry point, declare the
+ *  function symbol, make it global, etc.
+ *
+ *  NOTE:  This macro relies on assembler relaxation for large values
+ *  of locsize.  It might not work with the no-transform directive.
+ *  NOTE:  For the call0 ABI, this macro ensures SP is allocated or
+ *  de-allocated cleanly, i.e. without temporarily allocating too much
+ *  (or allocating negatively!) due to addi relaxation.
+ *
+ *  NOTE:  Generating the proper sequence and register allocation for
+ *  making calls in an ABI independent manner is a separate topic not
+ *  covered by this macro.
+ *
+ *  NOTE:  To access arguments, you can't use a fixed offset from SP.
+ *  The offset depends on the ABI, whether the function is leaf, etc.
+ *  The simplest method is probably to use the .locsz symbol, which
+ *  is set by this macro to the actual number of bytes allocated on
+ *  the stack, in other words, to the offset from SP to the arguments.
+ *  E.g. for a function whose arguments are all 32-bit integers, you
+ *  can get the 7th and 8th arguments (1st and 2nd args stored on stack)
+ *  using:
+ *	l32i	a2, sp, .locsz
+ *	l32i	a3, sp, .locsz+4
+ *  (this example works as long as locsize is under L32I's offset limit
+ *   of 1020 minus up to 48 bytes of ABI-specific stack usage;
+ *   otherwise you might first need to do "addi a?, sp, .locsz"
+ *   or similar sequence).
+ *
+ *  NOTE:  For call0 ABI, this macro (and abi_return) may clobber a9
+ *  (a caller-saved register).
+ *
+ *  Examples:
+ *		abi_entry
+ *		abi_entry  5
+ *		abi_entry  22, 8
+ *		abi_entry  0, 4
+ */
+
+	/*
+	 *  Compute .locsz and .callsz without emitting any instructions.
+	 *  Used by both abi_entry and abi_return.
+	 *  Assumes locsize >= 0.
+	 */
+	.macro	abi_entry_size locsize=0, callsize=0
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+	.ifeq	\callsize
+	 .set	.callsz, 16
+	.else
+	 .ifeq	\callsize-4
+	  .set	.callsz, 16
+	 .else
+	  .ifeq	\callsize-8
+	   .set	.callsz, 32
+	  .else
+	   .ifeq \callsize-12
+	    .set .callsz, 48
+	   .else
+	    .error	"abi_entry: invalid call size \callsize"
+	   .endif
+	  .endif
+	 .endif
+	.endif
+	.set	.locsz, .callsz + ((\locsize + 15) & -16)
+#else
+	.set	.callsz, \callsize
+	.if	.callsz		/* if calls, need space for return PC */
+	 .set	.locsz, (\locsize + 4 + 15) & -16
+	.else
+	 .set	.locsz, (\locsize + 15) & -16
+	.endif
+#endif
+	.endm
+
+	.macro abi_entry locsize=0, callsize=0
+	.iflt	\locsize
+	 .error	"abi_entry: invalid negative size of locals (\locsize)"
+	.endif
+	abi_entry_size	\locsize, \callsize
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+	.ifgt	.locsz - 32760	/* .locsz > 32760 (ENTRY's max range)? */
+	/*  Funky computation to try to have assembler use addmi efficiently if possible:  */
+	entry	sp, 0x7F00 + (.locsz & 0xF0)
+	addi	a12, sp, - ((.locsz & -0x100) - 0x7F00)
+	movsp	sp, a12
+	.else
+	entry	sp, .locsz
+	.endif
+#else
+	.if	.locsz
+	 .ifle	.locsz - 128	/* if locsz <= 128 */
+	addi	sp, sp, -.locsz
+	  .if	.callsz
+	s32i	a0, sp, .locsz - 4
+	  .endif
+	 .elseif  .callsz	/* locsz > 128, with calls: */
+	movi	a9, .locsz - 16		/* note: a9 is caller-saved */
+	addi	sp, sp, -16
+	s32i	a0, sp, 12
+	sub	sp, sp, a9
+	 .else			/* locsz > 128, no calls: */
+	movi	a9, .locsz
+	sub	sp, sp, a9
+	 .endif			/* end */
+	.endif
+#endif
+	.endm
+
+
+
+/*----------------------------------------------------------------------
+ *  abi_return
+ * 
+ *  Generate proper function exit sequence for the current ABI
+ *  (windowed or call0).  Takes care of freeing stack space and
+ *  restoring the return PC, if necessary.
+ *  NOTE:  This macro MUST be invoked following a corresponding
+ *  abi_entry macro invocation.  For call0 ABI in particular,
+ *  all stack and PC restoration are done according to the last
+ *  abi_entry macro invoked before this macro in the assembly file.
+ *
+ *  Normally this macro takes no arguments.  However to allow
+ *  for placing abi_return *before* abi_entry (as must be done
+ *  for some highly optimized assembly), it optionally takes
+ *  exactly the same arguments as abi_entry.
+ */
+
+	.macro abi_return	locsize=-1, callsize=0
+	.ifge	\locsize
+	abi_entry_size	\locsize, \callsize
+	.endif
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+	retw
+#else
+	.if	.locsz
+	 .iflt	.locsz - 128	/* if locsz < 128 */
+	  .if	.callsz
+	l32i	a0, sp, .locsz - 4
+	  .endif
+	addi	sp, sp, .locsz
+	 .elseif  .callsz	/* locsz >= 128, with calls: */
+	addi	a9, sp, .locsz - 16
+	l32i	a0, a9, 12
+	addi	sp, a9, 16
+	 .else			/* locsz >= 128, no calls: */
+	movi	a9, .locsz
+	add	sp, sp, a9
+	 .endif			/* end */
+	.endif
+	ret
+#endif
+	.endm
+
+
+#endif /*XTENSA_COREASM_H*/
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/corebits.h

@@ -0,0 +1,164 @@
+/*
+ * xtensa/corebits.h - Xtensa Special Register field positions, masks, values.
+ *
+ * (In previous releases, these were defined in specreg.h, a generated file.
+ *  This file is not generated, ie. it is processor configuration independent.)
+ */
+
+/* $Id: //depot/rel/Boreal/Xtensa/OS/include/xtensa/corebits.h#2 $ */
+
+/*
+ * Copyright (c) 2005-2007 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_COREBITS_H
+#define XTENSA_COREBITS_H
+
+/*  EXCCAUSE register fields:  */
+#define EXCCAUSE_EXCCAUSE_SHIFT	0
+#define EXCCAUSE_EXCCAUSE_MASK	0x3F
+/*  EXCCAUSE register values:  */
+/*
+ *  General Exception Causes
+ *  (values of EXCCAUSE special register set by general exceptions,
+ *   which vector to the user, kernel, or double-exception vectors).
+ */
+#define EXCCAUSE_ILLEGAL		0	/* Illegal Instruction */
+#define EXCCAUSE_SYSCALL		1	/* System Call (SYSCALL instruction) */
+#define EXCCAUSE_INSTR_ERROR		2	/* Instruction Fetch Error */
+# define EXCCAUSE_IFETCHERROR		2	/* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_LOAD_STORE_ERROR	3	/* Load Store Error */
+# define EXCCAUSE_LOADSTOREERROR	3	/* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_LEVEL1_INTERRUPT	4	/* Level 1 Interrupt */
+# define EXCCAUSE_LEVEL1INTERRUPT	4	/* (backward compatibility macro, deprecated, avoid) */
+#define EXCCAUSE_ALLOCA			5	/* Stack Extension Assist (MOVSP instruction) for alloca */
+#define EXCCAUSE_DIVIDE_BY_ZERO		6	/* Integer Divide by Zero */
+#define EXCCAUSE_SPECULATION		7	/* Use of Failed Speculative Access (not implemented) */
+#define EXCCAUSE_PRIVILEGED		8	/* Privileged Instruction */
+#define EXCCAUSE_UNALIGNED		9	/* Unaligned Load or Store */
+/* Reserved				10..11 */
+#define EXCCAUSE_INSTR_DATA_ERROR	12	/* PIF Data Error on Instruction Fetch (RB-200x and later) */
+#define EXCCAUSE_LOAD_STORE_DATA_ERROR	13	/* PIF Data Error on Load or Store (RB-200x and later) */
+#define EXCCAUSE_INSTR_ADDR_ERROR	14	/* PIF Address Error on Instruction Fetch (RB-200x and later) */
+#define EXCCAUSE_LOAD_STORE_ADDR_ERROR	15	/* PIF Address Error on Load or Store (RB-200x and later) */
+#define EXCCAUSE_ITLB_MISS		16	/* ITLB Miss (no ITLB entry matches, hw refill also missed) */
+#define EXCCAUSE_ITLB_MULTIHIT		17	/* ITLB Multihit (multiple ITLB entries match) */
+#define EXCCAUSE_INSTR_RING		18	/* Ring Privilege Violation on Instruction Fetch */
+/* Reserved				19 */	/* Size Restriction on IFetch (not implemented) */
+#define EXCCAUSE_INSTR_PROHIBITED	20	/* Cache Attribute does not allow Instruction Fetch */
+/* Reserved				21..23 */
+#define EXCCAUSE_DTLB_MISS		24	/* DTLB Miss (no DTLB entry matches, hw refill also missed) */
+#define EXCCAUSE_DTLB_MULTIHIT		25	/* DTLB Multihit (multiple DTLB entries match) */
+#define EXCCAUSE_LOAD_STORE_RING	26	/* Ring Privilege Violation on Load or Store */
+/* Reserved				27 */	/* Size Restriction on Load/Store (not implemented) */
+#define EXCCAUSE_LOAD_PROHIBITED	28	/* Cache Attribute does not allow Load */
+#define EXCCAUSE_STORE_PROHIBITED	29	/* Cache Attribute does not allow Store */
+/* Reserved				30..31 */
+#define EXCCAUSE_CP_DISABLED(n)		(32+(n))	/* Access to Coprocessor 'n' when disabled */
+#define EXCCAUSE_CP0_DISABLED		32	/* Access to Coprocessor 0 when disabled */
+#define EXCCAUSE_CP1_DISABLED		33	/* Access to Coprocessor 1 when disabled */
+#define EXCCAUSE_CP2_DISABLED		34	/* Access to Coprocessor 2 when disabled */
+#define EXCCAUSE_CP3_DISABLED		35	/* Access to Coprocessor 3 when disabled */
+#define EXCCAUSE_CP4_DISABLED		36	/* Access to Coprocessor 4 when disabled */
+#define EXCCAUSE_CP5_DISABLED		37	/* Access to Coprocessor 5 when disabled */
+#define EXCCAUSE_CP6_DISABLED		38	/* Access to Coprocessor 6 when disabled */
+#define EXCCAUSE_CP7_DISABLED		39	/* Access to Coprocessor 7 when disabled */
+/*#define EXCCAUSE_FLOATING_POINT	40*/	/* Floating Point Exception (not implemented) */
+/* Reserved				40..63 */
+
+/*  PS register fields:  */
+#define PS_WOE_SHIFT		18
+#define PS_WOE_MASK		0x00040000
+#define PS_WOE			PS_WOE_MASK
+#define PS_CALLINC_SHIFT	16
+#define PS_CALLINC_MASK		0x00030000
+#define PS_CALLINC(n)		(((n)&3)<<PS_CALLINC_SHIFT)	/* n = 0..3 */
+#define PS_OWB_SHIFT		8
+#define PS_OWB_MASK		0x00000F00
+#define PS_OWB(n)		(((n)&15)<<PS_OWB_SHIFT)	/* n = 0..15 (or 0..7) */
+#define PS_RING_SHIFT		6
+#define PS_RING_MASK		0x000000C0
+#define PS_RING(n)		(((n)&3)<<PS_RING_SHIFT)	/* n = 0..3 */
+#define PS_UM_SHIFT		5
+#define PS_UM_MASK		0x00000020
+#define PS_UM			PS_UM_MASK
+#define PS_EXCM_SHIFT		4
+#define PS_EXCM_MASK		0x00000010
+#define PS_EXCM			PS_EXCM_MASK
+#define PS_INTLEVEL_SHIFT	0
+#define PS_INTLEVEL_MASK	0x0000000F
+#define PS_INTLEVEL(n)		((n)&PS_INTLEVEL_MASK)		/* n = 0..15 */
+/*  Backward compatibility (deprecated):  */
+#define PS_PROGSTACK_SHIFT	PS_UM_SHIFT
+#define PS_PROGSTACK_MASK	PS_UM_MASK
+#define PS_PROG_SHIFT		PS_UM_SHIFT
+#define PS_PROG_MASK		PS_UM_MASK
+#define PS_PROG			PS_UM
+
+/*  DBREAKCn register fields:  */
+#define DBREAKC_MASK_SHIFT		0
+#define DBREAKC_MASK_MASK		0x0000003F
+#define DBREAKC_LOADBREAK_SHIFT		30
+#define DBREAKC_LOADBREAK_MASK		0x40000000
+#define DBREAKC_STOREBREAK_SHIFT	31
+#define DBREAKC_STOREBREAK_MASK		0x80000000
+
+/*  DEBUGCAUSE register fields:  */
+#define DEBUGCAUSE_DEBUGINT_SHIFT	5
+#define DEBUGCAUSE_DEBUGINT_MASK	0x20	/* debug interrupt */
+#define DEBUGCAUSE_BREAKN_SHIFT		4
+#define DEBUGCAUSE_BREAKN_MASK		0x10	/* BREAK.N instruction */
+#define DEBUGCAUSE_BREAK_SHIFT		3
+#define DEBUGCAUSE_BREAK_MASK		0x08	/* BREAK instruction */
+#define DEBUGCAUSE_DBREAK_SHIFT		2
+#define DEBUGCAUSE_DBREAK_MASK		0x04	/* DBREAK match */
+#define DEBUGCAUSE_IBREAK_SHIFT		1
+#define DEBUGCAUSE_IBREAK_MASK		0x02	/* IBREAK match */
+#define DEBUGCAUSE_ICOUNT_SHIFT		0
+#define DEBUGCAUSE_ICOUNT_MASK		0x01	/* ICOUNT would increment to zero */
+
+/*  MESR register fields:  */
+#define MESR_MEME		0x00000001	/* memory error */
+#define MESR_MEME_SHIFT		0
+#define MESR_DME		0x00000002	/* double memory error */
+#define MESR_DME_SHIFT		1
+#define MESR_RCE		0x00000010	/* recorded memory error */
+#define MESR_RCE_SHIFT		4
+#define MESR_LCE		
+#define MESR_LCE_SHIFT		?
+#define MESR_LCE_L
+#define MESR_ERRENAB		0x00000100
+#define MESR_ERRENAB_SHIFT	8
+#define MESR_ERRTEST		0x00000200
+#define MESR_ERRTEST_SHIFT	9
+#define MESR_DATEXC		0x00000400
+#define MESR_DATEXC_SHIFT	10
+#define MESR_INSEXC		0x00000800
+#define MESR_INSEXC_SHIFT	11
+#define MESR_WAYNUM_SHIFT	16
+#define MESR_ACCTYPE_SHIFT	20
+#define MESR_MEMTYPE_SHIFT	24
+#define MESR_ERRTYPE_SHIFT	30
+
+
+#endif /*XTENSA_COREBITS_H*/
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/hal.h

@@ -0,0 +1,925 @@
+/*
+   xtensa/hal.h -- contains a definition of the Core HAL interface
+
+   All definitions in this header file are independent of any specific
+   Xtensa processor configuration.  Thus software (eg. OS, application,
+   etc) can include this header file and be compiled into configuration-
+   independent objects that can be distributed and eventually linked
+   to the HAL library (libhal.a) to create a configuration-specific
+   final executable.
+
+   Certain definitions, however, are release/version-specific -- such as
+   the XTHAL_RELEASE_xxx macros (or additions made in later versions).
+
+
+   $Id: //depot/rel/Boreal/Xtensa/OS/target-os-src/hal.h.tpp#3 $
+
+   Copyright (c) 1999-2010 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef XTENSA_HAL_H
+#define XTENSA_HAL_H
+
+
+/****************************************************************************
+	    Definitions Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+
+/*----------------------------------------------------------------------
+	   Constant Definitions  (shared with assembly)
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Software (Xtensa Tools) version information.  Not configuration-specific!
+ *
+ *  NOTE:  "release" is a misnomer here, these are really product "version"
+ *	numbers.  A "release" is a collection of product versions
+ *	made available at once (together) to customers.
+ *	In the past, release and version names all matched in T####.# form,
+ *	making the distinction irrelevant.  This is no longer the case.
+ */
+#define XTHAL_RELEASE_MAJOR	8000
+#define XTHAL_RELEASE_MINOR	1
+#define XTHAL_RELEASE_NAME	"8.0.1"
+#define XTHAL_REL_8	1
+#define XTHAL_REL_8_0	1
+#define XTHAL_REL_8_0_1	1
+
+/*  HAL version numbers (these names are for backward compatibility):  */
+#define XTHAL_MAJOR_REV		XTHAL_RELEASE_MAJOR
+#define XTHAL_MINOR_REV		XTHAL_RELEASE_MINOR
+/*
+ *  A bit of software release/version history on values of XTHAL_{MAJOR,MINOR}_REV:
+ *
+ *	SW Version	MAJOR	MINOR		Comment
+ *	=======		=====	=====		=======
+ *	T1015.n		n/a	n/a		(HAL not yet available)
+ *	T1020.{0,1,2}	0	1		(HAL beta)
+ *	T1020.{3,4}	0	2		First release.
+ *	T1020.n (n>4)	0	2 or >3		(TBD)
+ *	T1030.0		0	1		(HAL beta)
+ *	T1030.{1,2}	0	3		Equivalent to first release.
+ *	T1030.n (n>=3)	0	>= 3		(TBD)
+ *	T1040.n		1040	n		Full CHAL available from T1040.2
+ *	T1050.n		1050	n		.
+ *	6.0.n		6000	n		Xtensa Tools v6   (RA-200x.n)
+ *	7.0.n		7000	n		Xtensa Tools v7   (RB-200x.n)
+ *	7.1.n		7010	n		Xtensa Tools v7.1 (RB-200x.(n+2))
+ *
+ *
+ *  Note:  there is a distinction between the software version with
+ *  which something is compiled (accessible using XTHAL_RELEASE_* macros)
+ *  and the software version with which the HAL library was compiled
+ *  (accessible using Xthal_release_* global variables).  This
+ *  distinction is particularly relevant for vendors that distribute
+ *  configuration-independent binaries (eg. an OS), where their customer
+ *  might link it with a HAL of a different Xtensa software version.
+ *  In this case, it may be appropriate for the OS to verify at run-time
+ *  whether XTHAL_RELEASE_* and Xthal_release_* are compatible.
+ *  [Guidelines as to which version is compatible with which are not
+ *  currently provided explicitly, but might be inferred from reading
+ *  OSKit documentation for all releases -- compatibility is also highly
+ *  dependent on which HAL features are used.  Each version is usually
+ *  backward compatible, with very few exceptions if any.]
+ *
+ *  Notes:
+ *	Tornado 2.0 supported in T1020.3+, T1030.1+, and T1040.{0,1} only.
+ *	Tornado 2.0.2 supported in T1040.2+, T1050, and 6.0.
+ *	Compile-time HAL port of NucleusPlus supported by T1040.2 and later.
+ */
+
+/*  Version comparison operators (among major/minor pairs):  */
+#define XTHAL_REL_GE(maja,mina, majb,minb)	((maja) > (majb) || \
+						 ((maja) == (majb) && (mina) >= (minb)))
+#define XTHAL_REL_GT(maja,mina, majb,minb)	((maja) > (majb) || \
+						 ((maja) == (majb) && (mina) > (minb)))
+#define XTHAL_REL_LE(maja,mina, majb,minb)	((maja) < (majb) || \
+						 ((maja) == (majb) && (mina) <= (minb)))
+#define XTHAL_REL_LT(maja,mina, majb,minb)	((maja) < (majb) || \
+						 ((maja) == (majb) && (mina) < (minb)))
+#define XTHAL_REL_EQ(maja,mina, majb,minb)	((maja) == (majb) && (mina) == (minb))
+
+/*  Fuzzy (3-way) logic operators:  */
+#define XTHAL_MAYBE		-1	/* 0=NO, 1=YES, -1=MAYBE */
+#define XTHAL_FUZZY_AND(a,b)	(((a)==0 || (b)==0) ? 0 : ((a)==1 && (b)==1) ? 1 : XTHAL_MAYBE)
+#define XTHAL_FUZZY_OR(a,b)	(((a)==1 || (b)==1) ? 1 : ((a)==0 && (b)==0) ? 0 : XTHAL_MAYBE)
+#define XTHAL_FUZZY_NOT(a)	(((a)==0 || (a)==1) ? (1-(a)) : XTHAL_MAYBE)
+
+
+/*
+ *  Architectural limit, independent of configuration:
+ */
+#define XTHAL_MAX_CPS		8	/* max number of coprocessors (0..7) */
+
+/*  Misc:  */
+#define XTHAL_LITTLEENDIAN		0
+#define XTHAL_BIGENDIAN			1
+
+
+
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------
+				HAL
+  ----------------------------------------------------------------------*/
+
+/* Constant to be checked in build = (XTHAL_MAJOR_REV<<16)|XTHAL_MINOR_REV */
+extern const unsigned int Xthal_rev_no;
+
+
+/*----------------------------------------------------------------------
+			Optional/Custom Processor State
+  ----------------------------------------------------------------------*/
+
+/* save & restore the extra processor state */
+extern void xthal_save_extra(void *base);
+extern void xthal_restore_extra(void *base);
+
+extern void xthal_save_cpregs(void *base, int);
+extern void xthal_restore_cpregs(void *base, int);
+/* versions specific to each coprocessor id */
+extern void xthal_save_cp0(void *base);
+extern void xthal_save_cp1(void *base);
+extern void xthal_save_cp2(void *base);
+extern void xthal_save_cp3(void *base);
+extern void xthal_save_cp4(void *base);
+extern void xthal_save_cp5(void *base);
+extern void xthal_save_cp6(void *base);
+extern void xthal_save_cp7(void *base);
+extern void xthal_restore_cp0(void *base);
+extern void xthal_restore_cp1(void *base);
+extern void xthal_restore_cp2(void *base);
+extern void xthal_restore_cp3(void *base);
+extern void xthal_restore_cp4(void *base);
+extern void xthal_restore_cp5(void *base);
+extern void xthal_restore_cp6(void *base);
+extern void xthal_restore_cp7(void *base);
+/* pointers to each of the functions above */
+extern void* Xthal_cpregs_save_fn[XTHAL_MAX_CPS];
+extern void* Xthal_cpregs_restore_fn[XTHAL_MAX_CPS];
+/* similarly for non-windowed ABI (may be same or different) */
+extern void* Xthal_cpregs_save_nw_fn[XTHAL_MAX_CPS];
+extern void* Xthal_cpregs_restore_nw_fn[XTHAL_MAX_CPS];
+
+/*extern void xthal_save_all_extra(void *base);*/
+/*extern void xthal_restore_all_extra(void *base);*/
+
+/* space for processor state */
+extern const unsigned int Xthal_extra_size;
+extern const unsigned int Xthal_extra_align;
+extern const unsigned int Xthal_cpregs_size[XTHAL_MAX_CPS];
+extern const unsigned int Xthal_cpregs_align[XTHAL_MAX_CPS];
+extern const unsigned int Xthal_all_extra_size;
+extern const unsigned int Xthal_all_extra_align;
+/* coprocessor names */
+extern const char * const Xthal_cp_names[XTHAL_MAX_CPS];
+
+/* initialize the extra processor */
+/*extern void xthal_init_extra(void);*/
+/* initialize the TIE coprocessor */
+/*extern void xthal_init_cp(int);*/
+
+/* initialize the extra processor */
+extern void xthal_init_mem_extra(void *);
+/* initialize the TIE coprocessor */
+extern void xthal_init_mem_cp(void *, int);
+
+/* the number of TIE coprocessors contiguous from zero (for Tor2) */
+extern const unsigned int Xthal_num_coprocessors;
+
+/* actual number of coprocessors */
+extern const unsigned char Xthal_cp_num;
+/* index of highest numbered coprocessor, plus one */
+extern const unsigned char Xthal_cp_max;
+/* index of highest allowed coprocessor number, per cfg, plus one */
+/*extern const unsigned char Xthal_cp_maxcfg;*/
+/* bitmask of which coprocessors are present */
+extern const unsigned int  Xthal_cp_mask;
+
+/* read & write extra state register */
+/*extern int xthal_read_extra(void *base, unsigned reg, unsigned *value);*/
+/*extern int xthal_write_extra(void *base, unsigned reg, unsigned value);*/
+
+/* read & write a TIE coprocessor register */
+/*extern int xthal_read_cpreg(void *base, int cp, unsigned reg, unsigned *value);*/
+/*extern int xthal_write_cpreg(void *base, int cp, unsigned reg, unsigned value);*/
+
+/* return coprocessor number based on register */
+/*extern int xthal_which_cp(unsigned reg);*/
+
+
+/*----------------------------------------------------------------------
+   				Register Windows
+  ----------------------------------------------------------------------*/
+
+/* number of registers in register window */
+extern const unsigned int  Xthal_num_aregs;
+extern const unsigned char Xthal_num_aregs_log2;
+
+
+/*----------------------------------------------------------------------
+   				Cache
+  ----------------------------------------------------------------------*/
+
+/* size of the cache lines in log2(bytes) */
+extern const unsigned char Xthal_icache_linewidth;
+extern const unsigned char Xthal_dcache_linewidth;
+/* size of the cache lines in bytes (2^linewidth) */
+extern const unsigned short Xthal_icache_linesize;
+extern const unsigned short Xthal_dcache_linesize;
+
+/* size of the caches in bytes (ways * 2^(linewidth + setwidth)) */
+extern const unsigned int  Xthal_icache_size;
+extern const unsigned int  Xthal_dcache_size;
+/* cache features */
+extern const unsigned char Xthal_dcache_is_writeback;
+
+/* invalidate the caches */
+extern void xthal_icache_region_invalidate( void *addr, unsigned size );
+extern void xthal_dcache_region_invalidate( void *addr, unsigned size );
+extern void xthal_icache_line_invalidate(void *addr);
+extern void xthal_dcache_line_invalidate(void *addr);
+/* write dirty data back */
+extern void xthal_dcache_region_writeback( void *addr, unsigned size );
+extern void xthal_dcache_line_writeback(void *addr);
+/* write dirty data back and invalidate */
+extern void xthal_dcache_region_writeback_inv( void *addr, unsigned size );
+extern void xthal_dcache_line_writeback_inv(void *addr);
+
+/* sync icache and memory */
+extern void xthal_icache_sync( void );
+/* sync dcache and memory */
+extern void xthal_dcache_sync( void );
+
+/* coherency (low-level -- not normally called directly) */
+extern void xthal_cache_coherence_on( void );
+extern void xthal_cache_coherence_off( void );
+/* coherency (high-level) */
+extern void xthal_cache_coherence_optin( void );
+extern void xthal_cache_coherence_optout( void );
+
+/* prefetch */
+#define XTHAL_PREFETCH_ENABLE	-1
+#define XTHAL_PREFETCH_DISABLE	0
+extern int  xthal_set_cache_prefetch( int );
+extern int  xthal_get_cache_prefetch( void );
+
+
+/*----------------------------------------------------------------------
+   				Debug
+  ----------------------------------------------------------------------*/
+
+/*  1 if debug option configured, 0 if not:  */
+extern const int Xthal_debug_configured;
+
+/*  Set (plant) and remove software breakpoint, both synchronizing cache:  */
+extern unsigned int xthal_set_soft_break(void *addr);
+extern void         xthal_remove_soft_break(void *addr, unsigned int);
+
+
+/*----------------------------------------------------------------------
+   				Disassembler
+  ----------------------------------------------------------------------*/
+
+/*  Max expected size of the return buffer for a disassembled instruction (hint only):  */
+#define XTHAL_DISASM_BUFSIZE	80
+
+/*  Disassembly option bits for selecting what to return:  */
+#define XTHAL_DISASM_OPT_ADDR	0x0001	/* display address */
+#define XTHAL_DISASM_OPT_OPHEX	0x0002	/* display opcode bytes in hex */
+#define XTHAL_DISASM_OPT_OPCODE	0x0004	/* display opcode name (mnemonic) */
+#define XTHAL_DISASM_OPT_PARMS	0x0008	/* display parameters */
+#define XTHAL_DISASM_OPT_ALL	0x0FFF	/* display everything */
+
+/* routine to get a string for the disassembled instruction */
+extern int xthal_disassemble( unsigned char *instr_buf, void *tgt_addr,
+		       char *buffer, unsigned buflen, unsigned options );
+
+/* routine to get the size of the next instruction. Returns 0 for
+   illegal instruction */
+extern int xthal_disassemble_size( unsigned char *instr_buf );
+
+
+/*----------------------------------------------------------------------
+			Instruction/Data RAM/ROM Access
+  ----------------------------------------------------------------------*/
+
+extern void* xthal_memcpy(void *dst, const void *src, unsigned len);
+extern void* xthal_bcopy(const void *src, void *dst, unsigned len);
+
+
+/*----------------------------------------------------------------------
+                           MP Synchronization
+  ----------------------------------------------------------------------*/
+
+extern int      xthal_compare_and_set( int *addr, int test_val, int compare_val );
+
+/*extern const char  Xthal_have_s32c1i;*/
+
+
+/*----------------------------------------------------------------------
+                             Miscellaneous
+  ----------------------------------------------------------------------*/
+
+extern const unsigned int  Xthal_release_major;
+extern const unsigned int  Xthal_release_minor;
+extern const char * const  Xthal_release_name;
+extern const char * const  Xthal_release_internal;
+
+extern const unsigned char Xthal_memory_order;
+extern const unsigned char Xthal_have_windowed;
+extern const unsigned char Xthal_have_density;
+extern const unsigned char Xthal_have_booleans;
+extern const unsigned char Xthal_have_loops;
+extern const unsigned char Xthal_have_nsa;
+extern const unsigned char Xthal_have_minmax;
+extern const unsigned char Xthal_have_sext;
+extern const unsigned char Xthal_have_clamps;
+extern const unsigned char Xthal_have_mac16;
+extern const unsigned char Xthal_have_mul16;
+extern const unsigned char Xthal_have_fp;
+extern const unsigned char Xthal_have_speculation;
+extern const unsigned char Xthal_have_threadptr;
+
+extern const unsigned char Xthal_have_pif;
+extern const unsigned short Xthal_num_writebuffer_entries;
+
+extern const unsigned int  Xthal_build_unique_id;
+/*  Version info for hardware targeted by software upgrades:  */
+extern const unsigned int  Xthal_hw_configid0;
+extern const unsigned int  Xthal_hw_configid1;
+extern const unsigned int  Xthal_hw_release_major;
+extern const unsigned int  Xthal_hw_release_minor;
+extern const char * const  Xthal_hw_release_name;
+extern const char * const  Xthal_hw_release_internal;
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
+
+
+
+
+
+/****************************************************************************
+    Definitions Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/*----------------------------------------------------------------------
+	   Constant Definitions  (shared with assembly)
+  ----------------------------------------------------------------------*/
+
+/*
+ *  Architectural limits, independent of configuration.
+ *  Note that these are ISA-defined limits, not micro-architecture implementation
+ *  limits enforced by the Xtensa Processor Generator (which may be stricter than
+ *  these below).
+ */
+#define XTHAL_MAX_INTERRUPTS	32	/* max number of interrupts (0..31) */
+#define XTHAL_MAX_INTLEVELS	16	/* max number of interrupt levels (0..15) */
+					/* (as of T1040, implementation limit is 7: 0..6) */
+#define XTHAL_MAX_TIMERS	4	/* max number of timers (CCOMPARE0..CCOMPARE3) */
+					/* (as of T1040, implementation limit is 3: 0..2) */
+
+/*  Interrupt types:  */
+#define XTHAL_INTTYPE_UNCONFIGURED	0
+#define XTHAL_INTTYPE_SOFTWARE		1
+#define XTHAL_INTTYPE_EXTERN_EDGE	2
+#define XTHAL_INTTYPE_EXTERN_LEVEL	3
+#define XTHAL_INTTYPE_TIMER		4
+#define XTHAL_INTTYPE_NMI		5
+#define XTHAL_INTTYPE_WRITE_ERROR	6
+#define XTHAL_MAX_INTTYPES		7	/* number of interrupt types */
+
+/*  Timer related:  */
+#define XTHAL_TIMER_UNCONFIGURED	-1	/* Xthal_timer_interrupt[] value for non-existent timers */
+#define XTHAL_TIMER_UNASSIGNED	XTHAL_TIMER_UNCONFIGURED	/* (for backwards compatibility only) */
+
+/*  Local Memory ECC/Parity:  */
+#define XTHAL_MEMEP_PARITY	1
+#define XTHAL_MEMEP_ECC		2
+/*  Flags parameter to xthal_memep_inject_error():  */
+#define XTHAL_MEMEP_F_LOCAL		0	/* local memory (default) */
+#define XTHAL_MEMEP_F_DCACHE_DATA	4	/* data cache data */
+#define XTHAL_MEMEP_F_DCACHE_TAG	5	/* data cache tag */
+#define XTHAL_MEMEP_F_ICACHE_DATA	6	/* instruction cache data */
+#define XTHAL_MEMEP_F_ICACHE_TAG	7	/* instruction cache tag */
+#define XTHAL_MEMEP_F_CORRECTABLE	16	/* inject correctable error
+						   (default is non-corr.) */
+
+
+/*  Access Mode bits (tentative):  */	/* bit abbr unit short_name       PPC equ - Description */
+#define XTHAL_AMB_EXCEPTION	0	/* 001 E EX fls: EXception        none
+					   exception on any access (aka "illegal") */
+#define XTHAL_AMB_HITCACHE	1	/* 002 C CH fls: use Cache on Hit ~(I CI)
+					   [or H HC]  way from tag match;
+					   [or U UC] (ISA: same except Isolate case) */
+#define XTHAL_AMB_ALLOCATE	2	/* 004 A AL fl?: ALlocate         none
+					   [or F FI fill] refill cache on miss, way from LRU
+					   (ISA: Read/Write Miss Refill) */
+#define XTHAL_AMB_WRITETHRU	3	/* 008 W WT --s: WriteThrough     W WT
+					   store immediately to memory (ISA: same) */
+#define XTHAL_AMB_ISOLATE	4	/* 010 I IS fls: ISolate          none
+					   use cache regardless of hit-vs-miss,
+					   way from vaddr (ISA: use-cache-on-miss+hit) */
+#define XTHAL_AMB_GUARD		5	/* 020 G GU ?l?: GUard            G *
+					   non-speculative; spec/replay refs not permitted */
+#define XTHAL_AMB_COHERENT	6	/* 040 M MC ?ls: Mem/MP Coherent  M
+					   on read, other CPU/bus-master may need to supply data;
+					   on write, maybe redirect to or flush other CPU dirty line; etc */
+#if 0
+#define XTHAL_AMB_ORDERED	x	/* 000 O OR fls: ORdered          G *
+					   mem accesses cannot be out of order */
+#define XTHAL_AMB_FUSEWRITES	x	/* 000 F FW --s: FuseWrites       none
+					   allow combining/merging/coalescing multiple writes
+					   (to same datapath data unit) into one
+					   (implied by writeback) */
+#define XTHAL_AMB_TRUSTED	x	/* 000 T TR ?l?: TRusted          none
+					   memory will not bus error (if it does,
+					   handle as fatal imprecise interrupt) */
+#define XTHAL_AMB_PREFETCH	x	/* 000 P PR fl?: PRefetch         none
+					   on refill, read line+1 into prefetch buffers */
+#define XTHAL_AMB_STREAM	x	/* 000 S ST ???: STreaming        none
+					   access one of N stream buffers */
+#endif /*0*/
+
+#define XTHAL_AM_EXCEPTION	(1<<XTHAL_AMB_EXCEPTION)
+#define XTHAL_AM_HITCACHE	(1<<XTHAL_AMB_HITCACHE)
+#define XTHAL_AM_ALLOCATE	(1<<XTHAL_AMB_ALLOCATE)
+#define XTHAL_AM_WRITETHRU	(1<<XTHAL_AMB_WRITETHRU)
+#define XTHAL_AM_ISOLATE	(1<<XTHAL_AMB_ISOLATE)
+#define XTHAL_AM_GUARD		(1<<XTHAL_AMB_GUARD)
+#define XTHAL_AM_COHERENT	(1<<XTHAL_AMB_COHERENT)
+#if 0
+#define XTHAL_AM_ORDERED	(1<<XTHAL_AMB_ORDERED)
+#define XTHAL_AM_FUSEWRITES	(1<<XTHAL_AMB_FUSEWRITES)
+#define XTHAL_AM_TRUSTED	(1<<XTHAL_AMB_TRUSTED)
+#define XTHAL_AM_PREFETCH	(1<<XTHAL_AMB_PREFETCH)
+#define XTHAL_AM_STREAM		(1<<XTHAL_AMB_STREAM)
+#endif /*0*/
+
+/*
+ *  Allowed Access Modes (bit combinations).
+ *
+ *  Columns are:
+ *  "FOGIWACE"
+ *	Access mode bits (see XTHAL_AMB_xxx above).
+ *	<letter> = bit is set
+ *	'-'      = bit is clear
+ *	'.'      = bit is irrelevant / don't care, as follows:
+ *			E=1 makes all others irrelevant
+ *			W,F relevant only for stores
+ *  "2345"
+ *	Indicates which Xtensa releases support the corresponding
+ *	access mode.  Releases for each character column are:
+ *		2 = prior to T1020.2:   T1015 (V1.5), T1020.0, T1020.1
+ *		3 = T1020.2 and later:  T1020.2+, T1030
+ *		4 = T1040
+ *		5 = T1050 (maybe), LX1, LX2, LX2.1
+ *		7 = LX2.2
+ *		8 = LX3.0
+ *	And the character column contents are:
+ *		<number> = supported by release(s)
+ *		"." = unsupported by release(s)
+ *		"?" = support unknown
+ */
+						/* FOMGIWACE 234578 */
+/*  For instruction fetch:  */
+#define XTHAL_FAM_EXCEPTION		0x001	/* ........E 234578 exception */
+/*efine XTHAL_FAM_ISOLATE*/	      /*0x012*/	/* .---I.-C- ...... isolate */
+#define XTHAL_FAM_BYPASS		0x000	/* .----.--- 234578 bypass */
+/*efine XTHAL_FAM_NACACHED*/	      /*0x002*/	/* .----.-C- ...... cached no-allocate (frozen) */
+#define XTHAL_FAM_CACHED		0x006	/* .----.AC- 234578 cached */
+/*  For data load:  */
+#define XTHAL_LAM_EXCEPTION		0x001	/* ........E 234578 exception */
+#define XTHAL_LAM_ISOLATE		0x012	/* .---I.-C- 234578 isolate */
+#define XTHAL_LAM_BYPASS		0x000	/* .O---.--- 2..... bypass speculative */
+#define XTHAL_LAM_BYPASSG		0x020	/* .O-G-.--- .34578 bypass guarded */
+#define XTHAL_LAM_CACHED_NOALLOC	0x002	/* .O---.-C- 234578 cached no-allocate speculative */
+#define XTHAL_LAM_NACACHED		XTHAL_LAM_CACHED_NOALLOC
+#define XTHAL_LAM_NACACHEDG		0x022	/* .O-G-.-C- .?.... cached no-allocate guarded */
+#define XTHAL_LAM_CACHED		0x006	/* .----.AC- 234578 cached speculative */
+#define XTHAL_LAM_COHCACHED		0x046	/* .-M--.AC- ....*8 cached speculative MP-coherent */
+/*  For data store:  */
+#define XTHAL_SAM_EXCEPTION		0x001	/* ........E 234578 exception */
+#define XTHAL_SAM_ISOLATE		0x032	/* .--GI--C- 234578 isolate */
+#define XTHAL_SAM_BYPASS		0x028	/* -O-G-W--- 234578 bypass */
+#define XTHAL_SAM_WRITETHRU		0x02A	/* -O-G-W-C- 234578 writethrough */
+/*efine XTHAL_SAM_WRITETHRU_ALLOC*/   /*0x02E*/	/* -O-G-WAC- ...... writethrough allocate */
+#define XTHAL_SAM_WRITEBACK		0x026	/* F-MG--AC- ...578 writeback */
+#define XTHAL_SAM_COHWRITEBACK		0x066	/* F-MG--AC- ....*8 writeback MP-coherent */
+#define XTHAL_SAM_WRITEBACK_NOALLOC	0x022	/* ?--G---C- .....8 writeback no-allocate */
+
+#if 0
+/*
+    Cache attribute encoding for CACHEATTR (per ISA):
+    (Note:  if this differs from ISA Ref Manual, ISA has precedence)
+
+	Inst-fetches	Loads		Stores
+	-------------	------------	-------------
+0x0	FCA_EXCEPTION	LCA_NACACHED	SCA_WRITETHRU	cached no-allocate (previously misnamed "uncached")
+0x1	FCA_CACHED	LCA_CACHED	SCA_WRITETHRU	cached
+0x2	FCA_BYPASS	LCA_BYPASS_G*	SCA_BYPASS	bypass cache (what most people call uncached)
+0x3	FCA_CACHED	LCA_CACHED	SCA_WRITEALLOCF	write-allocate
+		     or LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)
+0x4	FCA_CACHED	LCA_CACHED	SCA_WRITEBACK[M] write-back [MP-coherent]
+		     or LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)
+0x5	FCA_CACHED	LCA_CACHED	SCA_WRITEBACK_NOALLOC	write-back no-allocate
+     or	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	(if unimplemented)
+0x6..D	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	(reserved)
+0xE	FCA_EXCEPTION	LCA_ISOLATE	SCA_ISOLATE	isolate
+0xF	FCA_EXCEPTION	LCA_EXCEPTION	SCA_EXCEPTION	illegal
+     *  Prior to T1020.2?, guard feature not supported, this defaulted to speculative (no _G)
+*/
+#endif /*0*/
+
+
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*----------------------------------------------------------------------
+   				Register Windows
+  ----------------------------------------------------------------------*/
+
+/*  This spill any live register windows (other than the caller's):
+ *  (NOTE:  current implementation require privileged code, but
+ *   a user-callable implementation is possible.)  */
+extern void      xthal_window_spill( void );
+
+
+/*----------------------------------------------------------------------
+			Optional/Custom Processor State
+  ----------------------------------------------------------------------*/
+
+/* validate & invalidate the TIE register file */
+extern void xthal_validate_cp(int);
+extern void xthal_invalidate_cp(int);
+
+/* read and write cpenable register */
+extern void xthal_set_cpenable(unsigned);
+extern unsigned xthal_get_cpenable(void);
+
+
+/*----------------------------------------------------------------------
+   				Interrupts
+  ----------------------------------------------------------------------*/
+
+/* the number of interrupt levels */
+extern const unsigned char Xthal_num_intlevels;
+/* the number of interrupts */
+extern const unsigned char Xthal_num_interrupts;
+
+/* mask for level of interrupts */
+extern const unsigned int Xthal_intlevel_mask[XTHAL_MAX_INTLEVELS];
+/* mask for level 0 to N interrupts */
+extern const unsigned int Xthal_intlevel_andbelow_mask[XTHAL_MAX_INTLEVELS];
+
+/* level of each interrupt */
+extern const unsigned char Xthal_intlevel[XTHAL_MAX_INTERRUPTS];
+
+/* type per interrupt */
+extern const unsigned char Xthal_inttype[XTHAL_MAX_INTERRUPTS];
+
+/* masks of each type of interrupt */
+extern const unsigned int Xthal_inttype_mask[XTHAL_MAX_INTTYPES];
+
+/* interrupt numbers assigned to each timer interrupt */
+extern const int Xthal_timer_interrupt[XTHAL_MAX_TIMERS];
+
+/*  INTENABLE,INTERRUPT,INTSET,INTCLEAR register access functions:  */
+extern unsigned  xthal_get_intenable( void );
+extern void      xthal_set_intenable( unsigned );
+extern unsigned  xthal_get_interrupt( void );
+#define xthal_get_intread	xthal_get_interrupt	/* backward compatibility */
+extern void      xthal_set_intset( unsigned );
+extern void      xthal_set_intclear( unsigned );
+
+
+/*----------------------------------------------------------------------
+   				Debug
+  ----------------------------------------------------------------------*/
+
+/*  Number of instruction and data break registers:  */
+extern const int Xthal_num_ibreak;
+extern const int Xthal_num_dbreak;
+
+
+/*----------------------------------------------------------------------
+   				Core Counter
+  ----------------------------------------------------------------------*/
+
+/* counter info */
+extern const unsigned char Xthal_have_ccount;	/* set if CCOUNT register present */
+extern const unsigned char Xthal_num_ccompare;	/* number of CCOMPAREn registers */
+
+/* get CCOUNT register (if not present return 0) */
+extern unsigned xthal_get_ccount(void);
+
+/* set and get CCOMPAREn registers (if not present, get returns 0) */
+extern void     xthal_set_ccompare(int, unsigned);
+extern unsigned xthal_get_ccompare(int);
+
+
+/*----------------------------------------------------------------------
+                             Miscellaneous
+  ----------------------------------------------------------------------*/
+
+extern const unsigned char Xthal_have_prid;
+extern const unsigned char Xthal_have_exceptions;
+extern const unsigned char Xthal_xea_version;
+extern const unsigned char Xthal_have_interrupts;
+extern const unsigned char Xthal_have_highlevel_interrupts;
+extern const unsigned char Xthal_have_nmi;
+
+extern unsigned xthal_get_prid( void );
+
+
+/*----------------------------------------------------------------------
+		Virtual interrupt prioritization (DEPRECATED)
+  ----------------------------------------------------------------------*/
+
+/*  Convert between interrupt levels (as per PS.INTLEVEL) and virtual interrupt priorities:  */
+extern unsigned	xthal_vpri_to_intlevel(unsigned vpri);
+extern unsigned	xthal_intlevel_to_vpri(unsigned intlevel);
+
+/*  Enables/disables given set (mask) of interrupts; returns previous enabled-mask of all ints:  */
+extern unsigned	xthal_int_enable(unsigned);
+extern unsigned	xthal_int_disable(unsigned);
+
+/*  Set/get virtual priority of an interrupt:  */
+extern int	xthal_set_int_vpri(int intnum, int vpri);
+extern int	xthal_get_int_vpri(int intnum);
+
+/*  Set/get interrupt lockout level for exclusive access to virtual priority data structures:  */
+extern void	xthal_set_vpri_locklevel(unsigned intlevel);
+extern unsigned	xthal_get_vpri_locklevel(void);
+
+/*  Set/get current virtual interrupt priority:  */
+extern unsigned	xthal_set_vpri(unsigned vpri);
+extern unsigned	xthal_get_vpri(void);
+extern unsigned	xthal_set_vpri_intlevel(unsigned intlevel);
+extern unsigned	xthal_set_vpri_lock(void);
+
+
+/*----------------------------------------------------------------------
+	Generic Interrupt Trampolining Support (DEPRECATED)
+  ----------------------------------------------------------------------*/
+
+typedef void (XtHalVoidFunc)(void);
+
+/*  Bitmask of interrupts currently trampolining down:  */
+extern unsigned Xthal_tram_pending;
+
+/*
+ *  Bitmask of which interrupts currently trampolining down synchronously are
+ *  actually enabled; this bitmask is necessary because INTENABLE cannot hold
+ *  that state (sync-trampolining interrupts must be kept disabled while
+ *  trampolining);  in the current implementation, any bit set here is not set
+ *  in INTENABLE, and vice-versa; once a sync-trampoline is handled (at level
+ *  one), its enable bit must be moved from here to INTENABLE:
+ */
+extern unsigned Xthal_tram_enabled;
+
+/*  Bitmask of interrupts configured for sync trampolining:  */
+extern unsigned Xthal_tram_sync;
+
+/*  Trampoline support functions:  */
+extern unsigned  xthal_tram_pending_to_service( void );
+extern void      xthal_tram_done( unsigned serviced_mask );
+extern int       xthal_tram_set_sync( int intnum, int sync );
+extern XtHalVoidFunc* xthal_set_tram_trigger_func( XtHalVoidFunc *trigger_fn );
+
+
+/*----------------------------------------------------------------------
+			Internal Memories
+  ----------------------------------------------------------------------*/
+
+extern const unsigned char Xthal_num_instrom;
+extern const unsigned char Xthal_num_instram;
+extern const unsigned char Xthal_num_datarom;
+extern const unsigned char Xthal_num_dataram;
+extern const unsigned char Xthal_num_xlmi;
+
+/*  Each of the following arrays contains at least one entry,
+ *  or as many entries as needed if more than one:  */
+extern const unsigned int  Xthal_instrom_vaddr[];
+extern const unsigned int  Xthal_instrom_paddr[];
+extern const unsigned int  Xthal_instrom_size [];
+extern const unsigned int  Xthal_instram_vaddr[];
+extern const unsigned int  Xthal_instram_paddr[];
+extern const unsigned int  Xthal_instram_size [];
+extern const unsigned int  Xthal_datarom_vaddr[];
+extern const unsigned int  Xthal_datarom_paddr[];
+extern const unsigned int  Xthal_datarom_size [];
+extern const unsigned int  Xthal_dataram_vaddr[];
+extern const unsigned int  Xthal_dataram_paddr[];
+extern const unsigned int  Xthal_dataram_size [];
+extern const unsigned int  Xthal_xlmi_vaddr[];
+extern const unsigned int  Xthal_xlmi_paddr[];
+extern const unsigned int  Xthal_xlmi_size [];
+
+
+/*----------------------------------------------------------------------
+   				Cache
+  ----------------------------------------------------------------------*/
+
+/* number of cache sets in log2(lines per way) */
+extern const unsigned char Xthal_icache_setwidth;
+extern const unsigned char Xthal_dcache_setwidth;
+/* cache set associativity (number of ways) */
+extern const unsigned int  Xthal_icache_ways;
+extern const unsigned int  Xthal_dcache_ways;
+/* cache features */
+extern const unsigned char Xthal_icache_line_lockable;
+extern const unsigned char Xthal_dcache_line_lockable;
+
+/* cache attribute register control (used by other HAL routines) */
+extern unsigned xthal_get_cacheattr( void );
+extern unsigned xthal_get_icacheattr( void );
+extern unsigned xthal_get_dcacheattr( void );
+extern void     xthal_set_cacheattr( unsigned );
+extern void     xthal_set_icacheattr( unsigned );
+extern void     xthal_set_dcacheattr( unsigned );
+/* set cache attribute (access modes) for a range of memory */
+extern int      xthal_set_region_attribute( void *addr, unsigned size,
+					    unsigned cattr, unsigned flags );
+/*  Bits of flags parameter to xthal_set_region_attribute():  */
+#define XTHAL_CAFLAG_EXPAND		0x000100	/* only expand allowed access to range, don't reduce it */
+#define XTHAL_CAFLAG_EXACT		0x000200	/* return error if can't apply change to exact range specified */
+#define XTHAL_CAFLAG_NO_PARTIAL		0x000400	/* don't apply change to regions partially covered by range */
+#define XTHAL_CAFLAG_NO_AUTO_WB		0x000800	/* don't writeback data after leaving writeback attribute */
+#define XTHAL_CAFLAG_NO_AUTO_INV	0x001000	/* don't invalidate after disabling cache (entering bypass) */
+
+/* enable caches */
+extern void xthal_icache_enable( void );	/* DEPRECATED */
+extern void xthal_dcache_enable( void );	/* DEPRECATED */
+/* disable caches */
+extern void xthal_icache_disable( void );	/* DEPRECATED */
+extern void xthal_dcache_disable( void );	/* DEPRECATED */
+
+/* invalidate the caches */
+extern void xthal_icache_all_invalidate( void );
+extern void xthal_dcache_all_invalidate( void );
+/* write dirty data back */
+extern void xthal_dcache_all_writeback( void );
+/* write dirty data back and invalidate */
+extern void xthal_dcache_all_writeback_inv( void );
+/* prefetch and lock specified memory range into cache */
+extern void xthal_icache_region_lock( void *addr, unsigned size );
+extern void xthal_dcache_region_lock( void *addr, unsigned size );
+extern void xthal_icache_line_lock(void *addr);
+extern void xthal_dcache_line_lock(void *addr);
+/* unlock from cache */
+extern void xthal_icache_all_unlock( void );
+extern void xthal_dcache_all_unlock( void );
+extern void xthal_icache_region_unlock( void *addr, unsigned size );
+extern void xthal_dcache_region_unlock( void *addr, unsigned size );
+extern void xthal_icache_line_unlock(void *addr);
+extern void xthal_dcache_line_unlock(void *addr);
+
+
+
+/*----------------------------------------------------------------------
+                         Local Memory ECC/Parity
+  ----------------------------------------------------------------------*/
+
+/*  Inject memory errors; flags is bit combination of XTHAL_MEMEP_F_xxx:  */
+extern void xthal_memep_inject_error(void *addr, int size, int flags);
+
+
+
+/*----------------------------------------------------------------------
+                         Memory Management Unit
+  ----------------------------------------------------------------------*/
+
+extern const unsigned char Xthal_have_spanning_way;
+extern const unsigned char Xthal_have_identity_map;
+extern const unsigned char Xthal_have_mimic_cacheattr;
+extern const unsigned char Xthal_have_xlt_cacheattr;
+extern const unsigned char Xthal_have_cacheattr;
+extern const unsigned char Xthal_have_tlbs;
+
+extern const unsigned char Xthal_mmu_asid_bits;		/* 0 .. 8 */
+extern const unsigned char Xthal_mmu_asid_kernel;
+extern const unsigned char Xthal_mmu_rings;		/* 1 .. 4 (perhaps 0 if no MMU and/or no protection?) */
+extern const unsigned char Xthal_mmu_ring_bits;
+extern const unsigned char Xthal_mmu_sr_bits;
+extern const unsigned char Xthal_mmu_ca_bits;
+extern const unsigned int  Xthal_mmu_max_pte_page_size;
+extern const unsigned int  Xthal_mmu_min_pte_page_size;
+
+extern const unsigned char Xthal_itlb_way_bits;
+extern const unsigned char Xthal_itlb_ways;
+extern const unsigned char Xthal_itlb_arf_ways;
+extern const unsigned char Xthal_dtlb_way_bits;
+extern const unsigned char Xthal_dtlb_ways;
+extern const unsigned char Xthal_dtlb_arf_ways;
+
+/*  Convert between virtual and physical addresses (through static maps only):  */
+/*** WARNING: these two functions may go away in a future release; don't depend on them! ***/
+extern int  xthal_static_v2p( unsigned vaddr, unsigned *paddrp );
+extern int  xthal_static_p2v( unsigned paddr, unsigned *vaddrp, unsigned cached );
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+
+
+
+/****************************************************************************
+		EXPERIMENTAL and DEPRECATED Definitions
+ ****************************************************************************/
+
+
+#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef INCLUDE_DEPRECATED_HAL_CODE
+extern const unsigned char Xthal_have_old_exc_arch;
+extern const unsigned char Xthal_have_mmu;
+extern const unsigned int  Xthal_num_regs;
+extern const unsigned char Xthal_num_iroms;
+extern const unsigned char Xthal_num_irams;
+extern const unsigned char Xthal_num_droms;
+extern const unsigned char Xthal_num_drams;
+extern const unsigned int  Xthal_configid0;
+extern const unsigned int  Xthal_configid1;
+#endif
+
+#ifdef INCLUDE_DEPRECATED_HAL_DEBUG_CODE
+#define XTHAL_24_BIT_BREAK		0x80000000
+#define XTHAL_16_BIT_BREAK		0x40000000
+extern const unsigned short	Xthal_ill_inst_16[16];
+#define XTHAL_DEST_REG		0xf0000000	/* Mask for destination register */
+#define XTHAL_DEST_REG_INST	0x08000000	/* Branch address is in register */
+#define XTHAL_DEST_REL_INST	0x04000000	/* Branch address is relative */
+#define XTHAL_RFW_INST		0x00000800
+#define XTHAL_RFUE_INST		0x00000400
+#define XTHAL_RFI_INST		0x00000200
+#define XTHAL_RFE_INST		0x00000100
+#define XTHAL_RET_INST		0x00000080
+#define XTHAL_BREAK_INST	0x00000040
+#define XTHAL_SYSCALL_INST	0x00000020
+#define XTHAL_LOOP_END		0x00000010	/* Not set by xthal_inst_type */
+#define XTHAL_JUMP_INST		0x00000008	/* Call or jump instruction */
+#define XTHAL_BRANCH_INST	0x00000004	/* Branch instruction */
+#define XTHAL_24_BIT_INST	0x00000002
+#define XTHAL_16_BIT_INST   0x00000001
+typedef struct xthal_state {
+    unsigned	pc;
+    unsigned	ar[16];
+    unsigned	lbeg;
+    unsigned	lend;
+    unsigned	lcount;
+    unsigned	extra_ptr;
+    unsigned	cpregs_ptr[XTHAL_MAX_CPS];
+} XTHAL_STATE;
+extern unsigned int xthal_inst_type(void *addr);
+extern unsigned int xthal_branch_addr(void *addr);
+extern unsigned int xthal_get_npc(XTHAL_STATE *user_state);
+#endif /* INCLUDE_DEPRECATED_HAL_DEBUG_CODE */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*!_ASMLANGUAGE && !_NOCLANGUAGE && !__ASSEMBLER__ */
+
+#endif /*XTENSA_HAL_H*/
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/sim.h

@@ -0,0 +1,60 @@
+/* Copyright (c) 2004-2006 by Tensilica Inc.  ALL RIGHTS RESERVED.
+/  These coded instructions, statements, and computer programs are the
+/  copyrighted works and confidential proprietary information of Tensilica Inc.
+/  They may not be modified, copied, reproduced, distributed, or disclosed to
+/  third parties in any manner, medium, or form, in whole or in part, without
+/  the prior written consent of Tensilica Inc.
+*/
+
+/*  sim.h 
+ *
+ *  Definitions and prototypes for specific ISS SIMCALLs
+ *  (ie. outside the standard C library).
+ */
+
+#ifndef _INC_SIM_H_
+#define _INC_SIM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Shortcuts for enabling/disabling profiling in the Xtensa ISS  */
+extern void xt_iss_profile_enable(void);
+extern void xt_iss_profile_disable(void);
+
+/* Shortcut for setting the trace level in the Xtensa ISS */
+extern void xt_iss_trace_level(unsigned level);
+
+/* Generic interface for passing client commands in the Xtensa ISS:
+ *   returns 0 on success, -1 on failure.
+ */
+extern int xt_iss_client_command(const char *client, const char *command);
+
+/* Interface for switching simulation modes in the Xtensa ISS:
+ *   returns 0 on success, -1 on failure.
+ */
+#define XT_ISS_CYCLE_ACCURATE 0
+#define XT_ISS_FUNCTIONAL     1
+extern int xt_iss_switch_mode(int mode);
+
+
+/* Interface for waiting on a system synchronization event */
+extern void xt_iss_event_wait(unsigned event_id);
+
+/* Interface for firing a system synchronization event */
+extern void xt_iss_event_fire(unsigned event_id);
+
+/* Interface for invoking a user simcall action,
+ * which can be registered in XTMP or XTSC.
+ */
+extern int xt_iss_simcall(int arg1, int arg2, int arg3,
+                          int arg4, int arg5, int arg6);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_INC_SIM_H_*/
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/simcall-errno.h

@@ -0,0 +1,139 @@
+/* Error numbers for Xtensa ISS semihosting.  */
+
+/* Copyright (c) 2003 by Tensilica Inc.  ALL RIGHTS RESERVED.
+   These coded instructions, statements, and computer programs are the
+   copyrighted works and confidential proprietary information of Tensilica Inc.
+   They may not be modified, copied, reproduced, distributed, or disclosed to
+   third parties in any manner, medium, or form, in whole or in part, without
+   the prior written consent of Tensilica Inc.  */
+
+#ifndef _SIMCALL_ERRNO_H
+#define _SIMCALL_ERRNO_H
+
+/* Define the error numbers (using the default newlib values) with prefixes
+   so they can be used in ISS without conflicting with the host values.  */
+
+#define	_SIMC_EPERM	1
+#define	_SIMC_ENOENT	2
+#define	_SIMC_ESRCH	3
+#define	_SIMC_EINTR	4
+#define	_SIMC_EIO	5
+#define	_SIMC_ENXIO	6
+#define	_SIMC_E2BIG	7
+#define	_SIMC_ENOEXEC	8
+#define	_SIMC_EBADF	9
+#define	_SIMC_ECHILD	10
+#define	_SIMC_EAGAIN	11
+#define	_SIMC_ENOMEM	12
+#define	_SIMC_EACCES	13
+#define	_SIMC_EFAULT	14
+#define	_SIMC_ENOTBLK	15
+#define	_SIMC_EBUSY	16
+#define	_SIMC_EEXIST	17
+#define	_SIMC_EXDEV	18
+#define	_SIMC_ENODEV	19
+#define	_SIMC_ENOTDIR	20
+#define	_SIMC_EISDIR	21
+#define	_SIMC_EINVAL	22
+#define	_SIMC_ENFILE	23
+#define	_SIMC_EMFILE	24
+#define	_SIMC_ENOTTY	25
+#define	_SIMC_ETXTBSY	26
+#define	_SIMC_EFBIG	27
+#define	_SIMC_ENOSPC	28
+#define	_SIMC_ESPIPE	29
+#define	_SIMC_EROFS	30
+#define	_SIMC_EMLINK	31
+#define	_SIMC_EPIPE	32
+#define	_SIMC_EDOM	33
+#define	_SIMC_ERANGE	34
+#define	_SIMC_ENOMSG	35
+#define	_SIMC_EIDRM	36
+#define	_SIMC_ECHRNG	37
+#define	_SIMC_EL2NSYNC	38
+#define	_SIMC_EL3HLT	39
+#define	_SIMC_EL3RST	40
+#define	_SIMC_ELNRNG	41
+#define	_SIMC_EUNATCH	42
+#define	_SIMC_ENOCSI	43
+#define	_SIMC_EL2HLT	44
+#define	_SIMC_EDEADLK	45
+#define	_SIMC_ENOLCK	46
+#define _SIMC_EBADE	50
+#define _SIMC_EBADR	51
+#define _SIMC_EXFULL	52
+#define _SIMC_ENOANO	53
+#define _SIMC_EBADRQC	54
+#define _SIMC_EBADSLT	55
+#define _SIMC_EDEADLOCK	56
+#define _SIMC_EBFONT	57
+#define _SIMC_ENOSTR	60
+#define _SIMC_ENODATA	61
+#define _SIMC_ETIME	62
+#define _SIMC_ENOSR	63
+#define _SIMC_ENONET	64
+#define _SIMC_ENOPKG	65
+#define _SIMC_EREMOTE	66
+#define _SIMC_ENOLINK	67
+#define _SIMC_EADV	68
+#define _SIMC_ESRMNT	69
+#define	_SIMC_ECOMM	70
+#define _SIMC_EPROTO	71
+#define	_SIMC_EMULTIHOP	74
+#define	_SIMC_ELBIN	75
+#define	_SIMC_EDOTDOT	76
+#define _SIMC_EBADMSG	77
+#define _SIMC_EFTYPE	79
+#define _SIMC_ENOTUNIQ	80
+#define _SIMC_EBADFD	81
+#define _SIMC_EREMCHG	82
+#define _SIMC_ELIBACC	83
+#define _SIMC_ELIBBAD	84
+#define _SIMC_ELIBSCN	85
+#define _SIMC_ELIBMAX	86
+#define _SIMC_ELIBEXEC	87
+#define _SIMC_ENOSYS	88
+#define	_SIMC_ENMFILE	89
+#define _SIMC_ENOTEMPTY 90
+#define _SIMC_ENAMETOOLONG 91
+#define _SIMC_ELOOP 92
+#define _SIMC_EOPNOTSUPP 95
+#define _SIMC_EPFNOSUPPORT 96
+#define _SIMC_ECONNRESET 104
+#define _SIMC_ENOBUFS 105
+#define _SIMC_EAFNOSUPPORT 106
+#define _SIMC_EPROTOTYPE 107
+#define _SIMC_ENOTSOCK 108
+#define _SIMC_ENOPROTOOPT 109
+#define _SIMC_ESHUTDOWN 110
+#define _SIMC_ECONNREFUSED 111
+#define _SIMC_EADDRINUSE 112
+#define _SIMC_ECONNABORTED 113
+#define _SIMC_ENETUNREACH 114
+#define _SIMC_ENETDOWN 115
+#define _SIMC_ETIMEDOUT 116
+#define _SIMC_EHOSTDOWN 117
+#define _SIMC_EHOSTUNREACH 118
+#define _SIMC_EINPROGRESS 119
+#define _SIMC_EALREADY 120
+#define _SIMC_EDESTADDRREQ 121
+#define _SIMC_EMSGSIZE 122
+#define _SIMC_EPROTONOSUPPORT 123
+#define _SIMC_ESOCKTNOSUPPORT 124
+#define _SIMC_EADDRNOTAVAIL 125
+#define _SIMC_ENETRESET 126
+#define _SIMC_EISCONN 127
+#define _SIMC_ENOTCONN 128
+#define _SIMC_ETOOMANYREFS 129
+#define	_SIMC_EPROCLIM 130
+#define _SIMC_EUSERS 131
+#define _SIMC_EDQUOT 132
+#define _SIMC_ESTALE 133
+#define _SIMC_ENOTSUP 134
+#define _SIMC_ENOMEDIUM 135
+#define	_SIMC_ENOSHARE 136
+#define	_SIMC_ECASECLASH 137
+#define _SIMC_EILSEQ 138
+#define _SIMC_EOVERFLOW 139
+
+#endif /* ! _SIMCALL_ERRNO_H */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/simcall-fcntl.h

@@ -0,0 +1,21 @@
+/* File control operations for Xtensa ISS semihosting.  */
+
+/* Copyright (c) 2003 by Tensilica Inc.  ALL RIGHTS RESERVED.
+   These coded instructions, statements, and computer programs are the
+   copyrighted works and confidential proprietary information of Tensilica Inc.
+   They may not be modified, copied, reproduced, distributed, or disclosed to
+   third parties in any manner, medium, or form, in whole or in part, without
+   the prior written consent of Tensilica Inc.  */
+
+#ifndef _SIMCALL_FCNTL_H
+#define _SIMCALL_FCNTL_H
+
+#define	_SIMC_O_APPEND		0x0008
+#define	_SIMC_O_NONBLOCK	0x0080
+#define	_SIMC_O_CREAT		0x0100
+#define	_SIMC_O_TRUNC		0x0200
+#define	_SIMC_O_EXCL		0x0400
+#define _SIMC_O_TEXT		0x4000
+#define _SIMC_O_BINARY		0x8000
+
+#endif /* ! _SIMCALL_FCNTL_H */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/simcall.h

@@ -0,0 +1,188 @@
+/*
+ *  simcall.h  -  Simulator call numbers
+ *
+ *  Software that runs on a simulated Xtensa processor using
+ *  the instruction set simulator (ISS) can invoke simulator
+ *  services using the SIMCALL instruction.  The a2 register
+ *  is set prior to executing SIMCALL to a "simcall number",
+ *  indicating which service to invoke.  This file defines the
+ *  simcall numbers defined and/or supported by the Xtensa ISS.
+ *
+ *  IMPORTANT NOTE:  These numbers are highly subject to change!
+ *
+ *  Copyright (c) 2002-2007 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ *  These coded instructions, statements, and computer programs are the
+ *  copyrighted works and confidential proprietary information of Tensilica Inc.
+ *  They may not be modified, copied, reproduced, distributed, or disclosed to
+ *  third parties in any manner, medium, or form, in whole or in part, without
+ *  the prior written consent of Tensilica Inc.
+ */
+
+#ifndef SIMCALL_INCLUDED
+#define SIMCALL_INCLUDED
+
+/*
+ *  System call like services offered by the simulator host.
+ *  These are modeled after the Linux 2.4 kernel system calls
+ *  for Xtensa processors.  However not all system calls and
+ *  not all functionality of a given system call are implemented,
+ *  or necessarily have well defined or equivalent semantics in
+ *  the context of a simulation (as opposed to a Unix kernel).
+ *
+ *  These services behave largely as if they had been invoked
+ *  as a task in the simulator host's operating system
+ *  (eg. files accessed are those of the simulator host).
+ *  However, these SIMCALLs model a virtual operating system
+ *  so that various definitions, bit assignments etc
+ *  (eg. open mode bits, errno values, etc) are independent
+ *  of the host operating system used to run the simulation.
+ *  Rather these definitions are specific to the Xtensa ISS.
+ *  This way Xtensa ISA code written to use these SIMCALLs
+ *  can (in principle) be simulated on any host.
+ *
+ *  Up to 6 parameters are passed in registers a3 to a8
+ *  (note the 6th parameter isn't passed on the stack,
+ *   unlike windowed function calling conventions).
+ *  The return value is in a2.  A negative value in the
+ *  range -4096 to -1 indicates a negated error code to be
+ *  reported in errno with a return value of -1, otherwise
+ *  the value in a2 is returned as is.
+ */
+
+/* These #defines need to match what's in Xtensa/OS/vxworks/xtiss/simcalls.c */
+
+#define SYS_nop		0	/* n/a - setup; used to flush register windows */
+#define SYS_exit	1	/*x*/
+#define SYS_fork	2
+#define SYS_read	3	/*x*/
+#define SYS_write	4	/*x*/
+#define SYS_open	5	/*x*/
+#define SYS_close	6	/*x*/
+#define SYS_rename	7	/*x 38 - waitpid */
+#define SYS_creat	8	/*x*/
+#define SYS_link	9	/*x (not implemented on WIN32) */
+#define SYS_unlink	10	/*x*/
+#define SYS_execv	11	/* n/a - execve */
+#define SYS_execve	12	/* 11 - chdir */
+#define SYS_pipe	13	/* 42 - time */
+#define SYS_stat	14	/* 106 - mknod */
+#define SYS_chmod	15
+#define SYS_chown	16	/* 202 - lchown */
+#define SYS_utime	17	/* 30 - break */
+#define SYS_wait	18	/* n/a - oldstat */
+#define SYS_lseek	19	/*x*/
+#define SYS_getpid	20
+#define SYS_isatty	21	/* n/a - mount */
+#define SYS_fstat	22	/* 108 - oldumount */
+#define SYS_time	23	/* 13 - setuid */
+#define SYS_gettimeofday 24	/*x 78 - getuid (not implemented on WIN32) */
+#define SYS_times	25	/*X 43 - stime (Xtensa-specific implementation) */
+#define SYS_socket      26
+#define SYS_sendto      27
+#define SYS_recvfrom    28
+#define SYS_select_one  29      /* not compitible select, one file descriptor at the time */
+#define SYS_bind        30
+#define SYS_ioctl       31
+
+/*
+ *  Other...
+ */
+#define SYS_iss_argc         1000 /* returns value of argc */
+#define SYS_iss_argv_size    1001 /* bytes needed for argv & arg strings */
+#define SYS_iss_set_argv     1002 /* saves argv & arg strings at given addr */
+
+#define SYS_memset           1004 /* fill a range of memory (fast) */
+
+/*
+ * SIMCALLs for the ferret memory debugger. All are invoked by
+ * libferret.a ...  ( Xtensa/Target-Libs/ferret )
+ */
+#define SYS_ferret           1010
+#define SYS_malloc           1011
+#define SYS_free             1012
+#define SYS_more_heap        1013
+#define SYS_no_heap          1014
+#define SYS_enter_ferret     1015
+#define SYS_leave_ferret     1016
+
+/*
+ * SIMCALLs for ISS client commands
+ */
+#define SYS_profile_enable   1020
+#define SYS_profile_disable  1021
+#define SYS_trace_level      1022
+#define SYS_client_command   1023
+
+/*
+ * SIMCALL for simulation mode switching
+ */
+#define SYS_sim_mode_switch  1030
+
+/*
+ * SIMCALLs for XTMP/XTSC event notify and core stall
+ */
+#define SYS_event_fire       1040
+#define SYS_event_stall      1041
+
+/*
+ *  SIMCALLs for callbacks registered in XTMP/XTSC
+ */
+#define SYS_callback_first      100
+#define SYS_callback_last       999
+
+/*
+ * User defined simcall 
+ */
+#define SYS_user_simcall        100
+
+#define SYS_xmpa_errinfo        200
+#define SYS_xmpa_proc_status    201
+#define SYS_xmpa_proc_start     202
+#define SYS_xmpa_proc_stop      203
+#define SYS_xmpa_proc_mem_read  204
+#define SYS_xmpa_proc_mem_write 205
+#define SYS_xmpa_proc_mem_fill  206
+#define SYS_xmpa_proc_reg_read  207
+#define SYS_xmpa_proc_reg_write 208
+
+
+/*
+ *  Extra SIMCALLs for GDB:
+ */
+#define SYS_gdb_break         -1	/* invoked by XTOS on user exceptions if EPC points
+					   to a break.n/break, regardless of cause! */
+#define SYS_xmon_out          -2	/* invoked by XMON: ... */
+#define SYS_xmon_in           -3	/* invoked by XMON: ... */
+#define SYS_xmon_flush        -4	/* invoked by XMON: ... */
+#define SYS_gdb_abort         -5	/* invoked by XTOS in _xtos_panic() */
+#define SYS_gdb_illegal_inst  -6	/* invoked by XTOS for illegal instructions (too deeply) */
+#define SYS_xmon_init         -7	/* invoked by XMON: ... */
+#define SYS_gdb_enter_sktloop -8	/* invoked by XTOS on debug exceptions */
+#define SYS_unhandled_kernel_exc  -9	/* invoked by XTOS for unhandled kernel exceptions */
+#define SYS_unhandled_user_exc   -10	/* invoked by XTOS for unhandled user exceptions */
+#define SYS_unhandled_double_exc -11	/* invoked by XTOS for unhandled double exceptions */
+#define SYS_unhandled_highpri_interrupt -12	/* invoked by XTOS for unhandled high-priority interrupts */
+
+/*
+ *  SIMCALLs for vxWorks xtiss BSP:
+ */
+#define SYS_setup_ppp_pipes   -83
+#define SYS_log_msg           -84
+
+/*
+ * SYS_select_one specifiers 
+ */
+#define  XTISS_SELECT_ONE_READ    1
+#define  XTISS_SELECT_ONE_WRITE   2
+#define  XTISS_SELECT_ONE_EXCEPT  3
+
+/*
+ * SIMCALL for client calling arbitrary code in a client plug in.
+ * see clients/xcc_instr to see how this works.
+ */
+
+#define SYS_client           0xC0DECAFE
+
+
+
+#endif /* !SIMCALL_INCLUDED */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/specreg.h

@@ -0,0 +1,138 @@
+/*
+ * Xtensa Special Register symbolic names
+ */
+
+/* $Id: //depot/rel/Boreal/Xtensa/OS/include/xtensa/specreg.h#2 $ */
+
+/*
+ * Copyright (c) 2005-2010 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTENSA_SPECREG_H
+#define XTENSA_SPECREG_H
+
+/*  Special registers:  */
+#define LBEG		0
+#define LEND		1
+#define LCOUNT		2
+#define SAR		3
+#define BR		4
+#define LITBASE		5
+#define SCOMPARE1	12
+#define ACCLO		16
+#define ACCHI		17
+#define MR_0		32
+#define MR_1		33
+#define MR_2		34
+#define MR_3		35
+#define PREFCTL		40
+#define WINDOWBASE	72
+#define WINDOWSTART	73
+#define PTEVADDR	83
+#define RASID		90
+#define ITLBCFG		91
+#define DTLBCFG		92
+#define IBREAKENABLE	96
+#define CACHEATTR	98
+#define DDR		104
+#define IBREAKA_0	128
+#define IBREAKA_1	129
+#define DBREAKA_0	144
+#define DBREAKA_1	145
+#define DBREAKC_0	160
+#define DBREAKC_1	161
+#define EPC_1		177
+#define EPC_2		178
+#define EPC_3		179
+#define EPC_4		180
+#define EPC_5		181
+#define EPC_6		182
+#define EPC_7		183
+#define DEPC		192
+#define EPS_2		194
+#define EPS_3		195
+#define EPS_4		196
+#define EPS_5		197
+#define EPS_6		198
+#define EPS_7		199
+#define EXCSAVE_1	209
+#define EXCSAVE_2	210
+#define EXCSAVE_3	211
+#define EXCSAVE_4	212
+#define EXCSAVE_5	213
+#define EXCSAVE_6	214
+#define EXCSAVE_7	215
+#define CPENABLE	224
+#define INTERRUPT	226
+#define INTREAD		INTERRUPT	/* alternate name for backward compatibility */
+#define INTSET		INTERRUPT	/* alternate name for backward compatibility */
+#define INTCLEAR	227
+#define INTENABLE	228
+#define PS		230
+#define VECBASE		231
+#define EXCCAUSE	232
+#define DEBUGCAUSE	233
+#define CCOUNT		234
+#define PRID		235
+#define ICOUNT		236
+#define ICOUNTLEVEL	237
+#define EXCVADDR	238
+#define CCOMPARE_0	240
+#define CCOMPARE_1	241
+#define CCOMPARE_2	242
+#define MISC_REG_0	244
+#define MISC_REG_1	245
+#define MISC_REG_2	246
+#define MISC_REG_3	247
+
+/*  Special cases (bases of special register series):  */
+#define MR		32
+#define IBREAKA		128
+#define DBREAKA		144
+#define DBREAKC		160
+#define EPC		176
+#define EPS		192
+#define EXCSAVE		208
+#define CCOMPARE	240
+#define MISC_REG	244
+
+/*  Tensilica-defined user registers:  */
+#if 0
+/*#define ...	 21..24 */	/* (545CK) */
+/*#define ...	140..143 */	/* (545CK) */
+#define EXPSTATE	230	/* Diamond */
+#define THREADPTR	231	/* threadptr option */
+#define FCR		232	/* FPU */
+#define FSR		233	/* FPU */
+#define AE_OVF_SAR	240	/* HiFi2 */
+#define AE_BITHEAD	241	/* HiFi2 */
+#define AE_TS_FTS_BU_BP	242	/* HiFi2 */
+#define AE_SD_NO	243	/* HiFi2 */
+#define VSAR		240	/* VectraLX */
+#define ROUND_LO	242	/* VectraLX */
+#define ROUND_HI	243	/* VectraLX */
+#define CBEGIN		246	/* VectraLX */
+#define CEND		247	/* VectraLX */
+#endif
+
+#endif /* XTENSA_SPECREG_H */
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_MUL32.h

@@ -0,0 +1,24 @@
+/* Definitions for the 32-bit Integer Multiply Option. */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2009 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* NOTE: This file exists only for backward compatibility with RB-200X.x
+   and earlier Xtensa releases.  Starting with RC-2009.0 you should use 
+   <xtensa/tie/xt_mul.h>.  */
+
+#ifndef _XTENSA_xt_MUL32_HEADER
+#define _XTENSA_xt_MUL32_HEADER
+
+#ifdef __XTENSA__
+
+#include <xtensa/tie/xt_mul.h>
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_MUL32_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_core.h

@@ -0,0 +1,254 @@
+/* Definitions for the xt_core TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_core_HEADER
+#define _XTENSA_xt_core_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern void _TIE_xt_core_ILL(void);
+extern void _TIE_xt_core_NOP(void);
+extern void _TIE_xt_core_MEMW(void);
+extern void _TIE_xt_core_EXTW(void);
+extern void _TIE_xt_core_ISYNC(void);
+extern void _TIE_xt_core_DSYNC(void);
+extern void _TIE_xt_core_ESYNC(void);
+extern void _TIE_xt_core_RSYNC(void);
+extern unsigned _TIE_xt_core_RSR_176(void);
+extern void _TIE_xt_core_WSR_176(unsigned art);
+extern unsigned _TIE_xt_core_RSR_208(void);
+extern unsigned _TIE_xt_core_uint32_loadi(const unsigned * p, immediate o);
+extern void _TIE_xt_core_uint32_storei(unsigned c, unsigned * p, immediate o);
+extern unsigned _TIE_xt_core_uint32_move(unsigned b);
+extern int _TIE_xt_core_ADDI(int s, immediate i);
+extern int _TIE_xt_core_OR(int s, int t);
+extern int _TIE_xt_core_L32I(const int * p, immediate i);
+extern void _TIE_xt_core_S32I(int r, int * p, immediate i);
+extern unsigned char _TIE_xt_core_L8UI(const unsigned char * p, immediate i);
+extern void _TIE_xt_core_S8I(signed char r, signed char * p, immediate i);
+extern unsigned short _TIE_xt_core_L16UI(const unsigned short * p, immediate i);
+extern short _TIE_xt_core_L16SI(const short * p, immediate i);
+extern void _TIE_xt_core_S16I(short r, short * p, immediate i);
+extern int _TIE_xt_core_ADDMI(int s, immediate i);
+extern int _TIE_xt_core_ADD(int s, int t);
+extern int _TIE_xt_core_ADDX2(int s, int t);
+extern int _TIE_xt_core_ADDX4(int s, int t);
+extern int _TIE_xt_core_ADDX8(int s, int t);
+extern int _TIE_xt_core_SUB(int s, int t);
+extern int _TIE_xt_core_SUBX2(int s, int t);
+extern int _TIE_xt_core_SUBX4(int s, int t);
+extern int _TIE_xt_core_SUBX8(int s, int t);
+extern int _TIE_xt_core_AND(int s, int t);
+extern int _TIE_xt_core_XOR(int s, int t);
+extern unsigned _TIE_xt_core_EXTUI(unsigned t, immediate i, immediate o);
+extern int _TIE_xt_core_MOVI(immediate i);
+extern void _TIE_xt_core_MOVEQZ(int r /*inout*/, int s, int t);
+extern void _TIE_xt_core_MOVNEZ(int r /*inout*/, int s, int t);
+extern void _TIE_xt_core_MOVLTZ(int r /*inout*/, int s, int t);
+extern void _TIE_xt_core_MOVGEZ(int r /*inout*/, int s, int t);
+extern int _TIE_xt_core_NEG(int t);
+extern int _TIE_xt_core_ABS(int t);
+extern void _TIE_xt_core_SSR(int s);
+extern void _TIE_xt_core_SSL(int s);
+extern void _TIE_xt_core_SSA8L(int s);
+extern void _TIE_xt_core_SSA8B(int s);
+extern void _TIE_xt_core_SSAI(immediate i);
+extern int _TIE_xt_core_SLL(int s);
+extern int _TIE_xt_core_SRC(int s, int t);
+extern unsigned _TIE_xt_core_SRL(unsigned t);
+extern int _TIE_xt_core_SRA(int t);
+extern int _TIE_xt_core_SLLI(int s, immediate i);
+extern int _TIE_xt_core_SRAI(int t, immediate i);
+extern unsigned _TIE_xt_core_SRLI(unsigned t, immediate i);
+extern int _TIE_xt_core_SSAI_SRC(int src1, int src2, immediate amount);
+extern int _TIE_xt_core_SSR_SRC(int src1, int src2, int amount);
+extern int _TIE_xt_core_WSR_SAR_SRC(int src1, int src2, int amount);
+extern int _TIE_xt_core_SSR_SRA(int src, int amount);
+extern unsigned _TIE_xt_core_SSR_SRL(unsigned src, int amount);
+extern int _TIE_xt_core_SSL_SLL(int src, int amount);
+extern int _TIE_xt_core_RSIL(immediate t);
+extern unsigned _TIE_xt_core_RSR_SAR(void);
+extern void _TIE_xt_core_WSR_SAR(unsigned t);
+extern void _TIE_xt_core_XSR_SAR(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_LITBASE(void);
+extern void _TIE_xt_core_WSR_LITBASE(unsigned t);
+extern void _TIE_xt_core_XSR_LITBASE(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_PS(void);
+extern void _TIE_xt_core_WSR_PS(unsigned t);
+extern void _TIE_xt_core_XSR_PS(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_EPC1(void);
+extern void _TIE_xt_core_WSR_EPC1(unsigned t);
+extern void _TIE_xt_core_XSR_EPC1(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_EXCSAVE1(void);
+extern void _TIE_xt_core_WSR_EXCSAVE1(unsigned t);
+extern void _TIE_xt_core_XSR_EXCSAVE1(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_EPC2(void);
+extern void _TIE_xt_core_WSR_EPC2(unsigned t);
+extern void _TIE_xt_core_XSR_EPC2(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_EXCSAVE2(void);
+extern void _TIE_xt_core_WSR_EXCSAVE2(unsigned t);
+extern void _TIE_xt_core_XSR_EXCSAVE2(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_EPC3(void);
+extern void _TIE_xt_core_WSR_EPC3(unsigned t);
+extern void _TIE_xt_core_XSR_EPC3(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_EXCSAVE3(void);
+extern void _TIE_xt_core_WSR_EXCSAVE3(unsigned t);
+extern void _TIE_xt_core_XSR_EXCSAVE3(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_VECBASE(void);
+extern void _TIE_xt_core_WSR_VECBASE(unsigned t);
+extern void _TIE_xt_core_XSR_VECBASE(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_EPS2(void);
+extern void _TIE_xt_core_WSR_EPS2(unsigned t);
+extern void _TIE_xt_core_XSR_EPS2(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_EPS3(void);
+extern void _TIE_xt_core_WSR_EPS3(unsigned t);
+extern void _TIE_xt_core_XSR_EPS3(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_EXCCAUSE(void);
+extern void _TIE_xt_core_WSR_EXCCAUSE(unsigned t);
+extern void _TIE_xt_core_XSR_EXCCAUSE(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_EXCVADDR(void);
+extern void _TIE_xt_core_WSR_EXCVADDR(unsigned t);
+extern void _TIE_xt_core_XSR_EXCVADDR(unsigned t /*inout*/);
+extern unsigned _TIE_xt_core_RSR_DEPC(void);
+extern void _TIE_xt_core_WSR_DEPC(unsigned t);
+extern void _TIE_xt_core_XSR_DEPC(unsigned t /*inout*/);
+extern int _TIE_xt_core_RSR_PRID(void);
+#define XT_ILL _TIE_xt_core_ILL
+#define XT_NOP _TIE_xt_core_NOP
+#define XT_MEMW _TIE_xt_core_MEMW
+#define XT_EXTW _TIE_xt_core_EXTW
+#define XT_ISYNC _TIE_xt_core_ISYNC
+#define XT_DSYNC _TIE_xt_core_DSYNC
+#define XT_ESYNC _TIE_xt_core_ESYNC
+#define XT_RSYNC _TIE_xt_core_RSYNC
+#define XT_RSR_176 _TIE_xt_core_RSR_176
+#define XT_WSR_176 _TIE_xt_core_WSR_176
+#define XT_RSR_208 _TIE_xt_core_RSR_208
+#define XT_uint32_loadi _TIE_xt_core_uint32_loadi
+#define XT_uint32_storei _TIE_xt_core_uint32_storei
+#define XT_uint32_move _TIE_xt_core_uint32_move
+#define XT_ADDI _TIE_xt_core_ADDI
+#define XT_OR _TIE_xt_core_OR
+#define XT_L32I _TIE_xt_core_L32I
+#define XT_S32I _TIE_xt_core_S32I
+#define XT_L8UI _TIE_xt_core_L8UI
+#define XT_S8I _TIE_xt_core_S8I
+#define XT_L16UI _TIE_xt_core_L16UI
+#define XT_L16SI _TIE_xt_core_L16SI
+#define XT_S16I _TIE_xt_core_S16I
+#define XT_ADDMI _TIE_xt_core_ADDMI
+#define XT_ADD _TIE_xt_core_ADD
+#define XT_ADDX2 _TIE_xt_core_ADDX2
+#define XT_ADDX4 _TIE_xt_core_ADDX4
+#define XT_ADDX8 _TIE_xt_core_ADDX8
+#define XT_SUB _TIE_xt_core_SUB
+#define XT_SUBX2 _TIE_xt_core_SUBX2
+#define XT_SUBX4 _TIE_xt_core_SUBX4
+#define XT_SUBX8 _TIE_xt_core_SUBX8
+#define XT_AND _TIE_xt_core_AND
+#define XT_XOR _TIE_xt_core_XOR
+#define XT_EXTUI _TIE_xt_core_EXTUI
+#define XT_MOVI _TIE_xt_core_MOVI
+#define XT_MOVEQZ _TIE_xt_core_MOVEQZ
+#define XT_MOVNEZ _TIE_xt_core_MOVNEZ
+#define XT_MOVLTZ _TIE_xt_core_MOVLTZ
+#define XT_MOVGEZ _TIE_xt_core_MOVGEZ
+#define XT_NEG _TIE_xt_core_NEG
+#define XT_ABS _TIE_xt_core_ABS
+#define XT_SSR _TIE_xt_core_SSR
+#define XT_SSL _TIE_xt_core_SSL
+#define XT_SSA8L _TIE_xt_core_SSA8L
+#define XT_SSA8B _TIE_xt_core_SSA8B
+#define XT_SSAI _TIE_xt_core_SSAI
+#define XT_SLL _TIE_xt_core_SLL
+#define XT_SRC _TIE_xt_core_SRC
+#define XT_SRL _TIE_xt_core_SRL
+#define XT_SRA _TIE_xt_core_SRA
+#define XT_SLLI _TIE_xt_core_SLLI
+#define XT_SRAI _TIE_xt_core_SRAI
+#define XT_SRLI _TIE_xt_core_SRLI
+#define XT_SSAI_SRC _TIE_xt_core_SSAI_SRC
+#define XT_SSR_SRC _TIE_xt_core_SSR_SRC
+#define XT_WSR_SAR_SRC _TIE_xt_core_WSR_SAR_SRC
+#define XT_SSR_SRA _TIE_xt_core_SSR_SRA
+#define XT_SSR_SRL _TIE_xt_core_SSR_SRL
+#define XT_SSL_SLL _TIE_xt_core_SSL_SLL
+#define XT_RSIL _TIE_xt_core_RSIL
+#define XT_RSR_SAR _TIE_xt_core_RSR_SAR
+#define XT_WSR_SAR _TIE_xt_core_WSR_SAR
+#define XT_XSR_SAR _TIE_xt_core_XSR_SAR
+#define XT_RSR_LITBASE _TIE_xt_core_RSR_LITBASE
+#define XT_WSR_LITBASE _TIE_xt_core_WSR_LITBASE
+#define XT_XSR_LITBASE _TIE_xt_core_XSR_LITBASE
+#define XT_RSR_PS _TIE_xt_core_RSR_PS
+#define XT_WSR_PS _TIE_xt_core_WSR_PS
+#define XT_XSR_PS _TIE_xt_core_XSR_PS
+#define XT_RSR_EPC1 _TIE_xt_core_RSR_EPC1
+#define XT_WSR_EPC1 _TIE_xt_core_WSR_EPC1
+#define XT_XSR_EPC1 _TIE_xt_core_XSR_EPC1
+#define XT_RSR_EXCSAVE1 _TIE_xt_core_RSR_EXCSAVE1
+#define XT_WSR_EXCSAVE1 _TIE_xt_core_WSR_EXCSAVE1
+#define XT_XSR_EXCSAVE1 _TIE_xt_core_XSR_EXCSAVE1
+#define XT_RSR_EPC2 _TIE_xt_core_RSR_EPC2
+#define XT_WSR_EPC2 _TIE_xt_core_WSR_EPC2
+#define XT_XSR_EPC2 _TIE_xt_core_XSR_EPC2
+#define XT_RSR_EXCSAVE2 _TIE_xt_core_RSR_EXCSAVE2
+#define XT_WSR_EXCSAVE2 _TIE_xt_core_WSR_EXCSAVE2
+#define XT_XSR_EXCSAVE2 _TIE_xt_core_XSR_EXCSAVE2
+#define XT_RSR_EPC3 _TIE_xt_core_RSR_EPC3
+#define XT_WSR_EPC3 _TIE_xt_core_WSR_EPC3
+#define XT_XSR_EPC3 _TIE_xt_core_XSR_EPC3
+#define XT_RSR_EXCSAVE3 _TIE_xt_core_RSR_EXCSAVE3
+#define XT_WSR_EXCSAVE3 _TIE_xt_core_WSR_EXCSAVE3
+#define XT_XSR_EXCSAVE3 _TIE_xt_core_XSR_EXCSAVE3
+#define XT_RSR_VECBASE _TIE_xt_core_RSR_VECBASE
+#define XT_WSR_VECBASE _TIE_xt_core_WSR_VECBASE
+#define XT_XSR_VECBASE _TIE_xt_core_XSR_VECBASE
+#define XT_RSR_EPS2 _TIE_xt_core_RSR_EPS2
+#define XT_WSR_EPS2 _TIE_xt_core_WSR_EPS2
+#define XT_XSR_EPS2 _TIE_xt_core_XSR_EPS2
+#define XT_RSR_EPS3 _TIE_xt_core_RSR_EPS3
+#define XT_WSR_EPS3 _TIE_xt_core_WSR_EPS3
+#define XT_XSR_EPS3 _TIE_xt_core_XSR_EPS3
+#define XT_RSR_EXCCAUSE _TIE_xt_core_RSR_EXCCAUSE
+#define XT_WSR_EXCCAUSE _TIE_xt_core_WSR_EXCCAUSE
+#define XT_XSR_EXCCAUSE _TIE_xt_core_XSR_EXCCAUSE
+#define XT_RSR_EXCVADDR _TIE_xt_core_RSR_EXCVADDR
+#define XT_WSR_EXCVADDR _TIE_xt_core_WSR_EXCVADDR
+#define XT_XSR_EXCVADDR _TIE_xt_core_XSR_EXCVADDR
+#define XT_RSR_DEPC _TIE_xt_core_RSR_DEPC
+#define XT_WSR_DEPC _TIE_xt_core_WSR_DEPC
+#define XT_XSR_DEPC _TIE_xt_core_XSR_DEPC
+#define XT_RSR_PRID _TIE_xt_core_RSR_PRID
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_core_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_debug.h

@@ -0,0 +1,93 @@
+/* Definitions for the xt_debug TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_debug_HEADER
+#define _XTENSA_xt_debug_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+#include <xtensa/tie/xt_core.h>
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern void _TIE_xt_debug_BREAK(immediate imms, immediate immt);
+extern void _TIE_xt_debug_BREAK_N(immediate imms);
+extern unsigned _TIE_xt_debug_RSR_DBREAKA0(void);
+extern void _TIE_xt_debug_WSR_DBREAKA0(unsigned art);
+extern void _TIE_xt_debug_XSR_DBREAKA0(unsigned art /*inout*/);
+extern unsigned _TIE_xt_debug_RSR_DBREAKC0(void);
+extern void _TIE_xt_debug_WSR_DBREAKC0(unsigned art);
+extern void _TIE_xt_debug_XSR_DBREAKC0(unsigned art /*inout*/);
+extern unsigned _TIE_xt_debug_RSR_IBREAKA0(void);
+extern void _TIE_xt_debug_WSR_IBREAKA0(unsigned art);
+extern void _TIE_xt_debug_XSR_IBREAKA0(unsigned art /*inout*/);
+extern unsigned _TIE_xt_debug_RSR_IBREAKENABLE(void);
+extern void _TIE_xt_debug_WSR_IBREAKENABLE(unsigned art);
+extern void _TIE_xt_debug_XSR_IBREAKENABLE(unsigned art /*inout*/);
+extern unsigned _TIE_xt_debug_RSR_DEBUGCAUSE(void);
+extern void _TIE_xt_debug_WSR_DEBUGCAUSE(unsigned art);
+extern void _TIE_xt_debug_XSR_DEBUGCAUSE(unsigned art /*inout*/);
+extern unsigned _TIE_xt_debug_RSR_ICOUNT(void);
+extern void _TIE_xt_debug_WSR_ICOUNT(unsigned art);
+extern void _TIE_xt_debug_XSR_ICOUNT(unsigned art /*inout*/);
+extern unsigned _TIE_xt_debug_RSR_ICOUNTLEVEL(void);
+extern void _TIE_xt_debug_WSR_ICOUNTLEVEL(unsigned art);
+extern void _TIE_xt_debug_XSR_ICOUNTLEVEL(unsigned art /*inout*/);
+extern unsigned _TIE_xt_debug_RSR_DDR(void);
+extern void _TIE_xt_debug_WSR_DDR(unsigned art);
+extern void _TIE_xt_debug_XSR_DDR(unsigned art /*inout*/);
+#define XT_BREAK _TIE_xt_debug_BREAK
+#define XT_BREAK_N _TIE_xt_debug_BREAK_N
+#define XT_RSR_DBREAKA0 _TIE_xt_debug_RSR_DBREAKA0
+#define XT_WSR_DBREAKA0 _TIE_xt_debug_WSR_DBREAKA0
+#define XT_XSR_DBREAKA0 _TIE_xt_debug_XSR_DBREAKA0
+#define XT_RSR_DBREAKC0 _TIE_xt_debug_RSR_DBREAKC0
+#define XT_WSR_DBREAKC0 _TIE_xt_debug_WSR_DBREAKC0
+#define XT_XSR_DBREAKC0 _TIE_xt_debug_XSR_DBREAKC0
+#define XT_RSR_IBREAKA0 _TIE_xt_debug_RSR_IBREAKA0
+#define XT_WSR_IBREAKA0 _TIE_xt_debug_WSR_IBREAKA0
+#define XT_XSR_IBREAKA0 _TIE_xt_debug_XSR_IBREAKA0
+#define XT_RSR_IBREAKENABLE _TIE_xt_debug_RSR_IBREAKENABLE
+#define XT_WSR_IBREAKENABLE _TIE_xt_debug_WSR_IBREAKENABLE
+#define XT_XSR_IBREAKENABLE _TIE_xt_debug_XSR_IBREAKENABLE
+#define XT_RSR_DEBUGCAUSE _TIE_xt_debug_RSR_DEBUGCAUSE
+#define XT_WSR_DEBUGCAUSE _TIE_xt_debug_WSR_DEBUGCAUSE
+#define XT_XSR_DEBUGCAUSE _TIE_xt_debug_XSR_DEBUGCAUSE
+#define XT_RSR_ICOUNT _TIE_xt_debug_RSR_ICOUNT
+#define XT_WSR_ICOUNT _TIE_xt_debug_WSR_ICOUNT
+#define XT_XSR_ICOUNT _TIE_xt_debug_XSR_ICOUNT
+#define XT_RSR_ICOUNTLEVEL _TIE_xt_debug_RSR_ICOUNTLEVEL
+#define XT_WSR_ICOUNTLEVEL _TIE_xt_debug_WSR_ICOUNTLEVEL
+#define XT_XSR_ICOUNTLEVEL _TIE_xt_debug_XSR_ICOUNTLEVEL
+#define XT_RSR_DDR _TIE_xt_debug_RSR_DDR
+#define XT_WSR_DDR _TIE_xt_debug_WSR_DDR
+#define XT_XSR_DDR _TIE_xt_debug_XSR_DDR
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_debug_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_density.h

@@ -0,0 +1,57 @@
+/* Definitions for the xt_density TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_density_HEADER
+#define _XTENSA_xt_density_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+#include <xtensa/tie/xt_core.h>
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern void _TIE_xt_density_ILL_N(void);
+extern void _TIE_xt_density_NOP_N(void);
+extern int _TIE_xt_density_L32I_N(const int * p, immediate i);
+extern void _TIE_xt_density_S32I_N(int t, int * p, immediate i);
+extern int _TIE_xt_density_ADD_N(int s, int t);
+extern int _TIE_xt_density_ADDI_N(int s, immediate i);
+extern int _TIE_xt_density_MOV_N(int s);
+extern int _TIE_xt_density_MOVI_N(immediate i);
+#define XT_ILL_N _TIE_xt_density_ILL_N
+#define XT_NOP_N _TIE_xt_density_NOP_N
+#define XT_L32I_N _TIE_xt_density_L32I_N
+#define XT_S32I_N _TIE_xt_density_S32I_N
+#define XT_ADD_N _TIE_xt_density_ADD_N
+#define XT_ADDI_N _TIE_xt_density_ADDI_N
+#define XT_MOV_N _TIE_xt_density_MOV_N
+#define XT_MOVI_N _TIE_xt_density_MOVI_N
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_density_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_exceptions.h

@@ -0,0 +1,46 @@
+/* Definitions for the xt_exceptions TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_exceptions_HEADER
+#define _XTENSA_xt_exceptions_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern void _TIE_xt_exceptions_EXCW(void);
+extern void _TIE_xt_exceptions_SYSCALL(void);
+extern void _TIE_xt_exceptions_SIMCALL(void);
+#define XT_EXCW _TIE_xt_exceptions_EXCW
+#define XT_SYSCALL _TIE_xt_exceptions_SYSCALL
+#define XT_SIMCALL _TIE_xt_exceptions_SIMCALL
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_exceptions_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_externalregisters.h

@@ -0,0 +1,44 @@
+/* Definitions for the xt_externalregisters TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_externalregisters_HEADER
+#define _XTENSA_xt_externalregisters_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern void _TIE_xt_externalregisters_RER(void);
+extern void _TIE_xt_externalregisters_WER(void);
+#define XT_RER _TIE_xt_externalregisters_RER
+#define XT_WER _TIE_xt_externalregisters_WER
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_externalregisters_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_interrupt.h

@@ -0,0 +1,55 @@
+/* Definitions for the xt_interrupt TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_interrupt_HEADER
+#define _XTENSA_xt_interrupt_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+#include <xtensa/tie/xt_core.h>
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern void _TIE_xt_interrupt_WAITI(immediate s);
+extern unsigned _TIE_xt_interrupt_RSR_INTERRUPT(void);
+extern void _TIE_xt_interrupt_WSR_INTSET(unsigned art);
+extern void _TIE_xt_interrupt_WSR_INTCLEAR(unsigned art);
+extern unsigned _TIE_xt_interrupt_RSR_INTENABLE(void);
+extern void _TIE_xt_interrupt_WSR_INTENABLE(unsigned art);
+extern void _TIE_xt_interrupt_XSR_INTENABLE(unsigned art /*inout*/);
+#define XT_WAITI _TIE_xt_interrupt_WAITI
+#define XT_RSR_INTERRUPT _TIE_xt_interrupt_RSR_INTERRUPT
+#define XT_WSR_INTSET _TIE_xt_interrupt_WSR_INTSET
+#define XT_WSR_INTCLEAR _TIE_xt_interrupt_WSR_INTCLEAR
+#define XT_RSR_INTENABLE _TIE_xt_interrupt_RSR_INTENABLE
+#define XT_WSR_INTENABLE _TIE_xt_interrupt_WSR_INTENABLE
+#define XT_XSR_INTENABLE _TIE_xt_interrupt_XSR_INTENABLE
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_interrupt_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_misc.h

@@ -0,0 +1,45 @@
+/* Definitions for the xt_misc TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_misc_HEADER
+#define _XTENSA_xt_misc_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+#include <xtensa/tie/xt_core.h>
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern int _TIE_xt_misc_NSA(int s);
+extern unsigned _TIE_xt_misc_NSAU(unsigned s);
+#define XT_NSA _TIE_xt_misc_NSA
+#define XT_NSAU _TIE_xt_misc_NSAU
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_misc_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_mmu.h

@@ -0,0 +1,61 @@
+/* Definitions for the xt_mmu TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_mmu_HEADER
+#define _XTENSA_xt_mmu_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+#include <xtensa/tie/xt_core.h>
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern void _TIE_xt_mmu_IDTLB(unsigned ars);
+extern unsigned _TIE_xt_mmu_RDTLB1(unsigned ars);
+extern unsigned _TIE_xt_mmu_RDTLB0(unsigned ars);
+extern unsigned _TIE_xt_mmu_PDTLB(unsigned ars);
+extern void _TIE_xt_mmu_WDTLB(unsigned art, unsigned ars);
+extern void _TIE_xt_mmu_IITLB(unsigned ars);
+extern unsigned _TIE_xt_mmu_RITLB1(unsigned ars);
+extern unsigned _TIE_xt_mmu_RITLB0(unsigned ars);
+extern unsigned _TIE_xt_mmu_PITLB(unsigned ars);
+extern void _TIE_xt_mmu_WITLB(unsigned art, unsigned ars);
+#define XT_IDTLB _TIE_xt_mmu_IDTLB
+#define XT_RDTLB1 _TIE_xt_mmu_RDTLB1
+#define XT_RDTLB0 _TIE_xt_mmu_RDTLB0
+#define XT_PDTLB _TIE_xt_mmu_PDTLB
+#define XT_WDTLB _TIE_xt_mmu_WDTLB
+#define XT_IITLB _TIE_xt_mmu_IITLB
+#define XT_RITLB1 _TIE_xt_mmu_RITLB1
+#define XT_RITLB0 _TIE_xt_mmu_RITLB0
+#define XT_PITLB _TIE_xt_mmu_PITLB
+#define XT_WITLB _TIE_xt_mmu_WITLB
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_mmu_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_mul.h

@@ -0,0 +1,47 @@
+/* Definitions for the xt_mul TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_mul_HEADER
+#define _XTENSA_xt_mul_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+#include <xtensa/tie/xt_core.h>
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern int _TIE_xt_mul_MUL16S(short s, short t);
+extern unsigned _TIE_xt_mul_MUL16U(unsigned short s, unsigned short t);
+extern int _TIE_xt_mul_MULL(int s, int t);
+#define XT_MUL16S _TIE_xt_mul_MUL16S
+#define XT_MUL16U _TIE_xt_mul_MUL16U
+#define XT_MULL _TIE_xt_mul_MULL
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_mul_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_timer.h

@@ -0,0 +1,53 @@
+/* Definitions for the xt_timer TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_timer_HEADER
+#define _XTENSA_xt_timer_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+#include <xtensa/tie/xt_core.h>
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern unsigned _TIE_xt_timer_RSR_CCOUNT(void);
+extern void _TIE_xt_timer_WSR_CCOUNT(unsigned art);
+extern void _TIE_xt_timer_XSR_CCOUNT(unsigned art /*inout*/);
+extern unsigned _TIE_xt_timer_RSR_CCOMPARE0(void);
+extern void _TIE_xt_timer_WSR_CCOMPARE0(unsigned art);
+extern void _TIE_xt_timer_XSR_CCOMPARE0(unsigned art /*inout*/);
+#define XT_RSR_CCOUNT _TIE_xt_timer_RSR_CCOUNT
+#define XT_WSR_CCOUNT _TIE_xt_timer_WSR_CCOUNT
+#define XT_XSR_CCOUNT _TIE_xt_timer_XSR_CCOUNT
+#define XT_RSR_CCOMPARE0 _TIE_xt_timer_RSR_CCOMPARE0
+#define XT_WSR_CCOMPARE0 _TIE_xt_timer_WSR_CCOMPARE0
+#define XT_XSR_CCOMPARE0 _TIE_xt_timer_XSR_CCOMPARE0
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_timer_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/tie/xt_trace.h

@@ -0,0 +1,43 @@
+/* Definitions for the xt_trace TIE package */
+
+/*
+ * Customer ID=7011; Build=0x2b6f6; Copyright (c) 2004 by Tensilica Inc.  ALL RIGHTS RESERVED.
+ * These coded instructions, statements, and computer programs are the
+ * copyrighted works and confidential proprietary information of Tensilica Inc.
+ * They may not be modified, copied, reproduced, distributed, or disclosed to
+ * third parties in any manner, medium, or form, in whole or in part, without
+ * the prior written consent of Tensilica Inc.
+ */
+
+/* Do not modify. This is automatically generated.*/
+
+#ifndef _XTENSA_xt_trace_HEADER
+#define _XTENSA_xt_trace_HEADER
+
+#ifdef __XTENSA__
+#ifdef __XCC__
+
+#include <xtensa/tie/xt_core.h>
+
+/*
+ * The following prototypes describe intrinsic functions
+ * corresponding to TIE instructions.  Some TIE instructions
+ * may produce multiple results (designated as "out" operands
+ * in the iclass section) or may have operands used as both
+ * inputs and outputs (designated as "inout").  However, the C
+ * and C++ languages do not provide syntax that can express
+ * the in/out/inout constraints of TIE intrinsics.
+ * Nevertheless, the compiler understands these constraints
+ * and will check that the intrinsic functions are used
+ * correctly.  To improve the readability of these prototypes,
+ * the "out" and "inout" parameters are marked accordingly
+ * with comments.
+ */
+
+extern void _TIE_xt_trace_WSR_MMID(unsigned art);
+#define XT_WSR_MMID _TIE_xt_trace_WSR_MMID
+
+#endif /* __XCC__ */
+
+#endif /* __XTENSA__ */
+#endif /* !_XTENSA_xt_trace_HEADER */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/xtensa-libdb-macros.h

@@ -0,0 +1,165 @@
+/*
+ *  xtensa-libdb-macros.h
+ */
+
+/* $Id: //depot/rel/Boreal/Xtensa/Software/libdb/xtensa-libdb-macros.h#2 $ */
+
+/* Copyright (c) 2004-2008 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
+#ifndef __H_LIBDB_MACROS
+#define __H_LIBDB_MACROS
+
+/*
+ *  This header file provides macros used to construct, identify and use
+ *  "target numbers" that are assigned to various types of Xtensa processor
+ *  registers and states.  These target numbers are used by GDB in the remote
+ *  protocol, and are thus used by all GDB debugger agents (targets).
+ *  They are also used in ELF debugger information sections (stabs, dwarf, etc).
+ *
+ *  These macros are separated from xtensa-libdb.h because they are needed
+ *  by certain debugger agents that do not use or have access to libdb,
+ *  e.g. the OCD daemon, RedBoot, XMON, etc.
+ *
+ *  For the time being, for compatibility with certain 3rd party debugger
+ *  software vendors, target numbers are limited to 16 bits.  It is
+ *  conceivable that this will be extended in the future to 32 bits.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef uint32
+ #define uint32	unsigned int
+#endif
+#ifndef int32
+ #define int32	int
+#endif
+
+
+/*
+ *  Macros to form register "target numbers" for various standard registers/states:
+ */
+#define XTENSA_DBREGN_INVALID		-1		/* not a valid target number */
+#define XTENSA_DBREGN_A(n)		(0x0000+(n))	/* address registers a0..a15 */
+#define XTENSA_DBREGN_B(n)		(0x0010+(n))	/* boolean bits b0..b15 */
+#define XTENSA_DBREGN_PC		 0x0020		/* program counter */
+				      /* 0x0021		   RESERVED for use by Tensilica */
+#define XTENSA_DBREGN_BO(n)		(0x0022+(n))	/* boolean octuple-bits bo0..bo1 */
+#define XTENSA_DBREGN_BQ(n)		(0x0024+(n))	/* boolean quadruple-bits bq0..bq3 */
+#define XTENSA_DBREGN_BD(n)		(0x0028+(n))	/* boolean double-bits bd0..bd7 */
+#define XTENSA_DBREGN_F(n)		(0x0030+(n))	/* floating point registers f0..f15 */
+#define XTENSA_DBREGN_VEC(n)		(0x0040+(n))	/* Vectra vec regs v0..v15 */
+#define XTENSA_DBREGN_VSEL(n)		(0x0050+(n))	/* Vectra sel s0..s3 (V1) ..s7 (V2) */
+#define XTENSA_DBREGN_VALIGN(n)		(0x0058+(n))	/* Vectra valign regs u0..u3 */
+#define XTENSA_DBREGN_VCOEFF(n)		(0x005C+(n))	/* Vectra I vcoeff regs c0..c1 */
+				      /* 0x005E..0x005F	   RESERVED for use by Tensilica */
+#define XTENSA_DBREGN_AEP(n)		(0x0060+(n))	/* HiFi2 Audio Engine regs aep0..aep7 */
+#define XTENSA_DBREGN_AEQ(n)		(0x0068+(n))	/* HiFi2 Audio Engine regs aeq0..aeq3 */
+				      /* 0x006C..0x006F	   RESERVED for use by Tensilica */
+#define XTENSA_DBREGN_DF(n)		(0x0070+(n))	/* double floating point registers df0..df15 */
+				      /* 0x0080..0x00FF	   RESERVED for use by Tensilica */
+#define XTENSA_DBREGN_AR(n)		(0x0100+(n))	/* physical address regs ar0..ar63
+							   (note: only with window option) */
+				      /* 0x0140..0x01FF	   RESERVED for use by Tensilica */
+#define XTENSA_DBREGN_SREG(n)		(0x0200+(n))	/* special registers 0..255 (core) */
+#define XTENSA_DBREGN_BR		XTENSA_DBREGN_SREG(0x04)	/* all 16 boolean bits, BR */
+#define XTENSA_DBREGN_MR(n)		XTENSA_DBREGN_SREG(0x20+(n))	/* MAC16 registers m0..m3 */
+#define XTENSA_DBREGN_UREG(n)		(0x0300+(n))	/* user registers 0..255 (TIE) */
+				      /* 0x0400..0x0FFF	   RESERVED for use by Tensilica */
+				      /* 0x1000..0x1FFF	   user-defined regfiles */
+				      /* 0x2000..0xEFFF	   other states (and regfiles) */
+#define XTENSA_DBREGN_DBAGENT(n)	(0xF000+(n))	/* non-processor "registers" 0..4095 for
+							   3rd-party debugger agent defined use */
+				      /* > 0xFFFF (32-bit) RESERVED for use by Tensilica */
+/*#define XTENSA_DBREGN_CONTEXT(n)	(0x02000000+((n)<<20))*/	/* add this macro's value to a target
+							   number to identify a specific context 0..31
+							   for context-replicated registers */
+#define XTENSA_DBREGN_MASK		0xFFFF		/* mask of valid target_number bits */
+#define XTENSA_DBREGN_WRITE_SIDE	0x04000000	/* flag to request write half of a register
+							   split into distinct read and write entries
+							   with the same target number (currently only
+							   valid in a couple of libdb API functions;
+							   see xtensa-libdb.h for details) */
+
+/*
+ *  Macros to identify specific ranges of target numbers (formed above):
+ *  NOTE:  any context number (or other upper 12 bits) are considered
+ *  modifiers and are thus stripped out for identification purposes.
+ */
+#define XTENSA_DBREGN_IS_VALID(tn)	(((tn) & ~0xFFFF) == 0)	/* just tests it's 16-bit unsigned */
+#define XTENSA_DBREGN_IS_A(tn)		(((tn) & 0xFFF0)==0x0000)	/* is a0..a15 */
+#define XTENSA_DBREGN_IS_B(tn)		(((tn) & 0xFFF0)==0x0010)	/* is b0..b15 */
+#define XTENSA_DBREGN_IS_PC(tn)		(((tn) & 0xFFFF)==0x0020)	/* is program counter */
+#define XTENSA_DBREGN_IS_BO(tn)		(((tn) & 0xFFFE)==0x0022)	/* is bo0..bo1 */
+#define XTENSA_DBREGN_IS_BQ(tn)		(((tn) & 0xFFFC)==0x0024)	/* is bq0..bq3 */
+#define XTENSA_DBREGN_IS_BD(tn)		(((tn) & 0xFFF8)==0x0028)	/* is bd0..bd7 */
+#define XTENSA_DBREGN_IS_F(tn)		(((tn) & 0xFFF0)==0x0030)	/* is f0..f15 */
+#define XTENSA_DBREGN_IS_VEC(tn)	(((tn) & 0xFFF0)==0x0040)	/* is v0..v15 */
+#define XTENSA_DBREGN_IS_VSEL(tn)	(((tn) & 0xFFF8)==0x0050)	/* is s0..s7 (s0..s3 in V1) */
+#define XTENSA_DBREGN_IS_VALIGN(tn)	(((tn) & 0xFFFC)==0x0058)	/* is u0..u3 */
+#define XTENSA_DBREGN_IS_VCOEFF(tn)	(((tn) & 0xFFFE)==0x005C)	/* is c0..c1 */
+#define XTENSA_DBREGN_IS_AEP(tn)	(((tn) & 0xFFF8)==0x0060)	/* is aep0..aep7 */
+#define XTENSA_DBREGN_IS_AEQ(tn)	(((tn) & 0xFFFC)==0x0068)	/* is aeq0..aeq3 */
+#define XTENSA_DBREGN_IS_DF(tn)		(((tn) & 0xFFF0)==0x0070)	/* is df0..df15 */
+#define XTENSA_DBREGN_IS_AR(tn)		(((tn) & 0xFFC0)==0x0100)	/* is ar0..ar63 */
+#define XTENSA_DBREGN_IS_SREG(tn)	(((tn) & 0xFF00)==0x0200)	/* is special register */
+#define XTENSA_DBREGN_IS_BR(tn)		(((tn) & 0xFFFF)==XTENSA_DBREGN_SREG(0x04))	/* is BR */
+#define XTENSA_DBREGN_IS_MR(tn)		(((tn) & 0xFFFC)==XTENSA_DBREGN_SREG(0x20))	/* m0..m3 */
+#define XTENSA_DBREGN_IS_UREG(tn)	(((tn) & 0xFF00)==0x0300)	/* is user register */
+#define XTENSA_DBREGN_IS_DBAGENT(tn)	(((tn) & 0xF000)==0xF000)	/* is non-processor */
+/*#define XTENSA_DBREGN_IS_CONTEXT(tn)	(((tn) & 0x02000000) != 0)*/	/* specifies context # */
+
+/*
+ *  Macros to extract register index from a register "target number"
+ *  when a specific range has been identified using one of the _IS_ macros above.
+ *  These macros only return a useful value if the corresponding _IS_ macro returns true.
+ */
+#define XTENSA_DBREGN_A_INDEX(tn)	((tn) & 0x0F)		/* 0..15  for a0..a15 */
+#define XTENSA_DBREGN_B_INDEX(tn)	((tn) & 0x0F)		/* 0..15  for b0..b15 */
+#define XTENSA_DBREGN_BO_INDEX(tn)	((tn) & 0x01)		/* 0..1   for bo0..bo1 */
+#define XTENSA_DBREGN_BQ_INDEX(tn)	((tn) & 0x03)		/* 0..3   for bq0..bq3 */
+#define XTENSA_DBREGN_BD_INDEX(tn)	((tn) & 0x07)		/* 0..7   for bd0..bd7 */
+#define XTENSA_DBREGN_F_INDEX(tn)	((tn) & 0x0F)		/* 0..15  for f0..f15 */
+#define XTENSA_DBREGN_VEC_INDEX(tn)	((tn) & 0x0F)		/* 0..15  for v0..v15 */
+#define XTENSA_DBREGN_VSEL_INDEX(tn)	((tn) & 0x07)		/* 0..7   for s0..s7 */
+#define XTENSA_DBREGN_VALIGN_INDEX(tn)	((tn) & 0x03)		/* 0..3   for u0..u3 */
+#define XTENSA_DBREGN_VCOEFF_INDEX(tn)	((tn) & 0x01)		/* 0..1   for c0..c1 */
+#define XTENSA_DBREGN_AEP_INDEX(tn)	((tn) & 0x07)		/* 0..7   for aep0..aep7 */
+#define XTENSA_DBREGN_AEQ_INDEX(tn)	((tn) & 0x03)		/* 0..3   for aeq0..aeq3 */
+#define XTENSA_DBREGN_DF_INDEX(tn)	((tn) & 0x0F)		/* 0..15  for df0..df15 */
+#define XTENSA_DBREGN_AR_INDEX(tn)	((tn) & 0x3F)		/* 0..63  for ar0..ar63 */
+#define XTENSA_DBREGN_SREG_INDEX(tn)	((tn) & 0xFF)		/* 0..255 for special registers */
+#define XTENSA_DBREGN_MR_INDEX(tn)	((tn) & 0x03)		/* 0..3   for m0..m3 */
+#define XTENSA_DBREGN_UREG_INDEX(tn)	((tn) & 0xFF)		/* 0..255 for user registers */
+#define XTENSA_DBREGN_DBAGENT_INDEX(tn)	((tn) & 0xFFF)		/* 0..4095 for non-processor */
+/*#define XTENSA_DBREGN_CONTEXT_INDEX(tn)	(((tn) >> 20) & 0x1F)*/	/* 0..31  context numbers */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+      
+#endif /* __H_LIBDB_MACROS */
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/xtensa-xer.h

@@ -0,0 +1,149 @@
+/* xer-constants.h -- various constants describing external registers accessed 
+      via wer and rer.
+
+      TODO: find a better prefix. Also conditionalize certain constants based
+      on number of cores and interrupts actually present.  
+*/
+
+/*
+ * Copyright (c) 1999-2008 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <xtensa/config/core.h>
+
+#define NUM_INTERRUPTS 27
+#define NUM_CORES       4
+
+/* Routing of NMI (BInterrupt2)	and interrupts 0..n-1 (BInterrupt3+) 
+   RER reads
+   WER writes
+ */
+
+#define XER_MIROUT           0x0000
+#define XER_MIROUT_LAST      (XER_MIROUT + NUM_INTERRUPTS)
+
+
+/* IPI to core M (all 16 causes). 
+   
+   RER reads
+   WER clears
+ */
+#define XER_MIPICAUSE        0x0100
+#define XER_MIPICAUSE_FIELD_A_FIRST 0x0
+#define XER_MIPICAUSE_FIELD_A_LAST  0x0
+#define XER_MIPICAUSE_FIELD_B_FIRST 0x1
+#define XER_MIPICAUSE_FIELD_B_LAST  0x3
+#define XER_MIPICAUSE_FIELD_C_FIRST 0x4
+#define XER_MIPICAUSE_FIELD_C_LAST  0x7
+#define XER_MIPICAUSE_FIELD_D_FIRST 0x8
+#define XER_MIPICAUSE_FIELD_D_LAST  0xF
+
+
+/* IPI from cause bit 0..15  
+
+   RER invalid
+   WER sets
+*/
+#define XER_MIPISET          0x0140
+#define XER_MIPISET_LAST     0x014F
+
+
+/* Global enable
+
+   RER read
+   WER clear
+*/
+#define XER_MIENG            0x0180
+
+
+/* Global enable
+
+   RER invalid
+   WER set
+*/
+#define XER_MIENG_SET        0x0184
+
+/* Global assert
+
+   RER read
+   WER clear
+*/
+#define XER_MIASG            0x0188
+
+
+/* Global enable
+
+   RER invalid
+   WER set
+*/
+#define XER_MIASG_SET        0x018C
+
+
+/* IPI partition register
+
+   RER read
+   WER write
+*/
+#define XER_PART            0x0190
+#define XER_IPI0            0x0
+#define XER_IPI1            0x1
+#define XER_IPI2            0x2
+#define XER_IPI3            0x3
+
+#define XER_PART_ROUTE_IPI(NUM, FIELD) ((NUM) << ((FIELD) << 2))
+
+#define XER_PART_ROUTE_IPI_CAUSE(TO_A, TO_B, TO_C, TO_D)		\
+  (XER_PART_ROUTE_IPI(TO_A, XER_IPI0) |					\
+   XER_PART_ROUTE_IPI(TO_B, XER_IPI1) |					\
+   XER_PART_ROUTE_IPI(TO_C, XER_IPI2) |					\
+   XER_PART_ROUTE_IPI(TO_D, XER_IPI3))
+
+#define XER_IPI_WAKE_EXT_INTERRUPT XCHAL_EXTINT0_NUM
+#define XER_IPI_WAKE_CAUSE  XER_MIPICAUSE_FIELD_C_FIRST
+#define XER_IPI_WAKE_ADDRESS    (XER_MIPISET + XER_IPI_WAKE_CAUSE)
+#define XER_DEFAULT_IPI_ROUTING XER_PART_ROUTE_IPI_CAUSE(XER_IPI1, XER_IPI0, XER_IPI2, XER_IPI3)
+
+
+/* System configuration ID
+
+   RER read
+   WER invalid
+*/
+#define XER_SYSCFGID        0x01A0
+
+
+/* RunStall to slave processors
+
+   RER read
+   WER write
+*/
+#define XER_MPSCORE        0x0200
+
+
+/* Cache coherency ON
+
+   RER read
+   WER write
+*/
+#define XER_CCON           0x0220
+
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/xtruntime-frames.h

@@ -0,0 +1,160 @@
+/*  xtruntime-frames.h  -  exception stack frames for single-threaded run-time  */
+/* $Id: //depot/rel/Boreal/Xtensa/OS/include/xtensa/xtruntime-frames.h#2 $ */
+
+/*
+ * Copyright (c) 2002-2007 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _XTRUNTIME_FRAMES_H_
+#define _XTRUNTIME_FRAMES_H_
+
+#include <xtensa/config/core.h>
+
+/*  Macros that help define structures for both C and assembler:  */
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+#define STRUCT_BEGIN		.pushsection .text; .struct 0
+#define STRUCT_FIELD(ctype,size,pre,name)	pre##name:	.space	size
+#define STRUCT_AFIELD(ctype,size,pre,name,n)	pre##name:	.space	(size)*(n)
+#define STRUCT_END(sname)	sname##Size:; .popsection
+#else /*_ASMLANGUAGE||__ASSEMBLER__*/
+#define STRUCT_BEGIN		typedef struct {
+#define STRUCT_FIELD(ctype,size,pre,name)	ctype	name;
+#define STRUCT_AFIELD(ctype,size,pre,name,n)	ctype	name[n];
+#define STRUCT_END(sname)	} sname;
+#endif /*_ASMLANGUAGE||__ASSEMBLER__*/
+
+
+/*
+ *  Kernel vector mode exception stack frame.
+ *
+ *  NOTE:  due to the limited range of addi used in the current
+ *  kernel exception vector, and the fact that historically
+ *  the vector is limited to 12 bytes, the size of this
+ *  stack frame is limited to 128 bytes (currently at 64).
+ */
+STRUCT_BEGIN
+STRUCT_FIELD (long,4,KEXC_,pc)		/* "parm" */
+STRUCT_FIELD (long,4,KEXC_,ps)
+STRUCT_AFIELD(long,4,KEXC_,areg, 4)	/* a12 .. a15 */
+STRUCT_FIELD (long,4,KEXC_,sar)		/* "save" */
+#if XCHAL_HAVE_LOOPS
+STRUCT_FIELD (long,4,KEXC_,lcount)
+STRUCT_FIELD (long,4,KEXC_,lbeg)
+STRUCT_FIELD (long,4,KEXC_,lend)
+#endif
+#if XCHAL_HAVE_MAC16
+STRUCT_FIELD (long,4,KEXC_,acclo)
+STRUCT_FIELD (long,4,KEXC_,acchi)
+STRUCT_AFIELD(long,4,KEXC_,mr, 4)
+#endif
+STRUCT_END(KernelFrame)
+
+
+/*
+ *  User vector mode exception stack frame:
+ *
+ *  WARNING:  if you modify this structure, you MUST modify the
+ *  computation of the pad size (ALIGNPAD) accordingly.
+ */
+STRUCT_BEGIN
+STRUCT_FIELD (long,4,UEXC_,pc)
+STRUCT_FIELD (long,4,UEXC_,ps)
+STRUCT_FIELD (long,4,UEXC_,sar)
+STRUCT_FIELD (long,4,UEXC_,vpri)
+#ifdef __XTENSA_CALL0_ABI__
+STRUCT_FIELD (long,4,UEXC_,a0)
+#endif
+STRUCT_FIELD (long,4,UEXC_,a2)
+STRUCT_FIELD (long,4,UEXC_,a3)
+STRUCT_FIELD (long,4,UEXC_,a4)
+STRUCT_FIELD (long,4,UEXC_,a5)
+#ifdef __XTENSA_CALL0_ABI__
+STRUCT_FIELD (long,4,UEXC_,a6)
+STRUCT_FIELD (long,4,UEXC_,a7)
+STRUCT_FIELD (long,4,UEXC_,a8)
+STRUCT_FIELD (long,4,UEXC_,a9)
+STRUCT_FIELD (long,4,UEXC_,a10)
+STRUCT_FIELD (long,4,UEXC_,a11)
+STRUCT_FIELD (long,4,UEXC_,a12)
+STRUCT_FIELD (long,4,UEXC_,a13)
+STRUCT_FIELD (long,4,UEXC_,a14)
+STRUCT_FIELD (long,4,UEXC_,a15)
+#endif
+STRUCT_FIELD (long,4,UEXC_,exccause)	/* NOTE: can probably rid of this one (pass direct) */
+#if XCHAL_HAVE_LOOPS
+STRUCT_FIELD (long,4,UEXC_,lcount)
+STRUCT_FIELD (long,4,UEXC_,lbeg)
+STRUCT_FIELD (long,4,UEXC_,lend)
+#endif
+#if XCHAL_HAVE_MAC16
+STRUCT_FIELD (long,4,UEXC_,acclo)
+STRUCT_FIELD (long,4,UEXC_,acchi)
+STRUCT_AFIELD(long,4,UEXC_,mr, 4)
+#endif
+/* ALIGNPAD is the 16-byte alignment padding. */
+#ifdef __XTENSA_CALL0_ABI__
+# define CALL0_ABI	1
+#else
+# define CALL0_ABI	0
+#endif
+#define ALIGNPAD  ((3 + XCHAL_HAVE_LOOPS*1 + XCHAL_HAVE_MAC16*2 + CALL0_ABI*1) & 3)
+#if ALIGNPAD
+STRUCT_AFIELD(long,4,UEXC_,pad, ALIGNPAD)	/* 16-byte alignment padding */
+#endif
+/*STRUCT_AFIELD(char,1,UEXC_,ureg, (XCHAL_CPEXTRA_SA_SIZE_TOR2+3)&-4)*/	/* not used, and doesn't take alignment into account */
+STRUCT_END(UserFrame)
+
+
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+
+
+/*  Check for UserFrameSize small enough not to require rounding...:  */
+	/*  Skip 16-byte save area, then 32-byte space for 8 regs of call12
+	 *  (which overlaps with 16-byte GCC nested func chaining area),
+	 *  then exception stack frame:  */
+	.set	UserFrameTotalSize, 16+32+UserFrameSize
+	/*  Greater than 112 bytes? (max range of ADDI, both signs, when aligned to 16 bytes):  */
+	.ifgt	UserFrameTotalSize-112
+	/*  Round up to 256-byte multiple to accelerate immediate adds:  */
+	.set	UserFrameTotalSize, ((UserFrameTotalSize+255) & 0xFFFFFF00)
+	.endif
+# define ESF_TOTALSIZE	UserFrameTotalSize
+
+#endif /* _ASMLANGUAGE || __ASSEMBLER__ */
+
+
+#if XCHAL_NUM_CONTEXTS > 1
+/*  Structure of info stored on new context's stack for setup:  */
+STRUCT_BEGIN
+STRUCT_FIELD (long,4,INFO_,sp)
+STRUCT_FIELD (long,4,INFO_,arg1)
+STRUCT_FIELD (long,4,INFO_,funcpc)
+STRUCT_FIELD (long,4,INFO_,prevps)
+STRUCT_END(SetupInfo)
+#endif
+
+
+#define KERNELSTACKSIZE	1024
+
+
+#endif /* _XTRUNTIME_FRAMES_H_ */
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/extra_include/xtensa/xtruntime.h

@@ -0,0 +1,184 @@
+/*
+ * xtruntime.h  --  general C definitions for single-threaded run-time
+ *
+ * Copyright (c) 2002-2008 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef XTRUNTIME_H
+#define XTRUNTIME_H
+
+#include <xtensa/config/core.h>
+#include <xtensa/config/specreg.h>
+
+#ifndef XTSTR
+#define _XTSTR(x)	# x
+#define XTSTR(x)	_XTSTR(x)
+#endif
+
+#define _xtos_set_execption_handler _xtos_set_exception_handler	/* backward compatibility */
+#define _xtos_set_saved_intenable	_xtos_ints_on	/* backward compatibility */
+#define _xtos_clear_saved_intenable	_xtos_ints_off	/* backward compatibility */
+
+#if !defined(_ASMLANGUAGE) && !defined(__ASSEMBLER__)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*typedef void (_xtos_timerdelta_func)(int);*/
+#ifdef __cplusplus
+typedef void (_xtos_handler_func)(...);
+#else
+typedef void (_xtos_handler_func)();
+#endif
+typedef _xtos_handler_func *_xtos_handler;
+
+/*
+ *  unsigned XTOS_SET_INTLEVEL(int intlevel);
+ *  This macro sets the current interrupt level.
+ *  The 'intlevel' parameter must be a constant.
+ *  This macro returns a 32-bit value that must be passed to
+ *  XTOS_RESTORE_INTLEVEL() to restore the previous interrupt level.
+ *  XTOS_RESTORE_JUST_INTLEVEL() also does this, but in XEA2 configs
+ *  it restores only PS.INTLEVEL rather than the entire PS register
+ *  and thus is slower.
+ */
+#if !XCHAL_HAVE_INTERRUPTS
+# define XTOS_SET_INTLEVEL(intlevel)		0
+# define XTOS_SET_MIN_INTLEVEL(intlevel)	0
+# define XTOS_RESTORE_INTLEVEL(restoreval)
+# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)
+#elif XCHAL_HAVE_XEA2
+/*  In XEA2, we can simply safely set PS.INTLEVEL directly:  */
+/*  NOTE: these asm macros don't modify memory, but they are marked
+ *  as such to act as memory access barriers to the compiler because
+ *  these macros are sometimes used to delineate critical sections;
+ *  function calls are natural barriers (the compiler does not know
+ *  whether a function modifies memory) unless declared to be inlined.  */
+# define XTOS_SET_INTLEVEL(intlevel)		({ unsigned __tmp; \
+			__asm__ __volatile__(	"rsil	%0, " XTSTR(intlevel) "\n" \
+						: "=a" (__tmp) : : "memory" ); \
+			__tmp;})
+# define XTOS_SET_MIN_INTLEVEL(intlevel)		({ unsigned __tmp, __tmp2, __tmp3; \
+			__asm__ __volatile__(	"rsr	%0, " XTSTR(PS) "\n"	/* get old (current) PS.INTLEVEL */ \
+						"movi	%2, " XTSTR(intlevel) "\n" \
+						"extui	%1, %0, 0, 4\n"	/* keep only INTLEVEL bits of parameter */ \
+						"blt	%2, %1, 1f\n" \
+						"rsil	%0, " XTSTR(intlevel) "\n" \
+						"1:\n" \
+						: "=a" (__tmp), "=&a" (__tmp2), "=&a" (__tmp3) : : "memory" ); \
+			__tmp;})
+# define XTOS_RESTORE_INTLEVEL(restoreval)	do{ unsigned __tmp = (restoreval); \
+			__asm__ __volatile__(	"wsr	%0, " XTSTR(PS) " ; rsync\n" \
+						: : "a" (__tmp) : "memory" ); \
+			}while(0)
+# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)	_xtos_set_intlevel(restoreval)
+#else
+/*  In XEA1, we have to rely on INTENABLE register virtualization:  */
+extern unsigned		_xtos_set_vpri( unsigned vpri );
+extern unsigned		_xtos_vpri_enabled;	/* current virtual priority */
+# define XTOS_SET_INTLEVEL(intlevel)		_xtos_set_vpri(~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
+# define XTOS_SET_MIN_INTLEVEL(intlevel)	_xtos_set_vpri(_xtos_vpri_enabled & ~XCHAL_INTLEVEL_ANDBELOW_MASK(intlevel))
+# define XTOS_RESTORE_INTLEVEL(restoreval)	_xtos_set_vpri(restoreval)
+# define XTOS_RESTORE_JUST_INTLEVEL(restoreval)	_xtos_set_vpri(restoreval)
+#endif
+
+/*
+ *  The following macros build upon the above.  They are generally used
+ *  instead of invoking the SET_INTLEVEL and SET_MIN_INTLEVEL macros directly.
+ *  They all return a value that can be used with XTOS_RESTORE_INTLEVEL()
+ *  or _xtos_restore_intlevel() or _xtos_restore_just_intlevel() to restore
+ *  the effective interrupt level to what it was before the macro was invoked.
+ *  In XEA2, the DISABLE macros are much faster than the MASK macros
+ *  (in all configs, DISABLE sets the effective interrupt level, whereas MASK
+ *  makes ensures the effective interrupt level is at least the level given
+ *  without lowering it; in XEA2 with INTENABLE virtualization, these macros
+ *  affect PS.INTLEVEL only, not the virtual priority, so DISABLE has partial
+ *  MASK semantics).
+ *
+ *  A typical critical section sequence might be:
+ *	unsigned rval = XTOS_DISABLE_EXCM_INTERRUPTS;
+ *	... critical section ...
+ *	XTOS_RESTORE_INTLEVEL(rval);
+ */
+/*  Enable all interrupts (those activated with _xtos_ints_on()):  */
+#define XTOS_ENABLE_INTERRUPTS		XTOS_SET_INTLEVEL(0)
+/*  Disable low priority level interrupts (they can interact with the OS):  */
+#define XTOS_DISABLE_LOWPRI_INTERRUPTS	XTOS_SET_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
+#define XTOS_MASK_LOWPRI_INTERRUPTS	XTOS_SET_MIN_INTLEVEL(XCHAL_NUM_LOWPRI_LEVELS)
+/*  Disable interrupts that can interact with the OS:  */
+#define XTOS_DISABLE_EXCM_INTERRUPTS	XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL)
+#define XTOS_MASK_EXCM_INTERRUPTS	XTOS_SET_MIN_INTLEVEL(XCHAL_EXCM_LEVEL)
+#if 0 /* XTOS_LOCK_LEVEL is not exported to applications */
+/*  Disable interrupts that can interact with the OS, or manipulate virtual INTENABLE:  */
+#define XTOS_DISABLE_LOCK_INTERRUPTS	XTOS_SET_INTLEVEL(XTOS_LOCK_LEVEL)
+#define XTOS_MASK_LOCK_INTERRUPTS	XTOS_SET_MIN_INTLEVEL(XTOS_LOCK_LEVEL)
+#endif
+/*  Disable ALL interrupts (not for common use, particularly if one's processor
+ *  configuration has high-level interrupts and one cares about their latency):  */
+#define XTOS_DISABLE_ALL_INTERRUPTS	XTOS_SET_INTLEVEL(15)
+
+
+extern unsigned int	_xtos_ints_off( unsigned int mask );
+extern unsigned int	_xtos_ints_on( unsigned int mask );
+extern unsigned		_xtos_set_intlevel( int intlevel );
+extern unsigned		_xtos_set_min_intlevel( int intlevel );
+extern unsigned		_xtos_restore_intlevel( unsigned restoreval );
+extern unsigned		_xtos_restore_just_intlevel( unsigned restoreval );
+extern _xtos_handler	_xtos_set_interrupt_handler( int n, _xtos_handler f );
+extern _xtos_handler	_xtos_set_interrupt_handler_arg( int n, _xtos_handler f, void *arg );
+extern _xtos_handler	_xtos_set_exception_handler( int n, _xtos_handler f );
+
+extern void		_xtos_memep_initrams( void );
+extern void		_xtos_memep_enable( int flags );
+
+/*  Deprecated (but kept because they were documented):  */
+extern unsigned int	_xtos_read_ints( void );		/* use xthal_get_interrupt() instead */
+extern void		_xtos_clear_ints( unsigned int mask );	/* use xthal_set_intclear() instead */
+
+#if XCHAL_NUM_CONTEXTS > 1
+extern unsigned		_xtos_init_context(int context_num, int stack_size,
+					    _xtos_handler_func *start_func, int arg1);
+#endif
+
+/*  Deprecated:  */
+#if XCHAL_NUM_TIMERS > 0
+extern void		_xtos_timer_0_delta( int cycles );
+#endif
+#if XCHAL_NUM_TIMERS > 1
+extern void		_xtos_timer_1_delta( int cycles );
+#endif
+#if XCHAL_NUM_TIMERS > 2
+extern void		_xtos_timer_2_delta( int cycles );
+#endif
+#if XCHAL_NUM_TIMERS > 3
+extern void		_xtos_timer_3_delta( int cycles );
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_ASMLANGUAGE && !__ASSEMBLER__ */
+
+#endif /* XTRUNTIME_H */
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espconn/espconn.h

@@ -0,0 +1,757 @@
+/*
+ * ESPRESSIF MIT License
+ *
+ * Copyright (c) 2017 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESPCONN_H__
+#define __ESPCONN_H__
+
+#include "lwip/dns.h"
+#include "arch/sys_arch.h"
+#include "esp_common.h"
+#include "espconn/espconn_buf.h"
+
+#if 0
+#define espconn_printf(fmt, args...) os_printf(fmt,## args)
+#else
+#define espconn_printf(fmt, args...)
+#endif
+
+#if !NO_SYS
+#define ESPCONN_API_MUTEX_TAKE()    taskENTER_CRITICAL() //vTaskSuspendAll()//taskENTER_CRITICAL()//API_MUTEX_TAKE()
+#define ESPCONN_API_MUTEX_GIVE()    taskEXIT_CRITICAL() //xTaskResumeAll()//taskEXIT_CRITICAL()//API_MUTEX_GIVE()
+#else
+#define ESPCONN_API_MUTEX_TAKE()
+#define ESPCONN_API_MUTEX_GIVE()
+#endif
+
+typedef void* espconn_handle;
+typedef void (* espconn_connect_callback)(void* arg);
+typedef void (* espconn_reconnect_callback)(void* arg, sint8 err);
+
+/* Definitions for error constants. */
+
+#define ESPCONN_OK          0    /* No error, everything OK. */
+#define ESPCONN_MEM        -1    /* Out of memory error.     */
+#define ESPCONN_TIMEOUT    -3    /* Timeout.                 */
+#define ESPCONN_RTE        -4    /* Routing problem.         */
+#define ESPCONN_INPROGRESS  -5   /* Operation in progress    */
+#define ESPCONN_MAXNUM		-7	 /* Total number exceeds the set maximum*/
+
+#define ESPCONN_ABRT       -8    /* Connection aborted.      */
+#define ESPCONN_RST        -9    /* Connection reset.        */
+#define ESPCONN_CLSD       -10   /* Connection closed.       */
+#define ESPCONN_CONN       -11   /* Not connected.           */
+
+#define ESPCONN_ARG        -12   /* Illegal argument.        */
+#define ESPCONN_IF		   -14	 /* Low_level error			 */
+#define ESPCONN_ISCONN     -15   /* Already connected.       */
+#define ESPCONN_TIME	   -16	 /* Sync Time error			 */
+#define ESPCONN_NODATA	   -17	 /* No data can be read	     */
+
+#define ESPCONN_HANDSHAKE  -28   /* ssl handshake failed	 */
+#define ESPCONN_RESP_TIMEOUT -29 /* ssl handshake no response*/
+#define ESPCONN_PROTO_MSG  -61   /* ssl application invalid	 */
+
+#define ESPCONN_SSL			0x01
+#define ESPCONN_NORM		0x00
+
+#define ESPCONN_STA			0x01
+#define ESPCONN_AP			0x02
+#define ESPCONN_AP_STA		0x03
+
+#define STA_NETIF      0x00
+#define AP_NETIF       0x01
+
+/** Protocol family and type of the espconn */
+enum espconn_type {
+    ESPCONN_INVALID    = 0,
+    /* ESPCONN_TCP Group */
+    ESPCONN_TCP        = 0x10,
+    /* ESPCONN_UDP Group */
+    ESPCONN_UDP        = 0x20,
+};
+
+/** Current state of the espconn. Non-TCP espconn are always in state ESPCONN_NONE! */
+enum espconn_state {
+    ESPCONN_NONE,
+    ESPCONN_WAIT,
+    ESPCONN_LISTEN,
+    ESPCONN_CONNECT,
+    ESPCONN_WRITE,
+    ESPCONN_READ,
+    ESPCONN_CLOSE
+};
+
+typedef struct _esp_tcp {
+    int remote_port;
+    int local_port;
+    uint8 local_ip[4];
+    uint8 remote_ip[4];
+    espconn_connect_callback connect_callback;
+    espconn_reconnect_callback reconnect_callback;
+    espconn_connect_callback disconnect_callback;
+    espconn_connect_callback write_finish_fn;
+} esp_tcp;
+
+typedef struct _esp_udp {
+    int remote_port;
+    int local_port;
+    uint8 local_ip[4];
+    uint8 remote_ip[4];
+} esp_udp;
+
+typedef struct _remot_info {
+    enum espconn_state state;
+    int remote_port;
+    uint8 remote_ip[4];
+} remot_info;
+
+/** A callback prototype to inform about events for a espconn */
+typedef void (* espconn_recv_callback)(void* arg, char* pdata, unsigned short len);
+typedef void (* espconn_sent_callback)(void* arg);
+
+/** A espconn descriptor */
+struct espconn {
+    /** type of the espconn (TCP, UDP) */
+    enum espconn_type type;
+    /** current state of the espconn */
+    enum espconn_state state;
+    union {
+        esp_tcp* tcp;
+        esp_udp* udp;
+    } proto;
+    /** A callback function that is informed about events for this espconn */
+    espconn_recv_callback recv_callback;
+    espconn_sent_callback sent_callback;
+    uint8 link_cnt;
+    void* reverse;
+};
+
+enum espconn_option {
+    ESPCONN_START = 0x00,
+    ESPCONN_REUSEADDR = 0x01,
+    ESPCONN_NODELAY = 0x02,
+    ESPCONN_COPY = 0x04,
+    ESPCONN_KEEPALIVE = 0x08,
+    ESPCONN_END
+};
+
+enum espconn_level {
+    ESPCONN_KEEPIDLE,
+    ESPCONN_KEEPINTVL,
+    ESPCONN_KEEPCNT
+};
+
+enum espconn_mode {
+    ESPCONN_NOMODE,
+    ESPCONN_TCPSERVER_MODE,
+    ESPCONN_TCPCLIENT_MODE,
+    ESPCONN_UDP_MODE,
+    ESPCONN_NUM_MODE
+};
+
+struct espconn_packet {
+    uint16 sent_length;		/* sent length successful*/
+    uint16 snd_buf_size;	/* Available buffer size for sending  */
+    uint16 snd_queuelen;	/* Available buffer space for sending */
+    uint16 total_queuelen;	/* total Available buffer space for sending */
+    uint32 packseqno;		/* seqno to be sent */
+    uint32 packseq_nxt;		/* seqno expected */
+    uint32 packnum;
+};
+
+typedef struct _espconn_buf {
+    uint8* payload;
+    uint8* punsent;
+    uint16 unsent;
+    uint16 len;
+    uint16 tot_len;
+    struct _espconn_buf* pnext;
+} espconn_buf;
+
+typedef struct _comon_pkt {
+    void* pcb;
+    int remote_port;
+    uint8 remote_ip[4];
+    uint32 local_port;
+    uint32 local_ip;
+    espconn_buf* pbuf;
+    espconn_buf* ptail;
+    uint8* ptrbuf;
+    uint16 cntr;
+    sint8  err;
+    uint32 timeout;
+    uint32 recv_check;
+    uint8  pbuf_num;
+    struct espconn_packet packet_info;
+    bool write_flag;
+    enum espconn_option espconn_opt;
+} comon_pkt;
+
+typedef struct _espconn_msg {
+    struct espconn* pespconn;
+    comon_pkt pcommon;
+    uint8 count_opt;
+    uint8 espconn_mode;
+    uint8 sig_type;
+    sint16 hs_status;	//the status of the handshake
+    void* preverse;
+    void* pssl;
+    struct _espconn_msg* pnext;
+
+//***********Code for WIFI_BLOCK from upper**************
+    uint8 recv_hold_flag;
+    uint16 recv_holded_buf_Len;
+//*******************************************************
+    ringbuf* readbuf;
+} espconn_msg;
+
+#ifndef _MDNS_INFO
+#define _MDNS_INFO
+struct mdns_info {
+    char* host_name;
+    char* server_name;
+    uint16 server_port;
+    unsigned long ipAddr;
+    char* txt_data[10];
+};
+#endif
+
+#define linkMax 15
+
+#define   espconn_delay_disabled(espconn)  (((espconn)->pcommon.espconn_opt & ESPCONN_NODELAY) != 0)
+#define   espconn_delay_enabled(espconn)  (((espconn)->pcommon.espconn_opt & ESPCONN_NODELAY) == 0)
+#define   espconn_reuse_disabled(espconn)  (((espconn)->pcommon.espconn_opt & ESPCONN_REUSEADDR) != 0)
+#define   espconn_copy_disabled(espconn)  (((espconn)->pcommon.espconn_opt & ESPCONN_COPY) != 0)
+#define   espconn_copy_enabled(espconn)  (((espconn)->pcommon.espconn_opt & ESPCONN_COPY) == 0)
+#define   espconn_keepalive_disabled(espconn)  (((espconn)->pcommon.espconn_opt & ESPCONN_KEEPALIVE) != 0)
+#define   espconn_keepalive_enabled(espconn)  (((espconn)->pcommon.espconn_opt & ESPCONN_KEEPALIVE) == 0)
+
+#define espconn_TaskPrio        26
+#define espconn_TaskQueueLen    15
+
+enum espconn_sig {
+    SIG_ESPCONN_NONE,
+    SIG_ESPCONN_ERRER,
+    SIG_ESPCONN_LISTEN,
+    SIG_ESPCONN_CONNECT,
+    SIG_ESPCONN_WRITE,
+    SIG_ESPCONN_SEND,
+    SIG_ESPCONN_READ,
+    SIG_ESPCONN_CLOSE
+};
+
+#if !NO_SYS
+/**
+ * ESPCONN_THREAD_NAME: The name assigned to the main espconn thread.
+ */
+#ifndef ESPCONN_THREAD_NAME
+#define ESPCONN_THREAD_NAME              "espconn_thread"
+#endif
+/**
+ * ESPCONN_THREAD_STACKSIZE: The stack size used by the main espconn thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#define ESPCONN_THREAD_STACKSIZE          512			//not ok:384
+/**
+ * ESPCONN_THREAD_PRIO: The priority assigned to the main espconn thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#define ESPCONN_THREAD_PRIO               (configMAX_PRIORITIES-7)
+//#define ESPCONN_THREAD_PRIO               (configMAX_PRIORITIES-1)
+/**
+ * ESPCONN_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#define ESPCONN_MBOX_SIZE                 16
+
+#define ESPCONN_MAX_DELAY 				  portMAX_DELAY
+/**
+ * ESPCONN_LOCKING:
+ */
+#ifndef ESPCONN_LOCKING
+#define ESPCONN_LOCKING         0
+#endif
+/** The global semaphore to lock the task. */
+#if ESPCONN_LOCKING
+extern sys_mutex_t lock_espconn_task;
+#define LOCK_ESPCONN_TASK()     sys_mutex_lock(&lock_espconn_task)
+#define UNLOCK_ESPCONN_TASK()   sys_mutex_unlock(&lock_espconn_task)
+#else
+#define LOCK_ESPCONN_TASK()
+#define UNLOCK_ESPCONN_TASK()
+#endif
+#else
+
+#endif
+/******************************************************************************
+ * FunctionName : espconn_copy_partial
+ * Description  : reconnect with host
+ * Parameters   : arg -- Additional argument to pass to the callback function
+ * Returns      : none
+*******************************************************************************/
+
+void espconn_copy_partial(struct espconn* pesp_dest, struct espconn* pesp_source);
+
+/******************************************************************************
+ * FunctionName : espconn_copy_partial
+ * Description  : insert the node to the active connection list
+ * Parameters   : arg -- Additional argument to pass to the callback function
+ * Returns      : none
+*******************************************************************************/
+
+void espconn_list_creat(espconn_msg** phead, espconn_msg* pinsert);
+
+/******************************************************************************
+ * FunctionName : espconn_list_delete
+ * Description  : remove the node from the active connection list
+ * Parameters   : arg -- Additional argument to pass to the callback function
+ * Returns      : none
+*******************************************************************************/
+
+void espconn_list_delete(espconn_msg** phead, espconn_msg* pdelete);
+
+/******************************************************************************
+ * FunctionName : espconn_find_connection
+ * Description  : Initialize the server: set up a listening PCB and bind it to
+ *                the defined port
+ * Parameters   : espconn -- the espconn used to build server
+ * Returns      : none
+ *******************************************************************************/
+
+bool espconn_find_connection(struct espconn* pespconn, espconn_msg** pnode);
+
+/******************************************************************************
+ * FunctionName : espconn_get_connection_info
+ * Description  : used to specify the function that should be called when disconnect
+ * Parameters   : espconn -- espconn to set the err callback
+ *                discon_cb -- err callback function to call when err
+ * Returns      : none
+*******************************************************************************/
+
+sint8 espconn_get_connection_info(struct espconn* pespconn, remot_info** pcon_info, uint8 typeflags);
+
+/******************************************************************************
+ * FunctionName : espconn_get_packet_info
+ * Description  : get the packet info with host
+ * Parameters   : espconn -- the espconn used to disconnect the connection
+ * 				  infoarg -- the packet info
+ * Returns      : the errur code
+*******************************************************************************/
+
+sint8 espconn_get_packet_info(struct espconn* espconn, struct espconn_packet* infoarg);
+
+/******************************************************************************
+ * FunctionName : espconn_connect
+ * Description  : The function given as the connect
+ * Parameters   : espconn -- the espconn used to listen the connection
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_connect(struct espconn* espconn);
+
+/******************************************************************************
+ * FunctionName : espconn_disconnect
+ * Description  : disconnect with host
+ * Parameters   : espconn -- the espconn used to disconnect the connection
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_disconnect(struct espconn* espconn);
+
+/******************************************************************************
+ * FunctionName : espconn_delete
+ * Description  : disconnect with host
+ * Parameters   : espconn -- the espconn used to disconnect the connection
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_delete(struct espconn* espconn);
+
+/******************************************************************************
+ * FunctionName : espconn_accept
+ * Description  : The function given as the listen
+ * Parameters   : espconn -- the espconn used to listen the connection
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_accept(struct espconn* espconn);
+
+/******************************************************************************
+ * FunctionName : espconn_create
+ * Description  : sent data for client or server
+ * Parameters   : espconn -- espconn to the data transmission
+ * Returns      : result
+*******************************************************************************/
+
+extern sint8 espconn_create(struct espconn* espconn);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_get_wnd
+ * Description  : get the window size of simulatenously active TCP connections
+ * Parameters   : none
+ * Returns      : the number of TCP_MSS active TCP connections
+*******************************************************************************/
+extern uint8 espconn_tcp_get_wnd(void);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_set_max_con
+ * Description  : set the window size simulatenously active TCP connections
+ * Parameters   : num -- the number of TCP_MSS
+ * Returns      : ESPCONN_ARG -- Illegal argument
+ * 				  ESPCONN_OK  -- No error
+*******************************************************************************/
+extern sint8 espconn_tcp_set_wnd(uint8 num);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_get_max_con
+ * Description  : get the number of simulatenously active TCP connections
+ * Parameters   : none
+ * Returns      : none
+*******************************************************************************/
+
+extern uint8 espconn_tcp_get_max_con(void);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_set_max_con
+ * Description  : set the number of simulatenously active TCP connections
+ * Parameters   : num -- total number
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_tcp_set_max_con(uint8 num);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_get_max_retran
+ * Description  : get the Maximum number of retransmissions of data active TCP connections
+ * Parameters   : none
+ * Returns      : the Maximum number of retransmissions
+*******************************************************************************/
+extern uint8 espconn_tcp_get_max_retran(void);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_set_max_retran
+ * Description  : set the Maximum number of retransmissions of data active TCP connections
+ * Parameters   : num -- the Maximum number of retransmissions
+ * Returns      : result
+*******************************************************************************/
+
+extern sint8 espconn_tcp_set_max_retran(uint8 num);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_get_max_syn
+ * Description  : get the Maximum number of retransmissions of SYN segments
+ * Parameters   : none
+ * Returns      : the Maximum number of retransmissions
+*******************************************************************************/
+
+extern uint8 espconn_tcp_get_max_syn(void);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_set_max_syn
+ * Description  : set the Maximum number of retransmissions of SYN segments
+ * Parameters   : num -- the Maximum number of retransmissions
+ * Returns      : result
+*******************************************************************************/
+
+extern sint8 espconn_tcp_set_max_syn(uint8 num);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_get_max_con_allow
+ * Description  : get the count of simulatenously active connections on the server
+ * Parameters   : espconn -- espconn to get the count
+ * Returns      : result
+*******************************************************************************/
+
+extern sint8 espconn_tcp_get_max_con_allow(struct espconn* espconn);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_set_max_con_allow
+ * Description  : set the count of simulatenously active connections on the server
+ * Parameters   : espconn -- espconn to set the count
+ * Returns      : result
+*******************************************************************************/
+
+extern sint8 espconn_tcp_set_max_con_allow(struct espconn* espconn, uint8 num);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_set_buf_count
+ * Description  : set the total number of espconn_buf on the unsent lists
+ * Parameters   : espconn -- espconn to set the count
+ * 				  num -- the total number of espconn_buf
+ * Returns      : result
+*******************************************************************************/
+
+extern sint8 espconn_tcp_set_buf_count(struct espconn* espconn, uint8 num);
+
+/******************************************************************************
+ * FunctionName : espconn_regist_time
+ * Description  : used to specify the time that should be called when don't recv data
+ * Parameters   : espconn -- the espconn used to the connection
+ * 				  interval -- the timer when don't recv data
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_regist_time(struct espconn* espconn, uint32 interval, uint8 type_flag);
+
+/******************************************************************************
+ * FunctionName : espconn_regist_sentcb
+ * Description  : Used to specify the function that should be called when data
+ * 				  has been successfully delivered to the remote host.
+ * Parameters   : struct espconn *espconn -- espconn to set the sent callback
+ * 				  espconn_sent_callback sent_cb -- sent callback function to
+ * 				  call for this espconn when data is successfully sent
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_regist_sentcb(struct espconn* espconn, espconn_sent_callback sent_cb);
+
+/******************************************************************************
+ * FunctionName : espconn_regist_sentcb
+ * Description  : Used to specify the function that should be called when data
+ *                has been successfully delivered to the remote host.
+ * Parameters   : espconn -- espconn to set the sent callback
+ *                sent_cb -- sent callback function to call for this espconn
+ *                when data is successfully sent
+ * Returns      : none
+*******************************************************************************/
+extern sint8 espconn_regist_write_finish(struct espconn* espconn, espconn_connect_callback write_finish_fn);
+
+/******************************************************************************
+ * FunctionName : espconn_sent
+ * Description  : sent data for client or server
+ * Parameters   : espconn -- espconn to set for client or server
+ * 				  psent -- data to send
+ *                length -- length of data to send
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_sent(struct espconn* espconn, uint8* psent, uint16 length);
+
+/******************************************************************************
+ * FunctionName : espconn_regist_connectcb
+ * Description  : used to specify the function that should be called when
+ * 				  connects to host.
+ * Parameters   : espconn -- espconn to set the connect callback
+ * 				  connect_cb -- connected callback function to call when connected
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_regist_connectcb(struct espconn* espconn, espconn_connect_callback connect_cb);
+
+/******************************************************************************
+ * FunctionName : espconn_regist_recvcb
+ * Description  : used to specify the function that should be called when recv
+ * 				  data from host.
+ * Parameters   : espconn -- espconn to set the recv callback
+ * 				  recv_cb -- recv callback function to call when recv data
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_regist_recvcb(struct espconn* espconn, espconn_recv_callback recv_cb);
+
+/******************************************************************************
+ * FunctionName : espconn_regist_reconcb
+ * Description  : used to specify the function that should be called when connection
+ * 				  because of err disconnect.
+ * Parameters   : espconn -- espconn to set the err callback
+ * 				  recon_cb -- err callback function to call when err
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_regist_reconcb(struct espconn* espconn, espconn_reconnect_callback recon_cb);
+
+/******************************************************************************
+ * FunctionName : espconn_regist_disconcb
+ * Description  : used to specify the function that should be called when disconnect
+ * Parameters   : espconn -- espconn to set the err callback
+ *                discon_cb -- err callback function to call when err
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_regist_disconcb(struct espconn* espconn, espconn_connect_callback discon_cb);
+
+/******************************************************************************
+ * FunctionName : espconn_port
+ * Description  : access port value for client so that we don't end up bouncing
+ *                all connections at the same time .
+ * Parameters   : none
+ * Returns      : access port value
+*******************************************************************************/
+
+extern uint32 espconn_port(void);
+
+/******************************************************************************
+ * FunctionName : espconn_set_opt
+ * Description  : access port value for client so that we don't end up bouncing
+ *                all connections at the same time .
+ * Parameters   : none
+ * Returns      : access port value
+*******************************************************************************/
+extern sint8 espconn_set_opt(struct espconn* espconn, uint8 opt);
+
+/******************************************************************************
+ * FunctionName : espconn_set_keepalive
+ * Description  : access level value for connection so that we set the value for
+ * 				  keep alive
+ * Parameters   : espconn -- the espconn used to set the connection
+ * 				  level -- the connection's level
+ * 				  value -- the value of time(s)
+ * Returns      : access port value
+*******************************************************************************/
+extern sint8 espconn_set_keepalive(struct espconn* espconn, uint8 level, void* optarg);
+
+/******************************************************************************
+ * FunctionName : espconn_get_keepalive
+ * Description  : access level value for connection so that we get the value for
+ * 				  keep alive
+ * Parameters   : espconn -- the espconn used to get the connection
+ * 				  level -- the connection's level
+ * Returns      : access keep alive value
+*******************************************************************************/
+extern sint8 espconn_get_keepalive(struct espconn* espconn, uint8 level, void* optarg);
+
+/******************************************************************************
+ * FunctionName : espconn_gethostbyname
+ * Description  : Resolve a hostname (string) into an IP address.
+ * Parameters   : pespconn -- espconn to resolve a hostname
+ *                hostname -- the hostname that is to be queried
+ *                addr -- pointer to a ip_addr_t where to store the address if
+ *                        it is already cached in the dns_table (only valid if
+ *                        ESPCONN_OK is returned!)
+ *                found -- a callback function to be called on success, failure
+ *                         or timeout (only if ERR_INPROGRESS is returned!)
+ * Returns      : err_t return code
+ *                - ESPCONN_OK if hostname is a valid IP address string or the host
+ *                  name is already in the local names table.
+ *                - ESPCONN_INPROGRESS enqueue a request to be sent to the DNS server
+ *                  for resolution if no errors are present.
+ *                - ESPCONN_ARG: dns client not initialized or invalid hostname
+*******************************************************************************/
+
+extern err_t espconn_gethostbyname(struct espconn* pespconn, const char* name, ip_addr_t* addr, dns_found_callback found);
+
+/******************************************************************************
+ * FunctionName : espconn_igmp_join
+ * Description  : join a multicast group
+ * Parameters   : host_ip -- the ip address of udp server
+ * 				  multicast_ip -- multicast ip given by user
+ * Returns      : none
+*******************************************************************************/
+extern sint8 espconn_igmp_join(ip_addr_t* host_ip, ip_addr_t* multicast_ip);
+
+/******************************************************************************
+ * FunctionName : espconn_igmp_leave
+ * Description  : leave a multicast group
+ * Parameters   : host_ip -- the ip address of udp server
+ * 				  multicast_ip -- multicast ip given by user
+ * Returns      : none
+*******************************************************************************/
+extern sint8 espconn_igmp_leave(ip_addr_t* host_ip, ip_addr_t* multicast_ip);
+
+/******************************************************************************
+ * FunctionName : espconn_mdns_init
+ * Description  : register a device with mdns
+ * Parameters   : ipAddr -- the ip address of device
+ * 				  hostname -- the hostname of device
+ * Returns      : none
+*******************************************************************************/
+extern void espconn_mdns_init(struct mdns_info* info);
+/******************************************************************************
+ * FunctionName : espconn_mdns_init
+ * Description  : close mdns socket
+ * Parameters   : void
+ * Returns      : none
+*******************************************************************************/
+extern void espconn_mdns_close(void);
+/******************************************************************************
+ * FunctionName : mdns_server_register
+ * Description  : register a server and join a multicast group
+ * Parameters   : none
+ * Returns      : none
+*******************************************************************************/
+extern void espconn_mdns_server_register(void);
+/******************************************************************************
+ * FunctionName : mdns_server_register
+ * Description  : unregister server and leave multicast group
+ * Parameters   : none
+ * Returns      : none
+*******************************************************************************/
+extern void espconn_mdns_server_unregister(void);
+/******************************************************************************
+ * FunctionName : espconn_mdns_get_servername
+ * Description  : get server name
+ * Parameters   : none
+ * Returns      : server name
+*******************************************************************************/
+extern char* espconn_mdns_get_servername(void);
+/******************************************************************************
+ * FunctionName : espconn_mdns_get_servername
+ * Description  : set server name
+ * Parameters   : server name
+ * Returns      : none
+*******************************************************************************/
+extern void espconn_mdns_set_servername(const char* name);
+/******************************************************************************
+ * FunctionName : espconn_mdns_set_hostname
+ * Description  : set host name
+ * Parameters   : host name
+ * Returns      : none
+*******************************************************************************/
+extern void espconn_mdns_set_hostname(char* name);
+/******************************************************************************
+ * FunctionName : espconn_mdns_init
+ * Description  : get host name
+ * Parameters   : void
+ * Returns      : hostname
+*******************************************************************************/
+extern char* espconn_mdns_get_hostname(void);
+/******************************************************************************
+ * FunctionName : espconn_mdns_disable
+ * Description  : join a multicast group
+ * Parameters   : host_ip -- the ip address of udp server
+ * 				  multicast_ip -- multicast ip given by user
+ * Returns      : none
+*******************************************************************************/
+extern void espconn_mdns_disable(void);
+/******************************************************************************
+ * FunctionName : espconn_mdns_enable
+ * Description  : enable mdns
+ * Parameters   : void
+ * Returns      : none
+*******************************************************************************/
+extern void espconn_mdns_enable(void);
+/******************************************************************************
+ * FunctionName : espconn_dns_setserver
+ * Description  : Initialize one of the DNS servers.
+ * Parameters   : numdns -- the index of the DNS server to set must
+ * 				  be < DNS_MAX_SERVERS = 2
+ * 			      dnsserver -- IP address of the DNS server to set
+ *  Returns     : none
+*******************************************************************************/
+extern void espconn_dns_setserver(u8_t numdns, ip_addr_t* dnsserver);
+#endif
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espconn/espconn_buf.h

@@ -0,0 +1,68 @@
+/*
+ * ESPRESSIF MIT License
+ *
+ * Copyright (c) 2017 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _ESPCONN_BUF_H_
+#define _ESPCONN_BUF_H_
+
+#include "c_types.h"
+
+typedef struct ringbuf_t {
+    uint8_t* buf;
+    uint8_t* head, *tail;
+    size_t size;
+} ringbuf, *ringbuf_t;
+
+ringbuf_t ringbuf_new(size_t capacity);
+
+size_t ringbuf_buffer_size(const struct ringbuf_t* rb);
+
+void ringbuf_reset(ringbuf_t rb);
+
+void ringbuf_free(ringbuf_t* rb);
+
+size_t ringbuf_capacity(const struct ringbuf_t* rb);
+
+size_t ringbuf_bytes_free(const struct ringbuf_t* rb);
+
+size_t ringbuf_bytes_used(const struct ringbuf_t* rb);
+
+int ringbuf_is_full(const struct ringbuf_t* rb);
+
+int ringbuf_is_empty(const struct ringbuf_t* rb);
+
+const void* ringbuf_tail(const struct ringbuf_t* rb);
+
+const void* ringbuf_head(const struct ringbuf_t* rb);
+
+static uint8_t* ringbuf_nextp(ringbuf_t rb, const uint8_t* p);
+
+size_t ringbuf_findchr(const struct ringbuf_t* rb, int c, size_t offset);
+
+size_t ringbuf_memset(ringbuf_t dst, int c, size_t len);
+
+void* ringbuf_memcpy_into(ringbuf_t dst, const void* src, size_t count);
+
+void* ringbuf_memcpy_from(void* dst, ringbuf_t src, size_t count);
+
+#endif /* RINGBUF_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espconn/espconn_tcp.h

@@ -0,0 +1,80 @@
+/*
+ * ESPRESSIF MIT License
+ *
+ * Copyright (c) 2017 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESPCONN_TCP_H__
+#define __ESPCONN_TCP_H__
+
+#ifndef ESPCONN_TCP_DEBUG
+#define ESPCONN_TCP_DEBUG LWIP_DBG_OFF
+#endif
+
+#include "espconn/espconn.h"
+
+#ifndef ESPCONN_TCP_TIMER
+#define ESPCONN_TCP_TIMER 40
+#endif
+
+#define  espconn_keepalive_enable(pcb)   ((pcb)->so_options |= SOF_KEEPALIVE)
+#define  espconn_keepalive_disable(pcb)   ((pcb)->so_options &= ~SOF_KEEPALIVE)
+
+/******************************************************************************
+ * FunctionName : espconn_kill_oldest_pcb
+ * Description  : A oldest incoming connection has been killed.
+ * Parameters   : none
+ * Returns      : none
+*******************************************************************************/
+
+extern void espconn_kill_oldest_pcb(void);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_disconnect
+ * Description  : A new incoming connection has been disconnected.
+ * Parameters   : espconn -- the espconn used to disconnect with host
+ * Returns      : none
+*******************************************************************************/
+
+extern void espconn_tcp_disconnect(espconn_msg* pdiscon, u8 type);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_client
+ * Description  : Initialize the client: set up a connect PCB and bind it to
+ *                the defined port
+ * Parameters   : espconn -- the espconn used to build client
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_tcp_client(struct espconn* espconn);
+
+/******************************************************************************
+ * FunctionName : espconn_tcp_server
+ * Description  : Initialize the server: set up a listening PCB and bind it to
+ *                the defined port
+ * Parameters   : espconn -- the espconn used to build server
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_tcp_server(struct espconn* espconn);
+
+#endif /* __CLIENT_TCP_H__ */
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espconn/espconn_udp.h

@@ -0,0 +1,88 @@
+/*
+ * ESPRESSIF MIT License
+ *
+ * Copyright (c) 2017 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESPCONN_UDP_H__
+#define __ESPCONN_UDP_H__
+
+#ifndef ESPCONN_UDP_DEBUG
+#define ESPCONN_UDP_DEBUG LWIP_DBG_OFF
+#endif
+
+#include "espconn/espconn.h"
+
+/******************************************************************************
+ * FunctionName : espconn_udp_client
+ * Description  : Initialize the client: set up a PCB and bind it to the port
+ * Parameters   : pespconn -- the espconn used to build client
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_udp_client(struct espconn* pespconn);
+
+/******************************************************************************
+ * FunctionName : espconn_udp_disconnect
+ * Description  : A new incoming connection has been disconnected.
+ * Parameters   : espconn -- the espconn used to disconnect with host
+ * Returns      : none
+*******************************************************************************/
+
+extern void espconn_udp_disconnect(espconn_msg* pdiscon);
+
+/******************************************************************************
+ * FunctionName : espconn_udp_server
+ * Description  : Initialize the server: set up a PCB and bind it to the port
+ * Parameters   : pespconn -- the espconn used to build server
+ * Returns      : none
+*******************************************************************************/
+
+extern sint8 espconn_udp_server(struct espconn* espconn);
+
+/******************************************************************************
+ * FunctionName : espconn_udp_sent
+ * Description  : sent data for client or server
+ * Parameters   : void *arg -- client or server to send
+ *                uint8* psent -- Data to send
+ *                uint16 length -- Length of data to send
+ * Returns      : none
+*******************************************************************************/
+
+extern err_t espconn_udp_sent(void* arg, uint8* psent, uint16 length);
+
+/******************************************************************************
+ * FunctionName : espconn_udp_sendto
+ * Description  : sent data for UDP
+ * Parameters   : void *arg -- UDP to send
+ * 				  uint8* psent -- Data to send
+ *                uint16 length -- Length of data to send
+ * Returns      : return espconn error code.
+ * - ESPCONN_OK. Successful. No error occured.
+ * - ESPCONN_MEM. Out of memory.
+ * - ESPCONN_RTE. Could not find route to destination address.
+ * - More errors could be returned by lower protocol layers.
+*******************************************************************************/
+extern err_t espconn_udp_sendto(void* arg, uint8* psent, uint16 length);
+
+#endif /* __ESPCONN_UDP_H__ */
+
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/arch/espos_arch.h

@@ -0,0 +1,20 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESPOS_ARCH_H_
+#define _ESPOS_ARCH_H_
+
+#include "espos_esp8266.h"
+
+#endif /* _ESPOS_ARCH_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/arch/espos_esp8266.h

@@ -0,0 +1,57 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESPOS_ESP8266_H_
+#define _ESPOS_ESP8266_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ESPOS_PROCESSORS_NUM 1u
+
+#define ESPOS_SPINLOCK_ARCH_UNLOCK_INITIALIZER \
+    {                                          \
+        0,                                     \
+    }
+
+typedef int32_t esp_err_t;
+
+typedef struct espos_spinlock_arch {
+    int lock;
+} espos_spinlock_arch_t;
+
+static inline uintptr_t espos_suspend_interrupt(void)
+{
+    uintptr_t state;
+
+    __asm__ volatile ("RSIL %0, 5" : "=a" (state) :: "memory");
+
+    return state;
+}
+
+static inline void espos_resume_interrupt(uintptr_t state)
+{
+    __asm__ volatile ("WSR %0, ps" :: "a" (state) : "memory");
+}
+
+#define espos_get_core_id() 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ESPOS_ESP8266_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_errno.h

@@ -0,0 +1,6 @@
+#ifndef _ESPOS_ERRNO_H_
+#define _ESPOS_ERRNO_H_
+
+#include <sys/errno.h>
+
+#endif /* _ESPOS_ERRNO_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_include.h

@@ -0,0 +1,15 @@
+#ifndef ESPOS_INCLUDE_H
+#define ESPOS_INCLUDE_H
+
+#include "espos_errno.h"
+#include "espos_mutex.h"
+#include "espos_queue.h"
+#include "espos_scheduler.h"
+#include "espos_semaphore.h"
+#include "espos_spinlock.h"
+#include "espos_task.h"
+#include "espos_time.h"
+#include "espos_timer.h"
+#include "espos_types.h"
+
+#endif /* ESPOS_INCLUDE_H */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_mutex.h

@@ -0,0 +1,141 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESPOS_MUTEX_H_
+#define _ESPOS_MUTEX_H_
+
+#include "espos_types.h"
+#include "espos_errno.h"
+#include "espos_time.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* use default option to create mutex */
+typedef enum espos_mutex_opt {
+
+    /* AT this mode, deadlock detection shall not be provided. Attempting to relock the mutex causes deadlock.
+     *
+     * If a thread attempts to unlock a mutex that it has not locked or a mutex which is unlocked,
+     * undefined behavior results.
+     */
+    ESPOS_MUTEX_NORMAL = 0,
+
+    ESPOS_MUTEX_RECURSIVE,
+
+    ESPOS_MUTEX_TYPE_MAX
+} espos_mutex_type_t;
+
+#define ESPOS_MUTEX_TYPE(type) (type & 0xFF)
+
+/**
+ * @brief create a mutex
+ *
+ * @param mutex mutex handle point
+ * @param opt mutex option, if you don't know how to do, just use "ESPOS_MUTEX_NORMAL" here
+ *
+ * @return the result
+ *             0 : successful
+ *       -ENOMEM : no enough memory
+ *       -EINTR  : you do this at interrupt state, and it is not supported
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_mutex_create(espos_mutex_t *mutex, espos_opt_t opt);
+
+/**
+ * @brief set a mutex name
+ *
+ * @param mutex mutex handle
+ * @param name mutex's name
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_mutex_set_name(espos_mutex_t mutex, const char *name);
+
+/**
+ * @brief lock a mutex
+ *
+ * @param mutex mutex handle
+ * @param wait_ticks sleep for system ticks if the locked mutex is not unlocked. Otherwise if someone
+ *                   else unlock the locked mutex, you will wake up.
+ *                   maximum time is "ESPOS_MAX_DELAY", no time is "ESPOS_NO_DELAY"
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *        -EINTR : you do this at interrupt state, and it is not supported
+ *    -ETIMEDOUT : timeout and you have not locked it
+ *
+ * @note you can transform the millisecond to ticks by "espos_ms_to_ticks"
+ */
+esp_err_t espos_mutex_lock(espos_mutex_t mutex, espos_tick_t wait_ticks);
+
+/**
+ * @bref try to lock a mutex and it will return immediately without being blocked
+ *
+ * @param m mutex handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *        -EINTR : you do this at interrupt state, and it is not supported
+ */
+#define espos_mutex_trylock(m) espos_mutex_lock(m, ESPOS_NO_DELAY)
+
+/**
+ * @brief unlock a mutex
+ *
+ * @param mutex mutex handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *        -EINTR : you do this at interrupt state, and it is not supported
+ *        -EPERM : current task don't lock the mutex
+ */
+esp_err_t espos_mutex_unlock(espos_mutex_t mutex);
+
+/**
+ * @brief get task handle which lock the mutex
+ *
+ * @param mutex mutex handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+espos_task_t espos_mutex_get_holder(espos_mutex_t mutex);
+
+/**
+ * @brief delete the mutex
+ *
+ * @param mutex mutex handle
+ *
+ * @return the result
+ *             0 : successful
+ *        -EINTR : you do this at interrupt state, and it is not supported
+ *       -EINVAL : input parameter error
+ *
+ * @note if low-level module is YunOS, this function will awake all task blocked at the mutex
+ */
+esp_err_t espos_mutex_del(espos_mutex_t mutex);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ESPOS_MUTEX_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_queue.h

@@ -0,0 +1,212 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESPOS_QUEUE_H_
+#define _ESPOS_QUEUE_H_
+
+#include "espos_types.h"
+#include "espos_errno.h"
+#include "espos_time.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum espos_queue_pos {
+    /* send message to the front of the queue */
+    ESPOS_QUEUE_SEND_FRONT = 0,
+
+    /* send message to the back of the queue */
+    ESPOS_QUEUE_SEND_BACK,
+
+    ESPOS_QUEUE_POS_MAX
+} espos_queue_pos_t;
+
+typedef enum espos_queue_send_opt {
+    /* send message with normal option */
+    ESPOS_QUEUE_SEND_OPT_NORMAL = 0,
+
+    ESPOS_QUEUE_SEND_OPT_MAX
+} espos_queue_send_opt_t;
+
+typedef enum espos_queue_recv_opt {
+    /* receive message with normal option */
+    ESPOS_QUEUE_RECV_OPT_NORMAL = 0,
+
+    ESPOS_QUEUE_RECV_OPT_MAX
+} espos_queue_recv_opt_t;
+
+/**
+ * @brief create a queue
+ *
+ * @param queue queue handle point
+ * @param msg_len queue internal message length (bytes)
+ * @param queue_len queue internal message maximum number
+ *
+ * @return the result
+ *             0 : successful
+ *       -ENOMEM : no enough memory
+ *       -EINTR  : you do this at interrupt state, and it is not supported
+ *       -EINVAL : input parameter error
+ *
+ * @note all input and out message length is fixedly "msg_len"
+ */
+esp_err_t espos_queue_create(espos_queue_t *queue, espos_size_t msg_len, espos_size_t queue_len);
+
+/**
+ * @brief set a queue name
+ *
+ * @param queue queue handle
+ * @param name queue's name
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_queue_set_name(espos_queue_t queue, const char *name);
+
+/**
+ * @brief send a message to the queue, it is suggested that you had better not use "espos_queue_send" directly,
+ *       please use "espos_queue_send_front" or "espos_queue_send_back"
+ *
+ * @param queue queue handle
+ * @param msg message point
+ * @param wait_ticks sleep for system ticks if the queue is full. Otherwise if queue is not full, you will wake up.
+ *                   maximum time is "ESPOS_MAX_DELAY", no time is "ESPOS_NO_DELAY"
+ * @param pos position where sending the message
+ *               ESPOS_QUEUE_SEND_FRONT : send message to the front of the queue
+ *               ESPOS_QUEUE_SEND_BACK  : send message to the back of the queue
+ * @param opt sending option
+ *               ESPOS_QUEUE_SEND_OPT_NORMAL : wake up blocked task
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ETIMEDOUT : timeout and the queue is full
+ *
+ * @note you can transform the millisecond to ticks by "espos_ms_to_ticks"
+ */
+esp_err_t espos_queue_send_generic(espos_queue_t queue, void *msg, espos_tick_t wait_ticks, espos_pos_t pos, espos_opt_t opt);
+
+/**
+ * @brief send a message to the front of the queue
+ *
+ * @param q queue handle
+ * @param m message point
+ * @param t sleep for system ticks if the queue is full. Otherwise if queue is not full, you will wake up.
+ *                   maximum time is "ESPOS_MAX_DELAY", no time is "ESPOS_NO_DELAY"
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ETIMEDOUT : timeout and the queue is full
+ *
+ * @note you can transform the millisecond to ticks by "espos_ms_to_ticks"
+ */
+#define espos_queue_send_front(q, m, t) espos_queue_send_generic(q, m, t, ESPOS_QUEUE_SEND_FRONT, ESPOS_QUEUE_SEND_OPT_NORMAL)
+
+/**
+ * @brief send a message to the back of the queue
+ *
+ * @param q queue handle
+ * @param m message point
+ * @param t sleep for system ticks if the queue is full. Otherwise if queue is not full, you will wake up.
+ *                   maximum time is "ESPOS_MAX_DELAY", no time is "ESPOS_NO_DELAY"
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ETIMEDOUT : timeout and the queue is full
+ *
+ * @note you can transform the millisecond to ticks by "espos_ms_to_ticks"
+ */
+#define espos_queue_send(q, m, t)  espos_queue_send_generic(q, m, t, ESPOS_QUEUE_SEND_BACK, ESPOS_QUEUE_SEND_OPT_NORMAL)
+
+/**
+ * @brief receive a message of the queue
+ *
+ * @param queue queue handle
+ * @param msg message point
+ * @param wait_ticks sleep for system ticks if the queue is empty. Otherwise if queue is not empty, you will wake up.
+ *                   maximum time is "ESPOS_MAX_DELAY", no time is "ESPOS_NO_DELAY", at CPU ISR mode, it is forced to be 0
+ * @param opt queue sending option
+ *               ESPOS_QUEUE_RECV_OPT_NORMAL : use wait_ticks to check if it is need be blocked
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ETIMEDOUT : timeout and the queue is empty
+ *
+ * @note you can transform the millisecond to ticks by "espos_ms_to_ticks"
+ */
+esp_err_t espos_queue_recv_generic(espos_queue_t queue, void *msg, espos_tick_t wait_ticks, espos_opt_t opt);
+
+/**
+ * @brief receive a message of the queue with normal option
+ *
+ * @param queue queue handle
+ * @param msg message point
+ * @param wait_ticks sleep for system ticks if the queue is empty. Otherwise if queue is not empty, you will wake up.
+ *                   maximum time is "ESPOS_MAX_DELAY", no time is "ESPOS_NO_DELAY", at CPU ISR mode, it is forced to be 0
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ETIMEDOUT : timeout and the queue is empty
+ *
+ * @note you can transform the millisecond to ticks by "espos_ms_to_ticks"
+ */
+#define espos_queue_recv(q, m, t) espos_queue_recv_generic(q, m, t, ESPOS_QUEUE_RECV_OPT_NORMAL)
+
+/**
+ * @brief get current message number of the queue
+ *
+ * @param queue queue handle
+ *
+ * @return current message number of the queue
+ */
+espos_size_t espos_queue_msg_waiting(espos_queue_t queue);
+
+/**
+ * @brief reset the queue
+ *
+ * @param queue queue handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *
+ * @note if low-level module is YunOS, the function will not awake the tasks which is blocked at the queue
+ */
+esp_err_t espos_queue_flush(espos_queue_t queue);
+
+/**
+ * @brief delete the queue
+ *
+ * @param queue queue handle
+ *
+ * @return the result
+ *             0 : successful
+ *        -EINTR : you do this at interrupt state, and it is not supported
+ *       -EINVAL : input parameter error
+ *
+ * @note if low-level module is YunOS, this function will awake all task blocked at the mutex
+ */
+esp_err_t espos_queue_del(espos_queue_t queue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ESPOS_QUEUE_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_scheduler.h

@@ -0,0 +1,325 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESPOS_SCHEDULER_H_
+#define _ESPOS_SCHEDULER_H_
+
+#include <stdbool.h>
+
+#include "espos_types.h"
+#include "espos_errno.h"
+#include "espos_spinlock.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * ESPOS state
+ */
+typedef enum espos_stat {
+    ESPOS_IS_NOT_STARTED = 0,
+    ESPOS_IS_RUNNING,
+    ESPOS_IS_SUSPENDED
+} espos_stat_t;
+
+/************************************ internal function ************************************/
+/**
+ * @brief enter ESPOS system critical state
+ *
+ * @param spinlock spinlock handle point
+ *
+ * @return critical state temple variable(used by "espos_exit_critical")
+ */
+espos_critical_t _espos_enter_critical(espos_spinlock_t *spinlock);
+
+/**
+ * @brief exit ESPOS system critical state
+ *
+ * @param spinlock spinlock handle point
+ * @param tmp critical state temple variable(created by "espos_enter_critical")
+ *
+ * @return none
+ */
+void _espos_exit_critical(espos_spinlock_t *spinlock, espos_critical_t tmp);
+
+/*******************************************************************************************/
+
+/**
+ * @brief initialize ESPOS system
+ *
+ * @return the result
+ *             0 : successful
+ *       -ENOMEM : no enough memory
+ */
+esp_err_t espos_init(void);
+
+/**
+ * @brief start ESPOS system
+ *
+ * @return the result
+ *             0 : successful
+ *        -EPERM : failed (it will never happen in a general way)
+ */
+esp_err_t espos_start(void);
+
+/**
+ * @brief get espos system state
+ *
+ * @return the state
+ *         ESPOS_IS_NOT_STARTED : ESPOS is not started
+ *         ESPOS_IS_RUNNING     : ESPOS is running
+ *         ESPOS_IS_SUSPENDED   : ESPOS is suspended
+ */
+espos_stat_t espos_sched_state_get(void);
+
+#if ESPOS_PROCESSORS_NUM > 1u
+
+/**
+ * @brief start ESPOS system CPU port
+ *
+ * @param port CPU port ID
+ *
+ * @return the result
+ *             0 : successful
+ *        -EPERM : failed (it will never happen in a general way)
+ */
+esp_err_t espos_start_port(int port);
+
+/**
+ * @brief declare espos critical temp data
+ */
+#define espos_declare_critical(t) espos_critical_t t
+
+/**
+ * @brief enter ESPOS system critical state
+ *
+ * @param sl spinlock handle
+ * @param t  critical state
+ *
+ * @return critical state temple variable(used by "espos_exit_critical")
+ */
+#define espos_enter_critical(t, sl) (t) = _espos_enter_critical(&(sl))
+
+/**
+ * @brief exit ESPOS system critical state
+ *
+ * @param t critical state temple variable(created by "espos_enter_critical")
+ * @param sl spinlock handle point
+ *
+ * @return none
+ */
+#define espos_exit_critical(t, sl) _espos_exit_critical(&(sl), t)
+
+/**
+ * @brief OS internal function enter ESPOS system critical state
+ *
+ * @param sl spinlock handle
+ * @param t  critical state
+ *
+ * @return critical state temple variable(used by "espos_exit_critical")
+ *
+ * @note: ESPOS is application level OS API, so it means all APIs call internal
+ *        real OS's function, so if OS's or its core hardware's functions want
+ *        to call ESPOS, loop nesting will occur, so we should tell ESPOS it's
+ *        at OS internal state now.
+ */
+#define espos_os_enter_critical(t, sl)  \
+    espos_os_enter();                  \
+    (t) = _espos_enter_critical(&(sl))
+
+/**
+ * @brief OS internal function exit ESPOS system critical state
+ *
+ * @param t critical state temple variable(created by "espos_enter_critical")
+ * @param sl spinlock handle point
+ *
+ * @return none
+ *
+ * @note: ESPOS is application level OS API, so it means all APIs call internal
+ *        real OS's function, so if OS's or its core hardware's functions want
+ *        to call ESPOS, loop nesting will occur, so we should tell ESPOS it's
+ *        at OS internal state now.
+ */
+#define espos_os_exit_critical(t, sl)   \
+    _espos_exit_critical(&(sl), t);     \
+    espos_os_exit()
+
+#else
+
+/**
+ * @brief start ESPOS system CPU port
+ *
+ * @param port CPU port ID
+ *
+ * @return the result
+ *       -ENODEV : no device
+ */
+static esp_err_t espos_start_port(int port)
+{
+    return -ENODEV;
+}
+
+/**
+ * @brief declare espos critical temp data
+ */
+#define espos_declare_critical(t) espos_critical_t t
+
+/**
+ * @brief enter ESPOS system critical state
+ *
+ * @param sl no mean
+ * @param t  critical state
+ *
+ * @return critical state temple variable(used by "espos_exit_critical")
+ */
+#define espos_enter_critical(t, sl) (t) = _espos_enter_critical(NULL)
+
+/**
+ * @brief exit ESPOS system critical state
+ *
+ * @param t critical state temple variable(created by "espos_enter_critical")
+ * @param sl no mean
+ *
+ * @return none
+ */
+#define espos_exit_critical(t, sl) _espos_exit_critical(NULL, t)
+
+/**
+ * @brief OS internal function enter ESPOS system critical state
+ *
+ * @param sl no mean
+ * @param t  critical state
+ *
+ * @return critical state temple variable(used by "espos_exit_critical")
+ *
+ * @note: ESPOS is application level OS API, so it means all APIs call internal
+ *        real OS's function, so if OS's or its core hardware's functions want
+ *        to call ESPOS, loop nesting will occur, so we should tell ESPOS it's
+ *        at OS internal state now.
+ */
+#define espos_os_enter_critical(t, sl)  \
+    espos_os_enter();                  \
+    (t) = _espos_enter_critical(NULL)
+
+/**
+ * @brief OS internal function exit ESPOS system critical state
+ *
+ * @param t critical state temple variable(created by "espos_enter_critical")
+ * @param sl no mean
+ *
+ * @return none
+ *
+ * @note: ESPOS is application level OS API, so it means all APIs call internal
+ *        real OS's function, so if OS's or its core hardware's functions want
+ *        to call ESPOS, loop nesting will occur, so we should tell ESPOS it's
+ *        at OS internal state now.
+ */
+#define espos_os_exit_critical(t, sl)   \
+    _espos_exit_critical(NULL, t);      \
+    espos_os_exit()
+
+#endif
+
+/**
+ * @brief suspend the local CPU core preempt and the current task
+ *        owned by local CPU core  will not be preempted
+ *
+ * @return the result
+ *             0 : successful
+ *       -EAGAIN : preempt suspending maximum number is reached, and fail to do it
+ *        -EINTR : you do this at interrupt state, and it is not supported
+ *
+ * @note the function can be used nested
+ */
+esp_err_t espos_preempt_suspend_local(void);
+
+/**
+ * @brief resume the local CPU core preempt
+ *
+ * @return the result
+ *             0 : successful
+ *       -EAGAIN : preempt resuming maximum number is reached, and fail to do it
+ *        -EINTR : you do this at interrupt state, and it is not supported
+ *
+ * @note the function can be used nested
+ */
+esp_err_t espos_preempt_resume_local(void);
+
+/**
+ * @brief enter system interrupt server, the function must be used after entering hardware interrupt
+ *
+ * @return the result
+ *             0 : successful
+ *       -EAGAIN : nested count is reached
+ *
+ * @note the function can be used nested
+ */
+esp_err_t espos_isr_enter (void);
+
+/**
+ * @brief exit system interrupt server, the function must be used before exiting hardware interrupt
+ *
+ * @return none
+ *
+ * @note the function can be used nested
+ */
+void espos_isr_exit(void);
+
+/**
+ * @brief check if the CPU is at ISR state
+ *
+ * @param none
+ *
+ * @return true if the CPU is at ISR state or false
+ */
+bool espos_in_isr(void);
+
+/**
+ * @brief mark it enters real OS interal function
+ *
+ * @return the result
+ *             0 : successful
+ *       -EAGAIN : nested count is reached
+ *
+ * @note the function can be used nested
+ */
+esp_err_t espos_os_enter(void);
+
+/**
+ * @brief remove mark it enters real OS interal function
+ *
+ * @param none
+ *
+ * @return none
+ */
+void espos_os_exit(void);
+
+/**
+ * @brief check if the function is at real OS internal fucntion
+ *
+ * @param none
+ *
+ * @return true if the CPU is at real OS internal fucntion or false
+ */
+bool espos_os_isr(void);
+
+size_t espos_get_free_heap_size(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_semaphore.h

@@ -0,0 +1,118 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESPOS_SEMAPHORE_H_
+#define _ESPOS_SEMAPHORE_H_
+
+#include "espos_types.h"
+#include "espos_errno.h"
+#include "espos_time.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief create a semaphore
+ *
+ * @param sem semaphore handle point
+ * @param max_count semaphore maximum count
+ * @param init_count semaphore initialized count
+ *
+ * @return the result
+ *             0 : successful
+ *       -ENOMEM : no enough memory
+ *       -EINVAL : input parameter error
+ *
+ * @note if low-level module is YunOS, "max_count" does not work, and the reachable count is "0xFFFFFFFF"
+ */
+esp_err_t espos_sem_create(espos_sem_t *sem, espos_sem_count_t max_count, espos_sem_count_t init_count);
+
+/**
+ * @brief set a semaphore name
+ *
+ * @param semaphore semaphore handle
+ * @param name semaphore's name
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_sem_set_name(espos_sem_t sem, const char *name);
+
+/**
+ * @brief take semaphore
+ *
+ * @param sem semaphore handle
+ * @param wait_ticks sleep for system ticks if the semaphore is empty. Otherwise if semaphore is given,
+ *                   oldest blocked task will wake up.
+ *                   maximum time is "ESPOS_MAX_DELAY", no time is "ESPOS_NO_DELAY"
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ETIMEDOUT : timeout and not take semaphore
+ *
+ * @note you can transform the millisecond to ticks by "espos_ms_to_ticks"
+ */
+esp_err_t espos_sem_take(espos_sem_t sem, espos_tick_t wait_ticks);
+
+/**
+ * @brief try to take semaphore
+ *
+ * @param s semaphore handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ETIMEDOUT : not take semaphore
+ *
+ * @note you can transform the millisecond to ticks by "espos_ms_to_ticks"
+ */
+#define espos_sem_trytake(s) espos_sem_take(s, ESPOS_NO_DELAY)
+
+/**
+ * @brief give up semaphore
+ *
+ * @param sem semaphore handle
+ * @param wait_ticks no meaning
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *       -EAGAIN : the maximum count is reached
+ *
+ * @note you can transform the millisecond to ticks by "espos_ms_to_ticks"
+ */
+esp_err_t espos_sem_give(espos_sem_t sem);
+
+/**
+ * @brief delete the semaphore
+ *
+ * @param sem semaphore handle
+ *
+ * @return the result
+ *             0 : successful
+ *        -EINTR : you do this at interrupt state, and it is not supported
+ *       -EINVAL : input parameter error
+ *
+ * @note if low-level module is YunOS, this function will awake all task blocked here
+ */
+esp_err_t espos_sem_del(espos_sem_t sem);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ESPOS_SEMAPHORE_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_spinlock.h

@@ -0,0 +1,237 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESPOS_SPINLOCK_H_
+#define _ESPOS_SPINLOCK_H_
+
+#include "espos_types.h"
+#include "espos_errno.h"
+#include "espos_task.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if ESPOS_PROCESSORS_NUM > 1u
+
+typedef struct espos_spinlock {
+    espos_spinlock_arch_t lock;
+    espos_task_t holder;
+} espos_spinlock_t;
+
+#define ESPOS_SPINLOCK_UNLOCK_INITIALIZER       \
+    {                                           \
+        ESPOS_SPINLOCK_ARCH_UNLOCK_INITIALIZER, \
+        ESPOS_OBJ_NONE,                                      \
+    }
+
+#define ESPOS_DEFINE_SPINLOCK(l) \
+    espos_spinlock_t l = ESPOS_SPINLOCK_UNLOCK_INITIALIZER
+
+#define ESPOS_DEFINE_STATIC_SPINLOCK(l) \
+    static espos_spinlock_t l = ESPOS_SPINLOCK_UNLOCK_INITIALIZER
+
+/**
+ * @brief create a spinlock
+ *
+ * @param spinlock spinlock handle point
+ *
+ * @return the result
+ *             0 : successful
+ *       -ENOMEM : no enough memory
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_spinlock_create (espos_spinlock_t *spinlock);
+
+/**
+ * @brief set a spinlock name
+ *
+ * @param spinlock spinlock handle
+ * @param name spinlock's name
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_spinlock_set_name(espos_spinlock_t *spinlock, const char *name);
+
+/**
+ * @brief spin to lock a spinlock until successfully
+ *
+ * @param spinlock spinlock handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_spinlock_lock(espos_spinlock_t *spinlock);
+
+/**
+ * @brief try to lock a spinlock
+ *
+ * @param spinlock spinlock handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EAGAIN : no spinlock is valid
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_spinlock_trylock(espos_spinlock_t *spinlock);
+
+/**
+ * @brief get spinlock holder task handle
+ *
+ * @param spinlock spinlock handle
+ *
+ * @return holder task handle
+ */
+espos_task_t espos_spinlock_get_holder(espos_spinlock_t *spinlock);
+
+/**
+ * @brief unlock a spinlock
+ *
+ * @param spinlock spinlock handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EAGAIN : no spinlock is locked
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_spinlock_unlock(espos_spinlock_t *spinlock);
+
+/**
+ * @brief delete a spinlock
+ *
+ * @param spinlock spinlock handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EACCES : failed to do it with some special reason
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_spinlock_del(espos_spinlock_t *spinlock);
+
+#else
+
+typedef struct espos_spinlock {
+    espos_spinlock_arch_t lock;
+} espos_spinlock_t;
+
+#define ESPOS_SPINLOCK_UNLOCK_INITIALIZER       \
+    {                                           \
+        ESPOS_SPINLOCK_ARCH_UNLOCK_INITIALIZER, \
+    }
+
+#define ESPOS_DEFINE_SPINLOCK(l)
+
+#define ESPOS_DEFINE_STATIC_SPINLOCK(l)
+
+/**
+ * @brief create a spinlock
+ *
+ * @param spinlock spinlock handle point
+ *
+ * @return the result
+ *       -ENODEV : no device
+ */
+static esp_err_t espos_spinlock_create (espos_spinlock_t *spinlock)
+{
+    return -ENODEV;
+}
+
+/**
+ * @brief set a spinlock name
+ *
+ * @param spinlock spinlock handle
+ * @param name spinlock's name
+ *
+ * @return the result
+ *       -ENODEV : no device
+ */
+static esp_err_t espos_spinlock_set_name(espos_spinlock_t *spinlock, const char *name)
+{
+    return -ENODEV;
+}
+
+/**
+ * @brief spin to lock a spinlock until successfully
+ *
+ * @param spinlock spinlock handle
+ *
+ * @return the result
+ *       -ENODEV : no device
+ */
+static esp_err_t espos_spinlock_lock(espos_spinlock_t *spinlock)
+{
+    return -ENODEV;
+}
+
+/**
+ * @brief try to lock a spinlock
+ *
+ * @param spinlock spinlock handle
+ *
+ * @return the result
+ *       -ENODEV : no device
+ */
+static esp_err_t espos_spinlock_trylock(espos_spinlock_t *spinlock)
+{
+    return -ENODEV;
+}
+
+/**
+ * @brief get spinlock holder task handle
+ *
+ * @param spinlock spinlock handle
+ *
+ * @return none espos object
+ */
+static espos_task_t espos_spinlock_get_holder(espos_spinlock_t *spinlock)
+{
+    return ESPOS_OBJ_NONE;
+}
+
+/**
+ * @brief unlock a spinlock
+ *
+ * @param spinlock spinlock handle
+ *
+ * @return the result
+ *       -ENODEV : no device
+ */
+static esp_err_t espos_spinlock_unlock(espos_spinlock_t *spinlock)
+{
+    return -ENODEV;
+}
+
+/**
+ * @brief delete a spinlock
+ *
+ * @param spinlock spinlock handle
+ *
+ * @return the result
+ *       -ENODEV : no device
+ */
+static esp_err_t espos_spinlock_del(espos_spinlock_t *spinlock)
+{
+    return -ENODEV;
+}
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ESPOS_SPINLOCK_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_task.h

@@ -0,0 +1,210 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESPOS_TASK_H_
+#define _ESPOS_TASK_H_
+
+#include "espos_types.h"
+#include "espos_errno.h"
+#include "espos_time.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* task will run at any CPU */
+#define ESPOS_TASK_NO_AFFINITY  -1
+
+/* create task and start it automatically */
+#define ESPOS_TASK_CREATE_NORMAL 0
+/* just create task and don't start it */
+#define ESPOS_TASK_CREATE_SILENCE 1
+
+/* task delete itself */
+#define ESPOS_TASK_DELETE_SELF 0
+
+/*
+ * we should use a platform API instead of 'marco'
+ */
+#define ESPOS_TASK_PRIO_NUM espos_task_prio_num()
+
+/* task maximum priority number */
+#define ESPOS_TASK_PRIO_MAX (ESPOS_TASK_PRIO_NUM - 1)
+
+/**
+ * @brief create a task
+ *
+ * @param task  task handle point
+ * @param name  task name, if name is NULL, we will use "default_task" default
+ * @param arg   task entry function inputting parameter
+ * @param prio  task priority
+ * @param ticks task time slice
+ * @param stack_size task stack size, its unit is "byte"
+ * @param entry task entry function
+ * @param opt   task option
+ *               ESPOS_TASK_CREATE_NORMAL : the created task will be started automatically
+ *               ESPOS_TASK_CREATE_SILENCE : the created task will not be started automatically
+ * @param cpu_id task CPU id
+ *               natural number : the task only runs at the CPU of the number
+ *               ESPOS_TASK_NO_AFFINITY : the task runs at any CPU
+ *
+ * @return the result
+ *             0 : successful
+ *       -ENOMEM : no enough memory
+ *       -EINVAL : input parameter error
+ *       -EINTR  : you do this at interrupt state, and it is not supported
+ */
+esp_err_t espos_task_create_on_cpu(espos_task_t *task, const char *name, void *arg, espos_prio_t prio,
+                                     espos_tick_t ticks, espos_size_t stack_size, espos_task_entry_t entry, espos_opt_t opt, espos_cpu_t cpu_id);
+
+
+/**
+ * @brief create a task and set its CPU id to be "ESPOS_TASK_NO_AFFINITY"
+ *
+ * @param task  task handle point
+ * @param name  task name, if name is NULL, we will use "default_task" default
+ * @param arg   task entry function inputting parameter
+ * @param prio  task priority
+ * @param ticks task time slice
+ * @param stack_size task stack size, its unit is "byte"
+ * @param entry task entry function
+ * @param opt   task option
+ *               ESPOS_TASK_CREATE_NORMAL : the created task will be started automatically
+ *               ESPOS_TASK_CREATE_SILENCE : the created task will not be started automatically
+ *
+ * @return the result
+ *             0 : successful
+ *       -ENOMEM : no enough memory
+ *       -EINVAL : input parameter error
+ *       -EINTR  : you do this at interrupt state, and it is not supported
+ */
+#define espos_task_create(task, name, arg, prio, ticks, stack_size, entry, opt)   \
+            espos_task_create_on_cpu(task, name, arg, prio, ticks, stack_size, entry, opt, ESPOS_TASK_NO_AFFINITY)
+
+/**
+ * @brief delete a task
+ *
+ * @param task task handle
+ *               ESPOS_TASK_DELETE_SELF : task will delete itself
+ *
+ * @return the result
+ *             0 : successful
+ *       -EACCES : failed to do it with some special reason
+ */
+esp_err_t espos_task_del(espos_task_t task);
+
+/**
+ * @brief let current task sleep for some ticks
+ *
+ * @param delay_ticks system ticks
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_task_delay(const espos_tick_t delay_ticks);
+
+/**
+ * @brief suspend target task
+ *
+ * @param task task handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_task_suspend(espos_task_t task);
+
+/**
+ * @brief resume target task
+ *
+ * @param task task handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_task_resume(espos_task_t task);
+
+/**
+ * @brief yield the cpu once
+ *
+ * @return the result
+ *             0 : successful
+ *       -EACCES : failed to do it with some special reason
+ */
+esp_err_t espos_task_yield(void);
+
+/**
+ * @brief get current task handle
+ *
+ * @return current task handle
+ */
+espos_task_t espos_task_get_current(void);
+
+/**
+ * @brief get current task name point
+ *
+ * @param task task handle
+ * @param pname pointing at name's point
+ *
+ * @return current task handle
+ */
+esp_err_t espos_task_get_name (espos_task_t task, char **pname);
+
+/**
+ * @brief set task private data
+ *
+ * @param task task handle
+ * @param idx  task data index
+ * @param info task private data
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_task_set_private_data(espos_task_t task, int idx, void *info);
+
+/**
+ * @brief get task private data
+ *
+ * @param task task handle
+ * @param idx  task data index
+ * @param info task private data point
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_task_get_private_data(espos_task_t task, int idx, void **info);
+
+/**
+ * @brief get CPU affinity of task
+ *
+ * @return CPU affinity of task
+ */
+espos_cpu_t espos_task_get_affinity(espos_task_t task);
+
+/**
+ * @brief get ESPOS task priority number
+ *
+ * @return ESPOS task priority number
+ */
+espos_size_t espos_task_prio_num(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ESPOS_TASK_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_time.h

@@ -0,0 +1,73 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESPOS_TIME_H_
+#define _ESPOS_TIME_H_
+
+#include "espos_types.h"
+#include "espos_errno.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * delay or wait for ticks, it is used by mutex, queue,
+ * semaphore, timer and so on
+ */
+/* no delay for ticks, function will return immediately */
+#define ESPOS_NO_DELAY  0u
+/* delay forever, function will never return until event triggers */
+#define ESPOS_MAX_DELAY 0xffffffffu
+
+/**
+ * @brief get tick milliseconds per system tick
+ *
+ * @return current ticks
+ */
+espos_time_t espos_get_tick_per_ms(void);
+
+/**
+ * @brief get current system ticks
+ *
+ * @return current ticks
+ */
+espos_tick_t espos_get_tick_count(void);
+
+/**
+ * @brief transform milliseconds to system ticks
+ *
+ * @param ms milliseconds
+ *
+ * @return system ticks
+ *
+ * @note the function discards the shortage of digits, for example:
+ *       20ms -> 2 ticks ; 21ms -> 2 ticks; 29 -> 2 ticks
+ */
+espos_tick_t espos_ms_to_ticks(espos_time_t ms);
+
+/**
+ * @brief transform system ticks to milliseconds
+ *
+ * @param ticks system ticks
+ *
+ * @return milliseconds
+ */
+espos_time_t espos_ticks_to_ms(espos_tick_t ticks);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ESPOS_TIME_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_timer.h

@@ -0,0 +1,173 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESPOS_TIMER_H_
+#define _ESPOS_TIMER_H_
+
+#include "espos_types.h"
+#include "espos_errno.h"
+#include "espos_time.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* timer just run once after starting it */
+#define ESPOS_TIMER_NO_AUTO_RUN   0
+/* timer run cycle after starting it */
+#define ESPOS_TIMER_AUTO_RUN      (1 << 0)
+
+/* timer configuration command */
+typedef enum espos_timer_cmd {
+    /* configure time's period */
+    ESPOS_TIMER_CHANGE_PERIOD = 0,
+    /* configure time to be "once" */
+    ESPOS_TIMER_CHANGE_ONCE,
+    /* configure time to be "auto" */
+    ESPOS_TIMER_CHANGE_AUTO,
+
+    ESPOS_TIMER_CMD_MAX
+} espos_timer_cmd_t;
+
+/**
+ * @brief create a timer
+ *
+ * @param timer timer handle point
+ * @param name  timer name, if name is NULL, we will use "default_timer" default
+ * @param cb    timer callback function
+ * @param arg   timer entry function inputting parameter
+ * @param period_ticks  timer period ticks
+ * @param opt   timer option
+ *               ESPOS_TIMER_NO_AUTO_RUN : created timer will run once, even if it is started,
+ *               ESPOS_TIMER_AUTO_RUN : created timer will run automatically
+ *
+ * @return the result
+ *             0 : successful
+ *       -ENOMEM : no enough memory
+ *       -EINVAL : input parameter error
+ *       -EINTR  : you do this at interrupt state, and it is not supported
+ *
+ * @note after starting the created timer by "espos_timer_start", it will only run.
+ */
+esp_err_t espos_timer_create(espos_timer_t *timer, const char *name, espos_timer_cb_t cb, void *arg,
+                               espos_tick_t period_ticks, espos_opt_t opt);
+
+/**
+ * @brief start a timer
+ *
+ * @param timer timer handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *       -ECANCELED : failed for some reason depend on low-level OS
+ *
+ * @note after starting the created timer by "espos_timer_start", it will only run
+ */
+esp_err_t espos_timer_start(espos_timer_t timer);
+
+/**
+ * @brief stop a timer
+ *
+ * @param timer timer handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ECANCELED : failed for some reason depend on low-level OS
+ *
+ * @note the timer should be started again, if it is stopped
+ */
+esp_err_t espos_timer_stop(espos_timer_t timer);
+
+/**
+ * @brief configure a timer
+ *
+ * @param timer timer handle
+ * @param opt   timer option command
+ * @param arg   timer parameter
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ECANCELED : failed for some reason depend on low-level OS
+ */
+esp_err_t espos_timer_change(espos_timer_t timer, espos_opt_t opt, void *arg);
+
+/**
+ * @brief configure period of timer
+ *
+ * @param t timer handle
+ * @param a timer period
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ECANCELED : failed for some reason depend on low-level OS
+ */
+#define espos_timer_set_period(t, a) espos_timer_change(t, ESPOS_TIMER_CHANGE_PERIOD, (void *)a)
+
+/**
+ * @brief configure timer to be "once"
+ *
+ * @param t timer handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ECANCELED : failed for some reason depend on low-level OS
+ */
+#define espos_timer_set_once(t) espos_timer_change(t, ESPOS_TIMER_CHANGE_ONCE, NULL)
+
+/**
+ * @brief configure timer to be "auto"
+ *
+ * @param t timer handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ *    -ECANCELED : failed for some reason depend on low-level OS
+ */
+#define espos_timer_set_auto(t) espos_timer_change(t, ESPOS_TIMER_CHANGE_AUTO, NULL)
+
+/**
+ * @brief delete a timer
+ *
+ * @param t timer handle
+ *
+ * @return the result
+ *             0 : successful
+ *       -EACCES : failed to do it with some special reason
+ *       -EINTR  : you do this at interrupt state, and it is not supported
+ */
+esp_err_t espos_timer_del(espos_timer_t timer);
+
+/**
+ * @brief get current timer name point
+ *
+ * @param timer timer handle
+ * @param pname pointing at name's point
+ *
+ * @return the result
+ *             0 : successful
+ *       -EINVAL : input parameter error
+ */
+esp_err_t espos_get_timer_name (espos_timer_t timer, char **pname);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ESPOS_TIMER_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espos/espos_types.h

@@ -0,0 +1,38 @@
+#ifndef _ESPOS_TYPES_H_
+#define _ESPOS_TYPES_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#include "arch/espos_arch.h"
+
+#define ESPOS_OBJ_NONE  0
+
+#ifdef ARCH64
+typedef uint64_t        espos_obj_t;
+#else
+typedef uint32_t        espos_obj_t;
+#endif
+
+typedef espos_obj_t     espos_task_t;
+typedef espos_obj_t     espos_queue_t;
+typedef espos_obj_t     espos_mutex_t;
+typedef espos_obj_t     espos_sem_t;
+typedef espos_obj_t     espos_timer_t;
+typedef espos_obj_t     espos_critical_t;
+
+typedef size_t          espos_size_t;
+typedef size_t          espos_pos_t;
+typedef uint8_t         espos_prio_t;
+typedef uint32_t        espos_opt_t;
+typedef int32_t         espos_cpu_t;
+
+typedef espos_size_t    espos_tick_t;
+typedef espos_size_t    espos_time_t;
+typedef espos_size_t    espos_sem_count_t;
+
+typedef void (*espos_task_entry_t)(void *p);
+typedef void (*espos_timer_cb_t)(espos_timer_t timer, void *arg);
+
+#endif /* _ESPOS_TYPES_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/airkiss.h

@@ -0,0 +1,150 @@
+/*
+ * airkiss.h
+ *
+ *  Created on: 2015-1-26
+ *      Author: peterfan
+ */
+
+#ifndef AIRKISS_H_
+#define AIRKISS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef void* (*airkiss_memset_fn) (void* ptr, int value, unsigned int num);
+typedef void* (*airkiss_memcpy_fn) (void* dst, const void* src, unsigned int num);
+typedef int (*airkiss_memcmp_fn) (const void* ptr1, const void* ptr2, unsigned int num);
+typedef int (*airkiss_printf_fn) (const char* format, ...);
+
+
+
+typedef struct
+{
+	airkiss_memset_fn memset;
+	airkiss_memcpy_fn memcpy;
+	airkiss_memcmp_fn memcmp;
+	airkiss_printf_fn printf;
+
+} airkiss_config_t;
+
+/** \defgroup WiFi_APIs WiFi Related APIs
+  * @brief WiFi APIs
+  */
+
+/** @addtogroup WiFi_APIs
+  * @{
+  */
+
+/** \defgroup AirKiss_APIs AirKiss APIs
+  * @brief AirKiss APIs
+  *
+  * API airkiss_lan_recv and airkiss_lan_pack are provided for the function that AirKiss can detect 
+  * the ESP8266 devices in LAN, more details about AirKiss please refer to WeChat : http://iot.weixin.qq.com.
+  *
+  * Workflow : Create a UDP transmission. When UDP data is received, call API airkiss_lan_recv and 
+  * input the UDP data, if the airkiss_lan_recv returns AIRKISS_LAN_SSDP_REQ, airkiss_lan_pack 
+  * can be called to make a response packet.
+  *
+  */
+
+/** @addtogroup AirKiss_APIs
+  * @{
+  */
+
+/**
+  * @brief       Get the version information of AirKiss lib.
+  *
+  * @attention The lenth of version is unknown
+  *
+  * @param     null.
+  *
+  * @return     the version information of AirKiss lib
+  */
+
+const char* airkiss_version(void);
+
+
+typedef enum
+{
+	/** the length of the data buffer is lack*/
+	AIRKISS_LAN_ERR_OVERFLOW = -5,
+
+	/** Do not support the type of instruction */
+	AIRKISS_LAN_ERR_CMD = -4,
+
+	/** Error reading data package */
+	AIRKISS_LAN_ERR_PAKE = -3,
+
+	/** Error function passing parameters */
+	AIRKISS_LAN_ERR_PARA = -2,
+
+	/** Packet data error */
+	AIRKISS_LAN_ERR_PKG = -1,
+
+	/** Message format is correct */
+	AIRKISS_LAN_CONTINUE = 0,
+
+	/** Find equipment request packet is received */
+	AIRKISS_LAN_SSDP_REQ = 1,
+
+	/** Packet packaging complete */
+	AIRKISS_LAN_PAKE_READY = 2
+
+
+} airkiss_lan_ret_t;
+
+
+typedef enum
+{
+	AIRKISS_LAN_SSDP_REQ_CMD = 0x1,
+	AIRKISS_LAN_SSDP_RESP_CMD = 0x1001,
+	AIRKISS_LAN_SSDP_NOTIFY_CMD = 0x1002
+} airkiss_lan_cmdid_t;
+
+/**
+  * @brief     Parse the UDP packet sent by AirKiss.
+  *
+  * @param     const void* body : the start of the UDP message body data pointer.
+  * @param     unsigned short length : the effective length of data.
+  * @param     const airkiss_config_t* config : input struct airkiss_config_t
+  *
+  * @return    >=0 : succeed (reference airkiss_lan_ret_t)
+  * @return    <0  : error code (reference airkiss_lan_ret_t)
+  */
+
+int airkiss_lan_recv(const void* body, unsigned short length, const airkiss_config_t* config);
+
+
+/**
+  * @brief     Packaging the UDP packet.
+  *
+  * @param     airkiss_lan_cmdid_t ak_lan_cmdid : type of the packet.
+  * @param     void* appid       : Vendor's Wechat public number id, got from WeChat.
+  * @param     void* deviceid   : device model id, got from WeChat.
+  * @param     void* _datain    : user data waiting for packet assembly.
+  * @param     unsigned short inlength  : the lenth of user data.
+  * @param     void* _dataout              : data buffer addr, to store the packet got by _datain packet assembly.
+  * @param     unsigned short* outlength        : the size of data buffer.
+  * @param     const airkiss_config_t* config   : input struct airkiss_config_t
+  *
+  * @return    >=0 : succeed (reference airkiss_lan_ret_t)
+  * @return    <0  : error code (reference airkiss_lan_ret_t)
+  */
+
+int airkiss_lan_pack(airkiss_lan_cmdid_t ak_lan_cmdid, void* appid, void* deviceid, void* _datain, unsigned short inlength, void* _dataout, unsigned short* outlength, const airkiss_config_t* config);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* AIRKISS_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/c_types.h

@@ -0,0 +1,114 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _C_TYPES_H_
+#define _C_TYPES_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint8_t  u8_t;
+typedef int8_t   s8_t;
+typedef uint16_t u16_t;
+typedef int16_t  s16_t;
+typedef uint32_t u32_t;
+typedef int32_t  s32_t;
+
+typedef uint8_t  uint8;
+typedef uint8_t  u8;
+typedef int8_t   sint8;
+typedef int8_t   int8;
+typedef int8_t   s8;
+typedef uint16_t uint16;
+typedef uint16_t u16;
+typedef int16_t  sint16;
+typedef int16_t  s16;
+typedef uint32_t uint32;
+typedef uint32_t u_int;
+typedef uint32_t u32;
+typedef int32_t  sint32;
+typedef int32_t  s32;
+typedef int32_t  int32;
+typedef int64_t  sint64;
+typedef uint64_t uint64;
+typedef uint64_t u64;
+typedef float    real32;
+typedef double   real64;
+
+#define __le16      u16
+
+#define LOCAL       static
+
+#ifndef NULL
+#define NULL        (void *)0
+#endif /* NULL */
+
+/* probably should not put STATUS here */
+typedef enum {
+    OK = 0,
+    FAIL,
+    PENDING,
+    BUSY,
+    CANCEL,
+} STATUS;
+
+#define BIT(nr)     (1UL << (nr))
+
+#define REG_WRITE(_r, _v)       (*(volatile uint32 *)(_r)) = (_v)
+#define REG_READ(_r)            (*(volatile uint32 *)(_r))
+
+#define REG_SET_BIT(_r, _b)     (*(volatile uint32 *)(_r) |= (_b))
+#define REG_CLR_BIT(_r, _b)     (*(volatile uint32 *)(_r) &= ~(_b))
+
+#define __packed            __attribute__((packed))
+#define STORE_ATTR          __attribute__((aligned(4)))
+
+#define SHMEM_ATTR
+
+#ifdef ICACHE_FLASH
+#define ICACHE_FLASH_ATTR __attribute__((section(".irom0.text")))
+#else
+#define ICACHE_FLASH_ATTR
+#endif
+
+#define DMEM_ATTR           __attribute__((section(".bss")))
+#define IRAM_ATTR           __attribute__((section(".text")))
+#define ICACHE_RODATA_ATTR  __attribute__((section(".irom.text")))
+
+#ifndef __cplusplus
+#define BOOL            bool
+#define TRUE            true
+#define FALSE           false
+#endif /* !__cplusplus */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _C_TYPES_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp8266/eagle_soc.h

@@ -0,0 +1,126 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _EAGLE_SOC_H_
+#define _EAGLE_SOC_H_
+
+//Register Bits{{
+#define BIT31   0x80000000
+#define BIT30   0x40000000
+#define BIT29   0x20000000
+#define BIT28   0x10000000
+#define BIT27   0x08000000
+#define BIT26   0x04000000
+#define BIT25   0x02000000
+#define BIT24   0x01000000
+#define BIT23   0x00800000
+#define BIT22   0x00400000
+#define BIT21   0x00200000
+#define BIT20   0x00100000
+#define BIT19   0x00080000
+#define BIT18   0x00040000
+#define BIT17   0x00020000
+#define BIT16   0x00010000
+#define BIT15   0x00008000
+#define BIT14   0x00004000
+#define BIT13   0x00002000
+#define BIT12   0x00001000
+#define BIT11   0x00000800
+#define BIT10   0x00000400
+#define BIT9    0x00000200
+#define BIT8    0x00000100
+#define BIT7    0x00000080
+#define BIT6    0x00000040
+#define BIT5    0x00000020
+#define BIT4    0x00000010
+#define BIT3    0x00000008
+#define BIT2    0x00000004
+#define BIT1    0x00000002
+#define BIT0    0x00000001
+//}}
+
+//Registers Operation {{
+#define ETS_UNCACHED_ADDR(addr) (addr)
+#define ETS_CACHED_ADDR(addr)   (addr)
+
+#define READ_PERI_REG(addr)                             (*((volatile uint32 *)ETS_UNCACHED_ADDR(addr)))
+#define WRITE_PERI_REG(addr, val)                       (*((volatile uint32 *)ETS_UNCACHED_ADDR(addr))) = (uint32)(val)
+#define CLEAR_PERI_REG_MASK(reg, mask)                  WRITE_PERI_REG((reg), (READ_PERI_REG(reg) & (~(mask))))
+#define SET_PERI_REG_MASK(reg, mask)                    WRITE_PERI_REG((reg), (READ_PERI_REG(reg) | (mask)))
+#define GET_PERI_REG_BITS(reg, hipos, lowpos)           ((READ_PERI_REG(reg) >> (lowpos)) & ((1 << ((hipos) - (lowpos) + 1)) - 1))
+#define SET_PERI_REG_BITS(reg, bit_map, value, shift)   (WRITE_PERI_REG((reg), (READ_PERI_REG(reg) & (~((bit_map) << (shift)))) | ((value) << (shift)) ))
+//}}
+
+//Periheral Clock {{
+#define CPU_CLK_FREQ                80 * 1000000       // unit: Hz
+#define APB_CLK_FREQ                CPU_CLK_FREQ
+#define UART_CLK_FREQ               APB_CLK_FREQ
+#define TIMER_CLK_FREQ              (APB_CLK_FREQ >> 8) // divided by 256
+//}}
+
+//Peripheral device base address define{{
+#define PERIPHS_DPORT_BASEADDR      0x3ff00000
+#define PERIPHS_RTC_BASEADDR        0x60000700
+//}}
+
+//DPORT{{
+#define HOST_INF_SEL                (PERIPHS_DPORT_BASEADDR + 0x28)
+#define DPORT_LINK_DEVICE_SEL       0x000000FF
+#define DPORT_LINK_DEVICE_SEL_S     8
+#define DPORT_PERI_IO_SWAP          0x000000FF
+#define DPORT_PERI_IO_SWAP_S        0
+#define PERI_IO_CSPI_OVERLAP        (BIT(7)) // two spi masters on cspi
+#define PERI_IO_HSPI_OVERLAP        (BIT(6)) // two spi masters on hspi
+#define PERI_IO_HSPI_PRIO           (BIT(5)) // hspi is with the higher prior
+#define PERI_IO_UART1_PIN_SWAP      (BIT(3)) // swap uart1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts)
+#define PERI_IO_UART0_PIN_SWAP      (BIT(2)) // swap uart0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts)
+#define PERI_IO_SPI_PORT_SWAP       (BIT(1)) // swap two spi
+#define PERI_IO_UART_PORT_SWAP      (BIT(0)) // swap two uart
+//}}
+
+//Interrupt remap control registers define{{
+#define EDGE_INT_ENABLE_REG         (PERIPHS_DPORT_BASEADDR + 0x04)
+#define TM1_EDGE_INT_ENABLE()       SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
+#define TM1_EDGE_INT_DISABLE()      CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
+//}}
+
+//RTC reg {{
+#define REG_RTC_BASE                PERIPHS_RTC_BASEADDR
+
+#define RTC_SLP_VAL                     (REG_RTC_BASE + 0x004) // the target value of RTC_COUNTER for wakeup from light-sleep/deep-sleep
+#define RTC_SLP_CNT_VAL                 (REG_RTC_BASE + 0x01C) // the current value of RTC_COUNTER
+
+#define RTC_SCRATCH0                    (REG_RTC_BASE + 0x030) // the register for software to save some values for watchdog reset
+#define RTC_SCRATCH1                    (REG_RTC_BASE + 0x034) // the register for software to save some values for watchdog reset
+#define RTC_SCRATCH2                    (REG_RTC_BASE + 0x038) // the register for software to save some values for watchdog reset
+#define RTC_SCRATCH3                    (REG_RTC_BASE + 0x03C) // the register for software to save some values for watchdog reset
+
+#define RTC_GPIO_OUT                    (REG_RTC_BASE + 0x068) // used by gpio16
+#define RTC_GPIO_ENABLE                 (REG_RTC_BASE + 0x074)
+#define RTC_GPIO_IN_DATA                (REG_RTC_BASE + 0x08C)
+#define RTC_GPIO_CONF                   (REG_RTC_BASE + 0x090)
+#define PAD_XPD_DCDC_CONF               (REG_RTC_BASE + 0x0A0)
+//}}
+
+#endif //_EAGLE_SOC_H_

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp8266/esp8266.h

@@ -0,0 +1,37 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP8266_H__
+#define __ESP8266_H__
+
+#include "ets_sys.h"
+#include "eagle_soc.h"
+#include "gpio_register.h"
+#include "pin_mux_register.h"
+#include "spi_register.h"
+#include "timer_register.h"
+#include "uart_register.h"
+
+#endif
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp8266/ets_sys.h

@@ -0,0 +1,63 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ETS_SYS_H__
+#define __ETS_SYS_H__
+
+/* interrupt related */
+#define ETS_SPI_INUM        2
+#define ETS_GPIO_INUM       4
+#define ETS_UART_INUM       5
+#define ETS_MAX_INUM        6
+#define ETS_SOFT_INUM       7
+#define ETS_WDT_INUM        8
+#define ETS_FRC_TIMER1_INUM 9
+
+extern char NMIIrqIsOn;
+extern uint32 WDEV_INTEREST_EVENT;
+
+#define INT_ENA_WDEV        0x3ff20c18
+#define WDEV_TSF0_REACH_INT (BIT(27))
+
+#define ETS_INTR_LOCK() do {    \
+    if (NMIIrqIsOn == 0) { \
+        vPortEnterCritical();   \
+        char m = 10;    \
+        do {    \
+            REG_WRITE(INT_ENA_WDEV, 0); \
+            m = 10; \
+            for (; m > 0; m--) {}   \
+            REG_WRITE(INT_ENA_WDEV, WDEV_TSF0_REACH_INT);   \
+        } while(0);  \
+    }   \
+    } while(0)
+
+#define ETS_INTR_UNLOCK()   do {    \
+    if (NMIIrqIsOn == 0) { \
+        REG_WRITE(INT_ENA_WDEV, WDEV_INTEREST_EVENT);   \
+        vPortExitCritical(); \
+    }   \
+    } while(0)
+
+#endif /* _ETS_SYS_H */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp8266/gpio_register.h

@@ -0,0 +1,338 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _GPIO_REGISTER_H_
+#define _GPIO_REGISTER_H_
+
+#define PERIPHS_GPIO_BASEADDR               0x60000300
+
+#define GPIO_OUT_ADDRESS                    0x00
+#define GPIO_BT_SEL                             0x0000ffff
+#define GPIO_BT_SEL_S                           16
+#define GPIO_OUT_DATA                           0x0000ffff
+#define GPIO_OUT_DATA_S                         0
+
+#define GPIO_OUT_W1TS_ADDRESS               0x04
+#define GPIO_OUT_DATA_W1TS                      0x0000ffff
+#define GPIO_OUT_DATA_W1TS_S                    0
+
+#define GPIO_OUT_W1TC_ADDRESS               0x08
+#define GPIO_OUT_DATA_W1TC                      0x0000ffff
+#define GPIO_OUT_DATA_W1TC_S                    0
+#define GPIO_OUT_DATA_MASK                      0x0000ffff
+
+#define GPIO_ENABLE_ADDRESS                 0x0c
+#define GPIO_SDIO_SEL                           0x0000003f
+#define GPIO_SDIO_SEL_S                         16
+#define GPIO_ENABLE_DATA                        0x0000ffff
+#define GPIO_ENABLE_DATA_S                      0
+
+#define GPIO_ENABLE_W1TS_ADDRESS            0x10
+#define GPIO_ENABLE_DATA_W1TS                   0x0000ffff
+#define GPIO_ENABLE_DATA_W1TS_s                 0
+
+#define GPIO_ENABLE_W1TC_ADDRESS            0x14
+#define GPIO_ENABLE_DATA_W1TC                   0x0000ffff
+#define GPIO_ENABLE_DATA_W1TC_S                 0
+#define GPIO_ENABLE_DATA_DATA_MASK              0x0000ffff
+
+#define GPIO_IN_ADDRESS                     0x18
+#define GPIO_STRAPPING                          0x0000ffff
+#define GPIO_STRAPPING_S                        16
+#define GPIO_IN_DATA                            0x0000ffff
+#define GPIO_IN_DATA_S                          0
+
+#define GPIO_STATUS_ADDRESS                 0x1c
+#define GPIO_STATUS_INTERRUPT                   0x0000ffff
+#define GPIO_STATUS_INTERRUPT_S                 0
+
+#define GPIO_STATUS_W1TS_ADDRESS            0x20
+#define GPIO_STATUS_INTERRUPT_W1TS              0x0000ffff
+#define GPIO_STATUS_INTERRUPT_W1TS_S            0
+
+#define GPIO_STATUS_W1TC_ADDRESS            0x24
+#define GPIO_STATUS_INTERRUPT_W1TC              0x0000ffff
+#define GPIO_STATUS_INTERRUPT_W1TC_S            0
+#define GPIO_STATUS_INTERRUPT_DATA_MASK         0x0000ffff
+
+//Region1: used for gpio config for GPIO_PIN0_ADDRESS~GPIO_PIN15_ADDRESS
+#define GPIO_ID_PIN0                        0
+#define GPIO_ID_PIN(n)                      (GPIO_ID_PIN0+(n))
+#define GPIO_LAST_REGISTER_ID               GPIO_ID_PIN(15)
+#define GPIO_ID_NONE                        0xffffffff
+#define GPIO_PIN_COUNT                      16
+
+#define GPIO_PIN_CONFIG_MSB                 12
+#define GPIO_PIN_CONFIG_LSB                 11
+#define GPIO_PIN_CONFIG_MASK                (0x00000003<<GPIO_PIN_CONFIG_LSB)
+#define GPIO_PIN_CONFIG_GET(x)              (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
+#define GPIO_PIN_CONFIG_SET(x)              (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
+
+#define GPIO_WAKEUP_ENABLE                  1
+#define GPIO_WAKEUP_DISABLE                 (~GPIO_WAKEUP_ENABLE)
+#define GPIO_PIN_WAKEUP_ENABLE_MSB          10
+#define GPIO_PIN_WAKEUP_ENABLE_LSB          10
+#define GPIO_PIN_WAKEUP_ENABLE_MASK         (0x00000001<<GPIO_PIN_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN_WAKEUP_ENABLE_GET(x)       (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
+#define GPIO_PIN_WAKEUP_ENABLE_SET(x)       (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
+
+#define GPIO_PIN_INT_TYPE_MSB               9
+#define GPIO_PIN_INT_TYPE_LSB               7
+#define GPIO_PIN_INT_TYPE_MASK              (0x00000007<<GPIO_PIN_INT_TYPE_LSB)
+#define GPIO_PIN_INT_TYPE_GET(x)            (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
+#define GPIO_PIN_INT_TYPE_SET(x)            (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
+
+#define GPIO_PAD_DRIVER_ENABLE              1
+#define GPIO_PAD_DRIVER_DISABLE             (~GPIO_PAD_DRIVER_ENABLE)
+#define GPIO_PIN_DRIVER_MSB                 2
+#define GPIO_PIN_DRIVER_LSB                 2
+#define GPIO_PIN_DRIVER_MASK                (0x00000001<<GPIO_PIN_DRIVER_LSB)
+#define GPIO_PIN_DRIVER_GET(x)              (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
+#define GPIO_PIN_PAD_DRIVER_SET(x)          (((x) << GPIO_PIN_DRIVER_LSB) & GPIO_PIN_DRIVER_MASK)
+
+#define GPIO_PIN_SOURCE_MSB                 0
+#define GPIO_PIN_SOURCE_LSB                 0
+#define GPIO_PIN_SOURCE_MASK                (0x00000001<<GPIO_PIN_SOURCE_LSB)
+#define GPIO_PIN_SOURCE_GET(x)              (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
+#define GPIO_PIN_SOURCE_SET(x)              (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK)
+//end of region1
+
+#define GPIO_PIN0_ADDRESS                   0x28
+#define GPIO_PIN0_CONFIG                        0x00000003
+#define GPIO_PIN0_CONFIG_S                      11
+#define GPIO_PIN0_WAKEUP_ENABLE                 BIT10
+#define GPIO_PIN0_WAKEUP_ENABLE_S               10
+#define GPIO_PIN0_INT_TYPE                      0x00000007
+#define GPIO_PIN0_INT_TYPE_S                    7
+#define GPIO_PIN0_DRIVER                        BIT2
+#define GPIO_PIN0_DRIVER_S                      2
+#define GPIO_PIN0_SOURCE                        BIT0
+#define GPIO_PIN0_SOURCE_S                      0
+
+#define GPIO_PIN1_ADDRESS                   0x2c
+#define GPIO_PIN1_CONFIG                        0x00000003
+#define GPIO_PIN1_CONFIG_S                      11
+#define GPIO_PIN1_WAKEUP_ENABLE                 BIT10
+#define GPIO_PIN1_WAKEUP_ENABLE_S               10
+#define GPIO_PIN1_INT_TYPE                      0x00000007
+#define GPIO_PIN1_INT_TYPE_S                    7
+#define GPIO_PIN1_DRIVER                        BIT2
+#define GPIO_PIN1_DRIVER_S                      2
+#define GPIO_PIN1_SOURCE                        BIT0
+#define GPIO_PIN1_SOURCE_S                      0
+
+#define GPIO_PIN2_ADDRESS                   0x30
+#define GPIO_PIN2_CONFIG                        0x00000003
+#define GPIO_PIN2_CONFIG_S                      11
+#define GPIO_PIN2_WAKEUP_ENABLE                 BIT10
+#define GPIO_PIN2_WAKEUP_ENABLE_S               10
+#define GPIO_PIN2_INT_TYPE                      0x00000007
+#define GPIO_PIN2_INT_TYPE_S                    7
+#define GPIO_PIN2_DRIVER                        BIT2
+#define GPIO_PIN2_DRIVER_S                      2
+#define GPIO_PIN2_SOURCE                        BIT0
+#define GPIO_PIN2_SOURCE_S                      0
+
+#define GPIO_PIN3_ADDRESS                   0x34
+#define GPIO_PIN3_CONFIG                        0x00000003
+#define GPIO_PIN3_CONFIG_S                      11
+#define GPIO_PIN3_WAKEUP_ENABLE                 BIT10
+#define GPIO_PIN3_WAKEUP_ENABLE_S               10
+#define GPIO_PIN3_INT_TYPE                      0x00000007
+#define GPIO_PIN3_INT_TYPE_S                    7
+#define GPIO_PIN3_DRIVER                        BIT2
+#define GPIO_PIN3_DRIVER_S                      2
+#define GPIO_PIN3_SOURCE                        BIT0
+#define GPIO_PIN3_SOURCE_S                      0
+
+#define GPIO_PIN4_ADDRESS                   0x38
+#define GPIO_PIN4_CONFIG                        0x00000003
+#define GPIO_PIN4_CONFIG_S                      11
+#define GPIO_PIN4_WAKEUP_ENABLE                 BIT10
+#define GPIO_PIN4_WAKEUP_ENABLE_S               10
+#define GPIO_PIN4_INT_TYPE                      0x00000007
+#define GPIO_PIN4_INT_TYPE_S                    7
+#define GPIO_PIN4_DRIVER                        BIT2
+#define GPIO_PIN4_DRIVER_S                      2
+#define GPIO_PIN4_SOURCE                        BIT0
+#define GPIO_PIN4_SOURCE_S                      0
+
+#define GPIO_PIN5_ADDRESS                   0x3c
+#define GPIO_PIN5_CONFIG                        0x00000003
+#define GPIO_PIN5_CONFIG_S                      11
+#define GPIO_PIN5_WAKEUP_ENABLE                 BIT10
+#define GPIO_PIN5_WAKEUP_ENABLE_S               10
+#define GPIO_PIN5_INT_TYPE                      0x00000007
+#define GPIO_PIN5_INT_TYPE_S                    7
+#define GPIO_PIN5_DRIVER                        BIT2
+#define GPIO_PIN5_DRIVER_S                      2
+#define GPIO_PIN5_SOURCE                        BIT0
+#define GPIO_PIN5_SOURCE_S                      0
+
+#define GPIO_PIN6_ADDRESS                   0x40
+#define GPIO_PIN6_CONFIG                        0x00000003
+#define GPIO_PIN6_CONFIG_S                      11
+#define GPIO_PIN6_WAKEUP_ENABLE                 BIT10
+#define GPIO_PIN6_WAKEUP_ENABLE_S               10
+#define GPIO_PIN6_INT_TYPE                      0x00000007
+#define GPIO_PIN6_INT_TYPE_S                    7
+#define GPIO_PIN6_DRIVER                        BIT2
+#define GPIO_PIN6_DRIVER_S                      2
+#define GPIO_PIN6_SOURCE                        BIT0
+#define GPIO_PIN6_SOURCE_S                      0
+
+#define GPIO_PIN7_ADDRESS                   0x44
+#define GPIO_PIN7_CONFIG                        0x00000003
+#define GPIO_PIN7_CONFIG_S                      11
+#define GPIO_PIN7_WAKEUP_ENABLE                 BIT10
+#define GPIO_PIN7_WAKEUP_ENABLE_S               10
+#define GPIO_PIN7_INT_TYPE                      0x00000007
+#define GPIO_PIN7_INT_TYPE_S                    7
+#define GPIO_PIN7_DRIVER                        BIT2
+#define GPIO_PIN7_DRIVER_S                      2
+#define GPIO_PIN7_SOURCE                        BIT0
+#define GPIO_PIN7_SOURCE_S                      0
+
+#define GPIO_PIN8_ADDRESS                   0x48
+#define GPIO_PIN8_CONFIG                        0x00000003
+#define GPIO_PIN8_CONFIG_S                      11
+#define GPIO_PIN8_WAKEUP_ENABLE                 BIT10
+#define GPIO_PIN8_WAKEUP_ENABLE_S               10
+#define GPIO_PIN8_INT_TYPE                      0x00000007
+#define GPIO_PIN8_INT_TYPE_S                    7
+#define GPIO_PIN8_DRIVER                        BIT2
+#define GPIO_PIN8_DRIVER_S                      2
+#define GPIO_PIN8_SOURCE                        BIT0
+#define GPIO_PIN8_SOURCE_S                      0
+
+#define GPIO_PIN9_ADDRESS                   0x4c
+#define GPIO_PIN9_CONFIG                        0x00000003
+#define GPIO_PIN9_CONFIG_S                      11
+#define GPIO_PIN9_WAKEUP_ENABLE                 BIT10
+#define GPIO_PIN9_WAKEUP_ENABLE_S               10
+#define GPIO_PIN9_INT_TYPE                      0x00000007
+#define GPIO_PIN9_INT_TYPE_S                    7
+#define GPIO_PIN9_DRIVER                        BIT2
+#define GPIO_PIN9_DRIVER_S                      2
+#define GPIO_PIN9_SOURCE                        BIT0
+#define GPIO_PIN9_SOURCE_S                      0
+
+#define GPIO_PIN10_ADDRESS                  0x50
+#define GPIO_PIN10_CONFIG                       0x00000003
+#define GPIO_PIN10_CONFIG_S                     11
+#define GPIO_PIN10_WAKEUP_ENABLE                BIT10
+#define GPIO_PIN10_WAKEUP_ENABLE_S              10
+#define GPIO_PIN10_INT_TYPE                     0x00000007
+#define GPIO_PIN10_INT_TYPE_S                   7
+#define GPIO_PIN10_DRIVER                       BIT2
+#define GPIO_PIN10_DRIVER_S                     2
+#define GPIO_PIN10_SOURCE                       BIT0
+#define GPIO_PIN10_SOURCE_S                     0
+
+#define GPIO_PIN11_ADDRESS                  0x54
+#define GPIO_PIN11_CONFIG                       0x00000003
+#define GPIO_PIN11_CONFIG_S                     11
+#define GPIO_PIN11_WAKEUP_ENABLE                BIT10
+#define GPIO_PIN11_WAKEUP_ENABLE_S              10
+#define GPIO_PIN11_INT_TYPE                     0x00000007
+#define GPIO_PIN11_INT_TYPE_S                   7
+#define GPIO_PIN11_DRIVER                       BIT2
+#define GPIO_PIN11_DRIVER_S                     2
+#define GPIO_PIN11_SOURCE                       BIT0
+#define GPIO_PIN11_SOURCE_S                     0
+
+#define GPIO_PIN12_ADDRESS                  0x58
+#define GPIO_PIN12_CONFIG                       0x00000003
+#define GPIO_PIN12_CONFIG_S                     11
+#define GPIO_PIN12_WAKEUP_ENABLE                BIT10
+#define GPIO_PIN12_WAKEUP_ENABLE_S              10
+#define GPIO_PIN12_INT_TYPE                     0x00000007
+#define GPIO_PIN12_INT_TYPE_S                   7
+#define GPIO_PIN12_DRIVER                       BIT2
+#define GPIO_PIN12_DRIVER_S                     2
+#define GPIO_PIN12_SOURCE                       BIT0
+#define GPIO_PIN12_SOURCE_S                     0
+
+#define GPIO_PIN13_ADDRESS                  0x5c
+#define GPIO_PIN13_CONFIG                       0x00000003
+#define GPIO_PIN13_CONFIG_S                     11
+#define GPIO_PIN13_WAKEUP_ENABLE                BIT10
+#define GPIO_PIN13_WAKEUP_ENABLE_S              10
+#define GPIO_PIN13_INT_TYPE                     0x00000007
+#define GPIO_PIN13_INT_TYPE_S                   7
+#define GPIO_PIN13_DRIVER                       BIT2
+#define GPIO_PIN13_DRIVER_S                     2
+#define GPIO_PIN13_SOURCE                       BIT0
+#define GPIO_PIN13_SOURCE_S                     0
+
+#define GPIO_PIN14_ADDRESS                  0x60
+#define GPIO_PIN14_CONFIG                       0x00000003
+#define GPIO_PIN14_CONFIG_S                     11
+#define GPIO_PIN14_WAKEUP_ENABLE                BIT10
+#define GPIO_PIN14_WAKEUP_ENABLE_S              10
+#define GPIO_PIN14_INT_TYPE                     0x00000007
+#define GPIO_PIN14_INT_TYPE_S                   7
+#define GPIO_PIN14_DRIVER                       BIT2
+#define GPIO_PIN14_DRIVER_S                     2
+#define GPIO_PIN14_SOURCE                       BIT0
+#define GPIO_PIN14_SOURCE_S                     0
+
+#define GPIO_PIN15_ADDRESS                  0x64
+#define GPIO_PIN15_CONFIG                       0x00000003
+#define GPIO_PIN15_CONFIG_S                     11
+#define GPIO_PIN15_WAKEUP_ENABLE                BIT10
+#define GPIO_PIN15_WAKEUP_ENABLE_S              10
+#define GPIO_PIN15_INT_TYPE                     0x00000007
+#define GPIO_PIN15_INT_TYPE_S                   7
+#define GPIO_PIN15_DRIVER                       BIT2
+#define GPIO_PIN15_DRIVER_S                     2
+#define GPIO_PIN15_SOURCE                       BIT0
+#define GPIO_PIN15_SOURCE_S                     0
+
+#define GPIO_SIGMA_DELTA_ADDRESS            0x68
+#define SIGMA_DELTA_ENABLE                      BIT16
+#define SIGMA_DELTA_ENABLE_S                    16
+#define SIGMA_DELTA_PRESCALAR                   0x000000ff
+#define SIGMA_DELTA_PRESCALAR_S                 8
+#define SIGMA_DELTA_TARGET                      0x000000ff
+#define SIGMA_DELTA_TARGET_S                    0
+
+#define GPIO_RTC_CALIB_SYNC_ADDRESS         0x6c
+#define RTC_CALIB_START                         BIT31
+#define RTC_CALIB_START_S                       31
+#define RTC_PERIOD_NUM                          0x000003ff
+#define RTC_PERIOD_NUM_S                        0
+
+#define GPIO_RTC_CALIB_VALUE_ADDRESS        0x70
+#define RTC_CALIB_RDY                           BIT31
+#define RTC_CALIB_RDY_S                         31
+#define RTC_CALIB_RDY_REAL                      BIT30
+#define RTC_CALIB_RDY_REAL_S                    30
+#define RTC_CALIB_VALUE                         0x000fffff
+#define RTC_CALIB_VALUE_S                       0
+
+#define GPIO_REG_READ(reg)                  READ_PERI_REG(PERIPHS_GPIO_BASEADDR + reg)
+#define GPIO_REG_WRITE(reg, val)            WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + reg, val)
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp8266/pin_mux_register.h

@@ -0,0 +1,152 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+#include "eagle_soc.h"
+#define PERIPHS_IO_MUX                  0x60000800
+
+#define PERIPHS_IO_MUX_FUNC             0x13
+#define PERIPHS_IO_MUX_FUNC_S           4
+#define PERIPHS_IO_MUX_PULLUP           BIT7
+#define PERIPHS_IO_MUX_PULLDWN          BIT6
+#define PERIPHS_IO_MUX_SLEEP_PULLUP     BIT3
+#define PERIPHS_IO_MUX_SLEEP_PULLDWN    BIT2
+#define PERIPHS_IO_MUX_SLEEP_OE         BIT1
+#define PERIPHS_IO_MUX_OE               BIT0
+
+#define PERIPHS_IO_MUX_CONF_U           (PERIPHS_IO_MUX + 0x00)
+#define SPI0_CLK_EQU_SYS_CLK                BIT8
+#define SPI1_CLK_EQU_SYS_CLK                BIT9
+
+#define PERIPHS_IO_MUX_MTDI_U           (PERIPHS_IO_MUX + 0x04)
+#define FUNC_MTDI                           0
+#define FUNC_I2SI_DATA                      1
+#define FUNC_HSPIQ_MISO                     2
+#define FUNC_GPIO12                         3
+#define FUNC_UART0_DTR                      4
+
+#define PERIPHS_IO_MUX_MTCK_U           (PERIPHS_IO_MUX + 0x08)
+#define FUNC_MTCK                            0
+#define FUNC_I2SI_BCK                        1
+#define FUNC_HSPID_MOSI                      2
+#define FUNC_GPIO13                          3
+#define FUNC_UART0_CTS                       4
+
+#define PERIPHS_IO_MUX_MTMS_U           (PERIPHS_IO_MUX + 0x0C)
+#define FUNC_MTMS                           0
+#define FUNC_I2SI_WS                        1
+#define FUNC_HSPI_CLK                       2
+#define FUNC_GPIO14                         3
+#define FUNC_UART0_DSR                      4
+
+#define PERIPHS_IO_MUX_MTDO_U           (PERIPHS_IO_MUX + 0x10)
+#define FUNC_MTDO                           0
+#define FUNC_I2SO_BCK                       1
+#define FUNC_HSPI_CS0                       2
+#define FUNC_GPIO15                         3
+#define FUNC_U0RTS                          4
+#define FUNC_UART0_RTS                      4
+
+#define PERIPHS_IO_MUX_U0RXD_U          (PERIPHS_IO_MUX + 0x14)
+#define FUNC_U0RXD                          0
+#define FUNC_I2SO_DATA                      1
+#define FUNC_GPIO3                          3
+#define FUNC_CLK_XTAL_BK                    4
+
+#define PERIPHS_IO_MUX_U0TXD_U          (PERIPHS_IO_MUX + 0x18)
+#define FUNC_U0TXD                          0
+#define FUNC_SPICS1                         1
+#define FUNC_GPIO1                          3
+#define FUNC_CLK_RTC_BK                     4
+
+#define PERIPHS_IO_MUX_SD_CLK_U         (PERIPHS_IO_MUX + 0x1c)
+#define FUNC_SDCLK                          0
+#define FUNC_SPICLK                         1
+#define FUNC_GPIO6                          3
+#define UART1_CTS                           4
+
+#define PERIPHS_IO_MUX_SD_DATA0_U       (PERIPHS_IO_MUX + 0x20)
+#define FUNC_SDDATA0                        0
+#define FUNC_SPIQ_MISO                      1
+#define FUNC_GPIO7                          3
+#define FUNC_U1TXD                          4
+#define FUNC_UART1_TXD                      4
+
+#define PERIPHS_IO_MUX_SD_DATA1_U       (PERIPHS_IO_MUX + 0x24)
+#define FUNC_SDDATA1                        0
+#define FUNC_SPID_MOSI                      1
+#define FUNC_GPIO8                          3
+#define FUNC_U1RXD                          4
+#define FUNC_UART1_RXD                      4
+
+#define PERIPHS_IO_MUX_SD_DATA2_U       (PERIPHS_IO_MUX + 0x28)
+#define FUNC_SDDATA2                        0
+#define FUNC_SPIHD                          1
+#define FUNC_GPIO9                          3
+#define UFNC_HSPIHD                         4
+
+#define PERIPHS_IO_MUX_SD_DATA3_U       (PERIPHS_IO_MUX + 0x2c)
+#define FUNC_SDDATA3                        0
+#define FUNC_SPIWP                          1
+#define FUNC_GPIO10                         3
+#define FUNC_HSPIWP                         4
+
+#define PERIPHS_IO_MUX_SD_CMD_U         (PERIPHS_IO_MUX + 0x30)
+#define FUNC_SDCMD                          0
+#define FUNC_SPICS0                         1
+#define FUNC_GPIO11                         3
+#define U1RTS                               4
+#define UART1_RTS                           4
+
+#define PERIPHS_IO_MUX_GPIO0_U          (PERIPHS_IO_MUX + 0x34)
+#define FUNC_GPIO0                          0
+#define FUNC_SPICS2                         1
+#define FUNC_CLK_OUT                        4
+
+#define PERIPHS_IO_MUX_GPIO2_U          (PERIPHS_IO_MUX + 0x38)
+#define FUNC_GPIO2                          0
+#define FUNC_I2SO_WS                        1
+#define FUNC_U1TXD_BK                       2
+#define FUNC_UART1_TXD_BK                   2
+#define FUNC_U0TXD_BK                       4
+#define FUNC_UART0_TXD_BK                   4
+
+#define PERIPHS_IO_MUX_GPIO4_U          (PERIPHS_IO_MUX + 0x3C)
+#define FUNC_GPIO4                          0
+#define FUNC_CLK_XTAL                       1
+
+#define PERIPHS_IO_MUX_GPIO5_U          (PERIPHS_IO_MUX + 0x40)
+#define FUNC_GPIO5                          0
+#define FUNC_CLK_RTC                        1
+
+#define PIN_PULLUP_DIS(PIN_NAME)         CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP)
+#define PIN_PULLUP_EN(PIN_NAME)          SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP)
+
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)  do { \
+        CLEAR_PERI_REG_MASK(PIN_NAME, (PERIPHS_IO_MUX_FUNC << PERIPHS_IO_MUX_FUNC_S)); \
+        SET_PERI_REG_MASK(PIN_NAME, (((FUNC & BIT2) << 2) | (FUNC & 0x3)) << PERIPHS_IO_MUX_FUNC_S); \
+    } while (0)
+
+#endif //_PIN_MUX_H_

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp8266/spi_register.h

@@ -0,0 +1,193 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef SPI_REGISTER_H_INCLUDED
+#define SPI_REGISTER_H_INCLUDED
+
+#define REG_SPI_BASE(i)             (0x60000200 - i*0x100)
+
+#define SPI_CMD(i)                  (REG_SPI_BASE(i) + 0x0)
+#define SPI_USR                         (BIT(18))
+
+#define SPI_ADDR(i)                 (REG_SPI_BASE(i) + 0x4)
+
+#define SPI_CTRL(i)                 (REG_SPI_BASE(i) + 0x8)
+#define SPI_WR_BIT_ORDER                (BIT(26))
+#define SPI_RD_BIT_ORDER                (BIT(25))
+#define SPI_QIO_MODE                    (BIT(24))
+#define SPI_DIO_MODE                    (BIT(23))
+#define SPI_QOUT_MODE                   (BIT(20))
+#define SPI_DOUT_MODE                   (BIT(14))
+#define SPI_FASTRD_MODE                 (BIT(13))
+
+#define SPI_RD_STATUS(i)             (REG_SPI_BASE(i) + 0x10)
+
+#define SPI_CTRL2(i)                 (REG_SPI_BASE(i) + 0x14)
+#define SPI_CS_DELAY_NUM                0x0000000F
+#define SPI_CS_DELAY_NUM_S              28
+#define SPI_CS_DELAY_MODE               0x00000003
+#define SPI_CS_DELAY_MODE_S             26
+#define SPI_MOSI_DELAY_NUM              0x00000007
+#define SPI_MOSI_DELAY_NUM_S            23
+#define SPI_MOSI_DELAY_MODE             0x00000003
+#define SPI_MOSI_DELAY_MODE_S           21
+#define SPI_MISO_DELAY_NUM              0x00000007
+#define SPI_MISO_DELAY_NUM_S            18
+#define SPI_MISO_DELAY_MODE             0x00000003
+#define SPI_MISO_DELAY_MODE_S           16
+
+#define SPI_CLOCK(i)                (REG_SPI_BASE(i) + 0x18)
+#define SPI_CLK_EQU_SYSCLK              (BIT(31))
+#define SPI_CLKDIV_PRE                  0x00001FFF
+#define SPI_CLKDIV_PRE_S                18
+#define SPI_CLKCNT_N                    0x0000003F
+#define SPI_CLKCNT_N_S                  12
+#define SPI_CLKCNT_H                    0x0000003F
+#define SPI_CLKCNT_H_S                  6
+#define SPI_CLKCNT_L                    0x0000003F
+#define SPI_CLKCNT_L_S                  0
+
+#define SPI_USER(i)                 (REG_SPI_BASE(i) + 0x1C)
+#define SPI_USR_COMMAND                 (BIT(31))
+#define SPI_USR_ADDR                    (BIT(30))
+#define SPI_USR_DUMMY                   (BIT(29))
+#define SPI_USR_MISO                    (BIT(28))
+#define SPI_USR_MOSI                    (BIT(27))
+#define SPI_USR_MOSI_HIGHPART           (BIT(25))
+#define SPI_USR_MISO_HIGHPART           (BIT(24))
+#define SPI_SIO                         (BIT(16))
+#define SPI_FWRITE_QIO                  (BIT(15))
+#define SPI_FWRITE_DIO                  (BIT(14))
+#define SPI_FWRITE_QUAD                 (BIT(13))
+#define SPI_FWRITE_DUAL                 (BIT(12))
+#define SPI_WR_BYTE_ORDER               (BIT(11))
+#define SPI_RD_BYTE_ORDER               (BIT(10))
+#define SPI_CK_OUT_EDGE                 (BIT(7))
+#define SPI_CK_I_EDGE                   (BIT(6))
+#define SPI_CS_SETUP                    (BIT(5))
+#define SPI_CS_HOLD                     (BIT(4))
+#define SPI_FLASH_MODE                  (BIT(2))
+
+#define SPI_USER1(i)                (REG_SPI_BASE(i) + 0x20)
+#define SPI_USR_ADDR_BITLEN             0x0000003F
+#define SPI_USR_ADDR_BITLEN_S           26
+#define SPI_USR_MOSI_BITLEN             0x000001FF
+#define SPI_USR_MOSI_BITLEN_S           17
+#define SPI_USR_MISO_BITLEN             0x000001FF
+#define SPI_USR_MISO_BITLEN_S           8
+#define SPI_USR_DUMMY_CYCLELEN          0x000000FF
+#define SPI_USR_DUMMY_CYCLELEN_S        0
+
+#define SPI_USER2(i)                (REG_SPI_BASE(i) + 0x24)
+#define SPI_USR_COMMAND_BITLEN          0x0000000F
+#define SPI_USR_COMMAND_BITLEN_S        28
+#define SPI_USR_COMMAND_VALUE           0x0000FFFF
+#define SPI_USR_COMMAND_VALUE_S         0
+
+#define SPI_WR_STATUS(i)            (REG_SPI_BASE(i) + 0x28)
+
+#define SPI_PIN(i)                  (REG_SPI_BASE(i) + 0x2C)
+#define SPI_CS2_DIS                     (BIT(2))
+#define SPI_CS1_DIS                     (BIT(1))
+#define SPI_CS0_DIS                     (BIT(0))
+
+#define SPI_SLAVE(i)                (REG_SPI_BASE(i)  + 0x30)
+#define SPI_SYNC_RESET                  (BIT(31))
+#define SPI_SLAVE_MODE                  (BIT(30))
+#define SPI_SLV_WR_RD_BUF_EN            (BIT(29))
+#define SPI_SLV_WR_RD_STA_EN            (BIT(28))
+#define SPI_SLV_CMD_DEFINE              (BIT(27))
+#define SPI_TRANS_CNT                   0x0000000F
+#define SPI_TRANS_CNT_S                 23
+#define SPI_TRANS_DONE_EN               (BIT(9))
+#define SPI_SLV_WR_STA_DONE_EN          (BIT(8))
+#define SPI_SLV_RD_STA_DONE_EN          (BIT(7))
+#define SPI_SLV_WR_BUF_DONE_EN          (BIT(6))
+#define SPI_SLV_RD_BUF_DONE_EN          (BIT(5))
+#define SLV_SPI_INT_EN                  0x0000001f
+#define SLV_SPI_INT_EN_S                5
+#define SPI_TRANS_DONE                  (BIT(4))
+#define SPI_SLV_WR_STA_DONE             (BIT(3))
+#define SPI_SLV_RD_STA_DONE             (BIT(2))
+#define SPI_SLV_WR_BUF_DONE             (BIT(1))
+#define SPI_SLV_RD_BUF_DONE             (BIT(0))
+
+#define SPI_SLAVE1(i)               (REG_SPI_BASE(i) + 0x34)
+#define SPI_SLV_STATUS_BITLEN           0x0000001F
+#define SPI_SLV_STATUS_BITLEN_S         27
+#define SPI_SLV_BUF_BITLEN              0x000001FF
+#define SPI_SLV_BUF_BITLEN_S            16
+#define SPI_SLV_RD_ADDR_BITLEN          0x0000003F
+#define SPI_SLV_RD_ADDR_BITLEN_S        10
+#define SPI_SLV_WR_ADDR_BITLEN          0x0000003F
+#define SPI_SLV_WR_ADDR_BITLEN_S        4
+#define SPI_SLV_WRSTA_DUMMY_EN          (BIT(3))
+#define SPI_SLV_RDSTA_DUMMY_EN          (BIT(2))
+#define SPI_SLV_WRBUF_DUMMY_EN          (BIT(1))
+#define SPI_SLV_RDBUF_DUMMY_EN          (BIT(0))
+
+#define SPI_SLAVE2(i)               (REG_SPI_BASE(i) + 0x38)
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN    0x000000FF
+#define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S  24
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN    0x000000FF
+#define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S  16
+#define SPI_SLV_WRSTR_DUMMY_CYCLELEN    0x000000FF
+#define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S  8
+#define SPI_SLV_RDSTR_DUMMY_CYCLELEN    0x000000FF
+#define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S  0
+
+#define SPI_SLAVE3(i)               (REG_SPI_BASE(i) + 0x3C)
+#define SPI_SLV_WRSTA_CMD_VALUE         0x000000FF
+#define SPI_SLV_WRSTA_CMD_VALUE_S       24
+#define SPI_SLV_RDSTA_CMD_VALUE         0x000000FF
+#define SPI_SLV_RDSTA_CMD_VALUE_S       16
+#define SPI_SLV_WRBUF_CMD_VALUE         0x000000FF
+#define SPI_SLV_WRBUF_CMD_VALUE_S       8
+#define SPI_SLV_RDBUF_CMD_VALUE         0x000000FF
+#define SPI_SLV_RDBUF_CMD_VALUE_S       0
+
+#define SPI_W0(i)                   (REG_SPI_BASE(i) + 0x40)
+#define SPI_W1(i)                   (REG_SPI_BASE(i) + 0x44)
+#define SPI_W2(i)                   (REG_SPI_BASE(i) + 0x48)
+#define SPI_W3(i)                   (REG_SPI_BASE(i) + 0x4C)
+#define SPI_W4(i)                   (REG_SPI_BASE(i) + 0x50)
+#define SPI_W5(i)                   (REG_SPI_BASE(i) + 0x54)
+#define SPI_W6(i)                   (REG_SPI_BASE(i) + 0x58)
+#define SPI_W7(i)                   (REG_SPI_BASE(i) + 0x5C)
+#define SPI_W8(i)                   (REG_SPI_BASE(i) + 0x60)
+#define SPI_W9(i)                   (REG_SPI_BASE(i) + 0x64)
+#define SPI_W10(i)                  (REG_SPI_BASE(i) + 0x68)
+#define SPI_W11(i)                  (REG_SPI_BASE(i) + 0x6C)
+#define SPI_W12(i)                  (REG_SPI_BASE(i) + 0x70)
+#define SPI_W13(i)                  (REG_SPI_BASE(i) + 0x74)
+#define SPI_W14(i)                  (REG_SPI_BASE(i) + 0x78)
+#define SPI_W15(i)                  (REG_SPI_BASE(i) + 0x7C)
+
+#define SPI_EXT2(i)                 (REG_SPI_BASE(i) + 0xF8)
+
+#define SPI_EXT3(i)                 (REG_SPI_BASE(i) + 0xFC)
+#define SPI_INT_HOLD_ENA                0x00000003
+#define SPI_INT_HOLD_ENA_S              0
+
+#endif // SPI_REGISTER_H_INCLUDED

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp8266/timer_register.h

@@ -0,0 +1,93 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _TIMER_REGISTER_H_
+#define _TIMER_REGISTER_H_
+
+#define PERIPHS_TIMER_BASEDDR       0x60000600
+
+#define FRC1_LOAD_ADDRESS           (PERIPHS_TIMER_BASEDDR + 0x0)
+#define TIMER_FRC1_LOAD_VALUE           0x007FFFFF
+#define TIMER_FRC1_LOAD_VALUE_S         0
+#define FRC1_LOAD_DATA_MSB              22
+#define FRC1_LOAD_DATA_LSB              0
+#define FRC1_LOAD_DATA_MASK             0x007fffff
+
+#define FRC1_COUNT_ADDRESS          (PERIPHS_TIMER_BASEDDR + 0x4)
+#define TIMER_FRC1_COUNT                0x007FFFFF
+#define TIMER_FRC1_COUNT_S              0
+#define FRC1_COUNT_DATA_MSB             22
+#define FRC1_COUNT_DATA_LSB             0
+#define FRC1_COUNT_DATA_MASK            0x007fffff
+
+#define FRC1_CTRL_ADDRESS           (PERIPHS_TIMER_BASEDDR + 0x8)
+#define TIMER_FRC1_INT                  (BIT(8))
+#define TIMER_FRC1_CTRL                 0x000000FF
+#define TIMER_FRC1_CTRL_S               0
+#define FRC1_CTRL_DATA_MSB              7
+#define FRC1_CTRL_DATA_LSB              0
+#define FRC1_CTRL_DATA_MASK             0x000000ff
+
+#define FRC1_INT_ADDRESS            (PERIPHS_TIMER_BASEDDR + 0xC)
+#define TIMER_FRC1_INT_CLR_MASK         (BIT(0))
+#define FRC1_INT_CLR_MSB                0
+#define FRC1_INT_CLR_LSB                0
+#define FRC1_INT_CLR_MASK               0x00000001
+
+#define FRC2_LOAD_ADDRESS           (PERIPHS_TIMER_BASEDDR + 0x20)
+#define TIMER_FRC2_LOAD_VALUE           0xFFFFFFFF
+#define TIMER_FRC2_LOAD_VALUE_S         0
+#define FRC2_LOAD_DATA_MSB              31
+#define FRC2_LOAD_DATA_LSB              0
+#define FRC2_LOAD_DATA_MASK             0xffffffff
+
+#define FRC2_COUNT_ADDRESS          (PERIPHS_TIMER_BASEDDR + 0x24)
+#define TIMER_FRC2_COUNT                0xFFFFFFFF
+#define TIMER_FRC2_COUNT_S              0
+#define FRC2_COUNT_DATA_MSB             31
+#define FRC2_COUNT_DATA_LSB             0
+#define FRC2_COUNT_DATA_MASK            0xffffffff
+
+#define FRC2_CTRL_ADDRESS           (PERIPHS_TIMER_BASEDDR + 0x28)
+#define TIMER_FRC2_INT                  (BIT(8))
+#define TIMER_FRC2_CTRL                 0x000000FF
+#define TIMER_FRC2_CTRL_S               0
+#define FRC2_CTRL_DATA_MSB              7
+#define FRC2_CTRL_DATA_LSB              0
+#define FRC2_CTRL_DATA_MASK             0x000000ff
+
+#define FRC2_INT_ADDRESS            (PERIPHS_TIMER_BASEDDR + 0x2C)
+#define TIMER_FRC2_INT_CLR_MASK         (BIT(0))
+#define FRC2_INT_CLR_MSB                0
+#define FRC2_INT_CLR_LSB                0
+#define FRC2_INT_CLR_MASK               0x00000001
+
+#define FRC2_ALARM_ADDRESS          (PERIPHS_TIMER_BASEDDR + 0x30)
+#define TIMER_FRC2_ALARM                0xFFFFFFFF
+#define TIMER_FRC2_ALARM_S              0
+#define FRC2_ALARM_DATA_MSB             31
+#define FRC2_ALARM_DATA_LSB             0
+#define FRC2_ALARM_DATA_MASK            0xffffffff
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp8266/uart_register.h

@@ -0,0 +1,154 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef UART_REGISTER_H_
+#define UART_REGISTER_H_
+
+#define REG_UART_BASE(i)                (0x60000000 + (i)*0xf00)
+//version value:32'h062000
+
+#define UART_FIFO(i)                    (REG_UART_BASE(i) + 0x0)
+#define UART_RXFIFO_RD_BYTE                 0x000000FF
+#define UART_RXFIFO_RD_BYTE_S               0
+
+#define UART_INT_RAW(i)                 (REG_UART_BASE(i) + 0x4)
+#define UART_RXFIFO_TOUT_INT_RAW            (BIT(8))
+#define UART_BRK_DET_INT_RAW                (BIT(7))
+#define UART_CTS_CHG_INT_RAW                (BIT(6))
+#define UART_DSR_CHG_INT_RAW                (BIT(5))
+#define UART_RXFIFO_OVF_INT_RAW             (BIT(4))
+#define UART_FRM_ERR_INT_RAW                (BIT(3))
+#define UART_PARITY_ERR_INT_RAW             (BIT(2))
+#define UART_TXFIFO_EMPTY_INT_RAW           (BIT(1))
+#define UART_RXFIFO_FULL_INT_RAW            (BIT(0))
+
+#define UART_INT_ST(i)                  (REG_UART_BASE(i) + 0x8)
+#define UART_RXFIFO_TOUT_INT_ST             (BIT(8))
+#define UART_BRK_DET_INT_ST                 (BIT(7))
+#define UART_CTS_CHG_INT_ST                 (BIT(6))
+#define UART_DSR_CHG_INT_ST                 (BIT(5))
+#define UART_RXFIFO_OVF_INT_ST              (BIT(4))
+#define UART_FRM_ERR_INT_ST                 (BIT(3))
+#define UART_PARITY_ERR_INT_ST              (BIT(2))
+#define UART_TXFIFO_EMPTY_INT_ST            (BIT(1))
+#define UART_RXFIFO_FULL_INT_ST             (BIT(0))
+
+#define UART_INT_ENA(i)                 (REG_UART_BASE(i) + 0xC)
+#define UART_RXFIFO_TOUT_INT_ENA            (BIT(8))
+#define UART_BRK_DET_INT_ENA                (BIT(7))
+#define UART_CTS_CHG_INT_ENA                (BIT(6))
+#define UART_DSR_CHG_INT_ENA                (BIT(5))
+#define UART_RXFIFO_OVF_INT_ENA             (BIT(4))
+#define UART_FRM_ERR_INT_ENA                (BIT(3))
+#define UART_PARITY_ERR_INT_ENA             (BIT(2))
+#define UART_TXFIFO_EMPTY_INT_ENA           (BIT(1))
+#define UART_RXFIFO_FULL_INT_ENA            (BIT(0))
+
+#define UART_INT_CLR(i)                 (REG_UART_BASE(i) + 0x10)
+#define UART_RXFIFO_TOUT_INT_CLR            (BIT(8))
+#define UART_BRK_DET_INT_CLR                (BIT(7))
+#define UART_CTS_CHG_INT_CLR                (BIT(6))
+#define UART_DSR_CHG_INT_CLR                (BIT(5))
+#define UART_RXFIFO_OVF_INT_CLR             (BIT(4))
+#define UART_FRM_ERR_INT_CLR                (BIT(3))
+#define UART_PARITY_ERR_INT_CLR             (BIT(2))
+#define UART_TXFIFO_EMPTY_INT_CLR           (BIT(1))
+#define UART_RXFIFO_FULL_INT_CLR            (BIT(0))
+
+#define UART_CLKDIV(i)                  (REG_UART_BASE(i) + 0x14)
+#define UART_CLKDIV_CNT                     0x000FFFFF
+#define UART_CLKDIV_S                       0
+
+#define UART_AUTOBAUD(i)                (REG_UART_BASE(i) + 0x18)
+#define UART_GLITCH_FILT                    0x000000FF
+#define UART_GLITCH_FILT_S                  8
+#define UART_AUTOBAUD_EN                    (BIT(0))
+
+#define UART_STATUS(i)                  (REG_UART_BASE(i) + 0x1C)
+#define UART_TXD                            (BIT(31))
+#define UART_RTSN                           (BIT(30))
+#define UART_DTRN                           (BIT(29))
+#define UART_TXFIFO_CNT                     0x000000FF
+#define UART_TXFIFO_CNT_S                   16
+#define UART_RXD                            (BIT(15))
+#define UART_CTSN                           (BIT(14))
+#define UART_DSRN                           (BIT(13))
+#define UART_RXFIFO_CNT                     0x000000FF
+#define UART_RXFIFO_CNT_S                   0
+
+#define UART_CONF0(i)                   (REG_UART_BASE(i) + 0x20)
+#define UART_DTR_INV                        (BIT(24))
+#define UART_RTS_INV                        (BIT(23))
+#define UART_TXD_INV                        (BIT(22))
+#define UART_DSR_INV                        (BIT(21))
+#define UART_CTS_INV                        (BIT(20))
+#define UART_RXD_INV                        (BIT(19))
+#define UART_TXFIFO_RST                     (BIT(18))
+#define UART_RXFIFO_RST                     (BIT(17))
+#define UART_IRDA_EN                        (BIT(16))
+#define UART_TX_FLOW_EN                     (BIT(15))
+#define UART_LOOPBACK                       (BIT(14))
+#define UART_IRDA_RX_INV                    (BIT(13))
+#define UART_IRDA_TX_INV                    (BIT(12))
+#define UART_IRDA_WCTL                      (BIT(11))
+#define UART_IRDA_TX_EN                     (BIT(10))
+#define UART_IRDA_DPLX                      (BIT(9))
+#define UART_TXD_BRK                        (BIT(8))
+#define UART_SW_DTR                         (BIT(7))
+#define UART_SW_RTS                         (BIT(6))
+#define UART_STOP_BIT_NUM                   0x00000003
+#define UART_STOP_BIT_NUM_S                 4
+#define UART_BIT_NUM                        0x00000003
+#define UART_BIT_NUM_S                      2
+#define UART_PARITY_EN                      (BIT(1))
+#define UART_PARITY                         (BIT(0))
+
+#define UART_CONF1(i)                   (REG_UART_BASE(i) + 0x24)
+#define UART_RX_TOUT_EN                     (BIT(31))
+#define UART_RX_TOUT_THRHD                  0x0000007F
+#define UART_RX_TOUT_THRHD_S                24
+#define UART_RX_FLOW_EN                     (BIT(23))
+#define UART_RX_FLOW_THRHD                  0x0000007F
+#define UART_RX_FLOW_THRHD_S                16
+#define UART_TXFIFO_EMPTY_THRHD             0x0000007F
+#define UART_TXFIFO_EMPTY_THRHD_S           8
+#define UART_RXFIFO_FULL_THRHD              0x0000007F
+#define UART_RXFIFO_FULL_THRHD_S            0
+
+#define UART_LOWPULSE(i)                (REG_UART_BASE(i) + 0x28)
+#define UART_LOWPULSE_MIN_CNT               0x000FFFFF
+#define UART_LOWPULSE_MIN_CNT_S             0
+
+#define UART_HIGHPULSE(i)               (REG_UART_BASE(i) + 0x2C)
+#define UART_HIGHPULSE_MIN_CNT              0x000FFFFF
+#define UART_HIGHPULSE_MIN_CNT_S            0
+
+#define UART_PULSE_NUM(i)               (REG_UART_BASE(i) + 0x30)
+#define UART_PULSE_NUM_CNT                  0x0003FF
+#define UART_PULSE_NUM_CNT_S                0
+
+#define UART_DATE(i)                    (REG_UART_BASE(i) + 0x78)
+#define UART_ID(i)                      (REG_UART_BASE(i) + 0x7C)
+
+#endif // UART_REGISTER_H_INCLUDED

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_common.h

@@ -0,0 +1,112 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP_COMMON_H__
+#define __ESP_COMMON_H__
+
+/** \mainpage ESP8266_RTOS_SDK
+ *
+ *    - Misc APIs : misc APIs
+ *    - WiFi APIs : WiFi related APIs
+   *    - SoftAP APIs : ESP8266 Soft-AP APIs
+   *    - Station APIs : ESP8266 station APIs
+   *    - Common APIs : WiFi common APIs
+   *    - Force Sleep APIs : WiFi Force Sleep APIs
+   *    - Rate Control APIs : WiFi Rate Control APIs
+   *    - User IE APIs : WiFi User IE APIs
+   *    - Sniffer APIs : WiFi sniffer APIs
+   *    - WPS APIs : WiFi WPS APIs
+   *    - Smartconfig APIs : SmartConfig APIs
+   *    - AirKiss APIs : AirKiss APIs
+ *    - Spiffs APIs : Spiffs APIs
+ *    - SSC APIs : Simple Serial Command APIs
+ *    - System APIs : System APIs
+   *    - Boot APIs : Boot mode APIs
+   *    - Upgrade APIs : Firmware upgrade (FOTA) APIs
+ *    - Software timer APIs : Software timer APIs
+ *    - Network Espconn APIs : Network espconn APIs
+ *    - ESP-NOW APIs : ESP-NOW APIs
+ *    - Mesh APIs : Mesh APIs
+ *    - Driver APIs : Driver APIs
+   *    - PWM Driver APIs : PWM driver APIs
+   *    - UART Driver APIs : UART driver APIs
+   *    - GPIO Driver APIs : GPIO driver APIs
+   *    - SPI Driver APIs : SPI Flash APIs
+   *    - Hardware timer APIs : Hardware timer APIs
+ *
+  * void user_init(void) is the entrance function of the application.
+  * @attention 1. It is recommended that users set the timer to the periodic mode
+  *               for periodic checks. 
+  * @attention (1). In freeRTOS timer or os_timer, do not delay by while(1) or
+  *               in the manner that will block the thread.
+  * @attention (2). The timer callback should not occupy CPU more than 15ms.
+  * @attention (3). os_timer_t should not define a local variable, it has to be global varialbe
+  *               or memory got by malloc.
+  *
+  * @attention 2. Since esp_iot_rtos_sdk_v1.0.4, functions are stored in CACHE by
+  *               default, need not be added ICACHE_FLASH_ATTR any more. The interrupt
+  *               functions can also be stored in CACHE. If users want to store some
+  *               frequently called functions in RAM, please add IRAM_ATTR before
+  *               functions' name.
+  *
+  * @attention 3. Network programming use socket, please do not bind to the same port.  
+  * @attention (1). If users want to create 3 or more than 3 TCP connections, please add 
+  *               "TCP_WND = 2 x TCP_MSS;" in "user_init".
+  *
+  * @attention 4. Priority of the RTOS SDK is 15. xTaskCreate is an interface of
+  *               freeRTOS. For details of the freeRTOS and APIs of the system, 
+  *               please visit http://www.freertos.org
+  * @attention (1). When using xTaskCreate to create a task, the task stack range is [176, 512].
+  * @attention (2). If an array whose length is over 60 bytes is used in a task, 
+  *                 it is suggested that users use malloc and free rather than local
+  *                 variable to allocate array. Large local variables could lead to
+  *                 task stack overflow.
+  * @attention (3). The RTOS SDK takes some priorities. Priority of the pp task is
+  *                 13; priority of precise timer(ms) thread is 12; priority of the
+  *                 TCP/IP task is 10; priority of the freeRTOS timer is 2; priority of
+  *                 the idle task is 0.
+  * @attention (4). Users can use tasks with priorities from 1 to 9. 
+  * @attention (5). Do not revise FreeRTOSConfig.h, configurations are decided by source code
+  *                 inside the RTOS SDK, users can not change it.
+ */
+
+#include "c_types.h"
+#include "esp_libc.h"
+#include "esp_misc.h"
+#include "esp_wifi.h"
+#include "esp_softap.h"
+#include "esp_sta.h"
+#include "esp_system.h"
+#include "esp_timer.h"
+//#include "esp_ssc.h"
+//#include "esp_spiffs.h"
+//#include "esp_wpa2.h"
+
+#include "esp8266/esp8266.h"
+
+//#include "smartconfig.h"
+//#include "spi_flash.h"
+//#include "pwm.h"
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_libc.h

@@ -0,0 +1,171 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP_LIBC_H__
+#define __ESP_LIBC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+char *strcpy(char *dst, const char *src);
+char *strncpy(char *dst, const char *src, size_t n);
+int strcmp(const char *s1, const char *s2);
+int strncmp(const char *s1, const char *s2, size_t n);
+size_t strlen(const char *s);
+char *strstr(const char *s1, const char *s2);
+char *strcat(char *dst, const char *src);
+char *strncat(char *dst, const char *src, size_t count);
+size_t strspn(const char *s, const char *accept);
+size_t strcspn(const char *s, const char *reject);
+char *strtok_r(char *s, const char *delim, char **ptrptr);
+char *strtok(char *s, const char *delim);
+char *strrchr(const char *s, int c);
+char *strdup(const char *s);
+char *strchr(const char *s, int c);
+long strtol(const char *str, char **endptr, int base);
+
+void bzero(void *s, size_t n);
+
+void *memcpy(void *dst, const void *src, size_t n);
+void *memset(void *dst, int c, size_t n);
+int memcmp(const void *m1, const void *m2, size_t n);
+void *memmove(void *dst, const void *src, size_t n);
+
+int rand(void);
+
+int printf(const char *format, ...);
+int sprintf(char *out, const char *format, ...);
+int snprintf(char *buf, unsigned int count, const char *format, ...);
+int puts(const char *str);
+
+void *malloc(size_t n);
+void free(void *p);
+void *calloc(size_t c, size_t n);
+void *zalloc(size_t n);
+void *realloc(void *p, size_t n);
+
+int atoi(const char *s);
+long atol(const char *s);
+
+unsigned long os_random(void);
+int os_get_random(unsigned char *buf, size_t len);
+
+#ifndef os_printf
+/* NOTE: don't use printf_opt in irq handler, for test */
+#define os_printf(fmt, ...) do {    \
+        static const char flash_str[] ICACHE_RODATA_ATTR STORE_ATTR = fmt;  \
+        printf(flash_str, ##__VA_ARGS__);   \
+    } while(0)
+#endif
+
+/* Note: check_memleak_debug_enable is a weak function inside SDK.
+ * please copy following codes to user_main.c.
+#include "esp_libc.h"
+
+bool ICACHE_FLASH_ATTR check_memleak_debug_enable(void)
+{
+    return MEMLEAK_DEBUG_ENABLE;
+}
+*/
+
+#ifndef MEMLEAK_DEBUG
+#define MEMLEAK_DEBUG_ENABLE    0
+#ifndef os_free
+#define os_free(s)        free(s)
+#endif
+
+#ifndef os_malloc
+#define os_malloc(s)      malloc(s)
+#endif
+
+#ifndef os_calloc
+#define os_calloc(p, s)   calloc(p, s)
+#endif
+
+#ifndef os_realloc
+#define os_realloc(p, s)  realloc(p, s)
+#endif
+
+#ifndef os_zalloc
+#define os_zalloc(s)      zalloc(s)
+#endif
+#else
+#define MEMLEAK_DEBUG_ENABLE    1
+
+#ifndef os_free
+#define os_free(s) \
+do{\
+    static const char mem_debug_file[] ICACHE_RODATA_ATTR STORE_ATTR = __FILE__;    \
+    vPortFree(s, mem_debug_file, __LINE__);\
+}while(0)
+#endif
+
+#ifndef os_malloc
+#define os_malloc(s)    \
+    ({  \
+        static const char mem_debug_file[] ICACHE_RODATA_ATTR STORE_ATTR = __FILE__;    \
+        pvPortMalloc(s, mem_debug_file, __LINE__, false);  \
+    })
+#endif
+
+#ifndef os_malloc_iram
+#define os_malloc_iram(s)    \
+    ({  \
+        static const char mem_debug_file[] ICACHE_RODATA_ATTR STORE_ATTR = __FILE__;    \
+        pvPortMalloc(s, mem_debug_file, __LINE__, true);  \
+    })
+#endif
+
+#ifndef os_calloc
+#define os_calloc(p, s)    \
+    ({  \
+        static const char mem_debug_file[] ICACHE_RODATA_ATTR STORE_ATTR = __FILE__;    \
+        pvPortCalloc(p, s, mem_debug_file, __LINE__);  \
+    })
+#endif
+
+#ifndef os_realloc
+#define os_realloc(p, s)    \
+    ({  \
+        static const char mem_debug_file[] ICACHE_RODATA_ATTR STORE_ATTR = __FILE__;    \
+        pvPortRealloc(p, s, mem_debug_file, __LINE__);  \
+    })
+#endif
+
+#ifndef os_zalloc
+#define os_zalloc(s)    \
+    ({  \
+        static const char mem_debug_file[] ICACHE_RODATA_ATTR STORE_ATTR = __FILE__;    \
+        pvPortZalloc(s, mem_debug_file, __LINE__);  \
+    })
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LIBC_H__ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_misc.h

@@ -0,0 +1,108 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP_MISC_H__
+#define __ESP_MISC_H__
+
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup Misc_APIs Misc APIs
+  * @brief misc APIs
+  */
+
+/** @addtogroup Misc_APIs
+  * @{
+  */
+
+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
+
+#define IP2STR(ipaddr) ip4_addr1_16(ipaddr), \
+    ip4_addr2_16(ipaddr), \
+    ip4_addr3_16(ipaddr), \
+    ip4_addr4_16(ipaddr)
+
+#define IPSTR "%d.%d.%d.%d"
+
+/**
+  * @brief  Delay function, maximum value: 65535 us.
+  *
+  * @param  uint16 us : delay time, uint: us, maximum value: 65535 us
+  *
+  * @return null
+  */
+void os_delay_us(uint16 us);
+
+/**
+  * @brief     Register the print output function.
+  *
+  * @attention os_install_putc1((void *)uart1_write_char) in uart_init will set
+  *            printf to print from UART 1, otherwise, printf will start from
+  *            UART 0 by default.
+  *
+  * @param     void(*p)(char c) - pointer of print function
+  *
+  * @return    null
+  */
+void os_install_putc1(void (*p)(char c));
+
+/**
+  * @brief  Print a character. Start from from UART0 by default.
+  *
+  * @param  char c - character to be printed
+  *
+  * @return null
+  */
+void os_putc(char c);
+
+enum dhcp_status {
+    DHCP_STOPPED,   /**< disable DHCP */
+    DHCP_STARTED    /**< enable DHCP */
+};
+
+struct dhcps_lease {
+    bool enable;                /**< enable DHCP lease or not */
+    struct ip_addr start_ip;    /**< start IP of IP range */
+    struct ip_addr end_ip;      /**< end IP of IP range */
+};
+
+enum dhcps_offer_option {
+    OFFER_START = 0x00,         /**< DHCP offer option start */
+    OFFER_ROUTER = 0x01,        /**< DHCP offer router, only support this option now */
+    OFFER_END                   /**< DHCP offer option start */
+};
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_softap.h

@@ -0,0 +1,290 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP_SOFTAP_H__
+#define __ESP_SOFTAP_H__
+
+#include "queue.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup WiFi_APIs WiFi Related APIs
+  * @brief WiFi APIs
+  */
+
+/** @addtogroup WiFi_APIs
+  * @{
+  */
+
+/** \defgroup SoftAP_APIs SoftAP APIs
+  * @brief ESP8266 Soft-AP APIs
+  * @attention To call APIs related to ESP8266 soft-AP has to enable soft-AP mode first (wifi_set_opmode)
+  */
+
+/** @addtogroup SoftAP_APIs
+  * @{
+  */
+
+struct softap_config {
+    uint8 ssid[32];         /**< SSID of ESP8266 soft-AP */
+    uint8 password[64];     /**< Password of ESP8266 soft-AP */
+    uint8 ssid_len;         /**< Length of SSID. If softap_config.ssid_len==0, check the SSID until there is a termination character; otherwise, set the SSID length according to softap_config.ssid_len. */
+    uint8 channel;          /**< Channel of ESP8266 soft-AP */
+    AUTH_MODE authmode;     /**< Auth mode of ESP8266 soft-AP. Do not support AUTH_WEP in soft-AP mode */
+    uint8 ssid_hidden;      /**< Broadcast SSID or not, default 0, broadcast the SSID */
+    uint8 max_connection;   /**< Max number of stations allowed to connect in, default 4, max 4 */
+    uint16 beacon_interval; /**< Beacon interval, 100 ~ 60000 ms, default 100 */
+};
+
+struct station_info {
+    STAILQ_ENTRY(station_info)     next;    /**< Information of next AP */
+
+    uint8 bssid[6];                         /**< BSSID of AP */
+    struct ip_addr ip;                      /**< IP address of AP */
+};
+
+/**
+  * @brief  Get the current configuration of the ESP8266 WiFi soft-AP
+  *
+  * @param  struct softap_config *config : ESP8266 soft-AP configuration
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_softap_get_config(struct softap_config *config);
+
+/**
+  * @brief  Get the configuration of the ESP8266 WiFi soft-AP saved in the flash
+  *
+  * @param  struct softap_config *config : ESP8266 soft-AP configuration
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_softap_get_config_default(struct softap_config *config);
+
+/**
+  * @brief     Set the configuration of the WiFi soft-AP and save it to the Flash.
+  *
+  * @attention 1. This configuration will be saved in flash system parameter area if changed
+  * @attention 2. The ESP8266 is limited to only one channel, so when in the soft-AP+station mode,
+  *               the soft-AP will adjust its channel automatically to be the same as
+  *               the channel of the ESP8266 station.
+  *
+  * @param     struct softap_config *config : ESP8266 soft-AP configuration
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_softap_set_config(struct softap_config *config);
+
+/**
+  * @brief     Set the configuration of the WiFi soft-AP; the configuration will
+  *            not be saved to the Flash.
+  *
+  * @attention The ESP8266 is limited to only one channel, so when in the soft-AP+station mode,
+  *            the soft-AP will adjust its channel automatically to be the same as
+  *            the channel of the ESP8266 station.
+  *
+  * @param     struct softap_config *config : ESP8266 soft-AP configuration
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_softap_set_config_current(struct softap_config *config);
+
+/**
+  * @brief     Get the number of stations connected to the ESP8266 soft-AP.
+  *
+  * @attention The ESP8266 is limited to only one channel, so when in the soft-AP+station mode,
+  *            the soft-AP will adjust its channel automatically to be the same as
+  *            the channel of the ESP8266 station.
+  *
+  * @param     null
+  *
+  * @return    the number of stations connected to the ESP8266 soft-AP
+  */
+uint8 wifi_softap_get_station_num(void);
+
+/**
+  * @brief     Get the information of stations connected to the ESP8266 soft-AP,
+  *            including MAC and IP.
+  *
+  * @attention wifi_softap_get_station_info depends on DHCP, it can only
+  *            be used when DHCP is enabled, so it can not get the static IP.
+  *
+  * @param     null
+  *
+  * @return    struct station_info* : station information structure
+  */
+struct station_info *wifi_softap_get_station_info(void);
+
+/**
+  * @brief     Free the space occupied by station_info when wifi_softap_get_station_info is called.
+  *
+  * @attention The ESP8266 is limited to only one channel, so when in the soft-AP+station mode,
+  *            the soft-AP will adjust its channel automatically to be the same as
+  *            the channel of the ESP8266 station.
+  *
+  * @param     null
+  *
+  * @return    null
+  */
+void wifi_softap_free_station_info(void);
+
+/**
+  * @brief     Enable the ESP8266 soft-AP DHCP server.
+  *
+  * @attention 1. The DHCP is enabled by default.
+  * @attention 2. The DHCP and the static IP related API (wifi_set_ip_info) influence
+  *               each other, if the DHCP is enabled, the static IP will be disabled;
+  *               if the static IP is enabled, the DHCP will be disabled.
+  *               It depends on the latest configuration.
+  *
+  * @param     null
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_softap_dhcps_start(void);
+
+/**
+  * @brief  Disable the ESP8266 soft-AP DHCP server. The DHCP is enabled by default.
+  *
+  * @param  null
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_softap_dhcps_stop(void);
+
+/**
+  * @brief  Get the ESP8266 soft-AP DHCP server status.
+  *
+  * @param  null
+  *
+  * @return enum dhcp_status
+  */
+enum dhcp_status wifi_softap_dhcps_status(void);
+
+/**
+  * @brief     Query the IP range that can be got from the ESP8266 soft-AP DHCP server.
+  *
+  * @attention This API can only be called during ESP8266 soft-AP DHCP server enabled.
+  *
+  * @param     struct dhcps_lease *please : IP range of the ESP8266 soft-AP DHCP server.
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_softap_get_dhcps_lease(struct dhcps_lease *please);
+
+/**
+  * @brief     Set the IP range of the ESP8266 soft-AP DHCP server.
+  *
+  * @attention 1. The IP range should be in the same sub-net with the ESP8266
+  *               soft-AP IP address.
+  * @attention 2. This API should only be called when the DHCP server is disabled
+  *               (wifi_softap_dhcps_stop).
+  * @attention 3. This configuration will only take effect the next time when the
+  *               DHCP server is enabled (wifi_softap_dhcps_start).
+  *    - If the DHCP server is disabled again, this API should be called to set the IP range.
+  *    - Otherwise, when the DHCP server is enabled later, the default IP range will be used.
+  *
+  * @param     struct dhcps_lease *please : IP range of the ESP8266 soft-AP DHCP server.
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_softap_set_dhcps_lease(struct dhcps_lease *please);
+
+/**
+  * @brief     Get ESP8266 soft-AP DHCP server lease time.
+  *
+  * @attention This API can only be called during ESP8266 soft-AP DHCP server enabled.
+  *
+  * @param     null
+  *
+  * @return    lease time, uint: minute.
+  */
+uint32 wifi_softap_get_dhcps_lease_time(void);
+
+/**
+  * @brief     Set ESP8266 soft-AP DHCP server lease time, default is 120 minutes.
+  *
+  * @attention This API can only be called during ESP8266 soft-AP DHCP server enabled.
+  *
+  * @param     uint32 minute : lease time, uint: minute, range:[1, 2880].
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_softap_set_dhcps_lease_time(uint32 minute);
+
+/**
+  * @brief     Reset ESP8266 soft-AP DHCP server lease time which is 120 minutes by default.
+  *
+  * @attention This API can only be called during ESP8266 soft-AP DHCP server enabled.
+  *
+  * @param     null
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_softap_reset_dhcps_lease_time(void);
+
+/**
+  * @brief  Set the ESP8266 soft-AP DHCP server option.
+  *
+  * Example:          
+  * <pre> 
+  *         uint8 mode = 0;
+  *         wifi_softap_set_dhcps_offer_option(OFFER_ROUTER, &mode);
+  * </pre>
+  *
+  * @param  uint8 level : OFFER_ROUTER, set the router option.
+  * @param  void* optarg :
+  *    - bit0, 0 disable the router information;
+  *    - bit0, 1 enable the router information.
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_softap_set_dhcps_offer_option(uint8 level, void *optarg);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_spiffs.h

@@ -0,0 +1,84 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP_SPIFFS_H__
+#define __ESP_SPIFFS_H__
+
+#include "spiffs/spiffs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup Spiffs_APIs Spiffs APIs
+  * @brief Spiffs APIs
+  *
+  * More details about spiffs on https://github.com/pellepl/spiffs
+  *
+  */
+
+/** @addtogroup Spiffs_APIs
+  * @{
+  */
+
+struct esp_spiffs_config {
+    uint32 phys_size;        /**< physical size of the SPI Flash */
+    uint32 phys_addr;        /**< physical offset in spi flash used for spiffs, must be on block boundary */
+    uint32 phys_erase_block; /**< physical size when erasing a block */
+
+    uint32 log_block_size;   /**< logical size of a block, must be on physical block size boundary and must never be less than a physical block */
+    uint32 log_page_size;    /**< logical size of a page, at least log_block_size/8  */
+
+    uint32 fd_buf_size;      /**< file descriptor memory area size */
+    uint32 cache_buf_size;   /**< cache buffer size */
+};
+
+/**
+  * @brief  Initialize spiffs
+  *
+  * @param  struct esp_spiffs_config *config : ESP8266 spiffs configuration
+  *
+  * @return 0         : succeed
+  * @return otherwise : fail
+  */
+sint32 esp_spiffs_init(struct esp_spiffs_config *config);
+
+/**
+  * @brief  Deinitialize spiffs
+  *
+  * @param  uint8 format : 0, only deinit; otherwise, deinit spiffs and format.
+  *
+  * @return null
+  */
+void esp_spiffs_deinit(uint8 format);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_SPIFFS_H__ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_ssc.h

@@ -0,0 +1,125 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP_SSC_H__
+#define __ESP_SSC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CMD_T_ASYNC   0x01
+#define CMD_T_SYNC    0x02
+
+typedef struct cmd_s {
+    char *cmd_str;
+    uint8 flag;
+    uint8 id;
+    void (* cmd_func)(void);
+    void (* cmd_callback)(void *arg);
+} ssc_cmd_t;
+
+#define MAX_LINE_N  127
+
+typedef enum {
+    SSC_BR_9600   = 9600,
+    SSC_BR_19200  = 19200,
+    SSC_BR_38400  = 38400,
+    SSC_BR_57600  = 57600,
+    SSC_BR_74880  = 74880,
+    SSC_BR_115200 = 115200,
+    SSC_BR_230400 = 230400,
+    SSC_BR_460800 = 460800,
+    SSC_BR_921600 = 921600
+} SscBaudRate;
+
+/** \defgroup SSC_APIs SSC APIs
+  * @brief SSC APIs
+  *
+  * SSC means simple serial command.
+  * SSC APIs allows users to define their own command, users can refer to spiffs_test/test_main.c.
+  *
+  */
+
+/** @addtogroup SSC_APIs
+  * @{
+  */
+
+/**
+  * @brief  Initial the ssc function.
+  *
+  * @param  SscBaudRate bandrate : baud rate
+  *
+  * @return null
+  */
+void ssc_attach(SscBaudRate bandrate);
+
+/**
+  * @brief   Get the length of the simple serial command.
+  *
+  * @param   null
+  *
+  * @return  length of the command.
+  */
+int ssc_param_len(void);
+
+/**
+  * @brief   Get the simple serial command string.
+  *
+  * @param   null
+  *
+  * @return  the command.
+  */
+char *ssc_param_str(void);
+
+/**
+  * @brief   Parse the simple serial command (ssc).
+  *
+  * @param   char *pLine  : [input] the ssc string
+  * @param   char *argv[] : [output] parameters of the ssc
+  *
+  * @return  the number of parameters.
+  */
+int ssc_parse_param(char *pLine, char *argv[]);
+
+/**
+  * @brief  Register the user-defined simple serial command (ssc) set.
+  *
+  * @param  ssc_cmd_t *cmdset   : the ssc set
+  * @param  uint8 cmdnum        : number of commands
+  * @param  void (* help)(void) : callback of user-guide
+  *
+  * @return  null
+  */
+void ssc_register(ssc_cmd_t *cmdset, uint8 cmdnum, void (* help)(void));
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_SSC_H__ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_sta.h

@@ -0,0 +1,393 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP_STA_H__
+#define __ESP_STA_H__
+
+#include "queue.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup WiFi_APIs WiFi Related APIs
+  * @brief WiFi APIs
+  */
+
+/** @addtogroup WiFi_APIs
+  * @{
+  */
+
+/** \defgroup Station_APIs Station APIs
+  * @brief     ESP8266 station APIs
+  * @attention To call APIs related to ESP8266 station has to enable station mode
+  *            first (wifi_set_opmode)
+  */
+
+/** @addtogroup Station_APIs
+  * @{
+  */
+
+struct station_config {
+    uint8 ssid[32];         /**< SSID of target AP*/
+    uint8 password[64];     /**< password of target AP*/
+    uint8 bssid_set;        /**< whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/
+    uint8 bssid[6];         /**< MAC address of target AP*/
+};
+
+/**
+  * @brief  Get the current configuration of the ESP8266 WiFi station.
+  *
+  * @param  struct station_config *config : ESP8266 station configuration
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_station_get_config(struct station_config *config);
+
+/**
+  * @brief  Get the configuration parameters saved in the Flash of the ESP8266 WiFi station.
+  *
+  * @param  struct station_config *config : ESP8266 station configuration
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_station_get_config_default(struct station_config *config);
+
+/**
+  * @brief     Set the configuration of the ESP8266 station and save it to the Flash.
+  *
+  * @attention 1. This API can be called only when the ESP8266 station is enabled.
+  * @attention 2. If wifi_station_set_config is called in user_init , there is no
+  *               need to call wifi_station_connect.
+  *               The ESP8266 station will automatically connect to the AP (router)
+  *               after the system initialization. Otherwise, wifi_station_connect should be called.
+  * @attention 3. Generally, station_config.bssid_set needs to be 0; and it needs
+  *               to be 1 only when users need to check the MAC address of the AP.
+  * @attention 4. This configuration will be saved in the Flash system parameter area if changed.
+  *
+  * @param     struct station_config *config : ESP8266 station configuration
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_station_set_config(struct station_config *config);
+
+/**
+  * @brief     Set the configuration of the ESP8266 station. And the configuration
+  *            will not be saved to the Flash.
+  *
+  * @attention 1. This API can be called only when the ESP8266 station is enabled.
+  * @attention 2. If wifi_station_set_config_current is called in user_init , there
+  *               is no need to call wifi_station_connect.
+  *               The ESP8266 station will automatically connect to the AP (router)
+  *               after the system initialization. Otherwise, wifi_station_connect
+  *               should be called.
+  * @attention 3. Generally, station_config.bssid_set needs to be 0; and it needs
+  *               to be 1 only when users need to check the MAC address of the AP.
+  *
+  * @param     struct station_config *config : ESP8266 station configuration
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_station_set_config_current(struct station_config *config);
+
+/**
+  * @brief     Connect the ESP8266 WiFi station to the AP.
+  *
+  * @attention 1. This API should be called when the ESP8266 station is enabled,
+  *               and the system initialization is completed. Do not call this API in user_init.
+  * @attention 2. If the ESP8266 is connected to an AP, call wifi_station_disconnect to disconnect.
+  *
+  * @param     null
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_station_connect(void);
+
+/**
+  * @brief     Disconnect the ESP8266 WiFi station from the AP.
+  *
+  * @attention This API should be called when the ESP8266 station is enabled,
+  *            and the system initialization is completed. Do not call this API in user_init.
+  *
+  * @param     null
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_station_disconnect(void);
+
+struct scan_config {
+    uint8 *ssid;            /**< SSID of AP */
+    uint8 *bssid;           /**< MAC address of AP */
+    uint8 channel;          /**< channel, scan the specific channel */
+    uint8 show_hidden;      /**< enable to scan AP whose SSID is hidden */
+};
+
+struct bss_info {
+    STAILQ_ENTRY(bss_info)     next;    /**< information of next AP */
+
+    uint8 bssid[6];                     /**< MAC address of AP */
+    uint8 ssid[32];                     /**< SSID of AP */
+    uint8 ssid_len;                     /**< SSID length */
+    uint8 channel;                      /**< channel of AP */
+    sint8 rssi;                         /**< single strength of AP */
+    AUTH_MODE authmode;                 /**< authmode of AP */
+    uint8 is_hidden;                    /**< SSID of current AP is hidden or not. */
+    sint16 freq_offset;                 /**< frequency offset */
+    sint16 freqcal_val;
+    uint8 *esp_mesh_ie;
+};
+
+/**
+  * @brief  Callback function for wifi_station_scan.
+  *
+  * @param  void *arg : information of APs that are found; save them as linked list;
+  *                     refer to struct bss_info
+  * @param  STATUS status : status of scanning
+  *
+  * @return null
+  */
+typedef void (* scan_done_cb_t)(void *arg, STATUS status);
+
+/**
+  * @brief     Scan all available APs.
+  *
+  * @attention This API should be called when the ESP8266 station is enabled, and
+  *            the system initialization is completed. Do not call this API in user_init.
+  *
+  * @param     struct scan_config *config : configuration of scanning
+  * @param     struct scan_done_cb_t cb : callback of scanning
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_station_scan(struct scan_config *config, scan_done_cb_t cb);
+
+/**
+  * @brief  Check if the ESP8266 station will connect to the recorded AP automatically
+  *         when the power is on.
+  *
+  * @param  null
+  *
+  * @return true  : connect to the AP automatically
+  * @return false : not connect to the AP automatically
+  */
+bool wifi_station_get_auto_connect(void);
+
+/**
+  * @brief     Set whether the ESP8266 station will connect to the recorded AP
+  *            automatically when the power is on. It will do so by default.
+  *
+  * @attention 1. If this API is called in user_init, it is effective immediately
+  *               after the power is on. If it is called in other places, it will
+  *               be effective the next time when the power is on.
+  * @attention 2. This configuration will be saved in Flash system parameter area if changed.
+  *
+  * @param     bool set : If it will automatically connect to the AP when the power is on
+  *    - true : it will connect automatically
+  *    - false: it will not connect automatically
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_station_set_auto_connect(bool set);
+
+/**
+  * @brief  Check whether the ESP8266 station will reconnect to the AP after disconnection.
+  *
+  * @param  null
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_station_get_reconnect_policy(void);
+
+/**
+  * @brief     Set whether the ESP8266 station will reconnect to the AP after disconnection.
+  *            It will do so by default.
+  *
+  * @attention If users want to call this API, it is suggested that users call this API in user_init.
+  *
+  * @param     bool set : if it's true, it will enable reconnection; if it's false,
+  *                       it will disable reconnection.
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_station_set_reconnect_policy(bool set);
+
+typedef enum {
+    STATION_IDLE = 0,        /**< ESP8266 station idle */
+    STATION_CONNECTING,      /**< ESP8266 station is connecting to AP*/
+    STATION_WRONG_PASSWORD,  /**< the password is wrong*/
+    STATION_NO_AP_FOUND,     /**< ESP8266 station can not find the target AP*/
+    STATION_CONNECT_FAIL,    /**< ESP8266 station fail to connect to AP*/
+    STATION_GOT_IP           /**< ESP8266 station got IP address from AP*/
+} STATION_STATUS;
+
+/**
+  * @brief  Get the connection status of the ESP8266 WiFi station.
+  *
+  * @param  null
+  *
+  * @return the status of connection
+  */
+STATION_STATUS wifi_station_get_connect_status(void);
+
+/**
+  * @brief  Get the information of APs (5 at most) recorded by ESP8266 station.
+  *
+  * @param  struct station_config config[] : information of the APs, the array size should be 5.
+  *
+  * @return The number of APs recorded.
+  */
+uint8 wifi_station_get_current_ap_id(void);
+
+/**
+  * @brief  Switch the ESP8266 station connection to a recorded AP.
+  *
+  * @param  uint8 new_ap_id : AP's record id, start counting from 0.
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_station_ap_change(uint8 current_ap_id);
+
+/**
+  * @brief     Set the number of APs that can be recorded in the ESP8266 station.
+  *            When the ESP8266 station is connected to an AP, the SSID and password
+  *            of the AP will be recorded.
+  *
+  * @attention This configuration will be saved in the Flash system parameter area if changed.
+  *
+  * @param     uint8 ap_number : the number of APs that can be recorded (MAX: 5)
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_station_ap_number_set(uint8 ap_number);
+
+/**
+  * @brief  Get the information of APs (5 at most) recorded by ESP8266 station.
+  *
+  * Example:          
+  * <pre> 
+  *         struct station_config config[5];
+  *         nt i = wifi_station_get_ap_info(config);
+  * </pre>
+  *
+  * @param  struct station_config config[] : information of the APs, the array size should be 5.
+  *
+  * @return The number of APs recorded.
+  */
+uint8 wifi_station_get_ap_info(struct station_config config[]);
+
+/**
+  * @brief  Get rssi of the AP which ESP8266 station connected to.
+  *
+  * @param  null
+  *
+  * @return 31 : fail, invalid value.
+  * @return others : succeed, value of rssi. In general, rssi value < 10
+  */
+sint8 wifi_station_get_rssi(void);
+
+/**
+  * @brief     Enable the ESP8266 station DHCP client.
+  *
+  * @attention 1. The DHCP is enabled by default.
+  * @attention 2. The DHCP and the static IP API ((wifi_set_ip_info)) influence each other,
+  *               and if the DHCP is enabled, the static IP will be disabled;
+  *               if the static IP is enabled, the DHCP will be disabled.
+  *               It depends on the latest configuration.
+  *
+  * @param  null
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_station_dhcpc_start(void);
+
+/**
+  * @brief     Disable the ESP8266 station DHCP client.
+  *
+  * @attention 1. The DHCP is enabled by default.
+  * @attention 2. The DHCP and the static IP API ((wifi_set_ip_info)) influence each other,
+  *               and if the DHCP is enabled, the static IP will be disabled;
+  *               if the static IP is enabled, the DHCP will be disabled.
+  *               It depends on the latest configuration.
+  *
+  * @param     null
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_station_dhcpc_stop(void);
+
+/**
+  * @brief   Get the ESP8266 station DHCP client status.
+  *
+  * @param  null
+  *
+  * @return  enum dhcp_status
+  */
+enum dhcp_status wifi_station_dhcpc_status(void);
+
+/**
+  * @brief    Set ESP8266 station DHCP hostname.
+  *
+  * @param  char *name : hostname of ESP8266 station
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_station_set_hostname(char *name);
+
+/**
+  * @brief  Get ESP8266 station DHCP hostname.
+  *
+  * @param  null
+  *
+  * @return the hostname of ESP8266 station
+  */
+char* wifi_station_get_hostname(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_system.h

@@ -0,0 +1,591 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP_SYSTEM_H__
+#define __ESP_SYSTEM_H__
+
+#include "c_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup System_APIs System APIs
+  * @brief System APIs
+  */
+
+/** @addtogroup System_APIs
+  * @{
+  */
+
+typedef enum {
+    REASON_DEFAULT_RST = 0,         /**< normal startup by power on */
+        REASON_WDT_RST,             /**< hardware watch dog reset */
+        REASON_EXCEPTION_RST,       /**< exception reset, GPIO status won't change */
+        REASON_SOFT_WDT_RST,        /**< software watch dog reset, GPIO status won't change */
+        REASON_SOFT_RESTART,        /**< software restart ,system_restart , GPIO status won't change */
+        REASON_DEEP_SLEEP_AWAKE,    /**< wake up from deep-sleep */
+        REASON_EXT_SYS_RST          /**< external system reset */
+} rst_reason;
+
+struct rst_info {
+    rst_reason reason;  /**< enum rst_reason */
+    uint32 exccause;
+    uint32 epc1;
+    uint32 epc2;
+    uint32 epc3;
+    uint32 excvaddr;
+    uint32 depc;
+    uint32 rtn_addr;
+};
+
+/**
+  * @brief  Get the reason of restart.
+  *
+  * @param  null
+  *
+  * @return struct rst_info* : information of the system restart
+  */
+struct rst_info *system_get_rst_info(void);
+
+/**
+  * @brief  Get information of the SDK version.
+  *
+  * @param  null
+  *
+  * @return Information of the SDK version.
+  */
+const char *system_get_sdk_version(void);
+
+/**
+  * @brief  Reset to default settings.
+  *
+  *         Reset to default settings of the following APIs : wifi_station_set_auto_connect,
+  *         wifi_set_phy_mode, wifi_softap_set_config related, wifi_station_set_config
+  *         related, and wifi_set_opmode.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_restore(void);
+
+/**
+  * @brief  Restart system.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_restart(void);
+
+/**
+  * @brief     Set the chip to deep-sleep mode.
+  *
+  *            The device will automatically wake up after the deep-sleep time set
+  *            by the users. Upon waking up, the device boots up from user_init.
+  *
+  * @attention 1. XPD_DCDC should be connected to EXT_RSTB through 0 ohm resistor
+  *               in order to support deep-sleep wakeup.
+  * @attention 2. system_deep_sleep(0): there is no wake up timer; in order to wake
+  *               up, connect a GPIO to pin RST, the chip will wake up by a falling-edge
+  *               on pin RST
+  *
+  * @param     uint32 time_in_us : deep-sleep time, unit: microsecond
+  *
+  * @return    null
+  */
+void system_deep_sleep(uint32 time_in_us);
+
+/**
+  * @brief  Call this API before system_deep_sleep to set the activity after the
+  *         next deep-sleep wakeup.
+  *
+  *         If this API is not called, default to be system_deep_sleep_set_option(1).
+  *
+  * @param  uint8 option :
+  * @param  0 : Radio calibration after the deep-sleep wakeup is decided by byte
+  *             108 of esp_init_data_default.bin (0~127byte).
+  * @param  1 : Radio calibration will be done after the deep-sleep wakeup. This
+  *             will lead to stronger current.
+  * @param  2 : Radio calibration will not be done after the deep-sleep wakeup.
+  *             This will lead to weaker current.
+  * @param  4 : Disable radio calibration after the deep-sleep wakeup (the same
+  *             as modem-sleep). This will lead to the weakest current, but the device
+  *             can't receive or transmit data after waking up.
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool system_deep_sleep_set_option(uint8 option);
+
+/**
+  * @brief  Get system time, unit: microsecond.
+  *
+  * @param  null
+  *
+  * @return System time, unit: microsecond.
+  */
+uint32 system_get_time(void);
+
+/**
+  * @brief  Print the system memory distribution, including data/rodata/bss/heap.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_print_meminfo(void);
+
+/**
+  * @brief  Get the size of available heap.
+  *
+  * @param  null
+  *
+  * @return Available heap size.
+  */
+uint32 system_get_free_heap_size(void);
+
+/**
+  * @brief  Get the chip ID.
+  *
+  * @param  null
+  *
+  * @return The chip ID.
+  */
+uint32 system_get_chip_id(void);
+
+/**
+  * @brief     Get the RTC clock cycle.
+  *
+  * @attention 1. The RTC clock cycle has decimal part.
+  * @attention 2. The RTC clock cycle will change according to the temperature,
+  *               so RTC timer is not very precise.
+  *
+  * @param     null
+  *
+  * @return    RTC clock period (unit: microsecond), bit11~ bit0 are decimal.
+  */
+uint32 system_rtc_clock_cali_proc(void);
+
+/**
+  * @brief     Get RTC time, unit: RTC clock cycle.
+  *
+  * Example:
+  *            If system_get_rtc_time returns 10 (it means 10 RTC cycles), and
+  *            system_rtc_clock_cali_proc returns 5.75 (it means 5.75 microseconds per RTC clock cycle),
+  *            (then the actual time is 10 x 5.75 = 57.5 microseconds.
+  *
+  * @attention System time will return to zero because of system_restart, but the
+  *            RTC time still goes on. If the chip is reset by pin EXT_RST or pin
+  *            CHIP_EN (including the deep-sleep wakeup), situations are shown as below:
+  * @attention 1. reset by pin EXT_RST : RTC memory won't change, RTC timer returns to zero
+  * @attention 2. watchdog reset : RTC memory won't change, RTC timer won't change
+  * @attention 3. system_restart : RTC memory won't change, RTC timer won't change
+  * @attention 4. power on : RTC memory is random value, RTC timer starts from zero
+  * @attention 5. reset by pin CHIP_EN : RTC memory is random value, RTC timer starts from zero
+  *
+  * @param     null
+  *
+  * @return    RTC time.
+  */
+uint32 system_get_rtc_time(void);
+
+/**
+  * @brief     Read user data from the RTC memory.
+  *
+  *            The user data segment (512 bytes, as shown below) is used to store user data.
+  *
+  *             |<---- system data(256 bytes) ---->|<----------- user data(512 bytes) --------->|
+  *
+  * @attention Read and write unit for data stored in the RTC memory is 4 bytes.
+  * @attention src_addr is the block number (4 bytes per block). So when reading data
+  *            at the beginning of the user data segment, src_addr will be 256/4 = 64,
+  *            n will be data length.
+  *
+  * @param     uint8 src : source address of rtc memory, src_addr >= 64
+  * @param     void *dst : data pointer
+  * @param     uint16 n : data length, unit: byte
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool system_rtc_mem_read(uint8 src, void *dst, uint16 n);
+
+/**
+  * @brief     Write user data to  the RTC memory.
+  *
+  *            During deep-sleep, only RTC is working. So users can store their data
+  *            in RTC memory if it is needed. The user data segment below (512 bytes)
+  *            is used to store the user data.
+  *
+  *            |<---- system data(256 bytes) ---->|<----------- user data(512 bytes) --------->|
+  *
+  * @attention Read and write unit for data stored in the RTC memory is 4 bytes.
+  * @attention src_addr is the block number (4 bytes per block). So when storing data
+  *            at the beginning of the user data segment, src_addr will be 256/4 = 64,
+  *            n will be data length.
+  *
+  * @param     uint8 src : source address of rtc memory, src_addr >= 64
+  * @param     void *dst : data pointer
+  * @param     uint16 n : data length, unit: byte
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool system_rtc_mem_write(uint8 dst, const void *src, uint16 n);
+
+/**
+  * @brief  UART0 swap.
+  *
+  *         Use MTCK as UART0 RX, MTDO as UART0 TX, so ROM log will not output from
+  *         this new UART0. We also need to use MTDO (U0RTS) and MTCK (U0CTS) as UART0 in hardware.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_uart_swap(void);
+
+/**
+  * @brief  Disable UART0 swap.
+  *
+  *         Use the original UART0, not MTCK and MTDO.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_uart_de_swap(void);
+
+/**
+  * @brief     Measure the input voltage of TOUT pin 6, unit : 1/1024 V.
+  *
+  * @attention 1. system_adc_read can only be called when the TOUT pin is connected
+  *               to the external circuitry, and the TOUT pin input voltage should
+  *               be limited to 0~1.0V.
+  * @attention 2. When the TOUT pin is connected to the external circuitry, the 107th
+  *               byte (vdd33_const) of esp_init_data_default.bin(0~127byte) should be
+  *               set as the real power voltage of VDD3P3 pin 3 and 4.
+  * @attention 3. The unit of vdd33_const is 0.1V, the effective value range is [18, 36];
+  *               if vdd33_const is in [0, 18) or (36, 255), 3.3V is used to optimize RF by default.
+  *
+  * @param     null
+  *
+  * @return    Input voltage of TOUT pin 6, unit : 1/1024 V
+  */
+uint16 system_adc_read(void);
+
+/**
+  * @brief     Measure the power voltage of VDD3P3 pin 3 and 4, unit : 1/1024 V.
+  *
+  * @attention 1. system_get_vdd33 depends on RF, please do not use it if RF is disabled.
+  * @attention 2. system_get_vdd33 can only be called when TOUT pin is suspended.
+  * @attention 3. The 107th byte in esp_init_data_default.bin (0~127byte) is named
+  *               as "vdd33_const", when TOUT pin is suspended vdd33_const must be
+  *               set as 0xFF, that is 255.
+  *
+  * @param     null
+  *
+  * @return    Power voltage of VDD33, unit : 1/1024 V
+  */
+uint16 system_get_vdd33(void);
+
+/**
+  * @brief  Write data into flash with protection.
+  *
+  *         Flash read/write has to be 4-bytes aligned.
+  *
+  *         Protection of flash read/write :
+  *             use 3 sectors (4KBytes per sector) to save  4KB data with protect,
+  *             sector 0 and sector 1 are data sectors, back up each other,
+  *             save data alternately, sector 2 is flag sector, point out which sector
+  *             is keeping the latest data, sector 0 or sector 1.
+  *
+  * @param  uint16 start_sec : start sector (sector 0) of the 3 sectors which are
+  *                            used for flash read/write protection.
+  *    - For example, in IOT_Demo we can use the 3 sectors (3 * 4KB) starting from flash
+  *      0x3D000 for flash read/write protection, so the parameter start_sec should be 0x3D
+  * @param  void *param : pointer of the data to be written
+  * @param  uint16 len : data length, should be less than a sector, which is 4 * 1024
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool system_param_save_with_protect(uint16 start_sec, void *param, uint16 len);
+
+/**
+  * @brief  Read the data saved into flash with the read/write protection.
+  *
+  *         Flash read/write has to be 4-bytes aligned.
+  *
+  *         Read/write protection of flash:
+  *             use 3 sectors (4KB per sector) to save  4KB data with protect, sector
+  *             0 and sector 1 are data sectors, back up each other, save data alternately,
+  *             sector 2 is flag sector, point out which sector is keeping the latest data,
+  *             sector 0 or sector 1.
+  *
+  * @param  uint16 start_sec : start sector (sector 0) of the 3 sectors used for
+  *                            flash read/write protection. It cannot be sector 1 or sector 2.
+  *    - For example, in IOT_Demo, the 3 sectors (3 * 4KB) starting from flash 0x3D000
+  *      can be used for flash read/write protection.
+  *      The parameter start_sec is 0x3D, and it cannot be 0x3E or 0x3F.
+  * @param  uint16 offset : offset of data saved in sector
+  * @param  void *param : data pointer
+  * @param  uint16 len : data length, offset + len =< 4 * 1024
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool system_param_load(uint16 start_sec, uint16 offset, void *param, uint16 len);
+
+/**
+  * @brief  Set the maximum value of RF TX Power, unit : 0.25dBm.
+  *
+  * @param  uint8 max_tpw : the maximum value of RF Tx Power, unit : 0.25dBm, range [0, 82].
+  *                         It can be set refer to the 34th byte (target_power_qdb_0)
+  *                         of esp_init_data_default.bin(0~127byte)
+  *
+  * @return null
+  */
+void system_phy_set_max_tpw(uint8 max_tpw);
+
+/**
+  * @brief     Adjust the RF TX Power according to VDD33, unit : 1/1024 V.
+  *
+  * @attention 1. When TOUT pin is suspended, VDD33 can be measured by system_get_vdd33.
+  * @attention 2. When TOUT pin is connected to the external circuitry, system_get_vdd33
+  *               can not be used to measure VDD33.
+  *
+  * @param     uint16 vdd33 : VDD33, unit : 1/1024V, range [1900, 3300]
+  *
+  * @return    null
+  */
+void system_phy_set_tpw_via_vdd33(uint16 vdd33);
+
+/**
+  * @brief     Enable RF or not when wakeup from deep-sleep.
+  *
+  * @attention 1. This API can only be called in user_rf_pre_init.
+  * @attention 2. Function of this API is similar to system_deep_sleep_set_option,
+  *               if they are both called, it will disregard system_deep_sleep_set_option
+  *               which is called before deep-sleep, and refer to system_phy_set_rfoption
+  *               which is called when deep-sleep wake up.
+  * @attention 3. Before calling this API, system_deep_sleep_set_option should be called
+  *               once at least.
+  *
+  * @param     uint8 option :
+  *    - 0 : Radio calibration after deep-sleep wake up depends on esp_init_data_default.bin (0~127byte) byte 108.
+  *    - 1 : Radio calibration is done after deep-sleep wake up; this increases the
+  *          current consumption.
+  *    - 2 : No radio calibration after deep-sleep wake up; this reduces the current consumption.
+  *    - 4 : Disable RF after deep-sleep wake up, just like modem sleep; this has the
+  *          least current consumption; the device is not able to transmit or receive
+  *          data after wake up.
+  *
+  * @return    null
+  */
+void system_phy_set_rfoption(uint8 option);
+
+/** @addtogroup Upgrade_APIs
+  * @{
+  */
+
+/**
+  * @brief  Check the user bin.
+  *
+  * @param  null
+  *
+  * @return 0x00 : UPGRADE_FW_BIN1, i.e. user1.bin
+  * @return 0x01 : UPGRADE_FW_BIN2, i.e. user2.bin
+  */
+uint8 system_upgrade_userbin_check(void);
+
+/**
+  * @brief  Reboot system to use the new software.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_upgrade_reboot(void);
+
+/**
+  * @brief  Check the upgrade status flag.
+  *
+  * @param  null
+  *
+  * @return #define UPGRADE_FLAG_IDLE      0x00
+  * @return #define UPGRADE_FLAG_START     0x01
+  * @return #define UPGRADE_FLAG_FINISH    0x02
+  */
+uint8 system_upgrade_flag_check();
+
+/**
+  * @brief     Set the upgrade status flag.
+  *
+  * @attention After downloading new softwares, set the flag to UPGRADE_FLAG_FINISH
+  *            and call system_upgrade_reboot to reboot the system in order to run
+  *            the new software.
+  *
+  * @param     uint8 flag:
+  *    - UPGRADE_FLAG_IDLE      0x00
+  *    - UPGRADE_FLAG_START     0x01
+  *    - UPGRADE_FLAG_FINISH    0x02
+  *
+  * @return    null
+  */
+void system_upgrade_flag_set(uint8 flag);
+
+/**
+  * @}
+  */
+
+/** \defgroup System_boot_APIs Boot APIs
+  * @brief boot APIs
+  */
+
+/** @addtogroup System_boot_APIs
+  * @{
+  */
+
+#define SYS_BOOT_ENHANCE_MODE   0   /**<  It can load and run firmware at any address, for Espressif factory test bin*/
+#define SYS_BOOT_NORMAL_MODE    1   /**<  It can only load and run at some addresses of user1.bin (or user2.bin)*/
+
+#define SYS_BOOT_NORMAL_BIN     0   /**<  user1.bin or user2.bin*/
+#define SYS_BOOT_TEST_BIN       1   /**<  can only be Espressif test bin*/
+
+/**
+  * @brief     Get information of the boot version.
+  *
+  * @attention If boot version >= 1.3 , users can enable the enhanced boot mode
+  *            (refer to system_restart_enhance).
+  *
+  * @param     null
+  *
+  * @return    Information of the boot version.
+  */
+uint8 system_get_boot_version(void);
+
+/**
+  * @brief  Get the address of the current running user bin (user1.bin or user2.bin).
+  *
+  * @param  null
+  *
+  * @return The address of the current running user bin.
+  */
+uint32 system_get_userbin_addr(void);
+
+/**
+  * @brief  Get the boot mode.
+  *
+  * @param  null
+  *
+  * @return #define SYS_BOOT_ENHANCE_MODE   0
+  * @return #define SYS_BOOT_NORMAL_MODE    1
+  */
+uint8 system_get_boot_mode(void);
+
+/**
+  * @brief     Restarts the system, and enters the enhanced boot mode.
+  *
+  * @attention SYS_BOOT_TEST_BIN is used for factory test during production; users
+  *            can apply for the test bin from Espressif Systems.
+  *
+  * @param     uint8 bin_type : type of bin
+  *    - #define SYS_BOOT_NORMAL_BIN      0   // user1.bin or user2.bin
+  *    - #define SYS_BOOT_TEST_BIN        1   // can only be Espressif test bin
+  * @param     uint32 bin_addr : starting address of the bin file
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool system_restart_enhance(uint8 bin_type, uint32 bin_addr);
+
+typedef enum {
+    FLASH_SIZE_4M_MAP_256_256 = 0,  /**<  Flash size : 4Mbits. Map : 256KBytes + 256KBytes */
+    FLASH_SIZE_2M,                  /**<  Flash size : 2Mbits. Map : 256KBytes */
+    FLASH_SIZE_8M_MAP_512_512,      /**<  Flash size : 8Mbits. Map : 512KBytes + 512KBytes */
+    FLASH_SIZE_16M_MAP_512_512,     /**<  Flash size : 16Mbits. Map : 512KBytes + 512KBytes */
+    FLASH_SIZE_32M_MAP_512_512,     /**<  Flash size : 32Mbits. Map : 512KBytes + 512KBytes */
+    FLASH_SIZE_16M_MAP_1024_1024,   /**<  Flash size : 16Mbits. Map : 1024KBytes + 1024KBytes */
+    FLASH_SIZE_32M_MAP_1024_1024,    /**<  Flash size : 32Mbits. Map : 1024KBytes + 1024KBytes */
+    FLASH_SIZE_32M_MAP_2048_2048,    /**<  attention: don't support now ,just compatible for nodemcu;
+                                           Flash size : 32Mbits. Map : 2048KBytes + 2048KBytes */
+    FLASH_SIZE_64M_MAP_1024_1024,     /**<  Flash size : 64Mbits. Map : 1024KBytes + 1024KBytes */
+    FLASH_SIZE_128M_MAP_1024_1024     /**<  Flash size : 128Mbits. Map : 1024KBytes + 1024KBytes */
+
+} flash_size_map;
+
+/**
+  * @brief  Get the current Flash size and Flash map.
+  *
+  *         Flash map depends on the selection when compiling, more details in document
+  *         "2A-ESP8266__IOT_SDK_User_Manual"
+  *
+  * @param  null
+  *
+  * @return enum flash_size_map
+  */
+flash_size_map system_get_flash_size_map(void);
+
+#define SYS_CPU_80MHZ   80
+#define SYS_CPU_160MHZ  160
+
+/**
+  * @brief  Set CPU frequency. Default is 80MHz.
+  *
+  *         System bus frequency is 80MHz, will not be affected by CPU frequency.
+  *         The frequency of UART, SPI, or other peripheral devices, are divided
+  *         from system bus frequency, so they will not be affected by CPU frequency either.
+  *
+  * @param  uint8 freq : CPU frequency, 80 or 160.
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool system_update_cpu_freq(uint8 freq);
+
+/**
+  * @brief  Get CPU frequency.
+  *
+  * @param  null
+  *
+  * @return CPU frequency, unit : MHz.
+  */
+uint8 system_get_cpu_freq(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_timer.h

@@ -0,0 +1,101 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESP_TIMER_H__
+#define __ESP_TIMER_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* timer related */
+typedef void os_timer_func_t(void *timer_arg);
+
+typedef struct _os_timer_t {
+    struct _os_timer_t *timer_next;
+    void               *timer_handle;
+    uint32             timer_expire;
+    uint32             timer_period;
+    os_timer_func_t    *timer_func;
+    bool               timer_repeat_flag;
+    void               *timer_arg;
+} os_timer_t;
+
+/** \defgroup Timer_APIs Software timer APIs
+  * @brief Software timer APIs
+  *
+  * Timers of the following interfaces are software timers. Functions of the timers are executed during the tasks.
+  * Since a task can be stopped, or be delayed because there are other tasks with higher priorities, the following os_timer interfaces cannot guarantee the precise execution of the timers.
+  *    -  For the same timer, os_timer_arm (or os_timer_arm_us)  cannot be invoked repeatedly. os_timer_disarm should be invoked first.
+  *    -  os_timer_setfn can only be invoked when the timer is not enabled, i.e., after  os_timer_disarm or before os_timer_arm (or os_timer_arm_us).
+  *
+  */
+
+/** @addtogroup Timer_APIs
+  * @{
+  */
+
+/**
+  * @brief     Set the timer callback function.
+  *
+  * @attention 1. The callback function must be set in order to enable the timer.
+  * @attention 2. Operating system scheduling is disabled in timer callback.
+  *
+  * @param     os_timer_t *ptimer : Timer structure
+  * @param     os_timer_func_t *pfunction : timer callback function
+  * @param     void *parg : callback function parameter
+  *
+  * @return    null
+  */
+void os_timer_setfn(os_timer_t *ptimer, os_timer_func_t *pfunction, void *parg);
+
+/**
+  * @brief  Enable the millisecond timer.
+  *
+  * @param  os_timer_t *ptimer : timer structure
+  * @param  uint32_t milliseconds : Timing, unit: millisecond, range: 5 ~ 0x68DB8
+  * @param  bool repeat_flag : Whether the timer will be invoked repeatedly or not
+  *
+  * @return null
+  */
+void os_timer_arm(os_timer_t *ptimer, uint32 msec, bool repeat_flag);
+
+/**
+  * @brief  Disarm the timer
+  *
+  * @param  os_timer_t *ptimer : Timer structure
+  *
+  * @return null
+  */
+void os_timer_disarm(os_timer_t *ptimer);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_wpa2.h

@@ -0,0 +1,52 @@
+#ifndef ESP_WPA2_H
+#define ESP_WPA2_H
+
+/**
+  * @brief  Set wpa2 enterprise authentication.
+  *
+  * @attention wpa2 enterprise authentication can only be used when ESP8266 station is enabled.
+  *            wpa2 enterprise authentication can only support PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
+  *
+  * @param  enable
+  *    - 1: enable wpa2 enterprise authentication;
+  *    - 0: disable wpa2 enterprise authentication
+  *
+  * @return  0: succeed
+            -1: fail
+  */
+int wifi_station_set_wpa2_enterprise_auth(int enable);
+
+/**
+  * @brief  Set username for PEAP/TTLS method.
+  *
+  * @param  username: point to address where stores the username;
+  *         len: length of username, limited to 1~127
+  *
+  * @return  0: succeed
+  *         -1: fail(len <= 0 or len >= 128)
+  *         -2: fail(internal memory malloc fail)
+  */
+int wifi_station_set_enterprise_username(unsigned char *username, int len);
+
+/**
+  * @brief  Set password for PEAP/TTLS method..
+  *
+  * @param  password: point to address where stores the password;
+  *         len: length of password
+  *
+  * @return  0: succeed
+  *         -1: fail(len <= 0)
+  *         -2: fail(internal memory malloc fail)
+  */
+int wifi_station_set_enterprise_password(unsigned char *password, int len);
+
+/**
+  * @brief  Set CA certificate for PEAP/TTLS method.
+  *
+  * @param  ca_cert: point to address where stores the CA certificate;
+  *
+  * @return 0: succeed
+  */
+int wifi_station_set_enterprise_ca_cert(unsigned char *ca_cert, int len);
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/esp_wps.h

@@ -0,0 +1,139 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESPWPS_H__
+#define __ESPWPS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup WiFi_APIs WiFi Related APIs
+  * @brief WiFi APIs
+  */
+
+/** @addtogroup WiFi_APIs
+  * @{
+  */
+
+/** \defgroup WPS_APIs  WPS APIs
+  * @brief ESP8266 WPS APIs
+  *
+  * WPS can only be used when ESP8266 station is enabled.
+  *
+  */
+
+/** @addtogroup WPS_APIs
+  * @{
+  */
+
+typedef enum wps_type {
+    WPS_TYPE_DISABLE = 0,
+    WPS_TYPE_PBC,
+    WPS_TYPE_PIN,
+    WPS_TYPE_DISPLAY,
+    WPS_TYPE_MAX,
+} WPS_TYPE_t;
+
+enum wps_cb_status {
+    WPS_CB_ST_SUCCESS = 0,     /**< WPS succeed */
+    WPS_CB_ST_FAILED,          /**< WPS fail */
+    WPS_CB_ST_TIMEOUT,         /**< WPS timeout, fail */
+    WPS_CB_ST_WEP,             /**< WPS failed because that WEP is not supported */
+    WPS_CB_ST_SCAN_ERR,        /**< can not find the target WPS AP */
+};
+
+/**
+  * @brief     Enable Wi-Fi WPS function.
+  *
+  * @attention WPS can only be used when ESP8266 station is enabled.
+  *
+  * @param     WPS_TYPE_t wps_type : WPS type, so far only WPS_TYPE_PBC is supported
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool wifi_wps_enable(WPS_TYPE_t wps_type);
+
+/**
+  * @brief  Disable Wi-Fi WPS function and release resource it taken.
+  *
+  * @param  null
+  *
+  * @return true  : succeed
+  * @return false : fail
+  */
+bool wifi_wps_disable(void);
+
+/**
+  * @brief     WPS starts to work.
+  *
+  * @attention WPS can only be used when ESP8266 station is enabled.
+  *
+  * @param     null
+  *
+  * @return    true  : WPS starts to work successfully, but does not mean WPS succeed.
+  * @return    false : fail
+  */
+bool wifi_wps_start(void);
+
+/**
+  * @brief  WPS callback.
+  *
+  * @param  int status : status of WPS, enum wps_cb_status.
+  *    -  If parameter status == WPS_CB_ST_SUCCESS in WPS callback, it means WPS got AP's
+  *       information, user can call wifi_wps_disable to disable WPS and release resource,
+  *       then call wifi_station_connect to connect to target AP.
+  *    -  Otherwise, it means that WPS fail, user can create a timer to retry WPS by
+  *       wifi_wps_start after a while, or call wifi_wps_disable to disable WPS and release resource.
+  *
+  * @return null
+  */
+typedef void (*wps_st_cb_t)(int status);
+
+/**
+  * @brief     Set WPS callback.
+  *
+  * @attention WPS can only be used when ESP8266 station is enabled.
+  *
+  * @param     wps_st_cb_t cb : callback.
+  *
+  * @return    true  : WPS starts to work successfully, but does not mean WPS succeed.
+  * @return    false : fail
+  */
+bool wifi_set_wps_cb(wps_st_cb_t cb);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/espconn.h

@@ -0,0 +1,704 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESPCONN_H__
+#define __ESPCONN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef sint8 err_t;
+
+typedef void *espconn_handle;
+
+/** \defgroup Espconn_APIs Network Espconn APIs
+  * @brief Network espconn APIs
+  *
+  */
+
+/** @addtogroup Espconn_APIs
+  * @{
+  */
+
+/**
+  * @brief     Connect callback.
+  *
+  *            Callback which will be called if successful listening (ESP8266 as TCP server)
+  *            or connection (ESP8266 as TCP client) callback, register by espconn_regist_connectcb.
+  *
+  * @attention The pointer "void *arg" may be different in different callbacks, please don't
+  *            use this pointer directly to distinguish one from another in multiple connections,
+  *            use remote_ip and remote_port in espconn instead.
+  *
+  * @param     void *arg : pointer corresponding structure espconn.
+  *
+  * @return    null
+  */
+typedef void (* espconn_connect_callback)(void *arg);
+
+/**
+  * @brief     Reconnect callback.
+  *
+  *            Enter this callback when error occurred, TCP connection broke. This callback is
+  *            registered by espconn_regist_reconcb.
+  *
+  * @attention The pointer "void *arg" may be different in different callbacks, please don't
+  *            use this pointer directly to distinguish one from another in multiple connections,
+  *            use remote_ip and remote_port in espconn instead.
+  *
+  * @param     void *arg : pointer corresponding structure espconn.
+  * @param     sint8 err : error code
+  *    -  ESCONN_TIMEOUT    - Timeout
+  *    -  ESPCONN_ABRT      - TCP connection aborted
+  *    -  ESPCONN_RST       - TCP connection abort
+  *    -  ESPCONN_CLSD      - TCP connection closed
+  *    -  ESPCONN_CONN      - TCP connection
+  *    -  ESPCONN_HANDSHAKE - TCP SSL handshake fail
+  *    -  ESPCONN_PROTO_MSG - SSL application invalid
+  *
+  * @return  null
+  */
+typedef void (* espconn_reconnect_callback)(void *arg, sint8 err);
+
+/* Definitions for error constants. */
+
+#define ESPCONN_OK           0  /**< No error, everything OK.   */
+#define ESPCONN_MEM         -1  /**< Out of memory.             */
+#define ESPCONN_TIMEOUT     -3  /**< Timeout.                   */
+#define ESPCONN_RTE         -4  /**< Routing problem.           */
+#define ESPCONN_INPROGRESS  -5  /**< Operation in progress.     */
+#define ESPCONN_MAXNUM      -7  /**< Total number exceeds the maximum limitation. */
+
+#define ESPCONN_ABRT        -8  /**< Connection aborted.    */
+#define ESPCONN_RST         -9  /**< Connection reset.      */
+#define ESPCONN_CLSD       -10  /**< Connection closed.     */
+#define ESPCONN_CONN       -11  /**< Not connected.         */
+
+#define ESPCONN_ARG        -12  /**< Illegal argument.      */
+#define ESPCONN_IF         -14  /**< UDP send error.        */
+#define ESPCONN_ISCONN     -15  /**< Already connected.     */
+
+/** Protocol family and type of the espconn */
+enum espconn_type {
+    ESPCONN_INVALID = 0,     /**< invalid type  */
+    ESPCONN_TCP     = 0x10,  /**< TCP           */
+    ESPCONN_UDP     = 0x20,  /**< UDP           */
+};
+
+/** Current state of the espconn. */
+enum espconn_state {
+    ESPCONN_NONE,        /**< idle state, no connection */
+    ESPCONN_WAIT,        /**< ESP8266 is as TCP client, and waiting for connection */
+    ESPCONN_LISTEN,      /**< ESP8266 is as TCP server, and waiting for connection */
+    ESPCONN_CONNECT,     /**< connected         */
+    ESPCONN_WRITE,       /**< sending data      */
+    ESPCONN_READ,        /**< receiving data    */
+    ESPCONN_CLOSE        /**< connection closed */
+};
+
+typedef struct _esp_tcp {
+    int remote_port;      /**< remote port of TCP connection            */
+    int local_port;       /**< ESP8266's local port of TCP connection   */
+    uint8 local_ip[4];    /**< local IP of ESP8266                      */
+    uint8 remote_ip[4];   /**< remote IP of TCP connection              */
+    espconn_connect_callback connect_callback;      /**< connected callback */
+    espconn_reconnect_callback reconnect_callback;  /**< as error handler, the TCP connection broke unexpectedly */
+    espconn_connect_callback disconnect_callback;   /**< disconnected callback */
+    espconn_connect_callback write_finish_fn;       /**< data send by espconn_send has wrote into buffer waiting for sending, or has sent successfully */
+} esp_tcp;
+
+typedef struct _esp_udp {
+    int remote_port;    /**< remote port of UDP transmission            */
+    int local_port;     /**< ESP8266's local port for UDP transmission  */
+    uint8 local_ip[4];  /**< local IP of ESP8266                        */
+    uint8 remote_ip[4]; /**< remote IP of UDP transmission              */
+} esp_udp;
+
+typedef struct _remot_info {
+    enum espconn_state state;   /**< state of espconn   */
+    int remote_port;            /**< remote port        */
+    uint8 remote_ip[4];         /**< remote IP address  */
+} remot_info;
+
+/** A callback prototype to inform about events for a espconn */
+typedef void (* espconn_recv_callback)(void *arg, char *pdata, unsigned short len);
+typedef void (* espconn_sent_callback)(void *arg);
+
+/** A espconn descriptor */
+struct espconn {
+    enum espconn_type type;     /**< type of the espconn (TCP or UDP)   */
+    enum espconn_state state;   /**< current state of the espconn       */
+    union {
+        esp_tcp *tcp;
+        esp_udp *udp;
+    } proto;
+    espconn_recv_callback recv_callback;    /**< data received callback */
+    espconn_sent_callback sent_callback;    /**< data sent callback     */
+    uint8 link_cnt;         /**< link count             */
+    void *reserve;          /**< reserved for user data */
+};
+
+enum espconn_option {
+    ESPCONN_START     = 0x00,   /**< no option, start enum. */
+    ESPCONN_REUSEADDR = 0x01,   /**< free memory after TCP disconnection happen, need not wait 2 minutes. */
+    ESPCONN_NODELAY   = 0x02,   /**< disable nagle algorithm during TCP data transmission, quicken the data transmission. */
+    ESPCONN_COPY      = 0x04,   /**< enable espconn_regist_write_finish, enter write_finish_callback means that the data espconn_send sending was written into 2920 bytes write-buffer waiting for sending or already sent. */
+    ESPCONN_KEEPALIVE = 0x08,   /**< enable TCP keep alive.    */
+    ESPCONN_END                 /**< no option, end enum.      */
+};
+
+enum espconn_level {
+    ESPCONN_KEEPIDLE,   /**< TCP keep-alive interval, unit : second.                */
+    ESPCONN_KEEPINTVL,  /**< packet interval during TCP keep-alive, unit : second.  */
+    ESPCONN_KEEPCNT     /**< maximum packet retry count of TCP keep-alive.          */
+};
+
+enum {
+    ESPCONN_IDLE = 0,
+    ESPCONN_CLIENT,
+    ESPCONN_SERVER,
+    ESPCONN_BOTH,
+    ESPCONN_MAX
+};
+
+/**
+  * @brief     espconn initialization.
+  *
+  * @attention   Please call this API in user_init, if you need to use espconn functions.
+  *
+  * @param     null
+  *
+  * @return    null
+  */
+void espconn_init(void);
+
+/**
+  * @brief     Connect to a TCP server (ESP8266 acting as TCP client).
+  *
+  * @attention If espconn_connect fail, returns non-0 value, there is no connection, so it
+  *            won't enter any espconn callback.
+  *
+  * @param     struct espconn *espconn : the network connection structure,  the espconn to
+  *            listen to the connection
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_RTE    - Routing Problem
+  *    -  ESPCONN_MEM    - Out of memory
+  *    -  ESPCONN_ISCONN - Already connected
+  *    -  ESPCONN_ARG    - illegal argument, can't find the corresponding TCP connection
+  *                        according to structure espconn
+  */
+sint8 espconn_connect(struct espconn *espconn);
+
+/**
+  * @brief     Disconnect a TCP connection.
+  *
+  * @attention Don't call this API in any espconn callback. If needed, please use system
+  *            task to trigger espconn_disconnect.
+  *
+  * @param     struct espconn *espconn : the network connection structure
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection
+  *                     according to structure espconn
+  */
+sint8 espconn_disconnect(struct espconn *espconn);
+
+/**
+  * @brief     Delete a transmission.
+  *
+  * @attention Corresponding creation API :
+  *    -  TCP: espconn_accept,
+  *    -  UDP: espconn_create
+  *
+  * @param     struct espconn *espconn : the network connection structure
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding network according
+  *                     to structure espconn
+  *    -  ESPCONN_INPROGRESS - the connection is still in progress, please call espconn_disconnect
+  *                     to disconnect before delete it.
+  */
+sint8 espconn_delete(struct espconn *espconn);
+
+/**
+  * @brief  Creates a TCP server (i.e. accepts connections).
+  *
+  * @param  struct espconn *espconn : the network connection structure
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_MEM    - Out of memory
+  *    -  ESPCONN_ISCONN - Already connected
+  *    -  ESPCONN_ARG    - illegal argument, can't find the corresponding TCP connection
+  *                        according to structure espconn
+  */
+sint8 espconn_accept(struct espconn *espconn);
+
+/**
+  * @brief     Create UDP transmission.
+  *
+  * @attention Parameter remote_ip and remote_port need to be set, do not set to be 0.
+  *
+  * @param     struct espconn *espconn : the UDP control block structure
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_MEM    - Out of memory
+  *    -  ESPCONN_ISCONN - Already connected
+  *    -  ESPCONN_ARG    - illegal argument, can't find the corresponding UDP transmission
+  *                        according to structure espconn
+  */
+sint8 espconn_create(struct espconn *espconn);
+
+/**
+  * @brief  Get maximum number of how many TCP connections are allowed.
+  *
+  * @param  null
+  *
+  * @return Maximum number of how many TCP connections are allowed.
+  */
+uint8 espconn_tcp_get_max_con(void);
+
+/**
+  * @brief  Set the maximum number of how many TCP connection is allowed.
+  *
+  * @param  uint8 num : Maximum number of how many TCP connection is allowed.
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection
+  *                     according to structure espconn
+  */
+sint8 espconn_tcp_set_max_con(uint8 num);
+
+/**
+  * @brief  Get the maximum number of TCP clients which are allowed to connect to ESP8266 TCP server.
+  *
+  * @param  struct espconn *espconn : the TCP server structure
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_tcp_get_max_con_allow(struct espconn *espconn);
+
+/**
+  * @brief  Set the maximum number of TCP clients allowed to connect to ESP8266 TCP server.
+  *
+  * @param  struct espconn *espconn : the TCP server structure
+  * @param  uint8 num : Maximum number of TCP clients which are allowed
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_tcp_set_max_con_allow(struct espconn *espconn, uint8 num);
+
+/**
+  * @brief     Register timeout interval of ESP8266 TCP server.
+  *
+  * @attention 1. If timeout is set to 0, timeout will be disable and ESP8266 TCP server will
+  *               not disconnect TCP clients has stopped communication. This usage of timeout=0,
+  *               is deprecated.
+  * @attention 2. This timeout interval is not very precise, only as reference.
+  *
+  * @param     struct espconn *espconn : the TCP connection structure
+  * @param     uint32 interval : timeout interval, unit: second, maximum: 7200 seconds
+  * @param     uint8 type_flag : 0, set for all connections; 1, set for a specific connection
+  *    -  If the type_flag set to be 0, please call this API after espconn_accept, before listened
+  *       a TCP connection.
+  *    -  If the type_flag set to be 1, the first parameter *espconn is the specific connection.
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_regist_time(struct espconn *espconn, uint32 interval, uint8 type_flag);
+
+/**
+  * @brief  Get the information about a TCP connection or UDP transmission.
+  *
+  * @param  struct espconn *espconn : the network connection structure
+  * @param  remot_info **pcon_info : connect to client info
+  * @param  uint8 typeflags : 0, regular server; 1, ssl server
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding transmission according to
+  *                     structure espconn
+  */
+sint8 espconn_get_connection_info(struct espconn *pespconn, remot_info **pcon_info, uint8 typeflags);
+
+/**
+  * @brief  Register data sent callback which will be called back when data are successfully sent.
+  *
+  * @param  struct espconn *espconn : the network connection structure
+  * @param  espconn_sent_callback sent_cb : registered callback function which will be called if
+  *                                         the data is successfully sent
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding transmission according
+  *                     to structure espconn
+  */
+sint8 espconn_regist_sentcb(struct espconn *espconn, espconn_sent_callback sent_cb);
+
+/**
+  * @brief  Register a callback which will be called when all sending TCP data is completely
+  *         write into write-buffer or sent.
+  *
+  *         Need to call espconn_set_opt to enable write-buffer first.
+  *
+  * @attention 1. write-buffer is used to keep TCP data that waiting to be sent, queue number
+  *               of the write-buffer is 8 which means that it can keep 8 packets at most.
+  *               The size of write-buffer is 2920 bytes.
+  * @attention 2. Users can enable it by using espconn_set_opt.
+  * @attention 3. Users can call espconn_send to send the next packet in write_finish_callback
+  *               instead of using espconn_sent_callback.
+  *
+  * @param     struct espconn *espconn : the network connection structure
+  * @param     espconn_connect_callback write_finish_fn : registered callback function which will
+  *                                                       be called if the data is completely write
+  *                                                       into write buffer or sent.
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_regist_write_finish(struct espconn *espconn, espconn_connect_callback write_finish_fn);
+
+/**
+  * @brief     Send data through network.
+  *
+  * @attention 1. Please call espconn_send after espconn_sent_callback of the pre-packet.
+  * @attention 2. If it is a UDP transmission, it is suggested to set espconn->proto.udp->remote_ip
+  *               and remote_port before every calling of espconn_send.
+  *
+  * @param     struct espconn *espconn : the network connection structure
+  * @param     uint8 *psent : pointer of data
+  * @param     uint16 length : data length
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_MEM    - Out of memory
+  *    -  ESPCONN_ARG    - illegal argument, can't find the corresponding network transmission
+  *                        according to structure espconn
+  *    -  ESPCONN_MAXNUM - buffer of sending data is full
+  *    -  ESPCONN_IF     - send UDP data fail
+  */
+sint8 espconn_send(struct espconn *espconn, uint8 *psent, uint16 length);
+
+/**
+  * @brief     Send data through network.
+  *
+  *            This API is deprecated, please use espconn_send instead.
+  *
+  * @attention 1. Please call espconn_sent after espconn_sent_callback of the pre-packet.
+  * @attention 2. If it is a UDP transmission, it is suggested to set espconn->proto.udp->remote_ip
+  *               and remote_port before every calling of espconn_sent.
+  *
+  * @param     struct espconn *espconn : the network connection structure
+  * @param     uint8 *psent : pointer of data
+  * @param     uint16 length : data length
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_MEM    - Out of memory
+  *    -  ESPCONN_ARG    - illegal argument, can't find the corresponding network transmission
+  *                        according to structure espconn
+  *    -  ESPCONN_MAXNUM - buffer of sending data is full
+  *    -  ESPCONN_IF     - send UDP data fail
+  */
+sint8 espconn_sent(struct espconn *espconn, uint8 *psent, uint16 length);
+
+/**
+  * @brief  Send UDP data.
+  *
+  * @param  struct espconn *espconn : the UDP structure
+  * @param  uint8 *psent : pointer of data
+  * @param  uint16 length : data length
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_MEM    - Out of memory
+  *    -  ESPCONN_MAXNUM - buffer of sending data is full
+  *    -  ESPCONN_IF     - send UDP data fail
+  */
+sint16 espconn_sendto(struct espconn *espconn, uint8 *psent, uint16 length);
+
+/**
+  * @brief  Register connection function which will be called back under successful TCP connection.
+  *
+  * @param  struct espconn *espconn : the TCP connection structure
+  * @param  espconn_connect_callback connect_cb : registered callback function
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_regist_connectcb(struct espconn *espconn, espconn_connect_callback connect_cb);
+
+/**
+  * @brief  register data receive function which will be called back when data are received.
+  *
+  * @param  struct espconn *espconn : the network transmission structure
+  * @param  espconn_recv_callback recv_cb : registered callback function
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_regist_recvcb(struct espconn *espconn, espconn_recv_callback recv_cb);
+
+/**
+  * @brief     Register reconnect callback.
+  *
+  * @attention espconn_reconnect_callback is more like a network-broken error handler; it handles
+  *            errors that occurs in any phase of the connection.
+  *            For instance, if espconn_send fails, espconn_reconnect_callback will be called
+  *            because the network is broken.
+  *
+  * @param  struct espconn *espconn : the TCP connection structure
+  * @param  espconn_reconnect_callback recon_cb : registered callback function
+  *
+  * @return  0     : succeed
+  * @return  Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_regist_reconcb(struct espconn *espconn, espconn_reconnect_callback recon_cb);
+
+/**
+  * @brief  Register disconnection function which will be called back under successful TCP
+  *         disconnection.
+  *
+  * @param  struct espconn *espconn : the TCP connection structure
+  * @param  espconn_connect_callback discon_cb : registered callback function
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_regist_disconcb(struct espconn *espconn, espconn_connect_callback discon_cb);
+
+/**
+  * @brief  Get an available port for network.
+  *
+  * @param  null
+  *
+  * @return Port number.
+  */
+uint32 espconn_port(void);
+
+/**
+  * @brief     Set option of TCP connection.
+  *
+  * @attention In general, we need not call this API. If call espconn_set_opt, please call
+  *            it in espconn_connect_callback.
+  *
+  * @param     struct espconn *espconn : the TCP connection structure
+  * @param     uint8 opt : option of TCP connection, refer to enum espconn_option
+  *    -  bit 0: 1: free memory after TCP disconnection happen need not wait 2 minutes;
+  *    -  bit 1: 1: disable nagle algorithm during TCP data transmission, quiken the data transmission.
+  *    -  bit 2: 1: enable espconn_regist_write_finish, enter write finish callback means
+  *                 the data espconn_send sending was written into 2920 bytes write-buffer
+  *                 waiting for sending or already sent.
+  *    -  bit 3: 1: enable TCP keep alive
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_set_opt(struct espconn *espconn, uint8 opt);
+
+/**
+  * @brief  Clear option of TCP connection.
+  *
+  * @param  struct espconn *espconn : the TCP connection structure
+  * @param  uint8 opt : enum espconn_option
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_clear_opt(struct espconn *espconn, uint8 opt);
+
+/**
+  * @brief     Set configuration of TCP keep alive.
+  *
+  * @attention In general, we need not call this API. If needed, please call it in
+  *            espconn_connect_callback and call espconn_set_opt to enable keep alive first.
+  *
+  * @param     struct espconn *espconn : the TCP connection structure
+  * @param     uint8 level : To do TCP keep-alive detection every ESPCONN_KEEPIDLE. If there
+  *                          is no response, retry ESPCONN_KEEPCNT times every ESPCONN_KEEPINTVL.
+  *                          If still no response, considers it as TCP connection broke, goes
+  *                          into espconn_reconnect_callback. Notice, keep alive interval is not
+  *                          precise, only for reference, it depends on priority.
+  * @param     void* optarg : value of parameter
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_set_keepalive(struct espconn *espconn, uint8 level, void *optarg);
+
+/**
+  * @brief  Get configuration of TCP keep alive.
+  *
+  * @param  struct espconn *espconn : the TCP connection structure
+  * @param  uint8 level : enum espconn_level
+  * @param  void* optarg : value of parameter
+  *
+  * @return 0     : succeed
+  * @return Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection according
+  *                     to structure espconn
+  */
+sint8 espconn_get_keepalive(struct espconn *espconn, uint8 level, void *optarg);
+
+/**
+  * @brief  Callback which is invoked when a hostname is found.
+  *
+  * @param  const char *name : hostname
+  * @param  ip_addr_t *ipaddr : IP address of the hostname, or to be NULL if the name could
+  *                             not be found (or on any other error).
+  * @param  void *callback_arg : callback argument.
+  *
+  * @return null
+  */
+typedef void (*dns_found_callback)(const char *name, ip_addr_t *ipaddr, void *callback_arg);
+
+/**
+  * @brief  DNS function.
+  *
+  *         Parse a hostname (string) to an IP address.
+  *
+  * @param  struct espconn *pespconn : espconn to parse a hostname.
+  * @param  const char *hostname : the hostname.
+  * @param  ip_addr_t *addr : IP address.
+  * @param  dns_found_callback found : callback of DNS
+  *
+  * @return err_t :
+  *    -  ESPCONN_OK - succeed
+  *    -  ESPCONN_INPROGRESS - error code : already connected
+  *    -  ESPCONN_ARG - error code : illegal argument, can't find network transmission
+  *                     according to structure espconn
+  */
+err_t espconn_gethostbyname(struct espconn *pespconn, const char *hostname, ip_addr_t *addr, dns_found_callback found);
+
+/**
+  * @brief     Join a multicast group.
+  *
+  * @attention This API can only be called after the ESP8266 station connects to a router.
+  *
+  * @param     ip_addr_t *host_ip :  IP of UDP host
+  * @param     ip_addr_t *multicast_ip :  IP of multicast group
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_MEM - Out of memory
+  */
+sint8 espconn_igmp_join(ip_addr_t *host_ip, ip_addr_t *multicast_ip);
+
+/**
+  * @brief     Leave a multicast group.
+  *
+  * @attention This API can only be called after the ESP8266 station connects to a router.
+  *
+  * @param     ip_addr_t *host_ip :  IP of UDP host
+  * @param     ip_addr_t *multicast_ip :  IP of multicast group
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_MEM - Out of memory
+  */
+sint8 espconn_igmp_leave(ip_addr_t *host_ip, ip_addr_t *multicast_ip);
+
+/**
+  * @brief     Puts in a request to block the TCP receive function.
+  *
+  * @attention The function does not act immediately; we recommend calling it while
+  *            reserving 5*1460 bytes of memory. This API can be called more than once.
+  *
+  * @param     struct espconn *espconn : corresponding TCP connection structure
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection
+  *                     according to structure espconn.
+  */
+sint8 espconn_recv_hold(struct espconn *pespconn);
+
+/**
+  * @brief     Unblock TCP receiving data (i.e. undo espconn_recv_hold).
+  *
+  * @attention This API takes effect immediately.
+  *
+  * @param     struct espconn *espconn : corresponding TCP connection structure
+  *
+  * @return    0     : succeed
+  * @return    Non-0 : error code
+  *    -  ESPCONN_ARG - illegal argument, can't find the corresponding TCP connection
+  *                     according to structure espconn.
+  */
+sint8 espconn_recv_unhold(struct espconn *pespconn);
+
+/**
+  * @brief     Set default DNS server. Two DNS server is allowed to be set.
+  *
+  * @attention Only if ESP8266 DHCP client is disabled (wifi_station_dhcpc_stop),
+  *            this API can be used.
+  *
+  * @param     char numdns : DNS server ID, 0 or 1
+  * @param     ip_addr_t *dnsserver : DNS server IP
+  *
+  * @return    null
+  */
+void espconn_dns_setserver(char numdns, ip_addr_t *dnsserver);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/espnow.h

@@ -0,0 +1,351 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __ESPNOW_H__
+#define __ESPNOW_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup ESPNow_APIs ESP-NOW APIs
+  * @brief ESP-NOW APIs
+  *
+  * @attention 1. ESP-NOW do not support broadcast and multicast.
+  * @attention 2. ESP-NOW is targeted to Smart-Light project, so it is suggested
+  *               that slave role corresponding to soft-AP or soft-AP+station mode,
+  *               controller role corresponding to station mode.
+  * @attention 3. When ESP8266 is in soft-AP+station mode, it will communicate through
+  *               station interface if it is in slave role, and communicate through
+  *               soft-AP interface if it is in controller role.
+  * @attention 4. ESP-NOW can not wake ESP8266 up from sleep, so if the target ESP8266
+  *               station is in sleep, ESP-NOW communication will fail.
+  * @attention 5. In station mode, ESP8266 supports 10 encrypt ESP-NOW peers at most,
+  *               with the unencrypted peers, it can be 20 peers in total at most.
+  * @attention 6. In the soft-AP mode or soft-AP + station mode, the ESP8266 supports
+  *               6 encrypt ESP-NOW peers at most, with the unencrypted peers, it can
+  *               be 20 peers in total at most.
+  *
+  */
+
+/** @addtogroup ESPNow_APIs
+  * @{
+  */
+
+enum esp_now_role {
+    ESP_NOW_ROLE_IDLE = 0,
+    ESP_NOW_ROLE_CONTROLLER,
+    ESP_NOW_ROLE_SLAVE,
+    ESP_NOW_ROLE_MAX,
+};
+
+/**
+  * @brief     ESP-NOW send callback.
+  *
+  * @attention The status will be OK, if ESP-NOW send packet successfully. But users
+  *            need to make sure by themselves that key of communication is correct.
+  *
+  * @param     uint8 *mac_addr : MAC address of target device
+  * @param     uint8 *data     : data received
+  * @param     uint8 len       : data length
+  *
+  * @return null
+  */
+typedef void (*esp_now_recv_cb_t)(uint8 *mac_addr, uint8 *data, uint8 len);
+
+/**
+  * @brief     ESP-NOW send callback.
+  *
+  * @attention The status will be OK, if ESP-NOW send packet successfully. But users
+  *            need to make sure by themselves that key of communication is correct.
+  *
+  * @param     uint8 *mac_addr : MAC address of target device
+  * @param     uint8 status    : status of ESP-NOW sending packet, 0, OK; 1, fail.
+  *
+  * @return    null
+  */
+typedef void (*esp_now_send_cb_t)(uint8 *mac_addr, uint8 status);
+
+/**
+  * @brief  ESP-NOW initialization.
+  *
+  * @param  null
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_init(void);
+
+/**
+  * @brief  Deinitialize ESP-NOW.
+  *
+  * @param  null
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_deinit(void);
+
+/**
+  * @brief  Register ESP-NOW send callback.
+  *
+  * @param  esp_now_send_cb_t cb : send callback
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_register_send_cb(esp_now_send_cb_t cb);
+
+/**
+  * @brief  Unregister ESP-NOW send callback.
+  *
+  * @param  null
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_unregister_send_cb(void);
+
+/**
+  * @brief  Register ESP-NOW receive callback.
+  *
+  * @param  esp_now_recv_cb_t cb : receive callback
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_register_recv_cb(esp_now_recv_cb_t cb);
+
+/**
+  * @brief  Unregister ESP-NOW receive callback.
+  *
+  * @param  null
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_unregister_recv_cb(void);
+
+/**
+  * @brief  Send ESP-NOW packet.
+  *
+  * @param  uint8 *da   : destination MAC address.
+  *                       If it's NULL, send packet to all MAC addresses recorded
+  *                       by ESP-NOW; otherwise, send packet to target MAC address.
+  * @param  uint8 *data : data need to send
+  * @param  uint8 len   : data length
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_send(uint8 *da, uint8 *data, uint8 len);
+
+/**
+  * @brief  Add an ESP-NOW peer, store MAC address of target device into ESP-NOW MAC list.
+  *
+  * @param  uint8 *mac_addr : MAC address of device
+  * @param  uint8 role      : role type of device, enum esp_now_role
+  * @param  uint8 channel   : channel of device
+  * @param  uint8 *key      : 16 bytes key which is needed for ESP-NOW communication
+  * @param  uint8 key_len   : length of key, has to be 16 bytes now
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_add_peer(uint8 *mac_addr, uint8 role, uint8 channel, uint8 *key, uint8 key_len);
+
+/**
+  * @brief  Delete an ESP-NOW peer, delete MAC address of the device from ESP-NOW MAC list.
+  *
+  * @param  u8 *mac_addr : MAC address of device
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_del_peer(uint8 *mac_addr);
+
+/**
+  * @brief  Set ESP-NOW role of device itself.
+  *
+  * @param  uint8 role : role type of device, enum esp_now_role.
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_set_self_role(uint8 role);
+
+/**
+  * @brief  Get ESP-NOW role of device itself.
+  *
+  * @param  uint8 role : role type of device, enum esp_now_role.
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_get_self_role(void);
+
+/**
+  * @brief  Set ESP-NOW role for a target device. If it is set multiple times,
+  *         new role will cover the old one.
+  *
+  * @param  uint8 *mac_addr : MAC address of device.
+  * @param  uint8 role      : role type, enum esp_now_role.
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_set_peer_role(uint8 *mac_addr, uint8 role);
+
+/**
+  * @brief  Get ESP-NOW role of a target device.
+  *
+  * @param  uint8 *mac_addr : MAC address of device.
+  *
+  * @return  ESP_NOW_ROLE_CONTROLLER, role type : controller
+  * @return  ESP_NOW_ROLE_SLAVE, role type : slave
+  * @return  otherwise : fail
+  */
+sint32 esp_now_get_peer_role(uint8 *mac_addr);
+
+/**
+  * @brief  Record channel information of a ESP-NOW device.
+  *
+  * When communicate with this device,
+  *    -  call esp_now_get_peer_channel to get its channel first,
+  *    -  then call wifi_set_channel to be in the same channel and do communication.
+  *
+  * @param  uint8 *mac_addr : MAC address of target device.
+  * @param  uint8 channel   : channel, usually to be 1 ~ 13, some area may use channel 14.
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_set_peer_channel(uint8 *mac_addr, uint8 channel);
+
+/**
+  * @brief  Get channel information of a ESP-NOW device.
+  *
+  * @attention ESP-NOW communication needs to be at the same channel.
+  *
+  * @param  uint8 *mac_addr : MAC address of target device.
+  *
+  * @return 1 ~ 13 (some area may get 14) : channel number
+  * @return Non-0 : fail
+  */
+sint32 esp_now_get_peer_channel(uint8 *mac_addr);
+
+/**
+  * @brief  Set ESP-NOW key for a target device.
+  *
+  * If it is set multiple times, new key will cover the old one.
+  *
+  * @param  uint8 *mac_addr : MAC address of target device.
+  * @param  uint8 *key      : 16 bytes key which is needed for ESP-NOW communication,
+  *                           if it is NULL, current key will be reset to be none.
+  * @param  uint8 key_len   : key length, has to be 16 bytes now
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_set_peer_key(uint8 *mac_addr, uint8 *key, uint8 key_len);
+
+/**
+  * @brief  Get ESP-NOW key of a target device.
+  *
+  * If it is set multiple times, new key will cover the old one.
+  *
+  * @param  uint8 *mac_addr : MAC address of target device.
+  * @param  uint8 *key      : pointer of key, buffer size has to be 16 bytes at least
+  * @param  uint8 key_len   : key length
+  *
+  * @return 0   : succeed
+  * @return > 0 : find target device but can't get key
+  * @return < 0 : fail
+  */
+sint32 esp_now_get_peer_key(uint8 *mac_addr, uint8 *key, uint8 *key_len);
+
+/**
+  * @brief      Get MAC address of ESP-NOW device.
+  *
+  *            Get MAC address of ESP-NOW device which is pointed now, and move
+  *            the pointer to next one in ESP-NOW MAC list or move the pointer to
+  *            the first one in ESP-NOW MAC list.
+  *
+  * @attention 1. This API can not re-entry
+  * @attention 2. Parameter has to be true when you call it the first time.
+  *
+  * @param  bool restart : true, move pointer to the first one in ESP-NOW MAC list;
+  *                        false, move pointer to the next one in ESP-NOW MAC list
+  *
+  * @return NULL, no ESP-NOW devices exist
+  * @return Otherwise, MAC address of ESP-NOW device which is pointed now
+  */
+uint8 *esp_now_fetch_peer(bool restart);
+
+/**
+  * @brief  Check if target device exists or not.
+  *
+  * @param  uint8 *mac_addr : MAC address of target device.
+  *
+  * @return 0   : device does not exist
+  * @return < 0 : error occur, check fail
+  * @return > 0 : device exists
+  */
+sint32 esp_now_is_peer_exist(uint8 *mac_addr);
+
+/**
+  * @brief  Get the total number of ESP-NOW devices which are associated, and the
+  *         number count of encrypted devices.
+  *
+  * @param  uint8 *all_cnt    : total number of ESP-NOW devices which are associated.
+  * @param  uint8 *encryp_cnt : number count of encrypted devices
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_get_cnt_info(uint8 *all_cnt, uint8 *encrypt_cnt);
+
+/**
+  * @brief  Set the encrypt key of communication key.
+  *
+  *         All ESP-NOW devices share the same encrypt key. If users do not set
+  *         the encrypt key, ESP-NOW communication key will be encrypted by a default key.
+  *
+  * @param  uint8 *key : pointer of encrypt key.
+  * @param  uint8 len  : key length, has to be 16 bytes now.
+  *
+  * @return 0     : succeed
+  * @return Non-0 : fail
+  */
+sint32 esp_now_set_kok(uint8 *key, uint8 len);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/pwm.h

@@ -0,0 +1,142 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __PWM_H__
+#define __PWM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup Driver_APIs Driver APIs
+  * @brief Driver APIs
+  */
+
+/** @addtogroup Driver_APIs
+  * @{
+  */
+
+/** \defgroup PWM_Driver_APIs PWM Driver APIs
+  * @brief PWM driver APIs
+  */
+
+/** @addtogroup PWM_Driver_APIs
+  * @{
+  */
+
+struct pwm_param {
+    uint32 period;      /**< PWM period */
+    uint32 freq;        /**< PWM frequency */
+    uint32 duty[8];     /**< PWM duty */
+};
+
+#define PWM_DEPTH 1023
+
+/**
+  * @brief     PWM function initialization, including GPIO, frequency and duty cycle.
+  *
+  * @attention This API can be called only once.
+  *
+  * @param     uint32 period : pwm frequency
+  * @param     uint32 *duty : duty cycle
+  * @param     uint32 pwm_channel_num : PWM channel number
+  * @param     uint32 (*pin_info_list)[3] : GPIO parameter of PWM channel, it is a pointer
+  *                                         of n x 3 array which defines GPIO register, IO
+  *                                         reuse of corresponding pin and GPIO number.
+  *
+  * @return    null
+  */
+void pwm_init(uint32 period, uint32 *duty, uint32 pwm_channel_num, uint32(*pin_info_list)[3]);
+
+/**
+  * @brief     Set the duty cycle of a PWM channel.
+  *
+  *            Set the time that high level signal will last, duty depends on period,
+  *            the maximum value can be 1023.
+  *           
+  *
+  * @attention After set configuration, pwm_start needs to be called to take effect.
+  *
+  * @param     uint32 duty : duty cycle
+  * @param     uint8 channel : PWM channel number
+  *
+  * @return    null
+  */
+void pwm_set_duty(uint32 duty, uint8 channel);
+
+/**
+  * @brief  Get the duty cycle of a PWM channel.
+  *
+  * @param  uint8 channel : PWM channel number
+  *
+  * @return Duty cycle of PWM output.
+  */
+uint32 pwm_get_duty(uint8 channel);
+
+/**
+  * @brief     Set PWM period, unit : us.
+  *
+  *            For example, for 1KHz PWM, period is 1000 us.
+  *
+  * @attention After set configuration, pwm_start needs to be called to take effect.
+  *
+  * @param     uint32 period : PWM period, unit : us.
+  *
+  * @return    null
+  */
+void pwm_set_period(uint32 period);
+
+/**
+  * @brief  Get PWM period, unit : us.
+  *
+  * @param  null
+  *
+  * @return PWM period, unit : us.
+  */
+uint32 pwm_get_period(void);
+
+/**
+  * @brief  Starts PWM. 
+  *
+  * @attention This function needs to be called after PWM configuration is changed.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void pwm_start(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/queue.h

@@ -0,0 +1,236 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef _SYS_QUEUE_H_
+#define _SYS_QUEUE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define QMD_SAVELINK(name, link)
+#define TRASHIT(x)
+
+/*
+ * Singly-linked List declarations.
+ */
+#define SLIST_HEAD(name, type)  \
+    struct name {   \
+        struct type *slh_first; /* first element */ \
+    }
+
+#define SLIST_HEAD_INITIALIZER(head)    \
+    { NULL }
+
+#define SLIST_ENTRY(type)   \
+    struct {    \
+        struct type *sle_next;  /* next element */  \
+    }
+
+/*
+ * Singly-linked List functions.
+ */
+#define SLIST_EMPTY(head)   ((head)->slh_first == NULL)
+
+#define SLIST_FIRST(head)   ((head)->slh_first)
+
+#define SLIST_FOREACH(var, head, field) \
+    for ((var) = SLIST_FIRST((head));   \
+            (var);  \
+            (var) = SLIST_NEXT((var), field))
+
+#define SLIST_FOREACH_SAFE(var, head, field, tvar)  \
+    for ((var) = SLIST_FIRST((head));   \
+            (var) && ((tvar) = SLIST_NEXT((var), field), 1);    \
+            (var) = (tvar))
+
+#define SLIST_FOREACH_PREVPTR(var, varp, head, field)   \
+    for ((varp) = &SLIST_FIRST((head)); \
+            ((var) = *(varp)) != NULL;  \
+            (varp) = &SLIST_NEXT((var), field))
+
+#define SLIST_INIT(head) do {   \
+        SLIST_FIRST((head)) = NULL; \
+    } while (0)
+
+#define SLIST_INSERT_AFTER(slistelm, elm, field) do {   \
+        SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field);   \
+        SLIST_NEXT((slistelm), field) = (elm);  \
+    } while (0)
+
+#define SLIST_INSERT_HEAD(head, elm, field) do {    \
+        SLIST_NEXT((elm), field) = SLIST_FIRST((head)); \
+        SLIST_FIRST((head)) = (elm);    \
+    } while (0)
+
+#define SLIST_NEXT(elm, field)  ((elm)->field.sle_next)
+
+#define SLIST_REMOVE(head, elm, type, field) do {   \
+        QMD_SAVELINK(oldnext, (elm)->field.sle_next);   \
+        if (SLIST_FIRST((head)) == (elm)) { \
+            SLIST_REMOVE_HEAD((head), field);   \
+        }   \
+        else {  \
+            struct type *curelm = SLIST_FIRST((head));  \
+            while (SLIST_NEXT(curelm, field) != (elm))  \
+                curelm = SLIST_NEXT(curelm, field); \
+            SLIST_REMOVE_AFTER(curelm, field);  \
+        }   \
+        TRASHIT(*oldnext);  \
+    } while (0)
+
+#define SLIST_REMOVE_AFTER(elm, field) do { \
+        SLIST_NEXT(elm, field) =    \
+                SLIST_NEXT(SLIST_NEXT(elm, field), field);  \
+    } while (0)
+
+#define SLIST_REMOVE_HEAD(head, field) do { \
+        SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field);   \
+    } while (0)
+
+/*
+ * Singly-linked Tail queue declarations.
+ */
+#define STAILQ_HEAD(name, type) \
+    struct name {   \
+        struct type *stqh_first;    /* first element */ \
+        struct type **stqh_last;    /* addr of last next element */ \
+    }
+
+#define STAILQ_HEAD_INITIALIZER(head)   \
+    { NULL, &(head).stqh_first }
+
+#define STAILQ_ENTRY(type)  \
+    struct {    \
+        struct type *stqe_next; /* next element */  \
+    }
+
+/*
+ * Singly-linked Tail queue functions.
+ */
+#define STAILQ_CONCAT(head1, head2) do {    \
+        if (!STAILQ_EMPTY((head2))) {   \
+            *(head1)->stqh_last = (head2)->stqh_first;  \
+            (head1)->stqh_last = (head2)->stqh_last;    \
+            STAILQ_INIT((head2));   \
+        }   \
+    } while (0)
+
+#define STAILQ_EMPTY(head)  ((head)->stqh_first == NULL)
+
+#define STAILQ_FIRST(head)  ((head)->stqh_first)
+
+#define STAILQ_FOREACH(var, head, field)    \
+    for((var) = STAILQ_FIRST((head));   \
+            (var);  \
+            (var) = STAILQ_NEXT((var), field))
+
+
+#define STAILQ_FOREACH_SAFE(var, head, field, tvar) \
+    for ((var) = STAILQ_FIRST((head));  \
+            (var) && ((tvar) = STAILQ_NEXT((var), field), 1);   \
+            (var) = (tvar))
+
+#define STAILQ_INIT(head) do {  \
+        STAILQ_FIRST((head)) = NULL;    \
+        (head)->stqh_last = &STAILQ_FIRST((head));  \
+    } while (0)
+
+#define STAILQ_INSERT_AFTER(head, tqelm, elm, field) do {   \
+        if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
+            (head)->stqh_last = &STAILQ_NEXT((elm), field); \
+        STAILQ_NEXT((tqelm), field) = (elm);    \
+    } while (0)
+
+#define STAILQ_INSERT_HEAD(head, elm, field) do {   \
+        if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL) \
+            (head)->stqh_last = &STAILQ_NEXT((elm), field); \
+        STAILQ_FIRST((head)) = (elm);   \
+    } while (0)
+
+#define STAILQ_INSERT_TAIL(head, elm, field) do {   \
+        STAILQ_NEXT((elm), field) = NULL;   \
+        *(head)->stqh_last = (elm); \
+        (head)->stqh_last = &STAILQ_NEXT((elm), field); \
+    } while (0)
+
+#define STAILQ_LAST(head, type, field)  \
+    (STAILQ_EMPTY((head))?   \
+     NULL : \
+     ((struct type *)(void *)\
+      ((char *)((head)->stqh_last) - __offsetof(struct type, field))))
+
+#define STAILQ_NEXT(elm, field) ((elm)->field.stqe_next)
+
+#define STAILQ_REMOVE(head, elm, type, field) do {  \
+        QMD_SAVELINK(oldnext, (elm)->field.stqe_next);  \
+        if (STAILQ_FIRST((head)) == (elm)) {    \
+            STAILQ_REMOVE_HEAD((head), field);  \
+        }   \
+        else {  \
+            struct type *curelm = STAILQ_FIRST((head)); \
+            while (STAILQ_NEXT(curelm, field) != (elm)) \
+                curelm = STAILQ_NEXT(curelm, field);    \
+            STAILQ_REMOVE_AFTER(head, curelm, field);   \
+        }   \
+        TRASHIT(*oldnext);  \
+    } while (0)
+
+#define STAILQ_REMOVE_HEAD(head, field) do {    \
+        if ((STAILQ_FIRST((head)) = \
+                STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL)  \
+            (head)->stqh_last = &STAILQ_FIRST((head));  \
+    } while (0)
+
+#define STAILQ_REMOVE_AFTER(head, elm, field) do {  \
+        if ((STAILQ_NEXT(elm, field) =  \
+                STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL)   \
+            (head)->stqh_last = &STAILQ_NEXT((elm), field); \
+    } while (0)
+
+#define STAILQ_SWAP(head1, head2, type) do {    \
+        struct type *swap_first = STAILQ_FIRST(head1);  \
+        struct type **swap_last = (head1)->stqh_last;   \
+        STAILQ_FIRST(head1) = STAILQ_FIRST(head2);  \
+        (head1)->stqh_last = (head2)->stqh_last;    \
+        STAILQ_FIRST(head2) = swap_first;   \
+        (head2)->stqh_last = swap_last; \
+        if (STAILQ_EMPTY(head1))    \
+            (head1)->stqh_last = &STAILQ_FIRST(head1);  \
+        if (STAILQ_EMPTY(head2))    \
+            (head2)->stqh_last = &STAILQ_FIRST(head2);  \
+    } while (0)
+
+#define STAILQ_INSERT_CHAIN_HEAD(head, elm_chead, elm_ctail, field) do {   \
+        if ((STAILQ_NEXT(elm_ctail, field) = STAILQ_FIRST(head)) == NULL ) { \
+            (head)->stqh_last = &STAILQ_NEXT(elm_ctail, field);            \
+        }                                                                      \
+        STAILQ_FIRST(head) = (elm_chead);                                    \
+    } while (0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_SYS_QUEUE_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/smartconfig.h

@@ -0,0 +1,165 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SMARTCONFIG_H__
+#define __SMARTCONFIG_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup WiFi_APIs WiFi Related APIs
+  * @brief WiFi APIs
+  */
+
+/** @addtogroup WiFi_APIs
+  * @{
+  */
+
+/** \defgroup Smartconfig_APIs Smartconfig APIs
+  * @brief SmartConfig APIs
+  *
+  * SmartConfig can only be enabled in station only mode.
+  * Please make sure the target AP is enabled before enable SmartConfig.
+  *
+  */
+
+/** @addtogroup Smartconfig_APIs
+  * @{
+  */
+
+typedef enum {
+    SC_STATUS_WAIT = 0,             /**< waiting, do not start connection in this phase */
+    SC_STATUS_FIND_CHANNEL,         /**< find target channel, start connection by APP in this phase */
+    SC_STATUS_GETTING_SSID_PSWD,    /**< getting SSID and password of target AP */
+    SC_STATUS_LINK,                 /**< connecting to target AP */
+    SC_STATUS_LINK_OVER,            /**< got IP, connect to AP successfully */
+} sc_status;
+
+typedef enum {
+    SC_TYPE_ESPTOUCH = 0,       /**< protocol: ESPTouch */
+    SC_TYPE_AIRKISS,            /**< protocol: AirKiss */
+    SC_TYPE_ESPTOUCH_AIRKISS,   /**< protocol: ESPTouch and AirKiss */
+} sc_type;
+
+/**
+  * @brief  The callback of SmartConfig, executed when smart-config status changed.
+  *
+  * @param  sc_status status : status of SmartConfig:
+  *    -  if status == SC_STATUS_GETTING_SSID_PSWD, parameter void *pdata is a pointer
+                       of sc_type, means SmartConfig type: AirKiss or ESP-TOUCH.
+  *    -  if status == SC_STATUS_LINK, parameter void *pdata is a pointer of struct station_config;
+  *    -  if status == SC_STATUS_LINK_OVER, parameter void *pdata is a pointer of mobile
+  *                    phone's IP address, 4 bytes. This is only available in ESPTOUCH, otherwise,
+  *                    it is NULL.
+  *    -  otherwise, parameter void *pdata is NULL.
+  * @param  void *pdata : data of SmartConfig
+  *
+  * @return null
+  */
+typedef void (*sc_callback_t)(sc_status status, void *pdata);
+
+/**
+  * @brief  Get the version of SmartConfig.
+  *
+  * @param  null
+  *
+  * @return SmartConfig version
+  */
+const char *smartconfig_get_version(void);
+
+/**
+  * @brief     Start SmartConfig mode.
+  *
+  *            Start SmartConfig mode, to connect ESP8266 station to AP, by sniffing
+  *            for special packets from the air, containing SSID and password of desired AP.
+  *            You need to broadcast the SSID and password (e.g. from mobile device or computer)
+  *            with the SSID and password encoded.
+  *
+  * @attention 1. This api can only be called in station mode.
+  * @attention 2. During SmartConfig, ESP8266 station and soft-AP are disabled.
+  * @attention 3. Can not call smartconfig_start twice before it finish, please call
+  *               smartconfig_stop first.
+  * @attention 4. Don't call any other APIs during SmartConfig, please call smartconfig_stop first.
+  *
+  * @param     sc_callback_t cb : SmartConfig callback; executed when SmartConfig status changed;
+  * @param     uint8 log : 1, UART output logs; otherwise, UART only outputs the result.
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool smartconfig_start(sc_callback_t cb, ...);
+
+/**
+  * @brief     Stop SmartConfig, free the buffer taken by smartconfig_start.
+  *
+  * @attention Whether connect to AP succeed or not, this API should be called to free
+  *            memory taken by smartconfig_start.
+  *
+  * @param     null
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool smartconfig_stop(void);
+
+/**
+  * @brief     Set timeout of SmartConfig.
+  *
+  * @attention SmartConfig timeout start at SC_STATUS_FIND_CHANNEL, SmartConfig will
+  *            restart if timeout.
+  *
+  * @param     uint8 time_s : range 15s~255s, offset:45s.
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool esptouch_set_timeout(uint8 time_s);
+
+/**
+  * @brief     Set protocol type of SmartConfig.
+  *
+  * @attention If users need to set the SmartConfig type, please set it before calling
+  *            smartconfig_start.
+  *
+  * @param     sc_type type : AirKiss, ESP-TOUCH or both.
+  *
+  * @return    true  : succeed
+  * @return    false : fail
+  */
+bool smartconfig_set_type(sc_type type);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/spi_flash.h

@@ -0,0 +1,165 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __SPI_FLASH_H__
+#define __SPI_FLASH_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup Driver_APIs Driver APIs
+  * @brief Driver APIs
+  */
+
+/** @addtogroup Driver_APIs
+  * @{
+  */
+
+/** \defgroup SPI_Driver_APIs SPI Driver APIs
+  * @brief SPI Flash APIs
+  */
+
+/** @addtogroup SPI_Driver_APIs
+  * @{
+  */
+
+typedef enum {
+    SPI_FLASH_RESULT_OK,        /**< SPI Flash operating OK */
+    SPI_FLASH_RESULT_ERR,       /**< SPI Flash operating fail */
+    SPI_FLASH_RESULT_TIMEOUT    /**< SPI Flash operating time out */
+} SpiFlashOpResult;
+
+typedef struct{
+    uint32  deviceId;
+    uint32  chip_size;    // chip size in byte
+    uint32  block_size;
+    uint32  sector_size;
+    uint32  page_size;
+    uint32  status_mask;
+} SpiFlashChip;
+
+#define SPI_FLASH_SEC_SIZE  4096    /**< SPI Flash sector size */
+
+/**
+  * @brief  Get ID info of SPI Flash.
+  *
+  * @param  null
+  *
+  * @return SPI Flash ID
+  */
+uint32 spi_flash_get_id(void);
+
+/**
+  * @brief  Read state register of SPI Flash.
+  *
+  * @param  uint32 *status : the read value (pointer) of state register.
+  *
+  * @return SpiFlashOpResult
+  */
+SpiFlashOpResult spi_flash_read_status(uint32 *status);
+
+/**
+  * @brief  Write state register of SPI Flash.
+  *
+  * @param  uint32 status_value : Write state register value.
+  *
+  * @return SpiFlashOpResult
+  */
+SpiFlashOpResult spi_flash_write_status(uint32 status_value);
+
+/**
+  * @brief  Erase the Flash sector.
+  *
+  * @param  uint16 sec : Sector number, the count starts at sector 0, 4KB per sector.
+  *
+  * @return SpiFlashOpResult
+  */
+SpiFlashOpResult spi_flash_erase_sector(uint16 sec);
+
+/**
+  * @brief  Write data to Flash.
+  *
+  * @param  uint32 des_addr  : destination address in Flash.
+  * @param  uint32 *src_addr : source address of the data.
+  * @param  uint32 size      : length of data
+  *
+  * @return SpiFlashOpResult
+  */
+SpiFlashOpResult spi_flash_write(uint32 des_addr, uint32 *src_addr, uint32 size);
+
+/**
+  * @brief  Read data from Flash.
+  *
+  * @param  uint32 src_addr  : source address of the data.
+  * @param  uint32 *des_addr : destination address in Flash.
+  * @param  uint32 size      : length of data
+  *
+  * @return SpiFlashOpResult
+  */
+SpiFlashOpResult spi_flash_read(uint32 src_addr, uint32 *des_addr, uint32 size);
+
+/**
+  * @brief  Registered function for spi_flash_set_read_func.
+  *
+  * @attention  used for sdk internal, don't need to care about params
+  *
+  * @param  SpiFlashChip *spi : spi flash struct pointer.
+  * @param  uint32 src_addr  : source address of the data.
+  * @param  uint32 *des_addr : destination address in Flash.
+  * @param  uint32 size      : length of data
+  *
+  * @return SpiFlashOpResult
+  */
+typedef SpiFlashOpResult (* user_spi_flash_read)(
+        SpiFlashChip *spi,
+        uint32 src_addr,
+        uint32 *des_addr,
+        uint32 size);
+
+/**
+  * @brief  Register user-define SPI flash read API.
+  *
+  * @attention This API can be only used in SPI overlap mode, please refer to ESP8266_RTOS_SDK
+  *            \examples\driver_lib\driver\spi_overlap.c
+  *
+  * @param  user_spi_flash_read read : user-define SPI flash read API .
+  *
+  * @return  none
+  */
+void spi_flash_set_read_func(user_spi_flash_read read);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/espressif/upgrade.h

@@ -0,0 +1,149 @@
+/*
+ * ESPRSSIF MIT License
+ *
+ * Copyright (c) 2015 <ESPRESSIF SYSTEMS (SHANGHAI) PTE LTD>
+ *
+ * Permission is hereby granted for use on ESPRESSIF SYSTEMS ESP8266 only, in which case,
+ * it is free of charge, to any person obtaining a copy of this software and associated
+ * documentation files (the "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the Software is furnished
+ * to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __UPGRADE_H__
+#define __UPGRADE_H__
+
+#include "lwip/sockets.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup System_APIs System APIs
+  * @brief System APIs
+  */
+
+/** @addtogroup System_APIs
+  * @{
+  */
+
+/** \defgroup Upgrade_APIs Upgrade APIs
+  * @brief Firmware upgrade (FOTA) APIs
+  */
+
+/** @addtogroup Upgrade_APIs
+  * @{
+  */
+
+#define SPI_FLASH_SEC_SIZE  4096    /**< SPI Flash sector size */
+
+#define USER_BIN1           0x00    /**< firmware, user1.bin */
+#define USER_BIN2           0x01    /**< firmware, user2.bin */
+
+#define UPGRADE_FLAG_IDLE   0x00    /**< flag of upgrading firmware, idle */
+#define UPGRADE_FLAG_START  0x01    /**< flag of upgrading firmware, start upgrade */
+#define UPGRADE_FLAG_FINISH 0x02    /**< flag of upgrading firmware, finish upgrading */
+
+#define UPGRADE_FW_BIN1     0x00    /**< firmware, user1.bin */
+#define UPGRADE_FW_BIN2     0x01    /**< firmware, user2.bin */
+
+/**
+  * @brief  Callback of upgrading firmware through WiFi.
+  *
+  * @param  void * arg : information about upgrading server
+  *
+  * @return null
+  */
+typedef void (*upgrade_states_check_callback)(void *arg);
+
+//#define UPGRADE_SSL_ENABLE
+
+struct upgrade_server_info {
+    struct sockaddr_in sockaddrin;          /**< socket of upgrading */
+    upgrade_states_check_callback check_cb; /**< callback of upgrading */
+    uint32 check_times;                     /**< time out of upgrading, unit : ms */
+    uint8 pre_version[16];                  /**< previous version of firmware */
+    uint8 upgrade_version[16];              /**< the new version of firmware */
+    uint8 *url;                             /**< the url of upgrading server */
+    void *pclient_param;
+    uint8 upgrade_flag;                     /**< true, upgrade succeed; false, upgrade fail */
+};
+
+/**
+  * @brief  Upgrade function initialization.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_upgrade_init();
+
+/**
+  * @brief  Upgrade function de-initialization.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void system_upgrade_deinit();
+
+/**
+ * @brief  Upgrade function de-initialization.
+ *
+ * @param  uint8 *data : segment of the firmware bin data
+ * @param  uint32 len  : length of the segment bin data
+ *
+ * @return null
+ */
+bool system_upgrade(uint8 *data, uint32 len);
+
+#ifdef UPGRADE_SSL_ENABLE
+
+/**
+ * @brief  Start upgrade firmware through WiFi with SSL connection.
+ *
+ * @param  struct upgrade_server_info *server : the firmware upgrade server info
+ *
+ * @return true  : succeed
+ * @return false : fail
+ */
+bool system_upgrade_start_ssl(struct upgrade_server_info *server);
+#else
+
+/**
+ * @brief  Start upgrade firmware through WiFi with normal connection.
+ *
+ * @param  struct upgrade_server_info *server : the firmware upgrade server info
+ *
+ * @return true  : succeed
+ * @return false : fail
+ */
+
+bool system_upgrade_start(struct upgrade_server_info *server);
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/json/cJSON.h

@@ -0,0 +1,149 @@
+/*
+  Copyright (c) 2009 Dave Gamble
+ 
+  Permission is hereby granted, free of charge, to any person obtaining a copy
+  of this software and associated documentation files (the "Software"), to deal
+  in the Software without restriction, including without limitation the rights
+  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+  copies of the Software, and to permit persons to whom the Software is
+  furnished to do so, subject to the following conditions:
+ 
+  The above copyright notice and this permission notice shall be included in
+  all copies or substantial portions of the Software.
+ 
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+  THE SOFTWARE.
+*/
+
+#ifndef cJSON__h
+#define cJSON__h
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* cJSON Types: */
+#define cJSON_False 0
+#define cJSON_True 1
+#define cJSON_NULL 2
+#define cJSON_Number 3
+#define cJSON_String 4
+#define cJSON_Array 5
+#define cJSON_Object 6
+	
+#define cJSON_IsReference 256
+#define cJSON_StringIsConst 512
+
+/* The cJSON structure: */
+typedef struct cJSON {
+	struct cJSON *next,*prev;	/* next/prev allow you to walk array/object chains. Alternatively, use GetArraySize/GetArrayItem/GetObjectItem */
+	struct cJSON *child;		/* An array or object item will have a child pointer pointing to a chain of the items in the array/object. */
+
+	int type;					/* The type of the item, as above. */
+
+	char *valuestring;			/* The item's string, if type==cJSON_String */
+	int valueint;				/* The item's number, if type==cJSON_Number */
+	double valuedouble;			/* The item's number, if type==cJSON_Number */
+
+	char *string;				/* The item's name string, if this item is the child of, or is in the list of subitems of an object. */
+} cJSON;
+
+typedef struct cJSON_Hooks {
+      void *(*malloc_fn)(size_t sz);
+      void (*free_fn)(void *ptr);
+} cJSON_Hooks;
+
+/* Supply malloc, realloc and free functions to cJSON */
+extern void cJSON_InitHooks(cJSON_Hooks* hooks);
+
+
+/* Supply a block of JSON, and this returns a cJSON object you can interrogate. Call cJSON_Delete when finished. */
+extern cJSON *cJSON_Parse(const char *value);
+/* Render a cJSON entity to text for transfer/storage. Free the char* when finished. */
+extern char  *cJSON_Print(cJSON *item);
+/* Render a cJSON entity to text for transfer/storage without any formatting. Free the char* when finished. */
+extern char  *cJSON_PrintUnformatted(cJSON *item);
+/* Render a cJSON entity to text using a buffered strategy. prebuffer is a guess at the final size. guessing well reduces reallocation. fmt=0 gives unformatted, =1 gives formatted */
+extern char *cJSON_PrintBuffered(cJSON *item,int prebuffer,int fmt);
+/* Delete a cJSON entity and all subentities. */
+extern void   cJSON_Delete(cJSON *c);
+
+/* Returns the number of items in an array (or object). */
+extern int	  cJSON_GetArraySize(cJSON *array);
+/* Retrieve item number "item" from array "array". Returns NULL if unsuccessful. */
+extern cJSON *cJSON_GetArrayItem(cJSON *array,int item);
+/* Get item "string" from object. Case insensitive. */
+extern cJSON *cJSON_GetObjectItem(cJSON *object,const char *string);
+
+/* For analysing failed parses. This returns a pointer to the parse error. You'll probably need to look a few chars back to make sense of it. Defined when cJSON_Parse() returns 0. 0 when cJSON_Parse() succeeds. */
+extern const char *cJSON_GetErrorPtr(void);
+	
+/* These calls create a cJSON item of the appropriate type. */
+extern cJSON *cJSON_CreateNull(void);
+extern cJSON *cJSON_CreateTrue(void);
+extern cJSON *cJSON_CreateFalse(void);
+extern cJSON *cJSON_CreateBool(int b);
+extern cJSON *cJSON_CreateNumber(double num);
+extern cJSON *cJSON_CreateString(const char *string);
+extern cJSON *cJSON_CreateArray(void);
+extern cJSON *cJSON_CreateObject(void);
+
+/* These utilities create an Array of count items. */
+extern cJSON *cJSON_CreateIntArray(const int *numbers,int count);
+extern cJSON *cJSON_CreateFloatArray(const float *numbers,int count);
+extern cJSON *cJSON_CreateDoubleArray(const double *numbers,int count);
+extern cJSON *cJSON_CreateStringArray(const char **strings,int count);
+
+/* Append item to the specified array/object. */
+extern void cJSON_AddItemToArray(cJSON *array, cJSON *item);
+extern void	cJSON_AddItemToObject(cJSON *object,const char *string,cJSON *item);
+extern void	cJSON_AddItemToObjectCS(cJSON *object,const char *string,cJSON *item);	/* Use this when string is definitely const (i.e. a literal, or as good as), and will definitely survive the cJSON object */
+/* Append reference to item to the specified array/object. Use this when you want to add an existing cJSON to a new cJSON, but don't want to corrupt your existing cJSON. */
+extern void cJSON_AddItemReferenceToArray(cJSON *array, cJSON *item);
+extern void	cJSON_AddItemReferenceToObject(cJSON *object,const char *string,cJSON *item);
+
+/* Remove/Detatch items from Arrays/Objects. */
+extern cJSON *cJSON_DetachItemFromArray(cJSON *array,int which);
+extern void   cJSON_DeleteItemFromArray(cJSON *array,int which);
+extern cJSON *cJSON_DetachItemFromObject(cJSON *object,const char *string);
+extern void   cJSON_DeleteItemFromObject(cJSON *object,const char *string);
+	
+/* Update array items. */
+extern void cJSON_InsertItemInArray(cJSON *array,int which,cJSON *newitem);	/* Shifts pre-existing items to the right. */
+extern void cJSON_ReplaceItemInArray(cJSON *array,int which,cJSON *newitem);
+extern void cJSON_ReplaceItemInObject(cJSON *object,const char *string,cJSON *newitem);
+
+/* Duplicate a cJSON item */
+extern cJSON *cJSON_Duplicate(cJSON *item,int recurse);
+/* Duplicate will create a new, identical cJSON item to the one you pass, in new memory that will
+need to be released. With recurse!=0, it will duplicate any children connected to the item.
+The item->next and ->prev pointers are always zero on return from Duplicate. */
+
+/* ParseWithOpts allows you to require (and check) that the JSON is null terminated, and to retrieve the pointer to the final byte parsed. */
+extern cJSON *cJSON_ParseWithOpts(const char *value,const char **return_parse_end,int require_null_terminated);
+
+extern void cJSON_Minify(char *json);
+
+/* Macros for creating things quickly. */
+#define cJSON_AddNullToObject(object,name)		cJSON_AddItemToObject(object, name, cJSON_CreateNull())
+#define cJSON_AddTrueToObject(object,name)		cJSON_AddItemToObject(object, name, cJSON_CreateTrue())
+#define cJSON_AddFalseToObject(object,name)		cJSON_AddItemToObject(object, name, cJSON_CreateFalse())
+#define cJSON_AddBoolToObject(object,name,b)	cJSON_AddItemToObject(object, name, cJSON_CreateBool(b))
+#define cJSON_AddNumberToObject(object,name,n)	cJSON_AddItemToObject(object, name, cJSON_CreateNumber(n))
+#define cJSON_AddStringToObject(object,name,s)	cJSON_AddItemToObject(object, name, cJSON_CreateString(s))
+
+/* When assigning an integer value, it needs to be propagated to valuedouble too. */
+#define cJSON_SetIntValue(object,val)			((object)?(object)->valueint=(object)->valuedouble=(val):(val))
+#define cJSON_SetNumberValue(object,val)		((object)?(object)->valueint=(object)->valuedouble=(val):(val))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/lwip/apps/sntp.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Frédéric Bernon, Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_APPS_SNTP_H
+#define LWIP_HDR_APPS_SNTP_H
+
+#include "apps/sntp_opts.h"
+#include "lwip/ip_addr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* SNTP operating modes: default is to poll using unicast.
+   The mode has to be set before calling sntp_init(). */
+#define SNTP_OPMODE_POLL            0
+#define SNTP_OPMODE_LISTENONLY      1
+void sntp_setoperatingmode(u8_t operating_mode);
+u8_t sntp_getoperatingmode(void);
+
+void sntp_init(void);
+void sntp_stop(void);
+u8_t sntp_enabled(void);
+
+void sntp_setserver(u8_t idx, const ip_addr_t *addr);
+ip_addr_t sntp_getserver(u8_t idx);
+
+#if SNTP_SERVER_DNS
+void sntp_setservername(u8_t idx, char *server);
+char *sntp_getservername(u8_t idx);
+#endif /* SNTP_SERVER_DNS */
+
+#if SNTP_GET_SERVERS_FROM_DHCP
+void sntp_servermode_dhcp(int set_servers_from_dhcp);
+#else /* SNTP_GET_SERVERS_FROM_DHCP */
+#define sntp_servermode_dhcp(x)
+#endif /* SNTP_GET_SERVERS_FROM_DHCP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_HDR_APPS_SNTP_H */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/lwip/apps/sntp_opts.h

@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2007-2009 Frédéric Bernon, Simon Goldschmidt
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Frédéric Bernon, Simon Goldschmidt
+ *
+ */
+#ifndef LWIP_HDR_APPS_SNTP_OPTS_H
+#define LWIP_HDR_APPS_SNTP_OPTS_H
+
+#include "lwip/opt.h"
+
+/** SNTP macro to change system time in seconds
+ * Define SNTP_SET_SYSTEM_TIME_US(sec, us) to set the time in microseconds instead of this one
+ * if you need the additional precision.
+ */
+#ifndef SNTP_SET_SYSTEM_TIME
+#define SNTP_SET_SYSTEM_TIME(sec)   sntp_set_system_time(sec)
+#endif
+
+/** The maximum number of SNTP servers that can be set */
+#ifndef SNTP_MAX_SERVERS
+#define SNTP_MAX_SERVERS           1
+#endif
+
+/** Set this to 1 to implement the callback function called by dhcp when
+ * NTP servers are received. */
+#ifndef SNTP_GET_SERVERS_FROM_DHCP
+#define SNTP_GET_SERVERS_FROM_DHCP 0
+#endif
+
+/* Set this to 1 to support DNS names (or IP address strings) to set sntp servers */
+#ifndef SNTP_SERVER_DNS
+#define SNTP_SERVER_DNS            1
+#endif
+
+/** One server address/name can be defined as default if SNTP_SERVER_DNS == 1:
+ * #define SNTP_SERVER_ADDRESS "pool.ntp.org"
+ */
+
+/**
+ * SNTP_DEBUG: Enable debugging for SNTP.
+ */
+#ifndef SNTP_DEBUG
+#define SNTP_DEBUG                  LWIP_DBG_OFF
+#endif
+
+/** SNTP server port */
+#ifndef SNTP_PORT
+#define SNTP_PORT                   123
+#endif
+
+/** Set this to 1 to allow config of SNTP server(s) by DNS name */
+#ifndef SNTP_SERVER_DNS
+#define SNTP_SERVER_DNS             0
+#endif
+
+/** Sanity check:
+ * Define this to
+ * - 0 to turn off sanity checks (default; smaller code)
+ * - >= 1 to check address and port of the response packet to ensure the
+ *        response comes from the server we sent the request to.
+ * - >= 2 to check returned Originate Timestamp against Transmit Timestamp
+ *        sent to the server (to ensure response to older request).
+ * - >= 3 @todo: discard reply if any of the LI, Stratum, or Transmit Timestamp
+ *        fields is 0 or the Mode field is not 4 (unicast) or 5 (broadcast).
+ * - >= 4 @todo: to check that the Root Delay and Root Dispersion fields are each
+ *        greater than or equal to 0 and less than infinity, where infinity is
+ *        currently a cozy number like one second. This check avoids using a
+ *        server whose synchronization source has expired for a very long time.
+ */
+#ifndef SNTP_CHECK_RESPONSE
+#define SNTP_CHECK_RESPONSE         0
+#endif
+
+/** According to the RFC, this shall be a random delay
+ * between 1 and 5 minutes (in milliseconds) to prevent load peaks.
+ * This can be defined to a random generation function,
+ * which must return the delay in milliseconds as u32_t.
+ * Turned off by default.
+ */
+#ifndef SNTP_STARTUP_DELAY
+#define SNTP_STARTUP_DELAY          0
+#endif
+
+/** If you want the startup delay to be a function, define this
+ * to a function (including the brackets) and define SNTP_STARTUP_DELAY to 1.
+ */
+#ifndef SNTP_STARTUP_DELAY_FUNC
+#define SNTP_STARTUP_DELAY_FUNC     SNTP_STARTUP_DELAY
+#endif
+
+/** SNTP receive timeout - in milliseconds
+ * Also used as retry timeout - this shouldn't be too low.
+ * Default is 3 seconds.
+ */
+#ifndef SNTP_RECV_TIMEOUT
+#define SNTP_RECV_TIMEOUT           3000
+#endif
+
+/** SNTP update delay - in milliseconds
+ * Default is 1 hour. Must not be beolw 15 seconds by specification (i.e. 15000)
+ */
+#ifndef SNTP_UPDATE_DELAY
+#define SNTP_UPDATE_DELAY           3600000
+#endif
+
+/** SNTP macro to get system time, used with SNTP_CHECK_RESPONSE >= 2
+ * to send in request and compare in response.
+ */
+#ifndef SNTP_GET_SYSTEM_TIME
+#define SNTP_GET_SYSTEM_TIME(sec, us)     do { (sec) = 0; (us) = 0; } while(0)
+#endif
+
+/** Default retry timeout (in milliseconds) if the response
+ * received is invalid.
+ * This is doubled with each retry until SNTP_RETRY_TIMEOUT_MAX is reached.
+ */
+#ifndef SNTP_RETRY_TIMEOUT
+#define SNTP_RETRY_TIMEOUT          SNTP_RECV_TIMEOUT
+#endif
+
+/** Maximum retry timeout (in milliseconds). */
+#ifndef SNTP_RETRY_TIMEOUT_MAX
+#define SNTP_RETRY_TIMEOUT_MAX      (SNTP_RETRY_TIMEOUT * 10)
+#endif
+
+/** Increase retry timeout with every retry sent
+ * Default is on to conform to RFC.
+ */
+#ifndef SNTP_RETRY_TIMEOUT_EXP
+#define SNTP_RETRY_TIMEOUT_EXP      1
+#endif
+
+#endif /* LWIP_HDR_APPS_SNTP_OPTS_H */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/lwip/apps/sntp_time.h

@@ -0,0 +1,61 @@
+/*
+ * sntp_time.h
+ *
+ *  Created on: 2016-11-9
+ *      Author: LiuHan
+ */
+
+#ifndef SNTP_TIME_H_
+#define SNTP_TIME_H_
+
+#include "lwip/opt.h"
+#include "lwip/timers.h"
+
+#define SECSPERMIN	60L
+#define MINSPERHOUR	60L
+#define HOURSPERDAY	24L
+#define SECSPERHOUR	(SECSPERMIN * MINSPERHOUR)
+#define SECSPERDAY	(SECSPERHOUR * HOURSPERDAY)
+#define DAYSPERWEEK	7
+#define MONSPERYEAR	12
+
+#define YEAR_BASE	1900
+#define EPOCH_YEAR      1970
+#define EPOCH_WDAY      4
+#define EPOCH_YEARS_SINCE_LEAP 2
+#define EPOCH_YEARS_SINCE_CENTURY 70
+#define EPOCH_YEARS_SINCE_LEAP_CENTURY 370
+
+#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0)
+
+typedef long sntp_time_t;
+
+typedef struct{
+  int	tm_sec;
+  int	tm_min;
+  int	tm_hour;
+  int	tm_mday;
+  int	tm_mon;
+  int	tm_year;
+  int	tm_wday;
+  int	tm_yday;
+  int	tm_isdst;
+}sntp_tm;
+
+typedef struct{
+  char ch;
+  int m;
+  int n;
+  int d;
+  int s;
+  sntp_time_t change;
+  int offset;
+}sntp_tm_type;
+
+void sntp_set_system_time(sntp_time_t GMT_Time);
+bool sntp_set_timezone(s8_t timezone);
+u32_t sntp_get_current_timestamp(void);
+char* sntp_get_real_time(sntp_time_t t);
+
+
+#endif /* SNTP_TIME_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/lwip/apps/time.h

@@ -0,0 +1,57 @@
+/*
+ * time.h
+ *
+ *  Created on: May 31, 2016
+ *      Author: liuhan
+ */
+
+#ifndef TIME_H_
+#define TIME_H_
+
+#include "c_types.h"
+#include "esp8266/eagle_soc.h"
+
+#if !NO_SYS
+#include "lwip/sockets.h"
+#else
+struct timeval {
+  unsigned long  tv_sec;         /* seconds */
+  unsigned long  tv_usec;        /* and microseconds */
+};
+#endif
+
+/***************************RTC TIME OPTION***************************************/
+// daylight settings
+// Base calculated with value obtained from NTP server (64 bits)
+#define sntp_base   (*((uint64_t*)RTC_SCRATCH0))
+// Timer value when base was obtained
+#define TIM_REF_SET(value) WRITE_PERI_REG(RTC_SCRATCH2, value)
+#define TIM_REF_GET()      READ_PERI_REG(RTC_SCRATCH2)
+
+// Setters and getters for CAL, TZ and DST.
+#define RTC_CAL_SET(val)    do {uint32 value = READ_PERI_REG(RTC_SCRATCH3);\
+    value |= ((val) & 0x0000FFFF);\
+    WRITE_PERI_REG(RTC_SCRATCH3, value);\
+    }while(0)
+#define RTC_DST_SET(val)    do {uint32 value = READ_PERI_REG(RTC_SCRATCH3);\
+    value |= (((val)<<16) & 0x00010000);\
+    WRITE_PERI_REG(RTC_SCRATCH3, value);\
+    }while(0)
+#define RTC_TZ_SET(val)     do {uint32 value = READ_PERI_REG(RTC_SCRATCH3);\
+    value |= (((val)<<24) & 0xFF000000);\
+    WRITE_PERI_REG(RTC_SCRATCH3, value);\
+    }while(0)
+
+#define RTC_CAL_GET()       (READ_PERI_REG(RTC_SCRATCH3) & 0x0000FFFF)
+#define RTC_DST_GET()       ((READ_PERI_REG(RTC_SCRATCH3) & 0x00010000)>>16)
+#define RTC_TZ_GET()        ((((int)READ_PERI_REG(RTC_SCRATCH3)) & ((int)0xFF000000))>>24)
+void system_update_rtc(time_t t, uint32 us);
+time_t sntp_get_rtc_time(sint32 *us);
+
+int  gettimeofday(struct timeval* t, void* timezone);
+void updateTime(uint32 ms);
+bool configTime(int timezone, int daylightOffset, char *server1, char *server2, char *server3, bool enable);
+time_t time(time_t *t);
+unsigned long millis(void);
+unsigned long micros(void);
+#endif /* TIME_H_ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/lwip/arch/cc.h

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __ARCH_CC_H__
+#define __ARCH_CC_H__
+
+#include "c_types.h"
+
+#define EFAULT 14
+
+#define ERRNO
+//#define LWIP_PROVIDE_ERRNO
+
+#if (1)
+#define BYTE_ORDER LITTLE_ENDIAN
+#else
+#define BYTE_ORDER BIG_ENDIAN
+#endif
+
+typedef unsigned long   mem_ptr_t;
+typedef int sys_prot_t;
+
+#define S16_F "d"
+#define U16_F "d"
+#define X16_F "x"
+
+#define S32_F "d"
+#define U32_F "d"
+#define X32_F "x"
+
+//#define PACK_STRUCT_FIELD(x) x __attribute__((packed))
+#define PACK_STRUCT_FIELD(x) x
+#define PACK_STRUCT_STRUCT __attribute__((packed))
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_END
+
+//#define LWIP_DEBUG
+
+#include <stdio.h>
+
+#ifndef os_printf
+#define os_printf(fmt, ...) do {    \
+    static const char flash_str[] ICACHE_RODATA_ATTR STORE_ATTR = fmt;  \
+    printf(flash_str, ##__VA_ARGS__);   \
+    } while(0)
+#endif
+
+#ifdef LWIP_DEBUG
+#define LWIP_PLATFORM_DIAG(x)   do {os_printf x;} while(0)
+#define LWIP_PLATFORM_ASSERT(x) do {os_printf(x); sys_arch_assert(__FILE__, __LINE__);} while(0)
+#else
+#define LWIP_PLATFORM_DIAG(x)
+#define LWIP_PLATFORM_ASSERT(x)
+#endif
+
+#ifndef LWIP_PLATFORM_BYTESWAP
+#define LWIP_PLATFORM_BYTESWAP 1
+#endif
+
+#define LWIP_PLATFORM_HTONS(_n)  ((u16_t)((((_n) & 0xff) << 8) | (((_n) >> 8) & 0xff)))
+#define LWIP_PLATFORM_HTONL(_n)  ((u32_t)( (((_n) & 0xff) << 24) | (((_n) & 0xff00) << 8) | (((_n) >> 8)  & 0xff00) | (((_n) >> 24) & 0xff) ))
+
+#endif /* __ARCH_CC_H__ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/lwip/arch/perf.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2001, Swedish Institute of Computer Science.
+ * All rights reserved. 
+ *
+ * Redistribution and use in source and binary forms, with or without 
+ * modification, are permitted provided that the following conditions 
+ * are met: 
+ * 1. Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer. 
+ * 2. Redistributions in binary form must reproduce the above copyright 
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the distribution. 
+ * 3. Neither the name of the Institute nor the names of its contributors 
+ *    may be used to endorse or promote products derived from this software 
+ *    without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND 
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+ * SUCH DAMAGE. 
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __PERF_H__
+#define __PERF_H__
+
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+
+#endif /* __PERF_H__ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/lwip/arch/sys_arch.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2001-2003 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+ 
+#ifndef __SYS_ARCH_H__
+#define __SYS_ARCH_H__
+
+#include "espos_task.h"
+#include "espos_semaphore.h"
+#include "espos_mutex.h"
+#include "espos_queue.h"
+#include "espos_scheduler.h"
+
+typedef espos_sem_t sys_sem_t;
+typedef espos_mutex_t sys_mutex_t;
+typedef espos_queue_t sys_mbox_t;
+typedef espos_task_t sys_thread_t;
+
+#define sys_mbox_valid( x ) ( ( ( *x ) == ESPOS_OBJ_NONE) ? false : true )
+#define sys_mbox_set_invalid( x ) ( ( *x ) = ESPOS_OBJ_NONE )
+#define sys_sem_valid( x ) ( ( ( *x ) == ESPOS_OBJ_NONE) ? false : true )
+#define sys_sem_set_invalid( x ) ( ( *x ) = ESPOS_OBJ_NONE )
+
+#define LWIP_COMPAT_MUTEX 0
+
+#endif /* __SYS_ARCH_H__ */
+

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/lwip/ipv4/lwip/autoip.h

@@ -0,0 +1,118 @@
+/**
+ * @file
+ *
+ * AutoIP Automatic LinkLocal IP Configuration
+ */
+
+/*
+ *
+ * Copyright (c) 2007 Dominik Spies <kontakt@dspies.de>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * Author: Dominik Spies <kontakt@dspies.de>
+ *
+ * This is a AutoIP implementation for the lwIP TCP/IP stack. It aims to conform
+ * with RFC 3927.
+ *
+ *
+ * Please coordinate changes and requests with Dominik Spies
+ * <kontakt@dspies.de>
+ */
+ 
+#ifndef __LWIP_AUTOIP_H__
+#define __LWIP_AUTOIP_H__
+
+#include "lwip/opt.h"
+
+#if LWIP_AUTOIP /* don't build if not configured for use in lwipopts.h */
+
+#include "lwip/netif.h"
+#include "lwip/udp.h"
+#include "netif/etharp.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* AutoIP Timing */
+#define AUTOIP_TMR_INTERVAL      100
+#define AUTOIP_TICKS_PER_SECOND (1000 / AUTOIP_TMR_INTERVAL)
+
+/* RFC 3927 Constants */
+#define PROBE_WAIT               1   /* second   (initial random delay)                 */
+#define PROBE_MIN                1   /* second   (minimum delay till repeated probe)    */
+#define PROBE_MAX                2   /* seconds  (maximum delay till repeated probe)    */
+#define PROBE_NUM                3   /*          (number of probe packets)              */
+#define ANNOUNCE_NUM             2   /*          (number of announcement packets)       */
+#define ANNOUNCE_INTERVAL        2   /* seconds  (time between announcement packets)    */
+#define ANNOUNCE_WAIT            2   /* seconds  (delay before announcing)              */
+#define MAX_CONFLICTS            10  /*          (max conflicts before rate limiting)   */
+#define RATE_LIMIT_INTERVAL      60  /* seconds  (delay between successive attempts)    */
+#define DEFEND_INTERVAL          10  /* seconds  (min. wait between defensive ARPs)     */
+
+/* AutoIP client states */
+#define AUTOIP_STATE_OFF         0
+#define AUTOIP_STATE_PROBING     1
+#define AUTOIP_STATE_ANNOUNCING  2
+#define AUTOIP_STATE_BOUND       3
+
+struct autoip
+{
+  ip_addr_t llipaddr;       /* the currently selected, probed, announced or used LL IP-Address */
+  u8_t state;               /* current AutoIP state machine state */
+  u8_t sent_num;            /* sent number of probes or announces, dependent on state */
+  u16_t ttw;                /* ticks to wait, tick is AUTOIP_TMR_INTERVAL long */
+  u8_t lastconflict;        /* ticks until a conflict can be solved by defending */
+  u8_t tried_llipaddr;      /* total number of probed/used Link Local IP-Addresses */
+};
+
+
+#define autoip_init() /* Compatibility define, no init needed. */
+
+/** Set a struct autoip allocated by the application to work with */
+void autoip_set_struct(struct netif *netif, struct autoip *autoip);
+
+/** Start AutoIP client */
+err_t autoip_start(struct netif *netif);
+
+/** Stop AutoIP client */
+err_t autoip_stop(struct netif *netif);
+
+/** Handles every incoming ARP Packet, called by etharp_arp_input */
+void autoip_arp_reply(struct netif *netif, struct etharp_hdr *hdr);
+
+/** Has to be called in loop every AUTOIP_TMR_INTERVAL milliseconds */
+void autoip_tmr(void);
+
+/** Handle a possible change in the network configuration */
+void autoip_network_changed(struct netif *netif);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LWIP_AUTOIP */
+
+#endif /* __LWIP_AUTOIP_H__ */

Living_SDK/platform/mcu/esp8266/bsp/ESP8266_RTOS_SDK/include/lwip/ipv4/lwip/icmp.h

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIP_ICMP_H__
+#define __LWIP_ICMP_H__
+
+#include "lwip/opt.h"
+#include "lwip/pbuf.h"
+#include "lwip/ip_addr.h"
+#include "lwip/netif.h"
+
+#if LWIP_IPV6 && LWIP_ICMP6
+#include "lwip/icmp6.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ICMP_ER   0    /* echo reply */
+#define ICMP_DUR  3    /* destination unreachable */
+#define ICMP_SQ   4    /* source quench */
+#define ICMP_RD   5    /* redirect */
+#define ICMP_ECHO 8    /* echo */
+#define ICMP_TE  11    /* time exceeded */
+#define ICMP_PP  12    /* parameter problem */
+#define ICMP_TS  13    /* timestamp */
+#define ICMP_TSR 14    /* timestamp reply */
+#define ICMP_IRQ 15    /* information request */
+#define ICMP_IR  16    /* information reply */
+
+enum icmp_dur_type {
+  ICMP_DUR_NET   = 0,  /* net unreachable */
+  ICMP_DUR_HOST  = 1,  /* host unreachable */
+  ICMP_DUR_PROTO = 2,  /* protocol unreachable */
+  ICMP_DUR_PORT  = 3,  /* port unreachable */
+  ICMP_DUR_FRAG  = 4,  /* fragmentation needed and DF set */
+  ICMP_DUR_SR    = 5   /* source route failed */
+};
+
+enum icmp_te_type {
+  ICMP_TE_TTL  = 0,    /* time to live exceeded in transit */
+  ICMP_TE_FRAG = 1     /* fragment reassembly time exceeded */
+};
+
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/bpstruct.h"
+#endif
+/** This is the standard ICMP header only that the u32_t data
+ *  is splitted to two u16_t like ICMP echo needs it.
+ *  This header is also used for other ICMP types that do not
+ *  use the data part.
+ */
+PACK_STRUCT_BEGIN
+struct icmp_echo_hdr {
+  PACK_STRUCT_FIELD(u8_t type);
+  PACK_STRUCT_FIELD(u8_t code);
+  PACK_STRUCT_FIELD(u16_t chksum);
+  PACK_STRUCT_FIELD(u16_t id);
+  PACK_STRUCT_FIELD(u16_t seqno);
+} PACK_STRUCT_STRUCT;
+PACK_STRUCT_END
+#ifdef PACK_STRUCT_USE_INCLUDES
+#  include "arch/epstruct.h"
+#endif
+
+#define ICMPH_TYPE(hdr) ((hdr)->type)
+#define ICMPH_CODE(hdr) ((hdr)->code)
+
+/** Combines type and code to an u16_t */
+#define ICMPH_TYPE_SET(hdr, t) ((hdr)->type = (t))
+#define ICMPH_CODE_SET(hdr, c) ((hdr)->code = (c))
+
+
+#if LWIP_ICMP /* don't build if not configured for use in lwipopts.h */
+
+void icmp_input(struct pbuf *p, struct netif *inp);
+void icmp_dest_unreach(struct pbuf *p, enum icmp_dur_type t);
+void icmp_time_exceeded(struct pbuf *p, enum icmp_te_type t);
+
+#endif /* LWIP_ICMP */
+
+#if (LWIP_IPV6 && LWIP_ICMP6)
+#define icmp_port_unreach(isipv6, pbuf) ((isipv6) ? \
+                                         icmp6_dest_unreach(pbuf, ICMP6_DUR_PORT) : \
+                                         icmp_dest_unreach(pbuf, ICMP_DUR_PORT))
+#elif LWIP_ICMP
+#define icmp_port_unreach(isipv6, pbuf) icmp_dest_unreach(pbuf, ICMP_DUR_PORT)
+#else /* (LWIP_IPV6 && LWIP_ICMP6) || LWIP_ICMP*/
+#define icmp_port_unreach(isipv6, pbuf)
+#endif /* (LWIP_IPV6 && LWIP_ICMP6) || LWIP_ICMP*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LWIP_ICMP_H__ */