rel_1.6.0 init

Living_SDK/platform/mcu/esp32/aos/heap_private.h

@@ -0,0 +1,54 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include <stdlib.h>
+#include <stdint.h>
+
+#include "espos_spinlock.h"
+#include <soc/soc_memory_layout.h>
+#include "multi_heap.h"
+#include "rom/queue.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Some common heap registration data structures used
+   for heap_caps_init.c to share heap information with heap_caps.c
+*/
+
+/* Type for describing each registered heap */
+typedef struct heap_t_ {
+    uint32_t caps[SOC_MEMORY_TYPE_NO_PRIOS]; ///< Capabilities for the type of memory in this heap (as a prioritised set). Copied from soc_memory_types so it's in RAM not flash.
+    intptr_t start;
+    intptr_t end;
+    espos_spinlock_t heap_mux;
+    multi_heap_handle_t heap;
+    SLIST_ENTRY(heap_t_) next;
+} heap_t;
+
+/* All registered heaps.
+
+   Forms a single linked list, even though most entries are contiguous.
+   This means at the expense of 4 bytes per heap, new heaps can be
+   added at runtime in a fast & thread-safe way.
+*/
+extern SLIST_HEAD(registered_heap_ll, heap_t_) registered_heaps;
+
+bool heap_caps_match(const heap_t *heap, uint32_t caps);
+
+#ifdef __cplusplus
+}
+#endif

Living_SDK/platform/mcu/esp32/aos/heap_wrapper.c

@@ -0,0 +1,28 @@
+#include "esp_attr.h"
+#include "k_api.h"
+
+IRAM_ATTR void *heap_caps_malloc(size_t size, uint32_t caps)
+{
+    (void)caps;
+    return krhino_mm_alloc(size);
+}
+
+IRAM_ATTR void heap_caps_free( void *ptr)
+{
+    krhino_mm_free(ptr);
+}
+
+IRAM_ATTR void *heap_caps_realloc( void *ptr, size_t size, int caps)
+{
+    return krhino_mm_realloc(ptr, size);
+}
+
+
+void heap_caps_enable_nonos_stack_heaps()
+{
+}
+
+int heap_caps_get_free_size(void)
+{
+    return 0;
+}

Living_SDK/platform/mcu/esp32/aos/hook_impl.c

@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2015-2017 Alibaba Group Holding Limited
+ */
+
+#include <k_api.h>
+#include "frxt/xtensa_config.h"
+
+void soc_hw_timer_init()
+{
+}
+
+#if (RHINO_CONFIG_USER_HOOK > 0)
+void krhino_idle_pre_hook(void)
+{
+
+}
+void krhino_idle_hook(void)
+{
+}
+
+void krhino_init_hook(void)
+{
+#if (RHINO_CONFIG_HW_COUNT > 0)
+    soc_hw_timer_init();
+#endif
+}
+#endif
+
+void krhino_start_hook(void)
+{
+#if (RHINO_CONFIG_TASK_SCHED_STATS > 0)
+    krhino_task_sched_stats_reset();
+#endif
+}
+
+void krhino_task_create_hook(ktask_t *task)
+{
+#if XCHAL_CP_NUM > 0
+    krhino_task_info_set(task, 0, (void *)((uint32_t)task->task_stack + XT_STK_FRMSZ));
+#endif
+}
+
+void krhino_task_del_hook(ktask_t *task, res_free_t *arg)
+{
+}
+
+void krhino_task_switch_hook(ktask_t *orgin, ktask_t *dest)
+{
+    (void)orgin;
+    (void)dest;
+}
+
+void krhino_tick_hook(void)
+{
+}
+
+void krhino_task_abort_hook(ktask_t *task)
+{
+    (void)task;
+}
+
+void krhino_mm_alloc_hook(void *mem, size_t size)
+{
+    (void)mem;
+    (void)size;
+}
+

Living_SDK/platform/mcu/esp32/aos/soc_impl.c

@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2015-2017 Alibaba Group Holding Limited
+ */
+
+#include <k_api.h>
+#include <assert.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+size_t soc_get_cur_sp()
+{
+    volatile size_t dummy = (size_t)&dummy;
+    return dummy;
+}
+
+#if (RHINO_CONFIG_HW_COUNT > 0)
+hr_timer_t soc_hr_hw_cnt_get(void)
+{
+    return 0;
+}
+#endif
+
+#define SYS_DYN_POOL_SIZE_1 0x18000
+
+extern uint8_t _heap_start, _heap_size;
+const k_mm_region_t g_mm_region[] = {
+    {(uint8_t*)0x3ffe8000, SYS_DYN_POOL_SIZE_1},
+    {&_heap_start, (uint32_t)&_heap_size},
+};
+int g_region_num  = sizeof(g_mm_region)/sizeof(k_mm_region_t);
+
+void soc_err_proc(kstat_t err)
+{
+    printf("kernel panic,err %d!\n",err);
+    assert(0);
+}
+
+krhino_err_proc_t g_err_proc = soc_err_proc;
+

Living_SDK/platform/mcu/esp32/aos/trace_impl.c

@@ -0,0 +1,233 @@
+/*
+ * Copyright (C) 2015-2017 Alibaba Group Holding Limited
+ */
+
+#include <k_api.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <aos/network.h>
+#include <hal/trace.h>
+#include <aos/aos.h>
+
+/* CLI Support */
+#ifdef CONFIG_AOS_CLI
+/* Trace Open*/
+#if (RHINO_CONFIG_TRACE > 0)
+#define TRACE_TASK_STACK_SIZE 512
+
+extern struct k_fifo trace_fifo;
+extern int32_t set_filter_task(const char * task_name);
+extern void set_event_mask(const uint32_t mask);
+extern void trace_deinit(void);
+static ktask_t *trace_task;
+static uint32_t trace_buf[1024];
+static volatile int trace_is_started;
+static char *filter_task;
+static char *ip_addr;
+static uint16_t ip_port = 8000;
+static int sockfd;
+
+void *trace_hal_init()
+{
+    int fd;
+    struct sockaddr_in servaddr;
+
+    TRACE_INIT();
+
+    if ((fd = socket(AF_INET, SOCK_STREAM, 0)) < 0) {
+        aos_cli_printf("create socket (%s:%u) error: %s(errno: %d)\r\n", ip_addr, ip_port, strerror(errno),errno);
+        return 0;
+    }
+
+    memset(&servaddr, 0, sizeof(servaddr));
+    servaddr.sin_family = AF_INET;
+    servaddr.sin_port = htons(ip_port);
+    inet_aton(ip_addr, &servaddr.sin_addr);
+
+    if (connect(fd, (struct sockaddr*)&servaddr, sizeof(servaddr)) < 0) {
+        aos_cli_printf("connect (%s:%u) error: %s(errno: %d)\r\n", ip_addr, ip_port, strerror(errno),errno);
+        close(fd);
+        return 0;
+    }
+    aos_cli_printf("connected on (%s:%u)\r\n", ip_addr, ip_port);
+
+    return (void *)fd;
+}
+
+
+ssize_t trace_hal_send(void *handle, void *buf, size_t len)
+{
+    int len_send = 0;
+    int len_total_send = 0;
+
+    while (1) {
+        len_send = send((int)handle, (buf + len_total_send) , len, 0);
+        if (len_send < 0) {
+            aos_cli_printf("send (%s:%u) msg error: %s(errno: %d)\r\n", ip_addr, ip_port, strerror(errno), errno);
+            return 0;
+        }
+
+        len_total_send += len_send;
+        len -= len_send;
+        if (len == 0) {
+            break;
+        }
+    }
+
+    return len_send;
+}
+
+ssize_t trace_hal_recv(void *handle, void *buf)
+{
+    return 0;
+}
+
+void trace_hal_deinit(void *handle)
+{
+    int fd;
+
+    fd = (int)handle;
+    close(fd);
+    *(int *)handle = -1;
+    sockfd = -1;
+}
+
+void trace_stop(void)
+{
+    set_filter_task(NULL);
+    set_event_mask(0);
+
+    trace_deinit();
+
+    trace_hal_deinit((void *)sockfd);
+
+    aos_cli_printf("trace (%s:%u) stop....\r\n", ip_addr, ip_port);
+
+    if (ip_addr) {
+        aos_free(ip_addr);
+        ip_addr = NULL;
+    }
+
+    if (filter_task){
+        aos_free(filter_task);
+        filter_task = NULL;
+    }
+}
+
+static void trace_entry(void *arg)
+{
+    uint32_t len;
+    while (1) {
+        if (trace_is_started == 0 ){
+            if (sockfd > 0) {
+                trace_stop();
+            }
+
+            krhino_task_sleep(200);
+        } else {
+            if (sockfd <= 0) {
+                sockfd = (int)trace_hal_init();
+            }
+
+            if (sockfd > 0) {
+                len = fifo_out_all(&trace_fifo, trace_buf);
+                if (len > 0) {
+                    trace_hal_send((void *)sockfd, trace_buf, len);
+                }
+            }
+
+            krhino_task_sleep(20);
+        }
+    }
+}
+
+static void handle_trace_cmd(char *pwbuf, int blen, int argc, char **argv)
+{
+    const char *rtype = argc > 1 ? argv[1] : "";
+    int ret = 0;
+
+    if (strcmp(rtype, "start") == 0) {
+        trace_is_started = 1;
+
+        if (argc == 3 || argc == 4) {
+            if (ip_addr == NULL) {
+                ip_addr = (char *) aos_malloc(strlen(argv[2])+1);
+                if (ip_addr == NULL) {
+                    k_err_proc(RHINO_NO_MEM);
+                }
+
+                strncpy(ip_addr, argv[2], strlen(argv[2]));
+                ip_addr[strlen(argv[2])] = '\0';
+            }
+
+            if (argc ==4){
+                ip_port = atoi(argv[3]);
+            }
+        } else {
+            aos_cli_printf("trace must specify the host ip (port)... \r\n");
+            return ;
+        }
+
+        if (trace_task == NULL && krhino_task_dyn_create(&trace_task, "trace_task", NULL, 3,
+            0, TRACE_TASK_STACK_SIZE, trace_entry, 1) != RHINO_SUCCESS) {
+                 aos_cli_printf("trace task creat fail \r\n");
+        }
+    } else if (strcmp(rtype, "task") == 0) {
+        if (argc != 3) {
+            return;
+        }
+        if (filter_task) {
+            aos_free(filter_task);
+        }
+
+        filter_task = (char *) aos_malloc(strlen(argv[2])+1);
+        if (filter_task == NULL) {
+            k_err_proc(RHINO_NO_MEM);
+        }
+
+        strncpy(filter_task, argv[2], strlen(argv[2]));
+        filter_task[strlen(argv[2])] = '\0';
+
+        set_filter_task(filter_task);
+    } else if (strcmp(rtype, "event") == 0) {
+        if (argc != 3) {
+            return;
+        }
+
+        set_event_mask(atoi(argv[2]));
+    } else if (strcmp(rtype, "stop") == 0) {
+        trace_is_started = 0;
+    }
+}
+
+static struct cli_command ncmd = {
+    .name = "trace",
+    .help = "trace [start ip (port) | task task_name| event event_id| stop]",
+    .function = handle_trace_cmd,
+};
+
+void trace_start(void)
+{
+    aos_cli_register_command(&ncmd);
+}
+#else
+void trace_start(void)
+{
+    printf("trace config close!!!\r\n");
+}
+#endif /* Trace end*/
+#else
+void trace_start(void)
+{
+    printf("trace should have cli to control!!!\r\n");
+}
+#endif /*Cli end*/
+
+
+

Living_SDK/platform/mcu/esp32/ble_hci_driver/hci_driver.c

@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2015-2017 Alibaba Group Holding Limited
+ */
+
+#include <zephyr.h>
+#include "errno.h"
+
+#define BT_DBG_ENABLED IS_ENABLED(CONFIG_BLUETOOTH_DEBUG_HCI_DRIVER)
+
+#include <misc/slist.h>
+#include <bluetooth/bluetooth.h>
+#include <bluetooth/hci_driver.h>
+#include <common/log.h>
+#include <misc/byteorder.h>
+
+#include "bt.h"
+#include "nvs_flash.h"
+
+#define HCI_NONE    0x00
+#define HCI_CMD     0x01
+#define HCI_ACL     0x02
+#define HCI_SCO     0x03
+#define HCI_EVT     0x04
+#define MIN_HCI_LEN 4
+struct hci_cmd_send_t {
+    struct k_sem send_sem;
+    uint8_t cmd_buf[BT_BUF_RX_SIZE];
+} g_esp32_hci_send;
+
+struct hci_cmd_recv_t {
+    struct net_buf *buf;
+    uint16_t remaining;
+    bool discardable;
+    uint8_t hdr_len;
+    uint8_t type;
+    union {
+        struct bt_hci_evt_hdr evt;
+        struct bt_hci_acl_hdr acl;
+        uint8_t hdr[4];
+    };
+} g_esp32_hci_recv;
+
+/* VHCI function interface */
+typedef struct vhci_host_callback {
+    void (*notify_host_send_available)(void);               /*!< callback used to notify that the host can send packet to controller */
+    int (*notify_host_recv)(uint8_t *data, uint16_t len);   /*!< callback used to notify that the controller has a packet to send to the host*/
+} vhci_host_callback_t;
+
+static void controller_rcv_pkt_ready(void)
+{
+    k_sem_give(&g_esp32_hci_send.send_sem);
+}
+
+static inline void copy_hdr(struct net_buf *buf)
+{
+    net_buf_add_mem(buf, g_esp32_hci_recv.hdr, g_esp32_hci_recv.hdr_len);
+}
+
+static void reset_rx(void)
+{
+    g_esp32_hci_recv.type = HCI_NONE;
+    g_esp32_hci_recv.remaining = 0;
+    g_esp32_hci_recv.hdr_len = 0;
+    g_esp32_hci_recv.discardable = false;
+}
+
+static int get_hci_evt_hdr(uint8_t *data, uint16_t len)
+{
+    struct bt_hci_evt_hdr *hdr = &g_esp32_hci_recv.evt;
+    g_esp32_hci_recv.hdr_len = sizeof(struct bt_hci_evt_hdr);
+    memcpy((uint8_t *)hdr, data, g_esp32_hci_recv.hdr_len);
+
+    if (hdr->evt == BT_HCI_EVT_LE_META_EVENT) {
+        memcpy((uint8_t *)hdr + g_esp32_hci_recv.hdr_len, data \
+               + g_esp32_hci_recv.hdr_len, 1);
+        g_esp32_hci_recv.hdr_len++;
+    }
+
+    if (hdr->evt == BT_HCI_EVT_LE_META_EVENT &&
+        g_esp32_hci_recv.hdr[sizeof(*hdr)] == BT_HCI_EVT_LE_ADVERTISING_REPORT) {
+        BT_DBG("Marking adv report as discardable");
+        g_esp32_hci_recv.discardable = true;
+    }
+
+    g_esp32_hci_recv.remaining = hdr->len - (g_esp32_hci_recv.hdr_len \
+                                 - sizeof(struct bt_hci_evt_hdr));
+    return g_esp32_hci_recv.hdr_len;
+}
+
+
+static int get_hci_acl_hdr(uint8_t *data, uint16_t len)
+{
+    struct bt_hci_acl_hdr *hdr = &g_esp32_hci_recv.acl;
+    g_esp32_hci_recv.hdr_len = sizeof(struct bt_hci_acl_hdr);
+    memcpy((uint8_t *)hdr, data, g_esp32_hci_recv.hdr_len);
+    g_esp32_hci_recv.remaining = sys_le16_to_cpu(hdr->len);
+    return g_esp32_hci_recv.hdr_len;
+}
+
+static struct net_buf *get_rx(int timeout)
+{
+    BT_DBG("type 0x%02x, evt 0x%02x", g_esp32_hci_recv.type, g_esp32_hci_recv.evt.evt);
+
+    if (g_esp32_hci_recv.type == HCI_EVT && (g_esp32_hci_recv.evt.evt == BT_HCI_EVT_CMD_COMPLETE ||
+            g_esp32_hci_recv.evt.evt == BT_HCI_EVT_CMD_STATUS)) {
+        return bt_buf_get_cmd_complete(timeout);
+    }
+
+    return bt_buf_get_rx(BT_BUF_EVT, timeout);
+}
+
+static int host_rcv_pkt(uint8_t *data, uint16_t len)
+{
+    uint8_t *pdata = data;
+    uint16_t length = len;
+    bool prio;
+    struct net_buf *buf;
+
+    BT_DBG("%s", bt_hex(data, len));
+
+    if (NULL == pdata || length < MIN_HCI_LEN) {
+        BT_ERR("wrong hci data len,%d\n", len);
+        return -EINVAL;
+    }
+
+    g_esp32_hci_recv.type = *pdata++;
+    length--;
+
+    switch (g_esp32_hci_recv.type) {
+        case HCI_EVT:
+            pdata += get_hci_evt_hdr(pdata, length);
+            break;
+
+        case HCI_ACL:
+            pdata += get_hci_acl_hdr(pdata, length);
+            break;
+
+        default:
+            BT_ERR("Unknown H:4 type 0x%02x", g_esp32_hci_recv.type);
+            g_esp32_hci_recv.type = HCI_NONE;
+            return -EINVAL;
+    }
+
+    if (!g_esp32_hci_recv.buf) {
+        g_esp32_hci_recv.buf = get_rx(K_NO_WAIT);
+
+        if (!g_esp32_hci_recv.buf) {
+            if (g_esp32_hci_recv.discardable) {
+                BT_WARN("Discarding event 0x%02x", g_esp32_hci_recv.evt.evt);
+                reset_rx();
+                return 0;
+            }
+
+            BT_WARN("Failed to allocate, deferring to rx_thread");
+            return -ENOMEM;
+        }
+
+        copy_hdr(g_esp32_hci_recv.buf);
+    }
+
+    net_buf_add_mem(g_esp32_hci_recv.buf, pdata, g_esp32_hci_recv.remaining);
+
+    buf = g_esp32_hci_recv.buf;
+    g_esp32_hci_recv.buf = NULL;
+
+    if (g_esp32_hci_recv.type == HCI_EVT) {
+        bt_buf_set_type(buf, BT_BUF_EVT);
+    } else {
+        bt_buf_set_type(buf, BT_BUF_ACL_IN);
+    }
+
+    prio = (g_esp32_hci_recv.type == HCI_EVT && bt_hci_evt_is_prio(g_esp32_hci_recv.evt.evt));
+
+    reset_rx();
+
+    if (prio) {
+        BT_DBG("Calling bt_recv_prio(%p)", buf);
+        bt_recv_prio(buf);
+    } else {
+        BT_DBG("Putting buf %p to rx fifo", buf);
+        bt_recv(buf);
+    }
+
+    return 0;
+}
+
+static const esp_vhci_host_callback_t vhci_host_cb = {
+    .notify_host_send_available = controller_rcv_pkt_ready,
+    .notify_host_recv = host_rcv_pkt,
+};
+
+static int esp32_hci_driver_send(struct net_buf *buf)
+{
+    if (NULL == buf) {
+        return -EINVAL;
+    }
+
+    switch (bt_buf_get_type(buf)) {
+        case BT_BUF_ACL_OUT:
+            g_esp32_hci_send.cmd_buf[0] = HCI_ACL;
+            break;
+
+        case BT_BUF_CMD:
+            g_esp32_hci_send.cmd_buf[0] = HCI_CMD;
+            break;
+
+        default:
+            BT_ERR("Unknown buffer type");
+            return -EINVAL;
+    }
+
+    memcpy(g_esp32_hci_send.cmd_buf + 1, buf->data, buf->len);
+
+    net_buf_unref(buf);
+
+    BT_DBG("%s", bt_hex(buf->data, buf->len));
+
+    if (esp_vhci_host_check_send_available()) {
+        k_sem_take(&g_esp32_hci_send.send_sem, K_FOREVER);
+        esp_vhci_host_send_packet(g_esp32_hci_send.cmd_buf, buf->len + 1);
+    }
+
+    return 0;
+}
+
+static int esp32_hci_driver_open(void)
+{
+    esp_vhci_host_register_callback(&vhci_host_cb);
+    return 0;
+}
+
+static struct bt_hci_driver drv = {
+    .name   = "esp32 Controller",
+    .bus    = BT_HCI_DRIVER_BUS_VIRTUAL,
+    .open   = esp32_hci_driver_open,
+    .send   = esp32_hci_driver_send,
+};
+
+int hci_driver_init()
+{
+    esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT();
+    esp_err_t ret = nvs_flash_init();
+
+    if (ret == ESP_ERR_NVS_NO_FREE_PAGES) {
+        ESP_ERROR_CHECK(nvs_flash_erase());
+        ret = nvs_flash_init();
+    }
+    ESP_ERROR_CHECK( ret );
+
+    bt_cfg.controller_task_prio = 23;  // set valid task priority
+    if (esp_bt_controller_init(&bt_cfg) != ESP_OK) {
+        return -1;
+    }
+
+    if (esp_bt_controller_enable(ESP_BT_MODE_BTDM) != ESP_OK) {
+        return -1;
+    }
+
+    bt_hci_driver_register(&drv);
+    k_sem_init(&g_esp32_hci_send.send_sem, 1, 1);
+    memset(g_esp32_hci_send.cmd_buf, 0, sizeof(g_esp32_hci_send.cmd_buf));
+    return 0;
+}

Living_SDK/platform/mcu/esp32/bsp/custom_partitions.csv

@@ -0,0 +1,12 @@
+# Name,   Type, SubType, Offset,  Size, Flags
+# Note: if you change the phy_init or app partition offset, make sure to change the offset in Kconfig.projbuild
+nvs,        data, nvs,      0x9000,   0x4000,
+otadata,    data, ota,      0xD000,   0x2000,
+phy_init,   data, phy,      0xf000,   0x1000,
+factory,    app,  factory,  0x10000,  0x100000,
+ota_0,      app,  ota_0,    0x110000, 0x100000,
+ota_1,      app,  ota_1,    0x210000, 0x100000,
+parameter1, 0x40, 0,        0x310000, 0x1000,
+parameter2, 0x40, 0,        0x311000, 0x2000,       
+parameter3, 0x40, 0,        0x313000, 0x1000,
+parameter4, 0x40, 0,        0x314000, 0x1000,

Living_SDK/platform/mcu/esp32/bsp/entry.c

@@ -0,0 +1,65 @@
+#include <stdio.h>
+#include <stdint.h>
+
+#include <hal/soc/soc.h>
+#include <hal/wifi.h>
+#include <aos/aos.h>
+#include <sdkconfig.h>
+
+uart_dev_t uart_0 = {
+    .port = CONFIG_CONSOLE_UART_NUM,
+};
+
+static kinit_t kinit = {
+    .argc = 0,
+    .argv = NULL,
+    .cli_enable = 1
+};
+
+static void app_entry(void *arg)
+{
+    aos_kernel_init(&kinit);
+}
+
+#ifdef ENABLE_WIFI
+#include "lwip/sockets.h"
+int __attribute__((weak)) eventfd(unsigned int initval, int flags)
+{
+    return socket(AF_INET, SOCK_DGRAM, 0);
+}
+
+extern void tcpip_adapter_init(void);
+extern hal_wifi_module_t sim_aos_wifi_eps32;
+extern void esp32_wifi_mesh_register(void);
+static void initialise_wifi(void)
+{
+    tcpip_adapter_init();
+    hal_wifi_register_module(&sim_aos_wifi_eps32);
+#ifdef CONFIG_AOS_MESH
+    esp32_wifi_mesh_register();
+#endif
+    hal_wifi_init();
+}
+#else
+static void initialise_wifi(void)
+{
+    
+}
+#endif
+
+extern uart_dev_t uart_0;
+extern struct hal_ota_module_s esp32_yos_ota_module;
+void app_main(void)
+{
+    initialise_wifi();
+    hal_uart_init(&uart_0);
+#ifdef HCI_H4_NRF51822
+    extern void nrf51822_h4_set_uart_config();
+    nrf51822_h4_set_uart_config();
+#endif
+#if defined(CONFIG_AOS_MESH) && defined(CONFIG_BT_MESH)
+    extern void esp_bt_mesh_register(void);
+    esp_bt_mesh_register();
+#endif
+    aos_task_new("main", app_entry, 0, 8192);
+}

Living_SDK/platform/mcu/esp32/bsp/ethernetif.c

@@ -0,0 +1,230 @@
+/**
+ * @file
+ * Ethernet Interface Skeleton
+ *
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#include <stdio.h>
+#include <string.h>
+
+#include "lwip/opt.h"
+
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/stats.h"
+#include "lwip/snmp.h"
+#include "lwip/ethip6.h"
+#include "netif/etharp.h"
+
+#include "esp_eth.h"
+#include "tcpip_adapter.h"
+
+/* Define those to better describe your network interface. */
+#define IFNAME0 'e'
+#define IFNAME1 'n'
+
+/**
+ * In this function, the hardware should be initialized.
+ * Called from ethernetif_init().
+ *
+ * @param netif the already initialized lwip network interface structure
+ *        for this ethernetif
+ */
+static void
+ethernet_low_level_init(struct netif *netif)
+{ 
+  /* set MAC hardware address length */
+  netif->hwaddr_len = ETHARP_HWADDR_LEN;
+
+  /* set MAC hardware address */
+
+  /* maximum transfer unit */
+  netif->mtu = 1500;
+
+  /* device capabilities */
+  /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
+  netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP;
+
+#if LWIP_IGMP
+  netif->flags |= NETIF_FLAG_IGMP;
+#endif
+
+
+}
+
+/**
+ * This function should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
+ * @return ERR_OK if the packet could be sent
+ *         an err_t value if the packet couldn't be sent
+ *
+ * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
+ *       strange results. You might consider waiting for space in the DMA queue
+ *       to become availale since the stack doesn't retry to send a packet
+ *       dropped because of memory failure (except for the TCP timers).
+ */
+static err_t
+ethernet_low_level_output(struct netif *netif, struct pbuf *p)
+{
+  struct pbuf *q;
+  esp_interface_t eth_if = tcpip_adapter_get_esp_if(netif);
+
+  if (eth_if != ESP_IF_ETH) {
+    LWIP_DEBUGF(NETIF_DEBUG,("eth_if=%d netif=%p pbuf=%p len=%d\n", eth_if, netif, p, p->len)); 
+
+    return ERR_IF;
+  }
+
+#if 1
+  q = p;
+  u16_t pbuf_x_len = 0;
+  pbuf_x_len = q->len;
+  if(q->next !=NULL) {
+    //char cnt = 0;
+    struct pbuf *tmp = q->next;
+    while(tmp != NULL) {
+      memcpy( (u8_t *)( (u8_t *)(q->payload) + pbuf_x_len), (u8_t *)tmp->payload , tmp->len );
+      pbuf_x_len += tmp->len;
+      //cnt++;
+      tmp = tmp->next;
+    }
+  }
+
+  return esp_eth_tx(q->payload, pbuf_x_len);
+#else
+  for(q = p; q != NULL; q = q->next) {
+    return esp_emac_tx(q->payload, q->len);
+  }
+  return ERR_OK;
+#endif
+}
+
+/**
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface. Then the type of the received packet is determined and
+ * the appropriate input function is called.
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @param buffer the ethernet buffer
+ * @param len the len of buffer
+ *
+ * @note When CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE is enabled, a copy of buffer
+ *       will be made for high layer (LWIP) and ethernet is responsible for
+ *       freeing the buffer. Otherwise, high layer and ethernet share the 
+ *       same buffer and high layer is responsible for freeing the buffer.
+ */
+void
+ethernetif_input(struct netif *netif, void *buffer, uint16_t len)
+{
+  struct pbuf *p;
+
+  if(buffer== NULL || !netif_is_up(netif)) {
+    return;
+  }
+
+  p = pbuf_alloc(PBUF_RAW, len, PBUF_RAM);
+  if (p == NULL) {
+    return;
+  }
+
+  memcpy(p->payload, buffer, len);
+
+/* full packet send to tcpip_thread to process */
+if (netif->input(p, netif) != ERR_OK) {
+  LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n"));
+  pbuf_free(p);
+}
+
+
+}
+
+/**
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ * This function should be passed as a parameter to netif_add().
+ *
+ * @param netif the lwip network interface structure for this ethernetif
+ * @return ERR_OK if the loopif is initialized
+ *         ERR_MEM if private data couldn't be allocated
+ *         any other err_t on error
+ */
+err_t
+ethernetif_init(struct netif *netif)
+{
+  LWIP_ASSERT("netif != NULL", (netif != NULL));
+
+#if LWIP_NETIF_HOSTNAME
+  /* Initialize interface hostname */
+
+#if 1
+  netif->hostname = "espressif";
+#else
+  netif->hostname = "lwip";
+#endif
+
+#endif /* LWIP_NETIF_HOSTNAME */
+
+  /*
+   * Initialize the snmp variables and counters inside the struct netif.
+   * The last argument should be replaced with your link speed, in units
+   * of bits per second.
+   */
+  NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS);
+
+  netif->name[0] = IFNAME0;
+  netif->name[1] = IFNAME1;
+  /* We directly use etharp_output() here to save a function call.
+   * You can instead declare your own function an call etharp_output()
+   * from it if you have to do some checks before sending (e.g. if link
+   * is available...) */
+  netif->output = etharp_output;
+#if LWIP_IPV6
+  netif->output_ip6 = ethip6_output;
+#endif /* LWIP_IPV6 */
+  netif->linkoutput = ethernet_low_level_output;
+
+  /* initialize the hardware */
+  ethernet_low_level_init(netif);
+
+  return ERR_OK;
+}

Living_SDK/platform/mcu/esp32/bsp/ethernetif.h

@@ -0,0 +1,35 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef _ETH_LWIP_IF_H_
+#define _ETH_LWIP_IF_H_
+
+#include "lwip/err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+err_t ethernetif_init(struct netif *netif);
+
+void ethernetif_input(struct netif *netif, void *buffer, u16_t len);
+
+void netif_reg_addr_change_cb(void* cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*  _ETH_LWIP_IF_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/app_update/include/esp_ota_ops.h

@@ -0,0 +1,178 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _OTA_OPS_H
+#define _OTA_OPS_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "esp_err.h"
+#include "esp_partition.h"
+#include "esp_spi_flash.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define OTA_SIZE_UNKNOWN 0xffffffff /*!< Used for esp_ota_begin() if new image size is unknown */
+
+#define ESP_ERR_OTA_BASE                         0x1500                     /*!< Base error code for ota_ops api */
+#define ESP_ERR_OTA_PARTITION_CONFLICT           (ESP_ERR_OTA_BASE + 0x01)  /*!< Error if request was to write or erase the current running partition */
+#define ESP_ERR_OTA_SELECT_INFO_INVALID          (ESP_ERR_OTA_BASE + 0x02)  /*!< Error if OTA data partition contains invalid content */
+#define ESP_ERR_OTA_VALIDATE_FAILED              (ESP_ERR_OTA_BASE + 0x03)  /*!< Error if OTA app image is invalid */
+
+/**
+ * @brief Opaque handle for an application OTA update
+ *
+ * esp_ota_begin() returns a handle which is then used for subsequent
+ * calls to esp_ota_write() and esp_ota_end().
+ */
+typedef uint32_t esp_ota_handle_t;
+
+/**
+ * @brief   Commence an OTA update writing to the specified partition.
+
+ * The specified partition is erased to the specified image size.
+ *
+ * If image size is not yet known, pass OTA_SIZE_UNKNOWN which will
+ * cause the entire partition to be erased.
+ *
+ * On success, this function allocates memory that remains in use
+ * until esp_ota_end() is called with the returned handle.
+ *
+ * @param partition Pointer to info for partition which will receive the OTA update. Required.
+ * @param image_size Size of new OTA app image. Partition will be erased in order to receive this size of image. If 0 or OTA_SIZE_UNKNOWN, the entire partition is erased.
+ * @param out_handle On success, returns a handle which should be used for subsequent esp_ota_write() and esp_ota_end() calls.
+
+ * @return
+ *    - ESP_OK: OTA operation commenced successfully.
+ *    - ESP_ERR_INVALID_ARG: partition or out_handle arguments were NULL, or partition doesn't point to an OTA app partition.
+ *    - ESP_ERR_NO_MEM: Cannot allocate memory for OTA operation.
+ *    - ESP_ERR_OTA_PARTITION_CONFLICT: Partition holds the currently running firmware, cannot update in place.
+ *    - ESP_ERR_NOT_FOUND: Partition argument not found in partition table.
+ *    - ESP_ERR_OTA_SELECT_INFO_INVALID: The OTA data partition contains invalid data.
+ *    - ESP_ERR_INVALID_SIZE: Partition doesn't fit in configured flash size.
+ *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
+ */
+esp_err_t esp_ota_begin(const esp_partition_t* partition, size_t image_size, esp_ota_handle_t* out_handle);
+
+/**
+ * @brief   Write OTA update data to partition
+ *
+ * This function can be called multiple times as
+ * data is received during the OTA operation. Data is written
+ * sequentially to the partition.
+ *
+ * @param handle  Handle obtained from esp_ota_begin
+ * @param data    Data buffer to write
+ * @param size    Size of data buffer in bytes.
+ *
+ * @return
+ *    - ESP_OK: Data was written to flash successfully.
+ *    - ESP_ERR_INVALID_ARG: handle is invalid.
+ *    - ESP_ERR_OTA_VALIDATE_FAILED: First byte of image contains invalid app image magic byte.
+ *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash write failed.
+ *    - ESP_ERR_OTA_SELECT_INFO_INVALID: OTA data partition has invalid contents
+ */
+esp_err_t esp_ota_write(esp_ota_handle_t handle, const void* data, size_t size);
+
+/**
+ * @brief Finish OTA update and validate newly written app image.
+ *
+ * @param handle  Handle obtained from esp_ota_begin().
+ *
+ * @note After calling esp_ota_end(), the handle is no longer valid and any memory associated with it is freed (regardless of result).
+ *
+ * @return
+ *    - ESP_OK: Newly written OTA app image is valid.
+ *    - ESP_ERR_NOT_FOUND: OTA handle was not found.
+ *    - ESP_ERR_INVALID_ARG: Handle was never written to.
+ *    - ESP_ERR_OTA_VALIDATE_FAILED: OTA image is invalid (either not a valid app image, or - if secure boot is enabled - signature failed to verify.)
+ *    - ESP_ERR_INVALID_STATE: If flash encryption is enabled, this result indicates an internal error writing the final encrypted bytes to flash.
+ */
+esp_err_t esp_ota_end(esp_ota_handle_t handle);
+
+/**
+ * @brief Configure OTA data for a new boot partition
+ *
+ * @note If this function returns ESP_OK, calling esp_restart() will boot the newly configured app partition.
+ *
+ * @param partition Pointer to info for partition containing app image to boot.
+ *
+ * @return
+ *    - ESP_OK: OTA data updated, next reboot will use specified partition.
+ *    - ESP_ERR_INVALID_ARG: partition argument was NULL or didn't point to a valid OTA partition of type "app".
+ *    - ESP_ERR_OTA_VALIDATE_FAILED: Partition contained invalid app image. Also returned if secure boot is enabled and signature validation failed.
+ *    - ESP_ERR_NOT_FOUND: OTA data partition not found.
+ *    - ESP_ERR_FLASH_OP_TIMEOUT or ESP_ERR_FLASH_OP_FAIL: Flash erase or write failed.
+ */
+esp_err_t esp_ota_set_boot_partition(const esp_partition_t* partition);
+
+/**
+ * @brief Get partition info of currently configured boot app
+ *
+ * If esp_ota_set_boot_partition() has been called, the partition which was set by that function will be returned.
+ *
+ * If esp_ota_set_boot_partition() has not been called, the result is usually the same as esp_ota_get_running_partition().
+ * The two results are not equal if the configured boot partition does not contain a valid app (meaning that the running partition
+ * will be an app that the bootloader chose via fallback).
+ *
+ * If the OTA data partition is not present or not valid then the result is the first app partition found in the
+ * partition table. In priority order, this means: the factory app, the first OTA app slot, or the test app partition.
+ *
+ * Note that there is no guarantee the returned partition is a valid app. Use esp_image_load(ESP_IMAGE_VERIFY, ...) to verify if the
+ * returned partition contains a bootable image.
+ *
+ * @return Pointer to info for partition structure, or NULL if partition table is invalid or a flash read operation failed. Any returned pointer is valid for the lifetime of the application.
+ */
+const esp_partition_t* esp_ota_get_boot_partition(void);
+
+
+/**
+ * @brief Get partition info of currently running app
+ *
+ * This function is different to esp_ota_get_boot_partition() in that
+ * it ignores any change of selected boot partition caused by
+ * esp_ota_set_boot_partition(). Only the app whose code is currently
+ * running will have its partition information returned.
+ *
+ * The partition returned by this function may also differ from esp_ota_get_boot_partition() if the configured boot
+ * partition is somehow invalid, and the bootloader fell back to a different app partition at boot.
+ *
+ * @return Pointer to info for partition structure, or NULL if no partition is found or flash read operation failed. Returned pointer is valid for the lifetime of the application.
+ */
+const esp_partition_t* esp_ota_get_running_partition(void);
+
+
+/**
+ * @brief Return the next OTA app partition which should be written with a new firmware.
+ *
+ * Call this function to find an OTA app partition which can be passed to esp_ota_begin().
+ *
+ * Finds next partition round-robin, starting from the current running partition.
+ *
+ * @param start_from If set, treat this partition info as describing the current running partition. Can be NULL, in which case esp_ota_get_running_partition() is used to find the currently running partition. The result of this function is never the same as this argument.
+ *
+ * @return Pointer to info for partition which should be updated next. NULL result indicates invalid OTA data partition, or that no eligible OTA app slot partition was found.
+ *
+ */
+const esp_partition_t* esp_ota_get_next_update_partition(const esp_partition_t *start_from);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* OTA_OPS_H */

Living_SDK/platform/mcu/esp32/bsp/include/bt/include/bt.h

@@ -0,0 +1,215 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __BT_H__
+#define __BT_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_err.h"
+#include "sdkconfig.h"
+#include "esp_task.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Controller config options, depend on config mask.
+ *        Config mask indicate which functions enabled, this means 
+ *        some options or parameters of some functions enabled by config mask.
+ */
+typedef struct {
+    uint16_t controller_task_stack_size;    /*!< Bluetooth controller task stack size */
+    uint8_t controller_task_prio;           /*!< Bluetooth controller task priority */
+    uint8_t hci_uart_no;                    /*!< If use UART1/2 as HCI IO interface, indicate UART number */
+    uint32_t hci_uart_baudrate;             /*!< If use UART1/2 as HCI IO interface, indicate UART baudrate */
+} esp_bt_controller_config_t;
+
+#ifdef CONFIG_BT_ENABLED
+
+#ifdef CONFIG_BT_HCI_UART_NO
+#define BT_HCI_UART_NO_DEFAULT CONFIG_BT_HCI_UART_NO
+#else
+#define BT_HCI_UART_NO_DEFAULT 1
+#endif /* BT_HCI_UART_NO_DEFAULT */
+
+#ifdef CONFIG_BT_HCI_UART_BAUDRATE
+#define BT_HCI_UART_BAUDRATE_DEFAULT CONFIG_BT_HCI_UART_BAUDRATE
+#else
+#define BT_HCI_UART_BAUDRATE_DEFAULT 921600
+#endif /* BT_HCI_UART_BAUDRATE_DEFAULT */
+
+#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {                       \
+    .controller_task_stack_size = ESP_TASK_BT_CONTROLLER_STACK,     \
+    .controller_task_prio = ESP_TASK_BT_CONTROLLER_PRIO,            \
+    .hci_uart_no = BT_HCI_UART_NO_DEFAULT,                          \
+    .hci_uart_baudrate = BT_HCI_UART_BAUDRATE_DEFAULT,              \
+};
+#else
+#define BT_CONTROLLER_INIT_CONFIG_DEFAULT() {0}; _Static_assert(0, "please enable bluetooth in menuconfig to use bt.h");
+#endif
+
+/**
+ * @brief Bluetooth mode for controller enable/disable
+ */
+typedef enum {
+    ESP_BT_MODE_IDLE       = 0x00,   /*!< Bluetooth is not running */
+    ESP_BT_MODE_BLE        = 0x01,   /*!< Run BLE mode */
+    ESP_BT_MODE_CLASSIC_BT = 0x02,   /*!< Run Classic BT mode */
+    ESP_BT_MODE_BTDM       = 0x03,   /*!< Run dual mode */
+} esp_bt_mode_t;
+
+/**
+ * @brief Bluetooth controller enable/disable/initialised/de-initialised status
+ */
+typedef enum {
+    ESP_BT_CONTROLLER_STATUS_IDLE = 0,
+    ESP_BT_CONTROLLER_STATUS_INITED,
+    ESP_BT_CONTROLLER_STATUS_ENABLED,
+    ESP_BT_CONTROLLER_STATUS_NUM,
+} esp_bt_controller_status_t;
+
+
+/**
+ * @brief BLE tx power type
+ *        ESP_BLE_PWR_TYPE_CONN_HDL0-9: for each connection, and only be set after connetion completed.
+ *                                      when disconnect, the correspond TX power is not effected.
+ *        ESP_BLE_PWR_TYPE_ADV : for advertising/scan response.
+ *        ESP_BLE_PWR_TYPE_SCAN : for scan.
+ *        ESP_BLE_PWR_TYPE_DEFAULT : if each connection's TX power is not set, it will use this default value.
+ *                                   if neither in scan mode nor in adv mode, it will use this default value.
+ *        If none of power type is set, system will use ESP_PWR_LVL_P1 as default for ADV/SCAN/CONN0-9.
+ */
+typedef enum {
+    ESP_BLE_PWR_TYPE_CONN_HDL0  = 0,            /*!< For connection handle 0 */
+    ESP_BLE_PWR_TYPE_CONN_HDL1  = 1,            /*!< For connection handle 1 */
+    ESP_BLE_PWR_TYPE_CONN_HDL2  = 2,            /*!< For connection handle 2 */
+    ESP_BLE_PWR_TYPE_CONN_HDL3  = 3,            /*!< For connection handle 3 */
+    ESP_BLE_PWR_TYPE_CONN_HDL4  = 4,            /*!< For connection handle 4 */
+    ESP_BLE_PWR_TYPE_CONN_HDL5  = 5,            /*!< For connection handle 5 */
+    ESP_BLE_PWR_TYPE_CONN_HDL6  = 6,            /*!< For connection handle 6 */
+    ESP_BLE_PWR_TYPE_CONN_HDL7  = 7,            /*!< For connection handle 7 */
+    ESP_BLE_PWR_TYPE_CONN_HDL8  = 8,            /*!< For connection handle 8 */
+    ESP_BLE_PWR_TYPE_CONN_HDL9  = 9,            /*!< For connection handle 9 */
+    ESP_BLE_PWR_TYPE_ADV        = 10,           /*!< For advertising */
+    ESP_BLE_PWR_TYPE_SCAN       = 11,           /*!< For scan */
+    ESP_BLE_PWR_TYPE_DEFAULT    = 12,           /*!< For default, if not set other, it will use default value */
+    ESP_BLE_PWR_TYPE_NUM        = 13,           /*!< TYPE numbers */
+} esp_ble_power_type_t;
+
+/**
+ * @brief Bluetooth TX power level(index), it's just a index corresponding to power(dbm).
+ */
+typedef enum {
+    ESP_PWR_LVL_N14 = 0,            /*!< Corresponding to -14dbm */
+    ESP_PWR_LVL_N11 = 1,            /*!< Corresponding to -11dbm */
+    ESP_PWR_LVL_N8  = 2,            /*!< Corresponding to  -8dbm */
+    ESP_PWR_LVL_N5  = 3,            /*!< Corresponding to  -5dbm */
+    ESP_PWR_LVL_N2  = 4,            /*!< Corresponding to  -2dbm */
+    ESP_PWR_LVL_P1  = 5,            /*!< Corresponding to   1dbm */
+    ESP_PWR_LVL_P4  = 6,            /*!< Corresponding to   4dbm */
+    ESP_PWR_LVL_P7  = 7,            /*!< Corresponding to   7dbm */
+} esp_power_level_t;
+
+/**
+ * @brief  Set BLE TX power
+ *         Connection Tx power should only be set after connection created.
+ * @param  power_type : The type of which tx power, could set Advertising/Connection/Default and etc
+ * @param  power_level: Power level(index) corresponding to absolute value(dbm)
+ * @return              ESP_OK - success, other - failed
+ */
+esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level);
+
+/**
+ * @brief  Get BLE TX power
+ *         Connection Tx power should only be get after connection created.
+ * @param  power_type : The type of which tx power, could set Advertising/Connection/Default and etc
+ * @return             >= 0 - Power level, < 0 - Invalid
+ */
+esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type);
+
+
+/**
+ * @brief  Initialize BT controller to allocate task and other resource.
+ * @param  cfg: Initial configuration of BT controller.
+ * This function should be called only once, before any other BT functions are called.
+ * @return       ESP_OK - success, other - failed
+ */
+esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg);
+
+/**
+ * @brief  De-initialize BT controller to free resource and delete task.
+ *
+ * This function should be called only once, after any other BT functions are called.
+ * This function is not whole completed, esp_bt_controller_init cannot called after this function.
+ * @return  ESP_OK - success, other - failed
+ */
+esp_err_t esp_bt_controller_deinit(void);
+
+/**
+ * @brief Enable BT controller
+ * @param mode : the mode(BLE/BT/BTDM) to enable.
+ *               Now only support BTDM.
+ * @return       ESP_OK - success, other - failed
+ */
+esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode);
+
+/**
+ * @brief  Disable BT controller
+ * @param mode : the mode(BLE/BT/BTDM) to disable.
+ *               Now only support BTDM.
+ * @return       ESP_OK - success, other - failed
+ */
+esp_err_t esp_bt_controller_disable(esp_bt_mode_t mode);
+
+/**
+ * @brief  Get BT controller is initialised/de-initialised/enabled/disabled
+ * @return status value
+ */
+esp_bt_controller_status_t esp_bt_controller_get_status(void);
+
+/** @brief esp_vhci_host_callback
+ *  used for vhci call host function to notify what host need to do
+ */
+typedef struct esp_vhci_host_callback {
+    void (*notify_host_send_available)(void);               /*!< callback used to notify that the host can send packet to controller */
+    int (*notify_host_recv)(uint8_t *data, uint16_t len);   /*!< callback used to notify that the controller has a packet to send to the host*/
+} esp_vhci_host_callback_t;
+
+/** @brief esp_vhci_host_check_send_available
+ *  used for check actively if the host can send packet to controller or not.
+ *  @return true for ready to send, false means cannot send packet
+ */
+bool esp_vhci_host_check_send_available(void);
+
+/** @brief esp_vhci_host_send_packet
+ * host send packet to controller
+ * @param data the packet point
+ *,@param len the packet length
+ */
+void esp_vhci_host_send_packet(uint8_t *data, uint16_t len);
+
+/** @brief esp_vhci_host_register_callback
+ * register the vhci referece callback, the call back
+ * struct defined by vhci_host_callback structure.
+ * @param callback esp_vhci_host_callback type variable
+ */
+void esp_vhci_host_register_callback(const esp_vhci_host_callback_t *callback);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BT_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/container/include/ringbuf.h

@@ -0,0 +1,248 @@
+#ifndef FREERTOS_RINGBUF_H
+#define FREERTOS_RINGBUF_H
+
+/*
+Header definitions for a FreeRTOS ringbuffer object
+
+A ringbuffer instantiated by these functions essentially acts like a FreeRTOS queue, with the
+difference that it's strictly FIFO and with the main advantage that you can put in randomly-sized
+items. The capacity, accordingly, isn't measured in the amount of items, but the amount of memory
+that is used for storing the items. Dependent on the size of the items, more or less of them will 
+fit in the ring buffer.
+
+This ringbuffer tries to be efficient with memory: when inserting an item, the item data will
+be copied to the ringbuffer memory. When retrieving an item, however, a reference to ringbuffer
+memory will be returned. The returned memory is guaranteed to be 32-bit aligned and contiguous.
+The application can use this memory, but as long as it does, ringbuffer writes that would write
+to this bit of memory will block.
+
+The requirement for items to be contiguous is slightly problematic when the only way to place
+the next item would involve a wraparound from the end to the beginning of the ringbuffer. This can
+be solved (or not) in a few ways:
+- type = RINGBUF_TYPE_ALLOWSPLIT: The insertion code will split the item in two items; one which fits
+in the space left at the end of the ringbuffer, one that contains the remaining data which is placed
+in the beginning. Two xRingbufferReceive calls will be needed to retrieve the data.
+- type = RINGBUF_TYPE_NOSPLIT: The insertion code will leave the room at the end of the ringbuffer
+unused and instead will put the entire item at the start of the ringbuffer, as soon as there is 
+enough free space.
+- type = RINGBUF_TYPE_BYTEBUF: This is your conventional byte-based ringbuffer. It does have no
+overhead, but it has no item contiguousness either: a read will just give you the entire written
+buffer space, or the space up to the end of the buffer, and writes can be broken up in any way 
+possible. Note that this type cannot do a 2nd read before returning the memory of the 1st.
+
+The maximum size of an item will be affected by this decision. When split items are allowed, it's
+acceptable to push items of (buffer_size)-16 bytes into the buffer. When it's not allowed, the
+maximum size is (buffer_size/2)-8 bytes. The bytebuf can fill the entire buffer with data, it has
+no overhead.
+*/
+
+#include "espos_time.h"
+
+//An opaque handle for a ringbuff object.
+typedef void * RingbufHandle_t;
+
+//The various types of buffer
+typedef enum {
+	RINGBUF_TYPE_NOSPLIT = 0,
+	RINGBUF_TYPE_ALLOWSPLIT,
+	RINGBUF_TYPE_BYTEBUF
+} ringbuf_type_t;
+
+
+/**
+ * @brief  Create a ring buffer
+ *
+ * @param  buf_length : Length of circular buffer, in bytes. Each entry will take up its own length, plus a header
+ *                      that at the moment is equal to sizeof(size_t).
+ * @param allow_split_items : pdTRUE if it is acceptable that item data is inserted as two
+ *                            items instead of one.
+ *
+ * @return A RingbufHandle_t handle to the created ringbuffer, or NULL in case of error.
+ */
+RingbufHandle_t xRingbufferCreate(size_t buf_length, ringbuf_type_t type);
+
+
+/**
+ * @brief  Delete a ring buffer
+ *
+ * @param  ringbuf - Ring buffer to delete
+ *
+ * @return void
+ */
+void vRingbufferDelete(RingbufHandle_t ringbuf);
+
+
+/**
+ * @brief  Get maximum size of an item that can be placed in the ring buffer
+ *
+ * @param  ringbuf - Ring buffer to query
+ *
+ * @return Maximum size, in bytes, of an item that can be placed in a ring buffer.
+ */
+size_t xRingbufferGetMaxItemSize(RingbufHandle_t ringbuf);
+
+
+/**
+ * @brief  Insert an item into the ring buffer
+ *
+ * @param  ringbuf - Ring buffer to insert the item into
+ * @param  data - Pointer to data to insert. NULL is allowed if data_size is 0.
+ * @param  data_size - Size of data to insert. A value of 0 is allowed.
+ * @param  xTicksToWait - Ticks to wait for room in the ringbuffer.
+ *
+ * @return pdTRUE if succeeded, pdFALSE on time-out or when the buffer is larger 
+ *         than indicated by xRingbufferGetMaxItemSize(ringbuf).
+ */
+int xRingbufferSend(RingbufHandle_t ringbuf, void *data, size_t data_size, espos_tick_t ticks_to_wait);
+
+
+/**
+ * @brief  Insert an item into the ring buffer from an ISR
+ *
+ * @param  ringbuf - Ring buffer to insert the item into
+ * @param  data - Pointer to data to insert. NULL is allowed if data_size is 0.
+ * @param  data_size - Size of data to insert. A value of 0 is allowed.
+ * @param  higher_prio_task_awoken - Value pointed to will be set to pdTRUE if the push woke up a higher
+ *                                     priority task.
+ *
+ * @return pdTRUE if succeeded, pdFALSE when the ring buffer does not have space.
+ */
+int xRingbufferSendFromISR(RingbufHandle_t ringbuf, void *data, size_t data_size, int *higher_prio_task_awoken);
+
+/**
+ * @brief  Retrieve an item from the ring buffer
+ *
+ * @param  ringbuf - Ring buffer to retrieve the item from
+ * @param  item_size - Pointer to a variable to which the size of the retrieved item will be written.
+ * @param  xTicksToWait - Ticks to wait for items in the ringbuffer.
+ *
+ * @return Pointer to the retrieved item on success; *item_size filled with the length of the 
+ *         item. NULL on timeout, *item_size is untouched in that case.
+ */
+void *xRingbufferReceive(RingbufHandle_t ringbuf, size_t *item_size, espos_tick_t ticks_to_wait);
+
+
+/**
+ * @brief  Retrieve an item from the ring buffer from an ISR
+ *
+ * @param  ringbuf - Ring buffer to retrieve the item from
+ * @param  item_size - Pointer to a variable to which the size of the retrieved item will be written.
+ *
+ * @return Pointer to the retrieved item on success; *item_size filled with the length of the 
+ *         item. NULL when the ringbuffer is empty, *item_size is untouched in that case.
+ */
+void *xRingbufferReceiveFromISR(RingbufHandle_t ringbuf, size_t *item_size);
+
+
+/**
+ * @brief  Retrieve bytes from a ByteBuf type of ring buffer, specifying the maximum amount of bytes
+ * to return
+ *
+ * @param  ringbuf - Ring buffer to retrieve the item from
+ * @param  item_size - Pointer to a variable to which the size of the retrieved item will be written.
+ * @param  xTicksToWait - Ticks to wait for items in the ringbuffer.
+ *
+ * @return Pointer to the retrieved item on success; *item_size filled with the length of the 
+ *         item. NULL on timeout, *item_size is untouched in that case.
+ */
+void *xRingbufferReceiveUpTo(RingbufHandle_t ringbuf, size_t *item_size, espos_tick_t ticks_to_wait, size_t wanted_size);
+
+
+/**
+ * @brief  Retrieve bytes from a ByteBuf type of ring buffer, specifying the maximum amount of bytes
+ * to return. Call this from an ISR.
+ *
+ * @param  ringbuf - Ring buffer to retrieve the item from
+ * @param  item_size - Pointer to a variable to which the size of the retrieved item will be written.
+ *
+ * @return Pointer to the retrieved item on success; *item_size filled with the length of the 
+ *         item. NULL when the ringbuffer is empty, *item_size is untouched in that case.
+ */
+void *xRingbufferReceiveUpToFromISR(RingbufHandle_t ringbuf, size_t *item_size, size_t wanted_size);
+
+
+
+/**
+ * @brief  Return a previously-retrieved item to the ringbuffer
+ *
+ * @param  ringbuf - Ring buffer the item was retrieved from
+ * @param  item - Item that was received earlier
+ *
+ * @return void
+ */
+void vRingbufferReturnItem(RingbufHandle_t ringbuf, void *item);
+
+
+
+/**
+ * @brief  Return a previously-retrieved item to the ringbuffer from an ISR
+ *
+ * @param  ringbuf - Ring buffer the item was retrieved from
+ * @param  item - Item that was received earlier
+ * @param  higher_prio_task_awoken - Value pointed to will be set to pdTRUE if the push woke up a higher
+ *                                     priority task.
+ *
+ * @return void
+ */
+void vRingbufferReturnItemFromISR(RingbufHandle_t ringbuf, void *item, int *higher_prio_task_awoken);
+
+
+// /**
+//  * @brief  Add the ringbuffer to a queue set. This specifically adds the semaphore that indicates
+//  *         more space has become available in the ringbuffer.
+//  *
+//  * @param  ringbuf - Ring buffer to add to the queue set
+//  * @param  xQueueSet - Queue set to add the ringbuffer to
+//  *
+//  * @return pdTRUE on success, pdFALSE otherwise
+//  */
+// int xRingbufferAddToQueueSetRead(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet);
+
+
+// /**
+//  * @brief  Add the ringbuffer to a queue set. This specifically adds the semaphore that indicates
+//  *         something has been written into the ringbuffer.
+//  *
+//  * @param  ringbuf - Ring buffer to add to the queue set
+//  * @param  xQueueSet - Queue set to add the ringbuffer to
+//  *
+//  * @return pdTRUE on success, pdFALSE otherwise
+//  */
+// int xRingbufferAddToQueueSetWrite(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet);
+
+
+// /**
+//  * @brief  Remove the ringbuffer from a queue set. This specifically removes the semaphore that indicates
+//  *         more space has become available in the ringbuffer.
+//  *
+//  * @param  ringbuf - Ring buffer to remove from the queue set
+//  * @param  xQueueSet - Queue set to remove the ringbuffer from
+//  *
+//  * @return pdTRUE on success, pdFALSE otherwise
+//  */
+// int xRingbufferRemoveFromQueueSetRead(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet);
+
+
+// /**
+//  * @brief  Remove the ringbuffer from a queue set. This specifically removes the semaphore that indicates
+//  *         something has been written to the ringbuffer.
+//  *
+//  * @param  ringbuf - Ring buffer to remove from the queue set
+//  * @param  xQueueSet - Queue set to remove the ringbuffer from
+//  *
+//  * @return pdTRUE on success, pdFALSE otherwise
+//  */
+// int xRingbufferRemoveFromQueueSetWrite(RingbufHandle_t ringbuf, QueueSetHandle_t xQueueSet);
+
+
+/**
+ * @brief  Debugging function to print the internal pointers in the ring buffer
+ *
+ * @param  ringbuf - Ring buffer to show
+ *
+ * @return void
+ */
+void xRingbufferPrintInfo(RingbufHandle_t ringbuf);
+
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/cpidf.sh

@@ -0,0 +1,11 @@
+#!bash
+target=$(dirname $0)
+cd $target
+dirs="esp32/include soc/esp32/include soc/include driver/include ethernet/include log/include nvs_flash/include spi_flash/include container/include"
+for d in $dirs;
+do
+    t=$(dirname $d)
+    mkdir -p $t
+    cp -r $IDF_PATH/components/$d $t
+done
+cd -

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/adc.h

@@ -0,0 +1,170 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_ADC_H_
+#define _DRIVER_ADC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "driver/gpio.h"
+
+typedef enum {
+    ADC_ATTEN_0db   = 0,  /*!<The input voltage of ADC will be reduced to about 1/1 */
+    ADC_ATTEN_2_5db = 1,  /*!<The input voltage of ADC will be reduced to about 1/1.34 */
+    ADC_ATTEN_6db   = 2,  /*!<The input voltage of ADC will be reduced to about 1/2 */
+    ADC_ATTEN_11db  = 3,  /*!<The input voltage of ADC will be reduced to about 1/3.6*/
+} adc_atten_t;
+
+typedef enum {
+    ADC_WIDTH_9Bit  = 0, /*!< ADC capture width is 9Bit*/
+    ADC_WIDTH_10Bit = 1, /*!< ADC capture width is 10Bit*/
+    ADC_WIDTH_11Bit = 2, /*!< ADC capture width is 11Bit*/
+    ADC_WIDTH_12Bit = 3, /*!< ADC capture width is 12Bit*/
+} adc_bits_width_t;
+
+typedef enum {
+    ADC1_CHANNEL_0 = 0, /*!< ADC1 channel 0 is GPIO36 */
+    ADC1_CHANNEL_1,     /*!< ADC1 channel 1 is GPIO37 */
+    ADC1_CHANNEL_2,     /*!< ADC1 channel 2 is GPIO38 */
+    ADC1_CHANNEL_3,     /*!< ADC1 channel 3 is GPIO39 */
+    ADC1_CHANNEL_4,     /*!< ADC1 channel 4 is GPIO32 */
+    ADC1_CHANNEL_5,     /*!< ADC1 channel 5 is GPIO33 */
+    ADC1_CHANNEL_6,     /*!< ADC1 channel 6 is GPIO34 */
+    ADC1_CHANNEL_7,     /*!< ADC1 channel 7 is GPIO35 */
+    ADC1_CHANNEL_MAX,
+} adc1_channel_t;
+
+/**
+ * @brief Configure ADC1 capture width.
+ *
+ * The configuration is for all channels of ADC1
+ *
+ * @param width_bit Bit capture width for ADC1
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t adc1_config_width(adc_bits_width_t width_bit);
+
+/**
+ * @brief Configure the ADC1 channel, including setting attenuation.
+ *
+ * @note This function also configures the input GPIO pin mux to
+ * connect it to the ADC1 channel. It must be called before calling
+ * adc1_get_raw() for this channel.
+ *
+ * The default ADC full-scale voltage is 1.1V. To read higher voltages (up to the pin maximum voltage,
+ * usually 3.3V) requires setting >0dB signal attenuation for that ADC channel.
+ *
+ * When VDD_A is 3.3V:
+ *
+ * - 0dB attenuaton (ADC_ATTEN_0db) gives full-scale voltage 1.1V
+ * - 2.5dB attenuation (ADC_ATTEN_2_5db) gives full-scale voltage 1.5V
+ * - 6dB attenuation (ADC_ATTEN_6db) gives full-scale voltage 2.2V
+ * - 11dB attenuation (ADC_ATTEN_11db) gives full-scale voltage 3.9V (see note below)
+ *
+ * @note The full-scale voltage is the voltage corresponding to a maximum reading (depending on ADC1 configured
+ * bit width, this value is: 4095 for 12-bits, 2047 for 11-bits, 1023 for 10-bits, 511 for 9 bits.)
+ *
+ * @note At 11dB attenuation the maximum voltage is limited by VDD_A, not the full scale voltage.
+ *
+ * @param channel ADC1 channel to configure
+ * @param atten  Attenuation level
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten);
+
+/**
+ * @brief Take an ADC1 reading on a single channel
+ *
+ * @note Call adc1_config_width() before the first time this
+ * function is called.
+ *
+ * @note For a given channel, adc1_config_channel_atten(channel)
+ * must be called before the first time this function is called.
+ *
+ * @param  channel ADC1 channel to read
+ *
+ * @return
+ *     - -1: Parameter error
+ *     -  Other: ADC1 channel reading.
+ */
+int adc1_get_raw(adc1_channel_t channel);
+
+/** @cond */    //Doxygen command to hide deprecated function from API Reference
+/*
+ * @deprecated This function returns an ADC1 reading but is deprecated due to
+ * a misleading name and has been changed to directly call the new function.
+ * Use the new function adc1_get_raw() instead
+ */
+int adc1_get_voltage(adc1_channel_t channel) __attribute__((deprecated));
+/** @endcond */
+
+/**
+ * @brief Configure ADC1 to be usable by the ULP
+ *
+ * This function reconfigures ADC1 to be controlled by the ULP.
+ * Effect of this function can be reverted using adc1_get_raw function.
+ *
+ * Note that adc1_config_channel_atten, adc1_config_width functions need
+ * to be called to configure ADC1 channels, before ADC1 is used by the ULP.
+ */
+void adc1_ulp_enable();
+
+/**
+ * @brief Read Hall Sensor
+ *
+ * @note The Hall Sensor uses channels 0 and 3 of ADC1. Do not configure
+ * these channels for use as ADC channels.
+ *
+ * @note The ADC1 module must be enabled by calling
+ *       adc1_config_width() before calling hall_sensor_read(). ADC1
+ *       should be configured for 12 bit readings, as the hall sensor
+ *       readings are low values and do not cover the full range of the
+ *       ADC.
+ *
+ * @return The hall sensor reading.
+ */
+int hall_sensor_read();
+
+/**
+ *  @brief Output ADC2 reference voltage to gpio 25 or 26 or 27
+ *
+ *  This function utilizes the testing mux exclusive to ADC 2 to route the
+ *  reference voltage one of ADC2's channels. Supported gpios are gpios
+ *  25, 26, and 27. This refernce voltage can be manually read from the pin
+ *  and used in the esp_adc_cal component.
+ *
+ *  @param[in]  gpio    GPIO number (gpios 25,26,27 supported)
+ *
+ *  @return
+ *                  - ESP_OK: v_ref successfully routed to selected gpio
+ *                  - ESP_ERR_INVALID_ARG: Unsupported gpio
+ */
+esp_err_t adc2_vref_to_gpio(gpio_num_t gpio);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*_DRIVER_ADC_H_*/
+

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/dac.h

@@ -0,0 +1,99 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_DAC_H_
+#define _DRIVER_DAC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "esp_err.h"
+
+typedef enum {
+    DAC_CHANNEL_1 = 1,  /*!< DAC channel 1 is GPIO25 */
+    DAC_CHANNEL_2,      /*!< DAC channel 2 is GPIO26 */
+    DAC_CHANNEL_MAX,
+} dac_channel_t;
+
+/** @cond */
+/**
+  * @brief  Set DAC output voltage.
+  *
+  * @note Function has been deprecated, please use dac_output_voltage instead.
+  *       This name will be removed in a future release.
+  *       The difference is that before calling dac_output_voltage, we need to initialize the dac pad by dac_output_enable
+  *
+  *
+  * @param channel DAC channel
+  * @param dac_value DAC output value
+  *
+  * @return
+  *     - ESP_OK success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t dac_out_voltage(dac_channel_t channel, uint8_t dac_value) __attribute__ ((deprecated));
+/** @endcond */
+
+/**
+ * @brief Set DAC output voltage.
+ *
+ * DAC output is 8-bit. Maximum (255) corresponds to VDD.
+ *
+ * @note Need to configure DAC pad before calling this function.
+ *       DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
+ *
+ * @param channel DAC channel
+ * @param dac_value DAC output value
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t dac_output_voltage(dac_channel_t channel, uint8_t dac_value);
+
+/**
+ * @brief DAC pad output enable
+ *
+ * @param channel DAC channel
+ * @note DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
+ *       I2S left channel will be mapped to DAC channel 2
+ *       I2S right channel will be mapped to DAC channel 1
+ */
+esp_err_t dac_output_enable(dac_channel_t channel);
+
+/**
+ * @brief DAC pad output disable
+ *
+ * @param channel DAC channel
+ * @note DAC channel 1 is attached to GPIO25, DAC channel 2 is attached to GPIO26
+ */
+esp_err_t dac_output_disable(dac_channel_t channel);
+
+/**
+ * @brief Enable DAC output data from I2S
+ */
+esp_err_t dac_i2s_enable();
+
+/**
+ * @brief Disable DAC output data from I2S
+ */
+esp_err_t dac_i2s_disable();
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*_DRIVER_DAC_H_*/
+

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/gpio.h

@@ -0,0 +1,520 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_GPIO_H_
+#define _DRIVER_GPIO_H_
+#include "esp_err.h"
+#include <esp_types.h>
+#include "soc/gpio_reg.h"
+#include "soc/gpio_struct.h"
+#include "soc/rtc_io_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/gpio_sig_map.h"
+#include "rom/gpio.h"
+#include "esp_attr.h"
+#include "esp_intr_alloc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GPIO_SEL_0              (BIT(0))                         /*!< Pin 0 selected */
+#define GPIO_SEL_1              (BIT(1))                         /*!< Pin 1 selected */
+#define GPIO_SEL_2              (BIT(2))                         /*!< Pin 2 selected 
+                                                                      @note There are more macros
+                                                                      like that up to pin 39,
+                                                                      excluding pins 20, 24 and 28..31.
+                                                                      They are not shown here 
+                                                                      to reduce redundant information. */
+/** @cond */
+#define GPIO_SEL_3              (BIT(3))                         /*!< Pin 3 selected */
+#define GPIO_SEL_4              (BIT(4))                         /*!< Pin 4 selected */
+#define GPIO_SEL_5              (BIT(5))                         /*!< Pin 5 selected */
+#define GPIO_SEL_6              (BIT(6))                         /*!< Pin 6 selected */
+#define GPIO_SEL_7              (BIT(7))                         /*!< Pin 7 selected */
+#define GPIO_SEL_8              (BIT(8))                         /*!< Pin 8 selected */
+#define GPIO_SEL_9              (BIT(9))                         /*!< Pin 9 selected */
+#define GPIO_SEL_10             (BIT(10))                        /*!< Pin 10 selected */
+#define GPIO_SEL_11             (BIT(11))                        /*!< Pin 11 selected */
+#define GPIO_SEL_12             (BIT(12))                        /*!< Pin 12 selected */
+#define GPIO_SEL_13             (BIT(13))                        /*!< Pin 13 selected */
+#define GPIO_SEL_14             (BIT(14))                        /*!< Pin 14 selected */
+#define GPIO_SEL_15             (BIT(15))                        /*!< Pin 15 selected */
+#define GPIO_SEL_16             (BIT(16))                        /*!< Pin 16 selected */
+#define GPIO_SEL_17             (BIT(17))                        /*!< Pin 17 selected */
+#define GPIO_SEL_18             (BIT(18))                        /*!< Pin 18 selected */
+#define GPIO_SEL_19             (BIT(19))                        /*!< Pin 19 selected */
+
+#define GPIO_SEL_21             (BIT(21))                        /*!< Pin 21 selected */
+#define GPIO_SEL_22             (BIT(22))                        /*!< Pin 22 selected */
+#define GPIO_SEL_23             (BIT(23))                        /*!< Pin 23 selected */
+
+#define GPIO_SEL_25             (BIT(25))                        /*!< Pin 25 selected */
+#define GPIO_SEL_26             (BIT(26))                        /*!< Pin 26 selected */
+#define GPIO_SEL_27             (BIT(27))                        /*!< Pin 27 selected */
+
+#define GPIO_SEL_32             ((uint64_t)(((uint64_t)1)<<32))  /*!< Pin 32 selected */
+#define GPIO_SEL_33             ((uint64_t)(((uint64_t)1)<<33))  /*!< Pin 33 selected */
+#define GPIO_SEL_34             ((uint64_t)(((uint64_t)1)<<34))  /*!< Pin 34 selected */
+#define GPIO_SEL_35             ((uint64_t)(((uint64_t)1)<<35))  /*!< Pin 35 selected */
+#define GPIO_SEL_36             ((uint64_t)(((uint64_t)1)<<36))  /*!< Pin 36 selected */
+#define GPIO_SEL_37             ((uint64_t)(((uint64_t)1)<<37))  /*!< Pin 37 selected */
+#define GPIO_SEL_38             ((uint64_t)(((uint64_t)1)<<38))  /*!< Pin 38 selected */
+#define GPIO_SEL_39             ((uint64_t)(((uint64_t)1)<<39))  /*!< Pin 39 selected */
+
+#define GPIO_PIN_REG_0          PERIPHS_IO_MUX_GPIO0_U
+#define GPIO_PIN_REG_1          PERIPHS_IO_MUX_U0TXD_U
+#define GPIO_PIN_REG_2          PERIPHS_IO_MUX_GPIO2_U
+#define GPIO_PIN_REG_3          PERIPHS_IO_MUX_U0RXD_U
+#define GPIO_PIN_REG_4          PERIPHS_IO_MUX_GPIO4_U
+#define GPIO_PIN_REG_5          PERIPHS_IO_MUX_GPIO5_U
+#define GPIO_PIN_REG_6          PERIPHS_IO_MUX_SD_CLK_U
+#define GPIO_PIN_REG_7          PERIPHS_IO_MUX_SD_DATA0_U
+#define GPIO_PIN_REG_8          PERIPHS_IO_MUX_SD_DATA1_U
+#define GPIO_PIN_REG_9          PERIPHS_IO_MUX_SD_DATA2_U
+#define GPIO_PIN_REG_10         PERIPHS_IO_MUX_SD_DATA3_U
+#define GPIO_PIN_REG_11         PERIPHS_IO_MUX_SD_CMD_U
+#define GPIO_PIN_REG_12         PERIPHS_IO_MUX_MTDI_U
+#define GPIO_PIN_REG_13         PERIPHS_IO_MUX_MTCK_U
+#define GPIO_PIN_REG_14         PERIPHS_IO_MUX_MTMS_U
+#define GPIO_PIN_REG_15         PERIPHS_IO_MUX_MTDO_U
+#define GPIO_PIN_REG_16         PERIPHS_IO_MUX_GPIO16_U
+#define GPIO_PIN_REG_17         PERIPHS_IO_MUX_GPIO17_U
+#define GPIO_PIN_REG_18         PERIPHS_IO_MUX_GPIO18_U
+#define GPIO_PIN_REG_19         PERIPHS_IO_MUX_GPIO19_U
+#define GPIO_PIN_REG_20         PERIPHS_IO_MUX_GPIO20_U
+#define GPIO_PIN_REG_21         PERIPHS_IO_MUX_GPIO21_U
+#define GPIO_PIN_REG_22         PERIPHS_IO_MUX_GPIO22_U
+#define GPIO_PIN_REG_23         PERIPHS_IO_MUX_GPIO23_U
+#define GPIO_PIN_REG_25         PERIPHS_IO_MUX_GPIO25_U
+#define GPIO_PIN_REG_26         PERIPHS_IO_MUX_GPIO26_U
+#define GPIO_PIN_REG_27         PERIPHS_IO_MUX_GPIO27_U
+#define GPIO_PIN_REG_32         PERIPHS_IO_MUX_GPIO32_U
+#define GPIO_PIN_REG_33         PERIPHS_IO_MUX_GPIO33_U
+#define GPIO_PIN_REG_34         PERIPHS_IO_MUX_GPIO34_U
+#define GPIO_PIN_REG_35         PERIPHS_IO_MUX_GPIO35_U
+#define GPIO_PIN_REG_36         PERIPHS_IO_MUX_GPIO36_U
+#define GPIO_PIN_REG_37         PERIPHS_IO_MUX_GPIO37_U
+#define GPIO_PIN_REG_38         PERIPHS_IO_MUX_GPIO38_U
+#define GPIO_PIN_REG_39         PERIPHS_IO_MUX_GPIO39_U
+
+#define GPIO_APP_CPU_INTR_ENA      (BIT(0))
+#define GPIO_APP_CPU_NMI_INTR_ENA  (BIT(1))
+#define GPIO_PRO_CPU_INTR_ENA      (BIT(2))
+#define GPIO_PRO_CPU_NMI_INTR_ENA  (BIT(3))
+#define GPIO_SDIO_EXT_INTR_ENA     (BIT(4))
+
+#define GPIO_MODE_DEF_INPUT           (BIT0)
+#define GPIO_MODE_DEF_OUTPUT          (BIT1)
+#define GPIO_MODE_DEF_OD              (BIT2)
+
+#define GPIO_PIN_COUNT              40
+/** @endcond */
+
+extern const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT];
+#define GPIO_IS_VALID_GPIO(gpio_num)      ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0))   /*!< Check whether it is a valid GPIO number */
+#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num)      ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 34))         /*!< Check whether it can be a valid GPIO number of output mode */
+
+typedef enum {
+    GPIO_NUM_0 = 0,     /*!< GPIO0, input and output */
+    GPIO_NUM_1 = 1,     /*!< GPIO1, input and output */
+    GPIO_NUM_2 = 2,     /*!< GPIO2, input and output
+                             @note There are more enumerations like that
+                             up to GPIO39, excluding GPIO20, GPIO24 and GPIO28..31.
+                             They are not shown here to reduce redundant information.
+                             @note GPIO34..39 are input mode only. */
+/** @cond */
+    GPIO_NUM_3 = 3,     /*!< GPIO3, input and output */
+    GPIO_NUM_4 = 4,     /*!< GPIO4, input and output */
+    GPIO_NUM_5 = 5,     /*!< GPIO5, input and output */
+    GPIO_NUM_6 = 6,     /*!< GPIO6, input and output */
+    GPIO_NUM_7 = 7,     /*!< GPIO7, input and output */
+    GPIO_NUM_8 = 8,     /*!< GPIO8, input and output */
+    GPIO_NUM_9 = 9,     /*!< GPIO9, input and output */
+    GPIO_NUM_10 = 10,   /*!< GPIO10, input and output */
+    GPIO_NUM_11 = 11,   /*!< GPIO11, input and output */
+    GPIO_NUM_12 = 12,   /*!< GPIO12, input and output */
+    GPIO_NUM_13 = 13,   /*!< GPIO13, input and output */
+    GPIO_NUM_14 = 14,   /*!< GPIO14, input and output */
+    GPIO_NUM_15 = 15,   /*!< GPIO15, input and output */
+    GPIO_NUM_16 = 16,   /*!< GPIO16, input and output */
+    GPIO_NUM_17 = 17,   /*!< GPIO17, input and output */
+    GPIO_NUM_18 = 18,   /*!< GPIO18, input and output */
+    GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
+
+    GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
+    GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
+    GPIO_NUM_23 = 23,   /*!< GPIO23, input and output */
+
+    GPIO_NUM_25 = 25,   /*!< GPIO25, input and output */
+    GPIO_NUM_26 = 26,   /*!< GPIO26, input and output */
+    GPIO_NUM_27 = 27,   /*!< GPIO27, input and output */
+
+    GPIO_NUM_32 = 32,   /*!< GPIO32, input and output */
+    GPIO_NUM_33 = 33,   /*!< GPIO33, input and output */
+    GPIO_NUM_34 = 34,   /*!< GPIO34, input mode only */
+    GPIO_NUM_35 = 35,   /*!< GPIO35, input mode only */
+    GPIO_NUM_36 = 36,   /*!< GPIO36, input mode only */
+    GPIO_NUM_37 = 37,   /*!< GPIO37, input mode only */
+    GPIO_NUM_38 = 38,   /*!< GPIO38, input mode only */
+    GPIO_NUM_39 = 39,   /*!< GPIO39, input mode only */
+    GPIO_NUM_MAX = 40,
+/** @endcond */    
+} gpio_num_t;
+
+typedef enum {
+    GPIO_INTR_DISABLE = 0,     /*!< Disable GPIO interrupt                             */
+    GPIO_INTR_POSEDGE = 1,     /*!< GPIO interrupt type : rising edge                  */
+    GPIO_INTR_NEGEDGE = 2,     /*!< GPIO interrupt type : falling edge                 */
+    GPIO_INTR_ANYEDGE = 3,     /*!< GPIO interrupt type : both rising and falling edge */
+    GPIO_INTR_LOW_LEVEL = 4,   /*!< GPIO interrupt type : input low level trigger      */
+    GPIO_INTR_HIGH_LEVEL = 5,  /*!< GPIO interrupt type : input high level trigger     */
+    GPIO_INTR_MAX,
+} gpio_int_type_t;
+
+typedef enum {
+    GPIO_MODE_INPUT = GPIO_MODE_DEF_INPUT,                                                         /*!< GPIO mode : input only                           */
+    GPIO_MODE_OUTPUT = GPIO_MODE_DEF_OUTPUT,                                                       /*!< GPIO mode : output only mode                     */
+    GPIO_MODE_OUTPUT_OD = ((GPIO_MODE_DEF_OUTPUT)|(GPIO_MODE_DEF_OD)),                             /*!< GPIO mode : output only with open-drain mode     */
+    GPIO_MODE_INPUT_OUTPUT_OD = ((GPIO_MODE_DEF_INPUT)|(GPIO_MODE_DEF_OUTPUT)|(GPIO_MODE_DEF_OD)), /*!< GPIO mode : output and input with open-drain mode*/
+    GPIO_MODE_INPUT_OUTPUT = ((GPIO_MODE_DEF_INPUT)|(GPIO_MODE_DEF_OUTPUT)),                       /*!< GPIO mode : output and input mode                */
+} gpio_mode_t;
+
+typedef enum {
+    GPIO_PULLUP_DISABLE = 0x0,     /*!< Disable GPIO pull-up resistor */
+    GPIO_PULLUP_ENABLE = 0x1,      /*!< Enable GPIO pull-up resistor */
+} gpio_pullup_t;
+
+typedef enum {
+    GPIO_PULLDOWN_DISABLE = 0x0,   /*!< Disable GPIO pull-down resistor */
+    GPIO_PULLDOWN_ENABLE = 0x1,    /*!< Enable GPIO pull-down resistor  */
+} gpio_pulldown_t;
+
+/**
+ * @brief Configuration parameters of GPIO pad for gpio_config function
+ */
+typedef struct {
+    uint64_t pin_bit_mask;          /*!< GPIO pin: set with bit mask, each bit maps to a GPIO */
+    gpio_mode_t mode;               /*!< GPIO mode: set input/output mode                     */
+    gpio_pullup_t pull_up_en;       /*!< GPIO pull-up                                         */
+    gpio_pulldown_t pull_down_en;   /*!< GPIO pull-down                                       */
+    gpio_int_type_t intr_type;      /*!< GPIO interrupt type                                  */
+} gpio_config_t;
+
+typedef enum {
+    GPIO_PULLUP_ONLY,               /*!< Pad pull up            */
+    GPIO_PULLDOWN_ONLY,             /*!< Pad pull down          */
+    GPIO_PULLUP_PULLDOWN,           /*!< Pad pull up + pull down*/
+    GPIO_FLOATING,                  /*!< Pad floating           */
+} gpio_pull_mode_t;
+
+typedef enum {
+    GPIO_DRIVE_CAP_0       = 0,    /*!< Pad drive capability: weak          */
+    GPIO_DRIVE_CAP_1       = 1,    /*!< Pad drive capability: stronger      */
+    GPIO_DRIVE_CAP_2       = 2,    /*!< Pad drive capability: default value */
+    GPIO_DRIVE_CAP_DEFAULT = 2,    /*!< Pad drive capability: default value */
+    GPIO_DRIVE_CAP_3       = 3,    /*!< Pad drive capability: strongest     */
+    GPIO_DRIVE_CAP_MAX,
+} gpio_drive_cap_t;
+
+typedef void (*gpio_isr_t)(void*);
+typedef intr_handle_t gpio_isr_handle_t;
+
+/**
+ * @brief GPIO common configuration
+ *
+ *        Configure GPIO's Mode,pull-up,PullDown,IntrType
+ *
+ * @param  pGPIOConfig Pointer to GPIO configure struct
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *
+ */
+esp_err_t gpio_config(const gpio_config_t *pGPIOConfig);
+
+
+/**
+ * @brief  GPIO set interrupt trigger type
+ *
+ * @param  gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ * @param  intr_type Interrupt type, select from gpio_int_type_t
+ *
+ * @return
+ *     - ESP_OK  Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *
+ */
+esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type);
+
+/**
+ * @brief  Enable GPIO module interrupt signal
+ *
+ * @param  gpio_num GPIO number. If you want to enable an interrupt on e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *
+ */
+esp_err_t gpio_intr_enable(gpio_num_t gpio_num);
+
+/**
+ * @brief  Disable GPIO module interrupt signal
+ *
+ * @param  gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *
+ */
+esp_err_t gpio_intr_disable(gpio_num_t gpio_num);
+
+/**
+ * @brief  GPIO set output level
+ *
+ * @param  gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ * @param  level Output level. 0: low ; 1: high
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO number error
+ *
+ */
+esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level);
+
+/**
+ * @brief  GPIO get input level
+ *
+ * @param  gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ *
+ * @return
+ *     - 0 the GPIO input level is 0
+ *     - 1 the GPIO input level is 1
+ *
+ */
+int gpio_get_level(gpio_num_t gpio_num);
+
+/**
+ * @brief	 GPIO set direction
+ *
+ * Configure GPIO direction,such as output_only,input_only,output_and_input
+ *
+ * @param  gpio_num  Configure GPIO pins number, it should be GPIO number. If you want to set direction of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ * @param  mode GPIO direction
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ *
+ */
+esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode);
+
+/**
+ * @brief  Configure GPIO pull-up/pull-down resistors
+ *
+ * Only pins that support both input & output have integrated pull-up and pull-down resistors. Input-only GPIOs 34-39 do not.
+ *
+ * @param  gpio_num GPIO number. If you want to set pull up or down mode for e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
+ * @param  pull GPIO pull up/down mode.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG : Parameter error
+ *
+ */
+esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull);
+
+/**
+  * @brief Enable GPIO wake-up function.
+  *
+  * @param gpio_num GPIO number.
+  *
+  * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type);
+
+/**
+  * @brief Disable GPIO wake-up function.
+  *
+  * @param gpio_num GPIO number
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num);
+
+/**
+ * @brief   Register GPIO interrupt handler, the handler is an ISR.
+ *          The handler will be attached to the same CPU core that this function is running on.
+ *
+ * This ISR function is called whenever any GPIO interrupt occurs. See
+ * the alternative gpio_install_isr_service() and
+ * gpio_isr_handler_add() API in order to have the driver support
+ * per-GPIO ISRs.
+ *
+ * @param  fn  Interrupt handler function.
+ * @param  intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+ *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
+ * @param  arg  Parameter for handler function
+ * @param  handle Pointer to return handle. If non-NULL, a handle for the interrupt will be returned here.
+ *
+ * \verbatim embed:rst:leading-asterisk
+ * To disable or remove the ISR, pass the returned handle to the :doc:`interrupt allocation functions </api-reference/system/intr_alloc>`.
+ * \endverbatim
+ *
+ * @return
+ *     - ESP_OK Success ;
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ */
+esp_err_t gpio_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, gpio_isr_handle_t *handle);
+
+/**
+  * @brief Enable pull-up on GPIO.
+  *
+  * @param gpio_num GPIO number
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t gpio_pullup_en(gpio_num_t gpio_num);
+
+/**
+  * @brief Disable pull-up on GPIO.
+  *
+  * @param gpio_num GPIO number
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t gpio_pullup_dis(gpio_num_t gpio_num);
+
+/**
+  * @brief Enable pull-down on GPIO.
+  *
+  * @param gpio_num GPIO number
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t gpio_pulldown_en(gpio_num_t gpio_num);
+
+/**
+  * @brief Disable pull-down on GPIO.
+  *
+  * @param gpio_num GPIO number
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num);
+
+/**
+  * @brief Install the driver's GPIO ISR handler service, which allows per-pin GPIO interrupt handlers.
+  *
+  * This function is incompatible with gpio_isr_register() - if that function is used, a single global ISR is registered for all GPIO interrupts. If this function is used, the ISR service provides a global GPIO ISR and individual pin handlers are registered via the gpio_isr_handler_add() function.
+  *
+  * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+  *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_FAIL Operation fail
+  *     - ESP_ERR_NO_MEM No memory to install this service
+  */
+esp_err_t gpio_install_isr_service(int intr_alloc_flags);
+
+/**
+  * @brief Uninstall the driver's GPIO ISR service, freeing related resources.
+  */
+void gpio_uninstall_isr_service();
+
+/**
+  * @brief Add ISR handler for the corresponding GPIO pin.
+  *
+  * Call this function after using gpio_install_isr_service() to
+  * install the driver's GPIO ISR handler service.
+  *
+  * The pin ISR handlers no longer need to be declared with IRAM_ATTR,
+  * unless you pass the ESP_INTR_FLAG_IRAM flag when allocating the
+  * ISR in gpio_install_isr_service().
+  *
+  * This ISR handler will be called from an ISR. So there is a stack
+  * size limit (configurable as "ISR stack size" in menuconfig). This
+  * limit is smaller compared to a global GPIO interrupt handler due
+  * to the additional level of indirection.
+  *
+  * @param gpio_num GPIO number
+  * @param isr_handler ISR handler function for the corresponding GPIO number.
+  * @param args parameter for ISR handler.
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_STATE Wrong state, the ISR service has not been initialized.
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t gpio_isr_handler_add(gpio_num_t gpio_num, gpio_isr_t isr_handler, void* args);
+
+/**
+  * @brief Remove ISR handler for the corresponding GPIO pin.
+  *
+  * @param gpio_num GPIO number
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_STATE Wrong state, the ISR service has not been initialized.
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t gpio_isr_handler_remove(gpio_num_t gpio_num);
+
+/**
+  * @brief Set GPIO pad drive capability
+  *
+  * @param gpio_num GPIO number, only support output GPIOs
+  * @param strength Drive capability of the pad
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength);
+
+/**
+  * @brief Get GPIO pad drive capability
+  *
+  * @param gpio_num GPIO number, only support output GPIOs
+  * @param strength Pointer to accept drive capability of the pad
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRIVER_GPIO_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/i2c.h

@@ -0,0 +1,514 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_I2C_H_
+#define _DRIVER_I2C_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include <esp_types.h>
+#include "esp_err.h"
+#include "esp_intr_alloc.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+#include "freertos/xtensa_api.h"
+#include "freertos/task.h"
+#include "freertos/queue.h"
+#include "ringbuf.h"
+#include "driver/gpio.h"
+
+#define I2C_APB_CLK_FREQ  APB_CLK_FREQ /*!< I2C source clock is APB clock, 80MHz */
+#define I2C_FIFO_LEN   (32)  /*!< I2C hardware fifo length */
+typedef enum{
+    I2C_MODE_SLAVE = 0,   /*!< I2C slave mode */
+    I2C_MODE_MASTER,      /*!< I2C master mode */
+    I2C_MODE_MAX,
+}i2c_mode_t;
+
+typedef enum {
+    I2C_MASTER_WRITE = 0,   /*!< I2C write data */
+    I2C_MASTER_READ,        /*!< I2C read data */
+} i2c_rw_t;
+
+typedef enum {
+    I2C_DATA_MODE_MSB_FIRST = 0,  /*!< I2C data msb first */
+    I2C_DATA_MODE_LSB_FIRST = 1,  /*!< I2C data lsb first */
+    I2C_DATA_MODE_MAX
+} i2c_trans_mode_t;
+
+typedef enum{
+    I2C_CMD_RESTART = 0,   /*!<I2C restart command */
+    I2C_CMD_WRITE,         /*!<I2C write command */
+    I2C_CMD_READ,          /*!<I2C read command */
+    I2C_CMD_STOP,          /*!<I2C stop command */
+    I2C_CMD_END            /*!<I2C end command */
+}i2c_opmode_t;
+
+typedef enum{
+    I2C_NUM_0 = 0,  /*!< I2C port 0 */
+    I2C_NUM_1 ,     /*!< I2C port 1 */
+    I2C_NUM_MAX
+} i2c_port_t;
+
+typedef enum {
+    I2C_ADDR_BIT_7 = 0,    /*!< I2C 7bit address for slave mode */
+    I2C_ADDR_BIT_10,       /*!< I2C 10bit address for slave mode */
+    I2C_ADDR_BIT_MAX,
+} i2c_addr_mode_t;
+
+/**
+ * @brief I2C initialization parameters
+ */
+typedef struct{
+    i2c_mode_t mode;       /*!< I2C mode */
+    gpio_num_t sda_io_num;        /*!< GPIO number for I2C sda signal */
+    gpio_pullup_t sda_pullup_en;  /*!< Internal GPIO pull mode for I2C sda signal*/
+    gpio_num_t scl_io_num;        /*!< GPIO number for I2C scl signal */
+    gpio_pullup_t scl_pullup_en;  /*!< Internal GPIO pull mode for I2C scl signal*/
+
+    union {
+        struct {
+            uint32_t clk_speed;     /*!< I2C clock frequency for master mode, (no higher than 1MHz for now) */
+        } master;
+        struct {
+            uint8_t addr_10bit_en;  /*!< I2C 10bit address mode enable for slave mode */
+            uint16_t slave_addr;    /*!< I2C address for slave mode */
+        } slave;
+
+    };
+}i2c_config_t;
+
+typedef void* i2c_cmd_handle_t;    /*!< I2C command handle  */
+
+/**
+ * @brief I2C driver install
+ *
+ * @param i2c_num I2C port number
+ * @param mode I2C mode( master or slave )
+ * @param slv_rx_buf_len receiving buffer size for slave mode
+ *        @note
+ *        Only slave mode will use this value, driver will ignore this value in master mode.
+ * @param slv_tx_buf_len sending buffer size for slave mode
+ *        @note
+ *        Only slave mode will use this value, driver will ignore this value in master mode.
+ * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+ *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_FAIL Driver install error
+ */
+esp_err_t i2c_driver_install(i2c_port_t i2c_num, i2c_mode_t mode, size_t slv_rx_buf_len, size_t slv_tx_buf_len, int intr_alloc_flags);
+
+/**
+ * @brief I2C driver delete
+ *
+ * @param i2c_num I2C port number
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_driver_delete(i2c_port_t i2c_num);
+
+/**
+ * @brief I2C parameter initialization
+ *
+ * @param i2c_num I2C port number
+ * @param i2c_conf pointer to I2C parameter settings
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_param_config(i2c_port_t i2c_num, const i2c_config_t* i2c_conf);
+
+/**
+ * @brief reset I2C tx hardware fifo
+ *
+ * @param i2c_num I2C port number
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_reset_tx_fifo(i2c_port_t i2c_num);
+
+/**
+ * @brief reset I2C rx fifo
+ *
+ * @param i2c_num I2C port number
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_reset_rx_fifo(i2c_port_t i2c_num);
+
+/**
+ * @brief I2C isr handler register
+ *
+ * @param i2c_num I2C port number
+ * @param fn isr handler function
+ * @param arg parameter for isr handler function
+ * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+ *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
+ * @param handle handle return from esp_intr_alloc.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_isr_register(i2c_port_t i2c_num, void (*fn)(void*), void * arg, int intr_alloc_flags, intr_handle_t *handle);
+
+/**
+ * @brief to delete and free I2C isr.
+ *
+ * @param handle handle of isr.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_isr_free(intr_handle_t handle);
+
+/**
+ * @brief Configure GPIO signal for I2C sck and sda
+ *
+ * @param i2c_num I2C port number
+ * @param sda_io_num GPIO number for I2C sda signal
+ * @param scl_io_num GPIO number for I2C scl signal
+ * @param sda_pullup_en Whether to enable the internal pullup for sda pin
+ * @param scl_pullup_en Whether to enable the internal pullup for scl pin
+ * @param mode I2C mode
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_set_pin(i2c_port_t i2c_num, gpio_num_t sda_io_num, gpio_num_t scl_io_num,
+                      gpio_pullup_t sda_pullup_en, gpio_pullup_t scl_pullup_en, i2c_mode_t mode);
+
+/**
+ * @brief Create and init I2C command link
+ *        @note
+ *        Before we build I2C command link, we need to call i2c_cmd_link_create() to create
+ *        a command link.
+ *        After we finish sending the commands, we need to call i2c_cmd_link_delete() to
+ *        release and return the resources.
+ *
+ * @return i2c command link handler
+ */
+i2c_cmd_handle_t i2c_cmd_link_create();
+
+/**
+ * @brief Free I2C command link
+ *        @note
+ *        Before we build I2C command link, we need to call i2c_cmd_link_create() to create
+ *        a command link.
+ *        After we finish sending the commands, we need to call i2c_cmd_link_delete() to
+ *        release and return the resources.
+ *
+ * @param cmd_handle I2C command handle
+ */
+void i2c_cmd_link_delete(i2c_cmd_handle_t cmd_handle);
+
+/**
+ * @brief Queue command for I2C master to generate a start signal
+ *        @note
+ *        Only call this function in I2C master mode
+ *        Call i2c_master_cmd_begin() to send all queued commands
+ *
+ * @param cmd_handle I2C cmd link
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_master_start(i2c_cmd_handle_t cmd_handle);
+
+/**
+ * @brief Queue command for I2C master to write one byte to I2C bus
+ *        @note
+ *        Only call this function in I2C master mode
+ *        Call i2c_master_cmd_begin() to send all queued commands
+ *
+ * @param cmd_handle I2C cmd link
+ * @param data I2C one byte command to write to bus
+ * @param ack_en enable ack check for master
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_master_write_byte(i2c_cmd_handle_t cmd_handle, uint8_t data, bool ack_en);
+
+/**
+ * @brief Queue command for I2C master to write buffer to I2C bus
+ *        @note
+ *        Only call this function in I2C master mode
+ *        Call i2c_master_cmd_begin() to send all queued commands
+ *
+ * @param cmd_handle I2C cmd link
+ * @param data data to send
+ * @param data_len data length
+ * @param ack_en enable ack check for master
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_master_write(i2c_cmd_handle_t cmd_handle, uint8_t* data, size_t data_len, bool ack_en);
+
+/**
+ * @brief Queue command for I2C master to read one byte from I2C bus
+ *        @note
+ *        Only call this function in I2C master mode
+ *        Call i2c_master_cmd_begin() to send all queued commands
+ *
+ * @param cmd_handle I2C cmd link
+ * @param data pointer accept the data byte
+ * @param ack ack value for read command
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_master_read_byte(i2c_cmd_handle_t cmd_handle, uint8_t* data, int ack);
+
+/**
+ * @brief Queue command for I2C master to read data from I2C bus
+ *        @note
+ *        Only call this function in I2C master mode
+ *        Call i2c_master_cmd_begin() to send all queued commands
+ *
+ * @param cmd_handle I2C cmd link
+ * @param data data buffer to accept the data from bus
+ * @param data_len read data length
+ * @param ack ack value for read command
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_master_read(i2c_cmd_handle_t cmd_handle, uint8_t* data, size_t data_len, int ack);
+
+/**
+ * @brief Queue command for I2C master to generate a stop signal
+ *        @note
+ *        Only call this function in I2C master mode
+ *        Call i2c_master_cmd_begin() to send all queued commands
+ *
+ * @param cmd_handle I2C cmd link
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_master_stop(i2c_cmd_handle_t cmd_handle);
+
+/**
+ * @brief I2C master send queued commands.
+ *        This function will trigger sending all queued commands.
+ *        The task will be blocked until all the commands have been sent out.
+ *        The I2C APIs are not thread-safe, if you want to use one I2C port in different tasks,
+ *        you need to take care of the multi-thread issue.
+ *        @note
+ *        Only call this function in I2C master mode
+ *
+ * @param i2c_num I2C port number
+ * @param cmd_handle I2C command handler
+ * @param ticks_to_wait maximum wait ticks.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_FAIL Sending command error, slave doesn't ACK the transfer.
+ *     - ESP_ERR_INVALID_STATE I2C driver not installed or not in master mode.
+ *     - ESP_ERR_TIMEOUT Operation timeout because the bus is busy.
+ */
+esp_err_t i2c_master_cmd_begin(i2c_port_t i2c_num, i2c_cmd_handle_t cmd_handle, portBASE_TYPE ticks_to_wait);
+
+/**
+ * @brief I2C slave write data to internal ringbuffer, when tx fifo empty, isr will fill the hardware
+ *        fifo from the internal ringbuffer
+ *        @note
+ *        Only call this function in I2C slave mode
+ *
+ * @param i2c_num I2C port number
+ * @param data data pointer to write into internal buffer
+ * @param size data size
+ * @param ticks_to_wait Maximum waiting ticks
+ *
+ * @return
+ *     - ESP_FAIL(-1) Parameter error
+ *     - Others(>=0) The number of data bytes that pushed to the I2C slave buffer.
+ */
+int i2c_slave_write_buffer(i2c_port_t i2c_num, uint8_t* data, int size, portBASE_TYPE ticks_to_wait);
+
+/**
+ * @brief I2C slave read data from internal buffer. When I2C slave receive data, isr will copy received data
+ *        from hardware rx fifo to internal ringbuffer. Then users can read from internal ringbuffer.
+ *        @note
+ *        Only call this function in I2C slave mode
+ *
+ * @param i2c_num I2C port number
+ * @param data data pointer to write into internal buffer
+ * @param max_size Maximum data size to read
+ * @param ticks_to_wait Maximum waiting ticks
+ *
+ * @return
+ *     - ESP_FAIL(-1) Parameter error
+ *     - Others(>=0) The number of data bytes that read from I2C slave buffer.
+ */
+int i2c_slave_read_buffer(i2c_port_t i2c_num, uint8_t* data, size_t max_size, portBASE_TYPE ticks_to_wait);
+
+/**
+ * @brief set I2C master clock period
+ *
+ * @param i2c_num I2C port number
+ * @param high_period clock cycle number during SCL is high level, high_period is a 14 bit value
+ * @param low_period clock cycle number during SCL is low level, low_period is a 14 bit value
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_set_period(i2c_port_t i2c_num, int high_period, int low_period);
+
+/**
+ * @brief get I2C master clock period
+ *
+ * @param i2c_num I2C port number
+ * @param high_period pointer to get clock cycle number during SCL is high level, will get a 14 bit value
+ * @param low_period pointer to get clock cycle number during SCL is low level, will get a 14 bit value
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_get_period(i2c_port_t i2c_num, int* high_period, int* low_period);
+
+/**
+ * @brief set I2C master start signal timing
+ *
+ * @param i2c_num I2C port number
+ * @param setup_time clock number between the falling-edge of SDA and rising-edge of SCL for start mark, it's a 10-bit value.
+ * @param hold_time clock num between the falling-edge of SDA and falling-edge of SCL for start mark, it's a 10-bit value.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_set_start_timing(i2c_port_t i2c_num, int setup_time, int hold_time);
+
+/**
+ * @brief get I2C master start signal timing
+ *
+ * @param i2c_num I2C port number
+ * @param setup_time pointer to get setup time
+ * @param hold_time pointer to get hold time
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_get_start_timing(i2c_port_t i2c_num, int* setup_time, int* hold_time);
+
+/**
+ * @brief set I2C master stop signal timing
+ *
+ * @param i2c_num I2C port number
+ * @param setup_time clock num between the rising-edge of SCL and the rising-edge of SDA, it's a 10-bit value.
+ * @param hold_time clock number after the STOP bit's rising-edge, it's a 14-bit value.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_set_stop_timing(i2c_port_t i2c_num, int setup_time, int hold_time);
+
+/**
+ * @brief get I2C master stop signal timing
+ *
+ * @param i2c_num I2C port number
+ * @param setup_time pointer to get setup time.
+ * @param hold_time pointer to get hold time.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_get_stop_timing(i2c_port_t i2c_num, int* setup_time, int* hold_time);
+
+/**
+ * @brief set I2C data signal timing
+ *
+ * @param i2c_num I2C port number
+ * @param sample_time clock number I2C used to sample data on SDA after the rising-edge of SCL, it's a 10-bit value
+ * @param hold_time clock number I2C used to hold the data after the falling-edge of SCL, it's a 10-bit value
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_set_data_timing(i2c_port_t i2c_num, int sample_time, int hold_time);
+
+/**
+ * @brief get I2C data signal timing
+ *
+ * @param i2c_num I2C port number
+ * @param sample_time pointer to get sample time
+ * @param hold_time pointer to get hold time
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_get_data_timing(i2c_port_t i2c_num, int* sample_time, int* hold_time);
+
+/**
+ * @brief set I2C data transfer mode
+ *
+ * @param i2c_num I2C port number
+ * @param tx_trans_mode I2C sending data mode
+ * @param rx_trans_mode I2C receving data mode
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_set_data_mode(i2c_port_t i2c_num, i2c_trans_mode_t tx_trans_mode, i2c_trans_mode_t rx_trans_mode);
+
+/**
+ * @brief get I2C data transfer mode
+ *
+ * @param i2c_num I2C port number
+ * @param tx_trans_mode pointer to get I2C sending data mode
+ * @param rx_trans_mode pointer to get I2C receiving data mode
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t i2c_get_data_mode(i2c_port_t i2c_num, i2c_trans_mode_t *tx_trans_mode, i2c_trans_mode_t *rx_trans_mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_DRIVER_I2C_H_*/

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/i2s.h

@@ -0,0 +1,409 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_I2S_H_
+#define _DRIVER_I2S_H_
+#include "esp_err.h"
+#include <esp_types.h>
+#include "soc/gpio_reg.h"
+#include "soc/soc.h"
+#include "soc/i2s_struct.h"
+#include "soc/i2s_reg.h"
+#include "soc/rtc_io_reg.h"
+#include "soc/io_mux_reg.h"
+#include "rom/gpio.h"
+#include "esp_attr.h"
+#include "esp_intr_alloc.h"
+#include "driver/periph_ctrl.h"
+#include "freertos/semphr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief I2S bit width per sample.
+ *
+ */
+typedef enum {
+    I2S_BITS_PER_SAMPLE_8BIT    = 8,        /*!< I2S bits per sample: 8-bits*/
+    I2S_BITS_PER_SAMPLE_16BIT   = 16,       /*!< I2S bits per sample: 16-bits*/
+    I2S_BITS_PER_SAMPLE_24BIT   = 24,       /*!< I2S bits per sample: 24-bits*/
+    I2S_BITS_PER_SAMPLE_32BIT   = 32,       /*!< I2S bits per sample: 32-bits*/
+} i2s_bits_per_sample_t;
+
+/**
+ * @brief I2S channel.
+ *
+ */
+typedef enum {
+    I2S_CHANNEL_MONO        = 1,            /*!< I2S 1 channel (mono)*/
+    I2S_CHANNEL_STEREO      = 2             /*!< I2S 2 channel (stereo)*/
+} i2s_channel_t;
+
+/**
+ * @brief I2S communication standard format
+ *
+ */
+typedef enum {
+    I2S_COMM_FORMAT_I2S         = 0x01, /*!< I2S communication format I2S*/
+    I2S_COMM_FORMAT_I2S_MSB     = 0x02, /*!< I2S format MSB*/
+    I2S_COMM_FORMAT_I2S_LSB     = 0x04, /*!< I2S format LSB*/
+    I2S_COMM_FORMAT_PCM         = 0x08, /*!< I2S communication format PCM*/
+    I2S_COMM_FORMAT_PCM_SHORT   = 0x10, /*!< PCM Short*/
+    I2S_COMM_FORMAT_PCM_LONG    = 0x20, /*!< PCM Long*/
+} i2s_comm_format_t;
+
+
+/**
+ * @brief I2S channel format type
+ */
+typedef enum {
+    I2S_CHANNEL_FMT_RIGHT_LEFT = 0x00,
+    I2S_CHANNEL_FMT_ALL_RIGHT,
+    I2S_CHANNEL_FMT_ALL_LEFT,
+    I2S_CHANNEL_FMT_ONLY_RIGHT,
+    I2S_CHANNEL_FMT_ONLY_LEFT,
+} i2s_channel_fmt_t;
+
+/**
+ * @brief PDM sample rate ratio, measured in Hz.
+ *
+ */
+typedef enum {
+    PDM_SAMPLE_RATE_RATIO_64,
+    PDM_SAMPLE_RATE_RATIO_128,
+} pdm_sample_rate_ratio_t;
+
+/**
+ * @brief PDM PCM convter enable/disable.
+ *
+ */
+typedef enum {
+    PDM_PCM_CONV_ENABLE,
+    PDM_PCM_CONV_DISABLE,
+} pdm_pcm_conv_t;
+
+
+/**
+ * @brief I2S Peripheral, 0 & 1.
+ *
+ */
+typedef enum {
+    I2S_NUM_0 = 0x0,  /*!< I2S 0*/
+    I2S_NUM_1 = 0x1,  /*!< I2S 1*/
+    I2S_NUM_MAX,
+} i2s_port_t;
+
+/**
+ * @brief I2S Mode, defaut is I2S_MODE_MASTER | I2S_MODE_TX
+ *
+ * @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip.
+ *
+ */
+typedef enum {
+    I2S_MODE_MASTER = 1,
+    I2S_MODE_SLAVE = 2,
+    I2S_MODE_TX = 4,
+    I2S_MODE_RX = 8,
+    I2S_MODE_DAC_BUILT_IN = 16,       /*!< Output I2S data to built-in DAC, no matter the data format is 16bit or 32 bit, the DAC module will only take the 8bits from MSB*/
+    //I2S_MODE_ADC_BUILT_IN = 32,     /*!< Currently not supported yet, will be added for the next version*/
+    I2S_MODE_PDM = 64,
+} i2s_mode_t;
+
+/**
+ * @brief I2S configuration parameters for i2s_param_config function
+ *
+ */
+typedef struct {
+    i2s_mode_t              mode;                   /*!< I2S work mode*/
+    int                     sample_rate;            /*!< I2S sample rate*/
+    i2s_bits_per_sample_t   bits_per_sample;        /*!< I2S bits per sample*/
+    i2s_channel_fmt_t       channel_format;         /*!< I2S channel format */
+    i2s_comm_format_t       communication_format;   /*!< I2S communication format */
+    int                     intr_alloc_flags;       /*!< Flags used to allocate the interrupt. One or multiple (ORred) ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info */
+    int                     dma_buf_count;          /*!< I2S DMA Buffer Count */
+    int                     dma_buf_len;            /*!< I2S DMA Buffer Length */
+} i2s_config_t;
+
+/**
+ * @brief I2S event types
+ *
+ */
+typedef enum {
+    I2S_EVENT_DMA_ERROR,
+    I2S_EVENT_TX_DONE,     /*!< I2S DMA finish sent 1 buffer*/
+    I2S_EVENT_RX_DONE,     /*!< I2S DMA finish received 1 buffer*/
+    I2S_EVENT_MAX,         /*!< I2S event max index*/
+} i2s_event_type_t;
+
+/**
+ * @brief I2S DAC mode for i2s_set_dac_mode.
+ *
+ * @note PDM and built-in DAC functions are only supported on I2S0 for current ESP32 chip.
+ */
+typedef enum {
+    I2S_DAC_CHANNEL_DISABLE  = 0,    /*!< Disable I2S built-in DAC signals*/
+    I2S_DAC_CHANNEL_RIGHT_EN = 1,    /*!< Enable I2S built-in DAC right channel, maps to DAC channel 1 on GPIO25*/
+    I2S_DAC_CHANNEL_LEFT_EN  = 2,    /*!< Enable I2S built-in DAC left  channel, maps to DAC channel 2 on GPIO26*/
+    I2S_DAC_CHANNEL_BOTH_EN  = 0x3,  /*!< Enable both of the I2S built-in DAC channels.*/
+    I2S_DAC_CHANNEL_MAX      = 0x4,  /*!< I2S built-in DAC mode max index*/
+} i2s_dac_mode_t;
+
+/**
+ * @brief Event structure used in I2S event queue
+ *
+ */
+typedef struct {
+    i2s_event_type_t    type;   /*!< I2S event type */
+    size_t              size;   /*!< I2S data size for I2S_DATA event*/
+} i2s_event_t;
+
+#define I2S_PIN_NO_CHANGE (-1) /*!< Use in i2s_pin_config_t for pins which should not be changed */
+
+/**
+ * @brief I2S pin number for i2s_set_pin
+ *
+ */
+typedef struct {
+    int bck_io_num;     /*!< BCK in out pin*/
+    int ws_io_num;      /*!< WS in out pin*/
+    int data_out_num;   /*!< DATA out pin*/
+    int data_in_num;    /*!< DATA in pin*/
+} i2s_pin_config_t;
+
+
+typedef intr_handle_t i2s_isr_handle_t;
+/**
+ * @brief Set I2S pin number
+ *
+ * @note
+ * The I2S peripheral output signals can be connected to multiple GPIO pads.
+ * However, the I2S peripheral input signal can only be connected to one GPIO pad.
+ *
+ * @param   i2s_num     I2S_NUM_0 or I2S_NUM_1
+ *
+ * @param   pin         I2S Pin structure, or NULL to set 2-channel 8-bit internal DAC pin configuration (GPIO25 & GPIO26)
+ *
+ * Inside the pin configuration structure, set I2S_PIN_NO_CHANGE for any pin where
+ * the current configuration should not be changed.
+ *
+ * @note if *pin is set as NULL, this function will initialize both of the built-in DAC channels by default.
+ *       if you don't want this to happen and you want to initialize only one of the DAC channels, you can call i2s_set_dac_mode instead.
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t i2s_set_pin(i2s_port_t i2s_num, const i2s_pin_config_t *pin);
+
+/**
+ * @brief Set I2S dac mode, I2S built-in DAC is disabled by default
+ *
+ * @param dac_mode DAC mode configurations - see i2s_dac_mode_t
+ *
+ * @note Built-in DAC functions are only supported on I2S0 for current ESP32 chip.
+ *       If either of the built-in DAC channel are enabled, the other one can not
+ *       be used as RTC DAC function at the same time.
+ *
+ * @return
+ *     - ESP_OK  Success
+ *     - ESP_ERR_INVALID_ARG  Parameter error
+ */
+esp_err_t i2s_set_dac_mode(i2s_dac_mode_t dac_mode);
+
+/**
+ * @brief Install and start I2S driver.
+ *
+ * @param i2s_num         I2S_NUM_0, I2S_NUM_1
+ *
+ * @param i2s_config      I2S configurations - see i2s_config_t struct
+ *
+ * @param queue_size      I2S event queue size/depth.
+ *
+ * @param i2s_queue       I2S event queue handle, if set NULL, driver will not use an event queue.
+ *
+ * This function must be called before any I2S driver read/write operations.
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config, int queue_size, void* i2s_queue);
+
+/**
+ * @brief Uninstall I2S driver.
+ *
+ * @param i2s_num  I2S_NUM_0, I2S_NUM_1
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t i2s_driver_uninstall(i2s_port_t i2s_num);
+
+/**
+ * @brief Write data to I2S DMA transmit buffer.
+ *
+ * @param i2s_num  I2S_NUM_0, I2S_NUM_1
+ *
+ * @param src      Source address to write from
+ *
+ * @param size     Size of data in bytes
+ *
+ * @param ticks_to_wait TX buffer wait timeout in RTOS ticks. If this
+ * many ticks pass without space becoming available in the DMA
+ * transmit buffer, then the function will return (note that if the
+ * data is written to the DMA buffer in pieces, the overall operation
+ * may still take longer than this timeout.) Pass portMAX_DELAY for no
+ * timeout.
+ *
+ * Format of the data in source buffer is determined by the I2S
+ * configuration (see i2s_config_t).
+ *
+ * @return  Number of bytes written, or ESP_FAIL (-1) for parameter error. If a timeout occurred, bytes written will be less than total size.
+ */
+int i2s_write_bytes(i2s_port_t i2s_num, const char *src, size_t size, TickType_t ticks_to_wait);
+
+/**
+ * @brief Read data from I2S DMA receive buffer
+ *
+ * @param i2s_num  I2S_NUM_0, I2S_NUM_1
+ *
+ * @param dest     Destination address to read into
+ *
+ * @param size     Size of data in bytes
+ *
+ * @param ticks_to_wait RX buffer wait timeout in RTOS ticks. If this many ticks pass without bytes becoming available in the DMA receive buffer, then the function will return (note that if data is read from the DMA buffer in pieces, the overall operation may still take longer than this timeout.) Pass portMAX_DELAY for no timeout.
+ *
+ * Format of the data in source buffer is determined by the I2S
+ * configuration (see i2s_config_t).
+ *
+ * @return  Number of bytes read, or ESP_FAIL (-1) for parameter error. If a timeout occurred, bytes read will be less than total size.
+ */
+int i2s_read_bytes(i2s_port_t i2s_num, char* dest, size_t size, TickType_t ticks_to_wait);
+
+/**
+ * @brief Push (write) a single sample to the I2S DMA TX buffer.
+ *
+ * Size of the sample is determined by the channel_format (mono or stereo)) & bits_per_sample configuration (see i2s_config_t).
+ *
+ * @param i2s_num  I2S_NUM_0, I2S_NUM_1
+ *
+ * @param sample Pointer to buffer containing sample to write. Size of buffer (in bytes) = (number of channels) * bits_per_sample / 8.
+ *
+ * @param ticks_to_wait Push timeout in RTOS ticks. If space is not available in the DMA TX buffer within this period, no data is written and function returns 0.
+ *
+ * @return Number of bytes successfully pushed to DMA buffer, or ESP_FAIL (-1) for parameter error. Will be either zero or the size of configured sample buffer.
+ */
+int i2s_push_sample(i2s_port_t i2s_num, const char *sample, TickType_t ticks_to_wait);
+
+/**
+ * @brief Pop (read) a single sample from the I2S DMA RX buffer.
+ *
+ * Size of the sample is determined by the channel_format (mono or stereo)) & bits_per_sample configuration (see i2s_config_t).
+ *
+ * @param i2s_num  I2S_NUM_0, I2S_NUM_1
+ *
+ * @param sample Buffer sample data will be read into. Size of buffer (in bytes) = (number of channels) * bits_per_sample / 8.
+ *
+ * @param ticks_to_wait Pop timeout in RTOS ticks. If a sample is not available in the DMA buffer within this period, no data is read and function returns zero.
+ *
+ * @return Number of bytes successfully read from DMA buffer, or ESP_FAIL (-1) for parameter error. Byte count will be either zero or the size of the configured sample buffer.
+
+ */
+int i2s_pop_sample(i2s_port_t i2s_num, char *sample, TickType_t ticks_to_wait);
+
+
+/**
+ * @brief Set sample rate used for I2S RX and TX.
+ *
+ * The bit clock rate is determined by the sample rate and i2s_config_t configuration parameters (number of channels, bits_per_sample).
+ *
+ * `bit_clock = rate * (number of channels) * bits_per_sample`
+ *
+ * @param i2s_num  I2S_NUM_0, I2S_NUM_1
+ *
+ * @param rate I2S sample rate (ex: 8000, 44100...)
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t i2s_set_sample_rates(i2s_port_t i2s_num, uint32_t rate);
+
+/**
+ * @brief Stop I2S driver
+ *
+ * Disables I2S TX/RX, until i2s_start() is called.
+ *
+ * @param i2s_num  I2S_NUM_0, I2S_NUM_1
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t i2s_stop(i2s_port_t i2s_num);
+
+/**
+ * @brief Start I2S driver
+ *
+ * It is not necessary to call this function after i2s_driver_install() (it is started automatically), however it is necessary to call it after i2s_stop().
+ *
+ *
+ * @param i2s_num  I2S_NUM_0, I2S_NUM_1
+ *
+* @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t i2s_start(i2s_port_t i2s_num);
+
+/**
+ * @brief Zero the contents of the TX DMA buffer.
+ *
+ * Pushes zero-byte samples into the TX DMA buffer, until it is full.
+ *
+ * @param i2s_num  I2S_NUM_0, I2S_NUM_1
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t i2s_zero_dma_buffer(i2s_port_t i2s_num);
+
+/**
+ * @brief Set clock & bit width used for I2S RX and TX.
+ * 
+ * Similar to i2s_set_sample_rates(), but also sets bit width.
+ *
+ * @param i2s_num  I2S_NUM_0, I2S_NUM_1
+ *
+ * @param rate I2S sample rate (ex: 8000, 44100...)
+ *
+ * @param bits I2S bit width (I2S_BITS_PER_SAMPLE_16BIT, I2S_BITS_PER_SAMPLE_24BIT, I2S_BITS_PER_SAMPLE_32BIT)
+ *
+ * @param ch I2S channel, (I2S_CHANNEL_MONO, I2S_CHANNEL_STEREO)
+ * 
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t i2s_set_clk(i2s_port_t i2s_num, uint32_t rate, i2s_bits_per_sample_t bits, i2s_channel_t ch);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRIVER_I2S_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/ledc.h

@@ -0,0 +1,387 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_LEDC_H_
+#define _DRIVER_LEDC_H_
+#include "esp_err.h"
+#include "soc/soc.h"
+#include "driver/gpio.h"
+#include "driver/periph_ctrl.h"
+#include "esp_intr_alloc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LEDC_APB_CLK_HZ (APB_CLK_FREQ)
+#define LEDC_REF_CLK_HZ (1*1000000)
+
+typedef enum {
+    LEDC_HIGH_SPEED_MODE = 0, /*!< LEDC high speed speed_mode */
+    LEDC_LOW_SPEED_MODE,    /*!< LEDC low speed speed_mode */
+    LEDC_SPEED_MODE_MAX,      /*!< LEDC speed limit */
+} ledc_mode_t;
+
+typedef enum {
+    LEDC_INTR_DISABLE = 0,    /*!< Disable LEDC interrupt */
+    LEDC_INTR_FADE_END,       /*!< Enable LEDC interrupt */
+} ledc_intr_type_t;
+
+typedef enum {
+    LEDC_DUTY_DIR_DECREASE = 0,    /*!< LEDC duty decrease direction */
+    LEDC_DUTY_DIR_INCREASE = 1,    /*!< LEDC duty increase direction */
+} ledc_duty_direction_t;
+
+typedef enum  {
+    LEDC_REF_TICK = 0, /*!< LEDC timer clock divided from reference tick(1Mhz) */
+    LEDC_APB_CLK,      /*!< LEDC timer clock divided from APB clock(80Mhz)*/
+} ledc_clk_src_t;
+
+typedef enum {
+    LEDC_TIMER_0 = 0, /*!< LEDC source timer TIMER0 */
+    LEDC_TIMER_1,     /*!< LEDC source timer TIMER1 */
+    LEDC_TIMER_2,     /*!< LEDC source timer TIMER2 */
+    LEDC_TIMER_3,     /*!< LEDC source timer TIMER3 */
+} ledc_timer_t;
+
+typedef enum {
+    LEDC_CHANNEL_0 = 0, /*!< LEDC channel 0 */
+    LEDC_CHANNEL_1,     /*!< LEDC channel 1 */
+    LEDC_CHANNEL_2,     /*!< LEDC channel 2 */
+    LEDC_CHANNEL_3,     /*!< LEDC channel 3 */
+    LEDC_CHANNEL_4,     /*!< LEDC channel 4 */
+    LEDC_CHANNEL_5,     /*!< LEDC channel 5 */
+    LEDC_CHANNEL_6,     /*!< LEDC channel 6 */
+    LEDC_CHANNEL_7,     /*!< LEDC channel 7 */
+    LEDC_CHANNEL_MAX,
+} ledc_channel_t;
+
+typedef enum {
+    LEDC_TIMER_10_BIT = 10, /*!< LEDC PWM depth 10Bit */
+    LEDC_TIMER_11_BIT = 11, /*!< LEDC PWM depth 11Bit */
+    LEDC_TIMER_12_BIT = 12, /*!< LEDC PWM depth 12Bit */
+    LEDC_TIMER_13_BIT = 13, /*!< LEDC PWM depth 13Bit */
+    LEDC_TIMER_14_BIT = 14, /*!< LEDC PWM depth 14Bit */
+    LEDC_TIMER_15_BIT = 15, /*!< LEDC PWM depth 15Bit */
+} ledc_timer_bit_t;
+
+typedef enum {
+    LEDC_FADE_NO_WAIT = 0,  /*!< LEDC fade function will return immediately */
+    LEDC_FADE_WAIT_DONE,    /*!< LEDC fade function will block until fading to the target duty*/
+    LEDC_FADE_MAX,
+} ledc_fade_mode_t;
+/**
+ * @brief Configuration parameters of LEDC channel for ledc_channel_config function
+ */
+typedef struct {
+    int gpio_num;                   /*!< the LEDC output gpio_num, if you want to use gpio16, gpio_num = 16*/
+    ledc_mode_t speed_mode;         /*!< LEDC speed speed_mode, high-speed mode or low-speed mode*/
+    ledc_channel_t channel;         /*!< LEDC channel(0 - 7)*/
+    ledc_intr_type_t intr_type;     /*!< configure interrupt, Fade interrupt enable  or Fade interrupt disable*/
+    ledc_timer_t timer_sel;         /*!< Select the timer source of channel (0 - 3)*/
+    uint32_t duty;                  /*!< LEDC channel duty, the duty range is [0, (2**bit_num) - 1], */
+} ledc_channel_config_t;
+
+/**
+ * @brief Configuration parameters of LEDC Timer timer for ledc_timer_config function
+ */
+typedef struct {
+    ledc_mode_t speed_mode;         /*!< LEDC speed speed_mode, high-speed mode or low-speed mode*/
+    ledc_timer_bit_t bit_num;       /*!< LEDC channel duty depth*/
+    ledc_timer_t  timer_num;        /*!< The timer source of channel (0 - 3)*/
+    uint32_t freq_hz;               /*!< LEDC timer frequency(Hz)*/
+} ledc_timer_config_t;
+
+typedef intr_handle_t ledc_isr_handle_t;
+
+/**
+ * @brief LEDC channel configuration
+ *        Configure LEDC channel with the given channel/output gpio_num/interrupt/source timer/frequency(Hz)/LEDC depth
+ *
+ * @param ledc_conf Pointer of LEDC channel configure struct
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t ledc_channel_config(const ledc_channel_config_t* ledc_conf);
+
+/**
+ * @brief LEDC timer configuration
+ *        Configure LEDC timer with the given source timer/frequency(Hz)/bit_num
+ *
+ * @param  timer_conf Pointer of LEDC timer configure struct
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_FAIL Can not find a proper pre-divider number base on the given frequency and the current bit_num.
+ */
+esp_err_t ledc_timer_config(const ledc_timer_config_t* timer_conf);
+
+/**
+ * @brief LEDC update channel parameters
+ *        Call this function to activate the LEDC updated parameters.
+ *        After ledc_set_duty, ledc_set_fade, we need to call this function to update the settings.
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,
+ * @param channel LEDC channel(0-7), select from ledc_channel_t
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *
+ */
+esp_err_t ledc_update_duty(ledc_mode_t speed_mode, ledc_channel_t channel);
+
+/**
+ * @brief LEDC stop.
+ *        Disable LEDC output, and set idle level
+ *
+ * @param  speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param  channel LEDC channel(0-7), select from ledc_channel_t
+ * @param  idle_level Set output idle level after LEDC stops.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t ledc_stop(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t idle_level);
+
+/**
+ * @brief LEDC set channel frequency(Hz)
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param  timer_num LEDC timer index(0-3), select from ledc_timer_t
+ * @param  freq_hz Set the LEDC frequency
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_FAIL Can not find a proper pre-divider number base on the given frequency and the current bit_num.
+ */
+esp_err_t ledc_set_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num, uint32_t freq_hz);
+
+/**
+ * @brief      LEDC get channel frequency(Hz)
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param timer_num LEDC timer index(0-3), select from ledc_timer_t
+ *
+ * @return
+ *     - 0  error
+ *     - Others Current LEDC frequency
+ */
+uint32_t ledc_get_freq(ledc_mode_t speed_mode, ledc_timer_t timer_num);
+
+/**
+ * @brief LEDC set duty
+ *        Only after calling ledc_update_duty will the duty update.
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param channel LEDC channel(0-7), select from ledc_channel_t
+ * @param duty Set the LEDC duty, the duty range is [0, (2**bit_num) - 1]
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t ledc_set_duty(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty);
+
+/**
+ * @brief LEDC get duty
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param channel LEDC channel(0-7), select from ledc_channel_t
+ *
+ * @return
+ *     - (-1) parameter error
+ *     - Others Current LEDC duty
+ */
+int ledc_get_duty(ledc_mode_t speed_mode, ledc_channel_t channel);
+
+/**
+ * @brief LEDC set gradient
+ *        Set LEDC gradient, After the function calls the ledc_update_duty function, the function can take effect.
+ *
+ * @param  speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param  channel LEDC channel(0-7), select from ledc_channel_t
+ * @param  duty Set the start of the gradient duty, the duty range is [0, (2**bit_num) - 1]
+ * @param  gradule_direction Set the direction of the gradient
+ * @param  step_num Set the number of the gradient
+ * @param  duty_cyle_num Set how many LEDC tick each time the gradient lasts
+ * @param  duty_scale Set gradient change amplitude
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t ledc_set_fade(ledc_mode_t speed_mode, ledc_channel_t channel, uint32_t duty, ledc_duty_direction_t gradule_direction,
+                        uint32_t step_num, uint32_t duty_cyle_num, uint32_t duty_scale);
+
+/**
+ * @brief Register LEDC interrupt handler, the handler is an ISR.
+ *        The handler will be attached to the same CPU core that this function is running on.
+ *
+ * @param fn Interrupt handler function.
+ * @param arg User-supplied argument passed to the handler function.
+ * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+ *        ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
+ * @param arg Parameter for handler function
+ * @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will
+ *        be returned here.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Function pointer error.
+ */
+esp_err_t ledc_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, ledc_isr_handle_t *handle);
+
+/**
+ * @brief Configure LEDC settings
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param timer_sel  Timer index(0-3), there are 4 timers in LEDC module
+ * @param div_num Timer clock divide number, the timer clock is divided from the selected clock source
+ * @param bit_num The count number of one period, counter range is 0 ~ ((2 ** bit_num) - 1)
+ * @param clk_src Select LEDC source clock.
+ *
+ * @return
+ *     - (-1) Parameter error
+ *     - Other Current LEDC duty
+ */
+esp_err_t ledc_timer_set(ledc_mode_t speed_mode, ledc_timer_t timer_sel, uint32_t div_num, uint32_t bit_num, ledc_clk_src_t clk_src);
+
+/**
+ * @brief Reset LEDC timer
+ *
+ * @param  speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param  timer_sel LEDC timer index(0-3), select from ledc_timer_t
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t ledc_timer_rst(ledc_mode_t speed_mode, uint32_t timer_sel);
+
+/**
+ * @brief Pause LEDC timer counter
+ *
+ * @param  speed_mode  Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param  timer_sel LEDC timer index(0-3), select from ledc_timer_t
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ *
+ */
+esp_err_t ledc_timer_pause(ledc_mode_t speed_mode, uint32_t timer_sel);
+
+/**
+ * @brief Resume LEDC timer
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param timer_sel LEDC timer index(0-3), select from ledc_timer_t
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t ledc_timer_resume(ledc_mode_t speed_mode, uint32_t timer_sel);
+
+/**
+ * @brief Bind LEDC channel with the selected timer
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param channel LEDC channel index(0-7), select from ledc_channel_t
+ * @param timer_idx LEDC timer index(0-3), select from ledc_timer_t
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t ledc_bind_channel_timer(ledc_mode_t speed_mode, uint32_t channel, uint32_t timer_idx);
+
+/**
+ * @brief Set LEDC fade function. Should call ledc_fade_func_install() before calling this function.
+ *        Call ledc_fade_start() after this to start fading.
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,
+ * @param channel LEDC channel index(0-7), select from ledc_channel_t
+ * @param target_duty Target duty of fading.( 0 - (2 ** bit_num - 1)))
+ * @param scale Controls the increase or decrease step scale.
+ * @param cycle_num increase or decrease the duty every cycle_num cycles
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_STATE Fade function not installed.
+ *     - ESP_FAIL Fade function init error
+ */
+esp_err_t ledc_set_fade_with_step(ledc_mode_t speed_mode, ledc_channel_t channel, int target_duty, int scale, int cycle_num);
+
+/**
+ * @brief Set LEDC fade function, with a limited time. Should call ledc_fade_func_install() before calling this function.
+ *        Call ledc_fade_start() after this to start fading.
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode,
+ * @param channel LEDC channel index(0-7), select from ledc_channel_t
+ * @param target_duty Target duty of fading.( 0 - (2 ** bit_num - 1)))
+ * @param max_fade_time_ms The maximum time of the fading ( ms ).
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_STATE Fade function not installed.
+ *     - ESP_FAIL Fade function init error
+ */
+esp_err_t ledc_set_fade_with_time(ledc_mode_t speed_mode, ledc_channel_t channel, int target_duty, int max_fade_time_ms);
+
+/**
+ * @brief Install ledc fade function. This function will occupy interrupt of LEDC module.
+ *
+ * @param intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+ *        ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_STATE Fade function already installed.
+ */
+esp_err_t ledc_fade_func_install(int intr_alloc_flags);
+
+/**
+ * @brief Uninstall LEDC fade function.
+ *
+ */
+void ledc_fade_func_uninstall();
+
+/**
+ * @brief Start LEDC fading.
+ *
+ * @param speed_mode Select the LEDC speed_mode, high-speed mode and low-speed mode
+ * @param channel LEDC channel number
+ * @param wait_done Whether to block until fading done.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_STATE Fade function not installed.
+ *     - ESP_ERR_INVALID_ARG Parameter error.
+ */
+esp_err_t ledc_fade_start(ledc_mode_t speed_mode, ledc_channel_t channel, ledc_fade_mode_t wait_done);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRIVER_LEDC_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/mcpwm.h

@@ -0,0 +1,709 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_MCPWM_H_
+#define _DRIVER_MCPWM_H_
+
+#include "esp_err.h"
+#include "soc/soc.h"
+#include "driver/gpio.h"
+#include "driver/periph_ctrl.h"
+#include "esp_intr.h"
+#include "esp_intr_alloc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief IO signals for MCPWM
+ *        6 MCPWM output pins that generate PWM signals
+ *        3 MCPWM fault input pins to detect faults like overcurrent, overvoltage, etc
+ *        3 MCPWM sync input pins to synchronize MCPWM outputs signals
+ *        3 MCPWM capture input pin to capture hall sell signal to measure time
+ */
+typedef enum {
+    MCPWM0A = 0,        /*!<PWM0A output pin*/
+    MCPWM0B,            /*!<PWM0B output pin*/
+    MCPWM1A,            /*!<PWM1A output pin*/
+    MCPWM1B,            /*!<PWM1B output pin*/
+    MCPWM2A,            /*!<PWM2A output pin*/
+    MCPWM2B,            /*!<PWM2B output pin*/
+    MCPWM_SYNC_0,       /*!<SYNC0  input pin*/
+    MCPWM_SYNC_1,       /*!<SYNC1  input pin*/
+    MCPWM_SYNC_2,       /*!<SYNC2  input pin*/
+    MCPWM_FAULT_0,      /*!<FAULT0 input pin*/
+    MCPWM_FAULT_1,      /*!<FAULT1 input pin*/
+    MCPWM_FAULT_2,      /*!<FAULT2 input pin*/
+    MCPWM_CAP_0 = 84,   /*!<CAP0   input pin*/
+    MCPWM_CAP_1,        /*!<CAP1   input pin*/
+    MCPWM_CAP_2,        /*!<CAP2   input pin*/
+} mcpwm_io_signals_t;
+
+/**
+ * @brief MCPWM pin number for
+ *
+ */
+typedef struct {
+    int mcpwm0a_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm0b_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm1a_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm1b_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm2a_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm2b_out_num;       /*!<MCPWM0A out pin*/
+    int mcpwm_sync0_in_num;    /*!<SYNC0  in pin*/
+    int mcpwm_sync1_in_num;    /*!<SYNC1  in pin*/
+    int mcpwm_sync2_in_num;    /*!<SYNC2  in pin*/
+    int mcpwm_fault0_in_num;   /*!<FAULT0 in pin*/
+    int mcpwm_fault1_in_num;   /*!<FAULT1 in pin*/
+    int mcpwm_fault2_in_num;   /*!<FAULT2 in pin*/
+    int mcpwm_cap0_in_num;     /*!<CAP0   in pin*/
+    int mcpwm_cap1_in_num;     /*!<CAP1   in pin*/
+    int mcpwm_cap2_in_num;     /*!<CAP2   in pin*/
+} mcpwm_pin_config_t;
+
+/**
+ * @brief Select MCPWM unit
+ */
+typedef enum {
+    MCPWM_UNIT_0 = 0,  /*!<MCPWM unit0 selected*/
+    MCPWM_UNIT_1,      /*!<MCPWM unit1 selected*/
+    MCPWM_UNIT_MAX,    /*!<Num of MCPWM units on ESP32*/
+} mcpwm_unit_t;
+
+/**
+ * @brief Select MCPWM timer
+ */
+typedef enum {
+    MCPWM_TIMER_0 = 0,  /*!<Select MCPWM timer0*/
+    MCPWM_TIMER_1,      /*!<Select MCPWM timer1*/
+    MCPWM_TIMER_2,      /*!<Select MCPWM timer2*/
+    MCPWM_TIMER_MAX,    /*!<Num of MCPWM timers on ESP32*/
+} mcpwm_timer_t;
+
+/**
+ * @brief Select MCPWM operator
+ */
+typedef enum {
+    MCPWM_OPR_A = 0,  /*!<Select MCPWMXA, where 'X' is timer number*/
+    MCPWM_OPR_B,      /*!<Select MCPWMXB, where 'X' is timer number*/
+    MCPWM_OPR_MAX,    /*!<Num of operators to each timer of MCPWM*/
+} mcpwm_operator_t;
+
+/**
+ * @brief Select type of MCPWM counter
+ */
+typedef enum {
+    MCPWM_UP_COUNTER = 1,   /*!<For asymmetric MCPWM*/
+    MCPWM_DOWN_COUNTER,     /*!<For asymmetric MCPWM*/
+    MCPWM_UP_DOWN_COUNTER,  /*!<For symmetric MCPWM, frequency is half of MCPWM frequency set*/
+    MCPWM_COUNTER_MAX,      /*!<Maximum counter mode*/
+} mcpwm_counter_type_t;
+
+/**
+ * @brief Select type of MCPWM duty cycle mode
+ */
+typedef enum {
+    MCPWM_DUTY_MODE_0 = 0, /*!<Active high duty, i.e. duty cycle proportional to high time for asymmetric MCPWM*/
+    MCPWM_DUTY_MODE_1,     /*!<Active low duty,  i.e. duty cycle proportional to low  time for asymmetric MCPWM, out of phase(inverted) MCPWM*/
+    MCPWM_DUTY_MODE_MAX,   /*!<Num of duty cycle modes*/
+} mcpwm_duty_type_t;
+
+/**
+ * @brief MCPWM carrier oneshot mode, in this mode the width of the first pulse of carrier can be programmed
+ */
+typedef enum {
+    MCPWM_ONESHOT_MODE_DIS = 0,  /*!<Enable oneshot mode*/
+    MCPWM_ONESHOT_MODE_EN,       /*!<Disable oneshot mode*/
+} mcpwm_carrier_os_t;
+
+/**
+ * @brief MCPWM carrier output inversion, high frequency carrier signal active with MCPWM signal is high
+ */
+typedef enum {
+    MCPWM_CARRIER_OUT_IVT_DIS = 0,  /*!<Enable  carrier output inversion*/
+    MCPWM_CARRIER_OUT_IVT_EN,       /*!<Disable carrier output inversion*/
+} mcpwm_carrier_out_ivt_t;
+
+/**
+ * @brief MCPWM select sync signal input
+ */
+typedef enum {
+    MCPWM_SELECT_SYNC0 = 4,  /*!<Select SYNC0 as input*/
+    MCPWM_SELECT_SYNC1,      /*!<Select SYNC1 as input*/
+    MCPWM_SELECT_SYNC2,      /*!<Select SYNC2 as input*/
+} mcpwm_sync_signal_t;
+
+/**
+ * @brief MCPWM select fault signal input
+ */
+typedef enum {
+    MCPWM_SELECT_F0 = 0,  /*!<Select F0 as input*/
+    MCPWM_SELECT_F1,      /*!<Select F1 as input*/
+    MCPWM_SELECT_F2,      /*!<Select F2 as input*/
+} mcpwm_fault_signal_t;
+
+/**
+ * @brief MCPWM select triggering level of fault signal
+ */
+typedef enum {
+    MCPWM_LOW_LEVEL_TGR = 0,  /*!<Fault condition occurs when fault input signal goes from high to low, currently not supported*/
+    MCPWM_HIGH_LEVEL_TGR,     /*!<Fault condition occurs when fault input signal goes low to high*/
+} mcpwm_fault_input_level_t;
+
+/**
+ * @brief MCPWM select action to be taken on MCPWMXA when fault occurs
+ */
+typedef enum {
+    MCPWM_NO_CHANGE_IN_MCPWMXA = 0,  /*!<No change in MCPWMXA output*/
+    MCPWM_FORCE_MCPWMXA_LOW,         /*!<Make MCPWMXA output low*/
+    MCPWM_FORCE_MCPWMXA_HIGH,        /*!<Make MCPWMXA output high*/
+    MCPWM_TOG_MCPWMXA,               /*!<Make MCPWMXA output toggle*/
+} mcpwm_action_on_pwmxa_t;
+
+/**
+ * @brief MCPWM select action to be taken on MCPWMxB when fault occurs
+ */
+typedef enum {
+    MCPWM_NO_CHANGE_IN_MCPWMXB = 0,  /*!<No change in MCPWMXB output*/
+    MCPWM_FORCE_MCPWMXB_LOW,         /*!<Make MCPWMXB output low*/
+    MCPWM_FORCE_MCPWMXB_HIGH,        /*!<Make MCPWMXB output high*/
+    MCPWM_TOG_MCPWMXB,               /*!<Make MCPWMXB output toggle*/
+} mcpwm_action_on_pwmxb_t;
+
+/**
+ * @brief MCPWM select capture signal input
+ */
+typedef enum {
+    MCPWM_SELECT_CAP0 = 0, /*!<Select CAP0 as input*/
+    MCPWM_SELECT_CAP1,     /*!<Select CAP1 as input*/
+    MCPWM_SELECT_CAP2,     /*!<Select CAP2 as input*/
+} mcpwm_capture_signal_t;
+
+/**
+ * @brief MCPWM select capture starts from which edge
+ */
+typedef enum {
+    MCPWM_NEG_EDGE = 0,  /*!<Capture starts from negative edge*/
+    MCPWM_POS_EDGE,      /*!<Capture starts from positive edge*/
+} mcpwm_capture_on_edge_t;
+
+/**
+ * @brief MCPWM deadtime types, used to generate deadtime, RED refers to rising edge delay and FED refers to falling edge delay
+ */
+typedef enum {
+    MCPWM_BYPASS_RED = 0,               /*!<MCPWMXA = no change, MCPWMXB = falling edge delay*/
+    MCPWM_BYPASS_FED,                   /*!<MCPWMXA = rising edge delay, MCPWMXB = no change*/
+    MCPWM_ACTIVE_HIGH_MODE,             /*!<MCPWMXA = rising edge delay,  MCPWMXB = falling edge delay*/
+    MCPWM_ACTIVE_LOW_MODE,              /*!<MCPWMXA = compliment of rising edge delay,  MCPWMXB = compliment of falling edge delay*/
+    MCPWM_ACTIVE_HIGH_COMPLIMENT_MODE,  /*!<MCPWMXA = rising edge delay,  MCPWMXB = compliment of falling edge delay*/
+    MCPWM_ACTIVE_LOW_COMPLIMENT_MODE,   /*!<MCPWMXA = compliment of rising edge delay,  MCPWMXB = falling edge delay*/
+    MCPWM_ACTIVE_RED_FED_FROM_PWMXA,    /*!<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXA*/
+    MCPWM_ACTIVE_RED_FED_FROM_PWMXB,    /*!<MCPWMXA = MCPWMXB = rising edge delay as well as falling edge delay, generated from MCPWMXB*/
+    MCPWM_DEADTIME_TYPE_MAX,
+} mcpwm_deadtime_type_t;
+
+/**
+ * @brief MCPWM config structure
+ */
+typedef struct {
+    uint32_t frequency;              /*!<Set frequency of MCPWM in Hz*/
+    float cmpr_a;                    /*!<Set % duty cycle for operator a(MCPWMXA), i.e for 62.3% duty cycle, duty_a = 62.3*/
+    float cmpr_b;                    /*!<Set % duty cycle for operator b(MCPWMXB), i.e for 48% duty cycle, duty_b = 48.0*/
+    mcpwm_duty_type_t duty_mode;     /*!<Set type of duty cycle*/
+    mcpwm_counter_type_t counter_mode;  /*!<Set  type of MCPWM counter*/
+} mcpwm_config_t;
+
+/**
+ * @brief MCPWM config carrier structure
+ */
+typedef struct {
+    uint8_t carrier_period;                 /*!<Set carrier period = (carrier_period + 1)*800ns, carrier_period should be < 16*/
+    uint8_t carrier_duty;                   /*!<Set carrier duty cycle, carrier_duty should be less then 8(increment every 12.5%)*/
+    uint8_t pulse_width_in_os;              /*!<Set pulse width of first pulse in one shot mode = (carrier period)*(pulse_width_in_os + 1), should be less then 16*/
+    mcpwm_carrier_os_t carrier_os_mode;        /*!<Enable or disable carrier oneshot mode*/
+    mcpwm_carrier_out_ivt_t carrier_ivt_mode;  /*!<Invert output of carrier*/
+} mcpwm_carrier_config_t;
+
+
+/**
+ * @brief This function initializes each gpio signal for MCPWM
+ *        @note
+ *        This function initializes one gpio at a time.
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param io_signal set MCPWM signals, each MCPWM unit has 6 output(MCPWMXA, MCPWMXB) and 9 input(SYNC_X, FAULT_X, CAP_X)
+ *                  'X' is timer_num(0-2)
+ * @param gpio_num set this to configure gpio for MCPWM, if you want to use gpio16, gpio_num = 16
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_gpio_init(mcpwm_unit_t mcpwm_num, mcpwm_io_signals_t io_signal, int gpio_num);
+
+/**
+ * @brief Initialize MCPWM gpio structure
+ *        @note
+ *        This function can be used to initialize more then one gpio at a time.
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param mcpwm_pin MCPWM pin structure
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_pin(mcpwm_unit_t mcpwm_num, const mcpwm_pin_config_t *mcpwm_pin);
+
+/**
+ * @brief Initialize MCPWM parameters
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param mcpwm_conf configure structure mcpwm_config_t
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_init( mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_config_t  *mcpwm_conf);
+
+/**
+ * @brief Set frequency(in Hz) of MCPWM timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param frequency set the frequency in Hz of each timer
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint32_t frequency);
+
+/**
+ * @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB)
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'X' is timer number selected
+ * @param duty set duty cycle in %(i.e for 62.3% duty cycle, duty = 62.3) of each operator
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, float duty);
+
+/**
+ * @brief Set duty cycle of each operator(MCPWMXA/MCPWMXB) in us
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+ * @param duty set duty value in microseconds of each operator
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_duty_in_us(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, uint32_t duty);
+
+/**
+ * @brief Set duty either active high or active low(out of phase/inverted)
+ *        @note
+ *        Call this function every time after mcpwm_set_signal_high or mcpwm_set_signal_low to resume with previously set duty cycle
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+ * @param duty_num set active low or active high duty type
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_duty_type(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num, mcpwm_duty_type_t duty_num);
+
+/**
+* @brief Get frequency of timer
+*
+* @param mcpwm_num set MCPWM unit(0-1)
+* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+*
+* @return
+*     - frequency of timer
+*/
+uint32_t mcpwm_get_frequency(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Get duty cycle of each operator
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+ *
+ * @return
+ *     - duty cycle in % of each operator(56.7 means duty is 56.7%)
+ */
+float mcpwm_get_duty(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
+
+/**
+ * @brief Use this function to set MCPWM signal high
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_signal_high(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
+
+/**
+ * @brief Use this function to set MCPWM signal low
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param op_num set the operator(MCPWMXA/MCPWMXB), 'x' is timer number selected
+
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_set_signal_low(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_operator_t op_num);
+/**
+ * @brief Start MCPWM signal on timer 'x'
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_start(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Start MCPWM signal on timer 'x'
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_stop(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief  Initialize carrier configuration
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_conf configure structure mcpwm_carrier_config_t
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_init(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, const mcpwm_carrier_config_t *carrier_conf);
+
+/**
+* @brief Enable MCPWM carrier submodule, for respective timer
+*
+* @param mcpwm_num set MCPWM unit(0-1)
+* @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+*
+* @return
+*     - ESP_OK Success
+*     - ESP_ERR_INVALID_ARG Parameter error
+*/
+esp_err_t mcpwm_carrier_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Disable MCPWM carrier submodule, for respective timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Set period of carrier
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_period set the carrier period of each timer, carrier period = (carrier_period + 1)*800ns
+ *                    (carrier_period <= 15)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_set_period(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t carrier_period);
+
+/**
+ * @brief Set duty_cycle of carrier
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_duty set duty_cycle of carrier , carrier duty cycle = carrier_duty*12.5%
+ *                  (chop_duty <= 7)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_set_duty_cycle(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t carrier_duty);
+
+/**
+ * @brief Enable and set width of first pulse in carrier oneshot mode
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param pulse_width set pulse width of first pulse in oneshot mode, width = (carrier period)*(pulse_width +1)
+ *                    (pulse_width <= 15)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_oneshot_mode_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, uint8_t pulse_width);
+
+/**
+ * @brief Disable oneshot mode, width of first pulse = carrier period
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_oneshot_mode_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Enable or disable carrier output inversion
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param carrier_ivt_mode enable or disable carrier output inversion
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_carrier_output_invert(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num,
+                                      mcpwm_carrier_out_ivt_t carrier_ivt_mode);
+
+/**
+ * @brief Enable and initialize deadtime for each MCPWM timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param dt_mode set deadtime mode
+ * @param red set rising edge delay = red*100ns
+ * @param fed set rising edge delay = fed*100ns
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_deadtime_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_deadtime_type_t dt_mode,
+                                uint32_t red, uint32_t fed);
+
+/**
+ * @brief Disable deadtime on MCPWM timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_deadtime_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Initialize fault submodule, currently low level triggering not supported
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param intput_level set fault signal level, which will cause fault to occur
+ * @param fault_sig set the fault Pin, which needs to be enabled
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_init(mcpwm_unit_t mcpwm_num, mcpwm_fault_input_level_t intput_level, mcpwm_fault_signal_t fault_sig);
+
+/**
+ * @brief Set oneshot mode on fault detection, once fault occur in oneshot mode reset is required to resume MCPWM signals
+ *        @note
+ *        currently low level triggering not supported
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param fault_sig set the fault Pin, which needs to be enabled for oneshot mode
+ * @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle
+ * @param action_on_pwmxb action to be taken on MCPWMXB when fault occurs, either no change or high or low or toggle
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_set_oneshot_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_fault_signal_t fault_sig,
+                                       mcpwm_action_on_pwmxa_t action_on_pwmxa, mcpwm_action_on_pwmxb_t action_on_pwmxb);
+
+/**
+ * @brief Set cycle-by-cycle mode on fault detection, once fault occur in cyc mode MCPWM signal resumes as soon as fault signal becomes inactive
+ *        @note
+ *        currently low level triggering not supported
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param fault_sig set the fault Pin, which needs to be enabled for cyc mode
+ * @param action_on_pwmxa action to be taken on MCPWMXA when fault occurs, either no change or high or low or toggle
+ * @param action_on_pwmxb action to be taken on MCPWMXB when fault occurs, either no change or high or low or toggle
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_set_cyc_mode(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_fault_signal_t fault_sig,
+                                   mcpwm_action_on_pwmxa_t action_on_pwmxa, mcpwm_action_on_pwmxb_t action_on_pwmxb);
+
+/**
+ * @brief Disable fault signal
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param fault_sig fault pin, which needs to be disabled
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_fault_deinit(mcpwm_unit_t mcpwm_num, mcpwm_fault_signal_t fault_sig);
+
+/**
+ * @brief Initialize capture submodule
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param cap_edge set capture edge, BIT(0) - negative edge, BIT(1) - positive edge
+ * @param cap_sig capture Pin, which needs to be enabled
+ * @param num_of_pulse count time between rising/falling edge between 2 *(pulses mentioned), counter uses APB_CLK
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+
+esp_err_t mcpwm_capture_enable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig, mcpwm_capture_on_edge_t cap_edge,
+                               uint32_t num_of_pulse);
+
+/**
+ * @brief Disable capture signal
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param cap_sig capture Pin, which needs to be disabled
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_capture_disable(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
+
+/**
+ * @brief Get capture value
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param cap_sig capture pin on which value is to be measured
+ *
+ * @return
+ *     Captured value
+ */
+uint32_t mcpwm_capture_signal_get_value(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
+
+/**
+ * @brief Get edge of capture signal
+ *
+ * @param mcpwm_num set MCPWM Channel(0-1)
+ * @param cap_sig capture pin of whose edge is to be determined
+ *
+ * @return
+ *     Capture signal edge: 1 - positive edge, 2 - negtive edge
+ */
+uint32_t mcpwm_capture_signal_get_edge(mcpwm_unit_t mcpwm_num, mcpwm_capture_signal_t cap_sig);
+
+/**
+ * @brief Initialize sync submodule
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ * @param sync_sig set the fault Pin, which needs to be enabled
+ * @param phase_val phase value in 1/1000(for 86.7%, phase_val = 867) which timer moves to on sync signal
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_sync_enable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num, mcpwm_sync_signal_t sync_sig,
+                            uint32_t phase_val);
+
+/**
+ * @brief Disable sync submodule on given timer
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param timer_num set timer number(0-2) of MCPWM, each MCPWM unit has 3 timers
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t mcpwm_sync_disable(mcpwm_unit_t mcpwm_num, mcpwm_timer_t timer_num);
+
+/**
+ * @brief Register MCPWM interrupt handler, the handler is an ISR.
+ *        the handler will be attached to the same CPU core that this function is running on.
+ *
+ * @param mcpwm_num set MCPWM unit(0-1)
+ * @param fn interrupt handler function.
+ * @param arg user-supplied argument passed to the handler function.
+ * @param intr_alloc_flags flags used to allocate the interrupt. One or multiple (ORred)
+ *        ESP_INTR_FLAG_* values. see esp_intr_alloc.h for more info.
+ * @param arg parameter for handler function
+ * @param handle pointer to return handle. If non-NULL, a handle for the interrupt will
+ *        be returned here.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Function pointer error.
+ */
+esp_err_t mcpwm_isr_register(mcpwm_unit_t mcpwm_num, void (*fn)(void *), void *arg, int intr_alloc_flags, intr_handle_t *handle);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*_DRIVER_MCPWM_H_*/

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/pcnt.h

@@ -0,0 +1,360 @@
+#ifndef __PCNT_H__
+#define __PCNT_H__
+
+#include <esp_types.h>
+#include "esp_intr.h"
+#include "esp_err.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+#include "freertos/xtensa_api.h"
+#include "soc/soc.h"
+#include "soc/pcnt_reg.h"
+#include "soc/pcnt_struct.h"
+#include "soc/gpio_sig_map.h"
+#include "driver/gpio.h"
+#include "esp_intr_alloc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PCNT_PIN_NOT_USED     (-1)  /*!< Pin are not used */
+
+typedef enum {
+    PCNT_MODE_KEEP = 0,             /*!< Control mode: won't change counter mode*/
+    PCNT_MODE_REVERSE = 1,          /*!< Control mode: invert counter mode(increase -> decrease, decrease -> increase);*/
+    PCNT_MODE_DISABLE = 2,          /*!< Control mode: Inhibit counter(counter value will not change in this condition)*/
+    PCNT_MODE_MAX
+} pcnt_ctrl_mode_t;
+
+typedef enum {
+    PCNT_COUNT_DIS = 0,            /*!< Counter mode: Inhibit counter(counter value will not change in this condition)*/
+    PCNT_COUNT_INC = 1,            /*!< Counter mode: Increase counter value*/
+    PCNT_COUNT_DEC = 2,            /*!< Counter mode: Decrease counter value*/
+    PCNT_COUNT_MAX
+} pcnt_count_mode_t;
+
+typedef enum {
+    PCNT_UNIT_0 = 0,                 /*!< PCNT unit0 */
+    PCNT_UNIT_1 = 1,                 /*!< PCNT unit1 */
+    PCNT_UNIT_2 = 2,                 /*!< PCNT unit2 */
+    PCNT_UNIT_3 = 3,                 /*!< PCNT unit3 */
+    PCNT_UNIT_4 = 4,                 /*!< PCNT unit4 */
+    PCNT_UNIT_5 = 5,                 /*!< PCNT unit5 */
+    PCNT_UNIT_6 = 6,                 /*!< PCNT unit6 */
+    PCNT_UNIT_7 = 7,                 /*!< PCNT unit7 */
+    PCNT_UNIT_MAX,
+} pcnt_unit_t; 
+
+typedef enum {
+    PCNT_CHANNEL_0 = 0x00,           /*!< PCNT channel0 */
+    PCNT_CHANNEL_1 = 0x01,           /*!< PCNT channel1 */
+    PCNT_CHANNEL_MAX,
+} pcnt_channel_t;
+
+typedef enum {
+    PCNT_EVT_L_LIM = 0,             /*!< PCNT watch point event: Minimum counter value */
+    PCNT_EVT_H_LIM = 1,             /*!< PCNT watch point event: Maximum counter value*/
+    PCNT_EVT_THRES_0 = 2,            /*!< PCNT watch point event: threshold0 value event*/
+    PCNT_EVT_THRES_1 = 3,            /*!< PCNT watch point event: threshold1 value event*/
+    PCNT_EVT_ZERO = 4,              /*!< PCNT watch point event: counter value zero event*/
+    PCNT_EVT_MAX
+} pcnt_evt_type_t;
+
+/**
+ * @brief Pulse Counter configure struct
+ */
+typedef struct {
+    int pulse_gpio_num;             /*!< Pulse input gpio_num, if you want to use gpio16, pulse_gpio_num = 16, a negative value will be ignored */
+    int ctrl_gpio_num;              /*!< Contol signal input gpio_num, a negative value will be ignored*/
+    pcnt_ctrl_mode_t lctrl_mode;    /*!< PCNT low control mode*/
+    pcnt_ctrl_mode_t hctrl_mode;    /*!< PCNT high control mode*/
+    pcnt_count_mode_t pos_mode;     /*!< PCNT positive edge count mode*/
+    pcnt_count_mode_t neg_mode;     /*!< PCNT negative edge count mode*/
+    int16_t counter_h_lim;          /*!< Maximum counter value */
+    int16_t counter_l_lim;          /*!< Minimum counter value */
+    pcnt_unit_t unit;               /*!< PCNT unit number */
+    pcnt_channel_t channel;         /*!< the PCNT channel */
+} pcnt_config_t;
+
+typedef intr_handle_t pcnt_isr_handle_t;
+
+/**
+ * @brief Configure Pulse Counter unit
+ *
+ * @param pcnt_config Pointer of Pulse Counter unit configure parameter
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_unit_config(const pcnt_config_t *pcnt_config);
+
+/**
+ * @brief Get pulse counter value
+ *
+ * @param pcnt_unit  Pulse Counter unit number
+ * @param count Pointer to accept counter value
+ *
+ * @return  
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_get_counter_value(pcnt_unit_t pcnt_unit, int16_t* count);
+
+/**
+ * @brief Pause PCNT counter of PCNT unit
+ *
+ * @param pcnt_unit PCNT unit number
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_counter_pause(pcnt_unit_t pcnt_unit);
+
+/**
+ * @brief Resume counting for PCNT counter
+ *
+ * @param pcnt_unit PCNT unit number, select from pcnt_unit_t
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_counter_resume(pcnt_unit_t pcnt_unit);
+
+/**
+ * @brief Clear and reset PCNT counter value to zero
+ *
+ * @param  pcnt_unit PCNT unit number, select from pcnt_unit_t
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_counter_clear(pcnt_unit_t pcnt_unit);
+
+/**
+ * @brief Enable PCNT interrupt for PCNT unit
+ *        @note
+ *        Each Pulse counter unit has five watch point events that share the same interrupt.
+ *        Configure events with pcnt_event_enable() and pcnt_event_disable()
+ *
+ * @param pcnt_unit PCNT unit number
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_intr_enable(pcnt_unit_t pcnt_unit);
+
+/**
+ * @brief Disable PCNT interrupt for PCNT uint
+ *
+ * @param pcnt_unit PCNT unit number
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_intr_disable(pcnt_unit_t pcnt_unit);
+
+/**
+ * @brief Enable PCNT event of PCNT unit
+ *
+ * @param unit PCNT unit number
+ * @param evt_type Watch point event type.
+ *                 All enabled events share the same interrupt (one interrupt per pulse counter unit).
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_event_enable(pcnt_unit_t unit, pcnt_evt_type_t evt_type);
+
+/**
+ * @brief Disable PCNT event of PCNT unit
+ *
+ * @param unit PCNT unit number
+ * @param evt_type Watch point event type.
+ *                 All enabled events share the same interrupt (one interrupt per pulse counter unit).
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_event_disable(pcnt_unit_t unit, pcnt_evt_type_t evt_type);
+
+/**
+ * @brief Set PCNT event value of PCNT unit
+ *
+ * @param unit PCNT unit number
+ * @param evt_type Watch point event type.
+ *                 All enabled events share the same interrupt (one interrupt per pulse counter unit).
+ *
+ * @param value Counter value for PCNT event
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_set_event_value(pcnt_unit_t unit, pcnt_evt_type_t evt_type, int16_t value);
+
+/**
+ * @brief Get PCNT event value of PCNT unit
+ *
+ * @param unit PCNT unit number
+ * @param evt_type Watch point event type.
+ *                 All enabled events share the same interrupt (one interrupt per pulse counter unit).
+ * @param value Pointer to accept counter value for PCNT event
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_get_event_value(pcnt_unit_t unit, pcnt_evt_type_t evt_type, int16_t *value);
+
+/**
+ * @brief Register PCNT interrupt handler, the handler is an ISR.
+ *        The handler will be attached to the same CPU core that this function is running on.
+ *
+ * @param fn Interrupt handler function.
+ * @param arg Parameter for handler function
+ * @param  intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+ *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
+ * @param  handle Pointer to return handle. If non-NULL, a handle for the interrupt will
+ *            be returned here.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Function pointer error.
+ */
+esp_err_t pcnt_isr_register(void (*fn)(void*), void * arg, int intr_alloc_flags, pcnt_isr_handle_t *handle);
+
+/**
+ * @brief Configure PCNT pulse signal input pin and control input pin
+ *
+ * @param unit PCNT unit number
+ * @param channel PCNT channel number
+ * @param pulse_io Pulse signal input GPIO
+ *        @note
+ *        Set to PCNT_PIN_NOT_USED if unused.
+ * @param ctrl_io Control signal input GPIO
+ *        @note
+ *        Set to PCNT_PIN_NOT_USED if unused.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_set_pin(pcnt_unit_t unit, pcnt_channel_t channel, int pulse_io, int ctrl_io);
+
+/**
+ * @brief Enable PCNT input filter
+ *
+ * @param unit PCNT unit number
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_filter_enable(pcnt_unit_t unit);
+
+/**
+ * @brief Disable PCNT input filter
+ *
+ * @param unit PCNT unit number
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_filter_disable(pcnt_unit_t unit);
+
+/**
+ * @brief Set PCNT filter value
+ *
+ * @param unit PCNT unit number
+ * @param filter_val PCNT signal filter value, counter in APB_CLK cycles.
+ *        Any pulses lasting shorter than this will be ignored when the filter is enabled.
+ *        @note
+ *        filter_val is a 10-bit value, so the maximum filter_val should be limited to 1023.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_set_filter_value(pcnt_unit_t unit, uint16_t filter_val);
+
+/**
+ * @brief Get PCNT filter value
+ *
+ * @param unit PCNT unit number
+ * @param filter_val Pointer to accept PCNT filter value.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_get_filter_value(pcnt_unit_t unit, uint16_t *filter_val);
+
+/**
+ * @brief Set PCNT counter mode
+ *
+ * @param unit PCNT unit number
+ * @param channel PCNT channel number
+ * @param pos_mode Counter mode when detecting positive edge
+ * @param neg_mode Counter mode when detecting negative edge
+ * @param hctrl_mode Counter mode when control signal is high level
+ * @param lctrl_mode Counter mode when control signal is low level
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t pcnt_set_mode(pcnt_unit_t unit, pcnt_channel_t channel,
+                        pcnt_count_mode_t pos_mode, pcnt_count_mode_t neg_mode,
+                        pcnt_ctrl_mode_t hctrl_mode, pcnt_ctrl_mode_t lctrl_mode);
+
+
+/**
+ * @addtogroup pcnt-examples
+ *
+ * @{
+ *
+ * EXAMPLE OF PCNT CONFIGURATION
+ * ==============================
+ * @code{c}
+ * //1. Config PCNT unit
+ * pcnt_config_t pcnt_config = {
+ *     .pulse_gpio_num = 4,         //set gpio4 as pulse input gpio
+ *     .ctrl_gpio_num = 5,          //set gpio5 as control gpio
+ *     .channel = PCNT_CHANNEL_0,         //use unit 0 channel 0
+ *     .lctrl_mode = PCNT_MODE_REVERSE,   //when control signal is low ,reverse the primary counter mode(inc->dec/dec->inc)
+ *     .hctrl_mode = PCNT_MODE_KEEP,      //when control signal is high,keep the primary counter mode
+ *     .pos_mode = PCNT_COUNT_INC,        //increment the counter
+ *     .neg_mode = PCNT_COUNT_DIS,        //keep the counter value
+ *     .counter_h_lim = 10,
+ *     .counter_l_lim = -10,
+ * };
+ * pcnt_unit_config(&pcnt_config);        //init unit
+ * @endcode
+ *
+ * EXAMPLE OF PCNT EVENT SETTING
+ * ==============================
+ * @code{c}
+ * //2. Configure PCNT watchpoint event.
+ * pcnt_set_event_value(PCNT_UNIT_0, PCNT_EVT_THRES_1, 5);   //set thres1 value
+ * pcnt_event_enable(PCNT_UNIT_0, PCNT_EVT_THRES_1);         //enable thres1 event
+ * @endcode
+ *
+ * For more examples please refer to PCNT example code in IDF_PATH/examples
+ *
+ * @}
+ */
+
+#ifdef __cplusplus 
+}
+#endif
+
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/periph_ctrl.h

@@ -0,0 +1,80 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_PERIPH_CTRL_H_
+#define _DRIVER_PERIPH_CTRL_H_
+#include "esp_err.h"
+#include "soc/soc.h"
+#include "soc/dport_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PERIPH_LEDC_MODULE = 0,
+    PERIPH_UART0_MODULE,
+    PERIPH_UART1_MODULE,
+    PERIPH_UART2_MODULE,
+    PERIPH_I2C0_MODULE,
+    PERIPH_I2C1_MODULE,
+    PERIPH_I2S0_MODULE,
+    PERIPH_I2S1_MODULE,
+    PERIPH_TIMG0_MODULE,
+    PERIPH_TIMG1_MODULE,
+    PERIPH_PWM0_MODULE,
+    PERIPH_PWM1_MODULE,
+    PERIPH_PWM2_MODULE,
+    PERIPH_PWM3_MODULE,
+    PERIPH_UHCI0_MODULE,
+    PERIPH_UHCI1_MODULE,
+    PERIPH_RMT_MODULE,
+    PERIPH_PCNT_MODULE,
+    PERIPH_SPI_MODULE,
+    PERIPH_HSPI_MODULE,
+    PERIPH_VSPI_MODULE,
+    PERIPH_SPI_DMA_MODULE,
+    PERIPH_SDMMC_MODULE,
+    PERIPH_SDIO_SLAVE_MODULE,
+    PERIPH_CAN_MODULE,
+    PERIPH_EMAC_MODULE,
+} periph_module_t;
+
+/**
+ * @brief      enable peripheral module
+ *
+ * @param[in]  periph    :  Peripheral module name
+ *
+ *
+ * @return     NULL
+ *
+ */
+void periph_module_enable(periph_module_t periph);
+
+/**
+ * @brief      disable peripheral module
+ *
+ * @param[in]  periph    :  Peripheral module name
+ *
+ *
+ * @return     NULL
+ *
+ */
+void periph_module_disable(periph_module_t periph);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRIVER_PERIPH_CTRL_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/rmt.h

@@ -0,0 +1,794 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_RMT_CTRL_H_
+#define _DRIVER_RMT_CTRL_H_
+#include "esp_err.h"
+#include "soc/rmt_reg.h"
+#include "soc/dport_reg.h"
+#include "soc/rmt_struct.h"
+#include "ringbuf.h"
+#include "driver/gpio.h"
+#include "driver/periph_ctrl.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RMT_MEM_BLOCK_BYTE_NUM (256)
+#define RMT_MEM_ITEM_NUM  (RMT_MEM_BLOCK_BYTE_NUM/4)
+
+typedef enum {
+    RMT_CHANNEL_0=0, /*!< RMT Channel0 */
+    RMT_CHANNEL_1,   /*!< RMT Channel1 */
+    RMT_CHANNEL_2,   /*!< RMT Channel2 */
+    RMT_CHANNEL_3,   /*!< RMT Channel3 */
+    RMT_CHANNEL_4,   /*!< RMT Channel4 */
+    RMT_CHANNEL_5,   /*!< RMT Channel5 */
+    RMT_CHANNEL_6,   /*!< RMT Channel6 */
+    RMT_CHANNEL_7,   /*!< RMT Channel7 */
+    RMT_CHANNEL_MAX
+} rmt_channel_t;
+
+typedef enum {
+    RMT_MEM_OWNER_TX = 0,  /*!< RMT RX mode, RMT transmitter owns the memory block*/
+    RMT_MEM_OWNER_RX = 1,  /*!< RMT RX mode, RMT receiver owns the memory block*/
+    RMT_MEM_OWNER_MAX,
+}rmt_mem_owner_t;
+
+typedef enum {
+    RMT_BASECLK_REF = 0,   /*!< RMT source clock system reference tick, 1MHz by default(Not supported in this version) */
+    RMT_BASECLK_APB,       /*!< RMT source clock is APB CLK, 80Mhz by default */
+    RMT_BASECLK_MAX,
+} rmt_source_clk_t;
+
+typedef enum {
+    RMT_DATA_MODE_FIFO = 0,  /*<! RMT memory access in FIFO mode */
+    RMT_DATA_MODE_MEM = 1,   /*<! RMT memory access in memory mode */
+    RMT_DATA_MODE_MAX,
+} rmt_data_mode_t;
+
+typedef enum {
+    RMT_MODE_TX=0,   /*!< RMT TX mode */
+    RMT_MODE_RX,     /*!< RMT RX mode */
+    RMT_MODE_MAX
+} rmt_mode_t;
+
+typedef enum {
+    RMT_IDLE_LEVEL_LOW=0,   /*!< RMT TX idle level: low Level */
+    RMT_IDLE_LEVEL_HIGH,    /*!< RMT TX idle level: high Level */
+    RMT_IDLE_LEVEL_MAX,
+} rmt_idle_level_t;
+
+typedef enum {
+    RMT_CARRIER_LEVEL_LOW=0,  /*!< RMT carrier wave is modulated for low Level output */
+    RMT_CARRIER_LEVEL_HIGH,   /*!< RMT carrier wave is modulated for high Level output */
+    RMT_CARRIER_LEVEL_MAX
+} rmt_carrier_level_t;
+
+/**
+ * @brief Data struct of RMT TX configure parameters
+ */
+typedef struct {
+    bool loop_en;                         /*!< RMT loop output mode*/
+    uint32_t carrier_freq_hz;             /*!< RMT carrier frequency */
+    uint8_t carrier_duty_percent;         /*!< RMT carrier duty (%) */
+    rmt_carrier_level_t carrier_level;    /*!< RMT carrier level */
+    bool carrier_en;                      /*!< RMT carrier enable */
+    rmt_idle_level_t idle_level;          /*!< RMT idle level */
+    bool idle_output_en;                  /*!< RMT idle level output enable*/
+}rmt_tx_config_t;
+
+/**
+ * @brief Data struct of RMT RX configure parameters
+ */
+typedef struct {
+    bool filter_en;                    /*!< RMT receiver filer enable*/
+    uint8_t filter_ticks_thresh;       /*!< RMT filter tick  number */
+    uint16_t idle_threshold;           /*!< RMT RX idle threshold */
+}rmt_rx_config_t;
+
+/**
+ * @brief Data struct of RMT configure parameters
+ */
+typedef struct {
+    rmt_mode_t rmt_mode;               /*!< RMT mode: transmitter or receiver */
+    rmt_channel_t channel;             /*!< RMT channel */
+    uint8_t clk_div;                   /*!< RMT channel counter divider */
+    gpio_num_t gpio_num;               /*!< RMT GPIO number */
+    uint8_t mem_block_num;             /*!< RMT memory block number */
+    union{
+        rmt_tx_config_t tx_config;     /*!< RMT TX parameter */
+        rmt_rx_config_t rx_config;     /*!< RMT RX parameter */
+    };
+} rmt_config_t;
+
+typedef intr_handle_t rmt_isr_handle_t;
+
+/**
+ * @brief Set RMT clock divider, channel clock is divided from source clock.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param div_cnt RMT counter clock divider
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt);
+
+/**
+ * @brief Get RMT clock divider, channel clock is divided from source clock.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param div_cnt pointer to accept RMT counter divider
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t* div_cnt);
+
+/**
+ * @brief Set RMT RX idle threshold value
+ *
+ *        In receive mode, when no edge is detected on the input signal
+ *        for longer than idle_thres channel clock cycles,
+ *        the receive process is finished.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param thresh RMT RX idle threshold
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh);
+
+/**
+ * @brief Get RMT idle threshold value.
+ *
+ *        In receive mode, when no edge is detected on the input signal
+ *        for longer than idle_thres channel clock cycles,
+ *        the receive process is finished.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param thresh pointer to accept RMT RX idle threshold value
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh);
+
+/**
+ * @brief Set RMT memory block number for RMT channel
+ *
+ *        This function is used to configure the amount of memory blocks allocated to channel n
+ *        The 8 channels share a 512x32-bit RAM block which can be read and written
+ *        by the processor cores over the APB bus, as well as read by the transmitters
+ *        and written by the receivers.
+ *        The RAM address range for channel n is start_addr_CHn to end_addr_CHn, which are defined by:
+ *        Memory block start address is RMT_CHANNEL_MEM(n) (in soc/rmt_reg.h),
+ *        that is, start_addr_chn = RMT base address + 0x800 + 64 ∗ 4 ∗ n, and
+ *        end_addr_chn = RMT base address + 0x800 +  64 ∗ 4 ∗ n + 64 ∗ 4 ∗ RMT_MEM_SIZE_CHn mod 512 ∗ 4
+ *        @note
+ *        If memory block number of one channel is set to a value greater than 1, this channel will occupy the memory
+ *        block of the next channel.
+ *        Channel0 can use at most 8 blocks of memory, accordingly channel7 can only use one memory block.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param rmt_mem_num RMT RX memory block number, one block has 64 * 32 bits.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num);
+
+/**
+ * @brief Get RMT memory block number
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param rmt_mem_num Pointer to accept RMT RX memory block number
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t* rmt_mem_num);
+
+/**
+ * @brief Configure RMT carrier for TX signal.
+ *
+ *        Set different values for carrier_high and carrier_low to set different frequency of carrier.
+ *        The unit of carrier_high/low is the source clock tick, not the divided channel counter clock.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param carrier_en Whether to enable output carrier.
+ *
+ * @param high_level High level duration of carrier
+ *
+ * @param low_level Low level duration of carrier.
+ *
+ * @param carrier_level Configure the way carrier wave is modulated for channel0-7.
+ *
+ *                      1'b1:transmit on low output level
+ *
+ *                      1'b0:transmit on high output level
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t high_level, uint16_t low_level, rmt_carrier_level_t carrier_level);
+
+/**
+ * @brief Set RMT memory in low power mode.
+ *
+ *        Reduce power consumed by memory. 1:memory is in low power state.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param pd_en RMT memory low power enable.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en);
+
+/**
+ * @brief Get RMT memory low power mode.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param pd_en Pointer to accept RMT memory low power mode.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool* pd_en);
+
+/**
+ * @brief Set RMT start sending data from memory.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param tx_idx_rst Set true to reset memory index for TX.
+ *        Otherwise, transmitter will continue sending from the last index in memory.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst);
+
+/**
+ * @brief Set RMT stop sending.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_tx_stop(rmt_channel_t channel);
+
+/**
+ * @brief Set RMT start receiving data.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param rx_idx_rst Set true to reset memory index for receiver.
+ *                   Otherwise, receiver will continue receiving data to the last index in memory.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst);
+
+/**
+ * @brief Set RMT stop receiving data.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_rx_stop(rmt_channel_t channel);
+
+/**
+ * @brief Reset RMT TX/RX memory index.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_memory_rw_rst(rmt_channel_t channel);
+
+/**
+ * @brief Set RMT memory owner.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param owner To set when the transmitter or receiver can process the memory of channel.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner);
+
+/**
+ * @brief Get RMT memory owner.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param owner Pointer to get memory owner.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t* owner);
+
+/**
+ * @brief Set RMT tx loop mode.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param loop_en To enable RMT transmitter loop sending mode.
+ *
+ *                If set true, transmitter will continue sending from the first data
+ *                to the last data in channel0-7 again and again.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en);
+
+/**
+ * @brief Get RMT tx loop mode.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param loop_en Pointer to accept RMT transmitter loop sending mode.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool* loop_en);
+
+/**
+ * @brief Set RMT RX filter.
+ *
+ *        In receive mode, channel0-7 will ignore input pulse when the pulse width is smaller than threshold.
+ *        Counted in source clock, not divided counter clock.
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param rx_filter_en To enable RMT receiver filter.
+ *
+ * @param thresh Threshold of pulse width for receiver.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t thresh);
+
+/**
+ * @brief Set RMT source clock
+ *
+ *        RMT module has two source clock:
+ *        1. APB clock which is 80Mhz
+ *        2. REF tick clock, which would be 1Mhz( not supported in this version).
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param base_clk To choose source clock for RMT module.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk);
+
+/**
+ * @brief Get RMT source clock
+ *
+ *        RMT module has two source clock:
+ *        1. APB clock which is 80Mhz
+ *        2. REF tick clock, which would be 1Mhz( not supported in this version).
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param src_clk Pointer to accept source clock for RMT module.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t* src_clk);
+
+/**
+ * @brief Set RMT idle output level for transmitter
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param idle_out_en To enable idle level output.
+ *
+ * @param level To set the output signal's level for channel0-7 in idle state.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_level_t level);
+
+/**
+ * @brief Get RMT status
+ *
+ * @param channel RMT channel (0-7)
+ *
+ * @param status Pointer to accept channel status.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t* status);
+
+/**
+ * @brief Set mask value to RMT interrupt enable register.
+ *
+ * @param mask Bit mask to set to the register
+ *
+ */
+void rmt_set_intr_enable_mask(uint32_t mask);
+
+/**
+ * @brief Clear mask value to RMT interrupt enable register.
+ *
+ * @param mask Bit mask to clear the register
+ *
+ */
+void rmt_clr_intr_enable_mask(uint32_t mask);
+
+/**
+ * @brief Set RMT RX interrupt enable
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @param en enable or disable RX interrupt.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en);
+
+/**
+ * @brief Set RMT RX error interrupt enable
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @param en enable or disable RX err interrupt.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en);
+
+/**
+ * @brief Set RMT TX interrupt enable
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @param en enable or disable TX interrupt.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en);
+
+/**
+ * @brief Set RMT TX threshold event interrupt enable
+ *
+ * Causes an interrupt when a threshold number of items have been transmitted.
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @param en enable or disable TX event interrupt.
+ *
+ * @param evt_thresh RMT event interrupt threshold value
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh);
+
+/**
+ * @brief Set RMT pins
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @param mode TX or RX mode for RMT
+ *
+ * @param gpio_num GPIO number to transmit or receive the signal.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_set_pin(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num);
+
+/**
+ * @brief Configure RMT parameters
+ *
+ * @param rmt_param RMT parameter structor
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_config(const rmt_config_t* rmt_param);
+
+/**
+ * @brief   register RMT interrupt handler, the handler is an ISR.
+ *
+ *          The handler will be attached to the same CPU core that this function is running on.
+ * @note If you already called rmt_driver_install to use system RMT driver,
+ *          please do not register ISR handler again.
+ *
+ * @param fn Interrupt handler function.
+ * @param arg Parameter for handler function
+ * @param  intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+ *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
+ * @param  handle If non-zero, a handle to later clean up the ISR gets stored here.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Function pointer error.
+ *     - ESP_FAIL System driver installed, can not register ISR handler for RMT
+ */
+esp_err_t rmt_isr_register(void (* fn)(void* ), void * arg, int intr_alloc_flags, rmt_isr_handle_t *handle);
+
+/**
+ * @brief   Deregister previously registered RMT interrupt handler
+ *
+ * @param handle Handle obtained from rmt_isr_register
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Handle invalid
+ */
+esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle);
+
+/**
+ * @brief Fill memory data of channel with given RMT items.
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @param item Pointer of items.
+ *
+ * @param item_num RMT sending items number.
+ *
+ * @param mem_offset Index offset of memory.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t* item, uint16_t item_num, uint16_t mem_offset);
+
+/**
+ * @brief Initialize RMT driver
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @param rx_buf_size Size of RMT RX ringbuffer. Can be 0 if the RX ringbuffer is not used.
+ *
+ * @param intr_alloc_flags Flags for the RMT driver interrupt handler. Pass 0 for default flags. See esp_intr_alloc.h for details.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_STATE Driver is already installed, call rmt_driver_uninstall first.
+ *     - ESP_ERR_NO_MEM Memory allocation failure
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr_alloc_flags);
+
+/**
+ * @brief Uninstall RMT driver.
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_driver_uninstall(rmt_channel_t channel);
+
+/**
+ * @brief RMT send waveform from rmt_item array.
+ *
+ *        This API allows user to send waveform with any length.
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @param rmt_item head point of RMT items array.
+ *
+ * @param item_num RMT data item number.
+ *
+ * @param wait_tx_done If set 1, it will block the task and wait for sending done.
+ *
+ *                     If set 0, it will not wait and return immediately.
+ *
+ *                     @note
+ *                     This function will not copy data, instead, it will point to the original items,
+ *                     and send the waveform items.
+ *                     If wait_tx_done is set to true, this function will block and will not return until
+ *                     all items have been sent out.
+ *                     If wait_tx_done is set to false, this function will return immediately, and the driver
+ *                     interrupt will continue sending the items. We must make sure the item data will not be
+ *                     damaged when the driver is still sending items in driver interrupt.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t* rmt_item, int item_num, bool wait_tx_done);
+
+/**
+ * @brief Wait RMT TX finished.
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @param wait_time Maximum time to wait for transmission to be complete 
+ *
+ * @return
+ *     - ESP_OK RMT Tx done successfully
+ *     - ESP_ERR_TIMEOUT Crossed the 'wait_time' given
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_FAIL Driver not installed
+ */
+esp_err_t rmt_wait_tx_done(rmt_channel_t channel, int wait_time);
+
+/**
+ * @brief Get ringbuffer from UART.
+ *
+ *        Users can get the RMT RX ringbuffer handler, and process the RX data.
+ *
+ * @param channel RMT channel (0 - 7)
+ *
+ * @param buf_handle Pointer to buffer handler to accept RX ringbuffer handler.
+ *
+ * @return
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ *     - ESP_OK Success
+ */
+esp_err_t rmt_get_ringbuf_handle(rmt_channel_t channel, RingbufHandle_t* buf_handle);
+
+/***************************EXAMPLE**********************************
+ *
+ * @note
+ * You can also refer to example/09_rmt_nec_tx_rx to have more information about how to use RMT module.
+ *
+ * ----------------EXAMPLE OF RMT SETTING ---------------------
+ * @code{c}
+ * //1. enable RMT
+ * //enable RMT module, or you can not set any register of it.
+ * //this will be done in rmt_config API.
+ * periph_module_enable(PERIPH_RMT_MODULE);
+ * @endcode
+ *
+ * @code{c}
+ * //2. set RMT transmitter
+ * void rmt_tx_init()
+ * {
+ *     rmt_config_t rmt_tx;
+ *     rmt_tx.channel = 0;
+ *     rmt_tx.gpio_num = 16;
+ *     rmt_tx.mem_block_num = 1;
+ *     rmt_tx.clk_div = 100;
+ *     rmt_tx.tx_config.loop_en = false;
+ *     rmt_tx.tx_config.carrier_duty_percent = 50;
+ *     rmt_tx.tx_config.carrier_freq_hz = 38000;
+ *     rmt_tx.tx_config.carrier_level = 1;
+ *     rmt_tx.tx_config.carrier_en = RMT_TX_CARRIER_EN;
+ *     rmt_tx.tx_config.idle_level = 0;
+ *     rmt_tx.tx_config.idle_output_en = true;
+ *     rmt_tx.rmt_mode = 0;
+ *     rmt_config(&rmt_tx);
+ *
+ *     //install system RMT driver, disable rx ringbuffer for transmitter.
+ *     rmt_driver_install(rmt_tx.channel, 0, 0);
+ * }
+ *
+ * @endcode
+ * @code{c}
+ * //3. set RMT receiver
+ * void rmt_rx_init()
+ * {
+ *     rmt_config_t rmt_rx;
+ *     rmt_rx.channel = 1;
+ *     rmt_rx.gpio_num = 19;
+ *     rmt_rx.clk_div = 100;
+ *     rmt_rx.mem_block_num = 1;
+ *     rmt_rx.rmt_mode = RMT_MODE_RX;
+ *     rmt_rx.rx_config.filter_en = true;
+ *     rmt_rx.rx_config.filter_ticks_thresh = 100;
+ *     rmt_rx.rx_config.idle_threshold = 0xffff;
+ *     rmt_config(&rmt_rx);
+ *
+ *     //install system RMT driver.
+ *     rmt_driver_install(rmt_rx.channel, 1000, 0);
+ * }
+ *
+ * ----------------EXAMPLE OF RMT INTERRUPT ------------------
+ * @code{c}
+ *
+ * rmt_isr_register(rmt_isr, NULL, 0);           //hook the ISR handler for RMT interrupt
+ * @endcode
+ * @note
+ *     0. If you have called rmt_driver_install, you don't need to set ISR handler any more.
+ *
+ * ----------------EXAMPLE OF INTERRUPT HANDLER ---------------
+ * @code{c}
+ * #include "esp_attr.h"
+ * void IRAM_ATTR rmt_isr_handler(void* arg)
+ * {
+ *    //read RMT interrupt status.
+ *    uint32_t intr_st = RMT.int_st.val;
+ *
+ *    //you will find which channels have triggered fade_end interrupt here,
+ *    //then, you can post some event to RTOS queue to process the event.
+ *    //later we will add a queue in the driver code.
+ *
+ *   //clear RMT interrupt status.
+ *    RMT.int_clr.val = intr_st;
+ * }
+ * @endcode
+ *
+ *--------------------------END OF EXAMPLE --------------------------
+ */
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRIVER_RMT_CTRL_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/rtc_cntl.h

@@ -0,0 +1,48 @@
+// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "esp_intr_alloc.h"
+
+/**
+ * @brief Register a handler for specific RTC_CNTL interrupts
+ *
+ * Multiple handlers can be registered using this function. Whenever an
+ * RTC interrupt happens, all handlers with matching rtc_intr_mask values
+ * will be called.
+ *
+ * @param handler  handler function to call
+ * @param handler_arg  argument to be passed to the handler
+ * @param rtc_intr_mask  combination of RTC_CNTL_*_INT_ENA bits indicating the
+ *                       sources to call the handler for
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_NO_MEM not enough memory to allocate handler structure
+ *      - other errors returned by esp_intr_alloc
+ */
+esp_err_t rtc_isr_register(intr_handler_t handler, void* handler_arg,
+                            uint32_t rtc_intr_mask);
+/**
+ * @brief Deregister the handler previously registered using rtc_isr_register
+ * @param handler  handler function to call (as passed to rtc_isr_register)
+ * @param handler_arg  argument of the handler (as passed to rtc_isr_register)
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if a handler matching both handler and
+ *        handler_arg isn't registered
+ */
+esp_err_t rtc_isr_deregister(intr_handler_t handler, void* handler_arg);

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/rtc_io.h

@@ -0,0 +1,265 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_RTC_GPIO_H_
+#define _DRIVER_RTC_GPIO_H_
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "driver/gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Pin function information for a single GPIO pad's RTC functions.
+ *
+ * This is an internal function of the driver, and is not usually useful
+ * for external use.
+ */
+typedef struct {
+    uint32_t reg;       /*!< Register of RTC pad, or 0 if not an RTC GPIO */
+    uint32_t mux;       /*!< Bit mask for selecting digital pad or RTC pad */
+    uint32_t func;      /*!< Shift of pad function (FUN_SEL) field */
+    uint32_t ie;        /*!< Mask of input enable */
+    uint32_t pullup;    /*!< Mask of pullup enable */
+    uint32_t pulldown;  /*!< Mask of pulldown enable */
+    uint32_t slpsel;    /*!< If slpsel bit is set, slpie will be used as pad input enabled signal in sleep mode */
+    uint32_t slpie;     /*!< Mask of input enable in sleep mode */
+    uint32_t hold;      /*!< Mask of hold enable */
+    uint32_t hold_force;/*!< Mask of hold_force bit for RTC IO in RTC_CNTL_HOLD_FORCE_REG */
+    uint32_t drv_v;     /*!< Mask of drive capability */
+    uint32_t drv_s;     /*!< Offset of drive capability */
+    int rtc_num;        /*!< RTC IO number, or -1 if not an RTC GPIO */
+} rtc_gpio_desc_t;
+
+typedef enum {
+    RTC_GPIO_MODE_INPUT_ONLY , /*!< Pad output */
+    RTC_GPIO_MODE_OUTPUT_ONLY, /*!< Pad input */
+    RTC_GPIO_MODE_INPUT_OUTUT, /*!< Pad pull output + input */
+    RTC_GPIO_MODE_DISABLED,    /*!< Pad (output + input) disable */
+} rtc_gpio_mode_t;
+
+/**
+ * @brief Provides access to a constant table of RTC I/O pin
+ * function information.
+ *
+ * This is an internal function of the driver, and is not usually useful
+ * for external use.
+ */
+extern const rtc_gpio_desc_t rtc_gpio_desc[GPIO_PIN_COUNT];
+
+/**
+ * @brief Determine if the specified GPIO is a valid RTC GPIO.
+ *
+ * @param gpio_num GPIO number
+ * @return true if GPIO is valid for RTC GPIO use. talse otherwise.
+ */
+inline static bool rtc_gpio_is_valid_gpio(gpio_num_t gpio_num)
+{
+    return gpio_num < GPIO_PIN_COUNT
+        && rtc_gpio_desc[gpio_num].reg != 0;
+}
+
+#define RTC_GPIO_IS_VALID_GPIO(gpio_num) rtc_gpio_is_valid_gpio(gpio_num) // Deprecated, use rtc_gpio_is_valid_gpio()
+
+/**
+ * @brief Init a GPIO as RTC GPIO
+ *
+ * This function must be called when initializing a pad for an analog function.
+ *
+ * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+esp_err_t rtc_gpio_init(gpio_num_t gpio_num);
+
+/**
+ * @brief Init a GPIO as digital GPIO
+ *
+ * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
+ *
+ * @return
+ *     - ESP_OK success
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num);
+
+/**
+ * @brief Get the RTC IO input level
+ *
+ * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
+ *
+ * @return
+ *     - 1 High level
+ *     - 0 Low level
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+uint32_t rtc_gpio_get_level(gpio_num_t gpio_num);
+
+/**
+ * @brief Set the RTC IO output level
+ *
+ * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
+ * @param  level output level
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+esp_err_t rtc_gpio_set_level(gpio_num_t gpio_num, uint32_t level);
+
+/**
+ * @brief    RTC GPIO set direction
+ *
+ * Configure RTC GPIO direction, such as output only, input only,
+ * output and input.
+ *
+ * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
+ * @param  mode GPIO direction
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+esp_err_t rtc_gpio_set_direction(gpio_num_t gpio_num, rtc_gpio_mode_t mode);
+
+/**
+ * @brief  RTC GPIO pullup enable
+ *
+ * This function only works for RTC IOs. In general, call gpio_pullup_en,
+ * which will work both for normal GPIOs and RTC IOs.
+ *
+ * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+esp_err_t rtc_gpio_pullup_en(gpio_num_t gpio_num);
+
+/**
+ * @brief  RTC GPIO pulldown enable
+ *
+ * This function only works for RTC IOs. In general, call gpio_pulldown_en,
+ * which will work both for normal GPIOs and RTC IOs.
+ *
+ * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+esp_err_t rtc_gpio_pulldown_en(gpio_num_t gpio_num);
+
+/**
+ * @brief  RTC GPIO pullup disable
+ *
+ * This function only works for RTC IOs. In general, call gpio_pullup_dis,
+ * which will work both for normal GPIOs and RTC IOs.
+ *
+ * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+esp_err_t rtc_gpio_pullup_dis(gpio_num_t gpio_num);
+
+/**
+ * @brief  RTC GPIO pulldown disable
+ *
+ * This function only works for RTC IOs. In general, call gpio_pulldown_dis,
+ * which will work both for normal GPIOs and RTC IOs.
+ *
+ * @param  gpio_num GPIO number (e.g. GPIO_NUM_12)
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+esp_err_t rtc_gpio_pulldown_dis(gpio_num_t gpio_num);
+
+/**
+ * @brief Enable hold function on an RTC IO pad
+ *
+ * Enabling HOLD function will cause the pad to latch current values of
+ * input enable, output enable, output value, function, drive strength values.
+ * This function is useful when going into light or deep sleep mode to prevent
+ * the pin configuration from changing.
+ *
+ * @param gpio_num GPIO number (e.g. GPIO_NUM_12)
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+esp_err_t rtc_gpio_hold_en(gpio_num_t gpio_num);
+
+/**
+ * @brief Disable hold function on an RTC IO pad
+ *
+ * Disabling hold function will allow the pad receive the values of
+ * input enable, output enable, output value, function, drive strength from
+ * RTC_IO peripheral.
+ *
+ * @param gpio_num GPIO number (e.g. GPIO_NUM_12)
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG GPIO is not an RTC IO
+ */
+esp_err_t rtc_gpio_hold_dis(gpio_num_t gpio_num);
+
+/**
+ * @brief Disable force hold signal for all RTC IOs
+ *
+ * Each RTC pad has a "force hold" input signal from the RTC controller.
+ * If this signal is set, pad latches current values of input enable,
+ * function, output enable, and other signals which come from the RTC mux.
+ * Force hold signal is enabled before going into deep sleep for pins which
+ * are used for EXT1 wakeup.
+ */
+void rtc_gpio_force_hold_dis_all();
+
+/**
+  * @brief Set RTC GPIO pad drive capability
+  *
+  * @param gpio_num GPIO number, only support output GPIOs
+  * @param strength Drive capability of the pad
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t rtc_gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength);
+
+/**
+  * @brief Get RTC GPIO pad drive capability
+  *
+  * @param gpio_num GPIO number, only support output GPIOs
+  * @param strength Pointer to accept drive capability of the pad
+  *
+  * @return
+  *     - ESP_OK Success
+  *     - ESP_ERR_INVALID_ARG Parameter error
+  */
+esp_err_t rtc_gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t* strength);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/sdmmc_defs.h

@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ * Adaptations to ESP-IDF Copyright (c) 2016 Espressif Systems (Shanghai) PTE LTD
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SDMMC_DEFS_H_
+#define _SDMMC_DEFS_H_
+
+#include <stdint.h>
+#include <limits.h>
+
+/* MMC commands */                              /* response type */
+#define MMC_GO_IDLE_STATE               0       /* R0 */
+#define MMC_SEND_OP_COND                1       /* R3 */
+#define MMC_ALL_SEND_CID                2       /* R2 */
+#define MMC_SET_RELATIVE_ADDR           3       /* R1 */
+#define MMC_SWITCH                      6       /* R1B */
+#define MMC_SELECT_CARD                 7       /* R1 */
+#define MMC_SEND_EXT_CSD                8       /* R1 */
+#define MMC_SEND_CSD                    9       /* R2 */
+#define MMC_SEND_CID                    10      /* R1 */
+#define MMC_STOP_TRANSMISSION           12      /* R1B */
+#define MMC_SEND_STATUS                 13      /* R1 */
+#define MMC_SET_BLOCKLEN                16      /* R1 */
+#define MMC_READ_BLOCK_SINGLE           17      /* R1 */
+#define MMC_READ_BLOCK_MULTIPLE         18      /* R1 */
+#define MMC_SET_BLOCK_COUNT             23      /* R1 */
+#define MMC_WRITE_BLOCK_SINGLE          24      /* R1 */
+#define MMC_WRITE_BLOCK_MULTIPLE        25      /* R1 */
+#define MMC_APP_CMD                     55      /* R1 */
+
+/* SD commands */                               /* response type */
+#define SD_SEND_RELATIVE_ADDR           3       /* R6 */
+#define SD_SEND_SWITCH_FUNC             6       /* R1 */
+#define SD_SEND_IF_COND                 8       /* R7 */
+#define SD_READ_OCR                     58      /* R3 */
+#define SD_CRC_ON_OFF                   59      /* R1 */
+
+/* SD application commands */                   /* response type */
+#define SD_APP_SET_BUS_WIDTH            6       /* R1 */
+#define SD_APP_SD_STATUS                13      /* R2 */
+#define SD_APP_OP_COND                  41      /* R3 */
+#define SD_APP_SEND_SCR                 51      /* R1 */
+
+/* OCR bits */
+#define MMC_OCR_MEM_READY               (1<<31) /* memory power-up status bit */
+#define MMC_OCR_ACCESS_MODE_MASK        0x60000000 /* bits 30:29 */
+#define MMC_OCR_SECTOR_MODE             (1<<30)
+#define MMC_OCR_BYTE_MODE               (1<<29)
+#define MMC_OCR_3_5V_3_6V               (1<<23)
+#define MMC_OCR_3_4V_3_5V               (1<<22)
+#define MMC_OCR_3_3V_3_4V               (1<<21)
+#define MMC_OCR_3_2V_3_3V               (1<<20)
+#define MMC_OCR_3_1V_3_2V               (1<<19)
+#define MMC_OCR_3_0V_3_1V               (1<<18)
+#define MMC_OCR_2_9V_3_0V               (1<<17)
+#define MMC_OCR_2_8V_2_9V               (1<<16)
+#define MMC_OCR_2_7V_2_8V               (1<<15)
+#define MMC_OCR_2_6V_2_7V               (1<<14)
+#define MMC_OCR_2_5V_2_6V               (1<<13)
+#define MMC_OCR_2_4V_2_5V               (1<<12)
+#define MMC_OCR_2_3V_2_4V               (1<<11)
+#define MMC_OCR_2_2V_2_3V               (1<<10)
+#define MMC_OCR_2_1V_2_2V               (1<<9)
+#define MMC_OCR_2_0V_2_1V               (1<<8)
+#define MMC_OCR_1_65V_1_95V             (1<<7)
+
+#define SD_OCR_SDHC_CAP                 (1<<30)
+#define SD_OCR_VOL_MASK                 0xFF8000 /* bits 23:15 */
+
+/* SD mode R1 response type bits */
+#define MMC_R1_READY_FOR_DATA           (1<<8)  /* ready for next transfer */
+#define MMC_R1_APP_CMD                  (1<<5)  /* app. commands supported */
+
+/* SPI mode R1 response type bits */
+#define SD_SPI_R1_IDLE_STATE            (1<<0)
+#define SD_SPI_R1_CMD_CRC_ERR           (1<<3)
+
+/* 48-bit response decoding (32 bits w/o CRC) */
+#define MMC_R1(resp)                    ((resp)[0])
+#define MMC_R3(resp)                    ((resp)[0])
+#define SD_R6(resp)                     ((resp)[0])
+#define MMC_R1_CURRENT_STATE(resp)      (((resp)[0] >> 9) & 0xf)
+
+/* SPI mode response decoding */
+#define SD_SPI_R1(resp)                 ((resp)[0] & 0xff)
+#define SD_SPI_R2(resp)                 ((resp)[0] & 0xffff)
+#define SD_SPI_R3(resp)                 ((resp)[0])
+#define SD_SPI_R7(resp)                 ((resp)[0])
+
+/* RCA argument and response */
+#define MMC_ARG_RCA(rca)                ((rca) << 16)
+#define SD_R6_RCA(resp)                 (SD_R6((resp)) >> 16)
+
+/* bus width argument */
+#define SD_ARG_BUS_WIDTH_1              0
+#define SD_ARG_BUS_WIDTH_4              2
+
+/* EXT_CSD fields */
+#define EXT_CSD_BUS_WIDTH               183     /* WO */
+#define EXT_CSD_HS_TIMING               185     /* R/W */
+#define EXT_CSD_REV                     192     /* RO */
+#define EXT_CSD_STRUCTURE               194     /* RO */
+#define EXT_CSD_CARD_TYPE               196     /* RO */
+#define EXT_CSD_SEC_COUNT               212     /* RO */
+
+/* EXT_CSD field definitions */
+#define EXT_CSD_CMD_SET_NORMAL          (1U << 0)
+#define EXT_CSD_CMD_SET_SECURE          (1U << 1)
+#define EXT_CSD_CMD_SET_CPSECURE        (1U << 2)
+
+/* EXT_CSD_HS_TIMING */
+#define EXT_CSD_HS_TIMING_BC            0
+#define EXT_CSD_HS_TIMING_HS            1
+#define EXT_CSD_HS_TIMING_HS200         2
+#define EXT_CSD_HS_TIMING_HS400         3
+
+/* EXT_CSD_BUS_WIDTH  */
+#define EXT_CSD_BUS_WIDTH_1             0
+#define EXT_CSD_BUS_WIDTH_4             1
+#define EXT_CSD_BUS_WIDTH_8             2
+#define EXT_CSD_BUS_WIDTH_4_DDR         5
+#define EXT_CSD_BUS_WIDTH_8_DDR         6
+
+/* EXT_CSD_CARD_TYPE */
+/* The only currently valid values for this field are 0x01, 0x03, 0x07,
+ * 0x0B and 0x0F. */
+#define EXT_CSD_CARD_TYPE_F_26M         (1 << 0)
+#define EXT_CSD_CARD_TYPE_F_52M         (1 << 1)
+#define EXT_CSD_CARD_TYPE_F_52M_1_8V    (1 << 2)
+#define EXT_CSD_CARD_TYPE_F_52M_1_2V    (1 << 3)
+#define EXT_CSD_CARD_TYPE_26M           0x01
+#define EXT_CSD_CARD_TYPE_52M           0x03
+#define EXT_CSD_CARD_TYPE_52M_V18       0x07
+#define EXT_CSD_CARD_TYPE_52M_V12       0x0b
+#define EXT_CSD_CARD_TYPE_52M_V12_18    0x0f
+
+/* MMC_SWITCH access mode */
+#define MMC_SWITCH_MODE_CMD_SET         0x00    /* Change the command set */
+#define MMC_SWITCH_MODE_SET_BITS        0x01    /* Set bits in value */
+#define MMC_SWITCH_MODE_CLEAR_BITS      0x02    /* Clear bits in value */
+#define MMC_SWITCH_MODE_WRITE_BYTE      0x03    /* Set target to value */
+
+/* MMC R2 response (CSD) */
+#define MMC_CSD_CSDVER(resp)            MMC_RSP_BITS((resp), 126, 2)
+#define  MMC_CSD_CSDVER_1_0             1
+#define  MMC_CSD_CSDVER_2_0             2
+#define  MMC_CSD_CSDVER_EXT_CSD         3
+#define MMC_CSD_MMCVER(resp)            MMC_RSP_BITS((resp), 122, 4)
+#define  MMC_CSD_MMCVER_1_0             0 /* MMC 1.0 - 1.2 */
+#define  MMC_CSD_MMCVER_1_4             1 /* MMC 1.4 */
+#define  MMC_CSD_MMCVER_2_0             2 /* MMC 2.0 - 2.2 */
+#define  MMC_CSD_MMCVER_3_1             3 /* MMC 3.1 - 3.3 */
+#define  MMC_CSD_MMCVER_4_0             4 /* MMC 4 */
+#define MMC_CSD_READ_BL_LEN(resp)       MMC_RSP_BITS((resp), 80, 4)
+#define MMC_CSD_C_SIZE(resp)            MMC_RSP_BITS((resp), 62, 12)
+#define MMC_CSD_CAPACITY(resp)          ((MMC_CSD_C_SIZE((resp))+1) << \
+                                         (MMC_CSD_C_SIZE_MULT((resp))+2))
+#define MMC_CSD_C_SIZE_MULT(resp)       MMC_RSP_BITS((resp), 47, 3)
+
+/* MMC v1 R2 response (CID) */
+#define MMC_CID_MID_V1(resp)            MMC_RSP_BITS((resp), 104, 24)
+#define MMC_CID_PNM_V1_CPY(resp, pnm)                                   \
+        do {                                                            \
+                (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
+                (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
+                (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
+                (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
+                (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
+                (pnm)[5] = MMC_RSP_BITS((resp), 56, 8);                 \
+                (pnm)[6] = MMC_RSP_BITS((resp), 48, 8);                 \
+                (pnm)[7] = '\0';                                        \
+        } while (0)
+#define MMC_CID_REV_V1(resp)            MMC_RSP_BITS((resp), 40, 8)
+#define MMC_CID_PSN_V1(resp)            MMC_RSP_BITS((resp), 16, 24)
+#define MMC_CID_MDT_V1(resp)            MMC_RSP_BITS((resp), 8, 8)
+
+/* MMC v2 R2 response (CID) */
+#define MMC_CID_MID_V2(resp)            MMC_RSP_BITS((resp), 120, 8)
+#define MMC_CID_OID_V2(resp)            MMC_RSP_BITS((resp), 104, 16)
+#define MMC_CID_PNM_V2_CPY(resp, pnm)                                   \
+        do {                                                            \
+                (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
+                (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
+                (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
+                (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
+                (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
+                (pnm)[5] = MMC_RSP_BITS((resp), 56, 8);                 \
+                (pnm)[6] = '\0';                                        \
+        } while (0)
+#define MMC_CID_PSN_V2(resp)            MMC_RSP_BITS((resp), 16, 32)
+
+/* SD R2 response (CSD) */
+#define SD_CSD_CSDVER(resp)             MMC_RSP_BITS((resp), 126, 2)
+#define  SD_CSD_CSDVER_1_0              0
+#define  SD_CSD_CSDVER_2_0              1
+#define SD_CSD_TAAC(resp)               MMC_RSP_BITS((resp), 112, 8)
+#define  SD_CSD_TAAC_1_5_MSEC           0x26
+#define SD_CSD_NSAC(resp)               MMC_RSP_BITS((resp), 104, 8)
+#define SD_CSD_SPEED(resp)              MMC_RSP_BITS((resp), 96, 8)
+#define  SD_CSD_SPEED_25_MHZ            0x32
+#define  SD_CSD_SPEED_50_MHZ            0x5a
+#define SD_CSD_CCC(resp)                MMC_RSP_BITS((resp), 84, 12)
+#define  SD_CSD_CCC_BASIC               (1 << 0)        /* basic */
+#define  SD_CSD_CCC_BR                  (1 << 2)        /* block read */
+#define  SD_CSD_CCC_BW                  (1 << 4)        /* block write */
+#define  SD_CSD_CCC_ERASE               (1 << 5)        /* erase */
+#define  SD_CSD_CCC_WP                  (1 << 6)        /* write protection */
+#define  SD_CSD_CCC_LC                  (1 << 7)        /* lock card */
+#define  SD_CSD_CCC_AS                  (1 << 8)        /*application specific*/
+#define  SD_CSD_CCC_IOM                 (1 << 9)        /* I/O mode */
+#define  SD_CSD_CCC_SWITCH              (1 << 10)       /* switch */
+#define SD_CSD_READ_BL_LEN(resp)        MMC_RSP_BITS((resp), 80, 4)
+#define SD_CSD_READ_BL_PARTIAL(resp)    MMC_RSP_BITS((resp), 79, 1)
+#define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
+#define SD_CSD_READ_BLK_MISALIGN(resp)  MMC_RSP_BITS((resp), 77, 1)
+#define SD_CSD_DSR_IMP(resp)            MMC_RSP_BITS((resp), 76, 1)
+#define SD_CSD_C_SIZE(resp)             MMC_RSP_BITS((resp), 62, 12)
+#define SD_CSD_CAPACITY(resp)           ((SD_CSD_C_SIZE((resp))+1) << \
+                                         (SD_CSD_C_SIZE_MULT((resp))+2))
+#define SD_CSD_V2_C_SIZE(resp)          MMC_RSP_BITS((resp), 48, 22)
+#define SD_CSD_V2_CAPACITY(resp)        ((SD_CSD_V2_C_SIZE((resp))+1) << 10) 
+#define SD_CSD_V2_BL_LEN                0x9     /* 512 */
+#define SD_CSD_VDD_R_CURR_MIN(resp)     MMC_RSP_BITS((resp), 59, 3)
+#define SD_CSD_VDD_R_CURR_MAX(resp)     MMC_RSP_BITS((resp), 56, 3)
+#define SD_CSD_VDD_W_CURR_MIN(resp)     MMC_RSP_BITS((resp), 53, 3)
+#define SD_CSD_VDD_W_CURR_MAX(resp)     MMC_RSP_BITS((resp), 50, 3)
+#define  SD_CSD_VDD_RW_CURR_100mA       0x7
+#define  SD_CSD_VDD_RW_CURR_80mA        0x6
+#define SD_CSD_C_SIZE_MULT(resp)        MMC_RSP_BITS((resp), 47, 3)
+#define SD_CSD_ERASE_BLK_EN(resp)       MMC_RSP_BITS((resp), 46, 1)
+#define SD_CSD_SECTOR_SIZE(resp)        MMC_RSP_BITS((resp), 39, 7) /* +1 */
+#define SD_CSD_WP_GRP_SIZE(resp)        MMC_RSP_BITS((resp), 32, 7) /* +1 */
+#define SD_CSD_WP_GRP_ENABLE(resp)      MMC_RSP_BITS((resp), 31, 1)
+#define SD_CSD_R2W_FACTOR(resp)         MMC_RSP_BITS((resp), 26, 3)
+#define SD_CSD_WRITE_BL_LEN(resp)       MMC_RSP_BITS((resp), 22, 4)
+#define  SD_CSD_RW_BL_LEN_2G            0xa
+#define  SD_CSD_RW_BL_LEN_1G            0x9
+#define SD_CSD_WRITE_BL_PARTIAL(resp)   MMC_RSP_BITS((resp), 21, 1)
+#define SD_CSD_FILE_FORMAT_GRP(resp)    MMC_RSP_BITS((resp), 15, 1)
+#define SD_CSD_COPY(resp)               MMC_RSP_BITS((resp), 14, 1)
+#define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
+#define SD_CSD_TMP_WRITE_PROTECT(resp)  MMC_RSP_BITS((resp), 12, 1)
+#define SD_CSD_FILE_FORMAT(resp)        MMC_RSP_BITS((resp), 10, 2)
+
+/* SD R2 response (CID) */
+#define SD_CID_MID(resp)                MMC_RSP_BITS((resp), 120, 8)
+#define SD_CID_OID(resp)                MMC_RSP_BITS((resp), 104, 16)
+#define SD_CID_PNM_CPY(resp, pnm)                                       \
+        do {                                                            \
+                (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
+                (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
+                (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
+                (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
+                (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
+                (pnm)[5] = '\0';                                        \
+        } while (0)
+#define SD_CID_REV(resp)                MMC_RSP_BITS((resp), 56, 8)
+#define SD_CID_PSN(resp)                MMC_RSP_BITS((resp), 24, 32)
+#define SD_CID_MDT(resp)                MMC_RSP_BITS((resp), 8, 12)
+
+/* SCR (SD Configuration Register) */
+#define SCR_STRUCTURE(scr)              MMC_RSP_BITS((scr), 60, 4)
+#define  SCR_STRUCTURE_VER_1_0          0 /* Version 1.0 */
+#define SCR_SD_SPEC(scr)                MMC_RSP_BITS((scr), 56, 4)
+#define  SCR_SD_SPEC_VER_1_0            0 /* Version 1.0 and 1.01 */
+#define  SCR_SD_SPEC_VER_1_10           1 /* Version 1.10 */
+#define  SCR_SD_SPEC_VER_2              2 /* Version 2.00 or Version 3.0X */
+#define SCR_DATA_STAT_AFTER_ERASE(scr)  MMC_RSP_BITS((scr), 55, 1)
+#define SCR_SD_SECURITY(scr)            MMC_RSP_BITS((scr), 52, 3)
+#define  SCR_SD_SECURITY_NONE           0 /* no security */
+#define  SCR_SD_SECURITY_1_0            1 /* security protocol 1.0 */
+#define  SCR_SD_SECURITY_1_0_2          2 /* security protocol 1.0 */
+#define SCR_SD_BUS_WIDTHS(scr)          MMC_RSP_BITS((scr), 48, 4)
+#define  SCR_SD_BUS_WIDTHS_1BIT         (1 << 0) /* 1bit (DAT0) */
+#define  SCR_SD_BUS_WIDTHS_4BIT         (1 << 2) /* 4bit (DAT0-3) */
+#define SCR_SD_SPEC3(scr)               MMC_RSP_BITS((scr), 47, 1)
+#define SCR_EX_SECURITY(scr)            MMC_RSP_BITS((scr), 43, 4)
+#define SCR_SD_SPEC4(scr)               MMC_RSP_BITS((scr), 42, 1)
+#define SCR_RESERVED(scr)               MMC_RSP_BITS((scr), 34, 8)
+#define SCR_CMD_SUPPORT_CMD23(scr)      MMC_RSP_BITS((scr), 33, 1)
+#define SCR_CMD_SUPPORT_CMD20(scr)      MMC_RSP_BITS((scr), 32, 1)
+#define SCR_RESERVED2(scr)              MMC_RSP_BITS((scr), 0, 32)
+
+/* Max supply current in SWITCH_FUNC response (in mA) */
+#define SD_SFUNC_I_MAX(status) (MMC_RSP_BITS((uint32_t *)(status), 496, 16))
+
+/* Supported flags in SWITCH_FUNC response */
+#define SD_SFUNC_SUPPORTED(status, group) \
+        (MMC_RSP_BITS((uint32_t *)(status), 400 + (group - 1) * 16, 16))
+
+/* Selected function in SWITCH_FUNC response */
+#define SD_SFUNC_SELECTED(status, group) \
+        (MMC_RSP_BITS((uint32_t *)(status), 376 + (group - 1) * 4, 4))
+
+/* Busy flags in SWITCH_FUNC response */
+#define SD_SFUNC_BUSY(status, group) \
+        (MMC_RSP_BITS((uint32_t *)(status), 272 + (group - 1) * 16, 16))
+
+/* Version of SWITCH_FUNC response */
+#define SD_SFUNC_VER(status)    (MMC_RSP_BITS((uint32_t *)(status), 368, 8))
+
+#define SD_SFUNC_GROUP_MAX      6
+#define SD_SFUNC_FUNC_MAX       15
+
+#define SD_ACCESS_MODE          1       /* Function group 1, Access Mode */
+
+#define SD_ACCESS_MODE_SDR12    0       /* 25 MHz clock */
+#define SD_ACCESS_MODE_SDR25    1       /* 50 MHz clock */
+#define SD_ACCESS_MODE_SDR50    2       /* UHS-I, 100 MHz clock */
+#define SD_ACCESS_MODE_SDR104   3       /* UHS-I, 208 MHz clock */
+#define SD_ACCESS_MODE_DDR50    4       /* UHS-I, 50 MHz clock, DDR */
+
+/**
+ * @brief Extract up to 32 sequential bits from an array of 32-bit words
+ *
+ * Bits within the word are numbered in the increasing order from LSB to MSB.
+ *
+ * As an example, consider 2 32-bit words:
+ *
+ * 0x01234567 0x89abcdef
+ *
+ * On a little-endian system, the bytes are stored in memory as follows:
+ *
+ * 67 45 23 01 ef cd ab 89
+ *
+ * MMC_RSP_BITS will extact bits as follows:
+ *
+ * start=0  len=4   -> result=0x00000007
+ * start=0  len=12  -> result=0x00000567
+ * start=28 len=8   -> result=0x000000f0
+ * start=59 len=5   -> result=0x00000011
+ *
+ * @param src array of words to extract bits from
+ * @param start index of the first bit to extract
+ * @param len number of bits to extract, 1 to 32
+ * @return 32-bit word where requested bits start from LSB
+ */
+static inline uint32_t MMC_RSP_BITS(uint32_t *src, int start, int len)
+{
+    uint32_t mask = (len % 32 == 0) ? UINT_MAX : UINT_MAX >> (32 - (len % 32));
+    size_t word = start / 32;
+    size_t shift = start % 32;
+    uint32_t right = src[word] >> shift;
+    uint32_t left = (len + shift <= 32) ? 0 : src[word + 1] << ((32 - shift) % 32);
+    return (left | right) & mask;
+}
+
+#endif //_SDMMC_DEFS_H_

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/sdmmc_host.h

@@ -0,0 +1,172 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include <stdint.h>
+#include <stddef.h>
+#include "esp_err.h"
+#include "sdmmc_types.h"
+#include "driver/gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SDMMC_HOST_SLOT_0     0     ///< SDMMC slot 0
+#define SDMMC_HOST_SLOT_1     1     ///< SDMMC slot 1
+
+/**
+ * @brief Default sdmmc_host_t structure initializer for SDMMC peripheral
+ *
+ * Uses SDMMC peripheral, with 4-bit mode enabled, and max frequency set to 20MHz
+ */
+#define SDMMC_HOST_DEFAULT() {\
+    .flags = SDMMC_HOST_FLAG_4BIT, \
+    .slot = SDMMC_HOST_SLOT_1, \
+    .max_freq_khz = SDMMC_FREQ_DEFAULT, \
+    .io_voltage = 3.3f, \
+    .init = &sdmmc_host_init, \
+    .set_bus_width = &sdmmc_host_set_bus_width, \
+    .set_card_clk = &sdmmc_host_set_card_clk, \
+    .do_transaction = &sdmmc_host_do_transaction, \
+    .deinit = &sdmmc_host_deinit, \
+}
+
+/**
+ * Extra configuration for SDMMC peripheral slot
+ */
+typedef struct {
+    gpio_num_t gpio_cd;     ///< GPIO number of card detect signal
+    gpio_num_t gpio_wp;     ///< GPIO number of write protect signal
+    uint8_t width;          ///< Bus width used by the slot (might be less than the max width supported)
+} sdmmc_slot_config_t;
+
+#define SDMMC_SLOT_NO_CD      ((gpio_num_t) -1)     ///< indicates that card detect line is not used
+#define SDMMC_SLOT_NO_WP      ((gpio_num_t) -1)     ///< indicates that write protect line is not used
+#define SDMMC_SLOT_WIDTH_DEFAULT 0 ///< use the default width for the slot (8 for slot 0, 4 for slot 1)
+
+/**
+ * Macro defining default configuration of SDMMC host slot
+ */
+#define SDMMC_SLOT_CONFIG_DEFAULT() {\
+    .gpio_cd = SDMMC_SLOT_NO_CD, \
+    .gpio_wp = SDMMC_SLOT_NO_WP, \
+    .width   = SDMMC_SLOT_WIDTH_DEFAULT, \
+}
+
+/**
+ * @brief Initialize SDMMC host peripheral
+ *
+ * @note This function is not thread safe
+ *
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if sdmmc_host_init was already called
+ *      - ESP_ERR_NO_MEM if memory can not be allocated
+ */
+esp_err_t sdmmc_host_init();
+
+/**
+ * @brief Initialize given slot of SDMMC peripheral
+ *
+ * On the ESP32, SDMMC peripheral has two slots:
+ *  - Slot 0: 8-bit wide, maps to HS1_* signals in PIN MUX
+ *  - Slot 1: 4-bit wide, maps to HS2_* signals in PIN MUX
+ *
+ * Card detect and write protect signals can be routed to
+ * arbitrary GPIOs using GPIO matrix.
+ *
+ * @note This function is not thread safe
+ *
+ * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
+ * @param slot_config  additional configuration for the slot
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if host has not been initialized using sdmmc_host_init
+ */
+esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t* slot_config);
+
+/**
+ * @brief Select bus width to be used for data transfer
+ *
+ * SD/MMC card must be initialized prior to this command, and a command to set
+ * bus width has to be sent to the card (e.g. SD_APP_SET_BUS_WIDTH)
+ *
+ * @note This function is not thread safe
+ *
+ * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
+ * @param width  bus width (1, 4, or 8 for slot 0; 1 or 4 for slot 1)
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if slot number or width is not valid
+ */
+esp_err_t sdmmc_host_set_bus_width(int slot, size_t width);
+
+/**
+ * @brief Set card clock frequency
+ *
+ * Currently only integer fractions of 40MHz clock can be used.
+ * For High Speed cards, 40MHz can be used.
+ * For Default Speed cards, 20MHz can be used.
+ *
+ * @note This function is not thread safe
+ *
+ * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
+ * @param freq_khz  card clock frequency, in kHz
+ * @return
+ *      - ESP_OK on success
+ *      - other error codes may be returned in the future
+ */
+esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz);
+
+/**
+ * @brief Send command to the card and get response
+ *
+ * This function returns when command is sent and response is received,
+ * or data is transferred, or timeout occurs.
+ *
+ * @note This function is not thread safe w.r.t. init/deinit functions,
+ *       and bus width/clock speed configuration functions. Multiple tasks
+ *       can call sdmmc_host_do_transaction as long as other sdmmc_host_*
+ *       functions are not called.
+ *
+ * @attention Data buffer passed in cmdinfo->data must be in DMA capable memory
+ *
+ * @param slot  slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1)
+ * @param cmdinfo   pointer to structure describing command and data to transfer
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_TIMEOUT if response or data transfer has timed out
+ *      - ESP_ERR_INVALID_CRC if response or data transfer CRC check has failed
+ *      - ESP_ERR_INVALID_RESPONSE if the card has sent an invalid response
+ *      - ESP_ERR_INVALID_SIZE if the size of data transfer is not valid in SD protocol
+ *      - ESP_ERR_INVALID_ARG if the data buffer is not in DMA capable memory
+ */
+esp_err_t sdmmc_host_do_transaction(int slot, sdmmc_command_t* cmdinfo);
+
+/**
+ * @brief Disable SDMMC host and release allocated resources
+ *
+ * @note This function is not thread safe
+ *
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if sdmmc_host_init function has not been called
+ */
+esp_err_t sdmmc_host_deinit();
+
+#ifdef __cplusplus
+}
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/sdmmc_types.h

@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
+ * Adaptations to ESP-IDF Copyright (c) 2016 Espressif Systems (Shanghai) PTE LTD
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SDMMC_TYPES_H_
+#define _SDMMC_TYPES_H_
+
+#include <stdint.h>
+#include <stddef.h>
+#include "esp_err.h"
+
+/**
+ * Decoded values from SD card Card Specific Data register
+ */
+typedef struct {
+    int csd_ver;                /*!< CSD structure format */
+    int mmc_ver;                /*!< MMC version (for CID format) */
+    int capacity;               /*!< total number of sectors */
+    int sector_size;            /*!< sector size in bytes */
+    int read_block_len;         /*!< block length for reads */
+    int card_command_class;     /*!< Card Command Class for SD */
+    int tr_speed;               /*!< Max transfer speed */
+} sdmmc_csd_t;
+
+/**
+ * Decoded values from SD card Card IDentification register
+ */
+typedef struct {
+    int mfg_id;     /*!< manufacturer identification number */
+    int oem_id;     /*!< OEM/product identification number */
+    char name[8];   /*!< product name (MMC v1 has the longest) */
+    int revision;   /*!< product revision */
+    int serial;     /*!< product serial number */
+    int date;       /*!< manufacturing date */
+} sdmmc_cid_t;
+
+/**
+ * Decoded values from SD Configuration Register
+ */
+typedef struct {
+    int sd_spec;    /*!< SD Physical layer specification version, reported by card */
+    int bus_width;  /*!< bus widths supported by card: BIT(0) — 1-bit bus, BIT(2) — 4-bit bus */
+} sdmmc_scr_t;
+
+/**
+ * SD/MMC command response buffer
+ */
+typedef uint32_t sdmmc_response_t[4];
+
+/**
+ * SD SWITCH_FUNC response buffer
+ */
+typedef struct {
+    uint32_t data[512 / 8 / sizeof(uint32_t)];  /*!< response data */
+} sdmmc_switch_func_rsp_t;
+
+/**
+ * SD/MMC command information
+ */
+typedef struct {
+        uint32_t opcode;            /*!< SD or MMC command index */
+        uint32_t arg;               /*!< SD/MMC command argument */
+        sdmmc_response_t response;  /*!< response buffer */
+        void* data;                 /*!< buffer to send or read into */
+        size_t datalen;             /*!< length of data buffer */
+        size_t blklen;              /*!< block length */
+        int flags;                  /*!< see below */
+#define SCF_ITSDONE      0x0001     /*!< command is complete */
+#define SCF_CMD(flags)   ((flags) & 0x00f0)
+#define SCF_CMD_AC       0x0000
+#define SCF_CMD_ADTC     0x0010
+#define SCF_CMD_BC       0x0020
+#define SCF_CMD_BCR      0x0030
+#define SCF_CMD_READ     0x0040     /*!< read command (data expected) */
+#define SCF_RSP_BSY      0x0100
+#define SCF_RSP_136      0x0200
+#define SCF_RSP_CRC      0x0400
+#define SCF_RSP_IDX      0x0800
+#define SCF_RSP_PRESENT  0x1000
+/* response types */
+#define SCF_RSP_R0       0 /*!< none */
+#define SCF_RSP_R1       (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
+#define SCF_RSP_R1B      (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
+#define SCF_RSP_R2       (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_136)
+#define SCF_RSP_R3       (SCF_RSP_PRESENT)
+#define SCF_RSP_R4       (SCF_RSP_PRESENT)
+#define SCF_RSP_R5       (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
+#define SCF_RSP_R5B      (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX|SCF_RSP_BSY)
+#define SCF_RSP_R6       (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
+#define SCF_RSP_R7       (SCF_RSP_PRESENT|SCF_RSP_CRC|SCF_RSP_IDX)
+        esp_err_t error;            /*!< error returned from transfer */
+} sdmmc_command_t;
+
+/**
+ * SD/MMC Host description
+ *
+ * This structure defines properties of SD/MMC host and functions
+ * of SD/MMC host which can be used by upper layers.
+ */
+typedef struct {
+    uint32_t flags;             /*!< flags defining host properties */
+#define SDMMC_HOST_FLAG_1BIT    BIT(0)      /*!< host supports 1-line SD and MMC protocol */
+#define SDMMC_HOST_FLAG_4BIT    BIT(1)      /*!< host supports 4-line SD and MMC protocol */
+#define SDMMC_HOST_FLAG_8BIT    BIT(2)      /*!< host supports 8-line MMC protocol */
+#define SDMMC_HOST_FLAG_SPI     BIT(3)      /*!< host supports SPI protocol */
+    int slot;                   /*!< slot number, to be passed to host functions */
+    int max_freq_khz;           /*!< max frequency supported by the host */
+#define SDMMC_FREQ_DEFAULT      20000       /*!< SD/MMC Default speed (limited by clock divider) */
+#define SDMMC_FREQ_HIGHSPEED    40000       /*!< SD High speed (limited by clock divider) */
+#define SDMMC_FREQ_PROBING      400         /*!< SD/MMC probing speed */
+    float io_voltage;           /*!< I/O voltage used by the controller (voltage switching is not supported) */
+    esp_err_t (*init)(void);    /*!< Host function to initialize the driver */
+    esp_err_t (*set_bus_width)(int slot, size_t width);    /*!< host function to set bus width */
+    esp_err_t (*set_card_clk)(int slot, uint32_t freq_khz); /*!< host function to set card clock frequency */
+    esp_err_t (*do_transaction)(int slot, sdmmc_command_t* cmdinfo);    /*!< host function to do a transaction */
+    esp_err_t (*deinit)(void);  /*!< host function to deinitialize the driver */
+} sdmmc_host_t;
+
+/**
+ * SD/MMC card information structure
+ */
+typedef struct {
+    sdmmc_host_t host;          /*!< Host with which the card is associated */
+    uint32_t ocr;               /*!< OCR (Operation Conditions Register) value */
+    sdmmc_cid_t cid;            /*!< decoded CID (Card IDentification) register value */
+    sdmmc_csd_t csd;            /*!< decoded CSD (Card-Specific Data) register value */
+    sdmmc_scr_t scr;            /*!< decoded SCR (SD card Configuration Register) value */
+    uint16_t rca;               /*!< RCA (Relative Card Address) */
+} sdmmc_card_t;
+
+
+
+
+#endif // _SDMMC_TYPES_H_

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/sdspi_host.h

@@ -0,0 +1,156 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include <stdint.h>
+#include <stddef.h>
+#include "esp_err.h"
+#include "sdmmc_types.h"
+#include "driver/gpio.h"
+#include "driver/spi_master.h"
+#include "driver/sdmmc_host.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Default sdmmc_host_t structure initializer for SD over SPI driver
+ *
+ * Uses SPI mode and max frequency set to 20MHz
+ *
+ * 'slot' can be set to one of HSPI_HOST, VSPI_HOST.
+ */
+#define SDSPI_HOST_DEFAULT() {\
+    .flags = SDMMC_HOST_FLAG_SPI, \
+    .slot = HSPI_HOST, \
+    .max_freq_khz = SDMMC_FREQ_DEFAULT, \
+    .io_voltage = 3.3f, \
+    .init = &sdspi_host_init, \
+    .set_bus_width = NULL, \
+    .set_card_clk = &sdspi_host_set_card_clk, \
+    .do_transaction = &sdspi_host_do_transaction, \
+    .deinit = &sdspi_host_deinit, \
+}
+
+/**
+ * Extra configuration for SPI host
+ */
+typedef struct {
+    gpio_num_t gpio_miso;   ///< GPIO number of MISO signal
+    gpio_num_t gpio_mosi;   ///< GPIO number of MOSI signal
+    gpio_num_t gpio_sck;    ///< GPIO number of SCK signal
+    gpio_num_t gpio_cs;     ///< GPIO number of CS signal
+    gpio_num_t gpio_cd;     ///< GPIO number of card detect signal
+    gpio_num_t gpio_wp;     ///< GPIO number of write protect signal
+    int dma_channel;        ///< DMA channel to be used by SPI driver (1 or 2)
+} sdspi_slot_config_t;
+
+#define SDSPI_SLOT_NO_CD    ((gpio_num_t) -1)   ///< indicates that card detect line is not used
+#define SDSPI_SLOT_NO_WP    ((gpio_num_t) -1)   ///< indicates that write protect line is not used
+
+/**
+ * Macro defining default configuration of SPI host
+ */
+#define SDSPI_SLOT_CONFIG_DEFAULT() {\
+    .gpio_miso = GPIO_NUM_2, \
+    .gpio_mosi = GPIO_NUM_15, \
+    .gpio_sck  = GPIO_NUM_14, \
+    .gpio_cs   = GPIO_NUM_13, \
+    .gpio_cd   = SDMMC_SLOT_NO_CD, \
+    .gpio_wp   = SDMMC_SLOT_NO_WP, \
+    .dma_channel = 1 \
+}
+
+/**
+ * @brief Initialize SD SPI driver
+ *
+ * @note This function is not thread safe
+ *
+ * @return
+ *      - ESP_OK on success
+ *      - other error codes may be returned in future versions
+ */
+esp_err_t sdspi_host_init();
+
+/**
+* @brief Initialize SD SPI driver for the specific SPI controller
+*
+* @note This function is not thread safe
+*
+* @param slot         SPI controller to use (HSPI_HOST or VSPI_HOST)
+* @param slot_config  pointer to slot configuration structure
+*
+* @return
+*      - ESP_OK on success
+*      - ESP_ERR_INVALID_ARG if sdspi_init_slot has invalid arguments
+*      - ESP_ERR_NO_MEM if memory can not be allocated
+*      - other errors from the underlying spi_master and gpio drivers
+*/
+esp_err_t sdspi_host_init_slot(int slot, const sdspi_slot_config_t* slot_config);
+
+/**
+ * @brief Send command to the card and get response
+ *
+ * This function returns when command is sent and response is received,
+ * or data is transferred, or timeout occurs.
+ *
+ * @note This function is not thread safe w.r.t. init/deinit functions,
+ *       and bus width/clock speed configuration functions. Multiple tasks
+ *       can call sdspi_host_do_transaction as long as other sdspi_host_*
+ *       functions are not called.
+ *
+ * @param slot      SPI controller (HSPI_HOST or VSPI_HOST)
+ * @param cmdinfo   pointer to structure describing command and data to transfer
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_TIMEOUT if response or data transfer has timed out
+ *      - ESP_ERR_INVALID_CRC if response or data transfer CRC check has failed
+ *      - ESP_ERR_INVALID_RESPONSE if the card has sent an invalid response
+ */
+esp_err_t sdspi_host_do_transaction(int slot, sdmmc_command_t *cmdinfo);
+
+/**
+ * @brief Set card clock frequency
+ *
+ * Currently only integer fractions of 40MHz clock can be used.
+ * For High Speed cards, 40MHz can be used.
+ * For Default Speed cards, 20MHz can be used.
+ *
+ * @note This function is not thread safe
+ *
+ * @param slot      SPI controller (HSPI_HOST or VSPI_HOST)
+ * @param freq_khz  card clock frequency, in kHz
+ * @return
+ *      - ESP_OK on success
+ *      - other error codes may be returned in the future
+ */
+esp_err_t sdspi_host_set_card_clk(int slot, uint32_t freq_khz);
+
+
+/**
+ * @brief Release resources allocated using sdspi_host_init
+ *
+ * @note This function is not thread safe
+ *
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if sdspi_host_init function has not been called
+ */
+esp_err_t sdspi_host_deinit();
+
+#ifdef __cplusplus
+}
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/sigmadelta.h

@@ -0,0 +1,108 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __DRIVER_SIGMADELTA_H__
+#define __DRIVER_SIGMADELTA_H__
+#include <esp_types.h>
+#include "soc/gpio_sd_struct.h"
+#include "soc/gpio_sd_reg.h"
+#include "driver/gpio.h"
+
+#ifdef _cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Sigma-delta channel list
+ */
+typedef enum{
+    SIGMADELTA_CHANNEL_0 = 0,         /*!< Sigma-delta channel0 */
+    SIGMADELTA_CHANNEL_1 = 1,         /*!< Sigma-delta channel1 */
+    SIGMADELTA_CHANNEL_2 = 2,         /*!< Sigma-delta channel2 */
+    SIGMADELTA_CHANNEL_3 = 3,         /*!< Sigma-delta channel3 */
+    SIGMADELTA_CHANNEL_4 = 4,         /*!< Sigma-delta channel4 */
+    SIGMADELTA_CHANNEL_5 = 5,         /*!< Sigma-delta channel5 */
+    SIGMADELTA_CHANNEL_6 = 6,         /*!< Sigma-delta channel6 */
+    SIGMADELTA_CHANNEL_7 = 7,         /*!< Sigma-delta channel7 */
+    SIGMADELTA_CHANNEL_MAX,
+} sigmadelta_channel_t;
+
+/**
+ * @brief Sigma-delta configure struct
+ */
+typedef struct {
+    sigmadelta_channel_t channel;    /*!< Sigma-delta channel number */
+    int8_t sigmadelta_duty;          /*!< Sigma-delta duty, duty ranges from -128 to 127. */
+    uint8_t sigmadelta_prescale;     /*!< Sigma-delta prescale, prescale ranges from 0 to 255. */
+    uint8_t  sigmadelta_gpio;        /*!< Sigma-delta output io number, refer to gpio.h for more details. */
+} sigmadelta_config_t;
+
+/**
+ * @brief Configure Sigma-delta channel
+ *
+ * @param  config Pointer of Sigma-delta channel configuration struct
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t sigmadelta_config(const sigmadelta_config_t *config);
+
+/**
+ * @brief Set Sigma-delta channel duty.
+ *
+ *        This function is used to set Sigma-delta channel duty,
+ *        If you add a capacitor between the output pin and ground,
+ *        the average output voltage Vdc = VDDIO / 256 * duty + VDDIO/2, VDDIO is power supply voltage.
+ *
+ * @param channel Sigma-delta channel number
+ * @param duty Sigma-delta duty of one channel, the value ranges from -128 to 127, recommended range is -90 ~ 90.
+ *             The waveform is more like a random one in this range.
+ *                                
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t sigmadelta_set_duty(sigmadelta_channel_t channel, int8_t duty);
+
+/**
+ * @brief Set Sigma-delta channel's clock pre-scale value.
+ *        The source clock is APP_CLK, 80MHz. The clock frequency of the sigma-delta channel is APP_CLK / pre_scale
+ *
+ * @param channel Sigma-delta channel number
+ * @param prescale The divider of source clock, ranges from 0 to 255
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t sigmadelta_set_prescale(sigmadelta_channel_t channel, uint8_t prescale);
+
+/**
+ * @brief Set Sigma-delta signal output pin
+ *
+ * @param channel Sigma-delta channel number
+ * @param gpio_num GPIO number of output pin.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t sigmadelta_set_pin(sigmadelta_channel_t channel, gpio_num_t gpio_num);
+
+#ifdef _cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/spi_common.h

@@ -0,0 +1,251 @@
+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef _DRIVER_SPI_COMMON_H_
+#define _DRIVER_SPI_COMMON_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_err.h"
+#include "soc/spi_struct.h"
+#include "rom/lldesc.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+//Maximum amount of bytes that can be put in one DMA descriptor
+#define SPI_MAX_DMA_LEN (4096-4)
+
+
+/**
+ * @brief Enum with the three SPI peripherals that are software-accessible in it
+ */
+typedef enum {
+    SPI_HOST=0,                     ///< SPI1, SPI
+    HSPI_HOST=1,                    ///< SPI2, HSPI
+    VSPI_HOST=2                     ///< SPI3, VSPI
+} spi_host_device_t;
+
+/**
+ * @brief This is a configuration structure for a SPI bus.
+ *
+ * You can use this structure to specify the GPIO pins of the bus. Normally, the driver will use the
+ * GPIO matrix to route the signals. An exception is made when all signals either can be routed through 
+ * the IO_MUX or are -1. In that case, the IO_MUX is used, allowing for >40MHz speeds.
+ *
+ * @note Be advised that the slave driver does not use the quadwp/quadhd lines and fields in spi_bus_config_t refering to these lines will be ignored and can thus safely be left uninitialized.
+ */
+typedef struct {
+    int mosi_io_num;                ///< GPIO pin for Master Out Slave In (=spi_d) signal, or -1 if not used.
+    int miso_io_num;                ///< GPIO pin for Master In Slave Out (=spi_q) signal, or -1 if not used.
+    int sclk_io_num;                ///< GPIO pin for Spi CLocK signal, or -1 if not used.
+    int quadwp_io_num;              ///< GPIO pin for WP (Write Protect) signal which is used as D2 in 4-bit communication modes, or -1 if not used.
+    int quadhd_io_num;              ///< GPIO pin for HD (HolD) signal which is used as D3 in 4-bit communication modes, or -1 if not used.
+    int max_transfer_sz;            ///< Maximum transfer size, in bytes. Defaults to 4094 if 0.
+} spi_bus_config_t;
+
+
+/**
+ * @brief Try to claim a SPI peripheral
+ *
+ * Call this if your driver wants to manage a SPI peripheral.
+ *
+ * @param host Peripheral to claim
+ * @return True if peripheral is claimed successfully; false if peripheral already is claimed.
+ */
+bool spicommon_periph_claim(spi_host_device_t host);
+
+/**
+ * @brief Return the SPI peripheral so another driver can claim it.
+ *
+ * @param host Peripheral to return
+ * @return True if peripheral is returned successfully; false if peripheral was free to claim already.
+ */
+bool spicommon_periph_free(spi_host_device_t host);
+
+/**
+ * @brief Try to claim a SPI DMA channel
+ * 
+ *  Call this if your driver wants to use SPI with a DMA channnel.
+ * 
+ * @param dma_chan channel to claim
+ * 
+ * @return True if success; false otherwise.
+ */
+bool spicommon_dma_chan_claim(int dma_chan);
+
+/**
+ * @brief Return the SPI DMA channel so other driver can claim it, or just to power down DMA.
+ * 
+ * @param dma_chan channel to return
+ * 
+ * @return True if success; false otherwise.
+ */
+bool spicommon_dma_chan_free(int dma_chan);
+
+#define SPICOMMON_BUSFLAG_SLAVE  0          ///< Initialize I/O in slave mode
+#define SPICOMMON_BUSFLAG_MASTER (1<<0)     ///< Initialize I/O in master mode
+#define SPICOMMON_BUSFLAG_QUAD   (1<<1)     ///< Also initialize WP/HD pins, if specified
+
+/**
+ * @brief Connect a SPI peripheral to GPIO pins
+ *
+ * This routine is used to connect a SPI peripheral to the IO-pads and DMA channel given in
+ * the arguments. Depending on the IO-pads requested, the routing is done either using the 
+ * IO_mux or using the GPIO matrix.
+ *
+ * @param host SPI peripheral to be routed
+ * @param bus_config Pointer to a spi_bus_config struct detailing the GPIO pins
+ * @param dma_chan DMA-channel (1 or 2) to use, or 0 for no DMA.
+ * @param flags Combination of SPICOMMON_BUSFLAG_* flags
+ * @param[out] is_native A value of 'true' will be written to this address if the GPIOs can be
+ *                  routed using the IO_mux, 'false' if the GPIO matrix is used.
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_OK                on success
+ */
+esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan, int flags, bool *is_native);
+
+/**
+ * @brief Free the IO used by a SPI peripheral
+ *
+ * @param host SPI peripheral to be freed
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_OK                on success
+ */
+
+esp_err_t spicommon_bus_free_io(spi_host_device_t host);
+
+/**
+ * @brief Initialize a Chip Select pin for a specific SPI peripheral
+ *
+ *
+ * @param host SPI peripheral
+ * @param cs_io_num GPIO pin to route
+ * @param cs_num CS id to route
+ * @param force_gpio_matrix If true, CS will always be routed through the GPIO matrix. If false,
+ *                          if the GPIO number allows it, the routing will happen through the IO_mux.
+ */
+
+void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, int force_gpio_matrix);
+
+/**
+ * @brief Free a chip select line
+ *
+ * @param host SPI peripheral
+ * @param cs_num CS id to free
+ */
+void spicommon_cs_free(spi_host_device_t host, int cs_num);
+
+
+/**
+ * @brief Setup a DMA link chain
+ *
+ * This routine will set up a chain of linked DMA descriptors in the array pointed to by
+ * ``dmadesc``. Enough DMA descriptors will be used to fit the buffer of ``len`` bytes in, and the
+ * descriptors will point to the corresponding positions in ``buffer`` and linked together. The
+ * end result is that feeding ``dmadesc[0]`` into DMA hardware results in the entirety ``len`` bytes
+ * of ``data`` being read or written.
+ *
+ * @param dmadesc Pointer to array of DMA descriptors big enough to be able to convey ``len`` bytes
+ * @param len Length of buffer
+ * @param data Data buffer to use for DMA transfer
+ * @param isrx True if data is to be written into ``data``, false if it's to be read from ``data``.
+ */
+void spicommon_setup_dma_desc_links(lldesc_t *dmadesc, int len, const uint8_t *data, bool isrx);
+
+/**
+ * @brief Get the position of the hardware registers for a specific SPI host
+ *
+ * @param host The SPI host
+ *
+ * @return A register descriptor stuct pointer, pointed at the hardware registers
+ */
+spi_dev_t *spicommon_hw_for_host(spi_host_device_t host);
+
+/**
+ * @brief Get the IRQ source for a specific SPI host
+ *
+ * @param host The SPI host
+ *
+ * @return The hosts IRQ source
+ */
+int spicommon_irqsource_for_host(spi_host_device_t host);
+
+/**
+ * Callback, to be called when a DMA engine reset is completed
+*/
+typedef void(*dmaworkaround_cb_t)(void *arg);
+
+
+/**
+ * @brief Request a reset for a certain DMA channel
+ *
+ * @note In some (well-defined) cases in the ESP32 (at least rev v.0 and v.1), a SPI DMA channel will get confused. This can be remedied
+ * by resetting the SPI DMA hardware in case this happens. Unfortunately, the reset knob used for thsi will reset _both_ DMA channels, and
+ * as such can only done safely when both DMA channels are idle. These functions coordinate this.
+ * 
+ * Essentially, when a reset is needed, a driver can request this using spicommon_dmaworkaround_req_reset. This is supposed to be called
+ * with an user-supplied function as an argument. If both DMA channels are idle, this call will reset the DMA subsystem and return true. 
+ * If the other DMA channel is still busy, it will return false; as soon as the other DMA channel is done, however, it will reset the 
+ * DMA subsystem and call the callback. The callback is then supposed to be used to continue the SPI drivers activity.
+ *
+ * @param dmachan DMA channel associated with the SPI host that needs a reset
+ * @param cb Callback to call in case DMA channel cannot be reset immediately
+ * @param arg Argument to the callback
+ *
+ * @return True when a DMA reset could be executed immediately. False when it could not; in this
+ *         case the callback will be called with the specified argument when the logic can execute
+ *         a reset, after that reset.
+ */
+bool spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t cb, void *arg);
+
+
+/**
+ * @brief Check if a DMA reset is requested but has not completed yet
+ *
+ * @return True when a DMA reset is requested but hasn't completed yet. False otherwise.
+ */
+bool spicommon_dmaworkaround_reset_in_progress();
+
+
+/**
+ * @brief Mark a DMA channel as idle.
+ *
+ * A call to this function tells the workaround logic that this channel will
+ * not be affected by a global SPI DMA reset.
+ */
+void spicommon_dmaworkaround_idle(int dmachan);
+
+/**
+ * @brief Mark a DMA channel as active.
+ *
+ * A call to this function tells the workaround logic that this channel will
+ * be affected by a global SPI DMA reset, and a reset like that should not be attempted.
+ */
+void spicommon_dmaworkaround_transfer_active(int dmachan);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/spi_master.h

@@ -0,0 +1,221 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef _DRIVER_SPI_MASTER_H_
+#define _DRIVER_SPI_MASTER_H_
+
+#include "esp_err.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+
+#include "driver/spi_common.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define SPI_DEVICE_TXBIT_LSBFIRST          (1<<0)  ///< Transmit command/address/data LSB first instead of the default MSB first
+#define SPI_DEVICE_RXBIT_LSBFIRST          (1<<1)  ///< Receive data LSB first instead of the default MSB first
+#define SPI_DEVICE_BIT_LSBFIRST            (SPI_DEVICE_TXBIT_LSBFIRST|SPI_DEVICE_RXBIT_LSBFIRST); ///< Transmit and receive LSB first
+#define SPI_DEVICE_3WIRE                   (1<<2)  ///< Use MOSI (=spid) for both sending and receiving data
+#define SPI_DEVICE_POSITIVE_CS             (1<<3)  ///< Make CS positive during a transaction instead of negative
+#define SPI_DEVICE_HALFDUPLEX              (1<<4)  ///< Transmit data before receiving it, instead of simultaneously
+#define SPI_DEVICE_CLK_AS_CS               (1<<5)  ///< Output clock on CS line if CS is active
+
+
+typedef struct spi_transaction_t spi_transaction_t;
+typedef void(*transaction_cb_t)(spi_transaction_t *trans);
+
+/**
+ * @brief This is a configuration for a SPI slave device that is connected to one of the SPI buses.
+ */
+typedef struct {
+    uint8_t command_bits;           ///< Amount of bits in command phase (0-16)
+    uint8_t address_bits;           ///< Amount of bits in address phase (0-64)
+    uint8_t dummy_bits;             ///< Amount of dummy bits to insert between address and data phase
+    uint8_t mode;                   ///< SPI mode (0-3)
+    uint8_t duty_cycle_pos;         ///< Duty cycle of positive clock, in 1/256th increments (128 = 50%/50% duty). Setting this to 0 (=not setting it) is equivalent to setting this to 128.
+    uint8_t cs_ena_pretrans;        ///< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions.
+    uint8_t cs_ena_posttrans;       ///< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16)
+    int clock_speed_hz;             ///< Clock speed, in Hz
+    int spics_io_num;               ///< CS GPIO pin for this device, or -1 if not used
+    uint32_t flags;                 ///< Bitwise OR of SPI_DEVICE_* flags
+    int queue_size;                 ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_device_queue_trans but not yet finished using spi_device_get_trans_result) at the same time
+    transaction_cb_t pre_cb;        ///< Callback to be called before a transmission is started. This callback is called within interrupt context.
+    transaction_cb_t post_cb;       ///< Callback to be called after a transmission has completed. This callback is called within interrupt context.
+} spi_device_interface_config_t;
+
+
+#define SPI_TRANS_MODE_DIO            (1<<0)  ///< Transmit/receive data in 2-bit mode
+#define SPI_TRANS_MODE_QIO            (1<<1)  ///< Transmit/receive data in 4-bit mode
+#define SPI_TRANS_MODE_DIOQIO_ADDR    (1<<4)  ///< Also transmit address in mode selected by SPI_MODE_DIO/SPI_MODE_QIO
+#define SPI_TRANS_USE_RXDATA          (1<<2)  ///< Receive into rx_data member of spi_transaction_t instead into memory at rx_buffer.
+#define SPI_TRANS_USE_TXDATA          (1<<3)  ///< Transmit tx_data member of spi_transaction_t instead of data at tx_buffer. Do not set tx_buffer when using this.
+
+/**
+ * This structure describes one SPI transaction. The descriptor should not be modified until the transaction finishes.
+ */
+struct spi_transaction_t {
+    uint32_t flags;                 ///< Bitwise OR of SPI_TRANS_* flags
+    uint16_t cmd;                   ///< Command data, of which the length is set in the ``command_bits`` of spi_device_interface_config_t.
+                                    ///< <b>NOTE: this field, used to be "command" in ESP-IDF 2.1 and before, is re-written to be used in a new way in ESP-IDF 3.0.</b>
+                                    ///< - Example: write 0x0123 and command_bits=12 to send command 0x12, 0x3_ (in previous version, you may have to write 0x3_12).
+    uint64_t addr;                  ///< Address data, of which the length is set in the ``address_bits`` of spi_device_interface_config_t.
+                                    ///< <b>NOTE: this field, used to be "address" in ESP-IDF 2.1 and before, is re-written to be used in a new way in ESP-IDF3.0.</b> 
+                                    ///< - Example: write 0x123400 and address_bits=24 to send address of 0x12, 0x34, 0x00 (in previous version, you may have to write 0x12340000).  
+    size_t length;                  ///< Total data length, in bits
+    size_t rxlength;                ///< Total data length received, should be not greater than ``length`` in full-duplex mode (0 defaults this to the value of ``length``).
+    void *user;                     ///< User-defined variable. Can be used to store eg transaction ID.
+    union {
+        const void *tx_buffer;      ///< Pointer to transmit buffer, or NULL for no MOSI phase
+        uint8_t tx_data[4];         ///< If SPI_USE_TXDATA is set, data set here is sent directly from this variable.
+    };
+    union {
+        void *rx_buffer;            ///< Pointer to receive buffer, or NULL for no MISO phase. Written by 4 bytes-unit if DMA is used.
+        uint8_t rx_data[4];         ///< If SPI_USE_RXDATA is set, data is received directly to this variable
+    };
+} ;        //the rx data should start from a 32-bit aligned address to get around dma issue.
+
+
+typedef struct spi_device_t* spi_device_handle_t;  ///< Handle for a device on a SPI bus
+
+/**
+ * @brief Initialize a SPI bus
+ *
+ * @warning For now, only supports HSPI and VSPI.
+ *
+ * @param host SPI peripheral that controls this bus
+ * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized
+ * @param dma_chan Either channel 1 or 2, or 0 in the case when no DMA is required. Selecting a DMA channel
+ *                 for a SPI bus allows transfers on the bus to have sizes only limited by the amount of 
+ *                 internal memory. Selecting no DMA channel (by passing the value 0) limits the amount of
+ *                 bytes transfered to a maximum of 32.
+ *
+ * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in 
+ *          DMA-capable memory.
+ *
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if configuration is invalid
+ *         - ESP_ERR_INVALID_STATE if host already is in use
+ *         - ESP_ERR_NO_MEM        if out of memory
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_bus_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan);
+
+/**
+ * @brief Free a SPI bus
+ *
+ * @warning In order for this to succeed, all devices have to be removed first.
+ *
+ * @param host SPI peripheral to free
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_ERR_INVALID_STATE if not all devices on the bus are freed
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_bus_free(spi_host_device_t host);
+
+/**
+ * @brief Allocate a device on a SPI bus
+ *
+ * This initializes the internal structures for a device, plus allocates a CS pin on the indicated SPI master
+ * peripheral and routes it to the indicated GPIO. All SPI master devices have three CS pins and can thus control
+ * up to three devices.
+ *
+ * @note While in general, speeds up to 80MHz on the dedicated SPI pins and 40MHz on GPIO-matrix-routed pins are
+ *       supported, full-duplex transfers routed over the GPIO matrix only support speeds up to 26MHz.
+ *
+ * @param host SPI peripheral to allocate device on
+ * @param dev_config SPI interface protocol config for the device
+ * @param handle Pointer to variable to hold the device handle
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_ERR_NOT_FOUND     if host doesn't have any free CS slots
+ *         - ESP_ERR_NO_MEM        if out of memory
+ *         - ESP_OK                on success
+ */ 
+esp_err_t spi_bus_add_device(spi_host_device_t host, spi_device_interface_config_t *dev_config, spi_device_handle_t *handle);
+
+
+/**
+ * @brief Remove a device from the SPI bus
+ *
+ * @param handle Device handle to free
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_ERR_INVALID_STATE if device already is freed
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_bus_remove_device(spi_device_handle_t handle);
+
+
+/**
+ * @brief Queue a SPI transaction for execution
+ *
+ * @param handle Device handle obtained using spi_host_add_dev
+ * @param trans_desc Description of transaction to execute
+ * @param ticks_to_wait Ticks to wait until there's room in the queue; use portMAX_DELAY to
+ *                      never time out.
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait);
+
+
+/**
+ * @brief Get the result of a SPI transaction queued earlier
+ *
+ * This routine will wait until a transaction to the given device (queued earlier with 
+ * spi_device_queue_trans) has succesfully completed. It will then return the description of the
+ * completed transaction so software can inspect the result and e.g. free the memory or 
+ * re-use the buffers.
+ *
+ * @param handle Device handle obtained using spi_host_add_dev
+ * @param trans_desc Pointer to variable able to contain a pointer to the description of the transaction 
+        that is executed. The descriptor should not be modified until the descriptor is returned by 
+        spi_device_get_trans_result.
+ * @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time
+                        out.
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_device_get_trans_result(spi_device_handle_t handle, spi_transaction_t **trans_desc, TickType_t ticks_to_wait);
+
+
+/**
+ * @brief Do a SPI transaction
+ *
+ * Essentially does the same as spi_device_queue_trans followed by spi_device_get_trans_result. Do
+ * not use this when there is still a transaction queued that hasn't been finalized 
+ * using spi_device_get_trans_result.
+ *
+ * @param handle Device handle obtained using spi_host_add_dev
+ * @param trans_desc Description of transaction to execute
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_device_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/spi_slave.h

@@ -0,0 +1,165 @@
+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef _DRIVER_SPI_SLAVE_H_
+#define _DRIVER_SPI_SLAVE_H_
+
+#include "esp_err.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+#include "driver/spi_common.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+#define SPI_SLAVE_TXBIT_LSBFIRST          (1<<0)  ///< Transmit command/address/data LSB first instead of the default MSB first
+#define SPI_SLAVE_RXBIT_LSBFIRST          (1<<1)  ///< Receive data LSB first instead of the default MSB first
+#define SPI_SLAVE_BIT_LSBFIRST            (SPI_TXBIT_LSBFIRST|SPI_RXBIT_LSBFIRST); ///< Transmit and receive LSB first
+
+
+typedef struct spi_slave_transaction_t spi_slave_transaction_t;
+typedef void(*slave_transaction_cb_t)(spi_slave_transaction_t *trans);
+
+/**
+ * @brief This is a configuration for a SPI host acting as a slave device.
+ */
+typedef struct {
+    int spics_io_num;               ///< CS GPIO pin for this device
+    uint32_t flags;                 ///< Bitwise OR of SPI_SLAVE_* flags
+    int queue_size;                 ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_slave_queue_trans but not yet finished using spi_slave_get_trans_result) at the same time
+    uint8_t mode;                   ///< SPI mode (0-3)
+    slave_transaction_cb_t post_setup_cb; ///< Callback called after the SPI registers are loaded with new data
+    slave_transaction_cb_t post_trans_cb; ///< Callback called after a transaction is done
+} spi_slave_interface_config_t;
+
+/**
+ * This structure describes one SPI transaction
+ */
+struct spi_slave_transaction_t {
+    size_t length;                  ///< Total data length, in bits
+    const void *tx_buffer;          ///< Pointer to transmit buffer, or NULL for no MOSI phase
+    void *rx_buffer;                ///< Pointer to receive buffer, or NULL for no MISO phase
+    void *user;                     ///< User-defined variable. Can be used to store eg transaction ID.
+};
+
+/**
+ * @brief Initialize a SPI bus as a slave interface
+ *
+ * @warning For now, only supports HSPI and VSPI.
+ *
+ * @param host SPI peripheral to use as a SPI slave interface
+ * @param bus_config Pointer to a spi_bus_config_t struct specifying how the host should be initialized
+ * @param slave_config Pointer to a spi_slave_interface_config_t struct specifying the details for the slave interface
+ * @param dma_chan Either 1 or 2. A SPI bus used by this driver must have a DMA channel associated with
+ *                 it. The SPI hardware has two DMA channels to share. This parameter indicates which
+ *                 one to use.
+ *
+ * @warning If a DMA channel is selected, any transmit and receive buffer used should be allocated in 
+ *          DMA-capable memory.
+ *
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if configuration is invalid
+ *         - ESP_ERR_INVALID_STATE if host already is in use
+ *         - ESP_ERR_NO_MEM        if out of memory
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *bus_config, const spi_slave_interface_config_t *slave_config, int dma_chan);
+
+/**
+ * @brief Free a SPI bus claimed as a SPI slave interface
+ *
+ * @param host SPI peripheral to free
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_ERR_INVALID_STATE if not all devices on the bus are freed
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_slave_free(spi_host_device_t host);
+
+
+/**
+ * @brief Queue a SPI transaction for execution
+ *
+ * Queues a SPI transaction to be executed by this slave device. (The transaction queue size was specified when the slave
+ * device was initialised via spi_slave_initialize.) This function may block if the queue is full (depending on the
+ * ticks_to_wait parameter). No SPI operation is directly initiated by this function, the next queued transaction
+ * will happen when the master initiates a SPI transaction by pulling down CS and sending out clock signals.
+ *
+ * This function hands over ownership of the buffers in ``trans_desc`` to the SPI slave driver; the application is
+ * not to access this memory until ``spi_slave_queue_trans`` is called to hand ownership back to the application.
+ *
+ * @param host SPI peripheral that is acting as a slave
+ * @param trans_desc Description of transaction to execute. Not const because we may want to write status back
+ *                   into the transaction description.
+ * @param ticks_to_wait Ticks to wait until there's room in the queue; use portMAX_DELAY to
+ *                      never time out.
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_slave_queue_trans(spi_host_device_t host, const spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait);
+
+
+/**
+ * @brief Get the result of a SPI transaction queued earlier
+ *
+ * This routine will wait until a transaction to the given device (queued earlier with 
+ * spi_slave_queue_trans) has succesfully completed. It will then return the description of the
+ * completed transaction so software can inspect the result and e.g. free the memory or 
+ * re-use the buffers.
+ *
+ * It is mandatory to eventually use this function for any transaction queued by ``spi_slave_queue_trans``.
+ *
+ * @param host SPI peripheral to that is acting as a slave
+ * @param[out] trans_desc Pointer to variable able to contain a pointer to the description of the 
+ *                   transaction that is executed
+ * @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time
+ *                      out.
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_slave_get_trans_result(spi_host_device_t host, spi_slave_transaction_t **trans_desc, TickType_t ticks_to_wait);
+
+
+/**
+ * @brief Do a SPI transaction
+ *
+ * Essentially does the same as spi_slave_queue_trans followed by spi_slave_get_trans_result. Do
+ * not use this when there is still a transaction queued that hasn't been finalized 
+ * using spi_slave_get_trans_result.
+ *
+ * @param host SPI peripheral to that is acting as a slave
+ * @param trans_desc Pointer to variable able to contain a pointer to the description of the 
+ *                   transaction that is executed. Not const because we may want to write status back
+ *                   into the transaction description.
+ * @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time
+ *                      out.
+ * @return 
+ *         - ESP_ERR_INVALID_ARG   if parameter is invalid
+ *         - ESP_OK                on success
+ */
+esp_err_t spi_slave_transmit(spi_host_device_t host, spi_slave_transaction_t *trans_desc, TickType_t ticks_to_wait);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/timer.h

@@ -0,0 +1,356 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_TIMER_H_
+#define _DRIVER_TIMER_H_
+#include "esp_err.h"
+#include "esp_attr.h"
+#include "soc/soc.h"
+#include "soc/timer_group_reg.h"
+#include "soc/timer_group_struct.h"
+#include "esp_intr_alloc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define TIMER_BASE_CLK   (APB_CLK_FREQ)
+/**
+ * @brief Selects a Timer-Group out of 2 available groups
+ */
+typedef enum {
+    TIMER_GROUP_0 = 0, /*!<Hw timer group 0*/
+    TIMER_GROUP_1 = 1, /*!<Hw timer group 1*/
+    TIMER_GROUP_MAX,
+} timer_group_t;
+
+/**
+ * @brief Select a hardware timer from timer groups
+ */
+typedef enum {
+    TIMER_0 = 0, /*!<Select timer0 of GROUPx*/
+    TIMER_1 = 1, /*!<Select timer1 of GROUPx*/
+    TIMER_MAX,
+} timer_idx_t;
+
+/**
+ * @brief Decides the direction of counter
+ */
+typedef enum {
+    TIMER_COUNT_DOWN = 0, /*!< Descending Count from cnt.high|cnt.low*/
+    TIMER_COUNT_UP = 1,   /*!< Ascending Count from Zero*/
+    TIMER_COUNT_MAX
+} timer_count_dir_t;
+
+/**
+ * @brief Decides whether timer is on or paused
+ */
+typedef enum {
+    TIMER_PAUSE = 0, /*!<Pause timer counter*/
+    TIMER_START = 1, /*!<Start timer counter*/
+} timer_start_t;
+
+/**
+ * @brief Decides whether to enable alarm mode
+ */
+typedef enum {
+    TIMER_ALARM_DIS = 0,  /*!< Disable timer alarm*/
+    TIMER_ALARM_EN = 1,   /*!< Enable timer alarm*/
+    TIMER_ALARM_MAX
+} timer_alarm_t;
+
+/**
+ * @brief Select interrupt type if running in alarm mode.
+ */
+typedef enum {
+    TIMER_INTR_LEVEL = 0,  /*!< Interrupt mode: level mode*/
+    //TIMER_INTR_EDGE = 1, /*!< Interrupt mode: edge mode, Not supported Now*/
+    TIMER_INTR_MAX
+} timer_intr_mode_t;
+
+/**
+ * @brief Select if Alarm needs to be loaded by software or automatically reload by hardware.
+ */
+typedef enum {
+    TIMER_AUTORELOAD_DIS = 0,  /*!< Disable auto-reload: hardware will not load counter value after an alarm event*/
+    TIMER_AUTORELOAD_EN = 1,   /*!< Enable auto-reload: hardware will load counter value after an alarm event*/
+    TIMER_AUTORELOAD_MAX,
+} timer_autoreload_t;
+
+/**
+ * @brief timer configure struct
+ */
+typedef struct {
+    bool alarm_en; /*!< Timer alarm enable */
+    bool counter_en; /*!< Counter enable */
+    timer_intr_mode_t intr_type; /*!< Interrupt mode */
+    timer_count_dir_t counter_dir; /*!< Counter direction  */
+    bool auto_reload; /*!< Timer auto-reload */
+    uint16_t divider; /*!< Counter clock divider*/
+} timer_config_t;
+
+
+/**
+ * @brief Interrupt handle, used in order to free the isr after use.
+ * Aliases to an int handle for now.
+ */
+typedef intr_handle_t timer_isr_handle_t;
+
+/**
+ * @brief Read the counter value of hardware timer.
+ *
+ * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param timer_val Pointer to accept timer counter value.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_get_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t* timer_val);
+
+/**
+ * @brief Read the counter value of hardware timer, in unit of a given scale.
+ *
+ * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param time Pointer, type of double*, to accept timer counter value, in seconds.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_get_counter_time_sec(timer_group_t group_num, timer_idx_t timer_num, double* time);
+
+/**
+ * @brief Set counter value to hardware timer.
+ *
+ * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param load_val Counter value to write to the hardware timer.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_set_counter_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t load_val);
+
+/**
+ * @brief Start the counter of hardware timer.
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_start(timer_group_t group_num, timer_idx_t timer_num);
+
+/**
+ * @brief Pause the counter of hardware timer.
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_pause(timer_group_t group_num, timer_idx_t timer_num);
+
+/**
+ * @brief Set counting mode for hardware timer.
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param counter_dir Counting direction of timer, count-up or count-down
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_set_counter_mode(timer_group_t group_num, timer_idx_t timer_num, timer_count_dir_t counter_dir);
+
+/**
+ * @brief Enable or disable counter reload function when alarm event occurs.
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param reload Counter reload mode.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_set_auto_reload(timer_group_t group_num, timer_idx_t timer_num, timer_autoreload_t reload);
+
+/**
+ * @brief Set hardware timer source clock divider. Timer groups clock are divider from APB clock.
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param divider Timer clock divider value.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_set_divider(timer_group_t group_num, timer_idx_t timer_num, uint16_t divider);
+
+/**
+ * @brief Set timer alarm value.
+ *
+ * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param alarm_value A 64-bit value to set the alarm value.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_set_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t alarm_value);
+
+/**
+ * @brief Get timer alarm value.
+ *
+ * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param alarm_value Pointer of A 64-bit value to accept the alarm value.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_get_alarm_value(timer_group_t group_num, timer_idx_t timer_num, uint64_t* alarm_value);
+
+/**
+ * @brief Get timer alarm value.
+ *
+ * @param group_num Timer group, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param alarm_en To enable or disable timer alarm function.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_set_alarm(timer_group_t group_num, timer_idx_t timer_num, timer_alarm_t alarm_en);
+
+
+/**
+ * @brief   register Timer interrupt handler, the handler is an ISR.
+ *          The handler will be attached to the same CPU core that this function is running on.
+ *
+ * @param group_num Timer group number
+ * @param timer_num Timer index of timer group
+ * @param fn Interrupt handler function.
+ *        @note
+ *        In case the this is called with the INIRAM flag, code inside the handler function can 
+ *        only call functions in IRAM, so it cannot call other timer APIs.
+ *        Use direct register access to access timers from inside the ISR in this case.
+ *
+ * @param arg Parameter for handler function
+ * @param  intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+ *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info.
+ * @param  handle Pointer to return handle. If non-NULL, a handle for the interrupt will
+ *            be returned here.
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Function pointer error.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_isr_register(timer_group_t group_num, timer_idx_t timer_num, void (*fn)(void*), void * arg, int intr_alloc_flags, timer_isr_handle_t *handle);
+
+/** @brief Initializes and configure the timer.
+ * 
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param config Pointer to timer initialization parameters.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_init(timer_group_t group_num, timer_idx_t timer_num, const timer_config_t* config);
+
+/** @brief Get timer configure value.
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index, 0 for hw_timer[0] & 1 for hw_timer[1]
+ * @param config Pointer of struct to accept timer parameters.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_get_config(timer_group_t group_num, timer_idx_t timer_num, timer_config_t *config);
+
+/** @brief Enable timer group interrupt, by enable mask
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param en_mask Timer interrupt enable mask.
+ *        Use TIMG_T0_INT_ENA_M to enable t0 interrupt
+ *        Use TIMG_T1_INT_ENA_M to enable t1 interrupt
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_group_intr_enable(timer_group_t group_num, uint32_t en_mask);
+
+/** @brief Disable timer group interrupt, by disable mask
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param disable_mask Timer interrupt disable mask.
+ *        Use TIMG_T0_INT_ENA_M to disable t0 interrupt
+ *        Use TIMG_T1_INT_ENA_M to disable t1 interrupt
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_group_intr_disable(timer_group_t group_num, uint32_t disable_mask);
+
+/** @brief Enable timer interrupt
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_enable_intr(timer_group_t group_num, timer_idx_t timer_num);
+
+/** @brief Disable timer interrupt
+ *
+ * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
+ * @param timer_num Timer index.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t timer_disable_intr(timer_group_t group_num, timer_idx_t timer_num);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TIMER_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/touch_pad.h

@@ -0,0 +1,502 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_TOUCH_PAD_H_
+#define _DRIVER_TOUCH_PAD_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "esp_intr.h"
+#include "esp_err.h"
+#include "esp_intr_alloc.h"
+
+typedef enum {
+    TOUCH_PAD_NUM0 = 0, /*!< Touch pad channel 0 is GPIO4 */
+    TOUCH_PAD_NUM1,     /*!< Touch pad channel 1 is GPIO0 */
+    TOUCH_PAD_NUM2,     /*!< Touch pad channel 2 is GPIO2 */
+    TOUCH_PAD_NUM3,     /*!< Touch pad channel 3 is GPIO15*/
+    TOUCH_PAD_NUM4,     /*!< Touch pad channel 4 is GPIO13*/
+    TOUCH_PAD_NUM5,     /*!< Touch pad channel 5 is GPIO12*/
+    TOUCH_PAD_NUM6,     /*!< Touch pad channel 6 is GPIO14*/
+    TOUCH_PAD_NUM7,     /*!< Touch pad channel 7 is GPIO27*/
+    TOUCH_PAD_NUM8,     /*!< Touch pad channel 8 is GPIO32*/
+    TOUCH_PAD_NUM9,     /*!< Touch pad channel 9 is GPIO33*/
+    TOUCH_PAD_MAX,
+} touch_pad_t;
+
+typedef enum {
+    TOUCH_HVOLT_KEEP = -1, /*!<Touch sensor high reference voltage, no change  */
+    TOUCH_HVOLT_2V4 = 0,   /*!<Touch sensor high reference voltage, 2.4V  */
+    TOUCH_HVOLT_2V5,       /*!<Touch sensor high reference voltage, 2.5V  */
+    TOUCH_HVOLT_2V6,       /*!<Touch sensor high reference voltage, 2.6V  */
+    TOUCH_HVOLT_2V7,       /*!<Touch sensor high reference voltage, 2.7V  */
+    TOUCH_HVOLT_MAX,
+} touch_high_volt_t;
+
+typedef enum {
+    TOUCH_LVOLT_KEEP = -1, /*!<Touch sensor low reference voltage, no change  */
+    TOUCH_LVOLT_0V5 = 0,   /*!<Touch sensor low reference voltage, 0.5V  */
+    TOUCH_LVOLT_0V6,       /*!<Touch sensor low reference voltage, 0.6V  */
+    TOUCH_LVOLT_0V7,       /*!<Touch sensor low reference voltage, 0.7V  */
+    TOUCH_LVOLT_0V8,       /*!<Touch sensor low reference voltage, 0.8V  */
+    TOUCH_LVOLT_MAX,
+} touch_low_volt_t;
+
+typedef enum {
+    TOUCH_HVOLT_ATTEN_KEEP = -1,  /*!<Touch sensor high reference voltage attenuation, no change  */
+    TOUCH_HVOLT_ATTEN_1V5 = 0,    /*!<Touch sensor high reference voltage attenuation, 1.5V attenuation  */
+    TOUCH_HVOLT_ATTEN_1V,         /*!<Touch sensor high reference voltage attenuation, 1.0V attenuation  */
+    TOUCH_HVOLT_ATTEN_0V5,        /*!<Touch sensor high reference voltage attenuation, 0.5V attenuation  */
+    TOUCH_HVOLT_ATTEN_0V,         /*!<Touch sensor high reference voltage attenuation,   0V attenuation  */
+    TOUCH_HVOLT_ATTEN_MAX,
+} touch_volt_atten_t;
+
+typedef enum {
+    TOUCH_PAD_SLOPE_0 = 0,       /*!<Touch sensor charge / discharge speed, always zero  */
+    TOUCH_PAD_SLOPE_1 = 1,       /*!<Touch sensor charge / discharge speed, slowest  */
+    TOUCH_PAD_SLOPE_2 = 2,       /*!<Touch sensor charge / discharge speed */
+    TOUCH_PAD_SLOPE_3 = 3,       /*!<Touch sensor charge / discharge speed  */
+    TOUCH_PAD_SLOPE_4 = 4,       /*!<Touch sensor charge / discharge speed  */
+    TOUCH_PAD_SLOPE_5 = 5,       /*!<Touch sensor charge / discharge speed  */
+    TOUCH_PAD_SLOPE_6 = 6,       /*!<Touch sensor charge / discharge speed  */
+    TOUCH_PAD_SLOPE_7 = 7,       /*!<Touch sensor charge / discharge speed, fast  */
+    TOUCH_PAD_SLOPE_MAX,
+} touch_cnt_slope_t;
+
+typedef enum {
+    TOUCH_TRIGGER_BELOW = 0,   /*!<Touch interrupt will happen if counter value is less than threshold.*/
+    TOUCH_TRIGGER_ABOVE = 1,   /*!<Touch interrupt will happen if counter value is larger than threshold.*/
+    TOUCH_TRIGGER_MAX,
+} touch_trigger_mode_t;
+
+typedef enum {
+    TOUCH_TRIGGER_SOURCE_BOTH = 0,  /*!< wakeup interrupt is generated if both SET1 and SET2 are "touched"*/
+    TOUCH_TRIGGER_SOURCE_SET1 = 1,  /*!< wakeup interrupt is generated if SET1 is "touched"*/
+    TOUCH_TRIGGER_SOURCE_MAX,
+} touch_trigger_src_t;
+
+typedef enum {
+    TOUCH_PAD_TIE_OPT_LOW = 0,    /*!<Initial level of charging voltage, low level */
+    TOUCH_PAD_TIE_OPT_HIGH = 1,   /*!<Initial level of charging voltage, high level */
+    TOUCH_PAD_TIE_OPT_MAX,
+} touch_tie_opt_t;
+
+typedef enum {
+    TOUCH_FSM_MODE_TIMER = 0,   /*!<To start touch FSM by timer */
+    TOUCH_FSM_MODE_SW,          /*!<To start touch FSM by software trigger */
+    TOUCH_FSM_MODE_MAX,
+} touch_fsm_mode_t;
+
+
+typedef intr_handle_t touch_isr_handle_t;
+
+#define TOUCH_PAD_SLEEP_CYCLE_DEFAULT   (0x1000)  /*!<The timer frequency is RTC_SLOW_CLK (can be 150k or 32k depending on the options), max value is 0xffff */
+#define TOUCH_PAD_MEASURE_CYCLE_DEFAULT (0xffff)  /*!<The timer frequency is 8Mhz, the max value is 0xffff */
+#define TOUCH_FSM_MODE_DEFAULT          (TOUCH_FSM_MODE_TIMER)  /*!<The touch FSM my be started by the software or timer */
+#define TOUCH_TRIGGER_MODE_DEFAULT      (TOUCH_TRIGGER_BELOW)   /*!<Interrupts can be triggered if sensor value gets below or above threshold */
+#define TOUCH_TRIGGER_SOURCE_DEFAULT    (TOUCH_TRIGGER_SOURCE_SET1)  /*!<The wakeup trigger source can be SET1 or both SET1 and SET2 */
+#define TOUCH_PAD_BIT_MASK_MAX          (0x3ff)
+
+/**
+ * @brief Initialize touch module.
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_FAIL Touch pad init error
+ */
+esp_err_t touch_pad_init();
+
+/**
+ * @brief Un-install touch pad driver.
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Touch pad driver not initialized
+ */
+esp_err_t touch_pad_deinit();
+
+/**
+ * @brief Configure touch pad interrupt threshold.
+ * @param touch_num touch pad index
+ * @param threshold interrupt threshold,
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG if argument wrong
+ *     - ESP_FAIL if touch pad not initialized
+ */
+esp_err_t touch_pad_config(touch_pad_t touch_num, uint16_t threshold);
+
+/**
+ * @brief get touch sensor counter value.
+ *  Each touch sensor has a counter to count the number of charge/discharge cycles.
+ *  When the pad is not 'touched', we can get a number of the counter.
+ *  When the pad is 'touched', the value in counter will get smaller because of the larger equivalent capacitance.
+ *  User can use this function to determine the interrupt trigger threshold.
+ *
+ * @param touch_num touch pad index
+ * @param touch_value pointer to accept touch sensor value
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Touch pad error
+ *     - ESP_FAIL Touch pad not initialized
+ */
+esp_err_t touch_pad_read(touch_pad_t touch_num, uint16_t * touch_value);
+
+/**
+ * @brief get filtered touch sensor counter value by IIR filter.
+ * @note touch_pad_filter_start has to be called before calling touch_pad_read_filtered.
+ *       This function can be called from ISR
+ *
+ * @param touch_num touch pad index
+ * @param touch_value pointer to accept touch sensor value
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_ERR_INVALID_ARG Touch pad error
+ *     - ESP_FAIL Touch pad not initialized
+ */
+esp_err_t touch_pad_read_filtered(touch_pad_t touch_num, uint16_t *touch_value);
+
+/**
+ * @brief   Register touch-pad ISR,
+ * @note Deprecated function, users should replace this with touch_pad_isr_register,
+ *       because RTC modules share a same interrupt index.
+ * @param fn  Pointer to ISR handler
+ * @param arg  Parameter for ISR
+ * @param unused Reserved, not used
+ * @param handle_unused Reserved, not used
+ * @return
+ *     - ESP_OK Success ;
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ */
+esp_err_t touch_pad_isr_handler_register(void(*fn)(void *), void *arg, int unused, intr_handle_t *handle_unused) __attribute__ ((deprecated));
+
+/**
+ * @brief   Register touch-pad ISR.
+ *          The handler will be attached to the same CPU core that this function is running on.
+ * @param fn  Pointer to ISR handler
+ * @param arg  Parameter for ISR
+ * @return
+ *     - ESP_OK Success ;
+ *     - ESP_ERR_INVALID_ARG GPIO error
+ */
+esp_err_t touch_pad_isr_register(intr_handler_t fn, void* arg);
+
+/**
+ * @brief Deregister the handler previously registered using touch_pad_isr_handler_register
+ * @param fn  handler function to call (as passed to touch_pad_isr_handler_register)
+ * @param arg  argument of the handler (as passed to touch_pad_isr_handler_register)
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if a handler matching both fn and
+ *        arg isn't registered
+ */
+esp_err_t touch_pad_isr_deregister(void(*fn)(void *), void *arg);
+
+/**
+ * @brief Set touch sensor measurement and sleep time
+ * @param sleep_cycle  The touch sensor will sleep after each measurement.
+ *                     sleep_cycle decide the interval between each measurement.
+ *                     t_sleep = sleep_cycle / (RTC_SLOW_CLK frequency).
+ *                     The approximate frequency value of RTC_SLOW_CLK can be obtained using rtc_clk_slow_freq_get_hz function.
+ * @param meas_cycle The duration of the touch sensor measurement.
+ *                   t_meas = meas_cycle / 8M, the maximum measure time is 0xffff / 8M = 8.19 ms
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_set_meas_time(uint16_t sleep_cycle, uint16_t meas_cycle);
+
+/**
+ * @brief Get touch sensor measurement and sleep time
+ * @param sleep_cycle  Pointer to accept sleep cycle number
+ * @param meas_cycle Pointer to accept measurement cycle count.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_meas_time(uint16_t *sleep_cycle, uint16_t *meas_cycle);
+
+/**
+ * @brief Set touch sensor reference voltage, if the voltage gap between high and low reference voltage get less,
+ *        the charging and discharging time would be faster, accordingly, the counter value would be larger.
+ *        In the case of detecting very slight change of capacitance, we can narrow down the gap so as to increase
+ *        the sensitivity. On the other hand, narrow voltage gap would also introduce more noise, but we can use a
+ *        software filter to pre-process the counter value.
+ * @param refh the value of DREFH
+ * @param refl the value of DREFL
+ * @param atten the attenuation on DREFH
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_set_voltage(touch_high_volt_t refh, touch_low_volt_t refl, touch_volt_atten_t atten);
+
+/**
+ * @brief Get touch sensor reference voltage,
+ * @param refh pointer to accept DREFH value
+ * @param refl pointer to accept DREFL value
+ * @param atten pointer to accept the attenuation on DREFH
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_voltage(touch_high_volt_t *refh, touch_low_volt_t *refl, touch_volt_atten_t *atten);
+
+/**
+ * @brief Set touch sensor charge/discharge speed for each pad.
+ *        If the slope is 0, the counter would always be zero.
+ *        If the slope is 1, the charging and discharging would be slow, accordingly, the counter value would be small.
+ *        If the slope is set 7, which is the maximum value, the charging and discharging would be fast, accordingly, the
+ *        counter value would be larger.
+ * @param touch_num touch pad index
+ * @param slope touch pad charge/discharge speed
+ * @param opt the initial voltage
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_set_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t slope, touch_tie_opt_t opt);
+
+/**
+ * @brief Get touch sensor charge/discharge speed for each pad
+ * @param touch_num touch pad index
+ * @param slope pointer to accept touch pad charge/discharge slope
+ * @param opt pointer to accept the initial voltage
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_get_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t *slope, touch_tie_opt_t *opt);
+
+/**
+ * @brief Initialize touch pad GPIO
+ * @param touch_num touch pad index
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_io_init(touch_pad_t touch_num);
+
+/**
+ * @brief Set touch sensor FSM mode, the test action can be triggered by the timer,
+ *        as well as by the software.
+ * @param mode FSM mode
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_set_fsm_mode(touch_fsm_mode_t mode);
+
+/**
+ * @brief Get touch sensor FSM mode
+ * @param mode pointer to accept FSM mode
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_fsm_mode(touch_fsm_mode_t *mode);
+
+/**
+ * @brief Trigger a touch sensor measurement, only support in SW mode of FSM
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_sw_start();
+
+/**
+ * @brief Set touch sensor interrupt threshold
+ * @param touch_num touch pad index
+ * @param threshold threshold of touchpad count, refer to touch_pad_set_trigger_mode to see how to set trigger mode.
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint16_t threshold);
+
+/**
+ * @brief Get touch sensor interrupt threshold
+ * @param touch_num touch pad index
+ * @param threshold pointer to accept threshold
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint16_t *threshold);
+
+/**
+ * @brief Set touch sensor interrupt trigger mode.
+ *        Interrupt can be triggered either when counter result is less than
+ *        threshold or when counter result is more than threshold.
+ * @param mode touch sensor interrupt trigger mode
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_set_trigger_mode(touch_trigger_mode_t mode);
+
+/**
+ * @brief Get touch sensor interrupt trigger mode
+ * @param mode pointer to accept touch sensor interrupt trigger mode
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_trigger_mode(touch_trigger_mode_t *mode);
+
+/**
+ * @brief Set touch sensor interrupt trigger source. There are two sets of touch signals.
+ *        Set1 and set2 can be mapped to several touch signals. Either set will be triggered
+ *        if at least one of its touch signal is 'touched'. The interrupt can be configured to be generated
+ *        if set1 is triggered, or only if both sets are triggered.
+ * @param src touch sensor interrupt trigger source
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_set_trigger_source(touch_trigger_src_t src);
+
+/**
+ * @brief Get touch sensor interrupt trigger source
+ * @param src pointer to accept touch sensor interrupt trigger source
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_trigger_source(touch_trigger_src_t *src);
+
+/**
+ * @brief Set touch sensor group mask.
+ *        Touch pad module has two sets of signals, 'Touched' signal is triggered only if
+ *        at least one of touch pad in this group is "touched".
+ *        This function will set the register bits according to the given bitmask.
+ * @param set1_mask bitmask of touch sensor signal group1, it's a 10-bit value
+ * @param set2_mask bitmask of touch sensor signal group2, it's a 10-bit value
+ * @param en_mask bitmask of touch sensor work enable, it's a 10-bit value
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_set_group_mask(uint16_t set1_mask, uint16_t set2_mask, uint16_t en_mask);
+
+/**
+ * @brief Get touch sensor group mask.
+ * @param set1_mask pointer to accept bitmask of touch sensor signal group1, it's a 10-bit value
+ * @param set2_mask pointer to accept bitmask of touch sensor signal group2, it's a 10-bit value
+ * @param en_mask pointer to accept bitmask of touch sensor work enable, it's a 10-bit value
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_get_group_mask(uint16_t *set1_mask, uint16_t *set2_mask, uint16_t *en_mask);
+
+/**
+ * @brief Clear touch sensor group mask.
+ *        Touch pad module has two sets of signals, Interrupt is triggered only if
+ *        at least one of touch pad in this group is "touched".
+ *        This function will clear the register bits according to the given bitmask.
+ * @param set1_mask bitmask touch sensor signal group1, it's a 10-bit value
+ * @param set2_mask bitmask touch sensor signal group2, it's a 10-bit value
+ * @param en_mask bitmask of touch sensor work enable, it's a 10-bit value
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if argument is wrong
+ */
+esp_err_t touch_pad_clear_group_mask(uint16_t set1_mask, uint16_t set2_mask, uint16_t en_mask);
+
+/**
+ * @brief To clear the touch status register, usually use this function in touch ISR to clear status.
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_clear_status();
+
+/**
+ * @brief Get the touch sensor status, usually used in ISR to decide which pads are 'touched'.
+ * @return
+ *      - touch status
+ */
+uint32_t touch_pad_get_status();
+
+/**
+ * @brief To enable touch pad interrupt
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_intr_enable();
+
+/**
+ * @brief To disable touch pad interrupt
+ * @return
+ *      - ESP_OK on success
+ */
+esp_err_t touch_pad_intr_disable();
+
+/**
+ * @brief set touch pad filter calibration period, in ms.
+ *        Need to call touch_pad_filter_start before all touch filter APIs
+ * @param new_period_ms filter period, in ms
+ * @return
+ *      - ESP_OK Success
+ *      - ESP_ERR_INVALID_STATE driver state error
+ *      - ESP_ERR_INVALID_ARG parameter error
+ */
+esp_err_t touch_pad_set_filter_period(uint32_t new_period_ms);
+
+/**
+ * @brief get touch pad filter calibration period, in ms
+ *        Need to call touch_pad_filter_start before all touch filter APIs
+ * @param p_period_ms pointer to accept period
+ * @return
+ *      - ESP_OK Success
+ *      - ESP_ERR_INVALID_STATE driver state error
+ *      - ESP_ERR_INVALID_ARG parameter error
+ */
+esp_err_t touch_pad_get_filter_period(uint32_t* p_period_ms);
+
+/**
+ * @brief start touch pad filter function
+ *      This API will start a filter to process the noise in order to prevent false triggering
+ *      when detecting slight change of capacitance.
+ *      Need to call touch_pad_filter_start before all touch filter APIs
+ *
+ *      If filter is not initialized, this API will initialize the filter with given period.
+ *      If filter is already initialized, this API will update the filter period.
+ * @note This filter uses FreeRTOS timer, which is dispatched from a task with
+ *       priority 1 by default on CPU 0. So if some application task with higher priority
+ *       takes a lot of CPU0 time, then the quality of data obtained from this filter will be affected.
+ *       You can adjust FreeRTOS timer task priority in menuconfig.
+ * @param filter_period_ms filter calibration period, in ms
+ * @return
+ *      - ESP_OK Success
+ *      - ESP_ERR_INVALID_ARG parameter error
+ *      - ESP_ERR_NO_MEM No memory for driver
+ *      - ESP_ERR_INVALID_STATE driver state error
+ */
+esp_err_t touch_pad_filter_start(uint32_t filter_period_ms);
+
+/**
+ * @brief stop touch pad filter function
+ *        Need to call touch_pad_filter_start before all touch filter APIs
+ * @return
+ *      - ESP_OK Success
+ *      - ESP_ERR_INVALID_STATE driver state error
+ */
+esp_err_t touch_pad_filter_stop();
+
+/**
+ * @brief delete touch pad filter driver and release the memory
+ *        Need to call touch_pad_filter_start before all touch filter APIs
+ * @return
+ *      - ESP_OK Success
+ *      - ESP_ERR_INVALID_STATE driver state error
+ */
+esp_err_t touch_pad_filter_delete();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif/*_DRIVER_TOUCH_PAD_H_*/
+

Living_SDK/platform/mcu/esp32/bsp/include/driver/include/driver/uart.h

@@ -0,0 +1,802 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DRIVER_UART_H_
+#define _DRIVER_UART_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "soc/uart_reg.h"
+#include "soc/uart_struct.h"
+#include "esp_err.h"
+#include "esp_intr_alloc.h"
+#include "driver/periph_ctrl.h"
+#include "ringbuf.h"
+#include <esp_types.h>
+
+#define UART_FIFO_LEN           (128)        /*!< Length of the hardware FIFO buffers */
+#define UART_INTR_MASK          0x1ff        /*!< mask of all UART interrupts */
+#define UART_LINE_INV_MASK      (0x3f << 19) /*!< TBD */
+#define UART_BITRATE_MAX        5000000      /*!< Max bit rate supported by UART */
+#define UART_PIN_NO_CHANGE      (-1)         /*!< Constant for uart_set_pin function which indicates that UART pin should not be changed */
+
+#define UART_INVERSE_DISABLE  (0x0)            /*!< Disable UART signal inverse*/
+#define UART_INVERSE_RXD   (UART_RXD_INV_M)    /*!< UART RXD input inverse*/
+#define UART_INVERSE_CTS   (UART_CTS_INV_M)    /*!< UART CTS input inverse*/
+#define UART_INVERSE_TXD   (UART_TXD_INV_M)    /*!< UART TXD output inverse*/
+#define UART_INVERSE_RTS   (UART_RTS_INV_M)    /*!< UART RTS output inverse*/
+
+/**
+ * @brief UART word length constants
+ */
+typedef enum {
+    UART_DATA_5_BITS = 0x0,    /*!< word length: 5bits*/
+    UART_DATA_6_BITS = 0x1,    /*!< word length: 6bits*/
+    UART_DATA_7_BITS = 0x2,    /*!< word length: 7bits*/
+    UART_DATA_8_BITS = 0x3,    /*!< word length: 8bits*/
+    UART_DATA_BITS_MAX = 0X4,
+} uart_word_length_t;
+
+/**
+ * @brief UART stop bits number
+ */
+typedef enum {
+    UART_STOP_BITS_1   = 0x1,  /*!< stop bit: 1bit*/
+    UART_STOP_BITS_1_5 = 0x2,  /*!< stop bit: 1.5bits*/
+    UART_STOP_BITS_2   = 0x3,  /*!< stop bit: 2bits*/
+    UART_STOP_BITS_MAX = 0x4,
+} uart_stop_bits_t;
+
+/**
+ * @brief UART peripheral number
+ */
+typedef enum {
+    UART_NUM_0 = 0x0,  /*!< UART base address 0x3ff40000*/
+    UART_NUM_1 = 0x1,  /*!< UART base address 0x3ff50000*/
+    UART_NUM_2 = 0x2,  /*!< UART base address 0x3ff6E000*/
+    UART_NUM_MAX,
+} uart_port_t;
+
+/**
+ * @brief UART parity constants
+ */
+typedef enum {
+    UART_PARITY_DISABLE = 0x0,   /*!< Disable UART parity*/
+    UART_PARITY_EVEN = 0x2,     /*!< Enable UART even parity*/
+    UART_PARITY_ODD  = 0x3      /*!< Enable UART odd parity*/
+} uart_parity_t;
+
+/**
+ * @brief UART hardware flow control modes
+ */
+typedef enum {
+    UART_HW_FLOWCTRL_DISABLE = 0x0,   /*!< disable hardware flow control*/
+    UART_HW_FLOWCTRL_RTS     = 0x1,   /*!< enable RX hardware flow control (rts)*/
+    UART_HW_FLOWCTRL_CTS     = 0x2,   /*!< enable TX hardware flow control (cts)*/
+    UART_HW_FLOWCTRL_CTS_RTS = 0x3,   /*!< enable hardware flow control*/
+    UART_HW_FLOWCTRL_MAX     = 0x4,
+} uart_hw_flowcontrol_t;
+
+/**
+ * @brief UART configuration parameters for uart_param_config function
+ */
+typedef struct {
+    int baud_rate;                      /*!< UART baudrate*/
+    uart_word_length_t data_bits;       /*!< UART byte size*/
+    uart_parity_t parity;               /*!< UART parity mode*/
+    uart_stop_bits_t stop_bits;         /*!< UART stop bits*/
+    uart_hw_flowcontrol_t flow_ctrl;    /*!< UART HW flow control mode(cts/rts)*/
+    uint8_t rx_flow_ctrl_thresh ;       /*!< UART HW RTS threshold*/
+} uart_config_t;
+
+/**
+ * @brief UART interrupt configuration parameters for uart_intr_config function
+ */
+typedef struct {
+    uint32_t intr_enable_mask;          /*!< UART interrupt enable mask, choose from UART_XXXX_INT_ENA_M under UART_INT_ENA_REG(i), connect with bit-or operator*/
+    uint8_t  rx_timeout_thresh;         /*!< UART timeout interrupt threshold(unit: time of sending one byte)*/
+    uint8_t  txfifo_empty_intr_thresh;  /*!< UART TX empty interrupt threshold.*/
+    uint8_t  rxfifo_full_thresh;        /*!< UART RX full interrupt threshold.*/
+} uart_intr_config_t;
+
+/**
+ * @brief UART event types used in the ringbuffer
+ */
+typedef enum {
+    UART_DATA,              /*!< UART data event*/
+    UART_BREAK,             /*!< UART break event*/
+    UART_BUFFER_FULL,       /*!< UART RX buffer full event*/
+    UART_FIFO_OVF,          /*!< UART FIFO overflow event*/
+    UART_FRAME_ERR,         /*!< UART RX frame error event*/
+    UART_PARITY_ERR,        /*!< UART RX parity event*/
+    UART_DATA_BREAK,        /*!< UART TX data and break event*/
+    UART_PATTERN_DET,       /*!< UART pattern detected */
+    UART_EVENT_MAX,         /*!< UART event max index*/
+} uart_event_type_t;
+
+/**
+ * @brief Event structure used in UART event queue
+ */
+typedef struct {
+    uart_event_type_t type; /*!< UART event type */
+    size_t size;            /*!< UART data size for UART_DATA event*/
+} uart_event_t;
+
+typedef intr_handle_t uart_isr_handle_t;
+
+/**
+ * @brief Set UART data bits.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param data_bit UART data bits
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit);
+
+/**
+ * @brief Get UART data bits.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param data_bit Pointer to accept value of UART data bits.
+ *
+ * @return
+ *     - ESP_FAIL  Parameter error
+ *     - ESP_OK    Success, result will be put in (*data_bit)
+ */
+esp_err_t uart_get_word_length(uart_port_t uart_num, uart_word_length_t* data_bit);
+
+/**
+ * @brief Set UART stop bits.
+ *
+ * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param stop_bits  UART stop bits
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Fail
+ */
+esp_err_t uart_set_stop_bits(uart_port_t uart_num, uart_stop_bits_t stop_bits);
+
+/**
+ * @brief Set UART stop bits.
+ *
+ * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param stop_bits  Pointer to accept value of UART stop bits.
+ *
+ * @return
+ *     - ESP_FAIL Parameter error
+ *     - ESP_OK   Success, result will be put in (*stop_bit)
+ */
+esp_err_t uart_get_stop_bits(uart_port_t uart_num, uart_stop_bits_t* stop_bits);
+
+/**
+ * @brief Set UART parity.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param parity_mode the enum of uart parity configuration
+ *
+ * @return
+ *     - ESP_FAIL  Parameter error
+ *     - ESP_OK    Success
+ */
+esp_err_t uart_set_parity(uart_port_t uart_num, uart_parity_t parity_mode);
+
+/**
+ * @brief Get UART parity mode.
+ *
+ * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param parity_mode Pointer to accept value of UART parity mode.
+ *
+ * @return
+ *     - ESP_FAIL  Parameter error
+ *     - ESP_OK    Success, result will be put in (*parity_mode)
+ *
+ */
+esp_err_t uart_get_parity(uart_port_t uart_num, uart_parity_t* parity_mode);
+
+/**
+ * @brief Set UART baud rate.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param baudrate UART baud rate.
+ *
+ * @return
+ *     - ESP_FAIL Parameter error
+ *     - ESP_OK   Success
+ */
+esp_err_t uart_set_baudrate(uart_port_t uart_num, uint32_t baudrate);
+
+/**
+ * @brief Get UART bit-rate.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param baudrate Pointer to accept value of UART baud rate
+ *
+ * @return
+ *     - ESP_FAIL Parameter error
+ *     - ESP_OK   Success, result will be put in (*baudrate)
+ *
+ */
+esp_err_t uart_get_baudrate(uart_port_t uart_num, uint32_t* baudrate);
+
+/**
+ * @brief Set UART line inverse mode
+ *
+ * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param inverse_mask Choose the wires that need to be inverted.
+ *        Inverse_mask should be chosen from UART_INVERSE_RXD/UART_INVERSE_TXD/UART_INVERSE_RTS/UART_INVERSE_CTS, combine with OR operation.
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_set_line_inverse(uart_port_t uart_num, uint32_t inverse_mask);
+
+/**
+ * @brief Set hardware flow control.
+ *
+ * @param uart_num   UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param flow_ctrl Hardware flow control mode
+ * @param rx_thresh Threshold of Hardware RX flow control(0 ~ UART_FIFO_LEN).
+ *          Only when UART_HW_FLOWCTRL_RTS is set, will the rx_thresh value be set.
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_set_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t flow_ctrl, uint8_t rx_thresh);
+
+/**
+ * @brief Get hardware flow control mode
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param flow_ctrl Option for different flow control mode.
+ *
+ * @return
+ *     - ESP_FAIL Parameter error
+ *     - ESP_OK   Success, result will be put in (*flow_ctrl)
+ */
+esp_err_t uart_get_hw_flow_ctrl(uart_port_t uart_num, uart_hw_flowcontrol_t* flow_ctrl);
+
+/**
+ * @brief Clear UART interrupt status
+ *
+ * @param uart_num   UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param clr_mask  Bit mask of the status that to be cleared.
+ *                  enable_mask should be chosen from the fields of register UART_INT_CLR_REG.
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_clear_intr_status(uart_port_t uart_num, uint32_t clr_mask);
+
+/**
+ * @brief Set UART interrupt enable
+ *
+ * @param uart_num      UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param enable_mask  Bit mask of the enable bits.
+ *                     enable_mask should be chosen from the fields of register UART_INT_ENA_REG.
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_enable_intr_mask(uart_port_t uart_num, uint32_t enable_mask);
+
+/**
+ * @brief Clear UART interrupt enable bits
+ *
+ * @param uart_num       UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param disable_mask  Bit mask of the disable bits.
+ *                      disable_mask should be chosen from the fields of register UART_INT_ENA_REG.
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_disable_intr_mask(uart_port_t uart_num, uint32_t disable_mask);
+
+
+/**
+ * @brief Enable UART RX interrupt(RX_FULL & RX_TIMEOUT INTERRUPT)
+ *
+ * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_enable_rx_intr(uart_port_t uart_num);
+
+/**
+ * @brief Disable UART RX interrupt(RX_FULL & RX_TIMEOUT INTERRUPT)
+ *
+ * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_disable_rx_intr(uart_port_t uart_num);
+
+/**
+ * @brief Disable UART TX interrupt(RX_FULL & RX_TIMEOUT INTERRUPT)
+ *
+ * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_disable_tx_intr(uart_port_t uart_num);
+
+/**
+ * @brief Enable UART TX interrupt(RX_FULL & RX_TIMEOUT INTERRUPT)
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param enable  1: enable; 0: disable
+ * @param thresh  Threshold of TX interrupt, 0 ~ UART_FIFO_LEN
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh);
+
+/**
+ * @brief register UART interrupt handler(ISR).
+ *
+ * @note UART ISR handler will be attached to the same CPU core that this function is running on.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param fn  Interrupt handler function.
+ * @param arg parameter for handler function
+ * @param  intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+ *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info. 
+ * @param handle Pointer to return handle. If non-NULL, a handle for the interrupt will
+ *        be returned here.
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void*), void * arg, int intr_alloc_flags,  uart_isr_handle_t *handle);
+
+
+/**
+ * @brief Free UART interrupt handler registered by uart_isr_register. Must be called on the same core as
+ * uart_isr_register was called.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_isr_free(uart_port_t uart_num);
+
+/**
+ * @brief Set UART pin number
+ *
+ * @note Internal signal can be output to multiple GPIO pads.
+ * Only one GPIO pad can connect with input signal.
+ *
+ * @param uart_num    UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param tx_io_num  UART TX pin GPIO number, if set to UART_PIN_NO_CHANGE, use the current pin.
+ * @param rx_io_num  UART RX pin GPIO number, if set to UART_PIN_NO_CHANGE, use the current pin.
+ * @param rts_io_num UART RTS pin GPIO number, if set to UART_PIN_NO_CHANGE, use the current pin.
+ * @param cts_io_num UART CTS pin GPIO number, if set to UART_PIN_NO_CHANGE, use the current pin.
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num);
+
+/**
+ * @brief UART set RTS level (before inverse)
+ *          UART rx hardware flow control should not be set.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param level   1: RTS output low(active); 0: RTS output high(block)
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_set_rts(uart_port_t uart_num, int level);
+
+/**
+ * @brief UART set DTR level (before inverse)
+ *
+ * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param level    1: DTR output low; 0: DTR output high
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_set_dtr(uart_port_t uart_num, int level);
+
+/**
+* @brief UART parameter configure
+ *
+ * @param uart_num     UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param uart_config UART parameter settings
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_config);
+
+/**
+* @brief UART interrupt configure
+ *
+ * @param uart_num     UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param intr_conf UART interrupt settings
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_intr_config(uart_port_t uart_num, const uart_intr_config_t *intr_conf);
+
+/**
+ * @brief Install UART driver.
+ *
+ * UART ISR handler will be attached to the same CPU core that this function is running on.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param rx_buffer_size UART RX ring buffer size, rx_buffer_size should be greater than UART_FIFO_LEN.
+ * @param tx_buffer_size UART TX ring buffer size.
+ *        If set to zero, driver will not use TX buffer, TX function will block task until all data have been sent out..
+ *        @note tx_buffer_size should be greater than UART_FIFO_LEN.
+ *
+ * @param queue_size UART event queue size/depth.
+ * @param uart_queue UART event queue handle (out param). On success, a new queue handle is written here to provide
+ *        access to UART events. If set to NULL, driver will not use an event queue.
+ * @param  intr_alloc_flags Flags used to allocate the interrupt. One or multiple (ORred)
+ *            ESP_INTR_FLAG_* values. See esp_intr_alloc.h for more info. Do not set ESP_INTR_FLAG_IRAM here
+ *            (the driver's ISR handler is not located in IRAM)
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_buffer_size, int queue_size, espos_queue_t *uart_queue, int intr_alloc_flags);
+
+/**
+ * @brief Uninstall UART driver.
+ *
+ * @param uart_num  UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_driver_delete(uart_port_t uart_num);
+
+/**
+ * @brief Wait UART TX FIFO empty
+ *
+ * @param uart_num       UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param ticks_to_wait Timeout, count in RTOS ticks
+ *
+ * @return
+ *     - ESP_OK   Success
+ *     - ESP_FAIL Parameter error
+ *     - ESP_ERR_TIMEOUT  Timeout
+ */
+esp_err_t uart_wait_tx_done(uart_port_t uart_num, espos_tick_t ticks_to_wait);
+
+/**
+ * @brief Send data to the UART port from a given buffer and length.
+ * 
+ * This function will not wait for the space in TX FIFO, just fill the TX FIFO and return when the FIFO is full.
+ * @note This function should only be used when UART TX buffer is not enabled.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param buffer data buffer address
+ * @param len    data length to send
+ *
+ * @return
+ *     - (-1)  Parameter error
+ *     - OTHERS(>=0)  The number of data that pushed to the TX FIFO
+ */
+int uart_tx_chars(uart_port_t uart_num, const char* buffer, uint32_t len);
+
+/**
+ * @brief Send data to the UART port from a given buffer and length,
+ *
+ * If parameter tx_buffer_size is set to zero:
+ * This function will not return until all the data have been sent out, or at least pushed into TX FIFO.
+ *
+ * Otherwise, if tx_buffer_size > 0, this function will return after copying all the data to tx ringbuffer,
+ * then, UART ISR will move data from ring buffer to TX FIFO gradually.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param src   data buffer address
+ * @param size  data length to send
+ *
+ * @return
+ *     - (-1) Parameter error
+ *     - OTHERS(>=0)  The number of data that pushed to the TX FIFO
+ */
+int uart_write_bytes(uart_port_t uart_num, const char* src, size_t size);
+
+/**
+ * @brief Send data to the UART port from a given buffer and length,
+ *
+ * If parameter tx_buffer_size is set to zero:
+ * This function will not return until all the data and the break signal have been sent out.
+ * After all data send out, send a break signal.
+ *
+ * Otherwise, if tx_buffer_size > 0, this function will return after copying all the data to tx ringbuffer,
+ * then, UART ISR will move data from ring buffer to TX FIFO gradually.
+ * After all data send out, send a break signal.
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param src   data buffer address
+ * @param size  data length to send
+ * @param brk_len break signal length (unit: time of one data bit at current_baudrate)
+ *
+ * @return
+ *     - (-1) Parameter error
+ *     - OTHERS(>=0) The number of data that pushed to the TX FIFO
+ */
+
+int uart_write_bytes_with_break(uart_port_t uart_num, const char* src, size_t size, int brk_len);
+
+/**
+ * @brief UART read bytes from UART buffer
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ * @param buf     pointer to the buffer.
+ * @param length  data length
+ * @param ticks_to_wait sTimeout, count in RTOS ticks
+ *
+ * @return
+ *     - (-1) Error
+ *     - Others return a char data from uart fifo.
+ */
+int uart_read_bytes(uart_port_t uart_num, uint8_t* buf, uint32_t length, espos_tick_t ticks_to_wait);
+
+/**
+ * @brief UART ring buffer flush
+ *
+ * @param uart_num UART_NUM_0, UART_NUM_1 or UART_NUM_2
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_flush(uart_port_t uart_num);
+
+/**
+ * @brief   UART get RX ring buffer cached data length
+ *
+ * @param   uart_num UART port number.
+ * @param   size Pointer of size_t to accept cached data length
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_get_buffered_data_len(uart_port_t uart_num, size_t* size);
+
+/**
+ * @brief   UART disable pattern detect function.
+ *          Designed for applications like 'AT commands'.
+ *          When the hardware detect a series of one same character, the interrupt will be triggered.
+ *
+ * @param   uart_num UART port number.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_disable_pattern_det_intr(uart_port_t uart_num);
+
+/**
+ * @brief   UART enable pattern detect function.
+ *          Designed for applications like 'AT commands'.
+ *          When the hardware detect a series of one same character, the interrupt will be triggered.
+ *
+ * @param uart_num UART port number.
+ * @param pattern_chr character of the pattern
+ * @param chr_num number of the character, 8bit value.
+ * @param chr_tout timeout of the interval between each pattern characters, 24bit value, unit is APB(80Mhz) clock cycle.
+ * @param post_idle idle time after the last pattern character, 24bit value, unit is APB(80Mhz) clock cycle.
+ * @param pre_idle idle time before the first pattern character, 24bit value, unit is APB(80Mhz) clock cycle.
+ *
+ * @return
+ *     - ESP_OK Success
+ *     - ESP_FAIL Parameter error
+ */
+esp_err_t uart_enable_pattern_det_intr(uart_port_t uart_num, char pattern_chr, uint8_t chr_num, int chr_tout, int post_idle, int pre_idle);
+/***************************EXAMPLE**********************************
+ *
+ *
+ * ----------------EXAMPLE OF UART SETTING ---------------------
+ * @code{c}
+ * //1. Setup UART
+ * #include "freertos/queue.h"
+ * //a. Set UART parameter
+ * int uart_num = 0;                                       //uart port number
+ * uart_config_t uart_config = {
+ *    .baud_rate = 115200,                                 //baudrate
+ *    .data_bits = UART_DATA_8_BITS,                       //data bit mode
+ *    .parity = UART_PARITY_DISABLE,                       //parity mode
+ *    .stop_bits = UART_STOP_BITS_1,                       //stop bit mode
+ *    .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,               //hardware flow control(cts/rts)
+ *    .rx_flow_ctrl_thresh = 120,                          //flow control threshold
+ * };
+ * uart_param_config(uart_num, &uart_config);
+ * //b1. Setup UART driver(with UART queue)
+ * QueueHandle_t uart_queue;
+ * //parameters here are just an example, tx buffer size is 2048
+ * uart_driver_install(uart_num, 1024 * 2, 1024 * 2, 10, &uart_queue, 0);
+ * //b2. Setup UART driver(without UART queue)
+ * //parameters here are just an example, tx buffer size is 0
+ * uart_driver_install(uart_num, 1024 * 2, 0, 10, NULL, 0);
+ *@endcode
+ *-----------------------------------------------------------------------------*
+ * @code{c}
+ * //2. Set UART pin
+ * //set UART pin, not needed if use default pins.
+ * uart_set_pin(uart_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, 15, 13);
+ * @endcode
+ *-----------------------------------------------------------------------------*
+ * @code{c}
+ * //3. Read data from UART.
+ * uint8_t data[128];
+ * int length = 0;
+ * length = uart_read_bytes(uart_num, data, sizeof(data), 100);
+ * @endcode
+ *-----------------------------------------------------------------------------*
+ * @code{c}
+ * //4. Write data to UART.
+ * char* test_str = "This is a test string.\n"
+ * uart_write_bytes(uart_num, (const char*)test_str, strlen(test_str));
+ * @endcode
+ *-----------------------------------------------------------------------------*
+ * @code{c}
+ * //5. Write data to UART, end with a break signal.
+ * uart_write_bytes_with_break(0, "test break\n",strlen("test break\n"), 100);
+ * @endcode
+ *-----------------------------------------------------------------------------*
+ * @code{c}
+ * //6. an example of echo test with hardware flow control on UART1
+ * void uart_loop_back_test()
+ * {
+ *     int uart_num = 1;
+ *     uart_config_t uart_config = {
+ *         .baud_rate = 115200,
+ *         .data_bits = UART_DATA_8_BITS,
+ *         .parity = UART_PARITY_DISABLE,
+ *         .stop_bits = UART_STOP_BITS_1,
+ *         .flow_ctrl = UART_HW_FLOWCTRL_CTS_RTS,
+ *         .rx_flow_ctrl_thresh = 122,
+ *     };
+ *     //Configure UART1 parameters
+ *     uart_param_config(uart_num, &uart_config);
+ *     //Set UART1 pins(TX: IO16, RX: IO17, RTS: IO18, CTS: IO19)
+ *     uart_set_pin(uart_num, 16, 17, 18, 19);
+ *     //Install UART driver( We don't need an event queue here)
+ *     uart_driver_install(uart_num, 1024 * 2, 1024*4, 0, NULL, 0);
+ *     uint8_t data[1000];
+ *     while(1) {
+ *         //Read data from UART
+ *         int len = uart_read_bytes(uart_num, data, sizeof(data), 10);
+ *         //Write data back to UART
+ *         uart_write_bytes(uart_num, (const char*)data, len);
+ *     }
+ * }
+ * @endcode
+ *-----------------------------------------------------------------------------*
+ * @code{c}
+ * //7. An example of using UART event queue on UART0.
+ * #include "freertos/queue.h"
+ * //A queue to handle UART event.
+ * QueueHandle_t uart0_queue;
+ * static const char *TAG = "uart_example";
+ * void uart_task(void *pvParameters)
+ * {
+ *     int uart_num = (int)pvParameters;
+ *     uart_event_t event;
+ *     size_t size = 1024;
+ *     uint8_t* dtmp = (uint8_t*)malloc(size);
+ *     for(;;) {
+ *         //Waiting for UART event.
+ *         if(xQueueReceive(uart0_queue, (void * )&event, (portTickType)portMAX_DELAY)) {
+ *             ESP_LOGI(TAG, "uart[%d] event:", uart_num);
+ *             switch(event.type) {
+ *                 memset(dtmp, 0, size);
+ *                 //Event of UART receving data
+ *                 case UART_DATA:
+ *                     ESP_LOGI(TAG,"data, len: %d", event.size);
+ *                     int len = uart_read_bytes(uart_num, dtmp, event.size, 10);
+ *                     ESP_LOGI(TAG, "uart read: %d", len);
+ *                     break;
+ *                 //Event of HW FIFO overflow detected
+ *                 case UART_FIFO_OVF:
+ *                     ESP_LOGI(TAG, "hw fifo overflow\n");
+ *                     break;
+ *                 //Event of UART ring buffer full
+ *                 case UART_BUFFER_FULL:
+ *                     ESP_LOGI(TAG, "ring buffer full\n");
+ *                     break;
+ *                 //Event of UART RX break detected
+ *                 case UART_BREAK:
+ *                     ESP_LOGI(TAG, "uart rx break\n");
+ *                     break;
+ *                 //Event of UART parity check error
+ *                 case UART_PARITY_ERR:
+ *                     ESP_LOGI(TAG, "uart parity error\n");
+ *                     break;
+ *                 //Event of UART frame error
+ *                 case UART_FRAME_ERR:
+ *                     ESP_LOGI(TAG, "uart frame error\n");
+ *                     break;
+ *                 //Others
+ *                 default:
+ *                     ESP_LOGI(TAG, "uart event type: %d\n", event.type);
+ *                     break;
+ *             }
+ *        }
+ *     }
+ *     free(dtmp);
+ *     dtmp = NULL;
+ *     vTaskDelete(NULL);
+ * }
+ *
+ * void uart_queue_test()
+ * {
+ *     int uart_num = 0;
+ *     uart_config_t uart_config = {
+ *        .baud_rate = 115200,
+ *        .data_bits = UART_DATA_8_BITS,
+ *        .parity = UART_PARITY_DISABLE,
+ *        .stop_bits = UART_STOP_BITS_1,
+ *        .flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
+ *        .rx_flow_ctrl_thresh = 122,
+ *     };
+ *     //Set UART parameters
+ *     uart_param_config(uart_num, &uart_config);
+ *     //Set UART pins,(-1: default pin, no change.)
+ *     uart_set_pin(uart_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
+ *     //Set UART log level
+ *     esp_log_level_set(TAG, ESP_LOG_INFO);
+ *     //Install UART driver, and get the queue.
+ *     uart_driver_install(uart_num, 1024 * 2, 1024*4, 10, &uart0_queue, 0);
+ *     //Create a task to handler UART event from ISR
+ *     xTaskCreate(uart_task, "uTask", 1024, (void*)uart_num, 10, NULL);
+ * }
+ * @endcode
+ *
+ ***************************END OF EXAMPLE**********************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_DRIVER_UART_H_*/

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_assert.h

@@ -0,0 +1,37 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __ESP_ASSERT_H__
+#define __ESP_ASSERT_H__
+
+#include "assert.h"
+
+/* Assert at compile time if possible, runtime otherwise */
+#ifndef __cplusplus
+/* __builtin_choose_expr() is only in C, makes this a lot cleaner */
+#define TRY_STATIC_ASSERT(CONDITION, MSG) do {                                                              \
+            _Static_assert(__builtin_choose_expr(__builtin_constant_p(CONDITION), (CONDITION), 1), #MSG);   \
+            assert(#MSG && (CONDITION));                                                                    \
+        } while(0)
+#else
+/* for C++, use __attribute__((error)) - works almost as well as _Static_assert */
+#define TRY_STATIC_ASSERT(CONDITION, MSG) do {                                                              \
+            if (__builtin_constant_p(CONDITION) && !(CONDITION)) {          \
+                extern __attribute__((error(#MSG))) void failed_compile_time_assert(void);      \
+                failed_compile_time_assert();                                                   \
+            }                                                                                   \
+            assert(#MSG && (CONDITION));                                                                    \
+        } while(0)
+#endif /* __cplusplus */
+
+#endif /* __ESP_ASSERT_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_attr.h

@@ -0,0 +1,44 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __ESP_ATTR_H__
+#define __ESP_ATTR_H__
+
+#define ROMFN_ATTR
+
+//Normally, the linker script will put all code and rodata in flash,
+//and all variables in shared RAM. These macros can be used to redirect
+//particular functions/variables to other memory regions.
+
+// Forces code into IRAM instead of flash.
+#define IRAM_ATTR __attribute__((section(".iram1")))
+
+// Forces data into DRAM instead of flash
+#define DRAM_ATTR __attribute__((section(".dram1")))
+
+// Forces a string into DRAM instead of flash
+// Use as ets_printf(DRAM_STR("Hello world!\n"));
+#define DRAM_STR(str) (__extension__({static const DRAM_ATTR char __c[] = (str); (const char *)&__c;}))
+
+// Forces code into RTC fast memory. See "docs/deep-sleep-stub.rst"
+#define RTC_IRAM_ATTR __attribute__((section(".rtc.text")))
+
+// Forces data into RTC slow memory. See "docs/deep-sleep-stub.rst"
+// Any variable marked with this attribute will keep its value
+// during a deep sleep / wake cycle.
+#define RTC_DATA_ATTR __attribute__((section(".rtc.data")))
+
+// Forces read-only data into RTC slow memory. See "docs/deep-sleep-stub.rst"
+#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata")))
+
+#endif /* __ESP_ATTR_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_brownout.h

@@ -0,0 +1,21 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef __ESP_BROWNOUT_H
+#define __ESP_BROWNOUT_H
+
+void esp_brownout_init();
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_cache_err_int.h

@@ -0,0 +1,33 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+/**
+ * @brief initialize cache invalid access interrupt
+ *
+ * This function enables cache invalid access interrupt source and connects it
+ * to interrupt input number ETS_CACHEERR_INUM (see soc/soc.h). It is called
+ * from the startup code.
+ */
+void esp_cache_err_int_init();
+
+
+/**
+ * @brief get the CPU which caused cache invalid access interrupt
+ * @return
+ *  - PRO_CPU_NUM, if PRO_CPU has caused cache IA interrupt
+ *  - APP_CPU_NUM, if APP_CPU has caused cache IA interrupt
+ *  - (-1) otherwise
+ */
+int esp_cache_err_get_cpuid();

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_clk.h

@@ -0,0 +1,64 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file esp_clk.h
+ *
+ * This file contains declarations of clock related functions.
+ * These functions are used in ESP-IDF components, but should not be considered
+ * to be part of public API.
+ */
+
+/**
+ * @brief Initialize clock-related settings
+ *
+ * Called from cpu_start.c, not intended to be called from other places.
+ * This function configures the CPU clock, RTC slow and fast clocks, and
+ * performs RTC slow clock calibration.
+ */
+void esp_clk_init(void);
+
+
+/**
+ * @brief Get the calibration value of RTC slow clock
+ *
+ * The value is in the same format as returned by rtc_clk_cal (microseconds,
+ * in Q13.19 fixed-point format).
+ *
+ * @return the calibration value obtained using rtc_clk_cal, at startup time
+ */
+uint32_t esp_clk_slowclk_cal_get();
+
+
+/**
+ * @brief Update the calibration value of RTC slow clock
+ *
+ * The value has to be in the same format as returned by rtc_clk_cal (microseconds,
+ * in Q13.19 fixed-point format).
+ * This value is used by timekeeping functions (such as gettimeofday) to
+ * calculate current time based on RTC counter value.
+ * @param value calibration value obtained using rtc_clk_cal
+ */
+void esp_clk_slowclk_cal_set(uint32_t value);
+
+/**
+ * @brief Disables clock of some peripherals
+ *
+ * Called from cpu_start.c, not intended to be called from other places.
+ * This function disables clock of useless peripherals when cpu starts.
+ */
+void esp_perip_clk_init(void);
+

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_coexist.h

@@ -0,0 +1,51 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Init software coexist
+ *
+ * @return Init ok or failed.
+ */
+esp_err_t coex_init(void);
+
+/**
+ * @brief De-init software coexist
+ */
+void coex_deinit(void);
+
+/**
+ * @brief Get software coexist enable or not
+ *
+ * @return software coexist enable status.
+ */
+bool coexist_get_enable(void);
+
+/**
+ * @brief Set software coexist enable or not
+ *
+ * @param enable software coexist or disable it
+ *
+ * @return Void.
+ */
+void coexist_set_enable(bool enable);
+
+#ifdef __cplusplus
+}
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_core_dump.h

@@ -0,0 +1,64 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef ESP_CORE_DUMP_H_
+#define ESP_CORE_DUMP_H_
+
+/**
+ * @brief  Initializes core dump module internal data.
+ *
+ * @note  Should be called at system startup.
+ */
+void esp_core_dump_init();
+
+/**
+ * @brief  Saves core dump to flash.
+ *
+ * The structure of data stored in flash is as follows:
+ * |   MAGIC1   |
+ * |  TOTAL_LEN |  TASKS_NUM | TCB_SIZE |
+ * | TCB_ADDR_1 | STACK_TOP_1 | STACK_END_1 | TCB_1 | STACK_1 |
+ * .            .       .         .
+ * .            .       .         .
+ * | TCB_ADDR_N | STACK_TOP_N | STACK_END_N | TCB_N | STACK_N |
+ * |   MAGIC2   |
+ * Core dump in flash consists of header and data for every task in the system at the moment of crash.
+ * For flash data integrity control two magic numbers are used at the beginning and the end of core dump.
+ * The structure of core dump data is described below in details.
+ * 1) MAGIC1 and MAGIC2 are special numbers stored at the beginning and the end of core dump.
+ *    They are used to control core dump data integrity. Size of every number is 4 bytes.
+ * 2) Core dump starts with header:
+ * 2.1) TOTAL_LEN is total length of core dump data in flash including magic numbers. Size is 4 bytes.
+ * 2.2) TASKS_NUM is the number of tasks for which data are stored. Size is 4 bytes.
+ * 2.3) TCB_SIZE is the size of task's TCB structure. Size is 4 bytes.
+ * 3) Core dump header is followed by the data for every task in the system.
+ *    Task data are started with task header:
+ * 3.1) TCB_ADDR is the address of TCB in memory. Size is 4 bytes.
+ * 3.2) STACK_TOP is the top of task's stack (address of the topmost stack item). Size is 4 bytes.
+ * 3.2) STACK_END is the end of task's stack (address from which task's stack starts). Size is 4 bytes.
+ * 4) Task header is followed by TCB data. Size is TCB_SIZE bytes.
+ * 5) Task's stack is placed after TCB data. Size is (STACK_END - STACK_TOP) bytes.
+ */
+void esp_core_dump_to_flash();
+
+/**
+ * @brief  Print base64-encoded core dump to UART.
+ *
+ * The structure of core dump data is the same as for data stored in flash (@see esp_core_dump_to_flash) with some notes:
+ * 1) Magic numbers are not present in core dump printed to UART.
+ * 2) Since magic numbers are omitted TOTAL_LEN does not include their size.
+ * 3) Printed base64 data are surrounded with special messages to help user recognize the start and end of actual data.
+ */
+void esp_core_dump_to_uart();
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_crosscore_int.h

@@ -0,0 +1,42 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __ESP_CROSSCORE_INT_H
+#define __ESP_CROSSCORE_INT_H
+
+
+/**
+ * Initialize the crosscore interrupt system for this CPU.
+ * This needs to be called once on every CPU that is used
+ * by FreeRTOS.
+ *
+ * If multicore FreeRTOS support is enabled, this will be
+ * called automatically by the startup code and should not
+ * be called manually.
+ */
+void esp_crosscore_int_init();
+
+
+/**
+ * Send an interrupt to a CPU indicating it should yield its
+ * currently running task in favour of a higher-priority task
+ * that presumably just woke up.
+ *
+ * This is used internally by FreeRTOS in multicore mode
+ * and should not be called by the user.
+ *
+ * @param coreID Core that should do the yielding
+ */
+void esp_crosscore_int_send_yield(int coreId);
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_deep_sleep.h

@@ -0,0 +1,94 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file esp_deep_sleep.h
+ * @brief legacy definitions of esp_deep_sleep APIs
+ *
+ * This file provides compatibility for applications using esp_deep_sleep_* APIs.
+ * New applications should use functions defined in "esp_sleep.h" instead.
+ * These functions and types will be deprecated at some point.
+ */
+
+#warning esp_deep_sleep.h will be deprecated in the next release. Use esp_sleep.h instead.
+
+#include "esp_sleep.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef esp_sleep_pd_domain_t esp_deep_sleep_pd_domain_t;
+typedef esp_sleep_pd_option_t esp_deep_sleep_pd_option_t;
+typedef esp_sleep_ext1_wakeup_mode_t esp_ext1_wakeup_mode_t;
+typedef esp_sleep_wakeup_cause_t esp_deep_sleep_wakeup_cause_t;
+
+inline static esp_err_t esp_deep_sleep_enable_ulp_wakeup(void)
+{
+    return esp_sleep_enable_ulp_wakeup();
+}
+
+inline static esp_err_t esp_deep_sleep_enable_timer_wakeup(uint64_t time_in_us)
+{
+    return esp_sleep_enable_timer_wakeup(time_in_us);
+}
+
+inline static esp_err_t esp_deep_sleep_enable_touchpad_wakeup(void)
+{
+    return esp_sleep_enable_touchpad_wakeup();
+}
+
+inline static touch_pad_t esp_deep_sleep_get_touchpad_wakeup_status()
+{
+    return esp_sleep_get_touchpad_wakeup_status();
+}
+
+inline static esp_err_t esp_deep_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
+{
+    return esp_sleep_enable_ext0_wakeup(gpio_num, level);
+}
+
+inline static esp_err_t esp_deep_sleep_enable_ext1_wakeup(uint64_t mask, esp_ext1_wakeup_mode_t mode)
+{
+    return esp_sleep_enable_ext1_wakeup(mask, mode);
+}
+
+inline static esp_err_t esp_deep_sleep_pd_config(
+        esp_deep_sleep_pd_domain_t domain,
+        esp_deep_sleep_pd_option_t option)
+{
+    return esp_sleep_pd_config(domain, option);
+}
+
+inline static esp_deep_sleep_wakeup_cause_t esp_deep_sleep_get_wakeup_cause()
+{
+    return esp_sleep_get_wakeup_cause();
+}
+
+#define ESP_DEEP_SLEEP_WAKEUP_UNDEFINED     ESP_SLEEP_WAKEUP_UNDEFINED
+#define ESP_DEEP_SLEEP_WAKEUP_EXT0          ESP_SLEEP_WAKEUP_EXT0
+#define ESP_DEEP_SLEEP_WAKEUP_EXT1          ESP_SLEEP_WAKEUP_EXT1
+#define ESP_DEEP_SLEEP_WAKEUP_TIMER         ESP_SLEEP_WAKEUP_TIMER
+#define ESP_DEEP_SLEEP_WAKEUP_TOUCHPAD      ESP_SLEEP_WAKEUP_TOUCHPAD
+#define ESP_DEEP_SLEEP_WAKEUP_ULP           ESP_SLEEP_WAKEUP_ULP
+
+
+
+#ifdef __cplusplus
+}
+#endif
+

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_deepsleep.h

@@ -0,0 +1,2 @@
+#warning esp_deepsleep.h has been renamed to esp_sleep.h, please update include directives
+#include "esp_sleep.h"

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_dport_access.h

@@ -0,0 +1,42 @@
+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <sdkconfig.h>
+
+#ifndef _ESP_DPORT_ACCESS_H_
+#define _ESP_DPORT_ACCESS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void esp_dport_access_stall_other_cpu_start(void);
+void esp_dport_access_stall_other_cpu_end(void);
+void esp_dport_access_int_init(void);
+void esp_dport_access_int_pause(void);
+void esp_dport_access_int_resume(void);
+
+#if defined(BOOTLOADER_BUILD) || defined(CONFIG_FREERTOS_UNICORE) || !defined(ESP_PLATFORM)
+#define DPORT_STALL_OTHER_CPU_START()
+#define DPORT_STALL_OTHER_CPU_END()
+#else
+#define DPORT_STALL_OTHER_CPU_START()   esp_dport_access_stall_other_cpu_start()
+#define DPORT_STALL_OTHER_CPU_END()     esp_dport_access_stall_other_cpu_end()
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ESP_DPORT_ACCESS_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_err.h

@@ -0,0 +1,82 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include <stdint.h>
+#include <stdio.h>
+#include <assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef int32_t esp_err_t;
+
+/* Definitions for error constants. */
+
+#define ESP_OK          0
+#define ESP_FAIL        -1
+
+#define ESP_ERR_NO_MEM          0x101
+#define ESP_ERR_INVALID_ARG     0x102
+#define ESP_ERR_INVALID_STATE   0x103
+#define ESP_ERR_INVALID_SIZE    0x104
+#define ESP_ERR_NOT_FOUND       0x105
+#define ESP_ERR_NOT_SUPPORTED   0x106
+#define ESP_ERR_TIMEOUT         0x107
+#define ESP_ERR_INVALID_RESPONSE    0x108
+#define ESP_ERR_INVALID_CRC     0x109
+#define ESP_ERR_INVALID_VERSION     0x10A
+#define ESP_ERR_INVALID_MAC     0x10B
+
+#define ESP_ERR_WIFI_BASE       0x3000 /*!< Starting number of WiFi error codes */
+
+void _esp_error_check_failed(esp_err_t rc, const char *file, int line, const char *function, const char *expression) __attribute__((noreturn));
+
+#ifndef __ASSERT_FUNC
+/* This won't happen on IDF, which defines __ASSERT_FUNC in assert.h, but it does happen when building on the host which
+   uses /usr/include/assert.h or equivalent.
+*/
+#ifdef __ASSERT_FUNCTION
+#define __ASSERT_FUNC __ASSERT_FUNCTION /* used in glibc assert.h */
+#else
+#define __ASSERT_FUNC "??"
+#endif
+#endif
+
+/**
+ * Macro which can be used to check the error code,
+ * and terminate the program in case the code is not ESP_OK.
+ * Prints the error code, error location, and the failed statement to serial output.
+ *
+ * Disabled if assertions are disabled.
+ */
+#ifdef NDEBUG
+#define ESP_ERROR_CHECK(x) do {                                         \
+        esp_err_t rc = (x);                                             \
+        (void) sizeof(rc);                                              \
+    } while(0);
+#else
+#define ESP_ERROR_CHECK(x) do {                                         \
+        esp_err_t rc = (x);                                             \
+        if (rc != ESP_OK) {                                             \
+            _esp_error_check_failed(rc, __FILE__, __LINE__,             \
+                                    __ASSERT_FUNC, #x);                 \
+        }                                                               \
+    } while(0);
+#endif
+
+#ifdef __cplusplus
+}
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_event.h

@@ -0,0 +1,180 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_EVENT_H__
+#define __ESP_EVENT_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "esp_err.h"
+#include "esp_wifi_types.h"
+#include "tcpip_adapter.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    SYSTEM_EVENT_WIFI_READY = 0,           /**< ESP32 WiFi ready */
+    SYSTEM_EVENT_SCAN_DONE,                /**< ESP32 finish scanning AP */
+    SYSTEM_EVENT_STA_START,                /**< ESP32 station start */
+    SYSTEM_EVENT_STA_STOP,                 /**< ESP32 station stop */
+    SYSTEM_EVENT_STA_CONNECTED,            /**< ESP32 station connected to AP */
+    SYSTEM_EVENT_STA_DISCONNECTED,         /**< ESP32 station disconnected from AP */
+    SYSTEM_EVENT_STA_AUTHMODE_CHANGE,      /**< the auth mode of AP connected by ESP32 station changed */
+    SYSTEM_EVENT_STA_GOT_IP,               /**< ESP32 station got IP from connected AP */
+    SYSTEM_EVENT_STA_LOST_IP,              /**< ESP32 station lost IP and the IP is reset to 0 */
+    SYSTEM_EVENT_STA_WPS_ER_SUCCESS,       /**< ESP32 station wps succeeds in enrollee mode */
+    SYSTEM_EVENT_STA_WPS_ER_FAILED,        /**< ESP32 station wps fails in enrollee mode */
+    SYSTEM_EVENT_STA_WPS_ER_TIMEOUT,       /**< ESP32 station wps timeout in enrollee mode */
+    SYSTEM_EVENT_STA_WPS_ER_PIN,           /**< ESP32 station wps pin code in enrollee mode */
+    SYSTEM_EVENT_AP_START,                 /**< ESP32 soft-AP start */
+    SYSTEM_EVENT_AP_STOP,                  /**< ESP32 soft-AP stop */
+    SYSTEM_EVENT_AP_STACONNECTED,          /**< a station connected to ESP32 soft-AP */
+    SYSTEM_EVENT_AP_STADISCONNECTED,       /**< a station disconnected from ESP32 soft-AP */
+    SYSTEM_EVENT_AP_PROBEREQRECVED,        /**< Receive probe request packet in soft-AP interface */
+    SYSTEM_EVENT_AP_STA_GOT_IP6,           /**< ESP32 station or ap interface v6IP addr is preferred */
+    SYSTEM_EVENT_ETH_START,                /**< ESP32 ethernet start */
+    SYSTEM_EVENT_ETH_STOP,                 /**< ESP32 ethernet stop */
+    SYSTEM_EVENT_ETH_CONNECTED,            /**< ESP32 ethernet phy link up */
+    SYSTEM_EVENT_ETH_DISCONNECTED,         /**< ESP32 ethernet phy link down */
+    SYSTEM_EVENT_ETH_GOT_IP,               /**< ESP32 ethernet got IP from connected AP */
+    SYSTEM_EVENT_MAX
+} system_event_id_t;
+
+typedef enum {
+    WPS_FAIL_REASON_NORMAL = 0,                   /**< ESP32 WPS normal fail reason */
+    WPS_FAIL_REASON_RECV_M2D,                       /**< ESP32 WPS receive M2D frame */
+    WPS_FAIL_REASON_MAX
+}system_event_sta_wps_fail_reason_t;
+typedef struct {
+    uint32_t status;          /**< status of scanning APs */
+    uint8_t  number;
+    uint8_t  scan_id;
+} system_event_sta_scan_done_t;
+
+typedef struct {
+    uint8_t ssid[32];         /**< SSID of connected AP */
+    uint8_t ssid_len;         /**< SSID length of connected AP */
+    uint8_t bssid[6];         /**< BSSID of connected AP*/
+    uint8_t channel;          /**< channel of connected AP*/
+    wifi_auth_mode_t authmode;
+} system_event_sta_connected_t;
+
+typedef struct {
+    uint8_t ssid[32];         /**< SSID of disconnected AP */
+    uint8_t ssid_len;         /**< SSID length of disconnected AP */
+    uint8_t bssid[6];         /**< BSSID of disconnected AP */
+    uint8_t reason;           /**< reason of disconnection */
+} system_event_sta_disconnected_t;
+
+typedef struct {
+    wifi_auth_mode_t old_mode;         /**< the old auth mode of AP */
+    wifi_auth_mode_t new_mode;         /**< the new auth mode of AP */
+} system_event_sta_authmode_change_t;
+
+typedef struct {
+    tcpip_adapter_ip_info_t ip_info;
+    bool ip_changed;
+} system_event_sta_got_ip_t;
+
+typedef struct {
+    uint8_t pin_code[8];         /**< PIN code of station in enrollee mode */
+} system_event_sta_wps_er_pin_t;
+
+typedef struct {
+    tcpip_adapter_ip6_info_t ip6_info;
+} system_event_ap_sta_got_ip6_t;
+
+typedef struct {
+    uint8_t mac[6];           /**< MAC address of the station connected to ESP32 soft-AP */
+    uint8_t aid;              /**< the aid that ESP32 soft-AP gives to the station connected to  */
+} system_event_ap_staconnected_t;
+
+typedef struct {
+    uint8_t mac[6];           /**< MAC address of the station disconnects to ESP32 soft-AP */
+    uint8_t aid;              /**< the aid that ESP32 soft-AP gave to the station disconnects to  */
+} system_event_ap_stadisconnected_t;
+
+typedef struct {
+    int rssi;                 /**< Received probe request signal strength */
+    uint8_t mac[6];           /**< MAC address of the station which send probe request */
+} system_event_ap_probe_req_rx_t;
+
+typedef union {
+    system_event_sta_connected_t               connected;          /**< ESP32 station connected to AP */
+    system_event_sta_disconnected_t            disconnected;       /**< ESP32 station disconnected to AP */
+    system_event_sta_scan_done_t               scan_done;          /**< ESP32 station scan (APs) done */
+    system_event_sta_authmode_change_t         auth_change;        /**< the auth mode of AP ESP32 station connected to changed */
+    system_event_sta_got_ip_t                  got_ip;             /**< ESP32 station got IP, first time got IP or when IP is changed */
+    system_event_sta_wps_er_pin_t              sta_er_pin;         /**< ESP32 station WPS enrollee mode PIN code received */
+    system_event_sta_wps_fail_reason_t         sta_er_fail_reason;/**< ESP32 station WPS enrollee mode failed reason code received */
+    system_event_ap_staconnected_t             sta_connected;      /**< a station connected to ESP32 soft-AP */
+    system_event_ap_stadisconnected_t          sta_disconnected;   /**< a station disconnected to ESP32 soft-AP */
+    system_event_ap_probe_req_rx_t             ap_probereqrecved;  /**< ESP32 soft-AP receive probe request packet */
+    system_event_ap_sta_got_ip6_t              got_ip6;            /**< ESP32 station or ap ipv6 addr state change to preferred */
+} system_event_info_t;
+
+typedef struct {
+    system_event_id_t     event_id;      /**< event ID */
+    system_event_info_t   event_info;    /**< event information */
+} system_event_t;
+
+typedef esp_err_t (*system_event_handler_t)(system_event_t *event);
+
+/**
+  * @brief  Send a event to event task
+  *
+  * @attention 1. Other task/modules, such as the TCPIP module, can call this API to send an event to event task
+  *
+  * @param  system_event_t * event : event
+  *
+  * @return ESP_OK : succeed
+  * @return others : fail
+  */
+esp_err_t esp_event_send(system_event_t *event);
+
+/**
+  * @brief  Default event handler for system events
+  *
+  * This function performs default handling of system events.
+  * When using esp_event_loop APIs, it is called automatically before invoking the user-provided
+  * callback function.
+  *
+  * Applications which implement a custom event loop must call this function
+  * as part of event processing.
+  *
+  * @param  event pointer to event to be handled
+  * @return ESP_OK if an event was handled successfully
+  */
+esp_err_t esp_event_process_default(system_event_t *event);
+
+/**
+  * @brief  Install default event handlers for Ethernet interface
+  *
+  */
+void esp_event_set_default_eth_handlers();
+
+/**
+  * @brief  Install default event handlers for Wi-Fi interfaces (station and AP)
+  *
+  */
+void esp_event_set_default_wifi_handlers();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_EVENT_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_event_loop.h

@@ -0,0 +1,81 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_EVENT_LOOP_H__
+#define __ESP_EVENT_LOOP_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "espos_queue.h"
+
+#include "esp_err.h"
+#include "esp_event.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+  * @brief  Application specified event callback function
+  *
+  * @param  void *ctx : reserved for user
+  * @param  system_event_t *event : event type defined in this file
+  *
+  * @return ESP_OK : succeed
+  * @return others : fail
+  */
+typedef esp_err_t (*system_event_cb_t)(void *ctx, system_event_t *event);
+
+/**
+  * @brief  Initialize event loop
+  *         Create the event handler and task
+  *
+  * @param  system_event_cb_t cb : application specified event callback, it can be modified by call esp_event_set_cb
+  * @param  void *ctx : reserved for user
+  *
+  * @return ESP_OK : succeed
+  * @return others : fail
+  */
+esp_err_t esp_event_loop_init(system_event_cb_t cb, void *ctx);
+
+/**
+  * @brief  Set application specified event callback function
+  *
+  * @attention 1. If cb is NULL, means application don't need to handle
+  *               If cb is not NULL, it will be call when an event is received, after the default event callback is completed
+  *
+  * @param  system_event_cb_t cb : callback
+  * @param  void *ctx : reserved for user
+  *
+  * @return system_event_cb_t : old callback
+  */
+system_event_cb_t esp_event_loop_set_cb(system_event_cb_t cb, void *ctx);
+
+/**
+  * @brief  Get the queue used by event loop
+  *
+  * @attention : currently this API is used to initialize "q" parameter
+  * of wifi_init structure.
+  *
+  * @return QueueHandle_t : event queue handle
+  */
+espos_queue_t esp_event_loop_get_queue(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_EVENT_LOOP_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_flash_data_types.h

@@ -0,0 +1,73 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __ESP_BIN_TYPES_H__
+#define __ESP_BIN_TYPES_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define ESP_PARTITION_TABLE_ADDR 0x8000
+#define ESP_PARTITION_MAGIC 0x50AA
+
+/* OTA selection structure (two copies in the OTA data partition.)
+   Size of 32 bytes is friendly to flash encryption */
+typedef struct {
+    uint32_t ota_seq;
+    uint8_t  seq_label[24];
+    uint32_t crc; /* CRC32 of ota_seq field only */
+} esp_ota_select_entry_t;
+
+
+typedef struct {
+    uint32_t offset;
+    uint32_t size;
+} esp_partition_pos_t;
+
+/* Structure which describes the layout of partition table entry.
+ * See docs/partition_tables.rst for more information about individual fields.
+ */
+typedef struct {
+	uint16_t magic;
+	uint8_t  type;
+    uint8_t  subtype;
+    esp_partition_pos_t pos;
+	uint8_t  label[16];
+    uint32_t flags;
+} esp_partition_info_t;
+
+#define PART_TYPE_APP 0x00
+#define PART_SUBTYPE_FACTORY  0x00
+#define PART_SUBTYPE_OTA_FLAG 0x10
+#define PART_SUBTYPE_OTA_MASK 0x0f
+#define PART_SUBTYPE_TEST     0x20
+
+#define PART_TYPE_DATA 0x01
+#define PART_SUBTYPE_DATA_OTA 0x00
+#define PART_SUBTYPE_DATA_RF  0x01
+#define PART_SUBTYPE_DATA_WIFI 0x02
+
+#define PART_TYPE_END 0xff
+#define PART_SUBTYPE_END 0xff
+
+#define PART_FLAG_ENCRYPTED (1<<0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__ESP_BIN_TYPES_H__

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_freertos_hooks.h

@@ -0,0 +1,83 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_FREERTOS_HOOKS_H__
+#define __ESP_FREERTOS_HOOKS_H__
+
+#include <stdbool.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*
+ Definitions for the tickhook and idlehook callbacks
+*/
+typedef bool (*esp_freertos_idle_cb_t)();
+typedef void (*esp_freertos_tick_cb_t)();
+
+/**
+  * @brief  Register a callback to be called on the freertos idle hook
+  *         The callback should return true if it's okay for the core to
+  *         sleep until an interrupt (or FreeRTOS tick) happens and false
+  *         if it should be called again as fast as possible.
+  *
+  * @warning Idle callbacks MUST NOT, UNDER ANY CIRCUMSTANCES, CALL 
+  *          A FUNCTION THAT MIGHT BLOCK.
+  *
+  * @param  esp_freertos_idle_cb_t new_idle_cb : Callback to be called
+  *
+  * @return ESP_OK : Callback registered
+  * @return ESP_ERR_NO_MEM : No more space to register hook
+  */
+esp_err_t esp_register_freertos_idle_hook(esp_freertos_idle_cb_t new_idle_cb);
+
+/**
+  * @brief  Register a callback to be called on the freertos tick hook
+  *
+  * @param  esp_freertos_tick_cb_t new_tick_cb : Callback to be called
+  *
+  * @return ESP_OK : Callback registered
+  * @return ESP_ERR_NO_MEM : No more space to register hook
+  */
+esp_err_t esp_register_freertos_tick_hook(esp_freertos_tick_cb_t tick_cb);
+
+
+/**
+  * @brief  Unregister an idle callback registered earlier
+  *
+  * @param  esp_freertos_idle_cb_t new_idle_cb : Callback to be unregistered
+  *
+  * @return void
+  */
+void esp_deregister_freertos_idle_hook(esp_freertos_idle_cb_t old_idle_cb);
+
+
+/**
+  * @brief  Unregister a tick callback registered earlier
+  *
+  * @param  esp_freertos_idle_cb_t new_idle_cb : Callback to be unregistered
+  *
+  * @return void
+  */
+void esp_deregister_freertos_tick_hook(esp_freertos_tick_cb_t old_tick_cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_gdbstub.h

@@ -0,0 +1,22 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef GDBSTUB_H
+#define GDBSTUB_H
+
+#include <xtensa/config/core.h>
+#include "freertos/xtensa_api.h"
+
+void esp_gdbstub_panic_handler(XtExcFrame *frame) __attribute__((noreturn));
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_int_wdt.h

@@ -0,0 +1,57 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_INT_WDT_H
+#define __ESP_INT_WDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Watchdog_APIs
+  * @{
+  */
+
+/*
+This routine enables a watchdog to catch instances of processes disabling
+interrupts for too long, or code within interrupt handlers taking too long. 
+It does this by setting up a watchdog which gets fed from the FreeRTOS
+task switch interrupt. When this watchdog times out, initially it will call
+a high-level interrupt routine that will panic FreeRTOS in order to allow
+for forensic examination of the state of the CPU. When this interrupt 
+handler is not called and the watchdog times out a second time, it will 
+reset the SoC.
+
+This uses the TIMERG1 WDT.
+*/
+
+
+/**
+  * @brief  Initialize the interrupt watchdog. This is called in the init code if
+  *         the interrupt watchdog is enabled in menuconfig.
+  *
+  */
+void esp_int_wdt_init();
+
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_interface.h

@@ -0,0 +1,37 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef __ESP_INTERFACE_H__
+#define __ESP_INTERFACE_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ESP_IF_WIFI_STA = 0,     /**< ESP32 station interface */
+    ESP_IF_WIFI_AP,          /**< ESP32 soft-AP interface */
+    ESP_IF_ETH,              /**< ESP32 ethernet interface */
+    ESP_IF_MAX
+} esp_interface_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __ESP_INTERFACE_TYPES_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_intr.h

@@ -0,0 +1,89 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_INTR_H__
+#define __ESP_INTR_H__
+
+#include "rom/ets_sys.h"
+#include "freertos/xtensa_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ESP_CCOMPARE_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_CCOMPARE_INUM, (func), (void *)(arg))
+
+#define ESP_EPWM_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_EPWM_INUM, (func), (void *)(arg))
+
+#define ESP_MPWM_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_MPWM_INUM, (func), (void *)(arg))
+
+#define ESP_SPI1_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_SPI1_INUM, (func), (void *)(arg))
+
+#define ESP_SPI2_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_SPI2_INUM, (func), (void *)(arg))
+
+#define ESP_SPI3_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_SPI3_INUM, (func), (void *)(arg))
+
+#define ESP_I2S0_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_I2S0_INUM, (func), (void *)(arg))
+
+#define ESP_PCNT_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_PCNT_INUM, (func), (void *)(arg))
+
+#define ESP_LEDC_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_LEDC_INUM, (func), (void *)(arg))
+
+#define ESP_WMAC_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_WMAC_INUM, (func), (void *)(arg))
+
+#define ESP_FRC_TIMER1_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_FRC_TIMER1_INUM, (func), (void *)(arg))
+
+#define ESP_FRC_TIMER2_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_FRC_TIMER2_INUM, (func), (void *)(arg))
+
+#define ESP_GPIO_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_GPIO_INUM, (func), (void *)(arg))
+
+#define ESP_UART0_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_UART0_INUM, (func), (void *)(arg))
+
+#define ESP_WDT_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_WDT_INUM, (func), (void *)(arg))
+
+#define ESP_RTC_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_RTC_INUM, (func), (void *)(arg))
+
+#define ESP_SLC_INTR_ATTACH(func, arg) \
+    xt_set_interrupt_handler(ETS_SLC_INUM, (func), (void *)(arg))
+
+#define ESP_RMT_CTRL_INTRL(func,arg)\
+    xt_set_interrupt_handler(ETS_RMT_CTRL_INUM, (func), (void *)(arg))
+
+#define ESP_INTR_ENABLE(inum) \
+    xt_ints_on((1<<inum))
+
+#define ESP_INTR_DISABLE(inum) \
+    xt_ints_off((1<<inum))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_INTR_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_intr_alloc.h

@@ -0,0 +1,282 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_INTR_ALLOC_H__
+#define __ESP_INTR_ALLOC_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** @addtogroup Intr_Alloc
+  * @{
+  */
+
+
+/** @brief Interrupt allocation flags
+ *
+ * These flags can be used to specify which interrupt qualities the
+ * code calling esp_intr_alloc* needs.
+ *
+ */
+
+//Keep the LEVELx values as they are here; they match up with (1<<level)
+#define ESP_INTR_FLAG_LEVEL1		(1<<1)	///< Accept a Level 1 interrupt vector
+#define ESP_INTR_FLAG_LEVEL2		(1<<2)	///< Accept a Level 2 interrupt vector
+#define ESP_INTR_FLAG_LEVEL3		(1<<3)	///< Accept a Level 3 interrupt vector
+#define ESP_INTR_FLAG_LEVEL4		(1<<4)	///< Accept a Level 4 interrupt vector
+#define ESP_INTR_FLAG_LEVEL5		(1<<5)	///< Accept a Level 5 interrupt vector
+#define ESP_INTR_FLAG_LEVEL6		(1<<6)	///< Accept a Level 6 interrupt vector
+#define ESP_INTR_FLAG_NMI			(1<<7)	///< Accept a Level 7 interrupt vector
+#define ESP_INTR_FLAG_SHARED		(1<<8)	///< Interrupt can be shared between ISRs
+#define ESP_INTR_FLAG_EDGE			(1<<9)	///< Edge-triggered interrupt
+#define ESP_INTR_FLAG_IRAM			(1<<10)	///< ISR can be called if cache is disabled
+#define ESP_INTR_FLAG_INTRDISABLED	(1<<11)	///< Return with this interrupt disabled
+
+#define ESP_INTR_FLAG_LOWMED	(ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3) ///< Low and medium prio interrupts. These can be handled in C.
+#define ESP_INTR_FLAG_HIGH		(ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6|ESP_INTR_FLAG_NMI) ///< High level interrupts. Need to be handled in assembly.
+
+#define ESP_INTR_FLAG_LEVELMASK	(ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
+								 ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
+								 ESP_INTR_FLAG_NMI) ///< Mask for all level flags
+/**@}*/
+
+
+/** @addtogroup Intr_Alloc_Pseudo_Src
+  * @{
+  */
+
+/**
+ * The esp_intr_alloc* functions can allocate an int for all ETS_*_INTR_SOURCE interrupt sources that
+ * are routed through the interrupt mux. Apart from these sources, each core also has some internal
+ * sources that do not pass through the interrupt mux. To allocate an interrupt for these sources,
+ * pass these pseudo-sources to the functions.
+ */
+#define ETS_INTERNAL_TIMER0_INTR_SOURCE		-1 ///< Xtensa timer 0 interrupt source
+#define ETS_INTERNAL_TIMER1_INTR_SOURCE		-2 ///< Xtensa timer 1 interrupt source
+#define ETS_INTERNAL_TIMER2_INTR_SOURCE		-3 ///< Xtensa timer 2 interrupt source
+#define ETS_INTERNAL_SW0_INTR_SOURCE		-4 ///< Software int source 1
+#define ETS_INTERNAL_SW1_INTR_SOURCE		-5 ///< Software int source 2
+#define ETS_INTERNAL_PROFILING_INTR_SOURCE	-6 ///< Int source for profiling
+
+/**@}*/
+
+// This is used to provide SystemView with positive IRQ IDs, otherwise sheduler events are not shown properly
+#define ETS_INTERNAL_INTR_SOURCE_OFF		(-ETS_INTERNAL_PROFILING_INTR_SOURCE)
+
+typedef void (*intr_handler_t)(void *arg); 
+
+
+typedef struct intr_handle_data_t intr_handle_data_t;
+typedef intr_handle_data_t* intr_handle_t ;
+
+/**
+ * @brief Mark an interrupt as a shared interrupt
+ * 
+ * This will mark a certain interrupt on the specified CPU as
+ * an interrupt that can be used to hook shared interrupt handlers
+ * to.
+ *
+ * @param intno The number of the interrupt (0-31)
+ * @param cpu CPU on which the interrupt should be marked as shared (0 or 1)
+ * @param is_in_iram Shared interrupt is for handlers that reside in IRAM and
+ *                   the int can be left enabled while the flash cache is disabled.
+ *
+ * @return ESP_ERR_INVALID_ARG if cpu or intno is invalid
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_mark_shared(int intno, int cpu, bool is_in_iram);
+
+/**
+ * @brief Reserve an interrupt to be used outside of this framework
+ * 
+ * This will mark a certain interrupt on the specified CPU as
+ * reserved, not to be allocated for any reason.
+ *
+ * @param intno The number of the interrupt (0-31)
+ * @param cpu CPU on which the interrupt should be marked as shared (0 or 1)
+ *
+ * @return ESP_ERR_INVALID_ARG if cpu or intno is invalid
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_reserve(int intno, int cpu);
+
+/**
+ * @brief Allocate an interrupt with the given parameters.
+ *
+ * This finds an interrupt that matches the restrictions as given in the flags
+ * parameter, maps the given interrupt source to it and hooks up the given
+ * interrupt handler (with optional argument) as well. If needed, it can return
+ * a handle for the interrupt as well.
+ *
+ * The interrupt will always be allocated on the core that runs this function.
+ *
+ * If ESP_INTR_FLAG_IRAM flag is used, and handler address is not in IRAM or
+ * RTC_FAST_MEM, then ESP_ERR_INVALID_ARG is returned.
+ *
+ * @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux
+ *               sources, as defined in soc/soc.h, or one of the internal
+ *               ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header.
+ * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the
+ *               choice of interrupts that this routine can choose from. If this value
+ *               is 0, it will default to allocating a non-shared interrupt of level
+ *               1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
+ *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return 
+ *               from this function with the interrupt disabled.
+ * @param handler The interrupt handler. Must be NULL when an interrupt of level >3
+ *               is requested, because these types of interrupts aren't C-callable.
+ * @param arg    Optional argument for passed to the interrupt handler
+ * @param ret_handle Pointer to an intr_handle_t to store a handle that can later be
+ *               used to request details or free the interrupt. Can be NULL if no handle
+ *               is required.
+ *
+ * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
+ *         ESP_ERR_NOT_FOUND No free interrupt found with the specified flags
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_alloc(int source, int flags, intr_handler_t handler, void *arg, intr_handle_t *ret_handle);
+
+
+/**
+ * @brief Allocate an interrupt with the given parameters.
+ *
+ *
+ * This essentially does the same as esp_intr_alloc, but allows specifying a register and mask
+ * combo. For shared interrupts, the handler is only called if a read from the specified 
+ * register, ANDed with the mask, returns non-zero. By passing an interrupt status register
+ * address and a fitting mask, this can be used to accelerate interrupt handling in the case
+ * a shared interrupt is triggered; by checking the interrupt statuses first, the code can
+ * decide which ISRs can be skipped
+ *
+ * @param source The interrupt source. One of the ETS_*_INTR_SOURCE interrupt mux
+ *               sources, as defined in soc/soc.h, or one of the internal
+ *               ETS_INTERNAL_*_INTR_SOURCE sources as defined in this header.
+ * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the
+ *               choice of interrupts that this routine can choose from. If this value
+ *               is 0, it will default to allocating a non-shared interrupt of level
+ *               1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
+ *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return 
+ *               from this function with the interrupt disabled.
+ * @param intrstatusreg The address of an interrupt status register
+ * @param intrstatusmask A mask. If a read of address intrstatusreg has any of the bits
+ *               that are 1 in the mask set, the ISR will be called. If not, it will be
+ *               skipped.
+ * @param handler The interrupt handler. Must be NULL when an interrupt of level >3
+ *               is requested, because these types of interrupts aren't C-callable.
+ * @param arg    Optional argument for passed to the interrupt handler
+ * @param ret_handle Pointer to an intr_handle_t to store a handle that can later be
+ *               used to request details or free the interrupt. Can be NULL if no handle
+ *               is required.
+ *
+ * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
+ *         ESP_ERR_NOT_FOUND No free interrupt found with the specified flags
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusreg, uint32_t intrstatusmask, intr_handler_t handler, void *arg, intr_handle_t *ret_handle);
+
+
+/**
+ * @brief Disable and free an interrupt.
+ *
+ * Use an interrupt handle to disable the interrupt and release the resources
+ * associated with it.
+ *
+ * @note 
+ * When the handler shares its source with other handlers, the interrupt status 
+ * bits it's responsible for should be managed properly before freeing it. see 
+ * ``esp_intr_disable`` for more details.
+ *
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ *
+ * @return ESP_ERR_INVALID_ARG if handle is invalid, or esp_intr_free runs on another core than
+ *                             where the interrupt is allocated on.
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_free(intr_handle_t handle);
+
+
+/**
+ * @brief Get CPU number an interrupt is tied to
+ * 
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ *
+ * @return The core number where the interrupt is allocated
+ */
+int esp_intr_get_cpu(intr_handle_t handle);
+
+/**
+ * @brief Get the allocated interrupt for a certain handle
+ * 
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ *
+ * @return The interrupt number
+ */
+int esp_intr_get_intno(intr_handle_t handle);
+
+/**
+ * @brief Disable the interrupt associated with the handle
+ * 
+ * @note 
+ * 1. For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
+ * CPU the interrupt is allocated on. Other interrupts have no such restriction.
+ * 2. When several handlers sharing a same interrupt source, interrupt status bits, which are 
+ * handled in the handler to be disabled, should be masked before the disabling, or handled
+ * in other enabled interrupts properly. Miss of interrupt status handling will cause infinite 
+ * interrupt calls and finally system crash.
+ *
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ *
+ * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_disable(intr_handle_t handle);
+
+/**
+ * @brief Ensable the interrupt associated with the handle
+ * 
+ * @note For local interrupts (ESP_INTERNAL_* sources), this function has to be called on the
+ *       CPU the interrupt is allocated on. Other interrupts have no such restriction.
+ *
+ * @param handle The handle, as obtained by esp_intr_alloc or esp_intr_alloc_intrstatus
+ *
+ * @return ESP_ERR_INVALID_ARG if the combination of arguments is invalid.
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_intr_enable(intr_handle_t handle);
+
+
+/**
+ * @brief Disable interrupts that aren't specifically marked as running from IRAM
+ */
+void esp_intr_noniram_disable();
+
+
+/**
+ * @brief Re-enable interrupts disabled by esp_intr_noniram_disable
+ */
+void esp_intr_noniram_enable();
+
+/**@}*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_ipc.h

@@ -0,0 +1,99 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_IPC_H__
+#define __ESP_IPC_H__
+
+#include <esp_err.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void (*esp_ipc_func_t)(void* arg);
+
+/**
+ * @brief Inter-processor call APIs
+ *
+ * FreeRTOS provides several APIs which can be used to communicate between
+ * different tasks, including tasks running on different CPUs.
+ * This module provides additional APIs to run some code on the other CPU.
+ *
+ * These APIs can only be used when FreeRTOS scheduler is running.
+ */
+
+
+/**
+ * @brief Initialize inter-processor call module.
+ *
+ * This function start two tasks, one on each CPU. These tasks are started
+ * with high priority. These tasks are normally inactive, waiting until one of
+ * the esp_ipc_call_* functions to be used. One of these tasks will be
+ * woken up to execute the callback provided to esp_ipc_call_nonblocking or
+ * esp_ipc_call_blocking.
+ */
+void esp_ipc_init();
+
+
+/**
+ * @brief Execute function on the given CPU
+ *
+ * This will wake a high-priority task on CPU indicated by cpu_id argument,
+ * and run func(arg) in the context of that task.
+ * This function returns as soon as the high-priority task is woken up.
+ * If another IPC call is already being executed, this function will also wait
+ * for it to complete.
+ *
+ * In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1.
+ *
+ * For complex functions, you may need to increase the stack size of the "IPC task"
+ * which runs the function must be sufficient. See the "Inter-Processor Call (IPC)
+ * task stack size" setting in menuconfig.
+ *
+ * @param cpu_id CPU where function should be executed (0 or 1)
+ * @param func pointer to a function which should be executed
+ * @param arg arbitrary argument to be passed into function
+ *
+ * @return ESP_ERR_INVALID_ARG if cpu_id is invalid
+ *         ESP_ERR_INVALID_STATE if FreeRTOS scheduler is not running
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_ipc_call(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
+
+
+/**
+ * @brief Execute function on the given CPU and wait for it to finish
+ *
+ * This will wake a high-priority task on CPU indicated by cpu_id argument,
+ * and run func(arg) in the context of that task.
+ * This function waits for func to return.
+ *
+ * In single-core mode, returns ESP_ERR_INVALID_ARG for cpu_id 1.
+ *
+ * @param cpu_id CPU where function should be executed (0 or 1)
+ * @param func pointer to a function which should be executed
+ * @param arg arbitrary argument to be passed into function
+ *
+ * @return ESP_ERR_INVALID_ARG if cpu_id is invalid
+ *         ESP_ERR_INVALID_STATE if FreeRTOS scheduler is not running
+ *         ESP_OK otherwise
+ */
+esp_err_t esp_ipc_call_blocking(uint32_t cpu_id, esp_ipc_func_t func, void* arg);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_IPC_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_panic.h

@@ -0,0 +1,83 @@
+#ifndef PANIC_H
+#define PANIC_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define PANIC_RSN_NONE 0
+#define PANIC_RSN_DEBUGEXCEPTION 1
+#define PANIC_RSN_DOUBLEEXCEPTION 2
+#define PANIC_RSN_KERNELEXCEPTION 3
+#define PANIC_RSN_COPROCEXCEPTION 4
+#define PANIC_RSN_INTWDT_CPU0 5
+#define PANIC_RSN_INTWDT_CPU1 6
+#define PANIC_RSN_CACHEERR 7
+#define PANIC_RSN_MAX 7
+
+
+#ifndef __ASSEMBLER__
+
+#include "esp_err.h"
+
+
+/**
+ * @brief If an OCD is connected over JTAG. set breakpoint 0 to the given function 
+ *        address. Do nothing otherwise.
+ * @param data  Pointer to the target breakpoint position
+ */
+
+void esp_set_breakpoint_if_jtag(void *fn);
+
+#define ESP_WATCHPOINT_LOAD 0x40000000
+#define ESP_WATCHPOINT_STORE 0x80000000
+#define ESP_WATCHPOINT_ACCESS 0xC0000000
+
+/**
+ * @brief Set a watchpoint to break/panic when a certain memory range is accessed.
+ *
+ * @param no Watchpoint number. On the ESP32, this can be 0 or 1.
+ * @param adr Base address to watch
+ * @param size Size of the region, starting at the base address, to watch. Must
+ *             be one of 2^n, with n in [0..6].
+ * @param flags One of ESP_WATCHPOINT_* flags
+ *
+ * @return ESP_ERR_INVALID_ARG on invalid arg, ESP_OK otherwise
+ *
+ * @warning The ESP32 watchpoint hardware watches a region of bytes by effectively 
+ *          masking away the lower n bits for a region with size 2^n. If adr does
+ *          not have zero for these lower n bits, you may not be watching the
+ *          region you intended.
+ */
+esp_err_t esp_set_watchpoint(int no, void *adr, int size, int flags);
+
+
+/**
+ * @brief Clear a watchpoint
+ *
+ * @param no Watchpoint to clear
+ *
+ */
+void esp_clear_watchpoint(int no);
+
+
+/**
+ * @brief Stops panic WDT
+ */
+void esp_panic_wdt_stop(void);
+
+/**
+ * @brief Checks stack pointer
+ */
+static inline bool esp_stack_ptr_is_sane(uint32_t sp)
+{
+	return !(sp < 0x3ffae010UL || sp > 0x3ffffff0UL || ((sp & 0xf) != 0));
+}
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_phy_init.h

@@ -0,0 +1,260 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file PHY init parameters and API
+ */
+
+
+/**
+ * @brief Structure holding PHY init parameters
+ */
+typedef struct {
+	uint8_t param_ver_id;                   /*!< init_data structure version */
+	uint8_t crystal_select;                 /*!< 0: 40MHz, 1: 26 MHz, 2: 24 MHz, 3: auto */
+	uint8_t wifi_rx_gain_swp_step_1;        /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_2;        /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_3;        /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_4;        /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_5;        /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_6;        /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_7;        /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_8;        /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_9;        /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_10;       /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_11;       /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_12;       /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_13;       /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_14;       /*!< do not change */
+	uint8_t wifi_rx_gain_swp_step_15;       /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_1;          /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_2;          /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_3;          /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_4;          /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_5;          /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_6;          /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_7;          /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_8;          /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_9;          /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_10;         /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_11;         /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_12;         /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_13;         /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_14;         /*!< do not change */
+	uint8_t bt_rx_gain_swp_step_15;         /*!< do not change */
+	uint8_t gain_cmp_1;                     /*!< do not change */
+	uint8_t gain_cmp_6;                     /*!< do not change */
+	uint8_t gain_cmp_11;                    /*!< do not change */
+	uint8_t gain_cmp_ext2_1;                /*!< do not change */
+	uint8_t gain_cmp_ext2_6;                /*!< do not change */
+	uint8_t gain_cmp_ext2_11;               /*!< do not change */
+	uint8_t gain_cmp_ext3_1;                /*!< do not change */
+	uint8_t gain_cmp_ext3_6;                /*!< do not change */
+	uint8_t gain_cmp_ext3_11;               /*!< do not change */
+	uint8_t gain_cmp_bt_ofs_1;              /*!< do not change */
+	uint8_t gain_cmp_bt_ofs_6;              /*!< do not change */
+	uint8_t gain_cmp_bt_ofs_11;             /*!< do not change */
+	uint8_t target_power_qdb_0;             /*!< 78 means target power is 78/4=19.5dbm */
+	uint8_t target_power_qdb_1;             /*!< 76 means target power is 76/4=19dbm */
+	uint8_t target_power_qdb_2;             /*!< 74 means target power is 74/4=18.5dbm */
+	uint8_t target_power_qdb_3;             /*!< 68 means target power is 68/4=17dbm */
+	uint8_t target_power_qdb_4;             /*!< 64 means target power is 64/4=16dbm */
+	uint8_t target_power_qdb_5;             /*!< 52 means target power is 52/4=13dbm */
+	uint8_t target_power_index_mcs0;        /*!< target power index is 0, means target power is target_power_qdb_0 19.5dbm;  (1m,2m,5.5m,11m,6m,9m) */
+	uint8_t target_power_index_mcs1;        /*!< target power index is 0, means target power is target_power_qdb_0 19.5dbm;  (12m) */
+	uint8_t target_power_index_mcs2;        /*!< target power index is 1, means target power is target_power_qdb_1 19dbm;    (18m) */
+	uint8_t target_power_index_mcs3;        /*!< target power index is 1, means target power is target_power_qdb_1 19dbm;    (24m) */
+	uint8_t target_power_index_mcs4;        /*!< target power index is 2, means target power is target_power_qdb_2 18.5dbm;  (36m) */
+	uint8_t target_power_index_mcs5;        /*!< target power index is 3, means target power is target_power_qdb_3 17dbm;    (48m) */
+	uint8_t target_power_index_mcs6;        /*!< target power index is 4, means target power is target_power_qdb_4 16dbm;    (54m) */
+	uint8_t target_power_index_mcs7;        /*!< target power index is 5, means target power is target_power_qdb_5 13dbm */
+	uint8_t pwr_ind_11b_en;                 /*!< 0: 11b power is same as mcs0 and 6m, 1: 11b power different with OFDM */
+	uint8_t pwr_ind_11b_0;                  /*!< 1m, 2m power index [0~5] */
+	uint8_t pwr_ind_11b_1;                  /*!< 5.5m, 11m power index [0~5] */
+	uint8_t chan_backoff_en;                /*!< 0: channel backoff disable, 1:channel backoff enable */
+	uint8_t chan1_power_backoff_qdb;        /*!< 4 means backoff is 1db */
+	uint8_t chan2_power_backoff_qdb;        /*!< see chan1_power_backoff_qdb */
+	uint8_t chan3_power_backoff_qdb;        /*!< chan1_power_backoff_qdb */
+	uint8_t chan4_power_backoff_qdb;        /*!< chan1_power_backoff_qdb */
+	uint8_t chan5_power_backoff_qdb;        /*!< chan1_power_backoff_qdb */
+	uint8_t chan6_power_backoff_qdb;        /*!< chan1_power_backoff_qdb */
+	uint8_t chan7_power_backoff_qdb;        /*!< chan1_power_backoff_qdb */
+	uint8_t chan8_power_backoff_qdb;        /*!< chan1_power_backoff_qdb */
+	uint8_t chan9_power_backoff_qdb;        /*!< chan1_power_backoff_qdb */
+	uint8_t chan10_power_backoff_qdb;       /*!< chan1_power_backoff_qdb */
+	uint8_t chan11_power_backoff_qdb;       /*!< chan1_power_backoff_qdb */
+	uint8_t chan12_power_backoff_qdb;       /*!< chan1_power_backoff_qdb */
+	uint8_t chan13_power_backoff_qdb;       /*!< chan1_power_backoff_qdb */
+	uint8_t chan14_power_backoff_qdb;       /*!< chan1_power_backoff_qdb */
+	uint8_t chan1_rate_backoff_index;       /*!< if bit i is set, backoff data rate is target_power_qdb_i */
+	uint8_t chan2_rate_backoff_index;       /*!< see chan1_rate_backoff_index */
+	uint8_t chan3_rate_backoff_index;       /*!< see chan1_rate_backoff_index */
+	uint8_t chan4_rate_backoff_index;       /*!< see chan1_rate_backoff_index */
+	uint8_t chan5_rate_backoff_index;       /*!< see chan1_rate_backoff_index */
+	uint8_t chan6_rate_backoff_index;       /*!< see chan1_rate_backoff_index */
+	uint8_t chan7_rate_backoff_index;       /*!< see chan1_rate_backoff_index */
+	uint8_t chan8_rate_backoff_index;       /*!< see chan1_rate_backoff_index */
+	uint8_t chan9_rate_backoff_index;       /*!< see chan1_rate_backoff_index */
+	uint8_t chan10_rate_backoff_index;      /*!< see chan1_rate_backoff_index */
+	uint8_t chan11_rate_backoff_index;      /*!< see chan1_rate_backoff_index */
+	uint8_t chan12_rate_backoff_index;      /*!< see chan1_rate_backoff_index */
+	uint8_t chan13_rate_backoff_index;      /*!< see chan1_rate_backoff_index */
+	uint8_t chan14_rate_backoff_index;      /*!< see chan1_rate_backoff_index */
+	uint8_t spur_freq_cfg_msb_1;            /*!< first spur: */
+	uint8_t spur_freq_cfg_1;                /*!< spur_freq_cfg = (spur_freq_cfg_msb_1 <<8) | spur_freq_cfg_1 */
+	uint8_t spur_freq_cfg_div_1;            /*!< spur_freq=spur_freq_cfg/spur_freq_cfg_div_1 */
+	uint8_t spur_freq_en_h_1;               /*!< the seventh bit for total enable */
+	uint8_t spur_freq_en_l_1;               /*!< each bit for 1 channel, and use [spur_freq_en_h, spur_freq_en_l] to select the spur's channel priority */
+	uint8_t spur_freq_cfg_msb_2;            /*!< second spur: */
+	uint8_t spur_freq_cfg_2;                /*!< spur_freq_cfg = (spur_freq_cfg_msb_2 <<8) | spur_freq_cfg_2 */
+	uint8_t spur_freq_cfg_div_2;            /*!< spur_freq=spur_freq_cfg/spur_freq_cfg_div_2 */
+	uint8_t spur_freq_en_h_2;               /*!< the seventh bit for total enable */
+	uint8_t spur_freq_en_l_2;               /*!< each bit for 1 channel, and use [spur_freq_en_h, spur_freq_en_l] to select the spur's channel priority */
+	uint8_t spur_freq_cfg_msb_3;            /*!< third spur: */
+	uint8_t spur_freq_cfg_3;                /*!< spur_freq_cfg = (spur_freq_cfg_msb_3 <<8) | spur_freq_cfg_3 */
+	uint8_t spur_freq_cfg_div_3;            /*!< spur_freq=spur_freq_cfg/spur_freq_cfg_div_3 */
+	uint8_t spur_freq_en_h_3;               /*!< the seventh bit for total enable */
+	uint8_t spur_freq_en_l_3;               /*!< each bit for 1 channel, and use [spur_freq_en_h, spur_freq_en_l] to select the spur's channel priority, */
+	uint8_t reserved[23];                   /*!< reserved for future expansion */
+} esp_phy_init_data_t;
+
+/**
+ * @brief Opaque PHY calibration data
+ */
+typedef struct {
+    uint8_t opaque[1904];                   /*!< calibration data */
+} esp_phy_calibration_data_t;
+
+typedef enum {
+    PHY_RF_CAL_PARTIAL = 0x00000000,        /*!< Do part of RF calibration. This should be used after power-on reset. */
+    PHY_RF_CAL_NONE    = 0x00000001,        /*!< Don't do any RF calibration. This mode is only suggested to be used after deep sleep reset. */
+    PHY_RF_CAL_FULL    = 0x00000002         /*!< Do full RF calibration. Produces best results, but also consumes a lot of time and current. Suggested to be used once. */
+} esp_phy_calibration_mode_t;
+
+/**
+ * @brief Get PHY init data
+ *
+ * If "Use a partition to store PHY init data" option is set in menuconfig,
+ * This function will load PHY init data from a partition. Otherwise,
+ * PHY init data will be compiled into the application itself, and this function
+ * will return a pointer to PHY init data located in read-only memory (DROM).
+ *
+ * If "Use a partition to store PHY init data" option is enabled, this function
+ * may return NULL if the data loaded from flash is not valid.
+ *
+ * @note Call esp_phy_release_init_data to release the pointer obtained using
+ * this function after the call to esp_wifi_init.
+ *
+ * @return pointer to PHY init data structure
+ */
+const esp_phy_init_data_t* esp_phy_get_init_data();
+
+/**
+ * @brief Release PHY init data
+ * @param data  pointer to PHY init data structure obtained from
+ *              esp_phy_get_init_data function
+ */
+void esp_phy_release_init_data(const esp_phy_init_data_t* data);
+
+/**
+ * @brief Function called by esp_phy_init to load PHY calibration data
+ *
+ * This is a convenience function which can be used to load PHY calibration
+ * data from NVS. Data can be stored to NVS using esp_phy_store_cal_data_to_nvs
+ * function.
+ *
+ * If calibration data is not present in the NVS, or
+ * data is not valid (was obtained for a chip with a different MAC address,
+ * or obtained for a different version of software), this function will
+ * return an error.
+ *
+ * If "Initialize PHY in startup code" option is set in menuconfig, this
+ * function will be used to load calibration data. To provide a different
+ * mechanism for loading calibration data, disable
+ * "Initialize PHY in startup code" option in menuconfig and call esp_phy_init
+ * function from the application. For an example usage of esp_phy_init and
+ * this function, see esp_phy_store_cal_data_to_nvs function in cpu_start.c
+ *
+ * @param out_cal_data pointer to calibration data structure to be filled with
+ *                     loaded data.
+ * @return ESP_OK on success
+ */
+esp_err_t esp_phy_load_cal_data_from_nvs(esp_phy_calibration_data_t* out_cal_data);
+
+/**
+ * @brief Function called by esp_phy_init to store PHY calibration data
+ *
+ * This is a convenience function which can be used to store PHY calibration
+ * data to the NVS. Calibration data is returned by esp_phy_init function.
+ * Data saved using this function to the NVS can later be loaded using
+ * esp_phy_store_cal_data_to_nvs function.
+ *
+ * If "Initialize PHY in startup code" option is set in menuconfig, this
+ * function will be used to store calibration data. To provide a different
+ * mechanism for storing calibration data, disable
+ * "Initialize PHY in startup code" option in menuconfig and call esp_phy_init
+ * function from the application.
+ *
+ * @param cal_data pointer to calibration data which has to be saved.
+ * @return ESP_OK on success
+ */
+esp_err_t esp_phy_store_cal_data_to_nvs(const esp_phy_calibration_data_t* cal_data);
+
+/**
+ * @brief Initialize PHY and RF module
+ *
+ * PHY and RF module should be initialized in order to use WiFi or BT.
+ * Now PHY and RF initializing job is done automatically when start WiFi or BT. Users should not
+ * call this API in their application.
+ *
+ * @param init_data  PHY parameters. Default set of parameters can
+ *                   be obtained by calling esp_phy_get_default_init_data
+ *                   function.
+ * @param mode  Calibration mode (Full, partial, or no calibration)
+ * @param[inout] calibration_data
+ * @return ESP_OK on success.
+ * @return ESP_FAIL on fail.
+ */
+esp_err_t esp_phy_rf_init(const esp_phy_init_data_t* init_data,
+        esp_phy_calibration_mode_t mode, esp_phy_calibration_data_t* calibration_data);
+
+/**
+ * @brief De-initialize PHY and RF module
+ *
+ * PHY module should be de-initialized in order to shutdown WiFi or BT.
+ * Now PHY and RF de-initializing job is done automatically when stop WiFi or BT. Users should not
+ * call this API in their application.
+ *
+ * @return ESP_OK on success.
+ */
+esp_err_t esp_phy_rf_deinit(void);
+
+/**
+ * @brief Load calibration data from NVS and initialize PHY and RF module
+ */
+void esp_phy_load_cal_and_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_sleep.h

@@ -0,0 +1,301 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include <stdint.h>
+#include "esp_err.h"
+#include "driver/gpio.h"
+#include "driver/touch_pad.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Logic function used for EXT1 wakeup mode.
+ */
+typedef enum {
+    ESP_EXT1_WAKEUP_ALL_LOW = 0,    //!< Wake the chip when all selected GPIOs go low
+    ESP_EXT1_WAKEUP_ANY_HIGH = 1    //!< Wake the chip when any of the selected GPIOs go high
+} esp_sleep_ext1_wakeup_mode_t;
+
+/**
+ * @brief Power domains which can be powered down in sleep mode
+ */
+typedef enum {
+    ESP_PD_DOMAIN_RTC_PERIPH,      //!< RTC IO, sensors and ULP co-processor
+    ESP_PD_DOMAIN_RTC_SLOW_MEM,    //!< RTC slow memory
+    ESP_PD_DOMAIN_RTC_FAST_MEM,    //!< RTC fast memory
+    ESP_PD_DOMAIN_MAX              //!< Number of domains
+} esp_sleep_pd_domain_t;
+
+/**
+ * @brief Power down options
+ */
+typedef enum {
+    ESP_PD_OPTION_OFF,      //!< Power down the power domain in sleep mode
+    ESP_PD_OPTION_ON,       //!< Keep power domain enabled during sleep mode
+    ESP_PD_OPTION_AUTO      //!< Keep power domain enabled in sleep mode, if it is needed by one of the wakeup options. Otherwise power it down.
+} esp_sleep_pd_option_t;
+
+/**
+ * @brief Sleep wakeup cause
+ */
+typedef enum {
+    ESP_SLEEP_WAKEUP_UNDEFINED,    //! In case of deep sleep, reset was not caused by exit from deep sleep
+    ESP_SLEEP_WAKEUP_EXT0,         //! Wakeup caused by external signal using RTC_IO
+    ESP_SLEEP_WAKEUP_EXT1,         //! Wakeup caused by external signal using RTC_CNTL
+    ESP_SLEEP_WAKEUP_TIMER,        //! Wakeup caused by timer
+    ESP_SLEEP_WAKEUP_TOUCHPAD,     //! Wakeup caused by touchpad
+    ESP_SLEEP_WAKEUP_ULP,          //! Wakeup caused by ULP program
+} esp_sleep_wakeup_cause_t;
+
+
+/**
+ * @brief Enable wakeup by ULP coprocessor
+ * @note In revisions 0 and 1 of the ESP32, ULP wakeup source
+ *       can not be used when RTC_PERIPH power domain is forced
+ *       to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup
+ *       source is used.
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if ULP co-processor is not enabled or if wakeup triggers conflict
+ */
+esp_err_t esp_sleep_enable_ulp_wakeup();
+
+/**
+ * @brief Enable wakeup by timer
+ * @param time_in_us  time before wakeup, in microseconds
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if value is out of range (TBD)
+ */
+esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us);
+
+/**
+ * @brief Enable wakeup by touch sensor
+ *
+ * @note In revisions 0 and 1 of the ESP32, touch wakeup source
+ *       can not be used when RTC_PERIPH power domain is forced
+ *       to be powered on (ESP_PD_OPTION_ON) or when ext0 wakeup
+ *       source is used.
+ *
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if wakeup triggers conflict
+ */
+esp_err_t esp_sleep_enable_touchpad_wakeup();
+
+/**
+ * @brief Get the touch pad which caused wakeup
+ *
+ * If wakeup was caused by another source, this function will return TOUCH_PAD_MAX;
+ *
+ * @return touch pad which caused wakeup
+ */
+touch_pad_t esp_sleep_get_touchpad_wakeup_status();
+
+/**
+ * @brief Enable wakeup using a pin
+ *
+ * This function uses external wakeup feature of RTC_IO peripheral.
+ * It will work only if RTC peripherals are kept on during sleep.
+ *
+ * This feature can monitor any pin which is an RTC IO. Once the pin transitions
+ * into the state given by level argument, the chip will be woken up.
+ *
+ * @note This function does not modify pin configuration. The pin is
+ *       configured in esp_sleep_start, immediately before entering sleep mode.
+ *
+ * @note In revisions 0 and 1 of the ESP32, ext0 wakeup source
+ *       can not be used together with touch or ULP wakeup sources.
+ *
+ * @param gpio_num  GPIO number used as wakeup source. Only GPIOs which are have RTC
+ *             functionality can be used: 0,2,4,12-15,25-27,32-39.
+ * @param level  input level which will trigger wakeup (0=low, 1=high)
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if the selected GPIO is not an RTC GPIO,
+ *        or the mode is invalid
+ *      - ESP_ERR_INVALID_STATE if wakeup triggers conflict
+ */
+esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level);
+
+/**
+ * @brief Enable wakeup using multiple pins
+ *
+ * This function uses external wakeup feature of RTC controller.
+ * It will work even if RTC peripherals are shut down during sleep.
+ *
+ * This feature can monitor any number of pins which are in RTC IOs.
+ * Once any of the selected pins goes into the state given by mode argument,
+ * the chip will be woken up.
+ *
+ * @note This function does not modify pin configuration. The pins are
+ *       configured in esp_sleep_start, immediately before
+ *       entering sleep mode.
+ *
+ * @note internal pullups and pulldowns don't work when RTC peripherals are
+ *       shut down. In this case, external resistors need to be added.
+ *       Alternatively, RTC peripherals (and pullups/pulldowns) may be
+ *       kept enabled using esp_sleep_pd_config function.
+ *
+ * @param mask  bit mask of GPIO numbers which will cause wakeup. Only GPIOs
+ *              which are have RTC functionality can be used in this bit map:
+ *              0,2,4,12-15,25-27,32-39.
+ * @param mode select logic function used to determine wakeup condition:
+ *            - ESP_EXT1_WAKEUP_ALL_LOW: wake up when all selected GPIOs are low
+ *            - ESP_EXT1_WAKEUP_ANY_HIGH: wake up when any of the selected GPIOs is high
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if any of the selected GPIOs is not an RTC GPIO,
+ *        or mode is invalid
+ */
+esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode_t mode);
+
+
+/**
+ * @brief Get the bit mask of GPIOs which caused wakeup (ext1)
+ *
+ * If wakeup was caused by another source, this function will return 0.
+ *
+ * @return bit mask, if GPIOn caused wakeup, BIT(n) will be set
+ */
+uint64_t esp_sleep_get_ext1_wakeup_status();
+
+/**
+ * @brief Set power down mode for an RTC power domain in sleep mode
+ *
+ * If not set set using this API, all power domains default to ESP_PD_OPTION_AUTO.
+ *
+ * @param domain  power domain to configure
+ * @param option  power down option (ESP_PD_OPTION_OFF, ESP_PD_OPTION_ON, or ESP_PD_OPTION_AUTO)
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if either of the arguments is out of range
+ */
+esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
+                                   esp_sleep_pd_option_t option);
+
+/**
+ * @brief Enter deep sleep with the configured wakeup options
+ *
+ * This function does not return.
+ */
+void esp_deep_sleep_start() __attribute__((noreturn));
+
+/**
+ * @brief Enter light sleep with the configured wakeup options
+ *
+ * @return
+ *  - ESP_OK on success (returned after wakeup)
+ *  - ESP_ERR_INVALID_STATE if WiFi or BT is not stopped
+ */
+esp_err_t esp_light_sleep_start();
+
+/**
+ * @brief Enter deep-sleep mode
+ *
+ * The device will automatically wake up after the deep-sleep time
+ * Upon waking up, the device calls deep sleep wake stub, and then proceeds
+ * to load application.
+ *
+ * Call to this function is equivalent to a call to esp_deep_sleep_enable_timer_wakeup
+ * followed by a call to esp_deep_sleep_start.
+ *
+ * esp_deep_sleep does not shut down WiFi, BT, and higher level protocol
+ * connections gracefully.
+ * Make sure relevant WiFi and BT stack functions are called to close any
+ * connections and deinitialize the peripherals. These include:
+ *     - esp_bluedroid_disable
+ *     - esp_bt_controller_disable
+ *     - esp_wifi_stop
+ *
+ * This function does not return.
+ *
+ * @param time_in_us  deep-sleep time, unit: microsecond
+ */
+void esp_deep_sleep(uint64_t time_in_us) __attribute__((noreturn));
+
+/**
+ * @brief Enter deep-sleep mode
+ *
+ * Function has been renamed to esp_deep_sleep.
+ * This name is deprecated and will be removed in a future version.
+ *
+ * @param time_in_us  deep-sleep time, unit: microsecond
+ */
+void system_deep_sleep(uint64_t time_in_us) __attribute__((noreturn, deprecated));
+
+
+/**
+ * @brief Get the source which caused wakeup from sleep
+ *
+ * @return wakeup cause, or ESP_DEEP_SLEEP_WAKEUP_UNDEFINED if reset happened for reason other than deep sleep wakeup
+ */
+esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause();
+
+
+/**
+ * @brief Default stub to run on wake from deep sleep.
+ *
+ * Allows for executing code immediately on wake from sleep, before
+ * the software bootloader or ESP-IDF app has started up.
+ *
+ * This function is weak-linked, so you can implement your own version
+ * to run code immediately when the chip wakes from
+ * sleep.
+ *
+ * See docs/deep-sleep-stub.rst for details.
+ */
+void esp_wake_deep_sleep(void);
+
+/**
+ * @brief Function type for stub to run on wake from sleep.
+ *
+ */
+typedef void (*esp_deep_sleep_wake_stub_fn_t)(void);
+
+/**
+ * @brief Install a new stub at runtime to run on wake from deep sleep
+ *
+ * If implementing esp_wake_deep_sleep() then it is not necessary to
+ * call this function.
+ *
+ * However, it is possible to call this function to substitute a
+ * different deep sleep stub. Any function used as a deep sleep stub
+ * must be marked RTC_IRAM_ATTR, and must obey the same rules given
+ * for esp_wake_deep_sleep().
+ */
+void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub);
+
+/**
+ * @brief Get current wake from deep sleep stub
+ * @return Return current wake from deep sleep stub, or NULL if
+ *         no stub is installed.
+ */
+esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void);
+
+/**
+ *  @brief The default esp-idf-provided esp_wake_deep_sleep() stub.
+ *
+ *  See docs/deep-sleep-stub.rst for details.
+ */
+void esp_default_wake_deep_sleep(void);
+
+
+#ifdef __cplusplus
+}
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_smartconfig.h

@@ -0,0 +1,136 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_SMARTCONFIG_H__
+#define __ESP_SMARTCONFIG_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    SC_STATUS_WAIT = 0,             /**< Waiting to start connect */
+    SC_STATUS_FIND_CHANNEL,         /**< Finding target channel */
+    SC_STATUS_GETTING_SSID_PSWD,    /**< Getting SSID and password of target AP */
+    SC_STATUS_LINK,                 /**< Connecting to target AP */
+    SC_STATUS_LINK_OVER,            /**< Connected to AP successfully */
+} smartconfig_status_t;
+
+typedef enum {
+    SC_TYPE_ESPTOUCH = 0,       /**< protocol: ESPTouch */
+    SC_TYPE_AIRKISS,            /**< protocol: AirKiss */
+    SC_TYPE_ESPTOUCH_AIRKISS,   /**< protocol: ESPTouch and AirKiss */
+} smartconfig_type_t;
+
+/**
+  * @brief  The callback of SmartConfig, executed when smart-config status changed.
+  *
+  * @param  status  Status of SmartConfig:
+  *    - SC_STATUS_GETTING_SSID_PSWD : pdata is a pointer of smartconfig_type_t, means config type.
+  *    - SC_STATUS_LINK : pdata is a pointer of struct station_config.
+  *    - SC_STATUS_LINK_OVER : pdata is a pointer of phone's IP address(4 bytes) if pdata unequal NULL.
+  *    - otherwise : parameter void *pdata is NULL.
+  * @param  pdata  According to the different status have different values.
+  *
+  */
+typedef void (*sc_callback_t)(smartconfig_status_t status, void *pdata);
+
+/**
+  * @brief  Get the version of SmartConfig.
+  *
+  * @return
+  *     - SmartConfig version const char.
+  */
+const char *esp_smartconfig_get_version(void);
+
+/**
+  * @brief     Start SmartConfig, config ESP device to connect AP. You need to broadcast information by phone APP.
+  *            Device sniffer special packets from the air that containing SSID and password of target AP.
+  *
+  * @attention 1. This API can be called in station or softAP-station mode.
+  * @attention 2. Can not call esp_smartconfig_start twice before it finish, please call
+  *               esp_smartconfig_stop first.
+  *
+  * @param     cb  SmartConfig callback function.
+  * @param     ... log  1: UART output logs; 0: UART only outputs the result.
+  *
+  * @return
+  *     - ESP_OK: succeed
+  *     - others: fail
+  */
+esp_err_t esp_smartconfig_start(sc_callback_t cb, ...);
+
+/**
+  * @brief     Stop SmartConfig, free the buffer taken by esp_smartconfig_start.
+  *
+  * @attention Whether connect to AP succeed or not, this API should be called to free
+  *            memory taken by smartconfig_start.
+  *
+  * @return
+  *     - ESP_OK: succeed
+  *     - others: fail
+  */
+esp_err_t esp_smartconfig_stop(void);
+
+/**
+  * @brief     Set timeout of SmartConfig process.
+  *
+  * @attention Timing starts from SC_STATUS_FIND_CHANNEL status. SmartConfig will restart if timeout.
+  *
+  * @param     time_s  range 15s~255s, offset:45s.
+  *
+  * @return
+  *     - ESP_OK: succeed
+  *     - others: fail
+  */
+esp_err_t esp_esptouch_set_timeout(uint8_t time_s);
+
+/**
+  * @brief     Set protocol type of SmartConfig.
+  *
+  * @attention If users need to set the SmartConfig type, please set it before calling
+  *            esp_smartconfig_start.
+  *
+  * @param     type  Choose from the smartconfig_type_t.
+  *
+  * @return
+  *     - ESP_OK: succeed
+  *     - others: fail
+  */
+esp_err_t esp_smartconfig_set_type(smartconfig_type_t type);
+
+/**
+  * @brief     Set mode of SmartConfig. default normal mode.
+  *
+  * @attention 1. Please call it before API esp_smartconfig_start.
+  * @attention 2. Fast mode have corresponding APP(phone).
+  * @attention 3. Two mode is compatible.
+  *
+  * @param     enable  false-disable(default); true-enable;
+  *
+  * @return
+  *     - ESP_OK: succeed
+  *     - others: fail
+  */
+esp_err_t esp_smartconfig_fast_mode(bool enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_spiram.h

@@ -0,0 +1,61 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef __ESP_SPIRAM_H
+#define __ESP_SPIRAM_H
+
+#include <stddef.h>
+#include <stdint.h>
+#include "esp_err.h"
+
+/**
+ * @brief Initialize spiram interface/hardware. Normally called from cpu_start.c.
+ *
+ * @return ESP_OK on success
+ */
+esp_err_t esp_spiram_init();
+
+
+/**
+ * @brief Memory test for SPI RAM. Should be called after SPI RAM is initialized and
+ * (in case of a dual-core system) the app CPU is online. This test overwrites the 
+ * memory with crap, so do not call after e.g. the heap allocator has stored important
+ * stuff in SPI RAM.
+ *
+ * @return true on success, false on failed memory test
+ */
+bool esp_spiram_test();
+
+
+/**
+ * @brief Get the size of the attached SPI RAM chip selected in menuconfig
+ *
+ * @return Size in bytes, or 0 if no external RAM chip support compiled in.
+ */
+size_t esp_spiram_get_size();
+
+
+/**
+ * @brief Force a writeback of the data in the SPI RAM cache. This is to be called whenever
+ * cache is disabled, because disabling cache on the ESP32 discards the data in the SPI
+ * RAM cache.
+ *
+ * This is meant for use from within the SPI flash code.
+ */
+void esp_spiram_writeback_cache();
+
+
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_ssc.h

@@ -0,0 +1,119 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_SSC_H__
+#define __ESP_SSC_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CMD_T_ASYNC   0x01
+#define CMD_T_SYNC    0x02
+
+typedef struct cmd_s {
+    char *cmd_str;
+    uint8_t flag;
+    uint8_t id;
+    void (* cmd_func)(void);
+    void (* cmd_callback)(void *arg);
+} ssc_cmd_t;
+
+#define MAX_LINE_N  127
+
+typedef enum {
+    SSC_BR_9600   = 9600,
+    SSC_BR_19200  = 19200,
+    SSC_BR_38400  = 38400,
+    SSC_BR_57600  = 57600,
+    SSC_BR_74880  = 74880,
+    SSC_BR_115200 = 115200,
+    SSC_BR_230400 = 230400,
+    SSC_BR_460800 = 460800,
+    SSC_BR_921600 = 921600
+} SscBaudRate;
+
+/** \defgroup SSC_APIs SSC APIs
+  * @brief SSC APIs
+  *
+  * SSC means simple serial command.
+  * SSC APIs allows users to define their own command, users can refer to spiffs_test/test_main.c.
+  *
+  */
+
+/** @addtogroup SSC_APIs
+  * @{
+  */
+
+/**
+  * @brief  Initial the ssc function.
+  *
+  * @attention param is no use, just compatible with ESP8266, default bandrate is 115200
+  *
+  * @param  SscBaudRate bandrate : baud rate
+  *
+  * @return null
+  */
+void ssc_attach(SscBaudRate bandrate);
+
+/**
+  * @brief   Get the length of the simple serial command.
+  *
+  * @param   null
+  *
+  * @return  length of the command.
+  */
+int ssc_param_len(void);
+
+/**
+  * @brief   Get the simple serial command string.
+  *
+  * @param   null
+  *
+  * @return  the command.
+  */
+char *ssc_param_str(void);
+
+/**
+  * @brief   Parse the simple serial command (ssc).
+  *
+  * @param   char *pLine  : [input] the ssc string
+  * @param   char *argv[] : [output] parameters of the ssc
+  *
+  * @return  the number of parameters.
+  */
+int ssc_parse_param(char *pLine, char *argv[]);
+
+/**
+  * @brief  Register the user-defined simple serial command (ssc) set.
+  *
+  * @param  ssc_cmd_t *cmdset   : the ssc set
+  * @param  uint8 cmdnum        : number of commands
+  * @param  void (* help)(void) : callback of user-guide
+  *
+  * @return  null
+  */
+void ssc_register(ssc_cmd_t *cmdset, uint8_t cmdnum, void (* help)(void));
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_SSC_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_system.h

@@ -0,0 +1,295 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_SYSTEM_H__
+#define __ESP_SYSTEM_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_err.h"
+#include "esp_sleep.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ESP_MAC_WIFI_STA,
+    ESP_MAC_WIFI_SOFTAP,
+    ESP_MAC_BT,
+    ESP_MAC_ETH,
+} esp_mac_type_t;
+
+#define TWO_UNIVERSAL_MAC_ADDR 2
+#define FOUR_UNIVERSAL_MAC_ADDR 4
+#define UNIVERSAL_MAC_ADDR_NUM CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS
+
+/**
+  * @attention  application don't need to call this function anymore. It do nothing and will
+  *             be removed in future version.
+  */
+void system_init(void) __attribute__ ((deprecated));
+
+/**
+  * @brief  Reset to default settings.
+  *
+  * Function has been deprecated, please use esp_wifi_restore instead.
+  * This name will be removed in a future release.
+  */
+void system_restore(void) __attribute__ ((deprecated));
+
+typedef void (*shutdown_handler_t)(void);
+/**
+  * @brief  Register shutdown handler
+  *
+  * This function allows you to register a handler that gets invoked before a
+  * systematic shutdown of the chip.
+  */
+esp_err_t esp_register_shutdown_handler(shutdown_handler_t handle);
+
+/**
+  * @brief  Restart PRO and APP CPUs.
+  *
+  * This function can be called both from PRO and APP CPUs.
+  * After successful restart, CPU reset reason will be SW_CPU_RESET.
+  * Peripherals (except for WiFi, BT, UART0, SPI1, and legacy timers) are not reset.
+  * This function does not return.
+  */
+void esp_restart(void) __attribute__ ((noreturn));
+
+/**
+  * @brief  Internal function to restart PRO and APP CPUs.
+  *
+  * @note This function should not be called from FreeRTOS applications.
+  *       Use esp_restart instead.
+  *
+  * This is an internal function called by esp_restart. It is called directly
+  * by the panic handler and brownout detector interrupt.
+  */
+void esp_restart_noos() __attribute__ ((noreturn));
+
+/**
+  * @brief  Restart system.
+  *
+  * Function has been renamed to esp_restart.
+  * This name will be removed in a future release.
+  */
+void system_restart(void) __attribute__ ((deprecated, noreturn));
+
+/**
+  * @brief  Get system time, unit: microsecond.
+  *
+  * This function is deprecated. Use 'gettimeofday' function for 64-bit precision.
+  * This definition will be removed in a future release.
+  */
+uint32_t system_get_time(void)  __attribute__ ((deprecated));
+
+/**
+  * @brief  Get the size of available heap.
+  *
+  * Note that the returned value may be larger than the maximum contiguous block
+  * which can be allocated.
+  *
+  * @return Available heap size, in bytes.
+  */
+uint32_t esp_get_free_heap_size(void);
+
+/**
+  * @brief  Get the size of available heap.
+  *
+  * Function has been renamed to esp_get_free_heap_size.
+  * This name will be removed in a future release.
+  *
+  * @return Available heap size, in bytes.
+  */
+uint32_t system_get_free_heap_size(void)  __attribute__ ((deprecated));
+
+/**
+  * @brief Get the minimum heap that has ever been available
+  *
+  * @return Minimum free heap ever available
+  */
+uint32_t esp_get_minimum_free_heap_size( void );
+
+/**
+ * @brief  Get one random 32-bit word from hardware RNG
+ *
+ * The hardware RNG is fully functional whenever an RF subsystem is running (ie Bluetooth or WiFi is enabled). For secure
+ * random values, call this function after WiFi or Bluetooth are started.
+ *
+ * When the app is running without an RF subsystem enabled, it should be considered a PRNG. To help improve this
+ * situation, the RNG is pre-seeded with entropy while the IDF bootloader is running. However no new entropy is
+ * available during the window of time between when the bootloader exits and an RF subsystem starts. It may be possible
+ * to discern a non-random pattern in a very large amount of output captured during this window of time.
+ *
+ * @return Random value between 0 and UINT32_MAX
+ */
+uint32_t esp_random(void);
+
+/**
+  * @brief  Set base MAC address with the MAC address which is stored in BLK3 of EFUSE or
+  *         external storage e.g. flash and EEPROM.
+  *
+  * Base MAC address is used to generate the MAC addresses used by the networking interfaces.
+  * If using base MAC address stored in BLK3 of EFUSE or external storage, call this API to set base MAC
+  * address with the MAC address which is stored in BLK3 of EFUSE or external storage before initializing
+  * WiFi/BT/Ethernet.
+  *
+  * @param  mac  base MAC address, length: 6 bytes.
+  *
+  * @return ESP_OK on success
+  */
+esp_err_t esp_base_mac_addr_set(uint8_t *mac);
+
+/**
+  * @brief  Return base MAC address which is set using esp_base_mac_addr_set.
+  *
+  * @param  mac  base MAC address, length: 6 bytes.
+  *
+  * @return ESP_OK on success
+  *         ESP_ERR_INVALID_MAC base MAC address has not been set
+  */
+esp_err_t esp_base_mac_addr_get(uint8_t *mac);
+
+/**
+  * @brief  Return base MAC address which was previously written to BLK3 of EFUSE.
+  *
+  * Base MAC address is used to generate the MAC addresses used by the networking interfaces.
+  * This API returns the custom base MAC address which was previously written to BLK3 of EFUSE.
+  * Writing this EFUSE allows setting of a different (non-Espressif) base MAC address. It is also
+  * possible to store a custom base MAC address elsewhere, see esp_base_mac_addr_set() for details.
+  *
+  * @param  mac  base MAC address, length: 6 bytes.
+  *
+  * @return ESP_OK on success
+  *         ESP_ERR_INVALID_VERSION An invalid MAC version field was read from BLK3 of EFUSE
+  *         ESP_ERR_INVALID_CRC An invalid MAC CRC was read from BLK3 of EFUSE
+  */
+esp_err_t esp_efuse_mac_get_custom(uint8_t *mac);
+
+/**
+  * @brief  Return base MAC address which is factory-programmed by Espressif in BLK0 of EFUSE.
+  *
+  * @param  mac  base MAC address, length: 6 bytes.
+  *
+  * @return ESP_OK on success
+  */
+esp_err_t esp_efuse_mac_get_default(uint8_t *mac);
+
+/**
+  * @brief  Read hardware MAC address from efuse.
+  *
+  * Function has been renamed to esp_efuse_mac_get_default.
+  * This name will be removed in a future release.
+  *
+  * @param  mac  hardware MAC address, length: 6 bytes.
+  *
+  * @return ESP_OK on success
+  */
+esp_err_t esp_efuse_read_mac(uint8_t *mac) __attribute__ ((deprecated));
+
+/**
+  * @brief  Read hardware MAC address.
+  *
+  * Function has been renamed to esp_efuse_mac_get_default.
+  * This name will be removed in a future release.
+  *
+  * @param  mac  hardware MAC address, length: 6 bytes.
+  * @return ESP_OK on success
+  */
+esp_err_t system_efuse_read_mac(uint8_t *mac) __attribute__ ((deprecated));
+
+/**
+  * @brief  Read base MAC address and set MAC address of the interface.
+  *
+  * This function first get base MAC address using esp_base_mac_addr_get or reads base MAC address
+  * from BLK0 of EFUSE. Then set the MAC address of the interface including wifi station, wifi softap,
+  * bluetooth and ethernet.
+  *
+  * @param  mac  MAC address of the interface, length: 6 bytes.
+  * @param  type  type of MAC address, 0:wifi station, 1:wifi softap, 2:bluetooth, 3:ethernet.
+  *
+  * @return ESP_OK on success
+  */
+esp_err_t esp_read_mac(uint8_t* mac, esp_mac_type_t type);
+
+/**
+  * @brief  Derive local MAC address from universal MAC address.
+  *
+  * This function derives a local MAC address from an universal MAC address.
+  * A `definition of local vs universal MAC address can be found on Wikipedia
+  * <https://en.wikipedia.org/wiki/MAC_address#Universal_vs._local>`.
+  * In ESP32, universal MAC address is generated from base MAC address in EFUSE or other external storage.
+  * Local MAC address is derived from the universal MAC address.
+  *
+  * @param  local_mac  Derived local MAC address, length: 6 bytes.
+  * @param  universal_mac  Source universal MAC address, length: 6 bytes.
+  *
+  * @return ESP_OK on success
+  */
+esp_err_t esp_derive_local_mac(uint8_t* local_mac, const uint8_t* universal_mac);
+
+/**
+ * Get SDK version
+ *
+ * This function is deprecated and will be removed in a future release.
+ *
+ * @return constant string "master"
+ */
+const char* system_get_sdk_version(void)  __attribute__ ((deprecated));
+
+/**
+ * Get IDF version
+ *
+ * @return constant string from IDF_VER
+ */
+const char* esp_get_idf_version(void);
+
+
+/**
+ * @brief Chip models
+ */
+typedef enum {
+    CHIP_ESP32 = 1, //!< ESP32
+} esp_chip_model_t;
+
+/**
+ * Chip feature flags, used in esp_chip_info_t
+ */
+#define CHIP_FEATURE_EMB_FLASH      BIT(0)
+#define CHIP_FEATURE_WIFI_BGN       BIT(1)
+#define CHIP_FEATURE_BLE            BIT(4)
+#define CHIP_FEATURE_BT             BIT(5)
+
+/**
+ * @brief The structure represents information about the chip
+ */
+typedef struct {
+    esp_chip_model_t model;  //!< chip model, one of esp_chip_model_t
+    uint32_t features;       //!< bit mask of CHIP_FEATURE_x feature flags
+    uint8_t cores;           //!< number of CPU cores
+    uint8_t revision;        //!< chip revision number
+} esp_chip_info_t;
+
+/**
+ * @brief Fill an esp_chip_info_t structure with information about the chip
+ * @param[out] out_info structure to be filled
+ */
+void esp_chip_info(esp_chip_info_t* out_info);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_SYSTEM_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_task.h

@@ -0,0 +1,56 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/* Notes:
+ * 1. Put all task priority and stack size definition in this file
+ * 2. If the task priority is less than 10, use ESP_TASK_PRIO_MIN + X style,
+ *    otherwise use ESP_TASK_PRIO_MAX - X style
+ * 3. If this is a daemon task, the macro prefix is ESP_TASKD_, otherwise
+ *    it's ESP_TASK_
+ * 4. If the configMAX_PRIORITIES is modified, please make all priority are
+ *    greater than 0
+ * 5. Make sure esp_task.h is consistent between wifi lib and idf
+ */
+
+#ifndef _ESP_TASK_H_
+#define _ESP_TASK_H_
+
+#include "sdkconfig.h"
+#include "espos_task.h"
+
+#define ESP_TASK_PRIO_MAX (ESPOS_TASK_PRIO_MAX)
+#define ESP_TASK_PRIO_MIN (0)
+
+/* Bt contoller Task */
+/* controller */
+#define ESP_TASK_BT_CONTROLLER_PRIO   (ESP_TASK_PRIO_MAX - 2)
+#ifdef CONFIG_NEWLIB_NANO_FORMAT
+#define BT_TASK_EXTRA_STACK_SIZE      (0)
+#else
+#define BT_TASK_EXTRA_STACK_SIZE      (512)
+#endif
+#define ESP_TASK_BT_CONTROLLER_STACK  (3584 + BT_TASK_EXTRA_STACK_SIZE)
+
+
+/* idf task */
+#define ESP_TASK_TIMER_PRIO           (ESP_TASK_PRIO_MAX - 3)
+#define ESP_TASK_TIMER_STACK          CONFIG_TIMER_TASK_STACK_SIZE
+#define ESP_TASKD_EVENT_PRIO          (ESP_TASK_PRIO_MAX - 5)
+#define ESP_TASKD_EVENT_STACK         CONFIG_SYSTEM_EVENT_TASK_STACK_SIZE
+#define ESP_TASK_TCPIP_PRIO           (ESP_TASK_PRIO_MAX - 7)
+#define ESP_TASK_TCPIP_STACK          CONFIG_TCPIP_TASK_STACK_SIZE
+#define ESP_TASK_MAIN_PRIO            (ESP_TASK_PRIO_MIN + 1)
+#define ESP_TASK_MAIN_STACK           CONFIG_MAIN_TASK_STACK_SIZE
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_task_wdt.h

@@ -0,0 +1,74 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_TASK_WDT_H
+#define __ESP_TASK_WDT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** \defgroup Watchdog_APIs Watchdog APIs
+  * @brief Watchdog APIs
+  */
+
+/** @addtogroup Watchdog_APIs
+  * @{
+  */
+
+/*
+This routine enables a more general-purpose task watchdog: tasks can individually
+feed the watchdog and the watchdog will bark if one or more tasks haven't fed the
+watchdog within the specified time. Optionally, the idle tasks can also configured
+to feed the watchdog in a similar fashion, to detect CPU starvation.
+
+This uses the TIMERG0 WDT.
+*/
+
+
+/**
+  * @brief  Initialize the task watchdog. This is called in the init code, if the
+  *         task watchdog is enabled in menuconfig.
+  *
+  */
+void esp_task_wdt_init();
+
+/**
+  * @brief  Feed the watchdog. After the first feeding session, the watchdog will expect the calling
+  *         task to keep feeding the watchdog until task_wdt_delete() is called.
+  *
+  */
+
+void esp_task_wdt_feed();
+
+
+/**
+  * @brief  Delete the watchdog for the current task.
+  *
+  */
+void esp_task_wdt_delete();
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_timer.h

@@ -0,0 +1,229 @@
+// Copyright 2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file esp_timer.h
+ * @brief microsecond-precision 64-bit timer API, replacement for ets_timer
+ *
+ * Not a public header yet. To be moved into include/ directory when it is made
+ * public.
+ *
+ * esp_timer APIs allow components to receive callbacks when a hardware timer
+ * reaches certain value. The timer provides microsecond accuracy and
+ * up to 64 bit range. Note that while the timer itself provides microsecond
+ * accuracy, callbacks are dispatched from an auxiliary task. Some time is
+ * needed to notify this task from timer ISR, and then to invoke the callback.
+ * If more than one callback needs to be dispatched at any particular time,
+ * each subsequent callback will be dispatched only when the previous callback
+ * returns. Therefore, callbacks should not do much work; instead, they should
+ * use RTOS notification mechanisms (queues, semaphores, event groups, etc.) to
+ * pass information to other tasks.
+ *
+ * <to be implemented> It should be possible to request the callback to be called
+ * directly from the ISR. This reduces the latency, but has potential impact on
+ * all other callbacks which need to be dispatched. This option should only be
+ * used for simple callback functions, which do not take longer than a few
+ * microseconds to run. </to be implemented>
+ *
+ * Implementation note: on the ESP32, esp_timer APIs use the "legacy" FRC2
+ * timer. Timer callbacks are called from a task running on the PRO CPU.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Opaque type representing a single esp_timer
+ */
+typedef struct esp_timer* esp_timer_handle_t;
+
+/**
+ * @brief Timer callback function type
+ * @param arg pointer to opaque user-specific data
+ */
+typedef void (*esp_timer_cb_t)(void* arg);
+
+
+/**
+ * @brief Method for dispatching timer callback
+ */
+typedef enum {
+    ESP_TIMER_TASK,     //!< Callback is called from timer task
+
+    /* Not supported for now, provision to allow callbacks to run directly
+     * from an ISR:
+
+        ESP_TIMER_ISR,      //!< Callback is called from timer ISR
+
+     */
+} esp_timer_dispatch_t;
+
+/**
+ * @brief Timer configuration passed to esp_timer_create
+ */
+typedef struct {
+    esp_timer_cb_t callback;        //!< Function to call when timer expires
+    void* arg;                      //!< Argument to pass to the callback
+    esp_timer_dispatch_t dispatch_method;   //!< Call the callback from task or from ISR
+    const char* name;               //!< Timer name, used in esp_timer_dump function
+} esp_timer_create_args_t;
+
+/**
+ * @brief Initialize esp_timer library
+ *
+ * @note This function is called from startup code. Applications do not need
+ * to call this function before using other esp_timer APIs.
+ *
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_NO_MEM if allocation has failed
+ *      - ESP_ERR_INVALID_STATE if already initialized
+ *      - other errors from interrupt allocator
+ */
+esp_err_t esp_timer_init();
+
+/**
+ * @brief De-initialize esp_timer library
+ *
+ * @note Normally this function should not be called from applications
+ *
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if not yet initialized
+ */
+esp_err_t esp_timer_deinit();
+
+/**
+ * @brief Create an esp_timer instance
+ *
+ * @note When done using the timer, delete it with esp_timer_delete function.
+ *
+ * @param create_args   Pointer to a structure with timer creation arguments.
+ *                      Not saved by the library, can be allocated on the stack.
+ * @param[out] out_handle  Output, pointer to esp_timer_handle_t variable which
+ *                         will hold the created timer handle.
+ *
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if some of the create_args are not valid
+ *      - ESP_ERR_INVALID_STATE if esp_timer library is not initialized yet
+ *      - ESP_ERR_NO_MEM if memory allocation fails
+ */
+esp_err_t esp_timer_create(const esp_timer_create_args_t* create_args,
+                           esp_timer_handle_t* out_handle);
+
+/**
+ * @brief Start one-shot timer
+ *
+ * Timer should not be running when this function is called.
+ *
+ * @param timer timer handle created using esp_timer_create
+ * @param timeout_us timer timeout, in microseconds relative to the current moment
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if the handle is invalid
+ *      - ESP_ERR_INVALID_STATE if the timer is already running
+ */
+esp_err_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us);
+
+/**
+ * @brief Start a periodic timer
+ *
+ * Timer should not be running when this function is called. This function will
+ * start the timer which will trigger every 'period' microseconds.
+ *
+ * @param timer timer handle created using esp_timer_create
+ * @param period timer period, in microseconds
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_ARG if the handle is invalid
+ *      - ESP_ERR_INVALID_STATE if the timer is already running
+ */
+esp_err_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period);
+
+/**
+ * @brief Stop the timer
+ *
+ * This function stops the timer previously started using esp_timer_start_once
+ * or esp_timer_start_periodic.
+ *
+ * @param timer timer handle created using esp_timer_create
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if the timer is not running
+ */
+esp_err_t esp_timer_stop(esp_timer_handle_t timer);
+
+/**
+ * @brief Delete an esp_timer instance
+ *
+ * The timer must be stopped before deleting. A one-shot timer which has expired
+ * does not need to be stopped.
+ *
+ * @param timer timer handle allocated using esp_timer_create
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_INVALID_STATE if the timer is not running
+ */
+esp_err_t esp_timer_delete(esp_timer_handle_t timer);
+
+/**
+ * @brief Get time in microseconds since boot
+ * @return number of microseconds since esp_timer_init was called (this normally
+ *          happens early during application startup).
+ */
+int64_t esp_timer_get_time();
+
+/**
+ * @brief Dump the list of timers to a stream
+ *
+ * If CONFIG_ESP_TIMER_PROFILING option is enabled, this prints the list of all
+ * the existing timers. Otherwise, only the list active timers is printed.
+ *
+ * The format is:
+ *
+ *   name  period  alarm  times_armed  times_triggered  total_callback_run_time
+ *
+ * where:
+ *
+ * name — timer name (if CONFIG_ESP_TIMER_PROFILING is defined), or timer pointer
+ * period — period of timer, in microseconds, or 0 for one-shot timer
+ * alarm - time of the next alarm, in microseconds since boot, or 0 if the timer
+ *         is not started
+ *
+ * The following fields are printed if CONFIG_ESP_TIMER_PROFILING is defined:
+ *
+ * times_armed — number of times the timer was armed via esp_timer_start_X
+ * times_triggered - number of times the callback was called
+ * total_callback_run_time - total time taken by callback to execute, across all calls
+ *
+ * @param stream stream (such as stdout) to dump the information to
+ * @return
+ *      - ESP_OK on success
+ *      - ESP_ERR_NO_MEM if can not allocate temporary buffer for the output
+ */
+esp_err_t esp_timer_dump(FILE* stream);
+
+
+#ifdef __cplusplus
+}
+#endif
+

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_types.h

@@ -0,0 +1,25 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_TYPES_H__
+#define __ESP_TYPES_H__
+
+#ifdef __GNUC__
+#include <sys/cdefs.h>
+#endif /*__GNUC__*/
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#endif /* __ESP_TYPES_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_wifi.h

@@ -0,0 +1,864 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+/*               Notes about WiFi Programming
+ *
+ *  The esp32 WiFi programming model can be depicted as following picture:
+ *
+ *
+ *                            default handler              user handler
+ *  -------------             ---------------             ---------------
+ *  |           |   event     |             | callback or |             |
+ *  |   tcpip   | --------->  |    event    | ----------> | application |
+ *  |   stack   |             |     task    |  event      |    task     |
+ *  |-----------|             |-------------|             |-------------|
+ *                                  /|\                          |
+ *                                   |                           |
+ *                            event  |                           |
+ *                                   |                           |
+ *                                   |                           |
+ *                             ---------------                   |
+ *                             |             |                   |
+ *                             | WiFi Driver |/__________________|
+ *                             |             |\     API call
+ *                             |             |
+ *                             |-------------|
+ *
+ * The WiFi driver can be consider as black box, it knows nothing about the high layer code, such as
+ * TCPIP stack, application task, event task etc, all it can do is to receive API call from high layer
+ * or post event queue to a specified Queue, which is initialized by API esp_wifi_init().
+ *
+ * The event task is a daemon task, which receives events from WiFi driver or from other subsystem, such
+ * as TCPIP stack, event task will call the default callback function on receiving the event. For example,
+ * on receiving event SYSTEM_EVENT_STA_CONNECTED, it will call tcpip_adapter_start() to start the DHCP
+ * client in it's default handler.
+ *
+ * Application can register it's own event callback function by API esp_event_init, then the application callback
+ * function will be called after the default callback. Also, if application doesn't want to execute the callback
+ * in the event task, what it needs to do is to post the related event to application task in the application callback function.
+ *
+ * The application task (code) generally mixes all these thing together, it calls APIs to init the system/WiFi and
+ * handle the events when necessary.
+ *
+ */
+
+#ifndef __ESP_WIFI_H__
+#define __ESP_WIFI_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "rom/queue.h"
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_wifi_types.h"
+#include "esp_wifi_crypto_types.h"
+#include "esp_event.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ESP_ERR_WIFI_OK          ESP_OK                    /*!< No error */
+#define ESP_ERR_WIFI_FAIL        ESP_FAIL                  /*!< General fail code */
+#define ESP_ERR_WIFI_NO_MEM      ESP_ERR_NO_MEM            /*!< Out of memory */
+#define ESP_ERR_WIFI_ARG         ESP_ERR_INVALID_ARG       /*!< Invalid argument */
+#define ESP_ERR_WIFI_NOT_SUPPORT ESP_ERR_NOT_SUPPORTED     /*!< Indicates that API is not supported yet */
+
+#define ESP_ERR_WIFI_NOT_INIT    (ESP_ERR_WIFI_BASE + 1)   /*!< WiFi driver was not installed by esp_wifi_init */
+#define ESP_ERR_WIFI_NOT_STARTED (ESP_ERR_WIFI_BASE + 2)   /*!< WiFi driver was not started by esp_wifi_start */
+#define ESP_ERR_WIFI_NOT_STOPPED (ESP_ERR_WIFI_BASE + 3)   /*!< WiFi driver was not stopped by esp_wifi_stop */
+#define ESP_ERR_WIFI_IF          (ESP_ERR_WIFI_BASE + 4)   /*!< WiFi interface error */
+#define ESP_ERR_WIFI_MODE        (ESP_ERR_WIFI_BASE + 5)   /*!< WiFi mode error */
+#define ESP_ERR_WIFI_STATE       (ESP_ERR_WIFI_BASE + 6)   /*!< WiFi internal state error */
+#define ESP_ERR_WIFI_CONN        (ESP_ERR_WIFI_BASE + 7)   /*!< WiFi internal control block of station or soft-AP error */
+#define ESP_ERR_WIFI_NVS         (ESP_ERR_WIFI_BASE + 8)   /*!< WiFi internal NVS module error */
+#define ESP_ERR_WIFI_MAC         (ESP_ERR_WIFI_BASE + 9)   /*!< MAC address is invalid */
+#define ESP_ERR_WIFI_SSID        (ESP_ERR_WIFI_BASE + 10)   /*!< SSID is invalid */
+#define ESP_ERR_WIFI_PASSWORD    (ESP_ERR_WIFI_BASE + 11)  /*!< Password is invalid */
+#define ESP_ERR_WIFI_TIMEOUT     (ESP_ERR_WIFI_BASE + 12)  /*!< Timeout error */
+#define ESP_ERR_WIFI_WAKE_FAIL   (ESP_ERR_WIFI_BASE + 13)  /*!< WiFi is in sleep state(RF closed) and wakeup fail */
+
+/**
+ * @brief WiFi stack configuration parameters passed to esp_wifi_init call.
+ */
+typedef struct {
+    system_event_handler_t event_handler;          /**< WiFi event handler */
+    wpa_crypto_funcs_t     wpa_crypto_funcs;       /**< WiFi station crypto functions when connect */
+    int                    static_rx_buf_num;      /**< WiFi static RX buffer number */
+    int                    dynamic_rx_buf_num;     /**< WiFi dynamic RX buffer number */
+    int                    tx_buf_type;            /**< WiFi TX buffer type */
+    int                    static_tx_buf_num;      /**< WiFi static TX buffer number */
+    int                    dynamic_tx_buf_num;     /**< WiFi dynamic TX buffer number */
+    int                    ampdu_enable;           /**< WiFi AMPDU feature enable flag */
+    int                    nvs_enable;             /**< WiFi NVS flash enable flag */
+    int                    nano_enable;            /**< Nano option for printf/scan family enable flag */
+    int                    tx_ba_win;              /**< WiFi Block Ack TX window size */
+    int                    rx_ba_win;              /**< WiFi Block Ack RX window size */
+    int                    magic;                  /**< WiFi init magic number, it should be the last field */
+} wifi_init_config_t;
+
+#ifdef CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM
+#define WIFI_STATIC_TX_BUFFER_NUM CONFIG_ESP32_WIFI_STATIC_TX_BUFFER_NUM
+#else
+#define WIFI_STATIC_TX_BUFFER_NUM 0
+#endif
+
+#ifdef CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM
+#define WIFI_DYNAMIC_TX_BUFFER_NUM CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM
+#else
+#define WIFI_DYNAMIC_TX_BUFFER_NUM 0
+#endif
+
+#if CONFIG_ESP32_WIFI_AMPDU_ENABLED
+#define WIFI_AMPDU_ENABLED        1
+#else
+#define WIFI_AMPDU_ENABLED        0
+#endif
+
+#if CONFIG_ESP32_WIFI_NVS_ENABLED
+#define WIFI_NVS_ENABLED          1
+#else
+#define WIFI_NVS_ENABLED          0
+#endif
+
+#if CONFIG_NEWLIB_NANO_FORMAT
+#define WIFI_NANO_FORMAT_ENABLED  1
+#else
+#define WIFI_NANO_FORMAT_ENABLED  0
+#endif
+
+extern const wpa_crypto_funcs_t g_wifi_default_wpa_crypto_funcs;
+
+#define WIFI_INIT_CONFIG_MAGIC    0x1F2F3F4F
+
+#ifdef CONFIG_ESP32_WIFI_AMPDU_ENABLED
+#define WIFI_DEFAULT_TX_BA_WIN CONFIG_ESP32_WIFI_TX_BA_WIN
+#define WIFI_DEFAULT_RX_BA_WIN CONFIG_ESP32_WIFI_RX_BA_WIN
+#else
+#define WIFI_DEFAULT_TX_BA_WIN 0 /* unused if ampdu_enable == false */
+#define WIFI_DEFAULT_RX_BA_WIN 0
+#endif
+
+#define WIFI_INIT_CONFIG_DEFAULT() { \
+    .event_handler = &esp_event_send, \
+    .wpa_crypto_funcs = g_wifi_default_wpa_crypto_funcs, \
+    .static_rx_buf_num = CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM,\
+    .dynamic_rx_buf_num = CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM,\
+    .tx_buf_type = CONFIG_ESP32_WIFI_TX_BUFFER_TYPE,\
+    .static_tx_buf_num = WIFI_STATIC_TX_BUFFER_NUM,\
+    .dynamic_tx_buf_num = WIFI_DYNAMIC_TX_BUFFER_NUM,\
+    .ampdu_enable = WIFI_AMPDU_ENABLED,\
+    .nvs_enable = WIFI_NVS_ENABLED,\
+    .nano_enable = WIFI_NANO_FORMAT_ENABLED,\
+    .tx_ba_win = WIFI_DEFAULT_TX_BA_WIN,\
+    .rx_ba_win = WIFI_DEFAULT_RX_BA_WIN,\
+    .magic = WIFI_INIT_CONFIG_MAGIC\
+};
+
+/**
+  * @brief  Init WiFi
+  *         Alloc resource for WiFi driver, such as WiFi control structure, RX/TX buffer,
+  *         WiFi NVS structure etc, this WiFi also start WiFi task
+  *
+  * @attention 1. This API must be called before all other WiFi API can be called
+  * @attention 2. Always use WIFI_INIT_CONFIG_DEFAULT macro to init the config to default values, this can
+  *               guarantee all the fields got correct value when more fields are added into wifi_init_config_t
+  *               in future release. If you want to set your owner initial values, overwrite the default values
+  *               which are set by WIFI_INIT_CONFIG_DEFAULT, please be notified that the field 'magic' of 
+  *               wifi_init_config_t should always be WIFI_INIT_CONFIG_MAGIC!
+  *
+  * @param  config provide WiFi init configuration
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NO_MEM: out of memory
+  *    - others: refer to error code esp_err.h
+  */
+esp_err_t esp_wifi_init(wifi_init_config_t *config);
+
+/**
+  * @brief  Deinit WiFi
+  *         Free all resource allocated in esp_wifi_init and stop WiFi task
+  *
+  * @attention 1. This API should be called if you want to remove WiFi driver from the system
+  *
+  * @return ESP_OK: succeed
+  */
+esp_err_t esp_wifi_deinit(void);
+
+/**
+  * @brief     Set the WiFi operating mode
+  *
+  *            Set the WiFi operating mode as station, soft-AP or station+soft-AP,
+  *            The default mode is soft-AP mode.
+  *
+  * @param     mode  WiFi operating mode
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - others: refer to error code in esp_err.h
+  */
+esp_err_t esp_wifi_set_mode(wifi_mode_t mode);
+
+/**
+  * @brief  Get current operating mode of WiFi
+  *
+  * @param[out]  mode  store current WiFi mode
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_get_mode(wifi_mode_t *mode);
+
+/**
+  * @brief  Start WiFi according to current configuration
+  *         If mode is WIFI_MODE_STA, it create station control block and start station
+  *         If mode is WIFI_MODE_AP, it create soft-AP control block and start soft-AP
+  *         If mode is WIFI_MODE_APSTA, it create soft-AP and station control block and start soft-AP and station
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - ESP_ERR_WIFI_NO_MEM: out of memory
+  *    - ESP_ERR_WIFI_CONN: WiFi internal error, station or soft-AP control block wrong
+  *    - ESP_ERR_WIFI_FAIL: other WiFi internal errors
+  */
+esp_err_t esp_wifi_start(void);
+
+/**
+  * @brief  Stop WiFi
+  *         If mode is WIFI_MODE_STA, it stop station and free station control block
+  *         If mode is WIFI_MODE_AP, it stop soft-AP and free soft-AP control block
+  *         If mode is WIFI_MODE_APSTA, it stop station/soft-AP and free station/soft-AP control block
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  */
+esp_err_t esp_wifi_stop(void);
+
+/**
+ * @brief  Restore WiFi stack persistent settings to default values
+ *
+ * This function will reset settings made using the following APIs:
+ * - esp_wifi_get_auto_connect,
+ * - esp_wifi_set_protocol,
+ * - esp_wifi_set_config related
+ * - esp_wifi_set_mode
+ *
+ * @return
+ *    - ESP_OK: succeed
+ *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+ */
+esp_err_t esp_wifi_restore(void);
+
+/**
+  * @brief     Connect the ESP32 WiFi station to the AP.
+  *
+  * @attention 1. This API only impact WIFI_MODE_STA or WIFI_MODE_APSTA mode
+  * @attention 2. If the ESP32 is connected to an AP, call esp_wifi_disconnect to disconnect.
+  *
+  * @return 
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
+  *    - ESP_ERR_WIFI_CONN: WiFi internal error, station or soft-AP control block wrong
+  *    - ESP_ERR_WIFI_SSID: SSID of AP which station connects is invalid
+  */
+esp_err_t esp_wifi_connect(void);
+
+/**
+  * @brief     Disconnect the ESP32 WiFi station from the AP.
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi was not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
+  *    - ESP_ERR_WIFI_FAIL: other WiFi internal errors
+  */
+esp_err_t esp_wifi_disconnect(void);
+
+/**
+  * @brief     Currently this API is just an stub API
+  *
+
+  * @return
+  *    - ESP_OK: succeed
+  *    - others: fail
+  */
+esp_err_t esp_wifi_clear_fast_connect(void);
+
+/**
+  * @brief     deauthenticate all stations or associated id equals to aid
+  *
+  * @param     aid  when aid is 0, deauthenticate all stations, otherwise deauthenticate station whose associated id is aid
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - ESP_ERR_WIFI_MODE: WiFi mode is wrong
+  */
+esp_err_t esp_wifi_deauth_sta(uint16_t aid);
+
+/**
+  * @brief     Scan all available APs.
+  *
+  * @attention If this API is called, the found APs are stored in WiFi driver dynamic allocated memory and the
+  *            will be freed in esp_wifi_scan_get_ap_records, so generally, call esp_wifi_scan_get_ap_records to cause
+  *            the memory to be freed once the scan is done
+  * @attention The values of maximum active scan time and passive scan time per channel are limited to 1500 milliseconds.
+  *            Values above 1500ms may cause station to disconnect from AP and are not recommended.
+  *
+  * @param     config  configuration of scanning
+  * @param     block if block is true, this API will block the caller until the scan is done, otherwise
+  *                         it will return immediately
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi was not started by esp_wifi_start
+  *    - ESP_ERR_WIFI_TIMEOUT: blocking scan is timeout
+  *    - others: refer to error code in esp_err.h
+  */
+esp_err_t esp_wifi_scan_start(wifi_scan_config_t *config, bool block);
+
+/**
+  * @brief     Stop the scan in process
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
+  */
+esp_err_t esp_wifi_scan_stop(void);
+
+/**
+  * @brief     Get number of APs found in last scan
+  *
+  * @param[out] number  store number of APIs found in last scan
+  *
+  * @attention This API can only be called when the scan is completed, otherwise it may get wrong value.
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_scan_get_ap_num(uint16_t *number);
+
+/**
+  * @brief     Get AP list found in last scan
+  *
+  * @param[inout]  number As input param, it stores max AP number ap_records can hold. 
+  *                As output param, it receives the actual AP number this API returns.
+  * @param         ap_records  wifi_ap_record_t array to hold the found APs
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_NOT_STARTED: WiFi is not started by esp_wifi_start
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - ESP_ERR_WIFI_NO_MEM: out of memory
+  */
+esp_err_t esp_wifi_scan_get_ap_records(uint16_t *number, wifi_ap_record_t *ap_records);
+
+
+/**
+  * @brief     Get information of AP which the ESP32 station is associated with
+  *
+  * @param     ap_info  the wifi_ap_record_t to hold AP information
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - others: fail
+  */
+esp_err_t esp_wifi_sta_get_ap_info(wifi_ap_record_t *ap_info);
+
+/**
+  * @brief     Set current power save type
+  *
+  * @attention Default power save type is WIFI_PS_NONE.
+  *
+  * @param     type  power save type
+  *
+  * @return    ESP_ERR_WIFI_NOT_SUPPORT: not supported yet
+  */
+esp_err_t esp_wifi_set_ps(wifi_ps_type_t type);
+
+/**
+  * @brief     Get current power save type
+  *
+  * @attention Default power save type is WIFI_PS_NONE.
+  *
+  * @param[out]  type: store current power save type
+  *
+  * @return    ESP_ERR_WIFI_NOT_SUPPORT: not supported yet
+  */
+esp_err_t esp_wifi_get_ps(wifi_ps_type_t *type);
+
+/**
+  * @brief     Set protocol type of specified interface
+  *            The default protocol is (WIFI_PROTOCOL_11B|WIFI_PROTOCOL_11G|WIFI_PROTOCOL_11N)
+  *
+  * @attention Currently we only support 802.11b or 802.11bg or 802.11bgn mode
+  *
+  * @param     ifx  interfaces
+  * @param     protocol_bitmap  WiFi protocol bitmap
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_IF: invalid interface
+  *    - others: refer to error codes in esp_err.h
+  */
+esp_err_t esp_wifi_set_protocol(wifi_interface_t ifx, uint8_t protocol_bitmap);
+
+/**
+  * @brief     Get the current protocol bitmap of the specified interface
+  *
+  * @param     ifx  interface
+  * @param[out] protocol_bitmap  store current WiFi protocol bitmap of interface ifx
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_IF: invalid interface
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - others: refer to error codes in esp_err.h
+  */
+esp_err_t esp_wifi_get_protocol(wifi_interface_t ifx, uint8_t *protocol_bitmap);
+
+/**
+  * @brief     Set the bandwidth of ESP32 specified interface
+  *
+  * @attention 1. API return false if try to configure an interface that is not enabled
+  * @attention 2. WIFI_BW_HT40 is supported only when the interface support 11N
+  *
+  * @param     ifx  interface to be configured
+  * @param     bw  bandwidth
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_IF: invalid interface
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - others: refer to error codes in esp_err.h
+  */
+esp_err_t esp_wifi_set_bandwidth(wifi_interface_t ifx, wifi_bandwidth_t bw);
+
+/**
+  * @brief     Get the bandwidth of ESP32 specified interface
+  *
+  * @attention 1. API return false if try to get a interface that is not enable
+  *
+  * @param     ifx interface to be configured
+  * @param[out] bw  store bandwidth of interface ifx
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_IF: invalid interface
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_get_bandwidth(wifi_interface_t ifx, wifi_bandwidth_t *bw);
+
+/**
+  * @brief     Set primary/secondary channel of ESP32
+  *
+  * @attention 1. This is a special API for sniffer
+  * @attention 2. This API should be called after esp_wifi_start() or esp_wifi_set_promiscuous()
+  *
+  * @param     primary  for HT20, primary is the channel number, for HT40, primary is the primary channel
+  * @param     second   for HT20, second is ignored, for HT40, second is the second channel
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_IF: invalid interface
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_set_channel(uint8_t primary, wifi_second_chan_t second);
+
+/**
+  * @brief     Get the primary/secondary channel of ESP32
+  *
+  * @attention 1. API return false if try to get a interface that is not enable
+  *
+  * @param     primary   store current primary channel
+  * @param[out]  second  store current second channel
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_get_channel(uint8_t *primary, wifi_second_chan_t *second);
+
+/**
+  * @brief     Set country code
+  *            The default value is WIFI_COUNTRY_CN
+  *
+  * @param     country  country type
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - others: refer to error code in esp_err.h
+  */
+esp_err_t esp_wifi_set_country(wifi_country_t country);
+
+/**
+  * @brief     Get country code
+  *
+  * @param     country  store current country
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_get_country(wifi_country_t *country);
+
+/**
+  * @brief     Set MAC address of the ESP32 WiFi station or the soft-AP interface.
+  *
+  * @attention 1. This API can only be called when the interface is disabled
+  * @attention 2. ESP32 soft-AP and station have different MAC addresses, do not set them to be the same.
+  * @attention 3. The bit 0 of the first byte of ESP32 MAC address can not be 1. For example, the MAC address
+  *      can set to be "1a:XX:XX:XX:XX:XX", but can not be "15:XX:XX:XX:XX:XX".
+  *
+  * @param     ifx  interface
+  * @param     mac  the MAC address
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - ESP_ERR_WIFI_IF: invalid interface
+  *    - ESP_ERR_WIFI_MAC: invalid mac address
+  *    - ESP_ERR_WIFI_MODE: WiFi mode is wrong
+  *    - others: refer to error codes in esp_err.h
+  */
+esp_err_t esp_wifi_set_mac(wifi_interface_t ifx, uint8_t mac[6]);
+
+/**
+  * @brief     Get mac of specified interface
+  *
+  * @param      ifx  interface
+  * @param[out] mac  store mac of the interface ifx
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - ESP_ERR_WIFI_IF: invalid interface
+  */
+esp_err_t esp_wifi_get_mac(wifi_interface_t ifx, uint8_t mac[6]);
+
+/**
+  * @brief The RX callback function in the promiscuous mode. 
+  *        Each time a packet is received, the callback function will be called.
+  *
+  * @param buf  Data received. Type of data in buffer (wifi_promiscuous_pkt_t or wifi_pkt_rx_ctrl_t) indicated by 'type' parameter.
+  * @param type  promiscuous packet type.
+  *
+  */
+typedef void (* wifi_promiscuous_cb_t)(void *buf, wifi_promiscuous_pkt_type_t type);
+
+/**
+  * @brief Register the RX callback function in the promiscuous mode.
+  *
+  * Each time a packet is received, the registered callback function will be called.
+  *
+  * @param cb  callback
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  */
+esp_err_t esp_wifi_set_promiscuous_rx_cb(wifi_promiscuous_cb_t cb);
+
+/**
+  * @brief     Enable the promiscuous mode.
+  *
+  * @param     en  false - disable, true - enable
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  */
+esp_err_t esp_wifi_set_promiscuous(bool en);
+
+/**
+  * @brief     Get the promiscuous mode.
+  *
+  * @param[out] en  store the current status of promiscuous mode
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_get_promiscuous(bool *en);
+
+/**
+  * @brief     Enable the promiscuous filter.
+  *
+  * @attention 1. The default filter is to filter all packets except WIFI_PKT_MISC
+  *
+  * @param     filter the packet type filtered by promisucous
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  */
+esp_err_t esp_wifi_set_promiscuous_filter(const wifi_promiscuous_filter_t *filter);
+
+/**
+  * @brief     Get the promiscuous filter.
+  *
+  * @param[out] filter  store the current status of promiscuous filter
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_get_promiscuous_filter(wifi_promiscuous_filter_t *filter);
+
+/**
+  * Description: enable/disable autoack in promiscous mode and set MAC address of promiscous interface.
+  *
+  * Param: autoack: true - enable autoack in promiscous mode
+  *                 false - disable autoack in promiscous mode
+  *        mac - MAC address of promiscous interface, 6 bytes
+  *
+  * return: ESP_ERR_WIFI_OK - succeed
+  *         ESP_ERR_WIFI_ARG - mac is NULL
+**/
+esp_err_t esp_wifi_set_promiscous_autoack(bool autoack, uint8_t *mac);
+
+/**
+  * @brief     Set the configuration of the ESP32 STA or AP
+  *
+  * @attention 1. This API can be called only when specified interface is enabled, otherwise, API fail
+  * @attention 2. For station configuration, bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.
+  * @attention 3. ESP32 is limited to only one channel, so when in the soft-AP+station mode, the soft-AP will adjust its channel automatically to be the same as
+  *               the channel of the ESP32 station.
+  *
+  * @param     ifx  interface
+  * @param     conf  station or soft-AP configuration
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - ESP_ERR_WIFI_IF: invalid interface
+  *    - ESP_ERR_WIFI_MODE: invalid mode
+  *    - ESP_ERR_WIFI_PASSWORD: invalid password
+  *    - ESP_ERR_WIFI_NVS: WiFi internal NVS error
+  *    - others: refer to the erro code in esp_err.h
+  */
+esp_err_t esp_wifi_set_config(wifi_interface_t ifx, wifi_config_t *conf);
+
+/**
+  * @brief     Get configuration of specified interface
+  *
+  * @param     ifx  interface
+  * @param[out]  conf  station or soft-AP configuration
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - ESP_ERR_WIFI_IF: invalid interface
+  */
+esp_err_t esp_wifi_get_config(wifi_interface_t ifx, wifi_config_t *conf);
+
+/**
+  * @brief     Get STAs associated with soft-AP
+  *
+  * @attention SSC only API
+  *
+  * @param[out] sta  station list
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  *    - ESP_ERR_WIFI_MODE: WiFi mode is wrong
+  *    - ESP_ERR_WIFI_CONN: WiFi internal error, the station/soft-AP control block is invalid
+  */
+esp_err_t esp_wifi_ap_get_sta_list(wifi_sta_list_t *sta);
+
+
+/**
+  * @brief     Set the WiFi API configuration storage type
+  *
+  * @attention 1. The default value is WIFI_STORAGE_FLASH
+  *
+  * @param     storage : storage type
+  *
+  * @return
+  *   - ESP_OK: succeed
+  *   - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *   - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_set_storage(wifi_storage_t storage);
+
+/**
+  * @brief     Set auto connect
+  *            The default value is true
+  *
+  * @param     en : true - enable auto connect / false - disable auto connect
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_MODE: WiFi internal error, the station/soft-AP control block is invalid
+  *    - others: refer to error code in esp_err.h
+  */
+esp_err_t esp_wifi_set_auto_connect(bool en);
+
+/**
+  * @brief     Get the auto connect flag
+  *
+  * @param[out] en  store current auto connect configuration
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_get_auto_connect(bool *en);
+
+/**
+  * @brief     Set 802.11 Vendor-Specific Information Element
+  *
+  * @param     enable If true, specified IE is enabled. If false, specified IE is removed.
+  * @param     type Information Element type. Determines the frame type to associate with the IE.
+  * @param     idx  Index to set or clear. Each IE type can be associated with up to two elements (indices 0 & 1).
+  * @param     vnd_ie Pointer to vendor specific element data. First 6 bytes should be a header with fields matching vendor_ie_data_t.
+  *            If enable is false, this argument is ignored and can be NULL. Data does not need to remain valid after the function returns.
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init()
+  *    - ESP_ERR_WIFI_ARG: Invalid argument, including if first byte of vnd_ie is not WIFI_VENDOR_IE_ELEMENT_ID (0xDD)
+  *      or second byte is an invalid length.
+  *    - ESP_ERR_WIFI_NO_MEM: Out of memory
+  */
+esp_err_t esp_wifi_set_vendor_ie(bool enable, wifi_vendor_ie_type_t type, wifi_vendor_ie_id_t idx, const void *vnd_ie);
+
+/**
+  * @brief     Function signature for received Vendor-Specific Information Element callback.
+  * @param     ctx Context argument, as passed to esp_wifi_set_vendor_ie_cb() when registering callback.
+  * @param     type Information element type, based on frame type received.
+  * @param     sa Source 802.11 address.
+  * @param     vnd_ie Pointer to the vendor specific element data received.
+  * @param     rssi Received signal strength indication.
+  */
+typedef void (*esp_vendor_ie_cb_t) (void *ctx, wifi_vendor_ie_type_t type, const uint8_t sa[6], const vendor_ie_data_t *vnd_ie, int rssi);
+
+/**
+  * @brief     Register Vendor-Specific Information Element monitoring callback.
+  *
+  * @param     cb   Callback function
+  * @param     ctx  Context argument, passed to callback function.
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  */
+esp_err_t esp_wifi_set_vendor_ie_cb(esp_vendor_ie_cb_t cb, void *ctx);
+
+/**
+  * @brief     Set maximum WiFi transmiting power
+  *
+  * @attention WiFi transmiting power is divided to six levels in phy init data.
+  *            Level0 represents highest transmiting power and level5 represents lowest
+  *            transmiting power. Packets of different rates are transmitted in
+  *            different powers according to the configuration in phy init data.
+  *            This API only sets maximum WiFi transmiting power. If this API is called,
+  *            the transmiting power of every packet will be less than or equal to the
+  *            value set by this API. If this API is not called, the value of maximum
+  *            transmitting power set in phy_init_data.bin or menuconfig (depend on
+  *            whether to use phy init data in partition or not) will be used. Default
+  *            value is level0. Values passed in power are mapped to transmit power
+  *            levels as follows:
+  *            - [78, 127]: level0
+  *            - [76, 77]: level1
+  *            - [74, 75]: level2
+  *            - [68, 73]: level3
+  *            - [60, 67]: level4
+  *            - [52, 59]: level5
+  *            - [44, 51]: level5 - 2dBm
+  *            - [34, 43]: level5 - 4.5dBm
+  *            - [28, 33]: level5 - 6dBm
+  *            - [20, 27]: level5 - 8dBm
+  *            - [8, 19]: level5 - 11dBm
+  *            - [-128, 7]: level5 - 14dBm
+  *
+  * @param     power  Maximum WiFi transmiting power.
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
+  */
+esp_err_t esp_wifi_set_max_tx_power(int8_t power);
+
+/**
+  * @brief     Get maximum WiFi transmiting power
+  *
+  * @attention This API gets maximum WiFi transmiting power. Values got
+  *            from power are mapped to transmit power levels as follows:
+  *            - 78: 19.5dBm
+  *            - 76: 19dBm
+  *            - 74: 18.5dBm
+  *            - 68: 17dBm
+  *            - 60: 15dBm
+  *            - 52: 13dBm
+  *            - 44: 11dBm
+  *            - 34: 8.5dBm
+  *            - 28: 7dBm
+  *            - 20: 5dBm
+  *            - 8:  2dBm
+  *            - -4: -1dBm
+  *
+  * @param     power  Maximum WiFi transmiting power.
+  *
+  * @return
+  *    - ESP_OK: succeed
+  *    - ESP_ERR_WIFI_NOT_INIT: WiFi is not initialized by esp_wifi_init
+  *    - ESP_ERR_WIFI_NOT_START: WiFi is not started by esp_wifi_start
+  *    - ESP_ERR_WIFI_ARG: invalid argument
+  */
+esp_err_t esp_wifi_get_max_tx_power(int8_t *power);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_WIFI_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_wifi_crypto_types.h

@@ -0,0 +1,301 @@
+// Hardware crypto support Copyright 2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef __ESP_WIFI_CRYPTO_TYPES_H__
+#define __ESP_WIFI_CRYPTO_TYPES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This enumation is about alorigthm will be set when do crypt hash 
+ * operation.When do wpa2 connecting, after invoke crypto_hash_xxx of
+ * fast_crypto_hash_xxx API, it will do relation crypt operation according
+ * to the enumation.
+ */
+typedef enum {
+    ESP_CRYPTO_HASH_ALG_MD5, ESP_CRYPTO_HASH_ALG_SHA1,
+    ESP_CRYPTO_HASH_ALG_HMAC_MD5, ESP_CRYPTO_HASH_ALG_HMAC_SHA1,
+    ESP_CRYPTO_HASH_ALG_SHA256, ESP_CRYPTO_HASH_ALG_HMAC_SHA256
+}esp_crypto_hash_alg_t;
+
+/*
+ * This enumation is about alorigthm will be set when do crypt cipher 
+ * operation.When do wpa2 connecting, after invoke crypto_cipher_xxx of
+ * fast_crypto_cipher_xxx API, it will do relation crypt operation according
+ * to the enumation.
+ */
+typedef enum {
+    ESP_CRYPTO_CIPHER_NULL, ESP_CRYPTO_CIPHER_ALG_AES, ESP_CRYPTO_CIPHER_ALG_3DES,
+    ESP_CRYPTO_CIPHER_ALG_DES, ESP_CRYPTO_CIPHER_ALG_RC2, ESP_CRYPTO_CIPHER_ALG_RC4
+} esp_crypto_cipher_alg_t;
+
+/*
+ * This structure is about the algorithm when do crypto_hash operation, for detail, 
+ * please reference to the structure crypto_hash.
+ */
+typedef struct crypto_hash esp_crypto_hash_t;
+
+/*
+ * This structure is about the algorithm when do crypto_cipher operation, for detail, 
+ * please reference to the structure crypto_cipher.
+ */
+typedef struct crypto_cipher esp_crypto_cipher_t;
+
+/**
+  * @brief The crypto callback function used in wpa enterprise hash operation when connect.
+  *        Initialize a esp_crypto_hash_t structure.
+  *
+  * @param alg  Hash algorithm.
+  * @param key  Key for keyed hash (e.g., HMAC) or %NULL if not needed.
+  * @param key_len  Length of the key in bytes
+  *
+  */
+typedef esp_crypto_hash_t * (*esp_crypto_hash_init_t)(esp_crypto_hash_alg_t alg, const unsigned char *key, int key_len);
+
+/**
+  * @brief The crypto callback function used in wpa enterprise hash operation when connect. 
+  *        Add data to hash calculation.
+  *
+  * @param ctz  Context pointer from esp_crypto_hash_init_t function.
+  * @param data  Data buffer to add.
+  * @param len  Length of the buffer.
+  *
+  */
+typedef void * (*esp_crypto_hash_update_t)(esp_crypto_hash_t *ctx, const unsigned char *data, int len);
+
+/**
+  * @brief The crypto callback function used in wpa enterprise hash operation when connect. 
+  *        Complete hash calculation.
+  *
+  * @param ctz  Context pointer from esp_crypto_hash_init_t function.
+  * @param hash   Buffer for hash value or %NULL if caller is just freeing the hash
+  *               context.
+  * @param len  Pointer to length of the buffer or %NULL if caller is just freeing the
+  *             hash context; on return, this is set to the actual length of the hash value
+  *             Returns: 0 on success, -1 if buffer is too small (len set to needed length),
+  *             or -2 on other failures (including failed crypto_hash_update() operations)
+  *
+  */
+typedef int * (*esp_crypto_hash_finish_t)(esp_crypto_hash_t *ctx, unsigned char *hash, int *len);
+
+/**
+  * @brief The AES callback function when do WPS connect. 
+  *
+  * @param key  Encryption key.
+  * @param iv  Encryption IV for CBC mode (16 bytes).
+  * @param data  Data to encrypt in-place.
+  * @param data_len  Length of data in bytes (must be divisible by 16)
+  */
+typedef int * (*esp_aes_128_encrypt_t)(const unsigned char *key, const unsigned char *iv, unsigned char *data, int data_len);
+
+/**
+  * @brief The AES callback function when do WPS connect. 
+  *
+  * @param key  Decryption key.
+  * @param iv  Decryption IV for CBC mode (16 bytes).
+  * @param data  Data to decrypt in-place.
+  * @param data_len  Length of data in bytes (must be divisible by 16)
+  *
+  */
+typedef int * (*esp_aes_128_decrypt_t)(const unsigned char *key, const unsigned char *iv, unsigned char *data, int data_len);
+
+/**
+  * @brief The AES callback function when do STA connect.
+  *
+  * @param kek  16-octet Key encryption key (KEK).
+  * @param n  Length of the plaintext key in 64-bit units;
+  * @param plain  Plaintext key to be wrapped, n * 64 bits
+  * @param cipher  Wrapped key, (n + 1) * 64 bits
+  *
+  */
+typedef int * (*esp_aes_wrap_t)(const unsigned char *kek, int n, const unsigned char *plain, unsigned char *cipher);
+
+/**
+  * @brief The AES callback function when do STA connect.
+  *
+  * @param kek  16-octet Key decryption key (KEK).
+  * @param n  Length of the plaintext key in 64-bit units;
+  * @param cipher  Wrapped key to be unwrapped, (n + 1) * 64 bits
+  * @param plain  Plaintext key, n * 64 bits
+  *
+  */
+typedef int * (*esp_aes_unwrap_t)(const unsigned char *kek, int n, const unsigned char *cipher, unsigned char *plain);
+
+/**
+  * @brief The crypto callback function used in wpa enterprise cipher operation when connect.
+  *        Initialize a esp_crypto_cipher_t structure.
+  *
+  * @param alg  cipher algorithm.
+  * @param iv  Initialization vector for block ciphers or %NULL for stream ciphers.
+  * @param key  Cipher key
+  * @param key_len  Length of key in bytes
+  *
+  */
+typedef esp_crypto_cipher_t * (*esp_crypto_cipher_init_t)(esp_crypto_cipher_alg_t alg, const unsigned char *iv, const unsigned char *key, int key_len);
+
+/**
+  * @brief The crypto callback function used in wpa enterprise cipher operation when connect.
+  *        Cipher encrypt.
+  *
+  * @param ctx  Context pointer from esp_crypto_cipher_init_t callback function.
+  * @param plain  Plaintext to cipher.
+  * @param crypt  Resulting ciphertext.
+  * @param len  Length of the plaintext.
+  *
+  */
+typedef int * (*esp_crypto_cipher_encrypt_t)(esp_crypto_cipher_t *ctx,
+				             const unsigned char *plain, unsigned char *crypt, int len);
+/**
+  * @brief The crypto callback function used in wpa enterprise cipher operation when connect.
+  *        Cipher decrypt.
+  *
+  * @param ctx  Context pointer from esp_crypto_cipher_init_t callback function.
+  * @param crypt  Ciphertext to decrypt.
+  * @param plain  Resulting plaintext.
+  * @param len  Length of the cipher text.
+  *
+  */
+typedef int * (*esp_crypto_cipher_decrypt_t)(esp_crypto_cipher_t *ctx,
+				             const unsigned char *crypt, unsigned char *plain, int len);
+/**
+  * @brief The crypto callback function used in wpa enterprise cipher operation when connect.
+  *        Free cipher context.
+  *
+  * @param ctx  Context pointer from esp_crypto_cipher_init_t callback function.
+  *
+  */
+typedef void * (*esp_crypto_cipher_deinit_t)(esp_crypto_cipher_t *ctx);
+
+/**
+  * @brief The SHA256 callback function when do WPS connect. 
+  *
+  * @param key  Key for HMAC operations.
+  * @param key_len  Length of the key in bytes.
+  * @param data  Pointers to the data area.
+  * @param data_len  Length of the data area.
+  * @param mac  Buffer for the hash (20 bytes).
+  *
+  */
+typedef void * (*esp_hmac_sha256_t)(const unsigned char *key, int key_len, const unsigned char *data,
+		                    int data_len, unsigned char *mac);
+
+/**
+  * @brief The SHA256 callback function when do WPS connect. 
+  *
+  * @param key  Key for HMAC operations.
+  * @param key_len  Length of the key in bytes.
+  * @param num_elem  Number of elements in the data vector.
+  * @param addr  Pointers to the data areas.
+  * @param len  Lengths of the data blocks.
+  * @param mac  Buffer for the hash (32 bytes).
+  *
+  */
+typedef void * (*esp_hmac_sha256_vector_t)(const unsigned char *key, int key_len, int num_elem,
+			                   const unsigned char *addr[], const int *len, unsigned char *mac);
+
+/**
+  * @brief The AES callback function when do STA connect.
+  *
+  * @param key  Key for PRF.
+  * @param key_len  Length of the key in bytes.
+  * @param label  A unique label for each purpose of the PRF.
+  * @param data  Extra data to bind into the key.
+  * @param data_len  Length of the data.
+  * @param buf  Buffer for the generated pseudo-random key.  
+  * @param buf_len  Number of bytes of key to generate.
+  *
+  */
+typedef void * (*esp_sha256_prf_t)(const unsigned char *key, int key_len, const char *label,
+	                           const unsigned char *data, int data_len, unsigned char *buf, int buf_len);
+
+/**
+  * @brief The SHA256 callback function when do WPS connect. 
+  *
+  * @param num_elem  Number of elements in the data vector.
+  * @param addr  Pointers to the data areas.
+  * @param len  Lengths of the data blocks.
+  * @param mac  Buffer for the hash.
+  *
+  */
+typedef int * (*esp_sha256_vector_t)(int num_elem, const unsigned char *addr[], const int *len,
+		                     unsigned char *mac);
+
+/**
+  * @brief The bignum calculate callback function used when do connect. 
+  *        In WPS process, it used to calculate public key and private key.
+  *
+  * @param base  Base integer (big endian byte array).
+  * @param base_len  Length of base integer in bytes.
+  * @param power  Power integer (big endian byte array).
+  * @param power_len  Length of power integer in bytes.
+  * @param modulus  Modulus integer (big endian byte array).
+  * @param modulus_len  Length of modulus integer in bytes.
+  * @param result  Buffer for the result.
+  * @param result_len  Result length (max buffer size on input, real len on output).
+  *
+  */
+typedef int * (*esp_crypto_mod_exp_t)(const unsigned char *base, int base_len,
+		                      const unsigned char *power, int power_len,
+		                      const unsigned char *modulus, int modulus_len,
+		                      unsigned char *result, unsigned int *result_len);
+/**
+  * @brief The crypto callback function structure used when do station security connect.
+  *        The structure can be set as software crypto or the crypto optimized by ESP32
+  *        hardware.
+  */
+typedef struct {
+    esp_aes_wrap_t aes_wrap;                         /**< station connect function used when send EAPOL frame */
+    esp_aes_unwrap_t aes_unwrap;                     /**< station connect function used when decrypt key data */
+    esp_hmac_sha256_vector_t hmac_sha256_vector;     /**< station connect function used when check MIC */
+    esp_sha256_prf_t sha256_prf;                     /**< station connect function used when check MIC */
+}wpa_crypto_funcs_t;
+
+/**
+  * @brief The crypto callback function structure used when do WPS process. The 
+  *        structure can be set as software crypto or the crypto optimized by ESP32
+  *        hardware.
+  */
+typedef struct{
+    esp_aes_128_encrypt_t aes_128_encrypt;          /**< function used to process message when do WPS */
+    esp_aes_128_decrypt_t aes_128_decrypt;          /**< function used to process message when do WPS */
+    esp_crypto_mod_exp_t crypto_mod_exp;            /**< function used to calculate public key and private key */
+    esp_hmac_sha256_t hmac_sha256;                  /**< function used to get attribute */
+    esp_hmac_sha256_vector_t hmac_sha256_vector;    /**< function used to process message when do WPS */
+    esp_sha256_vector_t sha256_vector;              /**< function used to process message when do WPS */
+}wps_crypto_funcs_t;
+
+/**
+  * @brief The crypto callback function structure used when do WPA enterprise connect.
+  *        The structure can be set as software crypto or the crypto optimized by ESP32
+  *        hardware.
+  */
+typedef struct {
+    esp_crypto_hash_init_t crypto_hash_init;                  /**< function used to initialize a crypto_hash structure when use TLSV1 */
+    esp_crypto_hash_update_t crypto_hash_update;              /**< function used to calculate hash data when use TLSV1 */
+    esp_crypto_hash_finish_t crypto_hash_finish;              /**< function used to finish the hash calculate when use TLSV1 */
+    esp_crypto_cipher_init_t crypto_cipher_init;              /**< function used to initialize a crypt_cipher structure when use TLSV1 */
+    esp_crypto_cipher_encrypt_t crypto_cipher_encrypt;        /**< function used to encrypt cipher when use TLSV1 */
+    esp_crypto_cipher_decrypt_t crypto_cipher_decrypt;        /**< function used to decrypt cipher when use TLSV1 */
+    esp_crypto_cipher_deinit_t crypto_cipher_deinit;          /**< function used to free context when use TLSV1 */
+    esp_sha256_vector_t sha256_vector;                        /**< function used to do X.509v3 certificate parsing and processing */
+    esp_crypto_mod_exp_t crypto_mod_exp;                      /**< function used to do key exchange when use TLSV1 */
+}wpa2_crypto_funcs_t;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_wifi_internal.h

@@ -0,0 +1,145 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+/*
+ * All the APIs declared here are internal only APIs, it can only be used by 
+ * espressif internal modules, such as SSC, LWIP, TCPIP adapter etc, espressif 
+ * customers are not recommended to use them.
+ *
+ * If someone really want to use specified APIs declared in here, please contact
+ * espressif AE/developer to make sure you know the limitations or risk of 
+ * the API, otherwise you may get unexpected behavior!!!
+ *
+ */
+
+
+#ifndef __ESP_WIFI_INTERNAL_H__
+#define __ESP_WIFI_INTERNAL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "rom/queue.h"
+#include "esp_err.h"
+#include "esp_wifi_types.h"
+#include "esp_event.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize Wi-Fi Driver
+ *     Alloc resource for WiFi driver, such as WiFi control structure, RX/TX buffer,
+ *     WiFi NVS structure among others.
+ *
+ * For the most part, you need not call this function directly. It gets called
+ * from esp_wifi_init().
+ *
+ * This function may be called, if you only need to initialize the Wi-Fi driver
+ * without having to use the network stack on top.
+ *
+ * @param  config provide WiFi init configuration
+ *
+ * @return
+ *    - ESP_OK: succeed
+ *    - ESP_ERR_WIFI_NO_MEM: out of memory
+ *    - others: refer to error code esp_err.h
+ */
+esp_err_t esp_wifi_init_internal(wifi_init_config_t *config);
+
+/**
+  * @brief  get whether the wifi driver is allowed to transmit data or not
+  *
+  * @return
+  *     - true  : upper layer should stop to transmit data to wifi driver
+  *     - false : upper layer can transmit data to wifi driver
+  */
+bool esp_wifi_internal_tx_is_stop(void);
+
+/**
+  * @brief  free the rx buffer which allocated by wifi driver
+  *
+  * @param  void* buffer: rx buffer pointer
+  */
+void esp_wifi_internal_free_rx_buffer(void* buffer);
+
+/**
+  * @brief  transmit the buffer via wifi driver
+  *
+  * @param  wifi_interface_t wifi_if : wifi interface id
+  * @param  void *buffer : the buffer to be tansmit
+  * @param  u16_t len : the length of buffer
+  *
+  * @return
+  *    - ERR_OK  : Successfully transmit the buffer to wifi driver
+  *    - ERR_MEM : Out of memory
+  *    - ERR_IF : WiFi driver error
+  *    - ERR_ARG : Invalid argument
+  */
+int esp_wifi_internal_tx(wifi_interface_t wifi_if, void *buffer, u16_t len);
+
+/**
+  * @brief     The WiFi RX callback function
+  *
+  *            Each time the WiFi need to forward the packets to high layer, the callback function will be called
+  */
+typedef esp_err_t (*wifi_rxcb_t)(void *buffer, uint16_t len, void *eb);
+
+/**
+  * @brief     Set the WiFi RX callback
+  *
+  * @attention 1. Currently we support only one RX callback for each interface
+  *
+  * @param     wifi_interface_t ifx : interface
+  * @param     wifi_rxcb_t fn : WiFi RX callback
+  *
+  * @return
+  *     - ESP_OK : succeed
+  *     - others : fail
+  */
+esp_err_t esp_wifi_internal_reg_rxcb(wifi_interface_t ifx, wifi_rxcb_t fn);
+
+/**
+  * @brief     Notify WIFI driver that the station got ip successfully
+  *
+  * @return
+  *     - ESP_OK : succeed
+  *     - others : fail
+  */
+esp_err_t esp_wifi_internal_set_sta_ip(void);
+
+
+esp_err_t esp_wifi_eibss_start(void);
+
+esp_err_t esp_wifi_eibss_stop(void);
+
+esp_err_t esp_wifi_eibss_set_bssid(const wifi_mac_t* bssid);
+
+esp_err_t esp_wifi_eibss_get_bssid(wifi_mac_t* bssid);
+
+esp_err_t esp_wifi_eibss_get_mac(wifi_mac_t* mac);
+
+esp_err_t esp_wifi_eibss_set_channel(int channel, wifi_second_chan_t width );
+
+esp_err_t esp_wifi_eibss_tx(void* buffer, int len, const wifi_mac_t* dst);
+
+typedef void (*esp_wifi_eibss_rxcb_t)(const void* buffer, int len, const wifi_mac_t* src);
+esp_err_t esp_wifi_eibss_reg_rxcb(esp_wifi_eibss_rxcb_t fn); 
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_WIFI_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_wifi_types.h

@@ -0,0 +1,291 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+
+#ifndef __ESP_WIFI_TYPES_H__
+#define __ESP_WIFI_TYPES_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "rom/queue.h"
+#include "esp_err.h"
+#include "esp_interface.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    WIFI_MODE_NULL = 0,  /**< null mode */
+    WIFI_MODE_STA,       /**< WiFi station mode */
+    WIFI_MODE_AP,        /**< WiFi soft-AP mode */
+    WIFI_MODE_APSTA,     /**< WiFi station + soft-AP mode */
+    WIFI_MODE_MAX
+} wifi_mode_t;
+
+typedef esp_interface_t wifi_interface_t;
+
+#define WIFI_IF_STA ESP_IF_WIFI_STA
+#define WIFI_IF_AP  ESP_IF_WIFI_AP
+
+typedef enum {
+    WIFI_COUNTRY_CN = 0, /**< country China, channel range [1, 14] */
+    WIFI_COUNTRY_JP,     /**< country Japan, channel range [1, 14] */
+    WIFI_COUNTRY_US,     /**< country USA, channel range [1, 11] */
+    WIFI_COUNTRY_EU,     /**< country Europe, channel range [1, 13] */
+    WIFI_COUNTRY_MAX
+} wifi_country_t;
+
+typedef enum {
+    WIFI_AUTH_OPEN = 0,         /**< authenticate mode : open */
+    WIFI_AUTH_WEP,              /**< authenticate mode : WEP */
+    WIFI_AUTH_WPA_PSK,          /**< authenticate mode : WPA_PSK */
+    WIFI_AUTH_WPA2_PSK,         /**< authenticate mode : WPA2_PSK */
+    WIFI_AUTH_WPA_WPA2_PSK,     /**< authenticate mode : WPA_WPA2_PSK */
+    WIFI_AUTH_WPA2_ENTERPRISE,  /**< authenticate mode : WPA2_ENTERPRISE */
+    WIFI_AUTH_MAX
+} wifi_auth_mode_t;
+
+enum {
+    WIFI_REASON_UNSPECIFIED              = 1,
+    WIFI_REASON_AUTH_EXPIRE              = 2,
+    WIFI_REASON_AUTH_LEAVE               = 3,
+    WIFI_REASON_ASSOC_EXPIRE             = 4,
+    WIFI_REASON_ASSOC_TOOMANY            = 5,
+    WIFI_REASON_NOT_AUTHED               = 6,
+    WIFI_REASON_NOT_ASSOCED              = 7,
+    WIFI_REASON_ASSOC_LEAVE              = 8,
+    WIFI_REASON_ASSOC_NOT_AUTHED         = 9,
+    WIFI_REASON_DISASSOC_PWRCAP_BAD      = 10,
+    WIFI_REASON_DISASSOC_SUPCHAN_BAD     = 11,
+    WIFI_REASON_IE_INVALID               = 13,
+    WIFI_REASON_MIC_FAILURE              = 14,
+    WIFI_REASON_4WAY_HANDSHAKE_TIMEOUT   = 15,
+    WIFI_REASON_GROUP_KEY_UPDATE_TIMEOUT = 16,
+    WIFI_REASON_IE_IN_4WAY_DIFFERS       = 17,
+    WIFI_REASON_GROUP_CIPHER_INVALID     = 18,
+    WIFI_REASON_PAIRWISE_CIPHER_INVALID  = 19,
+    WIFI_REASON_AKMP_INVALID             = 20,
+    WIFI_REASON_UNSUPP_RSN_IE_VERSION    = 21,
+    WIFI_REASON_INVALID_RSN_IE_CAP       = 22,
+    WIFI_REASON_802_1X_AUTH_FAILED       = 23,
+    WIFI_REASON_CIPHER_SUITE_REJECTED    = 24,
+
+    WIFI_REASON_BEACON_TIMEOUT           = 200,
+    WIFI_REASON_NO_AP_FOUND              = 201,
+    WIFI_REASON_AUTH_FAIL                = 202,
+    WIFI_REASON_ASSOC_FAIL               = 203,
+    WIFI_REASON_HANDSHAKE_TIMEOUT        = 204,
+};
+
+typedef enum {
+    WIFI_SECOND_CHAN_NONE = 0,  /**< the channel width is HT20 */
+    WIFI_SECOND_CHAN_ABOVE,     /**< the channel width is HT40 and the second channel is above the primary channel */
+    WIFI_SECOND_CHAN_BELOW,     /**< the channel width is HT40 and the second channel is below the primary channel */
+} wifi_second_chan_t;
+
+typedef enum {
+    WIFI_SCAN_TYPE_ACTIVE = 0,  /**< active scan */
+    WIFI_SCAN_TYPE_PASSIVE,     /**< passive scan */
+} wifi_scan_type_t;
+
+typedef struct {
+    uint32_t min;  /**< minimum active scan time per channel, units: millisecond */
+    uint32_t max;  /**< maximum active scan time per channel, units: millisecond, values above 1500ms may
+                                          cause station to disconnect from AP and are not recommended.  */
+} wifi_active_scan_time_t;
+
+typedef union {
+    wifi_active_scan_time_t active;  /**< active scan time per channel */
+    uint32_t passive;                /**< passive scan time per channel, units: millisecond, values above 1500ms may
+                                          cause station to disconnect from AP and are not recommended. */
+} wifi_scan_time_t;
+
+typedef struct {
+    uint8_t *ssid;               /**< SSID of AP */
+    uint8_t *bssid;              /**< MAC address of AP */
+    uint8_t channel;             /**< channel, scan the specific channel */
+    bool show_hidden;            /**< enable to scan AP whose SSID is hidden */
+    wifi_scan_type_t scan_type;  /**< scan type, active or passive */
+    wifi_scan_time_t scan_time;  /**< scan time per channel */
+} wifi_scan_config_t;
+
+typedef struct {
+    uint8_t bssid[6];                     /**< MAC address of AP */
+    uint8_t ssid[33];                     /**< SSID of AP */
+    uint8_t primary;                      /**< channel of AP */
+    wifi_second_chan_t second;            /**< second channel of AP */
+    int8_t  rssi;                         /**< signal strength of AP */
+    wifi_auth_mode_t authmode;            /**< authmode of AP */
+    uint32_t low_rate_enable:1;           /**< bit: 0 flag to identify if low rate is enabled or not */
+    uint32_t reserved:31;                 /**< bit: 1..31 reserved */
+} wifi_ap_record_t;
+
+typedef enum {
+    WIFI_PS_NONE,    /**< No power save */
+    WIFI_PS_MODEM,   /**< Modem power save */
+} wifi_ps_type_t;
+
+#define WIFI_PROTOCOL_11B         1
+#define WIFI_PROTOCOL_11G         2
+#define WIFI_PROTOCOL_11N         4
+#define WIFI_PROTOCOL_LR          8
+
+typedef enum {
+    WIFI_BW_HT20 = 1, /* Bandwidth is HT20 */
+    WIFI_BW_HT40,     /* Bandwidth is HT40 */
+} wifi_bandwidth_t;
+
+typedef struct {
+    uint8_t ssid[32];           /**< SSID of ESP32 soft-AP */
+    uint8_t password[64];       /**< Password of ESP32 soft-AP */
+    uint8_t ssid_len;           /**< Length of SSID. If softap_config.ssid_len==0, check the SSID until there is a termination character; otherwise, set the SSID length according to softap_config.ssid_len. */
+    uint8_t channel;            /**< Channel of ESP32 soft-AP */
+    wifi_auth_mode_t authmode;  /**< Auth mode of ESP32 soft-AP. Do not support AUTH_WEP in soft-AP mode */
+    uint8_t ssid_hidden;        /**< Broadcast SSID or not, default 0, broadcast the SSID */
+    uint8_t max_connection;     /**< Max number of stations allowed to connect in, default 4, max 4 */
+    uint16_t beacon_interval;   /**< Beacon interval, 100 ~ 60000 ms, default 100 ms */
+} wifi_ap_config_t;
+
+typedef struct {
+    uint8_t ssid[32];      /**< SSID of target AP*/
+    uint8_t password[64];  /**< password of target AP*/
+    bool bssid_set;        /**< whether set MAC address of target AP or not. Generally, station_config.bssid_set needs to be 0; and it needs to be 1 only when users need to check the MAC address of the AP.*/
+    uint8_t bssid[6];     /**< MAC address of target AP*/
+    uint8_t channel;       /**< channel of target AP. Set to 1~13 to scan starting from the specified channel before connecting to AP. If the channel of AP is unknown, set it to 0.*/
+} wifi_sta_config_t;
+
+typedef union {
+    wifi_ap_config_t  ap;  /**< configuration of AP */
+    wifi_sta_config_t sta; /**< configuration of STA */
+} wifi_config_t;
+
+typedef struct {
+    uint8_t mac[6];  /**< mac address of sta that associated with ESP32 soft-AP */
+} wifi_sta_info_t;
+
+#define ESP_WIFI_MAX_CONN_NUM  (10)       /**< max number of stations which can connect to ESP32 soft-AP */
+
+typedef struct {
+    wifi_sta_info_t sta[ESP_WIFI_MAX_CONN_NUM]; /**< station list */
+    int       num; /**< number of station that associated with ESP32 soft-AP */
+} wifi_sta_list_t;
+
+typedef enum {
+    WIFI_STORAGE_FLASH,  /**< all configuration will strore in both memory and flash */
+    WIFI_STORAGE_RAM,    /**< all configuration will only store in the memory */
+} wifi_storage_t;
+
+/**
+  * @brief     Vendor Information Element type
+  *
+  * Determines the frame type that the IE will be associated with.
+  */
+typedef enum {
+    WIFI_VND_IE_TYPE_BEACON,
+    WIFI_VND_IE_TYPE_PROBE_REQ,
+    WIFI_VND_IE_TYPE_PROBE_RESP,
+    WIFI_VND_IE_TYPE_ASSOC_REQ,
+    WIFI_VND_IE_TYPE_ASSOC_RESP,
+} wifi_vendor_ie_type_t;
+
+/**
+  * @brief     Vendor Information Element index
+  *
+  * Each IE type can have up to two associated vendor ID elements.
+  */
+typedef enum {
+    WIFI_VND_IE_ID_0,
+    WIFI_VND_IE_ID_1,
+} wifi_vendor_ie_id_t;
+
+#define WIFI_VENDOR_IE_ELEMENT_ID 0xDD
+
+/**
+ * @brief Vendor Information Element header
+ *
+ * The first bytes of the Information Element will match this header. Payload follows.
+ */
+typedef struct {
+    uint8_t element_id;      /**< Should be set to WIFI_VENDOR_IE_ELEMENT_ID (0xDD) */
+    uint8_t length;          /**< Length of all bytes in the element data following this field. Minimum 4. */
+    uint8_t vendor_oui[3];   /**< Vendor identifier (OUI). */
+    uint8_t vendor_oui_type; /**< Vendor-specific OUI type. */
+    uint8_t payload[0];      /**< Payload. Length is equal to value in 'length' field, minus 4. */
+} vendor_ie_data_t;
+
+typedef struct {
+    signed rssi:8;            /**< signal intensity of packet */
+    unsigned rate:5;          /**< data rate */
+    unsigned :1;              /**< reserve */
+    unsigned sig_mode:2;      /**< 0:is not 11n packet; 1:is 11n packet */
+    unsigned :16;             /**< reserve */
+    unsigned mcs:7;           /**< if is 11n packet, shows the modulation(range from 0 to 76) */
+    unsigned cwb:1;           /**< if is 11n packet, shows if is HT40 packet or not */
+    unsigned :16;             /**< reserve */
+    unsigned smoothing:1;     /**< reserve */
+    unsigned not_sounding:1;  /**< reserve */
+    unsigned :1;              /**< reserve */
+    unsigned aggregation:1;   /**< Aggregation */
+    unsigned stbc:2;          /**< STBC */
+    unsigned fec_coding:1;    /**< if is 11n packet, shows if is LDPC packet or not */
+    unsigned sgi:1;           /**< SGI */
+    unsigned noise_floor:8;   /**< noise floor */
+    unsigned ampdu_cnt:8;     /**< ampdu cnt */
+    unsigned channel:4;       /**< which channel this packet in */
+    unsigned :12;             /**< reserve */
+    unsigned timestamp:32;    /**< timestamp */
+    unsigned :32;             /**< reserve */
+    unsigned :32;             /**< reserve */
+    unsigned sig_len:12;      /**< It is really lenth of packet */
+    unsigned :12;             /**< reserve */
+    unsigned rx_state:8;      /**< rx state */
+} wifi_pkt_rx_ctrl_t;
+
+typedef struct {
+    wifi_pkt_rx_ctrl_t rx_ctrl;
+    uint8_t payload[0];       /**< ieee80211 packet buff, The length of payload is described by sig_len */
+} wifi_promiscuous_pkt_t;
+
+/**
+  * @brief     Promiscuous frame type
+  *
+  */
+typedef enum {
+    WIFI_PKT_MGMT,  /**< management type, receive packet buf is wifi_promiscuous_pkt_t */
+    WIFI_PKT_DATA,  /**< data type, receive packet buf is wifi_promiscuous_pkt_t */
+    WIFI_PKT_MISC,  /**< other type, such as MIMO etc, receive packet buf is wifi_promiscuous_pkt_t but the payload is NULL!!! */
+} wifi_promiscuous_pkt_type_t;
+
+
+#define WIFI_PROMIS_FILTER_MASK_ALL         (0xFFFFFFFF)  /**< filter all packets */
+#define WIFI_PROMIS_FILTER_MASK_MGMT        (1)           /**< filter the packets with type of WIFI_PKT_MGMT */
+#define WIFI_PROMIS_FILTER_MASK_DATA        (1<<1)        /**< filter the packets with type of WIFI_PKT_DATA */
+#define WIFI_PROMIS_FILTER_MASK_MISC        (1<<2)        /**< filter the packets with type of WIFI_PKT_MISC */
+#define WIFI_PROMIS_FILTER_MASK_DATA_MPDU   (1<<3)        /**< filter the MPDU which is a kind of WIFI_PKT_DATA */
+#define WIFI_PROMIS_FILTER_MASK_DATA_AMPDU  (1<<4)        /**< filter the AMPDU which is a kind of WIFI_PKT_DATA */
+
+typedef struct {
+    uint32_t filter_mask;
+} wifi_promiscuous_filter_t;
+
+typedef struct {
+    uint8_t mac[6];
+} wifi_mac_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_WIFI_TYPES_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_wpa2.h

@@ -0,0 +1,206 @@
+// Hardware crypto support Copyright 2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef ESP_WPA2_H
+#define ESP_WPA2_H
+
+#include "esp_err.h"
+#include "esp_wifi_crypto_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const wpa2_crypto_funcs_t g_wifi_default_wpa2_crypto_funcs;
+
+typedef struct {
+    const wpa2_crypto_funcs_t *crypto_funcs;
+}esp_wpa2_config_t;
+
+#define WPA2_CONFIG_INIT_DEFAULT() { \
+    .crypto_funcs = &g_wifi_default_wpa2_crypto_funcs \
+}
+
+/**
+  * @brief  Enable wpa2 enterprise authentication.
+  *
+  * @attention 1. wpa2 enterprise authentication can only be used when ESP32 station is enabled.
+  * @attention 2. wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
+  *
+  * @return
+  *    - ESP_ERR_WIFI_OK: succeed.
+  *    - ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
+  */
+esp_err_t esp_wifi_sta_wpa2_ent_enable(const esp_wpa2_config_t *config);
+
+/**
+  * @brief  Disable wpa2 enterprise authentication.
+  *
+  * @attention 1. wpa2 enterprise authentication can only be used when ESP32 station is enabled.
+  * @attention 2. wpa2 enterprise authentication can only support TLS, PEAP-MSCHAPv2 and TTLS-MSCHAPv2 method.
+  *
+  * @return
+  *    - ESP_ERR_WIFI_OK: succeed.
+  */
+esp_err_t esp_wifi_sta_wpa2_ent_disable(void);
+
+/**
+  * @brief  Set identity for PEAP/TTLS method.
+  *
+  * @attention The API only passes the parameter identity to the global pointer variable in wpa2 enterprise module.
+  *
+  * @param  identity: point to address where stores the identity;
+  * @param  len: length of identity, limited to 1~127
+  *
+  * @return
+  *    - ESP_ERR_WIFI_OK: succeed
+  *    - ESP_ERR_WIFI_ARG: fail(len <= 0 or len >= 128)
+  *    - ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
+  */
+esp_err_t esp_wifi_sta_wpa2_ent_set_identity(unsigned char *identity, int len);
+
+/**
+  * @brief  Clear identity for PEAP/TTLS method.
+  */
+void esp_wifi_sta_wpa2_ent_clear_identity(void);
+
+/**
+  * @brief  Set username for PEAP/TTLS method.
+  *
+  * @attention The API only passes the parameter username to the global pointer variable in wpa2 enterprise module.
+  *
+  * @param  username: point to address where stores the username;
+  * @param  len: length of username, limited to 1~127
+  *
+  * @return
+  *    - ESP_ERR_WIFI_OK: succeed
+  *    - ESP_ERR_WIFI_ARG: fail(len <= 0 or len >= 128)
+  *    - ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
+  */
+esp_err_t esp_wifi_sta_wpa2_ent_set_username(unsigned char *username, int len);
+
+/**
+  * @brief  Clear username for PEAP/TTLS method.
+  */
+void esp_wifi_sta_wpa2_ent_clear_username(void);
+
+/**
+  * @brief  Set password for PEAP/TTLS method..
+  *
+  * @attention The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
+  *
+  * @param  password: point to address where stores the password;
+  * @param  len: length of password(len > 0)
+  *
+  * @return
+  *    - ESP_ERR_WIFI_OK: succeed
+  *    - ESP_ERR_WIFI_ARG: fail(len <= 0)
+  *    - ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
+  */
+esp_err_t esp_wifi_sta_wpa2_ent_set_password(unsigned char *password, int len);
+
+/**
+  * @brief  Clear password for PEAP/TTLS method..
+  */
+void esp_wifi_sta_wpa2_ent_clear_password(void);
+
+/**
+  * @brief  Set new password for MSCHAPv2 method..
+  *
+  * @attention 1. The API only passes the parameter password to the global pointer variable in wpa2 enterprise module.
+  * @attention 2. The new password is used to substitute the old password when eap-mschapv2 failure request message with error code ERROR_PASSWD_EXPIRED is received.
+  *
+  * @param  password: point to address where stores the password;
+  * @param  len: length of password
+  *
+  * @return
+  *    - ESP_ERR_WIFI_OK: succeed
+  *    - ESP_ERR_WIFI_ARG: fail(len <= 0)
+  *    - ESP_ERR_WIFI_NO_MEM: fail(internal memory malloc fail)
+  */
+
+esp_err_t esp_wifi_sta_wpa2_ent_set_new_password(unsigned char *password, int len);
+
+/**
+  * @brief  Clear new password for MSCHAPv2 method..
+  */
+void esp_wifi_sta_wpa2_ent_clear_new_password(void);
+
+/**
+  * @brief  Set CA certificate for PEAP/TTLS method.
+  *
+  * @attention 1. The API only passes the parameter ca_cert to the global pointer variable in wpa2 enterprise module.
+  * @attention 2. The ca_cert should be zero terminated.
+  *
+  * @param  ca_cert: point to address where stores the CA certificate;
+  * @param  len: length of ca_cert
+  *
+  * @return
+  *    - ESP_ERR_WIFI_OK: succeed
+  */
+esp_err_t esp_wifi_sta_wpa2_ent_set_ca_cert(unsigned char *ca_cert, int len);
+
+/**
+  * @brief  Clear CA certificate for PEAP/TTLS method.
+  */
+void esp_wifi_sta_wpa2_ent_clear_ca_cert(void);
+
+/**
+  * @brief  Set client certificate and key.
+  *
+  * @attention 1. The API only passes the parameter client_cert, private_key and private_key_passwd to the global pointer variable in wpa2 enterprise module.
+  * @attention 2. The client_cert, private_key and private_key_passwd should be zero terminated.
+  *
+  * @param  client_cert: point to address where stores the client certificate;
+  * @param  client_cert_len: length of client certificate;
+  * @param  private_key: point to address where stores the private key;
+  * @param  private_key_len: length of private key, limited to 1~2048;
+  * @param  private_key_password: point to address where stores the private key password;
+  * @param  private_key_password_len: length of private key password;
+  *
+  * @return
+  *    - ESP_ERR_WIFI_OK: succeed
+  */
+esp_err_t esp_wifi_sta_wpa2_ent_set_cert_key(unsigned char *client_cert, int client_cert_len, unsigned char *private_key, int private_key_len, unsigned char *private_key_passwd, int private_key_passwd_len);
+
+/**
+  * @brief  Clear client certificate and key.
+  */
+void esp_wifi_sta_wpa2_ent_clear_cert_key(void);
+
+/**
+  * @brief  Set wpa2 enterprise certs time check(disable or not).
+  *
+  * @param  true: disable wpa2 enterprise certs time check
+  * @param  false: enable wpa2 enterprise certs time check
+  *
+  * @return
+  *    - ESP_OK: succeed
+  */
+esp_err_t esp_wifi_sta_wpa2_ent_set_disable_time_check(bool disable);
+
+/**
+  * @brief  Get wpa2 enterprise certs time check(disable or not).
+  *
+  * @param  disable: store disable value
+  *
+  * @return
+  *    - ESP_OK: succeed
+  */
+esp_err_t esp_wifi_sta_wpa2_ent_get_disable_time_check(bool *disable);
+
+#ifdef __cplusplus
+}
+#endif
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/esp_wps.h

@@ -0,0 +1,125 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef __ESP_WPS_H__
+#define __ESP_WPS_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_err.h"
+#include "esp_wifi_crypto_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup WiFi_APIs WiFi Related APIs
+  * @brief WiFi APIs
+  */
+
+/** @addtogroup WiFi_APIs
+  * @{
+  */
+
+/** \defgroup WPS_APIs  WPS APIs
+  * @brief ESP32 WPS APIs
+  *
+  * WPS can only be used when ESP32 station is enabled.
+  *
+  */
+
+/** @addtogroup WPS_APIs
+  * @{
+  */
+
+#define ESP_ERR_WIFI_REGISTRAR   (ESP_ERR_WIFI_BASE + 51)  /*!< WPS registrar is not supported */
+#define ESP_ERR_WIFI_WPS_TYPE    (ESP_ERR_WIFI_BASE + 52)  /*!< WPS type error */
+#define ESP_ERR_WIFI_WPS_SM      (ESP_ERR_WIFI_BASE + 53)  /*!< WPS state machine is not initialized */
+
+typedef enum wps_type {
+    WPS_TYPE_DISABLE = 0,
+    WPS_TYPE_PBC,
+    WPS_TYPE_PIN,
+    WPS_TYPE_MAX,
+} wps_type_t;
+
+extern const wps_crypto_funcs_t g_wifi_default_wps_crypto_funcs;
+
+typedef struct {
+    wps_type_t wps_type;
+    const wps_crypto_funcs_t *crypto_funcs;
+}esp_wps_config_t;
+
+#define WPS_CONFIG_INIT_DEFAULT(type) { \
+    .wps_type = type, \
+    .crypto_funcs = &g_wifi_default_wps_crypto_funcs, \
+}
+
+/**
+  * @brief     Enable Wi-Fi WPS function.
+  *
+  * @attention WPS can only be used when ESP32 station is enabled.
+  *
+  * @param     wps_type_t wps_type : WPS type, so far only WPS_TYPE_PBC and WPS_TYPE_PIN is supported
+  *
+  * @return    
+  *          - ESP_OK : succeed
+  *          - ESP_ERR_WIFI_WPS_TYPE : wps type is invalid
+  *          - ESP_ERR_WIFI_WPS_MODE : wifi is not in station mode or sniffer mode is on
+  *          - ESP_ERR_WIFI_FAIL : wps initialization fails
+  */
+esp_err_t esp_wifi_wps_enable(const esp_wps_config_t *config);
+
+/**
+  * @brief  Disable Wi-Fi WPS function and release resource it taken.
+  *
+  * @param  null
+  *
+  * @return    
+  *          - ESP_OK : succeed
+  *          - ESP_ERR_WIFI_WPS_MODE : wifi is not in station mode or sniffer mode is on
+  */
+esp_err_t esp_wifi_wps_disable(void);
+
+/**
+  * @brief     WPS starts to work.
+  *
+  * @attention WPS can only be used when ESP32 station is enabled.
+  *
+  * @param     timeout_ms : maximum blocking time before API return.
+  *          - 0 : non-blocking
+  *          - 1~120000 : blocking time (not supported in IDF v1.0)
+  *
+  * @return    
+  *          - ESP_OK : succeed
+  *          - ESP_ERR_WIFI_WPS_TYPE : wps type is invalid
+  *          - ESP_ERR_WIFI_WPS_MODE : wifi is not in station mode or sniffer mode is on
+  *          - ESP_ERR_WIFI_WPS_SM : wps state machine is not initialized
+  *          - ESP_ERR_WIFI_FAIL : wps initialization fails
+  */
+esp_err_t esp_wifi_wps_start(int timeout_ms);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ESP_WPS_H__ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/hwcrypto/aes.h

@@ -0,0 +1,263 @@
+/**
+ * \brief AES block cipher, ESP32 hardware accelerated version
+ * Based on mbedTLS FIPS-197 compliant version.
+ *
+ *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ *  Additions Copyright (C) 2016, Espressif Systems (Shanghai) PTE Ltd
+ *  SPDX-License-Identifier: Apache-2.0
+ *
+ *  Licensed under the Apache License, Version 2.0 (the "License"); you may
+ *  not use this file except in compliance with the License.
+ *  You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *  Unless required by applicable law or agreed to in writing, software
+ *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *  See the License for the specific language governing permissions and
+ *  limitations under the License.
+ *
+ *
+ */
+
+#ifndef ESP_AES_H
+#define ESP_AES_H
+
+#include "esp_types.h"
+#include "rom/aes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* padlock.c and aesni.c rely on these values! */
+#define ESP_AES_ENCRYPT     1
+#define ESP_AES_DECRYPT     0
+
+#define ERR_ESP_AES_INVALID_KEY_LENGTH                -0x0020  /**< Invalid key length. */
+#define ERR_ESP_AES_INVALID_INPUT_LENGTH              -0x0022  /**< Invalid data input length. */
+
+/**
+ * \brief          AES context structure
+ *
+ * \note           buf is able to hold 32 extra bytes, which can be used:
+ *                 - for alignment purposes if VIA padlock is used, and/or
+ *                 - to simplify key expansion in the 256-bit case by
+ *                 generating an extra round key
+ */
+typedef struct {
+    uint8_t key_bytes;
+    uint8_t key[32];
+} esp_aes_context;
+
+/**
+ * \brief Lock access to AES hardware unit
+ *
+ * AES hardware unit can only be used by one
+ * consumer at a time.
+ *
+ * esp_aes_xxx API calls automatically manage locking & unlocking of
+ * hardware, this function is only needed if you want to call
+ * ets_aes_xxx functions directly.
+ */
+void esp_aes_acquire_hardware( void );
+
+/**
+ * \brief Unlock access to AES hardware unit
+ *
+ * esp_aes_xxx API calls automatically manage locking & unlocking of
+ * hardware, this function is only needed if you want to call
+ * ets_aes_xxx functions directly.
+ */
+void esp_aes_release_hardware( void );
+
+/**
+ * \brief          Initialize AES context
+ *
+ * \param ctx      AES context to be initialized
+ */
+void esp_aes_init( esp_aes_context *ctx );
+
+/**
+ * \brief          Clear AES context
+ *
+ * \param ctx      AES context to be cleared
+ */
+void esp_aes_free( esp_aes_context *ctx );
+
+/**
+ * \brief          AES set key schedule (encryption or decryption)
+ *
+ * \param ctx      AES context to be initialized
+ * \param key      encryption key
+ * \param keybits  must be 128, 192 or 256
+ *
+ * \return         0 if successful, or ERR_AES_INVALID_KEY_LENGTH
+ */
+int esp_aes_setkey( esp_aes_context *ctx, const unsigned char *key, unsigned int keybits );
+
+/**
+ * \brief          AES-ECB block encryption/decryption
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param input    16-byte input block
+ * \param output   16-byte output block
+ *
+ * \return         0 if successful
+ */
+int esp_aes_crypt_ecb( esp_aes_context *ctx, int mode, const unsigned char input[16], unsigned char output[16] );
+
+/**
+ * \brief          AES-CBC buffer encryption/decryption
+ *                 Length should be a multiple of the block
+ *                 size (16 bytes)
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful, or ERR_AES_INVALID_INPUT_LENGTH
+ */
+int esp_aes_crypt_cbc( esp_aes_context *ctx,
+                       int mode,
+                       size_t length,
+                       unsigned char iv[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+
+
+/**
+ * \brief          AES-CFB128 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv_off   offset in IV (updated after use)
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int esp_aes_crypt_cfb128( esp_aes_context *ctx,
+                          int mode,
+                          size_t length,
+                          size_t *iv_off,
+                          unsigned char iv[16],
+                          const unsigned char *input,
+                          unsigned char *output );
+
+/**
+ * \brief          AES-CFB8 buffer encryption/decryption.
+ *
+ * Note: Due to the nature of CFB you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
+ *
+ * \note           Upon exit, the content of the IV is updated so that you can
+ *                 call the function same function again on the following
+ *                 block(s) of data and get the same result as if it was
+ *                 encrypted in one call. This allows a "streaming" usage.
+ *                 If on the other hand you need to retain the contents of the
+ *                 IV, you should either save it manually or use the cipher
+ *                 module instead.
+ *
+ * \param ctx      AES context
+ * \param mode     AES_ENCRYPT or AES_DECRYPT
+ * \param length   length of the input data
+ * \param iv       initialization vector (updated after use)
+ * \param input    buffer holding the input data
+ * \param output   buffer holding the output data
+ *
+ * \return         0 if successful
+ */
+int esp_aes_crypt_cfb8( esp_aes_context *ctx,
+                        int mode,
+                        size_t length,
+                        unsigned char iv[16],
+                        const unsigned char *input,
+                        unsigned char *output );
+
+/**
+ * \brief               AES-CTR buffer encryption/decryption
+ *
+ * Warning: You have to keep the maximum use of your counter in mind!
+ *
+ * Note: Due to the nature of CTR you should use the same key schedule for
+ * both encryption and decryption. So a context initialized with
+ * esp_aes_setkey_enc() for both AES_ENCRYPT and AES_DECRYPT.
+ *
+ * \param ctx           AES context
+ * \param length        The length of the data
+ * \param nc_off        The offset in the current stream_block (for resuming
+ *                      within current cipher stream). The offset pointer to
+ *                      should be 0 at the start of a stream.
+ * \param nonce_counter The 128-bit nonce and counter.
+ * \param stream_block  The saved stream-block for resuming. Is overwritten
+ *                      by the function.
+ * \param input         The input data stream
+ * \param output        The output data stream
+ *
+ * \return         0 if successful
+ */
+int esp_aes_crypt_ctr( esp_aes_context *ctx,
+                       size_t length,
+                       size_t *nc_off,
+                       unsigned char nonce_counter[16],
+                       unsigned char stream_block[16],
+                       const unsigned char *input,
+                       unsigned char *output );
+
+
+/**
+ * \brief           Internal AES block encryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see AES_ENCRYPT_ALT)
+ *
+ * \param ctx       AES context
+ * \param input     Plaintext block
+ * \param output    Output (ciphertext) block
+ */
+void esp_aes_encrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] );
+
+/**
+ * \brief           Internal AES block decryption function
+ *                  (Only exposed to allow overriding it,
+ *                  see AES_DECRYPT_ALT)
+ *
+ * \param ctx       AES context
+ * \param input     Ciphertext block
+ * \param output    Output (plaintext) block
+ */
+void esp_aes_decrypt( esp_aes_context *ctx, const unsigned char input[16], unsigned char output[16] );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* aes.h */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/hwcrypto/sha.h

@@ -0,0 +1,207 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ESP_SHA_H_
+#define _ESP_SHA_H_
+
+#include "rom/sha.h"
+#include "esp_types.h"
+
+/** @brief Low-level support functions for the hardware SHA engine
+ *
+ * @note If you're looking for a SHA API to use, try mbedtls component
+ * mbedtls/shaXX.h. That API supports hardware acceleration.
+ *
+ * The API in this header provides some building blocks for implementing a
+ * full SHA API such as the one in mbedtls, and also a basic SHA function esp_sha().
+ *
+ * Some technical details about the hardware SHA engine:
+ *
+ * - SHA accelerator engine calculates one digest at a time, per SHA
+ *   algorithm type. It initialises and maintains the digest state
+ *   internally. It is possible to read out an in-progress SHA digest
+ *   state, but it is not possible to restore a SHA digest state
+ *   into the engine.
+ *
+ * - The memory block SHA_TEXT_BASE is shared between all SHA digest
+ *   engines, so all engines must be idle before this memory block is
+ *   modified.
+ *
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Defined in rom/sha.h */
+typedef enum SHA_TYPE esp_sha_type;
+
+/** @brief Calculate SHA1 or SHA2 sum of some data, using hardware SHA engine
+ *
+ * @note For more versatile SHA calculations, where data doesn't need
+ * to be passed all at once, try the mbedTLS mbedtls/shaX.h APIs. The
+ * hardware-accelerated mbedTLS implementation is also faster when
+ * hashing large amounts of data.
+ *
+ * @note It is not necessary to lock any SHA hardware before calling
+ * this function, thread safety is managed internally.
+ *
+ * @note If a TLS connection is open then this function may block
+ * indefinitely waiting for a SHA engine to become available. Use the
+ * mbedTLS SHA API to avoid this problem.
+ *
+ * @param sha_type SHA algorithm to use.
+ *
+ * @param input Input data buffer.
+ *
+ * @param ilen Length of input data in bytes.
+ *
+ * @param output Buffer for output SHA digest. Output is 20 bytes for
+ * sha_type SHA1, 32 bytes for sha_type SHA2_256, 48 bytes for
+ * sha_type SHA2_384, 64 bytes for sha_type SHA2_512.
+ */
+void esp_sha(esp_sha_type sha_type, const unsigned char *input, size_t ilen, unsigned char *output);
+
+/* @brief Begin to execute a single SHA block operation
+ *
+ * @note This is a piece of a SHA algorithm, rather than an entire SHA
+ * algorithm.
+ *
+ * @note Call esp_sha_try_lock_engine() before calling this
+ * function. Do not call esp_sha_lock_memory_block() beforehand, this
+ * is done inside the function.
+ *
+ * @param sha_type SHA algorithm to use.
+ *
+ * @param data_block Pointer to block of data. Block size is
+ * determined by algorithm (SHA1/SHA2_256 = 64 bytes,
+ * SHA2_384/SHA2_512 = 128 bytes)
+ *
+ * @param is_first_block If this parameter is true, the SHA state will
+ * be initialised (with the initial state of the given SHA algorithm)
+ * before the block is calculated. If false, the existing state of the
+ * SHA engine will be used.
+ *
+ * @return As a performance optimisation, this function returns before
+ * the SHA block operation is complete. Both this function and
+ * esp_sha_read_state() will automatically wait for any previous
+ * operation to complete before they begin. If using the SHA registers
+ * directly in another way, call esp_sha_wait_idle() after calling this
+ * function but before accessing the SHA registers.
+ */
+void esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_first_block);
+
+/** @brief Read out the current state of the SHA digest loaded in the engine.
+ *
+ * @note This is a piece of a SHA algorithm, rather than an entire SHA algorithm.
+ *
+ * @note Call esp_sha_try_lock_engine() before calling this
+ * function. Do not call esp_sha_lock_memory_block() beforehand, this
+ * is done inside the function.
+ *
+ * If the SHA suffix padding block has been executed already, the
+ * value that is read is the SHA digest (in big endian
+ * format). Otherwise, the value that is read is an interim SHA state.
+ *
+ * @note If sha_type is SHA2_384, only 48 bytes of state will be read.
+ * This is enough for the final SHA2_384 digest, but if you want the
+ * interim SHA-384 state (to continue digesting) then pass SHA2_512 instead.
+ *
+ * @param sha_type SHA algorithm in use.
+ *
+ * @param state Pointer to a memory buffer to hold the SHA state. Size
+ * is 20 bytes (SHA1), 32 bytes (SHA2_256), 48 bytes (SHA2_384) or 64 bytes (SHA2_512).
+ *
+ */
+void esp_sha_read_digest_state(esp_sha_type sha_type, void *digest_state);
+
+/**
+ * @brief Obtain exclusive access to a particular SHA engine
+ *
+ * @param sha_type Type of SHA engine to use.
+ *
+ * Blocks until engine is available. Note: Can block indefinitely
+ * while a TLS connection is open, suggest using
+ * esp_sha_try_lock_engine() and failing over to software SHA.
+ */
+void esp_sha_lock_engine(esp_sha_type sha_type);
+
+/**
+ * @brief Try and obtain exclusive access to a particular SHA engine
+ *
+ * @param sha_type Type of SHA engine to use.
+ *
+ * @return Returns true if the SHA engine is locked for exclusive
+ * use. Call esp_sha_unlock_sha_engine() when done.  Returns false if
+ * the SHA engine is already in use, caller should use software SHA
+ * algorithm for this digest.
+ */
+bool esp_sha_try_lock_engine(esp_sha_type sha_type);
+
+/**
+ * @brief Unlock an engine previously locked with esp_sha_lock_engine() or esp_sha_try_lock_engine()
+ *
+ * @param sha_type Type of engine to release.
+ */
+void esp_sha_unlock_engine(esp_sha_type sha_type);
+
+/**
+ * @brief Acquire exclusive access to the SHA shared memory block at SHA_TEXT_BASE
+ *
+ * This memory block is shared across all the SHA algorithm types.
+ *
+ * Caller should have already locked a SHA engine before calling this function.
+ *
+ * Note that it is possible to obtain exclusive access to the memory block even
+ * while it is in use by the SHA engine. Caller should use esp_sha_wait_idle()
+ * to ensure the SHA engine is not reading from the memory block in hardware.
+ *
+ * @note You do not need to lock the memory block before calling esp_sha_block() or esp_sha_read_digest_state(), these functions handle memory block locking internally.
+ *
+ * Call esp_sha_unlock_memory_block() when done.
+ */
+void esp_sha_lock_memory_block(void);
+
+/**
+ * @brief Release exclusive access to the SHA register memory block at SHA_TEXT_BASE
+ *
+ * Caller should have already locked a SHA engine before calling this function.
+ *
+ * Call following esp_sha_lock_memory_block().
+ */
+void esp_sha_unlock_memory_block(void);
+
+/** @brief Wait for the SHA engine to finish any current operation
+ *
+ * @note This function does not ensure exclusive access to any SHA
+ * engine. Caller should use esp_sha_try_lock_engine() and
+ * esp_sha_lock_memory_block() as required.
+ *
+ * @note Functions declared in this header file wait for SHA engine
+ * completion automatically, so you don't need to use this API for
+ * these. However if accessing SHA registers directly, you will need
+ * to call this before accessing SHA registers if using the
+ * esp_sha_block() function.
+ *
+ * @note This function busy-waits, so wastes CPU resources.
+ * Best to delay calling until you are about to need it.
+ *
+ */
+void esp_sha_wait_idle(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/aes.h

@@ -0,0 +1,57 @@
+/*
+  ROM functions for hardware AES support.
+
+  It is not recommended to use these functions directly,
+  use the wrapper functions in hwcrypto/aes.h instead.
+
+ */
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_AES_H_
+#define _ROM_AES_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO, add comment for aes apis
+enum AES_BITS {
+    AES128,
+    AES192,
+    AES256
+};
+
+void ets_aes_enable(void);
+
+void ets_aes_disable(void);
+
+void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap,
+                        bool in_word_swap, bool in_byte_swap,
+                        bool out_word_swap, bool out_byte_swap);
+
+bool ets_aes_setkey_enc(const uint8_t *key, enum AES_BITS bits);
+
+bool ets_aes_setkey_dec(const uint8_t *key, enum AES_BITS bits);
+
+void ets_aes_crypt(const uint8_t input[16], uint8_t output[16]);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_AES_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/bigint.h

@@ -0,0 +1,62 @@
+/*
+  ROM functions for hardware bigint support.
+
+  It is not recommended to use these functions directly,
+  use the wrapper functions in hwcrypto/mpi.h instead.
+
+ */
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_BIGINT_H_
+#define _ROM_BIGINT_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: add comment here
+void ets_bigint_enable(void);
+
+void ets_bigint_disable(void);
+
+void ets_bigint_wait_finish(void);
+
+bool ets_bigint_mod_power_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
+                                  uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
+
+bool ets_bigint_mod_power_getz(uint32_t *z, uint32_t len);
+
+bool ets_bigint_mult_prepare(uint32_t *x, uint32_t *y, uint32_t len);
+
+bool ets_bigint_mult_getz(uint32_t *z, uint32_t len);
+
+bool ets_bigint_montgomery_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
+                                        uint32_t m_dash, uint32_t len, bool again);
+
+bool ets_bigint_montgomery_mult_getz(uint32_t *z, uint32_t len);
+
+bool ets_bigint_mod_mult_prepare(uint32_t *x, uint32_t *y, uint32_t *m,
+                                 uint32_t m_dash, uint32_t *rb, uint32_t len, bool again);
+
+bool ets_bigint_mod_mult_getz(uint32_t *m, uint32_t *z, uint32_t len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_BIGINT_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/cache.h

@@ -0,0 +1,194 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_CACHE_H_
+#define _ROM_CACHE_H_
+
+#include "soc/dport_access.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup uart_apis, uart configuration and communication related apis
+  * @brief uart apis
+  */
+
+/** @addtogroup uart_apis
+  * @{
+  */
+
+/**
+  * @brief Initialise cache mmu, mark all entries as invalid.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  int cpu_no : 0 for PRO cpu, 1 for APP cpu.
+  *
+  * @return None
+  */
+void mmu_init(int cpu_no);
+
+/**
+  * @brief Set Flash-Cache mmu mapping.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
+  *
+  * @param  int pod : process identifier. Range 0~7.
+  *
+  * @param  unsigned int vaddr : virtual address in CPU address space.
+  *                              Can be IRam0, IRam1, IRom0 and DRom0 memory address.
+  *                              Should be aligned by psize.
+  *
+  * @param  unsigned int paddr : physical address in Flash.
+  *                              Should be aligned by psize.
+  *
+  * @param  int psize : page size of flash, in kilobytes. Should be 64 here.
+  *
+  * @param  int num : pages to be set.
+  *
+  * @return unsigned int: error status
+  *                   0 : mmu set success
+  *                   1 : vaddr or paddr is not aligned
+  *                   2 : pid error
+  *                   3 : psize error
+  *                   4 : mmu table to be written is out of range
+  *                   5 : vaddr is out of range
+  */
+static inline unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num)
+{
+    extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr,  int psize, int num);
+
+    unsigned int ret;
+
+    DPORT_STALL_OTHER_CPU_START();
+    ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
+    DPORT_STALL_OTHER_CPU_END();
+
+    return ret;
+}
+
+/**
+  * @brief Set Ext-SRAM-Cache mmu mapping.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
+  *
+  * @param  int pod : process identifier. Range 0~7.
+  *
+  * @param  unsigned int vaddr : virtual address in CPU address space.
+  *                              Can be IRam0, IRam1, IRom0 and DRom0 memory address.
+  *                              Should be aligned by psize.
+  *
+  * @param  unsigned int paddr : physical address in Ext-SRAM.
+  *                              Should be aligned by psize.
+  *
+  * @param  int psize : page size of flash, in kilobytes. Should be 32 here.
+  *
+  * @param  int num : pages to be set.
+  *
+  * @return unsigned int: error status
+  *                   0 : mmu set success
+  *                   1 : vaddr or paddr is not aligned
+  *                   2 : pid error
+  *                   3 : psize error
+  *                   4 : mmu table to be written is out of range
+  *                   5 : vaddr is out of range
+  */
+static inline unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
+{
+    extern unsigned int cache_sram_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
+
+    unsigned int ret;
+
+    DPORT_STALL_OTHER_CPU_START();
+    ret = cache_sram_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
+    DPORT_STALL_OTHER_CPU_END();
+
+    return ret;
+}
+
+/**
+  * @brief Initialise cache access for the cpu.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  int cpu_no : 0 for PRO cpu, 1 for APP cpu.
+  *
+  * @return None
+  */
+static inline void IRAM_ATTR Cache_Read_Init(int cpu_no)
+{
+    extern void Cache_Read_Init_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Read_Init_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
+
+/**
+  * @brief Flush the cache value for the cpu.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  int cpu_no : 0 for PRO cpu, 1 for APP cpu.
+  *
+  * @return None
+  */
+static inline void IRAM_ATTR Cache_Flush(int cpu_no)
+{
+    extern void Cache_Flush_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Flush_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
+
+/**
+  * @brief Disable Cache access for the cpu.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  int cpu_no : 0 for PRO cpu, 1 for APP cpu.
+  *
+  * @return None
+  */
+static inline void IRAM_ATTR Cache_Read_Disable(int cpu_no)
+{
+    extern void Cache_Read_Disable_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Read_Disable_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
+
+/**
+  * @brief Enable Cache access for the cpu.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  int cpu_no : 0 for PRO cpu, 1 for APP cpu.
+  *
+  * @return None
+  */
+static inline void IRAM_ATTR Cache_Read_Enable(int cpu_no)
+{
+    extern void Cache_Read_Enable_rom(int cpu_no);
+    DPORT_STALL_OTHER_CPU_START();
+    Cache_Read_Enable_rom(cpu_no);
+    DPORT_STALL_OTHER_CPU_END();
+}
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_CACHE_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/crc.h

@@ -0,0 +1,127 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef ROM_CRC_H
+#define ROM_CRC_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup uart_apis, uart configuration and communication related apis
+  * @brief uart apis
+  */
+
+/** @addtogroup uart_apis
+  * @{
+  */
+
+
+/* Standard CRC8/16/32 algorithms. */
+// CRC-8        x8+x2+x1+1              0x07
+// CRC16-CCITT  x16+x12+x5+1   1021   ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS
+// CRC32:
+//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
+//If your buf is not continuous, you can use the first result to be the second parameter.
+
+/**
+  * @brief Crc32 value that is in little endian.
+  *
+  * @param  uint32_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @brief Crc32 value that is in big endian.
+  *
+  * @param  uint32_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @brief Crc16 value that is in little endian.
+  *
+  * @param  uint16_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @brief Crc16 value that is in big endian.
+  *
+  * @param  uint16_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @brief Crc8 value that is in little endian.
+  *
+  * @param  uint8_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @brief Crc8 value that is in big endian.
+  *
+  * @param  uint32_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/efuse.h

@@ -0,0 +1,117 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_EFUSE_H_
+#define _ROM_EFUSE_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup efuse_APIs efuse APIs
+  * @brief     ESP32 efuse read/write APIs
+  * @attention
+  *
+  */
+
+/** @addtogroup efuse_APIs
+  * @{
+  */
+
+/**
+  * @brief  Do a efuse read operation, to update the efuse value to efuse read registers.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void ets_efuse_read_op(void);
+
+/**
+  * @brief  Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again.
+  *
+  * @param  null
+  *
+  * @return null
+  */
+void ets_efuse_program_op(void);
+
+/**
+  * @brief  Read 8M Analog Clock value(8 bit) in efuse, the analog clock will not change with temperature.
+  *         It can be used to test the external xtal frequency, do not touch this efuse field.
+  *
+  * @param  null
+  *
+  * @return u32: 1 for 100KHZ, range is 0 to 255.
+  */
+uint32_t ets_efuse_get_8M_clock(void);
+
+/**
+  * @brief  Read spi flash pin configuration from Efuse
+  *
+  * @return
+  * - 0 for default SPI pins.
+  * - 1 for default HSPI pins.
+  * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
+  *   EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
+  *   WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
+  */
+uint32_t ets_efuse_get_spiconfig(void);
+
+#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
+#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
+
+#define EFUSE_SPICONFIG_RET_SPICLK_MASK         0x3f
+#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT        0
+#define EFUSE_SPICONFIG_RET_SPICLK(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPIQ_MASK           0x3f
+#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT          6
+#define EFUSE_SPICONFIG_RET_SPIQ(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPID_MASK           0x3f
+#define EFUSE_SPICONFIG_RET_SPID_SHIFT          12
+#define EFUSE_SPICONFIG_RET_SPID(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPICS0_MASK         0x3f
+#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT        18
+#define EFUSE_SPICONFIG_RET_SPICS0(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
+
+
+#define EFUSE_SPICONFIG_RET_SPIHD_MASK          0x3f
+#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT         24
+#define EFUSE_SPICONFIG_RET_SPIHD(ret)          (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
+
+/**
+  * @brief  A crc8 algorithm used in efuse check.
+  *
+  * @param  unsigned char const *p : Pointer to original data.
+  *
+  * @param  unsigned int len : Data length in byte.
+  *
+  * @return unsigned char: Crc value.
+  */
+unsigned char esp_crc8(unsigned char const *p, unsigned int len);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_EFUSE_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/ets_sys.h

@@ -0,0 +1,636 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_ETS_SYS_H_
+#define _ROM_ETS_SYS_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup ets_sys_apis, ets system related apis
+  * @brief ets system apis
+  */
+
+/** @addtogroup ets_sys_apis
+  * @{
+  */
+
+/************************************************************************
+  *                                NOTE
+  *   Many functions in this header files can't be run in FreeRTOS.
+  *   Please see the comment of the Functions.
+  *   There are also some functions that doesn't work on FreeRTOS
+  *   without listed in the header, such as:
+  *   xtos functions start with "_xtos_" in ld file.
+  *
+  ***********************************************************************
+  */
+
+/** \defgroup ets_apis, Espressif Task Scheduler related apis
+  * @brief ets apis
+  */
+
+/** @addtogroup ets_apis
+  * @{
+  */
+
+typedef enum {
+    ETS_OK     = 0, /**< return successful in ets*/
+    ETS_FAILED = 1  /**< return failed in ets*/
+} ETS_STATUS;
+
+typedef uint32_t ETSSignal;
+typedef uint32_t ETSParam;
+
+typedef struct ETSEventTag ETSEvent;    /**< Event transmit/receive in ets*/
+
+struct ETSEventTag {
+    ETSSignal sig;  /**< Event signal, in same task, different Event with different signal*/
+    ETSParam  par;  /**< Event parameter, sometimes without usage, then will be set as 0*/
+};
+
+typedef void (*ETSTask)(ETSEvent *e);       /**< Type of the Task processer*/
+typedef void (* ets_idle_cb_t)(void *arg);  /**< Type of the system idle callback*/
+
+/**
+  * @brief  Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it.
+  *
+  * @param  none
+  *
+  * @return none
+  */
+void ets_run(void);
+
+/**
+  * @brief  Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep.
+  *
+  * @param  ets_idle_cb_t func : The callback function.
+  *
+  * @param  void *arg : Argument of the callback.
+  *
+  * @return None
+  */
+void ets_set_idle_cb(ets_idle_cb_t func, void *arg);
+
+/**
+  * @brief  Init a task with processer, priority, queue to receive Event, queue length.
+  *
+  * @param  ETSTask task : The task processer.
+  *
+  * @param  uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task.
+  *
+  * @param  ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used.
+  *
+  * @param  uint8_t qlen : Queue length.
+  *
+  * @return None
+  */
+void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen);
+
+/**
+  * @brief  Post an event to an Task.
+  *
+  * @param  uint8_t prio : Priority of the Task.
+  *
+  * @param  ETSSignal sig : Event signal.
+  *
+  * @param  ETSParam  par : Event parameter
+  *
+  * @return ETS_OK     : post successful
+  * @return ETS_FAILED : post failed
+  */
+ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_boot_apis, Boot routing related apis
+  * @brief ets boot apis
+  */
+
+/** @addtogroup ets_apis
+  * @{
+  */
+
+extern const char *const exc_cause_table[40];   ///**< excption cause that defined by the core.*/
+
+/**
+  * @brief  Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
+  *         When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
+  *
+  * @param  uint32_t start : the PRO Entry code address value in uint32_t
+  *
+  * @return None
+  */
+void ets_set_user_start(uint32_t start);
+
+/**
+  * @brief  Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code.
+  *         When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run.
+  *
+  * @param  uint32_t callback : the Startup code address value in uint32_t
+  *
+  * @return None     : post successful
+  */
+void ets_set_startup_callback(uint32_t callback);
+
+/**
+  * @brief  Set App cpu Entry code, code can be called in PRO CPU.
+  *         When APP booting is completed, APP CPU will call the Entry code if not NULL.
+  *
+  * @param  uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D.
+  *
+  * @return None
+  */
+void ets_set_appcpu_boot_addr(uint32_t start);
+
+/**
+  * @brief  unpack the image in flash to iram and dram, no using cache.
+  *
+  * @param  uint32_t pos : Flash physical address.
+  *
+  * @param  uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
+  *
+  * @param  bool jump : Jump into the code in the function or not.
+  *
+  * @param  bool config : Config the flash when unpacking the image, config should be done only once.
+  *
+  * @return ETS_OK     : unpack successful
+  * @return ETS_FAILED : unpack failed
+  */
+ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config);
+
+/**
+  * @brief  unpack the image in flash to iram and dram, using cache, maybe decrypting.
+  *
+  * @param  uint32_t pos : Flash physical address.
+  *
+  * @param  uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
+  *
+  * @param  bool jump : Jump into the code in the function or not.
+  *
+  * @param  bool sb_need_check : Do security boot check or not.
+  *
+  * @param  bool config : Config the flash when unpacking the image, config should be done only once.
+  *
+  * @return ETS_OK     : unpack successful
+  * @return ETS_FAILED : unpack failed
+  */
+ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_printf_apis, ets_printf related apis used in ets
+  * @brief ets printf apis
+  */
+
+/** @addtogroup ets_printf_apis
+  * @{
+  */
+
+/**
+  * @brief  Printf the strings to uart or other devices, similar with printf, simple than printf.
+  *         Can not print float point data format, or longlong data format.
+  *         So we maybe only use this in ROM.
+  *
+  * @param  const char *fmt : See printf.
+  *
+  * @param  ... : See printf.
+  *
+  * @return int : the length printed to the output device.
+  */
+int ets_printf(const char *fmt, ...);
+
+/**
+  * @brief  Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
+  *         Can not print float point data format, or longlong data format
+  *
+  * @param  char c : char to output.
+  *
+  * @return None
+  */
+void ets_write_char_uart(char c);
+
+/**
+  * @brief  Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
+  *         To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
+  *
+  * @param  void (*)(char) p: Output function to install.
+  *
+  * @return None
+  */
+void ets_install_putc1(void (*p)(char c));
+
+/**
+  * @brief  Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
+  *         To install putc2, which is defaulted installed as NULL.
+  *
+  * @param  void (*)(char) p: Output function to install.
+  *
+  * @return None
+  */
+void ets_install_putc2(void (*p)(char c));
+
+/**
+  * @brief  Install putc1 as ets_write_char_uart.
+  *         In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_install_uart_printf(void);
+
+#define ETS_PRINTF(...) ets_printf(...)
+
+#define ETS_ASSERT(v) do { \
+    if (!(v)) {             \
+        ets_printf("%s %u \n", __FILE__, __LINE__); \
+        while (1) {};   \
+    }                   \
+} while (0);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_timer_apis, ets_timer related apis used in ets
+  * @brief ets timer apis
+  */
+
+/** @addtogroup ets_timer_apis
+  * @{
+  */
+typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
+
+typedef struct _ETSTIMER_ {
+    struct _ETSTIMER_    *timer_next;   /**< timer linker*/
+    uint32_t              timer_expire; /**< abstruct time when timer expire*/
+    uint32_t              timer_period; /**< timer period, 0 means timer is not periodic repeated*/
+    ETSTimerFunc         *timer_func;   /**< timer handler*/
+    void                 *timer_arg;    /**< timer handler argument*/
+} ETSTimer;
+
+/**
+  * @brief  Init ets timer, this timer range is 640 us to 429496 ms
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_timer_init(void);
+
+/**
+  * @brief  Arm an ets timer, this timer range is 640 us to 429496 ms.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @param  uint32_t tmout : Timer value in ms, range is 1 to 429496.
+  *
+  * @param  bool repeat : Timer is periodic repeated.
+  *
+  * @return None
+  */
+void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
+
+/**
+  * @brief  Arm an ets timer, this timer range is 640 us to 429496 ms.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @param  uint32_t tmout : Timer value in us, range is 1 to 429496729.
+  *
+  * @param  bool repeat : Timer is periodic repeated.
+  *
+  * @return None
+  */
+void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
+
+/**
+  * @brief  Disarm an ets timer.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @return None
+  */
+void ets_timer_disarm(ETSTimer *timer);
+
+/**
+  * @brief  Set timer callback and argument.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @param  ETSTimerFunc *pfunction : Timer callback.
+  *
+  * @param  void *parg : Timer callback argument.
+  *
+  * @return None
+  */
+void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
+
+/**
+  * @brief  Unset timer callback and argument to NULL.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @return None
+  */
+void ets_timer_done(ETSTimer *ptimer);
+
+/**
+  * @brief  CPU do while loop for some time.
+  *         In FreeRTOS task, please call FreeRTOS apis.
+  *
+  * @param  uint32_t us : Delay time in us.
+  *
+  * @return None
+  */
+void ets_delay_us(uint32_t us);
+
+/**
+  * @brief  Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
+  *         Call this function when CPU frequency is changed.
+  *
+  * @param  uint32_t ticks_per_us : CPU ticks per us.
+  *
+  * @return None
+  */
+void ets_update_cpu_frequency(uint32_t ticks_per_us);
+
+/**
+  * @brief  Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
+  *
+  * @note This function only sets the tick rate for the current CPU. It is located in ROM,
+  *       so the deep sleep stub can use it even if IRAM is not initialized yet.
+  *
+  * @param  uint32_t ticks_per_us : CPU ticks per us.
+  *
+  * @return None
+  */
+void ets_update_cpu_frequency_rom(uint32_t ticks_per_us);
+
+/**
+  * @brief  Get the real CPU ticks per us to the ets.
+  *         This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
+  *
+  * @param  None
+  *
+  * @return uint32_t : CPU ticks per us record in ets.
+  */
+uint32_t ets_get_cpu_frequency(void);
+
+/**
+  * @brief  Get xtal_freq/analog_8M*256 value calibrated in rtc module.
+  *
+  * @param  None
+  *
+  * @return uint32_t : xtal_freq/analog_8M*256.
+  */
+uint32_t ets_get_xtal_scale(void);
+
+/**
+  * @brief  Get xtal_freq value, If value not stored in RTC_STORE5, than store.
+  *
+  * @param  None
+  *
+  * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
+  *                         clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
+  *            else if analog_8M in efuse
+  *                         clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40;
+  *                    else clock = 26M.
+  */
+uint32_t ets_get_detected_xtal_freq(void);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_intr_apis, ets interrupt configure related apis
+  * @brief ets intr apis
+  */
+
+/** @addtogroup ets_intr_apis
+  * @{
+  */
+
+typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
+
+/**
+  * @brief  Attach a interrupt handler to a CPU interrupt number.
+  *         This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  int i : CPU interrupt number.
+  *
+  * @param  ets_isr_t func : Interrupt handler.
+  *
+  * @param  void *arg : argument of the handler.
+  *
+  * @return None
+  */
+void ets_isr_attach(int i, ets_isr_t func, void *arg);
+
+/**
+  * @brief  Mask the interrupts which show in mask bits.
+  *         This function equals to _xtos_ints_off(mask).
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  uint32_t mask : BIT(i) means mask CPU interrupt number i.
+  *
+  * @return None
+  */
+void ets_isr_mask(uint32_t mask);
+
+/**
+  * @brief  Unmask the interrupts which show in mask bits.
+  *         This function equals to _xtos_ints_on(mask).
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  uint32_t mask : BIT(i) means mask CPU interrupt number i.
+  *
+  * @return None
+  */
+void ets_isr_unmask(uint32_t unmask);
+
+/**
+  * @brief  Lock the interrupt to level 2.
+  *         This function direct set the CPU registers.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_intr_lock(void);
+
+/**
+  * @brief  Unlock the interrupt to level 0.
+  *         This function direct set the CPU registers.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_intr_unlock(void);
+
+/**
+  * @brief  Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt).
+  *         This function direct set the CPU registers.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_waiti0(void);
+
+/**
+  * @brief  Attach an CPU interrupt to a hardware source.
+  *         We have 4 steps to use an interrupt:
+  *         1.Attach hardware interrupt source to CPU.  intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
+  *         2.Set interrupt handler.                    xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
+  *         3.Enable interrupt for CPU.                 xt_ints_on(1 << ETS_WMAC_INUM);
+  *         4.Enable interrupt in the module.
+  *
+  * @param  int cpu_no : The CPU which the interrupt number belongs.
+  *
+  * @param  uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
+  *
+  * @param  uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
+  *
+  * @return None
+  */
+void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
+
+#define _ETSTR(v) # v
+#define _ETS_SET_INTLEVEL(intlevel)        ({ unsigned __tmp; \
+            __asm__ __volatile__(   "rsil   %0, " _ETSTR(intlevel) "\n" \
+                        : "=a" (__tmp) : : "memory" ); \
+            })
+
+#ifdef CONFIG_NONE_OS
+#define ETS_INTR_LOCK() \
+        ets_intr_lock()
+
+#define ETS_INTR_UNLOCK() \
+        ets_intr_unlock()
+
+#define ETS_ISR_ATTACH \
+        ets_isr_attach
+
+#define ETS_INTR_ENABLE(inum) \
+        ets_isr_unmask((1<<inum))
+
+#define ETS_INTR_DISABLE(inum) \
+        ets_isr_mask((1<<inum))
+
+#define ETS_WMAC_INTR_ATTACH(func, arg) \
+        ETS_ISR_ATTACH(ETS_WMAC_INUM, (func), (void *)(arg))
+
+#define ETS_TG0_T0_INTR_ATTACH(func, arg) \
+        ETS_ISR_ATTACH(ETS_TG0_T0_INUM, (func), (void *)(arg))
+
+#define ETS_GPIO_INTR_ATTACH(func, arg) \
+        ETS_ISR_ATTACH(ETS_GPIO_INUM, (func), (void *)(arg))
+
+#define ETS_UART0_INTR_ATTACH(func, arg) \
+        ETS_ISR_ATTACH(ETS_UART0_INUM, (func), (void *)(arg))
+
+#define ETS_WDT_INTR_ATTACH(func, arg) \
+        ETS_ISR_ATTACH(ETS_WDT_INUM, (func), (void *)(arg))
+
+#define ETS_SLC_INTR_ATTACH(func, arg) \
+        ETS_ISR_ATTACH(ETS_SLC_INUM, (func), (void *)(arg))
+
+#define ETS_BB_INTR_ENABLE() \
+        ETS_INTR_ENABLE(ETS_BB_INUM)
+
+#define ETS_BB_INTR_DISABLE() \
+        ETS_INTR_DISABLE(ETS_BB_INUM)
+
+#define ETS_UART0_INTR_ENABLE() \
+        ETS_INTR_ENABLE(ETS_UART0_INUM)
+
+#define ETS_UART0_INTR_DISABLE() \
+        ETS_INTR_DISABLE(ETS_UART0_INUM)
+
+#define ETS_GPIO_INTR_ENABLE() \
+        ETS_INTR_ENABLE(ETS_GPIO_INUM)
+
+#define ETS_GPIO_INTR_DISABLE() \
+        ETS_INTR_DISABLE(ETS_GPIO_INUM)
+
+#define ETS_WDT_INTR_ENABLE() \
+        ETS_INTR_ENABLE(ETS_WDT_INUM)
+
+#define ETS_WDT_INTR_DISABLE() \
+        ETS_INTR_DISABLE(ETS_WDT_INUM)
+
+#define ETS_TG0_T0_INTR_ENABLE() \
+        ETS_INTR_ENABLE(ETS_TG0_T0_INUM)
+
+#define ETS_TG0_T0_INTR_DISABLE() \
+        ETS_INTR_DISABLE(ETS_TG0_T0_INUM)
+
+#define ETS_SLC_INTR_ENABLE() \
+        ETS_INTR_ENABLE(ETS_SLC_INUM)
+
+#define ETS_SLC_INTR_DISABLE() \
+        ETS_INTR_DISABLE(ETS_SLC_INUM)
+#endif
+
+/**
+  * @}
+  */
+
+#ifndef MAC2STR
+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
+#endif
+
+#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
+
+typedef enum {
+    OK = 0,
+    FAIL,
+    PENDING,
+    BUSY,
+    CANCEL,
+} STATUS;
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_ETS_SYS_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/gpio.h

@@ -0,0 +1,300 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_GPIO_H_
+#define _ROM_GPIO_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "esp_attr.h"
+#include "soc/gpio_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup gpio_apis, uart configuration and communication related apis
+  * @brief gpio apis
+  */
+
+/** @addtogroup gpio_apis
+  * @{
+  */
+
+#define GPIO_REG_READ(reg)              READ_PERI_REG(reg)
+#define GPIO_REG_WRITE(reg, val)        WRITE_PERI_REG(reg, val)
+#define GPIO_PIN_COUNT                  40
+#define GPIO_ID_PIN0                    0
+#define GPIO_ID_PIN(n)                  (GPIO_ID_PIN0+(n))
+#define GPIO_PIN_ADDR(i)                (GPIO_PIN0_REG + i*4)
+
+#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
+    ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
+
+#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
+
+typedef enum {
+    GPIO_PIN_INTR_DISABLE = 0,
+    GPIO_PIN_INTR_POSEDGE = 1,
+    GPIO_PIN_INTR_NEGEDGE = 2,
+    GPIO_PIN_INTR_ANYEDGE = 3,
+    GPIO_PIN_INTR_LOLEVEL = 4,
+    GPIO_PIN_INTR_HILEVEL = 5
+} GPIO_INT_TYPE;
+
+#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
+        ((gpio_no < 32) ? gpio_output_set(bit_value<<gpio_no, (bit_value ? 0 : 1)<<gpio_no, 1<<gpio_no,0) : \
+                         gpio_output_set_high(bit_value<<(gpio_no - 32), (bit_value ? 0 : 1)<<(gpio_no - 32), 1<<(gpio_no -32),0))
+#define GPIO_DIS_OUTPUT(gpio_no)    ((gpio_no < 32) ? gpio_output_set(0,0,0, 1<<gpio_no) : gpio_output_set_high(0,0,0, 1<<gpio_no))
+#define GPIO_INPUT_GET(gpio_no)     ((gpio_no < 32)? ((gpio_input_get()>>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0))
+
+/* GPIO interrupt handler, registered through gpio_intr_handler_register */
+typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg);
+
+/**
+  * @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet
+  *        to initialize "output enables" and pin configurations for each gpio pin.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void gpio_init(void);
+
+/**
+  * @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
+  *         There is no particular ordering guaranteed; so if the order of writes is significant,
+  *         calling code should divide a single call into multiple calls.
+  *
+  * @param  uint32_t set_mask : the gpios that need high level.
+  *
+  * @param  uint32_t clear_mask : the gpios that need low level.
+  *
+  * @param  uint32_t enable_mask : the gpios that need be changed.
+  *
+  * @param  uint32_t disable_mask : the gpios that need diable output.
+  *
+  * @return None
+  */
+void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
+
+/**
+  * @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
+  *         There is no particular ordering guaranteed; so if the order of writes is significant,
+  *         calling code should divide a single call into multiple calls.
+  *
+  * @param  uint32_t set_mask : the gpios that need high level.
+  *
+  * @param  uint32_t clear_mask : the gpios that need low level.
+  *
+  * @param  uint32_t enable_mask : the gpios that need be changed.
+  *
+  * @param  uint32_t disable_mask : the gpios that need diable output.
+  *
+  * @return None
+  */
+void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
+
+/**
+  * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
+  *
+  * @param None
+  *
+  * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
+  */
+uint32_t gpio_input_get(void);
+
+/**
+  * @brief Sample the value of GPIO input pins(32-39) and returns a bitmask.
+  *
+  * @param None
+  *
+  * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32.
+  */
+uint32_t gpio_input_get_high(void);
+
+/**
+  * @brief Register an application-specific interrupt handler for GPIO pin interrupts.
+  *        Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack.
+  *        Please do not call this function in SDK.
+  *
+  * @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler
+  *
+  * @param void *arg : gpio application-specific interrupt handler argument.
+  *
+  * @return None
+  */
+void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg);
+
+/**
+  * @brief Get gpio interrupts which happens but not processed.
+  *        Please do not call this function in SDK.
+  *
+  * @param None
+  *
+  * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0.
+  */
+uint32_t gpio_intr_pending(void);
+
+/**
+  * @brief Get gpio interrupts which happens but not processed.
+  *        Please do not call this function in SDK.
+  *
+  * @param None
+  *
+  * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32.
+  */
+uint32_t gpio_intr_pending_high(void);
+
+/**
+  * @brief Ack gpio interrupts to process pending interrupts.
+  *        Please do not call this function in SDK.
+  *
+  * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0.
+  *
+  * @return None
+  */
+void gpio_intr_ack(uint32_t ack_mask);
+
+/**
+  * @brief Ack gpio interrupts to process pending interrupts.
+  *        Please do not call this function in SDK.
+  *
+  * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32.
+  *
+  * @return None
+  */
+void gpio_intr_ack_high(uint32_t ack_mask);
+
+/**
+  * @brief Set GPIO to wakeup the ESP32.
+  *        Please do not call this function in SDK.
+  *
+  * @param uint32_t i: gpio number.
+  *
+  * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
+  *
+  * @return None
+  */
+void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
+
+/**
+  * @brief disable GPIOs to wakeup the ESP32.
+  *        Please do not call this function in SDK.
+  *
+  * @param None
+  *
+  * @return None
+  */
+void gpio_pin_wakeup_disable(void);
+
+/**
+  * @brief set gpio input to a signal, one gpio can input to several signals.
+  *
+  * @param uint32_t gpio : gpio number, 0~0x27
+  *                        gpio == 0x30, input 0 to signal
+  *                        gpio == 0x34, ???
+  *                        gpio == 0x38, input 1 to signal
+  *
+  * @param uint32_t signal_idx : signal index.
+  *
+  * @param bool inv : the signal is inv or not
+  *
+  * @return None
+  */
+void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
+
+/**
+  * @brief set signal output to gpio, one signal can output to several gpios.
+  *
+  * @param uint32_t gpio : gpio number, 0~0x27
+  *
+  * @param uint32_t signal_idx : signal index.
+  *                        signal_idx == 0x100, cancel output put to the gpio
+  *
+  * @param bool out_inv : the signal output is inv or not
+  *
+  * @param bool oen_inv : the signal output enable is inv or not
+  *
+  * @return None
+  */
+void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
+
+/**
+  * @brief Select pad as a gpio function from IOMUX.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x27
+  *
+  * @return None
+  */
+void gpio_pad_select_gpio(uint8_t gpio_num);
+
+/**
+  * @brief Set pad driver capability.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x27
+  *
+  * @param uint8_t drv : 0-3
+  *
+  * @return None
+  */
+void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv);
+
+/**
+  * @brief Pull up the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x27
+  *
+  * @return None
+  */
+void gpio_pad_pullup(uint8_t gpio_num);
+
+/**
+  * @brief Pull down the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x27
+  *
+  * @return None
+  */
+void gpio_pad_pulldown(uint8_t gpio_num);
+
+/**
+  * @brief Unhold the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x27
+  *
+  * @return None
+  */
+void gpio_pad_unhold(uint8_t gpio_num);
+
+/**
+  * @brief Hold the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x27
+  *
+  * @return None
+  */
+void gpio_pad_hold(uint8_t gpio_num);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_GPIO_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/libc_stubs.h

@@ -0,0 +1,89 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_LIBC_STUBS_H_
+#define _ROM_LIBC_STUBS_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdarg.h>
+#include <reent.h>
+#include <errno.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* 
+ESP32 ROM code contains implementations of some of C library functions.
+Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
+implementation defined in the following struct.
+
+The table itself, by default, is not allocated in RAM. There are two pointers, `syscall_table_ptr_pro` and
+`syscall_table_ptr_app`, which can be set to point to the locations of syscall tables of CPU 0 (aka PRO CPU)
+and CPU 1 (aka APP CPU). Location of these pointers in .bss segment of ROM code is defined in linker script.
+
+So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
+application must allocate syscall table structure for each CPU being used, and populate it with pointers
+to actual implementations of corresponding syscalls.
+*/
+
+struct syscall_stub_table 
+{
+    struct _reent* (*__getreent)(void);
+    void* (*_malloc_r)(struct _reent *r, size_t);
+    void (*_free_r)(struct _reent *r, void*);
+    void* (*_realloc_r)(struct _reent *r, void*, size_t);
+    void* (*_calloc_r)(struct _reent *r, size_t, size_t);
+    void (*_abort)(void);
+    int (*_system_r)(struct _reent *r, const char*);
+    int (*_rename_r)(struct _reent *r, const char*, const char*);
+    clock_t (*_times_r)(struct _reent *r, struct tms *);
+    int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
+    void (*_raise_r)(struct _reent *r);
+    int (*_unlink_r)(struct _reent *r, const char*);
+    int (*_link_r)(struct _reent *r, const char*, const char*);
+    int (*_stat_r)(struct _reent *r, const char*, struct stat *);
+    int (*_fstat_r)(struct _reent *r, int, struct stat *);
+    void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
+    int (*_getpid_r)(struct _reent *r);
+    int (*_kill_r)(struct _reent *r, int, int);
+    void (*_exit_r)(struct _reent *r, int);
+    int (*_close_r)(struct _reent *r, int);
+    int (*_open_r)(struct _reent *r, const char *, int, int);
+    int (*_write_r)(struct _reent *r, int, const void *, int);
+    int (*_lseek_r)(struct _reent *r, int, int, int);
+    int (*_read_r)(struct _reent *r, int, void *, int);
+    void (*_lock_init)(_lock_t *lock);
+    void (*_lock_init_recursive)(_lock_t *lock);
+    void (*_lock_close)(_lock_t *lock);
+    void (*_lock_close_recursive)(_lock_t *lock);
+    void (*_lock_acquire)(_lock_t *lock);
+    void (*_lock_acquire_recursive)(_lock_t *lock);
+    int (*_lock_try_acquire)(_lock_t *lock);
+    int (*_lock_try_acquire_recursive)(_lock_t *lock);
+    void (*_lock_release)(_lock_t *lock);
+    void (*_lock_release_recursive)(_lock_t *lock);
+    int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, _CONST char *, size_t len), va_list * ap);
+    int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
+};
+
+extern struct syscall_stub_table* syscall_table_ptr_pro;
+extern struct syscall_stub_table* syscall_table_ptr_app;
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif /* _ROM_LIBC_STUBS_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/lldesc.h

@@ -0,0 +1,176 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_LLDESC_H_
+#define _ROM_LLDESC_H_
+
+#include <stdint.h>
+
+#include "queue.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LLDESC_TX_MBLK_SIZE                 268 /* */
+#define LLDESC_RX_SMBLK_SIZE                64  /* small block size, for small mgmt frame */
+#define LLDESC_RX_MBLK_SIZE                 524 /* rx is large sinec we want to contain mgmt frame in one block*/
+#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE    64  /* it is a small buffer which is a cycle link*/
+#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE      256 /*for ampdu entry*/
+#ifdef ESP_MAC_5
+#define LLDESC_TX_MBLK_NUM                  116  /* 64K / 256 */
+#define LLDESC_RX_MBLK_NUM                  82 /* 64K / 512 MAX 172*/
+#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM     4
+#define LLDESC_RX_AMPDU_LEN_MLBK_NUM       12
+#else
+#ifdef SBUF_RXTX
+#define LLDESC_TX_MBLK_NUM_MAX    (2 * 48) /* 23K / 260 - 8 */
+#define LLDESC_RX_MBLK_NUM_MAX    (2 * 48) /* 23K / 524 */
+#define LLDESC_TX_MBLK_NUM_MIN    (2 * 16) /* 23K / 260 - 8 */
+#define LLDESC_RX_MBLK_NUM_MIN    (2 * 16) /* 23K / 524 */
+#endif
+#define LLDESC_TX_MBLK_NUM      10      //(2 * 32) /* 23K / 260 - 8 */
+
+#ifdef IEEE80211_RX_AMPDU
+#define LLDESC_RX_MBLK_NUM      30
+#else
+#define LLDESC_RX_MBLK_NUM      10
+#endif /*IEEE80211_RX_AMPDU*/
+
+#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM  4
+#define LLDESC_RX_AMPDU_LEN_MLBK_NUM    8
+#endif /* !ESP_MAC_5 */
+/*
+ *  SLC2 DMA Desc struct, aka lldesc_t
+ * 
+ * -------------------------------------------------------------- 
+ * | own | EoF | sub_sof | 5'b0   | length [11:0] | size [11:0] |
+ * --------------------------------------------------------------
+ * |            buf_ptr [31:0]                                  |
+ * --------------------------------------------------------------
+ * |            next_desc_ptr [31:0]                            |
+ * --------------------------------------------------------------
+ */
+
+/* this bitfield is start from the LSB!!! */
+typedef struct lldesc_s {
+    volatile uint32_t size  :12,
+                        length:12,
+                        offset: 5, /* h/w reserved 5bit, s/w use it as offset in buffer */
+                        sosf  : 1, /* start of sub-frame */
+                        eof   : 1, /* end of frame */
+                        owner : 1; /* hw or sw */
+    volatile uint8_t *buf;       /* point to buffer data */
+    union{
+        volatile uint32_t empty;
+        STAILQ_ENTRY(lldesc_s) qe;  /* pointing to the next desc */
+    };
+} lldesc_t;
+
+typedef struct tx_ampdu_entry_s{
+    uint32_t sub_len  :12,
+              dili_num : 7,
+                       : 1,
+              null_byte: 2,
+              data     : 1,
+              enc      : 1,
+              seq      : 8;
+} tx_ampdu_entry_t;
+
+typedef struct lldesc_chain_s {
+    lldesc_t *head;
+    lldesc_t *tail;
+} lldesc_chain_t;
+
+#ifdef SBUF_RXTX
+enum sbuf_mask_s  {
+    SBUF_MOVE_NO = 0,
+    SBUF_MOVE_TX2RX,
+    SBUF_MOVE_RX2TX,
+} ;
+
+#define SBUF_MOVE_STEP 8
+#endif
+#define LLDESC_SIZE  sizeof(struct lldesc_s)
+
+/* SLC Descriptor  */
+#define LLDESC_OWNER_MASK                  0x80000000
+#define LLDESC_OWNER_SHIFT                         31
+#define LLDESC_SW_OWNED                             0
+#define LLDESC_HW_OWNED                             1
+
+#define LLDESC_EOF_MASK                    0x40000000
+#define LLDESC_EOF_SHIFT                           30
+
+#define LLDESC_SOSF_MASK                   0x20000000
+#define LLDESC_SOSF_SHIFT                          29
+
+#define LLDESC_LENGTH_MASK                 0x00fff000
+#define LLDESC_LENGTH_SHIFT                        12
+
+#define LLDESC_SIZE_MASK                   0x00000fff
+#define LLDESC_SIZE_SHIFT                           0
+
+#define LLDESC_ADDR_MASK                    0x000fffff
+
+void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t * mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner,
+                          lldesc_t **head,
+#ifdef TO_HOST_RESTART
+                          lldesc_t ** one_before_tail,
+#endif
+                          lldesc_t **tail);
+
+lldesc_t *lldesc_num2link(lldesc_t * head, uint16_t nblks);
+
+lldesc_t *lldesc_set_owner(lldesc_t * head, uint16_t nblks, uint8_t owner);
+
+static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
+{
+    lldesc_t *ds = head;
+    uint32_t len = 0;
+    
+    while (ds) {
+        len += ds->length;
+        ds = STAILQ_NEXT(ds, qe);
+    }
+    
+    return len;
+}
+
+static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
+{
+    ds->owner  = owner;
+    ds->eof    = eof;
+    ds->sosf   = sosf;
+    ds->length = len;
+}
+
+#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len)        do { \
+        (_desc)->owner  = (_owner); \
+        (_desc)->eof    = (_eof);   \
+        (_desc)->sosf   = (_sosf);  \
+        (_desc)->length = (_len);   \
+} while(0)
+
+#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
+
+#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
+
+#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_LLDESC_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/md5_hash.h

@@ -0,0 +1,38 @@
+/*
+ * MD5 internal definitions
+ * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Alternatively, this software may be distributed under the terms of BSD
+ * license.
+ *
+ * See README and COPYING for more details.
+ */
+
+#ifndef _ROM_MD5_HASH_H_
+#define _ROM_MD5_HASH_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct MD5Context {
+	uint32_t buf[4];
+	uint32_t bits[2];
+	uint8_t in[64];
+};
+
+void MD5Init(struct MD5Context *context);
+void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
+void MD5Final(unsigned char digest[16], struct MD5Context *context);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_MD5_HASH_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/miniz.h

@@ -0,0 +1,777 @@
+#ifndef MINIZ_HEADER_INCLUDED
+#define MINIZ_HEADER_INCLUDED
+
+#include <stdlib.h>
+
+// Defines to completely disable specific portions of miniz.c:
+// If all macros here are defined the only functionality remaining will be CRC-32, adler-32, tinfl, and tdefl.
+
+// Define MINIZ_NO_STDIO to disable all usage and any functions which rely on stdio for file I/O.
+#define MINIZ_NO_STDIO
+
+// If MINIZ_NO_TIME is specified then the ZIP archive functions will not be able to get the current time, or
+// get/set file times, and the C run-time funcs that get/set times won't be called.
+// The current downside is the times written to your archives will be from 1979.
+#define MINIZ_NO_TIME
+
+// Define MINIZ_NO_ARCHIVE_APIS to disable all ZIP archive API's.
+#define MINIZ_NO_ARCHIVE_APIS
+
+// Define MINIZ_NO_ARCHIVE_APIS to disable all writing related ZIP archive API's.
+#define MINIZ_NO_ARCHIVE_WRITING_APIS
+
+// Define MINIZ_NO_ZLIB_APIS to remove all ZLIB-style compression/decompression API's.
+#define MINIZ_NO_ZLIB_APIS
+
+// Define MINIZ_NO_ZLIB_COMPATIBLE_NAME to disable zlib names, to prevent conflicts against stock zlib.
+#define MINIZ_NO_ZLIB_COMPATIBLE_NAMES
+
+// Define MINIZ_NO_MALLOC to disable all calls to malloc, free, and realloc.
+// Note if MINIZ_NO_MALLOC is defined then the user must always provide custom user alloc/free/realloc
+// callbacks to the zlib and archive API's, and a few stand-alone helper API's which don't provide custom user
+// functions (such as tdefl_compress_mem_to_heap() and tinfl_decompress_mem_to_heap()) won't work.
+#define MINIZ_NO_MALLOC
+
+#if defined(__TINYC__) && (defined(__linux) || defined(__linux__))
+  // TODO: Work around "error: include file 'sys\utime.h' when compiling with tcc on Linux
+  #define MINIZ_NO_TIME
+#endif
+
+#if !defined(MINIZ_NO_TIME) && !defined(MINIZ_NO_ARCHIVE_APIS)
+  #include <time.h>
+#endif
+
+//Hardcoded options for Xtensa - JD
+#define MINIZ_X86_OR_X64_CPU 0
+#define MINIZ_LITTLE_ENDIAN 1
+#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 0
+#define MINIZ_HAS_64BIT_REGISTERS 0
+#define TINFL_USE_64BIT_BITBUF 0
+
+
+#if defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i486) || defined(i386) || defined(__ia64__) || defined(__x86_64__)
+// MINIZ_X86_OR_X64_CPU is only used to help set the below macros.
+#define MINIZ_X86_OR_X64_CPU 1
+#endif
+
+#if (__BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) || MINIZ_X86_OR_X64_CPU
+// Set MINIZ_LITTLE_ENDIAN to 1 if the processor is little endian.
+#define MINIZ_LITTLE_ENDIAN 1
+#endif
+
+#if MINIZ_X86_OR_X64_CPU
+// Set MINIZ_USE_UNALIGNED_LOADS_AND_STORES to 1 on CPU's that permit efficient integer loads and stores from unaligned addresses.
+#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 1
+#endif
+
+#if defined(_M_X64) || defined(_WIN64) || defined(__MINGW64__) || defined(_LP64) || defined(__LP64__) || defined(__ia64__) || defined(__x86_64__)
+// Set MINIZ_HAS_64BIT_REGISTERS to 1 if operations on 64-bit integers are reasonably fast (and don't involve compiler generated calls to helper functions).
+#define MINIZ_HAS_64BIT_REGISTERS 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// ------------------- zlib-style API Definitions.
+
+// For more compatibility with zlib, miniz.c uses unsigned long for some parameters/struct members. Beware: mz_ulong can be either 32 or 64-bits!
+typedef unsigned long mz_ulong;
+
+// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap.
+void mz_free(void *p);
+
+#define MZ_ADLER32_INIT (1)
+// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL.
+mz_ulong mz_adler32(mz_ulong adler, const unsigned char *ptr, size_t buf_len);
+
+#define MZ_CRC32_INIT (0)
+// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL.
+mz_ulong mz_crc32(mz_ulong crc, const unsigned char *ptr, size_t buf_len);
+
+// Compression strategies.
+enum { MZ_DEFAULT_STRATEGY = 0, MZ_FILTERED = 1, MZ_HUFFMAN_ONLY = 2, MZ_RLE = 3, MZ_FIXED = 4 };
+
+// Method
+#define MZ_DEFLATED 8
+
+#ifndef MINIZ_NO_ZLIB_APIS
+
+// Heap allocation callbacks.
+// Note that mz_alloc_func parameter types purpsosely differ from zlib's: items/size is size_t, not unsigned long.
+typedef void *(*mz_alloc_func)(void *opaque, size_t items, size_t size);
+typedef void (*mz_free_func)(void *opaque, void *address);
+typedef void *(*mz_realloc_func)(void *opaque, void *address, size_t items, size_t size);
+
+#define MZ_VERSION          "9.1.15"
+#define MZ_VERNUM           0x91F0
+#define MZ_VER_MAJOR        9
+#define MZ_VER_MINOR        1
+#define MZ_VER_REVISION     15
+#define MZ_VER_SUBREVISION  0
+
+// Flush values. For typical usage you only need MZ_NO_FLUSH and MZ_FINISH. The other values are for advanced use (refer to the zlib docs).
+enum { MZ_NO_FLUSH = 0, MZ_PARTIAL_FLUSH = 1, MZ_SYNC_FLUSH = 2, MZ_FULL_FLUSH = 3, MZ_FINISH = 4, MZ_BLOCK = 5 };
+
+// Return status codes. MZ_PARAM_ERROR is non-standard.
+enum { MZ_OK = 0, MZ_STREAM_END = 1, MZ_NEED_DICT = 2, MZ_ERRNO = -1, MZ_STREAM_ERROR = -2, MZ_DATA_ERROR = -3, MZ_MEM_ERROR = -4, MZ_BUF_ERROR = -5, MZ_VERSION_ERROR = -6, MZ_PARAM_ERROR = -10000 };
+
+// Compression levels: 0-9 are the standard zlib-style levels, 10 is best possible compression (not zlib compatible, and may be very slow), MZ_DEFAULT_COMPRESSION=MZ_DEFAULT_LEVEL.
+enum { MZ_NO_COMPRESSION = 0, MZ_BEST_SPEED = 1, MZ_BEST_COMPRESSION = 9, MZ_UBER_COMPRESSION = 10, MZ_DEFAULT_LEVEL = 6, MZ_DEFAULT_COMPRESSION = -1 };
+
+// Window bits
+#define MZ_DEFAULT_WINDOW_BITS 15
+
+struct mz_internal_state;
+
+// Compression/decompression stream struct.
+typedef struct mz_stream_s
+{
+  const unsigned char *next_in;     // pointer to next byte to read
+  unsigned int avail_in;            // number of bytes available at next_in
+  mz_ulong total_in;                // total number of bytes consumed so far
+
+  unsigned char *next_out;          // pointer to next byte to write
+  unsigned int avail_out;           // number of bytes that can be written to next_out
+  mz_ulong total_out;               // total number of bytes produced so far
+
+  char *msg;                        // error msg (unused)
+  struct mz_internal_state *state;  // internal state, allocated by zalloc/zfree
+
+  mz_alloc_func zalloc;             // optional heap allocation function (defaults to malloc)
+  mz_free_func zfree;               // optional heap free function (defaults to free)
+  void *opaque;                     // heap alloc function user pointer
+
+  int data_type;                    // data_type (unused)
+  mz_ulong adler;                   // adler32 of the source or uncompressed data
+  mz_ulong reserved;                // not used
+} mz_stream;
+
+typedef mz_stream *mz_streamp;
+
+// Returns the version string of miniz.c.
+const char *mz_version(void);
+
+// mz_deflateInit() initializes a compressor with default options:
+// Parameters:
+//  pStream must point to an initialized mz_stream struct.
+//  level must be between [MZ_NO_COMPRESSION, MZ_BEST_COMPRESSION].
+//  level 1 enables a specially optimized compression function that's been optimized purely for performance, not ratio.
+//  (This special func. is currently only enabled when MINIZ_USE_UNALIGNED_LOADS_AND_STORES and MINIZ_LITTLE_ENDIAN are defined.)
+// Return values:
+//  MZ_OK on success.
+//  MZ_STREAM_ERROR if the stream is bogus.
+//  MZ_PARAM_ERROR if the input parameters are bogus.
+//  MZ_MEM_ERROR on out of memory.
+int mz_deflateInit(mz_streamp pStream, int level);
+
+// mz_deflateInit2() is like mz_deflate(), except with more control:
+// Additional parameters:
+//   method must be MZ_DEFLATED
+//   window_bits must be MZ_DEFAULT_WINDOW_BITS (to wrap the deflate stream with zlib header/adler-32 footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate/no header or footer)
+//   mem_level must be between [1, 9] (it's checked but ignored by miniz.c)
+int mz_deflateInit2(mz_streamp pStream, int level, int method, int window_bits, int mem_level, int strategy);
+
+// Quickly resets a compressor without having to reallocate anything. Same as calling mz_deflateEnd() followed by mz_deflateInit()/mz_deflateInit2().
+int mz_deflateReset(mz_streamp pStream);
+
+// mz_deflate() compresses the input to output, consuming as much of the input and producing as much output as possible.
+// Parameters:
+//   pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
+//   flush may be MZ_NO_FLUSH, MZ_PARTIAL_FLUSH/MZ_SYNC_FLUSH, MZ_FULL_FLUSH, or MZ_FINISH.
+// Return values:
+//   MZ_OK on success (when flushing, or if more input is needed but not available, and/or there's more output to be written but the output buffer is full).
+//   MZ_STREAM_END if all input has been consumed and all output bytes have been written. Don't call mz_deflate() on the stream anymore.
+//   MZ_STREAM_ERROR if the stream is bogus.
+//   MZ_PARAM_ERROR if one of the parameters is invalid.
+//   MZ_BUF_ERROR if no forward progress is possible because the input and/or output buffers are empty. (Fill up the input buffer or free up some output space and try again.)
+int mz_deflate(mz_streamp pStream, int flush);
+
+// mz_deflateEnd() deinitializes a compressor:
+// Return values:
+//  MZ_OK on success.
+//  MZ_STREAM_ERROR if the stream is bogus.
+int mz_deflateEnd(mz_streamp pStream);
+
+// mz_deflateBound() returns a (very) conservative upper bound on the amount of data that could be generated by deflate(), assuming flush is set to only MZ_NO_FLUSH or MZ_FINISH.
+mz_ulong mz_deflateBound(mz_streamp pStream, mz_ulong source_len);
+
+// Single-call compression functions mz_compress() and mz_compress2():
+// Returns MZ_OK on success, or one of the error codes from mz_deflate() on failure.
+int mz_compress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
+int mz_compress2(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len, int level);
+
+// mz_compressBound() returns a (very) conservative upper bound on the amount of data that could be generated by calling mz_compress().
+mz_ulong mz_compressBound(mz_ulong source_len);
+
+// Initializes a decompressor.
+int mz_inflateInit(mz_streamp pStream);
+
+// mz_inflateInit2() is like mz_inflateInit() with an additional option that controls the window size and whether or not the stream has been wrapped with a zlib header/footer:
+// window_bits must be MZ_DEFAULT_WINDOW_BITS (to parse zlib header/footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate).
+int mz_inflateInit2(mz_streamp pStream, int window_bits);
+
+// Decompresses the input stream to the output, consuming only as much of the input as needed, and writing as much to the output as possible.
+// Parameters:
+//   pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
+//   flush may be MZ_NO_FLUSH, MZ_SYNC_FLUSH, or MZ_FINISH.
+//   On the first call, if flush is MZ_FINISH it's assumed the input and output buffers are both sized large enough to decompress the entire stream in a single call (this is slightly faster).
+//   MZ_FINISH implies that there are no more source bytes available beside what's already in the input buffer, and that the output buffer is large enough to hold the rest of the decompressed data.
+// Return values:
+//   MZ_OK on success. Either more input is needed but not available, and/or there's more output to be written but the output buffer is full.
+//   MZ_STREAM_END if all needed input has been consumed and all output bytes have been written. For zlib streams, the adler-32 of the decompressed data has also been verified.
+//   MZ_STREAM_ERROR if the stream is bogus.
+//   MZ_DATA_ERROR if the deflate stream is invalid.
+//   MZ_PARAM_ERROR if one of the parameters is invalid.
+//   MZ_BUF_ERROR if no forward progress is possible because the input buffer is empty but the inflater needs more input to continue, or if the output buffer is not large enough. Call mz_inflate() again
+//   with more input data, or with more room in the output buffer (except when using single call decompression, described above).
+int mz_inflate(mz_streamp pStream, int flush);
+
+// Deinitializes a decompressor.
+int mz_inflateEnd(mz_streamp pStream);
+
+// Single-call decompression.
+// Returns MZ_OK on success, or one of the error codes from mz_inflate() on failure.
+int mz_uncompress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
+
+// Returns a string description of the specified error code, or NULL if the error code is invalid.
+const char *mz_error(int err);
+
+// Redefine zlib-compatible names to miniz equivalents, so miniz.c can be used as a drop-in replacement for the subset of zlib that miniz.c supports.
+// Define MINIZ_NO_ZLIB_COMPATIBLE_NAMES to disable zlib-compatibility if you use zlib in the same project.
+#ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
+  typedef unsigned char Byte;
+  typedef unsigned int uInt;
+  typedef mz_ulong uLong;
+  typedef Byte Bytef;
+  typedef uInt uIntf;
+  typedef char charf;
+  typedef int intf;
+  typedef void *voidpf;
+  typedef uLong uLongf;
+  typedef void *voidp;
+  typedef void *const voidpc;
+  #define Z_NULL                0
+  #define Z_NO_FLUSH            MZ_NO_FLUSH
+  #define Z_PARTIAL_FLUSH       MZ_PARTIAL_FLUSH
+  #define Z_SYNC_FLUSH          MZ_SYNC_FLUSH
+  #define Z_FULL_FLUSH          MZ_FULL_FLUSH
+  #define Z_FINISH              MZ_FINISH
+  #define Z_BLOCK               MZ_BLOCK
+  #define Z_OK                  MZ_OK
+  #define Z_STREAM_END          MZ_STREAM_END
+  #define Z_NEED_DICT           MZ_NEED_DICT
+  #define Z_ERRNO               MZ_ERRNO
+  #define Z_STREAM_ERROR        MZ_STREAM_ERROR
+  #define Z_DATA_ERROR          MZ_DATA_ERROR
+  #define Z_MEM_ERROR           MZ_MEM_ERROR
+  #define Z_BUF_ERROR           MZ_BUF_ERROR
+  #define Z_VERSION_ERROR       MZ_VERSION_ERROR
+  #define Z_PARAM_ERROR         MZ_PARAM_ERROR
+  #define Z_NO_COMPRESSION      MZ_NO_COMPRESSION
+  #define Z_BEST_SPEED          MZ_BEST_SPEED
+  #define Z_BEST_COMPRESSION    MZ_BEST_COMPRESSION
+  #define Z_DEFAULT_COMPRESSION MZ_DEFAULT_COMPRESSION
+  #define Z_DEFAULT_STRATEGY    MZ_DEFAULT_STRATEGY
+  #define Z_FILTERED            MZ_FILTERED
+  #define Z_HUFFMAN_ONLY        MZ_HUFFMAN_ONLY
+  #define Z_RLE                 MZ_RLE
+  #define Z_FIXED               MZ_FIXED
+  #define Z_DEFLATED            MZ_DEFLATED
+  #define Z_DEFAULT_WINDOW_BITS MZ_DEFAULT_WINDOW_BITS
+  #define alloc_func            mz_alloc_func
+  #define free_func             mz_free_func
+  #define internal_state        mz_internal_state
+  #define z_stream              mz_stream
+  #define deflateInit           mz_deflateInit
+  #define deflateInit2          mz_deflateInit2
+  #define deflateReset          mz_deflateReset
+  #define deflate               mz_deflate
+  #define deflateEnd            mz_deflateEnd
+  #define deflateBound          mz_deflateBound
+  #define compress              mz_compress
+  #define compress2             mz_compress2
+  #define compressBound         mz_compressBound
+  #define inflateInit           mz_inflateInit
+  #define inflateInit2          mz_inflateInit2
+  #define inflate               mz_inflate
+  #define inflateEnd            mz_inflateEnd
+  #define uncompress            mz_uncompress
+  #define crc32                 mz_crc32
+  #define adler32               mz_adler32
+  #define MAX_WBITS             15
+  #define MAX_MEM_LEVEL         9
+  #define zError                mz_error
+  #define ZLIB_VERSION          MZ_VERSION
+  #define ZLIB_VERNUM           MZ_VERNUM
+  #define ZLIB_VER_MAJOR        MZ_VER_MAJOR
+  #define ZLIB_VER_MINOR        MZ_VER_MINOR
+  #define ZLIB_VER_REVISION     MZ_VER_REVISION
+  #define ZLIB_VER_SUBREVISION  MZ_VER_SUBREVISION
+  #define zlibVersion           mz_version
+  #define zlib_version          mz_version()
+#endif // #ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
+
+#endif // MINIZ_NO_ZLIB_APIS
+
+// ------------------- Types and macros
+
+typedef unsigned char mz_uint8;
+typedef signed short mz_int16;
+typedef unsigned short mz_uint16;
+typedef unsigned int mz_uint32;
+typedef unsigned int mz_uint;
+typedef long long mz_int64;
+typedef unsigned long long mz_uint64;
+typedef int mz_bool;
+
+#define MZ_FALSE (0)
+#define MZ_TRUE (1)
+
+// An attempt to work around MSVC's spammy "warning C4127: conditional expression is constant" message.
+#ifdef _MSC_VER
+   #define MZ_MACRO_END while (0, 0)
+#else
+   #define MZ_MACRO_END while (0)
+#endif
+
+// ------------------- ZIP archive reading/writing
+
+#ifndef MINIZ_NO_ARCHIVE_APIS
+
+enum
+{
+  MZ_ZIP_MAX_IO_BUF_SIZE = 64*1024,
+  MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE = 260,
+  MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE = 256
+};
+
+typedef struct
+{
+  mz_uint32 m_file_index;
+  mz_uint32 m_central_dir_ofs;
+  mz_uint16 m_version_made_by;
+  mz_uint16 m_version_needed;
+  mz_uint16 m_bit_flag;
+  mz_uint16 m_method;
+#ifndef MINIZ_NO_TIME
+  time_t m_time;
+#endif
+  mz_uint32 m_crc32;
+  mz_uint64 m_comp_size;
+  mz_uint64 m_uncomp_size;
+  mz_uint16 m_internal_attr;
+  mz_uint32 m_external_attr;
+  mz_uint64 m_local_header_ofs;
+  mz_uint32 m_comment_size;
+  char m_filename[MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE];
+  char m_comment[MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE];
+} mz_zip_archive_file_stat;
+
+typedef size_t (*mz_file_read_func)(void *pOpaque, mz_uint64 file_ofs, void *pBuf, size_t n);
+typedef size_t (*mz_file_write_func)(void *pOpaque, mz_uint64 file_ofs, const void *pBuf, size_t n);
+
+struct mz_zip_internal_state_tag;
+typedef struct mz_zip_internal_state_tag mz_zip_internal_state;
+
+typedef enum
+{
+  MZ_ZIP_MODE_INVALID = 0,
+  MZ_ZIP_MODE_READING = 1,
+  MZ_ZIP_MODE_WRITING = 2,
+  MZ_ZIP_MODE_WRITING_HAS_BEEN_FINALIZED = 3
+} mz_zip_mode;
+
+typedef struct mz_zip_archive_tag
+{
+  mz_uint64 m_archive_size;
+  mz_uint64 m_central_directory_file_ofs;
+  mz_uint m_total_files;
+  mz_zip_mode m_zip_mode;
+
+  mz_uint m_file_offset_alignment;
+
+  mz_alloc_func m_pAlloc;
+  mz_free_func m_pFree;
+  mz_realloc_func m_pRealloc;
+  void *m_pAlloc_opaque;
+
+  mz_file_read_func m_pRead;
+  mz_file_write_func m_pWrite;
+  void *m_pIO_opaque;
+
+  mz_zip_internal_state *m_pState;
+
+} mz_zip_archive;
+
+typedef enum
+{
+  MZ_ZIP_FLAG_CASE_SENSITIVE                = 0x0100,
+  MZ_ZIP_FLAG_IGNORE_PATH                   = 0x0200,
+  MZ_ZIP_FLAG_COMPRESSED_DATA               = 0x0400,
+  MZ_ZIP_FLAG_DO_NOT_SORT_CENTRAL_DIRECTORY = 0x0800
+} mz_zip_flags;
+
+// ZIP archive reading
+
+// Inits a ZIP archive reader.
+// These functions read and validate the archive's central directory.
+mz_bool mz_zip_reader_init(mz_zip_archive *pZip, mz_uint64 size, mz_uint32 flags);
+mz_bool mz_zip_reader_init_mem(mz_zip_archive *pZip, const void *pMem, size_t size, mz_uint32 flags);
+
+#ifndef MINIZ_NO_STDIO
+mz_bool mz_zip_reader_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint32 flags);
+#endif
+
+// Returns the total number of files in the archive.
+mz_uint mz_zip_reader_get_num_files(mz_zip_archive *pZip);
+
+// Returns detailed information about an archive file entry.
+mz_bool mz_zip_reader_file_stat(mz_zip_archive *pZip, mz_uint file_index, mz_zip_archive_file_stat *pStat);
+
+// Determines if an archive file entry is a directory entry.
+mz_bool mz_zip_reader_is_file_a_directory(mz_zip_archive *pZip, mz_uint file_index);
+mz_bool mz_zip_reader_is_file_encrypted(mz_zip_archive *pZip, mz_uint file_index);
+
+// Retrieves the filename of an archive file entry.
+// Returns the number of bytes written to pFilename, or if filename_buf_size is 0 this function returns the number of bytes needed to fully store the filename.
+mz_uint mz_zip_reader_get_filename(mz_zip_archive *pZip, mz_uint file_index, char *pFilename, mz_uint filename_buf_size);
+
+// Attempts to locates a file in the archive's central directory.
+// Valid flags: MZ_ZIP_FLAG_CASE_SENSITIVE, MZ_ZIP_FLAG_IGNORE_PATH
+// Returns -1 if the file cannot be found.
+int mz_zip_reader_locate_file(mz_zip_archive *pZip, const char *pName, const char *pComment, mz_uint flags);
+
+// Extracts a archive file to a memory buffer using no memory allocation.
+mz_bool mz_zip_reader_extract_to_mem_no_alloc(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
+mz_bool mz_zip_reader_extract_file_to_mem_no_alloc(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
+
+// Extracts a archive file to a memory buffer.
+mz_bool mz_zip_reader_extract_to_mem(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags);
+mz_bool mz_zip_reader_extract_file_to_mem(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags);
+
+// Extracts a archive file to a dynamically allocated heap buffer.
+void *mz_zip_reader_extract_to_heap(mz_zip_archive *pZip, mz_uint file_index, size_t *pSize, mz_uint flags);
+void *mz_zip_reader_extract_file_to_heap(mz_zip_archive *pZip, const char *pFilename, size_t *pSize, mz_uint flags);
+
+// Extracts a archive file using a callback function to output the file's data.
+mz_bool mz_zip_reader_extract_to_callback(mz_zip_archive *pZip, mz_uint file_index, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
+mz_bool mz_zip_reader_extract_file_to_callback(mz_zip_archive *pZip, const char *pFilename, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
+
+#ifndef MINIZ_NO_STDIO
+// Extracts a archive file to a disk file and sets its last accessed and modified times.
+// This function only extracts files, not archive directory records.
+mz_bool mz_zip_reader_extract_to_file(mz_zip_archive *pZip, mz_uint file_index, const char *pDst_filename, mz_uint flags);
+mz_bool mz_zip_reader_extract_file_to_file(mz_zip_archive *pZip, const char *pArchive_filename, const char *pDst_filename, mz_uint flags);
+#endif
+
+// Ends archive reading, freeing all allocations, and closing the input archive file if mz_zip_reader_init_file() was used.
+mz_bool mz_zip_reader_end(mz_zip_archive *pZip);
+
+// ZIP archive writing
+
+#ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
+
+// Inits a ZIP archive writer.
+mz_bool mz_zip_writer_init(mz_zip_archive *pZip, mz_uint64 existing_size);
+mz_bool mz_zip_writer_init_heap(mz_zip_archive *pZip, size_t size_to_reserve_at_beginning, size_t initial_allocation_size);
+
+#ifndef MINIZ_NO_STDIO
+mz_bool mz_zip_writer_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint64 size_to_reserve_at_beginning);
+#endif
+
+// Converts a ZIP archive reader object into a writer object, to allow efficient in-place file appends to occur on an existing archive.
+// For archives opened using mz_zip_reader_init_file, pFilename must be the archive's filename so it can be reopened for writing. If the file can't be reopened, mz_zip_reader_end() will be called.
+// For archives opened using mz_zip_reader_init_mem, the memory block must be growable using the realloc callback (which defaults to realloc unless you've overridden it).
+// Finally, for archives opened using mz_zip_reader_init, the mz_zip_archive's user provided m_pWrite function cannot be NULL.
+// Note: In-place archive modification is not recommended unless you know what you're doing, because if execution stops or something goes wrong before
+// the archive is finalized the file's central directory will be hosed.
+mz_bool mz_zip_writer_init_from_reader(mz_zip_archive *pZip, const char *pFilename);
+
+// Adds the contents of a memory buffer to an archive. These functions record the current local time into the archive.
+// To add a directory entry, call this method with an archive name ending in a forwardslash with empty buffer.
+// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
+mz_bool mz_zip_writer_add_mem(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, mz_uint level_and_flags);
+mz_bool mz_zip_writer_add_mem_ex(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags, mz_uint64 uncomp_size, mz_uint32 uncomp_crc32);
+
+#ifndef MINIZ_NO_STDIO
+// Adds the contents of a disk file to an archive. This function also records the disk file's modified time into the archive.
+// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
+mz_bool mz_zip_writer_add_file(mz_zip_archive *pZip, const char *pArchive_name, const char *pSrc_filename, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
+#endif
+
+// Adds a file to an archive by fully cloning the data from another archive.
+// This function fully clones the source file's compressed data (no recompression), along with its full filename, extra data, and comment fields.
+mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive *pSource_zip, mz_uint file_index);
+
+// Finalizes the archive by writing the central directory records followed by the end of central directory record.
+// After an archive is finalized, the only valid call on the mz_zip_archive struct is mz_zip_writer_end().
+// An archive must be manually finalized by calling this function for it to be valid.
+mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip);
+mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **pBuf, size_t *pSize);
+
+// Ends archive writing, freeing all allocations, and closing the output file if mz_zip_writer_init_file() was used.
+// Note for the archive to be valid, it must have been finalized before ending.
+mz_bool mz_zip_writer_end(mz_zip_archive *pZip);
+
+// Misc. high-level helper functions:
+
+// mz_zip_add_mem_to_archive_file_in_place() efficiently (but not atomically) appends a memory blob to a ZIP archive.
+// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
+mz_bool mz_zip_add_mem_to_archive_file_in_place(const char *pZip_filename, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
+
+// Reads a single file from an archive into a heap block.
+// Returns NULL on failure.
+void *mz_zip_extract_archive_file_to_heap(const char *pZip_filename, const char *pArchive_name, size_t *pSize, mz_uint zip_flags);
+
+#endif // #ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
+
+#endif // #ifndef MINIZ_NO_ARCHIVE_APIS
+
+// ------------------- Low-level Decompression API Definitions
+
+// Decompression flags used by tinfl_decompress().
+// TINFL_FLAG_PARSE_ZLIB_HEADER: If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib stream). Otherwise, the input is a raw deflate stream.
+// TINFL_FLAG_HAS_MORE_INPUT: If set, there are more input bytes available beyond the end of the supplied input buffer. If clear, the input buffer contains all remaining input.
+// TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: If set, the output buffer is large enough to hold the entire decompressed stream. If clear, the output buffer is at least the size of the dictionary (typically 32KB).
+// TINFL_FLAG_COMPUTE_ADLER32: Force adler-32 checksum computation of the decompressed bytes.
+enum
+{
+  TINFL_FLAG_PARSE_ZLIB_HEADER = 1,
+  TINFL_FLAG_HAS_MORE_INPUT = 2,
+  TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF = 4,
+  TINFL_FLAG_COMPUTE_ADLER32 = 8
+};
+
+// High level decompression functions:
+// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc().
+// On entry:
+//  pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress.
+// On return:
+//  Function returns a pointer to the decompressed data, or NULL on failure.
+//  *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data.
+//  The caller must call mz_free() on the returned block when it's no longer needed.
+void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
+
+// tinfl_decompress_mem_to_mem() decompresses a block in memory to another block in memory.
+// Returns TINFL_DECOMPRESS_MEM_TO_MEM_FAILED on failure, or the number of bytes written on success.
+#define TINFL_DECOMPRESS_MEM_TO_MEM_FAILED ((size_t)(-1))
+size_t tinfl_decompress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
+
+// tinfl_decompress_mem_to_callback() decompresses a block in memory to an internal 32KB buffer, and a user provided callback function will be called to flush the buffer.
+// Returns 1 on success or 0 on failure.
+typedef int (*tinfl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser);
+int tinfl_decompress_mem_to_callback(const void *pIn_buf, size_t *pIn_buf_size, tinfl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
+
+struct tinfl_decompressor_tag; typedef struct tinfl_decompressor_tag tinfl_decompressor;
+
+// Max size of LZ dictionary.
+#define TINFL_LZ_DICT_SIZE 32768
+
+// Return status.
+typedef enum
+{
+  TINFL_STATUS_BAD_PARAM = -3,
+  TINFL_STATUS_ADLER32_MISMATCH = -2,
+  TINFL_STATUS_FAILED = -1,
+  TINFL_STATUS_DONE = 0,
+  TINFL_STATUS_NEEDS_MORE_INPUT = 1,
+  TINFL_STATUS_HAS_MORE_OUTPUT = 2
+} tinfl_status;
+
+// Initializes the decompressor to its initial state.
+#define tinfl_init(r) do { (r)->m_state = 0; } MZ_MACRO_END
+#define tinfl_get_adler32(r) (r)->m_check_adler32
+
+// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability.
+// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output.
+tinfl_status tinfl_decompress(tinfl_decompressor *r, const mz_uint8 *pIn_buf_next, size_t *pIn_buf_size, mz_uint8 *pOut_buf_start, mz_uint8 *pOut_buf_next, size_t *pOut_buf_size, const mz_uint32 decomp_flags);
+
+// Internal/private bits follow.
+enum
+{
+  TINFL_MAX_HUFF_TABLES = 3, TINFL_MAX_HUFF_SYMBOLS_0 = 288, TINFL_MAX_HUFF_SYMBOLS_1 = 32, TINFL_MAX_HUFF_SYMBOLS_2 = 19,
+  TINFL_FAST_LOOKUP_BITS = 10, TINFL_FAST_LOOKUP_SIZE = 1 << TINFL_FAST_LOOKUP_BITS
+};
+
+typedef struct
+{
+  mz_uint8 m_code_size[TINFL_MAX_HUFF_SYMBOLS_0];
+  mz_int16 m_look_up[TINFL_FAST_LOOKUP_SIZE], m_tree[TINFL_MAX_HUFF_SYMBOLS_0 * 2];
+} tinfl_huff_table;
+
+#if MINIZ_HAS_64BIT_REGISTERS
+  #define TINFL_USE_64BIT_BITBUF 1
+#endif
+
+#if TINFL_USE_64BIT_BITBUF
+  typedef mz_uint64 tinfl_bit_buf_t;
+  #define TINFL_BITBUF_SIZE (64)
+#else
+  typedef mz_uint32 tinfl_bit_buf_t;
+  #define TINFL_BITBUF_SIZE (32)
+#endif
+
+struct tinfl_decompressor_tag
+{
+  mz_uint32 m_state, m_num_bits, m_zhdr0, m_zhdr1, m_z_adler32, m_final, m_type, m_check_adler32, m_dist, m_counter, m_num_extra, m_table_sizes[TINFL_MAX_HUFF_TABLES];
+  tinfl_bit_buf_t m_bit_buf;
+  size_t m_dist_from_out_buf_start;
+  tinfl_huff_table m_tables[TINFL_MAX_HUFF_TABLES];
+  mz_uint8 m_raw_header[4], m_len_codes[TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137];
+};
+
+// ------------------- Low-level Compression API Definitions
+
+// Set TDEFL_LESS_MEMORY to 1 to use less memory (compression will be slightly slower, and raw/dynamic blocks will be output more frequently).
+#define TDEFL_LESS_MEMORY 1
+
+// tdefl_init() compression flags logically OR'd together (low 12 bits contain the max. number of probes per dictionary search):
+// TDEFL_DEFAULT_MAX_PROBES: The compressor defaults to 128 dictionary probes per dictionary search. 0=Huffman only, 1=Huffman+LZ (fastest/crap compression), 4095=Huffman+LZ (slowest/best compression).
+enum
+{
+  TDEFL_HUFFMAN_ONLY = 0, TDEFL_DEFAULT_MAX_PROBES = 128, TDEFL_MAX_PROBES_MASK = 0xFFF
+};
+
+// TDEFL_WRITE_ZLIB_HEADER: If set, the compressor outputs a zlib header before the deflate data, and the Adler-32 of the source data at the end. Otherwise, you'll get raw deflate data.
+// TDEFL_COMPUTE_ADLER32: Always compute the adler-32 of the input data (even when not writing zlib headers).
+// TDEFL_GREEDY_PARSING_FLAG: Set to use faster greedy parsing, instead of more efficient lazy parsing.
+// TDEFL_NONDETERMINISTIC_PARSING_FLAG: Enable to decrease the compressor's initialization time to the minimum, but the output may vary from run to run given the same input (depending on the contents of memory).
+// TDEFL_RLE_MATCHES: Only look for RLE matches (matches with a distance of 1)
+// TDEFL_FILTER_MATCHES: Discards matches <= 5 chars if enabled.
+// TDEFL_FORCE_ALL_STATIC_BLOCKS: Disable usage of optimized Huffman tables.
+// TDEFL_FORCE_ALL_RAW_BLOCKS: Only use raw (uncompressed) deflate blocks.
+// The low 12 bits are reserved to control the max # of hash probes per dictionary lookup (see TDEFL_MAX_PROBES_MASK).
+enum
+{
+  TDEFL_WRITE_ZLIB_HEADER             = 0x01000,
+  TDEFL_COMPUTE_ADLER32               = 0x02000,
+  TDEFL_GREEDY_PARSING_FLAG           = 0x04000,
+  TDEFL_NONDETERMINISTIC_PARSING_FLAG = 0x08000,
+  TDEFL_RLE_MATCHES                   = 0x10000,
+  TDEFL_FILTER_MATCHES                = 0x20000,
+  TDEFL_FORCE_ALL_STATIC_BLOCKS       = 0x40000,
+  TDEFL_FORCE_ALL_RAW_BLOCKS          = 0x80000
+};
+
+// High level compression functions:
+// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc().
+// On entry:
+//  pSrc_buf, src_buf_len: Pointer and size of source block to compress.
+//  flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression.
+// On return:
+//  Function returns a pointer to the compressed data, or NULL on failure.
+//  *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data.
+//  The caller must free() the returned block when it's no longer needed.
+void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
+
+// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory.
+// Returns 0 on failure.
+size_t tdefl_compress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
+
+// Compresses an image to a compressed PNG file in memory.
+// On entry:
+//  pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4. 
+//  The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory.
+//  level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL
+//  If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps).
+// On return:
+//  Function returns a pointer to the compressed data, or NULL on failure.
+//  *pLen_out will be set to the size of the PNG image file.
+//  The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed.
+void *tdefl_write_image_to_png_file_in_memory_ex(const void *pImage, int w, int h, int num_chans, size_t *pLen_out, mz_uint level, mz_bool flip);
+void *tdefl_write_image_to_png_file_in_memory(const void *pImage, int w, int h, int num_chans, size_t *pLen_out);
+
+// Output stream interface. The compressor uses this interface to write compressed data. It'll typically be called TDEFL_OUT_BUF_SIZE at a time.
+typedef mz_bool (*tdefl_put_buf_func_ptr)(const void* pBuf, int len, void *pUser);
+
+// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally.
+mz_bool tdefl_compress_mem_to_output(const void *pBuf, size_t buf_len, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
+
+enum { TDEFL_MAX_HUFF_TABLES = 3, TDEFL_MAX_HUFF_SYMBOLS_0 = 288, TDEFL_MAX_HUFF_SYMBOLS_1 = 32, TDEFL_MAX_HUFF_SYMBOLS_2 = 19, TDEFL_LZ_DICT_SIZE = 32768, TDEFL_LZ_DICT_SIZE_MASK = TDEFL_LZ_DICT_SIZE - 1, TDEFL_MIN_MATCH_LEN = 3, TDEFL_MAX_MATCH_LEN = 258 };
+
+// TDEFL_OUT_BUF_SIZE MUST be large enough to hold a single entire compressed output block (using static/fixed Huffman codes).
+#if TDEFL_LESS_MEMORY
+enum { TDEFL_LZ_CODE_BUF_SIZE = 24 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 12, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
+#else
+enum { TDEFL_LZ_CODE_BUF_SIZE = 64 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 15, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
+#endif
+
+// The low-level tdefl functions below may be used directly if the above helper functions aren't flexible enough. The low-level functions don't make any heap allocations, unlike the above helper functions.
+typedef enum
+{
+  TDEFL_STATUS_BAD_PARAM = -2,
+  TDEFL_STATUS_PUT_BUF_FAILED = -1,
+  TDEFL_STATUS_OKAY = 0,
+  TDEFL_STATUS_DONE = 1,
+} tdefl_status;
+
+// Must map to MZ_NO_FLUSH, MZ_SYNC_FLUSH, etc. enums
+typedef enum
+{
+  TDEFL_NO_FLUSH = 0,
+  TDEFL_SYNC_FLUSH = 2,
+  TDEFL_FULL_FLUSH = 3,
+  TDEFL_FINISH = 4
+} tdefl_flush;
+
+// tdefl's compression state structure.
+typedef struct
+{
+  tdefl_put_buf_func_ptr m_pPut_buf_func;
+  void *m_pPut_buf_user;
+  mz_uint m_flags, m_max_probes[2];
+  int m_greedy_parsing;
+  mz_uint m_adler32, m_lookahead_pos, m_lookahead_size, m_dict_size;
+  mz_uint8 *m_pLZ_code_buf, *m_pLZ_flags, *m_pOutput_buf, *m_pOutput_buf_end;
+  mz_uint m_num_flags_left, m_total_lz_bytes, m_lz_code_buf_dict_pos, m_bits_in, m_bit_buffer;
+  mz_uint m_saved_match_dist, m_saved_match_len, m_saved_lit, m_output_flush_ofs, m_output_flush_remaining, m_finished, m_block_index, m_wants_to_finish;
+  tdefl_status m_prev_return_status;
+  const void *m_pIn_buf;
+  void *m_pOut_buf;
+  size_t *m_pIn_buf_size, *m_pOut_buf_size;
+  tdefl_flush m_flush;
+  const mz_uint8 *m_pSrc;
+  size_t m_src_buf_left, m_out_buf_ofs;
+  mz_uint8 m_dict[TDEFL_LZ_DICT_SIZE + TDEFL_MAX_MATCH_LEN - 1];
+  mz_uint16 m_huff_count[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
+  mz_uint16 m_huff_codes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
+  mz_uint8 m_huff_code_sizes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
+  mz_uint8 m_lz_code_buf[TDEFL_LZ_CODE_BUF_SIZE];
+  mz_uint16 m_next[TDEFL_LZ_DICT_SIZE];
+  mz_uint16 m_hash[TDEFL_LZ_HASH_SIZE];
+  mz_uint8 m_output_buf[TDEFL_OUT_BUF_SIZE];
+} tdefl_compressor;
+
+// Initializes the compressor.
+// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory.
+// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression.
+// If pBut_buf_func is NULL the user should always call the tdefl_compress() API.
+// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.)
+tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
+
+// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible.
+tdefl_status tdefl_compress(tdefl_compressor *d, const void *pIn_buf, size_t *pIn_buf_size, void *pOut_buf, size_t *pOut_buf_size, tdefl_flush flush);
+
+// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr.
+// tdefl_compress_buffer() always consumes the entire input buffer.
+tdefl_status tdefl_compress_buffer(tdefl_compressor *d, const void *pIn_buf, size_t in_buf_size, tdefl_flush flush);
+
+tdefl_status tdefl_get_prev_return_status(tdefl_compressor *d);
+mz_uint32 tdefl_get_adler32(tdefl_compressor *d);
+
+// Can't use tdefl_create_comp_flags_from_zip_params if MINIZ_NO_ZLIB_APIS isn't defined, because it uses some of its macros.
+#ifndef MINIZ_NO_ZLIB_APIS
+// Create tdefl_compress() flags given zlib-style compression parameters.
+// level may range from [0,10] (where 10 is absolute max compression, but may be much slower on some files)
+// window_bits may be -15 (raw deflate) or 15 (zlib)
+// strategy may be either MZ_DEFAULT_STRATEGY, MZ_FILTERED, MZ_HUFFMAN_ONLY, MZ_RLE, or MZ_FIXED
+mz_uint tdefl_create_comp_flags_from_zip_params(int level, int window_bits, int strategy);
+#endif // #ifndef MINIZ_NO_ZLIB_APIS
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MINIZ_HEADER_INCLUDED
+

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/queue.h

@@ -0,0 +1,645 @@
+/*-
+ * Copyright (c) 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)queue.h	8.5 (Berkeley) 8/20/94
+ * $FreeBSD$
+ */
+
+#ifndef _SYS_QUEUE_H_
+#define _SYS_QUEUE_H_
+
+#include <sys/cdefs.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * This file defines four types of data structures: singly-linked lists,
+ * singly-linked tail queues, lists and tail queues.
+ *
+ * A singly-linked list is headed by a single forward pointer. The elements
+ * are singly linked for minimum space and pointer manipulation overhead at
+ * the expense of O(n) removal for arbitrary elements. New elements can be
+ * added to the list after an existing element or at the head of the list.
+ * Elements being removed from the head of the list should use the explicit
+ * macro for this purpose for optimum efficiency. A singly-linked list may
+ * only be traversed in the forward direction.  Singly-linked lists are ideal
+ * for applications with large datasets and few or no removals or for
+ * implementing a LIFO queue.
+ *
+ * A singly-linked tail queue is headed by a pair of pointers, one to the
+ * head of the list and the other to the tail of the list. The elements are
+ * singly linked for minimum space and pointer manipulation overhead at the
+ * expense of O(n) removal for arbitrary elements. New elements can be added
+ * to the list after an existing element, at the head of the list, or at the
+ * end of the list. Elements being removed from the head of the tail queue
+ * should use the explicit macro for this purpose for optimum efficiency.
+ * A singly-linked tail queue may only be traversed in the forward direction.
+ * Singly-linked tail queues are ideal for applications with large datasets
+ * and few or no removals or for implementing a FIFO queue.
+ *
+ * A list is headed by a single forward pointer (or an array of forward
+ * pointers for a hash table header). The elements are doubly linked
+ * so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before
+ * or after an existing element or at the head of the list. A list
+ * may only be traversed in the forward direction.
+ *
+ * A tail queue is headed by a pair of pointers, one to the head of the
+ * list and the other to the tail of the list. The elements are doubly
+ * linked so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before or
+ * after an existing element, at the head of the list, or at the end of
+ * the list. A tail queue may be traversed in either direction.
+ *
+ * For details on the use of these macros, see the queue(3) manual page.
+ *
+ *
+ *				SLIST	LIST	STAILQ	TAILQ
+ * _HEAD			+	+	+	+
+ * _HEAD_INITIALIZER		+	+	+	+
+ * _ENTRY			+	+	+	+
+ * _INIT			+	+	+	+
+ * _EMPTY			+	+	+	+
+ * _FIRST			+	+	+	+
+ * _NEXT			+	+	+	+
+ * _PREV			-	-	-	+
+ * _LAST			-	-	+	+
+ * _FOREACH			+	+	+	+
+ * _FOREACH_SAFE		+	+	+	+
+ * _FOREACH_REVERSE		-	-	-	+
+ * _FOREACH_REVERSE_SAFE	-	-	-	+
+ * _INSERT_HEAD			+	+	+	+
+ * _INSERT_BEFORE		-	+	-	+
+ * _INSERT_AFTER		+	+	+	+
+ * _INSERT_TAIL			-	-	+	+
+ * _CONCAT			-	-	+	+
+ * _REMOVE_AFTER		+	-	+	-
+ * _REMOVE_HEAD			+	-	+	-
+ * _REMOVE			+	+	+	+
+ *
+ */
+#ifdef QUEUE_MACRO_DEBUG
+/* Store the last 2 places the queue element or head was altered */
+struct qm_trace {
+	char * lastfile;
+	int lastline;
+	char * prevfile;
+	int prevline;
+};
+
+#define	TRACEBUF	struct qm_trace trace;
+#define	TRASHIT(x)	do {(x) = (void *)-1;} while (0)
+#define	QMD_SAVELINK(name, link)	void **name = (void *)&(link)
+
+#define	QMD_TRACE_HEAD(head) do {					\
+	(head)->trace.prevline = (head)->trace.lastline;		\
+	(head)->trace.prevfile = (head)->trace.lastfile;		\
+	(head)->trace.lastline = __LINE__;				\
+	(head)->trace.lastfile = __FILE__;				\
+} while (0)
+
+#define	QMD_TRACE_ELEM(elem) do {					\
+	(elem)->trace.prevline = (elem)->trace.lastline;		\
+	(elem)->trace.prevfile = (elem)->trace.lastfile;		\
+	(elem)->trace.lastline = __LINE__;				\
+	(elem)->trace.lastfile = __FILE__;				\
+} while (0)
+
+#else
+#define	QMD_TRACE_ELEM(elem)
+#define	QMD_TRACE_HEAD(head)
+#define	QMD_SAVELINK(name, link)
+#define	TRACEBUF
+#define	TRASHIT(x)
+#endif	/* QUEUE_MACRO_DEBUG */
+
+/*
+ * Singly-linked List declarations.
+ */
+#define	SLIST_HEAD(name, type)						\
+struct name {								\
+	struct type *slh_first;	/* first element */			\
+}
+
+#define	SLIST_HEAD_INITIALIZER(head)					\
+	{ NULL }
+
+#define	SLIST_ENTRY(type)						\
+struct {								\
+	struct type *sle_next;	/* next element */			\
+}
+
+/*
+ * Singly-linked List functions.
+ */
+#define	SLIST_EMPTY(head)	((head)->slh_first == NULL)
+
+#define	SLIST_FIRST(head)	((head)->slh_first)
+
+#define	SLIST_FOREACH(var, head, field)					\
+	for ((var) = SLIST_FIRST((head));				\
+	    (var);							\
+	    (var) = SLIST_NEXT((var), field))
+
+#define	SLIST_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = SLIST_FIRST((head));				\
+	    (var) && ((tvar) = SLIST_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	SLIST_FOREACH_PREVPTR(var, varp, head, field)			\
+	for ((varp) = &SLIST_FIRST((head));				\
+	    ((var) = *(varp)) != NULL;					\
+	    (varp) = &SLIST_NEXT((var), field))
+
+#define	SLIST_INIT(head) do {						\
+	SLIST_FIRST((head)) = NULL;					\
+} while (0)
+
+#define	SLIST_INSERT_AFTER(slistelm, elm, field) do {			\
+	SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field);	\
+	SLIST_NEXT((slistelm), field) = (elm);				\
+} while (0)
+
+#define	SLIST_INSERT_HEAD(head, elm, field) do {			\
+	SLIST_NEXT((elm), field) = SLIST_FIRST((head));			\
+	SLIST_FIRST((head)) = (elm);					\
+} while (0)
+
+#define	SLIST_NEXT(elm, field)	((elm)->field.sle_next)
+
+#define	SLIST_REMOVE(head, elm, type, field) do {			\
+	QMD_SAVELINK(oldnext, (elm)->field.sle_next);			\
+	if (SLIST_FIRST((head)) == (elm)) {				\
+		SLIST_REMOVE_HEAD((head), field);			\
+	}								\
+	else {								\
+		struct type *curelm = SLIST_FIRST((head));		\
+		while (SLIST_NEXT(curelm, field) != (elm))		\
+			curelm = SLIST_NEXT(curelm, field);		\
+		SLIST_REMOVE_AFTER(curelm, field);			\
+	}								\
+	TRASHIT(*oldnext);						\
+} while (0)
+
+#define SLIST_REMOVE_AFTER(elm, field) do {				\
+	SLIST_NEXT(elm, field) =					\
+	    SLIST_NEXT(SLIST_NEXT(elm, field), field);			\
+} while (0)
+
+#define	SLIST_REMOVE_HEAD(head, field) do {				\
+	SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field);	\
+} while (0)
+
+/*
+ * Singly-linked Tail queue declarations.
+ */
+#define	STAILQ_HEAD(name, type)						\
+struct name {								\
+	struct type *stqh_first;/* first element */			\
+	struct type **stqh_last;/* addr of last next element */		\
+}
+
+#define	STAILQ_HEAD_INITIALIZER(head)					\
+	{ NULL, &(head).stqh_first }
+
+#define	STAILQ_ENTRY(type)						\
+struct {								\
+	struct type *stqe_next;	/* next element */			\
+}
+
+/*
+ * Singly-linked Tail queue functions.
+ */
+#define	STAILQ_CONCAT(head1, head2) do {				\
+	if (!STAILQ_EMPTY((head2))) {					\
+		*(head1)->stqh_last = (head2)->stqh_first;		\
+		(head1)->stqh_last = (head2)->stqh_last;		\
+		STAILQ_INIT((head2));					\
+	}								\
+} while (0)
+
+#define	STAILQ_EMPTY(head)	((head)->stqh_first == NULL)
+
+#define	STAILQ_FIRST(head)	((head)->stqh_first)
+
+#define	STAILQ_FOREACH(var, head, field)				\
+	for((var) = STAILQ_FIRST((head));				\
+	   (var);							\
+	   (var) = STAILQ_NEXT((var), field))
+
+
+#define	STAILQ_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = STAILQ_FIRST((head));				\
+	    (var) && ((tvar) = STAILQ_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	STAILQ_INIT(head) do {						\
+	STAILQ_FIRST((head)) = NULL;					\
+	(head)->stqh_last = &STAILQ_FIRST((head));			\
+} while (0)
+
+#define	STAILQ_INSERT_AFTER(head, tqelm, elm, field) do {		\
+	if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+	STAILQ_NEXT((tqelm), field) = (elm);				\
+} while (0)
+
+#define	STAILQ_INSERT_HEAD(head, elm, field) do {			\
+	if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL)	\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+	STAILQ_FIRST((head)) = (elm);					\
+} while (0)
+
+#define	STAILQ_INSERT_TAIL(head, elm, field) do {			\
+	STAILQ_NEXT((elm), field) = NULL;				\
+	*(head)->stqh_last = (elm);					\
+	(head)->stqh_last = &STAILQ_NEXT((elm), field);			\
+} while (0)
+
+#define	STAILQ_LAST(head, type, field)					\
+	(STAILQ_EMPTY((head)) ?						\
+		NULL :							\
+	        ((struct type *)(void *)				\
+		((char *)((head)->stqh_last) - __offsetof(struct type, field))))
+
+#define	STAILQ_NEXT(elm, field)	((elm)->field.stqe_next)
+
+#define	STAILQ_REMOVE(head, elm, type, field) do {			\
+	QMD_SAVELINK(oldnext, (elm)->field.stqe_next);			\
+	if (STAILQ_FIRST((head)) == (elm)) {				\
+		STAILQ_REMOVE_HEAD((head), field);			\
+	}								\
+	else {								\
+		struct type *curelm = STAILQ_FIRST((head));		\
+		while (STAILQ_NEXT(curelm, field) != (elm))		\
+			curelm = STAILQ_NEXT(curelm, field);		\
+		STAILQ_REMOVE_AFTER(head, curelm, field);		\
+	}								\
+	TRASHIT(*oldnext);						\
+} while (0)
+
+#define	STAILQ_REMOVE_HEAD(head, field) do {				\
+	if ((STAILQ_FIRST((head)) =					\
+	     STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL)		\
+		(head)->stqh_last = &STAILQ_FIRST((head));		\
+} while (0)
+
+#define STAILQ_REMOVE_AFTER(head, elm, field) do {			\
+	if ((STAILQ_NEXT(elm, field) =					\
+	     STAILQ_NEXT(STAILQ_NEXT(elm, field), field)) == NULL)	\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+} while (0)
+
+#define STAILQ_SWAP(head1, head2, type) do {				\
+	struct type *swap_first = STAILQ_FIRST(head1);			\
+	struct type **swap_last = (head1)->stqh_last;			\
+	STAILQ_FIRST(head1) = STAILQ_FIRST(head2);			\
+	(head1)->stqh_last = (head2)->stqh_last;			\
+	STAILQ_FIRST(head2) = swap_first;				\
+	(head2)->stqh_last = swap_last;					\
+	if (STAILQ_EMPTY(head1))					\
+		(head1)->stqh_last = &STAILQ_FIRST(head1);		\
+	if (STAILQ_EMPTY(head2))					\
+		(head2)->stqh_last = &STAILQ_FIRST(head2);		\
+} while (0)
+
+#define STAILQ_INSERT_CHAIN_HEAD(head, elm_chead, elm_ctail, field) do {   \
+    if ((STAILQ_NEXT(elm_ctail, field) = STAILQ_FIRST(head)) == NULL ) { \
+        (head)->stqh_last = &STAILQ_NEXT(elm_ctail, field);            \
+    }                                                                      \
+    STAILQ_FIRST(head) = (elm_chead);                                    \
+} while (0)
+
+
+/*
+ * List declarations.
+ */
+#define	LIST_HEAD(name, type)						\
+struct name {								\
+	struct type *lh_first;	/* first element */			\
+}
+
+#define	LIST_HEAD_INITIALIZER(head)					\
+	{ NULL }
+
+#define	LIST_ENTRY(type)						\
+struct {								\
+	struct type *le_next;	/* next element */			\
+	struct type **le_prev;	/* address of previous next element */	\
+}
+
+/*
+ * List functions.
+ */
+
+#if (defined(_KERNEL) && defined(INVARIANTS))
+#define	QMD_LIST_CHECK_HEAD(head, field) do {				\
+	if (LIST_FIRST((head)) != NULL &&				\
+	    LIST_FIRST((head))->field.le_prev !=			\
+	     &LIST_FIRST((head)))					\
+		panic("Bad list head %p first->prev != head", (head));	\
+} while (0)
+
+#define	QMD_LIST_CHECK_NEXT(elm, field) do {				\
+	if (LIST_NEXT((elm), field) != NULL &&				\
+	    LIST_NEXT((elm), field)->field.le_prev !=			\
+	     &((elm)->field.le_next))					\
+	     	panic("Bad link elm %p next->prev != elm", (elm));	\
+} while (0)
+
+#define	QMD_LIST_CHECK_PREV(elm, field) do {				\
+	if (*(elm)->field.le_prev != (elm))				\
+		panic("Bad link elm %p prev->next != elm", (elm));	\
+} while (0)
+#else
+#define	QMD_LIST_CHECK_HEAD(head, field)
+#define	QMD_LIST_CHECK_NEXT(elm, field)
+#define	QMD_LIST_CHECK_PREV(elm, field)
+#endif /* (_KERNEL && INVARIANTS) */
+
+#define	LIST_EMPTY(head)	((head)->lh_first == NULL)
+
+#define	LIST_FIRST(head)	((head)->lh_first)
+
+#define	LIST_FOREACH(var, head, field)					\
+	for ((var) = LIST_FIRST((head));				\
+	    (var);							\
+	    (var) = LIST_NEXT((var), field))
+
+#define	LIST_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = LIST_FIRST((head));				\
+	    (var) && ((tvar) = LIST_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	LIST_INIT(head) do {						\
+	LIST_FIRST((head)) = NULL;					\
+} while (0)
+
+#define	LIST_INSERT_AFTER(listelm, elm, field) do {			\
+	QMD_LIST_CHECK_NEXT(listelm, field);				\
+	if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
+		LIST_NEXT((listelm), field)->field.le_prev =		\
+		    &LIST_NEXT((elm), field);				\
+	LIST_NEXT((listelm), field) = (elm);				\
+	(elm)->field.le_prev = &LIST_NEXT((listelm), field);		\
+} while (0)
+
+#define	LIST_INSERT_BEFORE(listelm, elm, field) do {			\
+	QMD_LIST_CHECK_PREV(listelm, field);				\
+	(elm)->field.le_prev = (listelm)->field.le_prev;		\
+	LIST_NEXT((elm), field) = (listelm);				\
+	*(listelm)->field.le_prev = (elm);				\
+	(listelm)->field.le_prev = &LIST_NEXT((elm), field);		\
+} while (0)
+
+#define	LIST_INSERT_HEAD(head, elm, field) do {				\
+	QMD_LIST_CHECK_HEAD((head), field);				\
+	if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL)	\
+		LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
+	LIST_FIRST((head)) = (elm);					\
+	(elm)->field.le_prev = &LIST_FIRST((head));			\
+} while (0)
+
+#define	LIST_NEXT(elm, field)	((elm)->field.le_next)
+
+#define	LIST_REMOVE(elm, field) do {					\
+	QMD_SAVELINK(oldnext, (elm)->field.le_next);			\
+	QMD_SAVELINK(oldprev, (elm)->field.le_prev);			\
+	QMD_LIST_CHECK_NEXT(elm, field);				\
+	QMD_LIST_CHECK_PREV(elm, field);				\
+	if (LIST_NEXT((elm), field) != NULL)				\
+		LIST_NEXT((elm), field)->field.le_prev = 		\
+		    (elm)->field.le_prev;				\
+	*(elm)->field.le_prev = LIST_NEXT((elm), field);		\
+	TRASHIT(*oldnext);						\
+	TRASHIT(*oldprev);						\
+} while (0)
+
+#define LIST_SWAP(head1, head2, type, field) do {			\
+	struct type *swap_tmp = LIST_FIRST((head1));			\
+	LIST_FIRST((head1)) = LIST_FIRST((head2));			\
+	LIST_FIRST((head2)) = swap_tmp;					\
+	if ((swap_tmp = LIST_FIRST((head1))) != NULL)			\
+		swap_tmp->field.le_prev = &LIST_FIRST((head1));		\
+	if ((swap_tmp = LIST_FIRST((head2))) != NULL)			\
+		swap_tmp->field.le_prev = &LIST_FIRST((head2));		\
+} while (0)
+
+/*
+ * Tail queue declarations.
+ */
+#define	TAILQ_HEAD(name, type)						\
+struct name {								\
+	struct type *tqh_first;	/* first element */			\
+	struct type **tqh_last;	/* addr of last next element */		\
+	TRACEBUF							\
+}
+
+#define	TAILQ_HEAD_INITIALIZER(head)					\
+	{ NULL, &(head).tqh_first }
+
+#define	TAILQ_ENTRY(type)						\
+struct {								\
+	struct type *tqe_next;	/* next element */			\
+	struct type **tqe_prev;	/* address of previous next element */	\
+	TRACEBUF							\
+}
+
+/*
+ * Tail queue functions.
+ */
+#if (defined(_KERNEL) && defined(INVARIANTS))
+#define	QMD_TAILQ_CHECK_HEAD(head, field) do {				\
+	if (!TAILQ_EMPTY(head) &&					\
+	    TAILQ_FIRST((head))->field.tqe_prev !=			\
+	     &TAILQ_FIRST((head)))					\
+		panic("Bad tailq head %p first->prev != head", (head));	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_TAIL(head, field) do {				\
+	if (*(head)->tqh_last != NULL)					\
+	    	panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); 	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_NEXT(elm, field) do {				\
+	if (TAILQ_NEXT((elm), field) != NULL &&				\
+	    TAILQ_NEXT((elm), field)->field.tqe_prev !=			\
+	     &((elm)->field.tqe_next))					\
+		panic("Bad link elm %p next->prev != elm", (elm));	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_PREV(elm, field) do {				\
+	if (*(elm)->field.tqe_prev != (elm))				\
+		panic("Bad link elm %p prev->next != elm", (elm));	\
+} while (0)
+#else
+#define	QMD_TAILQ_CHECK_HEAD(head, field)
+#define	QMD_TAILQ_CHECK_TAIL(head, headname)
+#define	QMD_TAILQ_CHECK_NEXT(elm, field)
+#define	QMD_TAILQ_CHECK_PREV(elm, field)
+#endif /* (_KERNEL && INVARIANTS) */
+
+#define	TAILQ_CONCAT(head1, head2, field) do {				\
+	if (!TAILQ_EMPTY(head2)) {					\
+		*(head1)->tqh_last = (head2)->tqh_first;		\
+		(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last;	\
+		(head1)->tqh_last = (head2)->tqh_last;			\
+		TAILQ_INIT((head2));					\
+		QMD_TRACE_HEAD(head1);					\
+		QMD_TRACE_HEAD(head2);					\
+	}								\
+} while (0)
+
+#define	TAILQ_EMPTY(head)	((head)->tqh_first == NULL)
+
+#define	TAILQ_FIRST(head)	((head)->tqh_first)
+
+#define	TAILQ_FOREACH(var, head, field)					\
+	for ((var) = TAILQ_FIRST((head));				\
+	    (var);							\
+	    (var) = TAILQ_NEXT((var), field))
+
+#define	TAILQ_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = TAILQ_FIRST((head));				\
+	    (var) && ((tvar) = TAILQ_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	TAILQ_FOREACH_REVERSE(var, head, headname, field)		\
+	for ((var) = TAILQ_LAST((head), headname);			\
+	    (var);							\
+	    (var) = TAILQ_PREV((var), headname, field))
+
+#define	TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar)	\
+	for ((var) = TAILQ_LAST((head), headname);			\
+	    (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1);	\
+	    (var) = (tvar))
+
+#define	TAILQ_INIT(head) do {						\
+	TAILQ_FIRST((head)) = NULL;					\
+	(head)->tqh_last = &TAILQ_FIRST((head));			\
+	QMD_TRACE_HEAD(head);						\
+} while (0)
+
+#define	TAILQ_INSERT_AFTER(head, listelm, elm, field) do {		\
+	QMD_TAILQ_CHECK_NEXT(listelm, field);				\
+	if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
+		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
+		    &TAILQ_NEXT((elm), field);				\
+	else {								\
+		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
+		QMD_TRACE_HEAD(head);					\
+	}								\
+	TAILQ_NEXT((listelm), field) = (elm);				\
+	(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field);		\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+	QMD_TRACE_ELEM(&listelm->field);				\
+} while (0)
+
+#define	TAILQ_INSERT_BEFORE(listelm, elm, field) do {			\
+	QMD_TAILQ_CHECK_PREV(listelm, field);				\
+	(elm)->field.tqe_prev = (listelm)->field.tqe_prev;		\
+	TAILQ_NEXT((elm), field) = (listelm);				\
+	*(listelm)->field.tqe_prev = (elm);				\
+	(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field);		\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+	QMD_TRACE_ELEM(&listelm->field);				\
+} while (0)
+
+#define	TAILQ_INSERT_HEAD(head, elm, field) do {			\
+	QMD_TAILQ_CHECK_HEAD(head, field);				\
+	if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL)	\
+		TAILQ_FIRST((head))->field.tqe_prev =			\
+		    &TAILQ_NEXT((elm), field);				\
+	else								\
+		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
+	TAILQ_FIRST((head)) = (elm);					\
+	(elm)->field.tqe_prev = &TAILQ_FIRST((head));			\
+	QMD_TRACE_HEAD(head);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define	TAILQ_INSERT_TAIL(head, elm, field) do {			\
+	QMD_TAILQ_CHECK_TAIL(head, field);				\
+	TAILQ_NEXT((elm), field) = NULL;				\
+	(elm)->field.tqe_prev = (head)->tqh_last;			\
+	*(head)->tqh_last = (elm);					\
+	(head)->tqh_last = &TAILQ_NEXT((elm), field);			\
+	QMD_TRACE_HEAD(head);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define	TAILQ_LAST(head, headname)					\
+	(*(((struct headname *)((head)->tqh_last))->tqh_last))
+
+#define	TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
+
+#define	TAILQ_PREV(elm, headname, field)				\
+	(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
+
+#define	TAILQ_REMOVE(head, elm, field) do {				\
+	QMD_SAVELINK(oldnext, (elm)->field.tqe_next);			\
+	QMD_SAVELINK(oldprev, (elm)->field.tqe_prev);			\
+	QMD_TAILQ_CHECK_NEXT(elm, field);				\
+	QMD_TAILQ_CHECK_PREV(elm, field);				\
+	if ((TAILQ_NEXT((elm), field)) != NULL)				\
+		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
+		    (elm)->field.tqe_prev;				\
+	else {								\
+		(head)->tqh_last = (elm)->field.tqe_prev;		\
+		QMD_TRACE_HEAD(head);					\
+	}								\
+	*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field);		\
+	TRASHIT(*oldnext);						\
+	TRASHIT(*oldprev);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define TAILQ_SWAP(head1, head2, type, field) do {			\
+	struct type *swap_first = (head1)->tqh_first;			\
+	struct type **swap_last = (head1)->tqh_last;			\
+	(head1)->tqh_first = (head2)->tqh_first;			\
+	(head1)->tqh_last = (head2)->tqh_last;				\
+	(head2)->tqh_first = swap_first;				\
+	(head2)->tqh_last = swap_last;					\
+	if ((swap_first = (head1)->tqh_first) != NULL)			\
+		swap_first->field.tqe_prev = &(head1)->tqh_first;	\
+	else								\
+		(head1)->tqh_last = &(head1)->tqh_first;		\
+	if ((swap_first = (head2)->tqh_first) != NULL)			\
+		swap_first->field.tqe_prev = &(head2)->tqh_first;	\
+	else								\
+		(head2)->tqh_last = &(head2)->tqh_first;		\
+} while (0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_SYS_QUEUE_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/rtc.h

@@ -0,0 +1,218 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_RTC_H_
+#define _ROM_RTC_H_
+
+#include "ets_sys.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup rtc_apis, rtc registers and memory related apis
+  * @brief rtc apis
+  */
+
+/** @addtogroup rtc_apis
+  * @{
+  */
+
+/**************************************************************************************
+  *                                       Note:                                       *
+  *       Some Rtc memory and registers are used, in ROM or in internal library.      *
+  *          Please do not use reserved or used rtc memory or registers.              *
+  *                                                                                   *
+  *************************************************************************************
+  *                          RTC  Memory & Store Register usage
+  *************************************************************************************
+  *     rtc memory addr         type    size            usage
+  *     0x3ff61000(0x50000000)  Slow    SIZE_CP         Co-Processor code/Reset Entry
+  *     0x3ff61000+SIZE_CP      Slow    4096-SIZE_CP
+  *     0x3ff62800              Slow    4096            Reserved
+  *
+  *     0x3ff80000(0x400c0000)  Fast    8192            deep sleep entry code
+  *
+  *************************************************************************************
+  *     RTC store registers     usage
+  *     RTC_CNTL_STORE0_REG     Reserved
+  *     RTC_CNTL_STORE1_REG     RTC_SLOW_CLK calibration value
+  *     RTC_CNTL_STORE2_REG     Boot time, low word
+  *     RTC_CNTL_STORE3_REG     Boot time, high word
+  *     RTC_CNTL_STORE4_REG     External XTAL frequency
+  *     RTC_CNTL_STORE5_REG     APB bus frequency
+  *     RTC_CNTL_STORE6_REG     FAST_RTC_MEMORY_ENTRY
+  *     RTC_CNTL_STORE7_REG     FAST_RTC_MEMORY_CRC
+  *************************************************************************************
+  */
+
+#define RTC_SLOW_CLK_CAL_REG    RTC_CNTL_STORE1_REG
+#define RTC_BOOT_TIME_LOW_REG   RTC_CNTL_STORE2_REG
+#define RTC_BOOT_TIME_HIGH_REG  RTC_CNTL_STORE3_REG
+#define RTC_XTAL_FREQ_REG       RTC_CNTL_STORE4_REG
+#define RTC_APB_FREQ_REG        RTC_CNTL_STORE5_REG
+#define RTC_ENTRY_ADDR_REG      RTC_CNTL_STORE6_REG
+#define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
+
+
+typedef enum {
+    AWAKE = 0,             //<CPU ON
+    LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
+    DEEP_SLEEP  = BIT1     //CPU OFF, PLL OFF, only specific timer could wake up
+} SLEEP_MODE;
+
+typedef enum {
+    NO_MEAN                =  0,
+    POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
+    SW_RESET               =  3,    /**<3, Software reset digital core*/
+    OWDT_RESET             =  4,    /**<4, Legacy watch dog reset digital core*/
+    DEEPSLEEP_RESET        =  5,    /**<3, Deep Sleep reset digital core*/
+    SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core*/
+    TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core*/
+    TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core*/
+    RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core*/
+    INTRUSION_RESET        = 10,    /**<10, Instrusion tested to reset CPU*/
+    TGWDT_CPU_RESET        = 11,    /**<11, Time Group reset CPU*/
+    SW_CPU_RESET           = 12,    /**<12, Software reset CPU*/
+    RTCWDT_CPU_RESET       = 13,    /**<13, RTC Watch dog Reset CPU*/
+    EXT_CPU_RESET          = 14,    /**<14, for APP CPU, reseted by PRO CPU*/
+    RTCWDT_BROWN_OUT_RESET = 15,    /**<15, Reset when the vdd voltage is not stable*/
+    RTCWDT_RTC_RESET       = 16     /**<16, RTC Watch dog reset digital core and rtc module*/
+} RESET_REASON;
+
+typedef enum {
+    NO_SLEEP        = 0,
+    EXT_EVENT0_TRIG = BIT0,
+    EXT_EVENT1_TRIG = BIT1,
+    GPIO_TRIG       = BIT2,
+    TIMER_EXPIRE    = BIT3,
+    SDIO_TRIG       = BIT4,
+    MAC_TRIG        = BIT5,
+    UART0_TRIG      = BIT6,
+    UART1_TRIG      = BIT7,
+    TOUCH_TRIG      = BIT8,
+    SAR_TRIG        = BIT9,
+    BT_TRIG         = BIT10
+} WAKEUP_REASON;
+
+typedef enum {
+    DISEN_WAKEUP       = NO_SLEEP,
+    EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
+    EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
+    GPIO_TRIG_EN       = GPIO_TRIG,
+    TIMER_EXPIRE_EN    = TIMER_EXPIRE,
+    SDIO_TRIG_EN       = SDIO_TRIG,
+    MAC_TRIG_EN        = MAC_TRIG,
+    UART0_TRIG_EN      = UART0_TRIG,
+    UART1_TRIG_EN      = UART1_TRIG,
+    TOUCH_TRIG_EN      = TOUCH_TRIG,
+    SAR_TRIG_EN        = SAR_TRIG,
+    BT_TRIG_EN         = BT_TRIG
+} WAKEUP_ENABLE;
+
+typedef enum {
+    NO_INT             = 0,
+    WAKEUP_INT         = BIT0,
+    REJECT_INT         = BIT1,
+    SDIO_IDLE_INT      = BIT2,
+    RTC_WDT_INT        = BIT3,
+    RTC_TIME_VALID_INT = BIT4
+} RTC_INT_REASON;
+
+typedef enum {
+    DISEN_INT             = 0,
+    WAKEUP_INT_EN         = WAKEUP_INT,
+    REJECT_INT_EN         = REJECT_INT,
+    SDIO_IDLE_INT_EN      = SDIO_IDLE_INT,
+    RTC_WDT_INT_EN        = RTC_WDT_INT,
+    RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
+} RTC_INT_EN;
+
+/**
+  * @brief  Get the reset reason for CPU.
+  *
+  * @param  int cpu_no : CPU no.
+  *
+  * @return RESET_REASON
+  */
+RESET_REASON rtc_get_reset_reason(int cpu_no);
+
+/**
+  * @brief  Get the wakeup cause for CPU.
+  *
+  * @param  int cpu_no : CPU no.
+  *
+  * @return WAKEUP_REASON
+  */
+WAKEUP_REASON rtc_get_wakeup_cause(void);
+
+/**
+  * @brief Get CRC for Fast RTC Memory.
+  *
+  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
+  *
+  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
+  *
+  * @return uint32_t : CRC32 result
+  */
+uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
+
+/**
+  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void set_rtc_memory_crc(void);
+
+/**
+  * @brief Software Reset digital core.
+  *
+  * It is not recommended to use this function in esp-idf, use
+  * esp_restart() instead.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void software_reset(void);
+
+/**
+  * @brief Software Reset digital core.
+  *
+  * It is not recommended to use this function in esp-idf, use
+  * esp_restart() instead.
+  *
+  * @param  int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
+  *
+  * @return None
+  */
+void software_reset_cpu(int cpu_no);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_RTC_H_ */
+

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/secure_boot.h

@@ -0,0 +1,46 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_SECURE_BOOT_H_
+#define _ROM_SECURE_BOOT_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void ets_secure_boot_start(void);
+
+void ets_secure_boot_finish(void);
+
+void ets_secure_boot_hash(const uint32_t *buf);
+
+void ets_secure_boot_obtain(void);
+
+int ets_secure_boot_check(uint32_t *buf);
+
+void ets_secure_boot_rd_iv(uint32_t *buf);
+
+void ets_secure_boot_rd_abstract(uint32_t *buf);
+
+bool ets_secure_boot_check_start(uint8_t abs_index, uint32_t iv_addr);
+
+int ets_secure_boot_check_finish(uint32_t *abstract);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SECURE_BOOT_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/sha.h

@@ -0,0 +1,61 @@
+/*
+  ROM functions for hardware SHA support.
+
+  It is not recommended to use these functions directly.  If using
+  them from esp-idf then use the esp_sha_lock_engine() and
+  esp_sha_lock_memory_block() functions in hwcrypto/sha.h to ensure
+  exclusive access.
+ */
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_SHA_H_
+#define _ROM_SHA_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct SHAContext {
+    bool start;
+    uint32_t total_input_bits[4];
+} SHA_CTX;
+
+enum SHA_TYPE {
+    SHA1 = 0,
+    SHA2_256,
+    SHA2_384,
+    SHA2_512,
+
+
+    SHA_INVALID = -1,
+};
+
+void ets_sha_init(SHA_CTX *ctx);
+
+void ets_sha_enable(void);
+
+void ets_sha_disable(void);
+
+void ets_sha_update(SHA_CTX *ctx, enum SHA_TYPE type, const uint8_t *input, size_t input_bits);
+
+void ets_sha_finish(SHA_CTX *ctx, enum SHA_TYPE type, uint8_t *output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SHA_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/spi_flash.h

@@ -0,0 +1,546 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_SPI_FLASH_H_
+#define _ROM_SPI_FLASH_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "esp_attr.h"
+
+#include "soc/spi_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup spi_flash_apis, spi flash operation related apis
+  * @brief spi_flash apis
+  */
+
+/** @addtogroup spi_flash_apis
+  * @{
+  */
+
+/*************************************************************
+ *                            Note
+ *************************************************************
+ * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
+ *    used as an SPI master to access Flash and ext-SRAM by
+ *    Cache module. It will support Decryto read for Flash,
+ *    read/write for ext-SRAM. And SPI1 is also used as an
+ *    SPI master for Flash read/write and ext-SRAM read/write.
+ *    It will support Encrypto write for Flash.
+ * 2. As an SPI master, SPI support Highest clock to 80M,
+ *    however, Flash with 80M Clock should be configured
+ *    for different Flash chips. If you want to use 80M
+ *    clock We should use the SPI that is certified by
+ *    Espressif. However, the certification is not started
+ *    at the time, so please use 40M clock at the moment.
+ * 3. SPI Flash can use 2 lines or 4 lines mode. If you
+ *    use 2 lines mode, you can save two pad SPIHD and
+ *    SPIWP for gpio. ESP32 support configured SPI pad for
+ *    Flash, the configuration is stored in efuse and flash.
+ *    However, the configurations of pads should be certified
+ *    by Espressif. If you use this function, please use 40M
+ *    clock at the moment.
+ * 4. ESP32 support to use Common SPI command to configure
+ *    Flash to QIO mode, if you failed to configure with fix
+ *    command. With Common SPI Command, ESP32 can also provide
+ *    a way to use same Common SPI command groups on different
+ *    Flash chips.
+ * 5. This functions are not protected by packeting, Please use the
+ *************************************************************
+ */
+
+#define PERIPHS_SPI_FLASH_CMD                 SPI_CMD_REG(1)
+#define PERIPHS_SPI_FLASH_ADDR                SPI_ADDR_REG(1)
+#define PERIPHS_SPI_FLASH_CTRL                SPI_CTRL_REG(1)
+#define PERIPHS_SPI_FLASH_CTRL1               SPI_CTRL1_REG(1)
+#define PERIPHS_SPI_FLASH_STATUS              SPI_RD_STATUS_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG              SPI_USER_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG1             SPI_USER1_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG2             SPI_USER2_REG(1)
+#define PERIPHS_SPI_FLASH_C0                  SPI_W0_REG(1)
+#define PERIPHS_SPI_FLASH_C1                  SPI_W1_REG(1)
+#define PERIPHS_SPI_FLASH_C2                  SPI_W2_REG(1)
+#define PERIPHS_SPI_FLASH_C3                  SPI_W3_REG(1)
+#define PERIPHS_SPI_FLASH_C4                  SPI_W4_REG(1)
+#define PERIPHS_SPI_FLASH_C5                  SPI_W5_REG(1)
+#define PERIPHS_SPI_FLASH_C6                  SPI_W6_REG(1)
+#define PERIPHS_SPI_FLASH_C7                  SPI_W7_REG(1)
+#define PERIPHS_SPI_FLASH_TX_CRC              SPI_TX_CRC_REG(1)
+
+#define SPI0_R_QIO_DUMMY_CYCLELEN             3
+#define SPI0_R_QIO_ADDR_BITSLEN               31
+#define SPI0_R_FAST_DUMMY_CYCLELEN            7
+#define SPI0_R_DIO_DUMMY_CYCLELEN             3
+#define SPI0_R_FAST_ADDR_BITSLEN              23
+#define SPI0_R_SIO_ADDR_BITSLEN               23
+
+#define SPI1_R_QIO_DUMMY_CYCLELEN             3
+#define SPI1_R_QIO_ADDR_BITSLEN               31
+#define SPI1_R_FAST_DUMMY_CYCLELEN            7
+#define SPI1_R_DIO_DUMMY_CYCLELEN             3
+#define SPI1_R_DIO_ADDR_BITSLEN               31
+#define SPI1_R_FAST_ADDR_BITSLEN              23
+#define SPI1_R_SIO_ADDR_BITSLEN               23
+
+#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN   23
+
+#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN   SPI_WRSR_2B
+
+//SPI address register
+#define ESP_ROM_SPIFLASH_BYTES_LEN            24
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM  32
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM   64
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS  0x3f
+
+//SPI status register
+#define  ESP_ROM_SPIFLASH_BUSY_FLAG           BIT0
+#define  ESP_ROM_SPIFLASH_WRENABLE_FLAG       BIT1
+#define  ESP_ROM_SPIFLASH_BP0                 BIT2
+#define  ESP_ROM_SPIFLASH_BP1                 BIT3
+#define  ESP_ROM_SPIFLASH_BP2                 BIT4
+#define  ESP_ROM_SPIFLASH_WR_PROTECT          (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
+#define  ESP_ROM_SPIFLASH_QE                  BIT9
+
+typedef enum {
+    ESP_ROM_SPIFLASH_QIO_MODE = 0,
+    ESP_ROM_SPIFLASH_QOUT_MODE,
+    ESP_ROM_SPIFLASH_DIO_MODE,
+    ESP_ROM_SPIFLASH_DOUT_MODE,
+    ESP_ROM_SPIFLASH_FASTRD_MODE,
+    ESP_ROM_SPIFLASH_SLOWRD_MODE
+} esp_rom_spiflash_read_mode_t;
+
+typedef enum {
+    ESP_ROM_SPIFLASH_RESULT_OK,
+    ESP_ROM_SPIFLASH_RESULT_ERR,
+    ESP_ROM_SPIFLASH_RESULT_TIMEOUT
+} esp_rom_spiflash_result_t;
+
+typedef struct {
+    uint32_t device_id;
+    uint32_t chip_size;    // chip size in bytes
+    uint32_t block_size;
+    uint32_t sector_size;
+    uint32_t page_size;
+    uint32_t status_mask;
+} esp_rom_spiflash_chip_t;
+
+typedef struct {
+    uint8_t  data_length;
+    uint8_t  read_cmd0;
+    uint8_t  read_cmd1;
+    uint8_t  write_cmd;
+    uint16_t data_mask;
+    uint16_t data;
+} esp_rom_spiflash_common_cmd_t;
+
+/**
+  * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
+  *
+  * @param  uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
+  *
+  * @return None
+  */
+void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
+
+/**
+  * @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint8_t wp_gpio_num: WP gpio number.
+  *
+  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+  *
+  * @return None
+  */
+void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
+
+/**
+  * @brief Set SPI Flash pad drivers.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint8_t wp_gpio_num: WP gpio number.
+  *
+  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+  *
+  * @param  uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
+  *            drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
+  *                        Values usually read from falsh by rom code, function usually callde by rom code.
+  *                        if value with bit(3) set, the value is valid, bit[2:0] is the real value.
+  *
+  * @return None
+  */
+void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
+
+/**
+  * @brief Select SPI Flash function for pads.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+  *
+  * @return None
+  */
+void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
+
+/**
+  * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+  *
+  * @param  uint8_t legacy: In legacy mode, more SPI command is used in line.
+  *
+  * @return None
+  */
+void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
+
+/**
+  * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
+  *    Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t *status : The pointer to which to return the Flash status value.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
+
+/**
+  * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t *status : The pointer to which to return the Flash status value.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
+
+/**
+  * @brief Write status to Falsh status register.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t status_value : Value to .
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : write error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
+
+/**
+  * @brief Use a command to Read Flash status register.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t*status : The pointer to which to return the Flash status value.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
+
+/**
+  * @brief Config SPI Flash read mode when init.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
+  *
+  * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : config error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
+
+/**
+  * @brief Config SPI Flash clock divisor.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t freqdiv: clock divisor.
+  *
+  * @param  uint8_t spi: 0 for SPI0, 1 for SPI1.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : config error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
+
+/**
+  * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
+  *
+  * @return uint16_t  0 : do not send command any more.
+  *                   1 : go to the next command.
+  *                   n > 1 : skip (n - 1) commands.
+  */
+uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
+
+/**
+  * @brief Unlock SPI write protect.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
+
+/**
+  * @brief SPI write protect.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Lock error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
+
+/**
+  * @brief Update SPI Flash parameter.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t deviceId : Device ID read from SPI, the low 32 bit.
+  *
+  * @param  uint32_t chip_size : The Flash size.
+  *
+  * @param  uint32_t block_size : The Flash block size.
+  *
+  * @param  uint32_t sector_size : The Flash sector size.
+  *
+  * @param  uint32_t page_size : The Flash page size.
+  *
+  * @param  uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, 
+                                                        uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
+
+/**
+  * @brief Erase whole flash chip.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
+
+/**
+  * @brief Erase a 64KB block of flash
+  *        Uses SPI flash command D8H.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t block_num : Which block to erase.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
+
+/**
+  * @brief Erase a sector of flash.
+  *        Uses SPI flash command 20H.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t sector_num : Which sector to erase.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
+
+/**
+  * @brief Erase some sectors.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t start_addr : Start addr to erase, should be sector aligned.
+  *
+  * @param  uint32_t area_len : Length to erase, should be sector aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
+
+/**
+  * @brief Write Data to Flash, you should Erase it yourself if need.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t dest_addr : Address to write, should be 4 bytes aligned.
+  *
+  * @param  const uint32_t *src : The pointer to data which is to write.
+  *
+  * @param  uint32_t len : Length to write, should be 4 bytes aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
+
+/**
+  * @brief Read Data from Flash, you should Erase it yourself if need.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t src_addr : Address to read, should be 4 bytes aligned.
+  *
+  * @param  uint32_t *dest : The buf to read the data.
+  *
+  * @param  uint32_t len : Length to read, should be 4 bytes aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
+
+/**
+  * @brief SPI1 go into encrypto mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void esp_rom_spiflash_write_encrypted_enable(void);
+
+/**
+  * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t flash_addr : Address to write, should be 32 bytes aligned.
+  *
+  * @param  uint32_t *data : The pointer to data which is to write.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data);
+
+/**
+  * @brief SPI1 go out of encrypto mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void esp_rom_spiflash_write_encrypted_disable(void);
+
+/**
+  * @brief Write data to flash with transparent encryption.
+  * @note Sectors to be written should already be erased.
+  *
+  * @note Please do not call this function in SDK.
+  *
+  * @param  uint32_t flash_addr : Address to write, should be 32 byte aligned.
+  *
+  * @param  uint32_t *data : The pointer to data to write. Note, this pointer must
+  *                          be 32 bit aligned and the content of the data will be
+  *                          modified by the encryption function.
+  *
+  * @param  uint32_t len : Length to write, should be 32 bytes aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
+
+
+/** @brief Wait until SPI flash write operation is complete
+ *
+ * @note Please do not call this function in SDK.
+ *
+ * Reads the Write In Progress bit of the SPI flash status register,
+ * repeats until this bit is zero (indicating write complete).
+ *
+ * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
+ *         ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
+ */
+esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
+
+
+/** @brief Enable Quad I/O pin functions
+ *
+ * @note Please do not call this function in SDK.
+ *
+ * Sets the HD & WP pin functions for Quad I/O modes, based on the
+ * efuse SPI pin configuration.
+ *
+ * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
+ *
+ * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
+ * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
+ * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
+ * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
+ *   to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
+ *   Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
+ */
+void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
+
+/** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions
+ *
+ */
+extern esp_rom_spiflash_chip_t g_rom_flashchip;
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SPI_FLASH_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/tbconsole.h

@@ -0,0 +1,27 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _ROM_TBCONSOLE_H_
+#define _ROM_TBCONSOLE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void start_tb_console();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_TBCONSOLE_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/tjpgd.h

@@ -0,0 +1,99 @@
+/*----------------------------------------------------------------------------/
+/ TJpgDec - Tiny JPEG Decompressor include file               (C)ChaN, 2012
+/----------------------------------------------------------------------------*/
+#ifndef _TJPGDEC
+#define _TJPGDEC
+/*---------------------------------------------------------------------------*/
+/* System Configurations */
+
+#define	JD_SZBUF		512	/* Size of stream input buffer */
+#define JD_FORMAT		0	/* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
+#define	JD_USE_SCALE	1	/* Use descaling feature for output */
+#define JD_TBLCLIP		1	/* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
+
+/*---------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types must be 8-bit integer */
+typedef char			CHAR;
+typedef unsigned char	UCHAR;
+typedef unsigned char	BYTE;
+
+/* These types must be 16-bit integer */
+typedef short			SHORT;
+typedef unsigned short	USHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long			LONG;
+typedef unsigned long	ULONG;
+typedef unsigned long	DWORD;
+
+
+/* Error code */
+typedef enum {
+	JDR_OK = 0,	/* 0: Succeeded */
+	JDR_INTR,	/* 1: Interrupted by output function */	
+	JDR_INP,	/* 2: Device error or wrong termination of input stream */
+	JDR_MEM1,	/* 3: Insufficient memory pool for the image */
+	JDR_MEM2,	/* 4: Insufficient stream input buffer */
+	JDR_PAR,	/* 5: Parameter error */
+	JDR_FMT1,	/* 6: Data format error (may be damaged data) */
+	JDR_FMT2,	/* 7: Right format but not supported */
+	JDR_FMT3	/* 8: Not supported JPEG standard */
+} JRESULT;
+
+
+
+/* Rectangular structure */
+typedef struct {
+	WORD left, right, top, bottom;
+} JRECT;
+
+
+
+/* Decompressor object structure */
+typedef struct JDEC JDEC;
+struct JDEC {
+	UINT dctr;				/* Number of bytes available in the input buffer */
+	BYTE* dptr;				/* Current data read ptr */
+	BYTE* inbuf;			/* Bit stream input buffer */
+	BYTE dmsk;				/* Current bit in the current read byte */
+	BYTE scale;				/* Output scaling ratio */
+	BYTE msx, msy;			/* MCU size in unit of block (width, height) */
+	BYTE qtid[3];			/* Quantization table ID of each component */
+	SHORT dcv[3];			/* Previous DC element of each component */
+	WORD nrst;				/* Restart inverval */
+	UINT width, height;		/* Size of the input image (pixel) */
+	BYTE* huffbits[2][2];	/* Huffman bit distribution tables [id][dcac] */
+	WORD* huffcode[2][2];	/* Huffman code word tables [id][dcac] */
+	BYTE* huffdata[2][2];	/* Huffman decoded data tables [id][dcac] */
+	LONG* qttbl[4];			/* Dequaitizer tables [id] */
+	void* workbuf;			/* Working buffer for IDCT and RGB output */
+	BYTE* mcubuf;			/* Working buffer for the MCU */
+	void* pool;				/* Pointer to available memory pool */
+	UINT sz_pool;			/* Size of momory pool (bytes available) */
+	UINT (*infunc)(JDEC*, BYTE*, UINT);/* Pointer to jpeg stream input function */
+	void* device;			/* Pointer to I/O device identifiler for the session */
+};
+
+
+
+/* TJpgDec API functions */
+JRESULT jd_prepare (JDEC*, UINT(*)(JDEC*,BYTE*,UINT), void*, UINT, void*);
+JRESULT jd_decomp (JDEC*, UINT(*)(JDEC*,void*,JRECT*), BYTE);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TJPGDEC */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/rom/uart.h

@@ -0,0 +1,419 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ROM_UART_H_
+#define _ROM_UART_H_
+
+#include "esp_types.h"
+#include "esp_attr.h"
+#include "ets_sys.h"
+#include "soc/soc.h"
+#include "soc/uart_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup uart_apis, uart configuration and communication related apis
+  * @brief uart apis
+  */
+
+/** @addtogroup uart_apis
+  * @{
+  */
+
+#define RX_BUFF_SIZE                     0x100
+#define TX_BUFF_SIZE                     100
+
+//uart int enalbe register ctrl bits
+#define UART_RCV_INTEN                   BIT0
+#define UART_TRX_INTEN                   BIT1
+#define UART_LINE_STATUS_INTEN           BIT2
+
+//uart int identification ctrl bits
+#define UART_INT_FLAG_MASK               0x0E
+
+//uart fifo ctrl bits
+#define UART_CLR_RCV_FIFO                BIT1
+#define UART_CLR_TRX_FIFO                BIT2
+#define UART_RCVFIFO_TRG_LVL_BITS        BIT6
+
+//uart line control bits
+#define  UART_DIV_LATCH_ACCESS_BIT       BIT7
+
+//uart line status bits
+#define  UART_RCV_DATA_RDY_FLAG          BIT0
+#define  UART_RCV_OVER_FLOW_FLAG         BIT1
+#define  UART_RCV_PARITY_ERR_FLAG        BIT2
+#define  UART_RCV_FRAME_ERR_FLAG         BIT3
+#define  UART_BRK_INT_FLAG               BIT4
+#define  UART_TRX_FIFO_EMPTY_FLAG        BIT5
+#define  UART_TRX_ALL_EMPTY_FLAG         BIT6   // include fifo and shift reg
+#define  UART_RCV_ERR_FLAG               BIT7
+
+//send and receive message frame head
+#define FRAME_FLAG                       0x7E
+
+typedef enum {
+    UART_LINE_STATUS_INT_FLAG  = 0x06,
+    UART_RCV_FIFO_INT_FLAG     = 0x04,
+    UART_RCV_TMOUT_INT_FLAG    = 0x0C,
+    UART_TXBUFF_EMPTY_INT_FLAG = 0x02
+} UartIntType;   //consider bit0 for int_flag
+
+typedef enum {
+    RCV_ONE_BYTE      = 0x0,
+    RCV_FOUR_BYTE     = 0x1,
+    RCV_EIGHT_BYTE    = 0x2,
+    RCV_FOURTEEN_BYTE = 0x3
+} UartRcvFifoTrgLvl;
+
+typedef enum {
+    FIVE_BITS  = 0x0,
+    SIX_BITS   = 0x1,
+    SEVEN_BITS = 0x2,
+    EIGHT_BITS = 0x3
+} UartBitsNum4Char;
+
+typedef enum {
+    ONE_STOP_BIT      = 1,
+    ONE_HALF_STOP_BIT = 2,
+    TWO_STOP_BIT      = 3
+} UartStopBitsNum;
+
+typedef enum {
+    NONE_BITS = 0,
+    ODD_BITS  = 2,
+    EVEN_BITS = 3
+
+} UartParityMode;
+
+typedef enum {
+    STICK_PARITY_DIS = 0,
+    STICK_PARITY_EN  = 2
+} UartExistParity;
+
+typedef enum {
+    BIT_RATE_9600   = 9600,
+    BIT_RATE_19200  = 19200,
+    BIT_RATE_38400  = 38400,
+    BIT_RATE_57600  = 57600,
+    BIT_RATE_115200 = 115200,
+    BIT_RATE_230400 = 230400,
+    BIT_RATE_460800 = 460800,
+    BIT_RATE_921600 = 921600
+} UartBautRate;
+
+typedef enum {
+    NONE_CTRL,
+    HARDWARE_CTRL,
+    XON_XOFF_CTRL
+} UartFlowCtrl;
+
+typedef enum {
+    EMPTY,
+    UNDER_WRITE,
+    WRITE_OVER
+} RcvMsgBuffState;
+
+typedef struct {
+//    uint32_t     RcvBuffSize;
+    uint8_t *pRcvMsgBuff;
+    uint8_t *pWritePos;
+    uint8_t *pReadPos;
+    uint8_t  TrigLvl;
+    RcvMsgBuffState BuffState;
+} RcvMsgBuff;
+
+typedef struct {
+    uint32_t  TrxBuffSize;
+    uint8_t  *pTrxBuff;
+} TrxMsgBuff;
+
+typedef enum {
+    BAUD_RATE_DET,
+    WAIT_SYNC_FRM,
+    SRCH_MSG_HEAD,
+    RCV_MSG_BODY,
+    RCV_ESC_CHAR,
+} RcvMsgState;
+
+typedef struct {
+    UartBautRate     baut_rate;
+    UartBitsNum4Char data_bits;
+    UartExistParity  exist_parity;
+    UartParityMode   parity;    // chip size in byte
+    UartStopBitsNum  stop_bits;
+    UartFlowCtrl     flow_ctrl;
+    uint8_t          buff_uart_no;  //indicate which uart use tx/rx buffer
+    uint8_t          tx_uart_no;
+    RcvMsgBuff       rcv_buff;
+//    TrxMsgBuff       trx_buff;
+    RcvMsgState      rcv_state;
+    int              received;
+} UartDevice;
+
+/**
+  * @brief Init uart device struct value and reset uart0/uart1 rx.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void uartAttach(void);
+
+/**
+  * @brief Init uart0 or uart1 for UART download booting mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, else for UART1.
+  *
+  * @param  uint32_t clock : clock used by uart module, to adjust baudrate.
+  *
+  * @return None
+  */
+void Uart_Init(uint8_t uart_no, uint32_t clock);
+
+/**
+  * @brief Modify uart baudrate.
+  *        This function will reset RX/TX fifo for uart.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @param  uint32_t DivLatchValue : (clock << 4)/baudrate.
+  *
+  * @return None
+  */
+void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
+
+/**
+  * @brief Init uart0 or uart1 for UART download booting mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @param  uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected;
+  *                           1, two UART modules, hard to detect, detect and return.
+  *
+  * @return None
+  */
+int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync);
+
+/**
+  * @brief Switch printf channel of uart_tx_one_char.
+  *        Please do not call this function when printf.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @return None
+  */
+void uart_tx_switch(uint8_t uart_no);
+
+/**
+  * @brief Switch message exchange channel for UART download booting.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @return None
+  */
+void uart_buff_switch(uint8_t uart_no);
+
+/**
+  * @brief Output a char to printf channel, wait until fifo not full.
+  *
+  * @param  None
+  *
+  * @return OK.
+  */
+STATUS uart_tx_one_char(uint8_t TxChar);
+
+/**
+  * @brief Output a char to message exchange channel, wait until fifo not full.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return OK.
+  */
+STATUS uart_tx_one_char2(uint8_t TxChar);//for send message
+
+/**
+  * @brief Wait until uart tx full empty.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @return None.
+  */
+void uart_tx_flush(uint8_t uart_no);
+
+/**
+  * @brief Wait until uart tx full empty and the last char send ok.
+  *
+  * @param  uart_no : 0 for UART0, 1 for UART1, 2 for UART2
+  *
+  * The function defined in ROM code has a bug, so we define the correct version
+  * here for compatibility.
+  */
+static inline void IRAM_ATTR uart_tx_wait_idle(uint8_t uart_no) {
+    while(REG_GET_FIELD(UART_STATUS_REG(uart_no), UART_ST_UTX_OUT)) {
+        ;
+    }
+}
+
+/**
+  * @brief Get an input char from message channel.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pRxChar : the pointer to store the char.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+STATUS uart_rx_one_char(uint8_t *pRxChar);
+
+/**
+  * @brief Get an input char to message channel, wait until successful.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return char : input char value.
+  */
+char uart_rx_one_char_block(void);
+
+/**
+  * @brief Get an input string line from message channel.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pString : the pointer to store the string.
+  *
+  * @param  uint8_t MaxStrlen : the max string length, incude '\0'.
+  *
+  * @return OK.
+  */
+STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
+
+/**
+  * @brief Process uart recevied information in the interrupt handler.
+  *        Please do not call this function in SDK.
+  *
+  * @param  void *para : the message receive buffer.
+  *
+  * @return None
+  */
+void uart_rx_intr_handler(void *para);
+
+/**
+  * @brief Get an char from receive buffer.
+  *        Please do not call this function in SDK.
+  *
+  * @param  RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
+  *
+  * @param  uint8_t *pRxByte : the pointer to store the char.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
+
+/**
+  * @brief Get all chars from receive buffer.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pCmdLn : the pointer to store the string.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+STATUS UartGetCmdLn(uint8_t *pCmdLn);
+
+/**
+  * @brief Get uart configuration struct.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return UartDevice * : uart configuration struct pointer.
+  */
+UartDevice *GetUartDevice(void);
+
+/**
+  * @brief Send an packet to download tool, with SLIP escaping.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *p : the pointer to output string.
+  *
+  * @param  int len : the string length.
+  *
+  * @return None.
+  */
+void send_packet(uint8_t *p, int len);
+
+/**
+  * @brief Receive an packet from download tool, with SLIP escaping.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *p : the pointer to input string.
+  *
+  * @param  int len : If string length > len, the string will be truncated.
+  *
+  * @param  uint8_t is_sync : 0, only one UART module;
+  *                           1, two UART modules.
+  *
+  * @return int : the length of the string.
+  */
+int recv_packet(uint8_t *p, int len, uint8_t is_sync);
+
+/**
+  * @brief Send an packet to download tool, with SLIP escaping.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pData : the pointer to input string.
+  *
+  * @param  uint16_t DataLen : the string length.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
+
+/**
+  * @brief Receive an packet from download tool, with SLIP escaping.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pData : the pointer to input string.
+  *
+  * @param  uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated.
+  *
+  * @param  uint8_t is_sync : 0, only one UART module;
+  *                           1, two UART modules.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync);
+
+extern UartDevice UartDev;
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_UART_H_ */

Living_SDK/platform/mcu/esp32/bsp/include/esp32/include/xtensa/board.h

@@ -0,0 +1,28 @@
+/*  This header is supposed to be obtained from <board>/xtensa/board.h
+    using a -I directive passed to the compiler.  */
+
+#error "Unspecified board.  Missing -I directive to select supported Xtensa board, usually -I XTENSA_TOOLS_ROOT/xtensa-elf/include/xtensa/<BOARD> (XTENSA_TOOLS_ROOT is root of Xtensa Tools install, see xt-run --show-config=xttools)"
+
+/*
+ * Copyright (c) 2013 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+