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rel_1.6.0 init

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guocheng.kgc 2020-06-18 20:06:52 +08:00 • committed by shengdong.dsd
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66
Living_SDK/platform/mcu/es8p508x/HRSDK_GDB_ES8P508x/helloworld/hook_impl.c Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <k_api.h>
#include <stdio.h>
#include <aos/aos.h>
void soc_hw_timer_init()
{
}
#if (RHINO_CONFIG_USER_HOOK > 0)
void krhino_idle_hook(void)
{
}
void krhino_init_hook(void)
{
#if (RHINO_CONFIG_HW_COUNT > 0)
soc_hw_timer_init();
#endif
}
#endif
void krhino_start_hook(void)
{
#if (RHINO_CONFIG_TASK_SCHED_STATS > 0)
krhino_task_sched_stats_reset();
#endif
}
void krhino_task_create_hook(ktask_t *task)
{
#if XCHAL_CP_NUM > 0
krhino_task_info_set(task, 0, (void *)((uint32_t)task->task_stack + XT_STK_FRMSZ));
#endif
}
void krhino_task_del_hook(ktask_t *task, res_free_t *arg)
{
printf("%s del success!\n\r", task->task_name);
}
void krhino_task_switch_hook(ktask_t *orgin, ktask_t *dest)
{
(void)orgin;
(void)dest;
}
void krhino_tick_hook(void)
{
}
void krhino_task_abort_hook(ktask_t *task)
{
(void)task;
}
void krhino_mm_alloc_hook(void *mem, size_t size)
{
(void)mem;
(void)size;
}

29
Living_SDK/platform/mcu/es8p508x/HRSDK_GDB_ES8P508x/helloworld/irqhandler.c Normal file
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#include "irqhandler.h"
#include "k_api.h"
void NMI_Handler(void)
{
}
void HardFault_Handler(void)
{
while(1)
{
}
}
void SVC_Handler(void)
{
}
void SysTick_Handler(void)
{
krhino_intrpt_enter();
krhino_tick_proc();
krhino_intrpt_exit();
}

15
Living_SDK/platform/mcu/es8p508x/HRSDK_GDB_ES8P508x/helloworld/irqhandler.h Normal file
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#ifndef __IRQHANDLER_H__
#define __IRQHANDLER_H__
#include "ES8P508x.h"
void NMI_Handler(void);
void HardFault_Handler(void);
void SVC_Handler(void);
void PendSV_Handler(void);
void SysTick_Handler(void);
#endif

250
Living_SDK/platform/mcu/es8p508x/HRSDK_GDB_ES8P508x/helloworld/k_config.h Normal file
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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef CONFIG_H
#define CONFIG_H
/* chip level conf */
#ifndef RHINO_CONFIG_LITTLE_ENDIAN
#define RHINO_CONFIG_LITTLE_ENDIAN 1
#endif
#ifndef RHINO_CONFIG_CPU_STACK_DOWN
#define RHINO_CONFIG_CPU_STACK_DOWN 1
#endif
/* kernel feature conf */
#ifndef RHINO_CONFIG_SEM
#define RHINO_CONFIG_SEM 1
#endif
#ifndef RHINO_CONFIG_QUEUE
#define RHINO_CONFIG_QUEUE 1
#endif
#ifndef RHINO_CONFIG_TASK_SEM
#define RHINO_CONFIG_TASK_SEM 0
#endif
#ifndef RHINO_CONFIG_EVENT_FLAG
#define RHINO_CONFIG_EVENT_FLAG 0
#endif
#ifndef RHINO_CONFIG_TIMER
#define RHINO_CONFIG_TIMER 0
#endif
#ifndef RHINO_CONFIG_BUF_QUEUE
#define RHINO_CONFIG_BUF_QUEUE 0
#endif
#ifndef RHINO_CONFIG_MM_BLK
#define RHINO_CONFIG_MM_BLK 1
#endif
#ifndef RHINO_CONFIG_MM_DEBUG
#define RHINO_CONFIG_MM_DEBUG 1
#endif
#ifndef RHINO_CONFIG_MM_TLF
#define RHINO_CONFIG_MM_TLF 0
#endif
#ifndef RHINO_CONFIG_MM_TLF_BLK_SIZE
#define RHINO_CONFIG_MM_TLF_BLK_SIZE 8192
#endif
#define K_MM_STATISTIC 0
#ifndef RHINO_CONFIG_MM_MAXMSIZEBIT
#define RHINO_CONFIG_MM_MAXMSIZEBIT 19
#endif
#ifndef RHINO_CONFIG_GCC_RETADDR
#define RHINO_CONFIG_GCC_RETADDR 0
#endif
#ifndef RHINO_CONFIG_MM_LEAKCHECK
#define RHINO_CONFIG_MM_LEAKCHECK 0
#endif
#ifndef RHINO_CONFIG_RINGBUF_VENDOR
#define RHINO_CONFIG_RINGBUF_VENDOR 0
#endif
#ifndef RHINO_CONFIG_KOBJ_SET
#define RHINO_CONFIG_KOBJ_SET 0
#endif
/* kernel task conf */
#ifndef RHINO_CONFIG_TASK_SUSPEND
#define RHINO_CONFIG_TASK_SUSPEND 1
#endif
#ifndef RHINO_CONFIG_TASK_INFO
#define RHINO_CONFIG_TASK_INFO 0
#endif
#ifndef RHINO_CONFIG_TASK_DEL
#define RHINO_CONFIG_TASK_DEL 1
#endif
#ifndef RHINO_CONFIG_TASK_STACK_CUR_CHECK
#define RHINO_CONFIG_TASK_STACK_CUR_CHECK 0
#endif
#ifndef RHINO_CONFIG_TASK_WAIT_ABORT
#define RHINO_CONFIG_TASK_WAIT_ABORT 0
#endif
#ifndef RHINO_CONFIG_TASK_STACK_OVF_CHECK
#define RHINO_CONFIG_TASK_STACK_OVF_CHECK 1
#endif
#ifndef RHINO_CONFIG_SCHED_RR
#define RHINO_CONFIG_SCHED_RR 1
#endif
#ifndef RHINO_CONFIG_TIME_SLICE_DEFAULT
#define RHINO_CONFIG_TIME_SLICE_DEFAULT 50
#endif
#ifndef RHINO_CONFIG_PRI_MAX
#define RHINO_CONFIG_PRI_MAX 62
#endif
#ifndef RHINO_CONFIG_USER_PRI_MAX
#define RHINO_CONFIG_USER_PRI_MAX (RHINO_CONFIG_PRI_MAX - 2)
#endif
/* kernel workqueue conf */
#ifndef RHINO_CONFIG_WORKQUEUE
#define RHINO_CONFIG_WORKQUEUE 0
#endif
#ifndef RHINO_CONFIG_WORKQUEUE_STACK_SIZE
#define RHINO_CONFIG_WORKQUEUE_STACK_SIZE 768
#endif
/* kernel mm_region conf */
#ifndef RHINO_CONFIG_MM_REGION_MUTEX
#define RHINO_CONFIG_MM_REGION_MUTEX 0
#endif
/* kernel timer&tick conf */
#ifndef RHINO_CONFIG_HW_COUNT
#define RHINO_CONFIG_HW_COUNT 0
#endif
#ifndef RHINO_CONFIG_TICK_TASK
#define RHINO_CONFIG_TICK_TASK 0
#endif
#if (RHINO_CONFIG_TICK_TASK > 0)
#ifndef RHINO_CONFIG_TICK_TASK_STACK_SIZE
#define RHINO_CONFIG_TICK_TASK_STACK_SIZE 256
#endif
#ifndef RHINO_CONFIG_TICK_TASK_PRI
#define RHINO_CONFIG_TICK_TASK_PRI 1
#endif
#endif
#ifndef RHINO_CONFIG_TICKLESS
#define RHINO_CONFIG_TICKLESS 0
#endif
#ifndef RHINO_CONFIG_TICKS_PER_SECOND
#define RHINO_CONFIG_TICKS_PER_SECOND 100
#endif
/* must be 2^n size!, such as 1, 2, 4, 8, 16,32, etc....... */
#ifndef RHINO_CONFIG_TICK_HEAD_ARRAY
#define RHINO_CONFIG_TICK_HEAD_ARRAY 8
#endif
/*must reserve enough stack size for timer cb will consume*/
#ifndef RHINO_CONFIG_TIMER_TASK_STACK_SIZE
#define RHINO_CONFIG_TIMER_TASK_STACK_SIZE 300
#endif
#ifndef RHINO_CONFIG_TIMER_RATE
#define RHINO_CONFIG_TIMER_RATE 1
#endif
#ifndef RHINO_CONFIG_TIMER_TASK_PRI
#define RHINO_CONFIG_TIMER_TASK_PRI 5
#endif
/* kernel intrpt conf */
#ifndef RHINO_CONFIG_INTRPT_STACK_REMAIN_GET
#define RHINO_CONFIG_INTRPT_STACK_REMAIN_GET 0
#endif
#ifndef RHINO_CONFIG_INTRPT_STACK_OVF_CHECK
#define RHINO_CONFIG_INTRPT_STACK_OVF_CHECK 0
#endif
#ifndef RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL
#define RHINO_CONFIG_INTRPT_MAX_NESTED_LEVEL 188u
#endif
#ifndef RHINO_CONFIG_INTRPT_GUARD
#define RHINO_CONFIG_INTRPT_GUARD 0
#endif
/* kernel dyn alloc conf */
#ifndef RHINO_CONFIG_KOBJ_DYN_ALLOC
#define RHINO_CONFIG_KOBJ_DYN_ALLOC 0
#endif
#if (RHINO_CONFIG_KOBJ_DYN_ALLOC > 0)
#ifndef RHINO_CONFIG_K_DYN_QUEUE_MSG
#define RHINO_CONFIG_K_DYN_QUEUE_MSG 30
#endif
#ifndef RHINO_CONFIG_K_DYN_TASK_STACK
#define RHINO_CONFIG_K_DYN_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_K_DYN_MEM_TASK_PRI
#define RHINO_CONFIG_K_DYN_MEM_TASK_PRI 6
#endif
#endif
/* kernel idle conf */
#ifndef RHINO_CONFIG_IDLE_TASK_STACK_SIZE
#define RHINO_CONFIG_IDLE_TASK_STACK_SIZE 200
#endif
/* kernel hook conf */
#ifndef RHINO_CONFIG_USER_HOOK
#define RHINO_CONFIG_USER_HOOK 1
#endif
/* kernel stats conf */
#ifndef RHINO_CONFIG_SYSTEM_STATS
#define RHINO_CONFIG_SYSTEM_STATS 1
#endif
#ifndef RHINO_CONFIG_DISABLE_SCHED_STATS
#define RHINO_CONFIG_DISABLE_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_DISABLE_INTRPT_STATS
#define RHINO_CONFIG_DISABLE_INTRPT_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_STATS
#define RHINO_CONFIG_CPU_USAGE_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_PRI
#define RHINO_CONFIG_CPU_USAGE_TASK_PRI (RHINO_CONFIG_PRI_MAX - 2)
#endif
#ifndef RHINO_CONFIG_TASK_SCHED_STATS
#define RHINO_CONFIG_TASK_SCHED_STATS 0
#endif
#ifndef RHINO_CONFIG_CPU_USAGE_TASK_STACK
#define RHINO_CONFIG_CPU_USAGE_TASK_STACK 256
#endif
#ifndef RHINO_CONFIG_CPU_NUM
#define RHINO_CONFIG_CPU_NUM 1
#endif
/* kernel trace conf */
#ifndef RHINO_CONFIG_TRACE
#define RHINO_CONFIG_TRACE 0
#endif
#if ((RHINO_CONFIG_MM_TLF >= 1) && (RHINO_CONFIG_MM_BLK == 0))
#error "RHINO_CONFIG_MM_BLK should be 1 when RHINO_CONFIG_MM_TLF is enabled."
#endif
#if ((RHINO_CONFIG_KOBJ_DYN_ALLOC >= 1) && (RHINO_CONFIG_MM_TLF == 0))
#error "RHINO_CONFIG_MM_TLF should be 1 when RHINO_CONFIG_KOBJ_DYN_ALLOC is enabled."
#endif
#if (RHINO_CONFIG_PRI_MAX >= 256)
#error "RHINO_CONFIG_PRI_MAX must be <= 255."
#endif
#if ((RHINO_CONFIG_SEM == 0) && (RHINO_CONFIG_TASK_SEM >= 1))
#error "you need enable RHINO_CONFIG_SEM as well."
#endif
#if ((RHINO_CONFIG_HW_COUNT == 0) && (RHINO_CONFIG_TASK_SCHED_STATS >= 1))
#error "you need enable RHINO_CONFIG_HW_COUNT as well."
#endif
#if ((RHINO_CONFIG_HW_COUNT == 0) && (RHINO_CONFIG_DISABLE_SCHED_STATS >= 1))
#error "you need enable RHINO_CONFIG_HW_COUNT as well."
#endif
#endif /* CONFIG_H */

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Living_SDK/platform/mcu/es8p508x/HRSDK_GDB_ES8P508x/helloworld/sdk_init.c Normal file
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/*********************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
**********************************************************/
#include "sdk_init.h"
#include "k_config.h"
#include "lib_config.h"
#if defined (__CC_ARM) && defined(__MICROLIB)
void __aeabi_assert(const char *expr, const char *file, int line)
{
while (1);
}
#endif
void SystemTick_Config(void);
static void UARTInit(void);
static void LEDInit(void);
static void KeyInit(void);
void sdk_init(void)
{
SystemClockConfig();
DeviceClockAllEnable();
SystemTick_Config();
UARTInit();
LEDInit();
KeyInit();
}
void SystemTick_Config(void)
{
SYSTICK_InitStruType x;
x.SysTick_Value = SystemCoreClock/RHINO_CONFIG_TICKS_PER_SECOND;
x.SysTick_ClkSource = SysTick_ClkS_Cpu;
x.SysTick_ITEnable = ENABLE;
SysTick_Init(&x);
SysTick_Enable();
/* SysTick_IRQn interrupt configuration */
NVIC_SetPriority(SysTick_IRQn,0);
}
static void UARTInit(void)
{
GPIO_InitStruType y;
UART_InitStruType uart;
y.GPIO_Signal = GPIO_Pin_Signal_Digital;
y.GPIO_Func = GPIO_Func_2;
y.GPIO_Direction = GPIO_Dir_Out;
y.GPIO_PUEN = GPIO_PUE_Input_Disable;
y.GPIO_PDEN = GPIO_PDE_Input_Disable;
y.GPIO_OD = GPIO_ODE_Output_Disable;
y.GPIO_DS = GPIO_DS_Output_Normal;
GPIO_Init(GPIOA,GPIO_Pin_15,&y);
y.GPIO_Signal = GPIO_Pin_Signal_Digital;
y.GPIO_Func = GPIO_Func_2;
y.GPIO_Direction = GPIO_Dir_In;
y.GPIO_PUEN = GPIO_PUE_Input_Disable;
y.GPIO_PDEN = GPIO_PDE_Input_Disable;
y.GPIO_OD = GPIO_ODE_Output_Disable;
y.GPIO_DS = GPIO_DS_Output_Normal;
GPIO_Init(GPIOA,GPIO_Pin_16,&y);
uart.UART_StopBits = UART_StopBits_1;
uart.UART_TxMode = UART_DataMode_8;
uart.UART_TxPolar = UART_Polar_Normal;
uart.UART_RxMode = UART_DataMode_8;
uart.UART_RxPolar = UART_Polar_Normal;
uart.UART_BaudRate = 9600;
uart.UART_ClockSet = UART_Clock_1;
UART_Init(UART2,&uart);
UART_TBIMConfig(UART2,UART_TRBIM_Byte);
UART_RBIMConfig(UART2, UART_TRBIM_Byte);
UART_ITConfig(UART2,UART_IT_RB,ENABLE);
UART2_TxEnable();
UART2_RxEnable();
}
static void LEDInit(void)
{
GPIO_InitStruType x;
x.GPIO_Signal = GPIO_Pin_Signal_Digital;
x.GPIO_Func = GPIO_Func_0;
x.GPIO_Direction = GPIO_Dir_Out;
x.GPIO_PUEN = GPIO_PUE_Input_Disable;
x.GPIO_PDEN = GPIO_PDE_Input_Disable;
x.GPIO_OD = GPIO_ODE_Output_Disable;
x.GPIO_DS = GPIO_DS_Output_Normal;
GPIO_Init(GPIOA,GPIO_Pin_14,&x);
GPIO_Init(GPIOA,GPIO_Pin_13,&x);
GPIO_Init(GPIOA,GPIO_Pin_12,&x);
GPIO_Init(GPIOA,GPIO_Pin_11,&x);
GPIOA_SetBit(GPIO_Pin_14);
GPIOA_SetBit(GPIO_Pin_13);
GPIOA_SetBit(GPIO_Pin_12);
GPIOA_SetBit(GPIO_Pin_11);
}
static void KeyInit(void)
{
GPIO_InitStruType x;
x.GPIO_Signal = GPIO_Pin_Signal_Digital;
x.GPIO_Func = GPIO_Func_0;
x.GPIO_Direction = GPIO_Dir_In;
x.GPIO_PUEN = GPIO_PUE_Input_Enable;
x.GPIO_PDEN = GPIO_PDE_Input_Disable;
x.GPIO_OD = GPIO_ODE_Output_Disable;
x.GPIO_DS = GPIO_DS_Output_Normal;
GPIO_Init(GPIOB,GPIO_Pin_7,&x);
GPIO_Init(GPIOB,GPIO_Pin_2,&x);
GPIO_Init(GPIOB,GPIO_Pin_8,&x);
GPIO_Init(GPIOB,GPIO_Pin_3,&x);
GPIO_Init(GPIOA,GPIO_Pin_20,&x);
PINT_Config(PINT4, PINT_SEL2, PINT_Trig_Rise);
NVIC_Init(NVIC_PINT4_IRQn,NVIC_Priority_2,ENABLE);
PINT_Config(PINT7, PINT_SEL4, PINT_Trig_Rise);
NVIC_Init(NVIC_PINT7_IRQn,NVIC_Priority_2,ENABLE);
PINT_Config(PINT2, PINT_SEL4, PINT_Trig_Rise);
NVIC_Init(NVIC_PINT2_IRQn,NVIC_Priority_2,ENABLE);
PINT4_MaskDisable();
PINT4_Enable();
PINT2_MaskDisable();
PINT2_Enable();
PINT7_MaskDisable();
PINT7_Enable();
}

95
Living_SDK/platform/mcu/es8p508x/HRSDK_GDB_ES8P508x/helloworld/sdk_init.h Normal file
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/**
******************************************************************************
* File Name : main.hpp
* Description : This file contains the common defines of the application
******************************************************************************
** This notice applies to any and all portions of this file
* that are not between comment pairs USER CODE BEGIN and
* USER CODE END. Other portions of this file, whether
* inserted by the user or by software development tools
* are owned by their respective copyright owners.
*
* COPYRIGHT(c) 2017 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SOC_INIT_H
#define __SOC_INIT_H
/* Includes ------------------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private define ------------------------------------------------------------*/
#define B1_Pin GPIO_PIN_13
#define B1_GPIO_Port GPIOC
#define MCO_Pin GPIO_PIN_0
#define MCO_GPIO_Port GPIOH
#define USART_TX_Pin GPIO_PIN_2
#define USART_TX_GPIO_Port GPIOA
#define USART_RX_Pin GPIO_PIN_3
#define USART_RX_GPIO_Port GPIOA
#define LD2_Pin GPIO_PIN_5
#define LD2_GPIO_Port GPIOA
#define TMS_Pin GPIO_PIN_13
#define TMS_GPIO_Port GPIOA
#define TCK_Pin GPIO_PIN_14
#define TCK_GPIO_Port GPIOA
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* USER CODE BEGIN Private defines */
/* USER CODE END Private defines */
#ifdef __cplusplus
extern "C" {
#endif
void _Error_Handler(char *, int);
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif /* __SOC_INIT_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

52
Living_SDK/platform/mcu/es8p508x/HRSDK_GDB_ES8P508x/helloworld/system_ES8P508x.c Normal file
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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#include "system_ES8P508x.h"
uint32_t SystemCoreClock = 20000000;
void SystemCoreClockUpdate (void)
{
uint32_t Prot_Temp;
uint16_t Count=0;
Prot_Temp = SCU->PROT.PROT;
if(Prot_Temp != 0)
{SCU->PROT.Word = 0x55AA6996;}
SCU->SCLKEN1.HRC_EN = 1;
do
{
Count++;
}
while((SCU->SCLKEN1.HRC_RDY == 0)&&(Count != 0xFFF));
if(Count == 0xFFF)
{
return ;
}
SCU->SCLKEN0.SYSCLK_DIV = 0;
switch(SCU->SCLKEN0.CLK_SEL)
{
case 0:
SystemCoreClock = 20000000;
break;
case 1:
SystemCoreClock = 32000;
break;
default:
break;
}
if(Prot_Temp != 0)
{SCU->PROT.Word = 0x00000000;}
}
void SystemInit (void)
{
SystemCoreClockUpdate();
}
/*************************END OF FILE**********************/

16
Living_SDK/platform/mcu/es8p508x/HRSDK_GDB_ES8P508x/helloworld/system_ES8P508x.h Normal file
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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __SYSTEMES8P508x_H__
#define __SYSTEMES8P508x_H__
#include "ES8P508x.h"
#include "type.h"
extern uint32_t SystemCoreClock;
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#endif
/*************************END OF FILE**********************/

233
Living_SDK/platform/mcu/es8p508x/HRSDK_GDB_ES8P508x/startup_ES8P508x.s Normal file
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;*******************************************************************************
; *file : startup_ES8P508x.s
; *description: ES8P508x Device Startup File
; *author : Eastsoft MCU Software Team
; *version : V0.01
; *data : 6/30/2017
;
; *Copyright (C) 2017 Shanghai Eastsoft Microelectronics Co., Ltd.
; *
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
;*******************************************************************************
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; HardFault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PINT0_IRQHandler ;16, PINT0 IRQHandler
DCD PINT1_IRQHandler ;17, PINT1 IRQHandler
DCD PINT2_IRQHandler ;18, PINT2 IRQHandler
DCD PINT3_IRQHandler ;19, PINT3 IRQHandler
DCD PINT4_IRQHandler ;20, PINT4 IRQHandler
DCD PINT5_IRQHandler ;21, PINT5 IRQHandler
DCD PINT6_IRQHandler ;22, PINT6 IRQHandler
DCD PINT7_IRQHandler ;23, PINT7 IRQHandler
DCD T16N0_IRQHandler ;24, T16N0 IRQHandler
DCD T16N1_IRQHandler ;25, T16N1 IRQHandler
DCD T16N2_IRQHandler ;26, T16N2 IRQHandler
DCD T16N3_IRQHandler ;27, T16N3 IRQHandler
DCD T32N0_IRQHandler ;28, T32N0 IRQHandler
DCD 0 ;29, Reserved
DCD IWDT_IRQHandler ;30, IWDT IRQHandler
DCD WWDT_IRQHandler ;31, WWDT IRQHandler
DCD CCM_IRQHandler ;32, WDT IRQHandler
DCD PLK_IRQHandler ;33, PLK IRQHandler
DCD LVD_IRQHandler ;34, LVD IRQHandler
DCD KINT_IRQHandler ;35, KINT IRQHandler
DCD RTC_IRQHandler ;36, RTC IRQHandler
DCD ADC_IRQHandler ;37, ADC IRQHandler
DCD 0 ;38, Reserved
DCD AES_IRQHandler ;39, AES IRQHandler
DCD UART0_IRQHandler ;40, UART0 IRQHandler
DCD UART1_IRQHandler ;41, UART1 IRQHandler
DCD UART2_IRQHandler ;42, UART2 IRQHandler
DCD UART3_IRQHandler ;43, UART3 IRQHandler
DCD UART4_IRQHandler ;44, UART4 IRQHandler
DCD UART5_IRQHandler ;45, UART5 IRQHandler
DCD SPI0_IRQHandler ;46, SPI0 IRQHandler
DCD I2C0_IRQHandler ;47, I2C0 IRQHandler
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception IRQHandlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_IRQHandler PROC
EXPORT PINT0_IRQHandler [WEAK]
EXPORT PINT1_IRQHandler [WEAK]
EXPORT PINT2_IRQHandler [WEAK]
EXPORT PINT3_IRQHandler [WEAK]
EXPORT PINT4_IRQHandler [WEAK]
EXPORT PINT5_IRQHandler [WEAK]
EXPORT PINT6_IRQHandler [WEAK]
EXPORT PINT7_IRQHandler [WEAK]
EXPORT T16N0_IRQHandler [WEAK]
EXPORT T16N1_IRQHandler [WEAK]
EXPORT T16N2_IRQHandler [WEAK]
EXPORT T16N3_IRQHandler [WEAK]
EXPORT T32N0_IRQHandler [WEAK]
EXPORT IWDT_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT CCM_IRQHandler [WEAK]
EXPORT PLK_IRQHandler [WEAK]
EXPORT LVD_IRQHandler [WEAK]
EXPORT KINT_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT AES_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
PINT0_IRQHandler
PINT1_IRQHandler
PINT2_IRQHandler
PINT3_IRQHandler
PINT4_IRQHandler
PINT5_IRQHandler
PINT6_IRQHandler
PINT7_IRQHandler
T16N0_IRQHandler
T16N1_IRQHandler
T16N2_IRQHandler
T16N3_IRQHandler
T32N0_IRQHandler
IWDT_IRQHandler
WWDT_IRQHandler
CCM_IRQHandler
PLK_IRQHandler
LVD_IRQHandler
KINT_IRQHandler
RTC_IRQHandler
ADC_IRQHandler
AES_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
SPI0_IRQHandler
I2C0_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#include <k_api.h>
#include <assert.h>
#include <stdio.h>
#if (RHINO_CONFIG_MM_TLF > 0)
#if !defined (__CC_ARM) /* Keil / armcc */
extern void *heap_start;
extern void *heap_end;
extern void *heap_len;
//extern void *heap2_start;
//extern void *heap2_len;
#endif
#if defined (__CC_ARM) /* Keil / armcc */
#define HEAP_BUFFER_SIZE 1024*5
uint8_t g_heap_buf[HEAP_BUFFER_SIZE];
k_mm_region_t g_mm_region[] = {{g_heap_buf, HEAP_BUFFER_SIZE}, {(uint8_t *)0x10000000, 0x8000}};
#else
//k_mm_region_t g_mm_region[] = {{(uint8_t*)&heap_start,(size_t)&heap_len},{(uint8_t*)&heap2_start,(size_t)&heap2_len}};
k_mm_region_t g_mm_region[] = {{(uint8_t*)&heap_start,(size_t)&heap_len}};
#endif
int g_region_num = sizeof(g_mm_region)/sizeof(k_mm_region_t);
#endif
size_t soc_get_cur_sp()
{
size_t sp = 0;
#if defined (__GNUC__)&&!defined(__CC_ARM)
asm volatile(
"mov %0,sp\n"
:"=r"(sp));
#endif
return sp;
}
static void soc_print_stack()
{
void *cur, *end;
int i=0;
int *p;
end = krhino_cur_task_get()->task_stack_base + krhino_cur_task_get()->stack_size;
cur = (void *)soc_get_cur_sp();
p = (int*)cur;
while(p < (int*)end) {
if(i%4==0) {
printf("\r\n%08x:",(uint32_t)p);
}
printf("%08x ", *p);
i++;
p++;
}
printf("\r\n");
return;
}
void soc_err_proc(kstat_t err)
{
(void)err;
soc_print_stack();
assert(0);
}
krhino_err_proc_t g_err_proc = soc_err_proc;

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V3.02
* @date 16. July 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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/****************************************************************************
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#ifndef __LIBADC_H__
#define __LIBADC_H__
#include "ES8P508x.h"
#include "type.h"
typedef enum
{
ADC_ClkS_PCLK = 0x0 ,
ADC_ClkS_PLL = 0x1 ,
ADC_ClkS_32K = 0x2 ,
}ADC_TYPE_CLKS;
typedef enum
{
ADC_ClkDiv_1 = 0x0 ,
ADC_ClkDiv_2 = 0x1 ,
ADC_ClkDiv_4 = 0x2 ,
ADC_ClkDiv_8 = 0x3 ,
ADC_ClkDiv_16 = 0x4 ,
ADC_ClkDiv_32 = 0x5 ,
ADC_ClkDiv_64 = 0x6 ,
ADC_ClkDiv_256 = 0x7 ,
}ADC_TYPE_CLKDIV;
typedef enum
{
ADC_VrefP_Vcc = 0x0 ,
ADC_VrefP_Ref = 0x1 ,
ADC_VrefP_Ref2 = 0x2 ,
ADC_VrefP_Exter = 0x3 ,
}ADC_TYPE_VREFP;
typedef enum
{
ADC_SMPS_SOFT = 0,
ADC_SMPS_HARD = 1,
}ADC_TYPE_SMPS;
typedef enum
{
ADC_SampClk_2 = 0x0 ,
ADC_SampClk_4 = 0x1 ,
ADC_SampClk_8 = 0x2 ,
ADC_SampClk_16 = 0x3 ,
}ADC_TYPE_ST;
typedef enum
{
ADC_ConvSpeed_Low = 0x0 ,
ADC_ConvSpeed_High = 0x1 ,
}ADC_TYPE_HSEN;
typedef enum
{
ADC_CHS_AIN0 = 0,
ADC_CHS_AIN1 = 1,
ADC_CHS_AIN2 = 2,
ADC_CHS_AIN3 = 3,
ADC_CHS_AIN4 = 4,
ADC_CHS_AIN5 = 5,
ADC_CHS_AIN6 = 6,
ADC_CHS_AIN7 = 7,
ADC_CHS_AIN8 = 8,
ADC_CHS_AIN9 = 9,
ADC_CHS_AIN10 = 10,
ADC_CHS_AIN11 = 11,
ADC_CHS_AIN12 = 12,
ADC_CHS_AIN13 = 13,
ADC_CHS_AIN14 = 14,
ADC_CHS_AIN15 = 15,
}ADC_TYPE_CHS;
typedef enum
{
ADC_LP_86ua = 2,
ADC_LP_215ua = 0,
ADC_LP_120ua = 1,
ADC_LP_70ua = 3,
}ADC_TYPE_BUFLP;
typedef enum
{
ADC_BUFF_0ua = 0,
ADC_BUFF_34ua = 1,
ADC_BUFF_95ua = 2,
}ADC_TYPE_BUFEN;
typedef enum
{
ADC_IF = 0x01,
ADC_IF_ACPMIN = 0x02,
ADC_IF_ACPMAX =0x04,
ADC_IF_ACPOVER = 0x08,
}ADC_TYPE_IF;
typedef enum
{
ADC_IE = 0x01,
ADC_IE_ACPMIN = 0x02,
ADC_IE_ACPMAX =0x04,
ADC_IE_ACPOVER = 0x08,
}ADC_TYPE_IE;
typedef struct
{
ADC_TYPE_CLKS ADC_ClkS;
ADC_TYPE_CLKDIV ADC_ClkDiv;
ADC_TYPE_VREFP ADC_VrefP;
ADC_TYPE_SMPS ADC_SampS;
ADC_TYPE_ST ADC_SampClk;
ADC_TYPE_HSEN ADC_ConvSpeed;
ADC_TYPE_CHS ADC_ChS;
TYPE_FUNCEN ADC_IREF_EN;
TYPE_FUNCEN ADC_VREF_EN;
TYPE_FUNCEN ADC_VCMBUF_EN;
TYPE_FUNCEN ADC_VREFN;
TYPE_FUNCEN ADC_VRBUF_EN;
}ADC_InitStruType;
typedef enum
{
ADC_ACP_MIN_MIN = 0x0,
ADC_ACP_MIN_MAX = 0xfff,
}ADC_TYPE_ACP_MIN;
typedef enum
{
ADC_ACP_MAX_MIN = 0x0,
ADC_ACP_MAX_MAX = 0xfff,
}ADC_TYPE_ACP_MAX;
typedef enum
{
ADC_ACPC_OVFL_TIME_MAX = 0x9c3,
}ADC_TYPE_ACPC_OVFL_TIME;
typedef enum
{
ADC_ACPC_TIMES_1 = 0,
ADC_ACPC_TIMES_2 = 1,
ADC_ACPC_TIMES_4 = 2,
ADC_ACPC_TIMES_8 = 3,
ADC_ACPC_TIMES_MAX = 3,
}ADC_TYPE_ACPC_TIMES;
typedef enum
{
ADC_ACPC_CLKS_PCLK = 0,
ADC_ACPC_CLKS_LRC = 1,
}ADC_TYPE_ACPC_CLKS;
typedef FuncState ADC_TYPE_CHOP_EN1, ADC_TYPE_CHOP_EN;
typedef FuncState ADC_TYPE_VREF_EN,ADC_TYPE_IREF_EN;
typedef FuncState ADC_TYPE_EN,ADC_TYPE_ACP_EN;
typedef struct
{
ADC_TYPE_ACP_EN ACP_EN;
uint16_t ACPC_OVER_TIME;
ADC_TYPE_ACPC_TIMES ACPC_TIMES;
uint16_t ACPC_MIN_TARGET;
uint16_t ACPC_MAX_TARGET;
}ADC_ACP_TypeDef;
#define ADC_Enable() (ADC->CON0.EN = 0x1)
#define ADC_Disable() (ADC->CON0.EN = 0x0)
#define ADC_ACP_Enable() (ADC->CON0.ACP_EN = 1)
#define ADC_ACP_Disable() (ADC->CON0.ACP_EN = 0)
#define ADC_Start() (ADC->CON0.TRIG = 0x1)
#define ADC_SampStart() (ADC->CON1.SMPON = 0x1)
#define ADC_SampStop() (ADC->CON1.SMPON = 0x0)
#define ADC_VDD5_FLAG_Enable() (ADC->CHS.VDD5_FLAG_EN = 0x1)
#define ADC_VDD5_FLAG_Disable() (ADC->CHS.VDD5_FLAG_EN = 0x0)
#define ADC_IE_Enable() (ADC->IE.IE = 0x1)
#define ADC_IE_Disable() (ADC->IE.IE = 0x0)
#define ADC_ACPMINIE_Enable() (ADC->IE.ACPMINIE = 1)
#define ADC_ACPMINIE_Disable() (ADC->IE.ACPMINIE = 0)
#define ADC_ACPMAXIE_Enable() (ADC->IE.ACPMAXIE = 1)
#define ADC_ACPMAXIE_Disable() (ADC->IE.ACPMAXIE = 0)
#define ADC_ACPOVIE_Enable() (ADC->IE.ACPOVIE = 1)
#define ADC_ACPOVIE_Disable() (ADC->IE.ACPOVIE = 0)
void ADC_Init(ADC_InitStruType * ADC_InitStruct);
void ADC_Set_CH(ADC_TYPE_CHS AdcCH);
uint16_t ADC_GetConvValue(void);
FlagStatus ADC_GetConvStatus(void);
ErrorStatus ADC_ACPConfig(ADC_ACP_TypeDef *ADC_ACP_InitStruct);
ErrorStatus ADC_SoftStart(void);
ErrorStatus ADC_SoftStop(void);
uint16_t ADC_GetACPMeanValue(void);
uint16_t ADC_GetACPMinValue(void);
uint16_t ADC_GetACPMaxValue(void);
FlagStatus ADC_GetFlagStatus(ADC_TYPE_IF IFName);
ITStatus ADC_GetITStatus(ADC_TYPE_IE IEName);
ErrorStatus ADC_ClearIFStatus(ADC_TYPE_IF IFName);
void ADC_Reset(void);
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#ifndef __LIBAES_H__
#define __LIBAES_H__
#include "ES8P508x.h"
#include "type.h"
typedef enum {
AES_MODE_DECRYPT = 0,
AES_MODE_ENCRYPT = 1,
}AES_TYPE_MODE;
typedef enum {
AES_DONE_YES = 0,
AES_DONE_NO = 1,
}AES_TYPE_DONE;
typedef struct {
uint32_t DATA[4];
}AES_DATA_TypeDef;
typedef enum {
AES_IF_IF = 0x80,
}AES_TYPE_IF;
typedef enum {
AES_IT_IT = 0x40,
}AES_TYPE_IT;
typedef struct {
uint32_t KEY[4];
}AES_KEY_TypeDef;
typedef struct {
AES_TYPE_MODE MODE;
}AES_InitStruType;
#define AES_Enable() (AES->CON.GO_DONE = 1)
#define AES_Disable() (AES->CON.GO_DONE = 0)
void AES_Init(AES_InitStruType * AES_InitStruct);
void AES_WriteKey(uint32_t *AES_KEY);
void AES_ReadKey(uint32_t * AES_KEY);
void AES_WriteData(uint32_t *AES_DATA);
void AES_ReadData(uint32_t * AES_DATA);
void AES_ITConfig(AES_TYPE_IT AES_IE, TYPE_FUNCEN NewState);
FlagStatus AES_GetFlagStatus(AES_TYPE_IF Flag);
void AES_ClearITPendingBit(AES_TYPE_IF Flag);
AES_TYPE_DONE AES_GetDoneStatus(void);
void AES_Reset(void);
#endif

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __LIBCONFIG_H__
#define __LIBCONFIG_H__
#include "lib_adc.h"
#include "lib_iic.h"
#include "lib_scs.h"
#include "lib_scu.h"
#include "lib_spi.h"
#include "lib_timer.h"
#include "lib_uart.h"
#include "lib_wdt.h"
#include "lib_flashiap.h"
#include "lib_gpio.h"
#include "lib_printf.h"
#include "lib_iap.h"
#include "lib_crc.h"
#include "lib_aes.h"
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __LIBCRC_H
#define __LIBCRC_H
#include "ES8P508x.h"
#include "type.h"
#ifdef __cplusplus
extern "C" {
#endif
#define CRC_EmptayCheck_addr 0x10000010
#define CRC_FlashVerify_addr 0x10000014
#define CRC_UserCal_addr 0x10000018
#define CRC_CheckReset_addr 0x1000001C
typedef uint32_t (*CRC_EM)(void* address, uint32_t data_len);
typedef uint32_t (*CRC_FL)(void* address, uint32_t data_len, uint32_t type);
typedef uint32_t (*CRC_US)(void* address, uint32_t data_len, uint32_t type);
typedef uint32_t (*CRC_CH)(void);
typedef enum
{
CRC_XOROUT_NORMAL = 0x0,
CRC_XOROUT_ANTI = (1U<<14),
} CRC_XOROUT;
typedef enum
{
CRC_REFOUT_NORMAL = 0x0,
CRC_REFOUT_REVERSE = (1U<<13),
} CRC_REFOUT;
typedef enum
{
CRC_REFIN_NORMAL = 0x0,
CRC_REFIN_REVERSE = (1U<<12),
} CRC_REFIN;
typedef enum
{
CRC_MOD_CRC32 = 0x0,
CRC_MOD_CRC16 = (2U<<8),
CRC_MOD_CRC16_CCITT = (3U<<8),
} CRC_MOD_TYPE;
typedef enum
{
CRC_INIT_DATA_ALL_0 = 0x0,
CRC_INIT_DATA_ALL_1 = (1U<<3),
} CRC_INIT_DATA;
typedef enum
{
CRC_HS_TYPE_DISABLE = 0x0,
CRC_HS_TYPE_ENABLE = (1U<<2),
} CRC_HS_TYPE;
typedef struct
{
CRC_XOROUT xorout;
CRC_REFOUT refout;
CRC_REFIN refin;
CRC_MOD_TYPE mode;
CRC_INIT_DATA init_data_type;
CRC_HS_TYPE hs_type;
} CRC_CONValueStruType;
uint32_t CRC_getTypeValue(CRC_CONValueStruType con_value);
uint32_t CRC_EmptayCheck(void* address, uint32_t data_len);
uint32_t CRC_FlashVerify(void* address, uint32_t data_len, uint32_t type);
uint32_t CRC_UserCal(void* address, uint32_t data_len, uint32_t type);
uint32_t CRC_CheckReset(void);
#ifdef __cplusplus
}
#endif
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __LIBIAP_H__
#define __LIBIAP_H__
#include "ES8P508x.h"
#include "type.h"
#define FlashIAP_RegUnLock() (IAP->UL.UL = 0x49415055)
#define FlashIAP_RegLock() (IAP->UL.UL = 0x00000000)
#define FlashIAP_Enable() (IAP->CON.EN = 0x1)
#define FlashIAP_Disable() (IAP->CON.EN = 0x0)
#define FlashIAP_REQ() (IAP->CON.FLASH_REQ = 0x1)
ErrorStatus FlashIap_Close_WPROT(uint8_t Page);
ErrorStatus FlashIap_Open_WPROT(uint8_t Page);
ErrorStatus FlashIap_CloseAll_WPROT(void);
ErrorStatus FlashIap_OpenAll_WPROT(void);
ErrorStatus FlashIap_Unlock(void);
ErrorStatus FlashIap_WriteEnd(void);
ErrorStatus FlashIap_ErasePage(uint8_t Page_Addr);
ErrorStatus FlashIap_WriteCont(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32);
ErrorStatus FlashIap_WriteWord(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32);
ErrorStatus Flash_Read(uint32_t * Ram_Addr, uint32_t Flash_Addr, uint8_t Len);
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __LIBGPIO_H__
#define __LIBGPIO_H__
#include "ES8P508x.h"
#include "type.h"
typedef enum
{
GPIOA = 0x0 ,
GPIOB = 0x1 ,
}GPIO_TYPE;
typedef enum
{
GPIO_Pin_0 = 0x00,
GPIO_Pin_1 = 0x01,
GPIO_Pin_2 = 0x02,
GPIO_Pin_3 = 0x03,
GPIO_Pin_4 = 0x04,
GPIO_Pin_5 = 0x05,
GPIO_Pin_6 = 0x06,
GPIO_Pin_7 = 0x07,
GPIO_Pin_8 = 0x08,
GPIO_Pin_9 = 0x09,
GPIO_Pin_10 = 0x0A,
GPIO_Pin_11 = 0x0B,
GPIO_Pin_12 = 0x0C,
GPIO_Pin_13 = 0x0D,
GPIO_Pin_14 = 0x0E,
GPIO_Pin_15 = 0x0F,
GPIO_Pin_16 = 0x10,
GPIO_Pin_17 = 0x11,
GPIO_Pin_18 = 0x12,
GPIO_Pin_19 = 0x13,
GPIO_Pin_20 = 0x14,
GPIO_Pin_21 = 0x15,
GPIO_Pin_22 = 0x16,
GPIO_Pin_23 = 0x17,
GPIO_Pin_24 = 0x18,
GPIO_Pin_25 = 0x19,
GPIO_Pin_26 = 0x1A,
GPIO_Pin_27 = 0x1B,
GPIO_Pin_28 = 0x1C,
GPIO_Pin_29 = 0x1D,
GPIO_Pin_30 = 0x1E,
GPIO_Pin_31 = 0x1F,
}GPIO_TYPE_PIN;
typedef enum
{
GPIO_Func_0 = 0x0 ,
GPIO_Func_1 = 0x1 ,
GPIO_Func_2 = 0x2 ,
GPIO_Func_3 = 0x3 ,
}GPIO_TYPE_FUNC;
typedef enum
{
GPIO_Dir_Out = 0x0 ,
GPIO_Dir_In = 0x1 ,
}GPIO_TYPE_DIR;
typedef enum
{
GPIO_DS_Output_Normal = 0,
GPIO_DS_Output_Strong = 1,
} GPIO_TYPE_DS;
typedef enum {
GPIO_Pin_Signal_Digital = 0,
GPIO_Pin_Signal_Analog = 1,
} GPIO_Pin_Signal;
typedef enum {
GPIO_PUE_Input_Disable = 0,
GPIO_PUE_Input_Enable = 1,
} GPIO_PUE_Input;
typedef enum {
GPIO_PDE_Input_Disable = 0,
GPIO_PDE_Input_Enable = 1,
} GPIO_PDE_Input;
typedef enum {
GPIO_ODE_Output_Disable = 0,
GPIO_ODE_Output_Enable = 1,
} GPIO_ODE_Output;
typedef struct
{
GPIO_Pin_Signal GPIO_Signal;
GPIO_TYPE_FUNC GPIO_Func;
GPIO_TYPE_DIR GPIO_Direction;
GPIO_PUE_Input GPIO_PUEN;
GPIO_PDE_Input GPIO_PDEN;
GPIO_ODE_Output GPIO_OD;
GPIO_TYPE_DS GPIO_DS;
}GPIO_InitStruType;
/* PINT */
typedef enum
{
PINT0 = 0x0 ,
PINT1 = 0x1 ,
PINT2 = 0x2 ,
PINT3 = 0x3 ,
PINT4 = 0x4 ,
PINT5 = 0x5 ,
PINT6 = 0x6 ,
PINT7 = 0x7 ,
}PINT_TYPE;
/* PINT SEL */
typedef enum
{
PINT_SEL0 = 0x0 ,
PINT_SEL1 = 0x1 ,
PINT_SEL2 = 0x2 ,
PINT_SEL3 = 0x3 ,
PINT_SEL4 = 0x4 ,
PINT_SEL5 = 0x5 ,
PINT_SEL6 = 0x6 ,
PINT_SEL7 = 0x7 ,
}PINT_TYPE_SEL;
/* PINT Trigger */
typedef enum
{
PINT_Trig_Rise = 0x0 ,
PINT_Trig_Fall = 0x1 ,
PINT_Trig_High = 0x2 ,
PINT_Trig_Low = 0x3 ,
PINT_Trig_Change = 0x4 ,
}PINT_TYPE_TRIG;
typedef enum
{
PINT_IT_PINT0 = 0x01 ,
PINT_IT_PINT1 = 0x02 ,
PINT_IT_PINT2 = 0x04 ,
PINT_IT_PINT3 = 0x08 ,
PINT_IT_PINT4 = 0x10 ,
PINT_IT_PINT5 = 0x20 ,
PINT_IT_PINT6 = 0x40 ,
PINT_IT_PINT7 = 0x80 ,
PINT_IT_PINTAll = 0xFF ,
}PINT_TYPE_IT;
#define PINT0_Enable() (GPIO->PINTIE.PINTIE |= 0X1)
#define PINT1_Enable() (GPIO->PINTIE.PINTIE |= 0x2)
#define PINT2_Enable() (GPIO->PINTIE.PINTIE |= 0x4)
#define PINT3_Enable() (GPIO->PINTIE.PINTIE |= 0x8)
#define PINT4_Enable() (GPIO->PINTIE.PINTIE |= 0x10)
#define PINT5_Enable() (GPIO->PINTIE.PINTIE |= 0x20)
#define PINT6_Enable() (GPIO->PINTIE.PINTIE |= 0x40)
#define PINT7_Enable() (GPIO->PINTIE.PINTIE |= 0x80)
#define PINT0_Disable() (GPIO->PINTIE.PINTIE &= ~0x01)
#define PINT1_Disable() (GPIO->PINTIE.PINTIE &= ~0x02)
#define PINT2_Disable() (GPIO->PINTIE.PINTIE &= ~0x04)
#define PINT3_Disable() (GPIO->PINTIE.PINTIE &= ~0x08)
#define PINT4_Disable() (GPIO->PINTIE.PINTIE &= ~0x10)
#define PINT5_Disable() (GPIO->PINTIE.PINTIE &= ~0x20)
#define PINT6_Disable() (GPIO->PINTIE.PINTIE &= ~0x40)
#define PINT7_Disable() (GPIO->PINTIE.PINTIE &= ~0x80)
#define PINT0_MaskEnable() (GPIO->PINTIE.PMASK |= 0X01)
#define PINT1_MaskEnable() (GPIO->PINTIE.PMASK |= 0x02)
#define PINT2_MaskEnable() (GPIO->PINTIE.PMASK |= 0x04)
#define PINT3_MaskEnable() (GPIO->PINTIE.PMASK |= 0x08)
#define PINT4_MaskEnable() (GPIO->PINTIE.PMASK |= 0x10)
#define PINT5_MaskEnable() (GPIO->PINTIE.PMASK |= 0x20)
#define PINT6_MaskEnable() (GPIO->PINTIE.PMASK |= 0x40)
#define PINT7_MaskEnable() (GPIO->PINTIE.PMASK |= 0x80)
#define PINT0_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x01)
#define PINT1_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x02)
#define PINT2_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x04)
#define PINT3_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x08)
#define PINT4_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x10)
#define PINT5_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x20)
#define PINT6_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x40)
#define PINT7_MaskDisable() (GPIO->PINTIE.PMASK &= ~0x80)
#define PINT_ClearAllITPending() (GPIO->PIF.Word = (uint32_t)0xff)
void GPIO_Init(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_InitStruType* GPIO_InitStruct);
void GPIO_Write(GPIO_TYPE GPIOx, uint32_t Value);
uint32_t GPIO_Read(GPIO_TYPE GPIOx);
PinStatus GPIO_ReadBit(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx);
void GPIOA_SetBit(GPIO_TYPE_PIN PINx);
void GPIOA_ResetBit(GPIO_TYPE_PIN PINx);
void GPIOA_ToggleBit(GPIO_TYPE_PIN PINx);
void GPIOB_SetBit(GPIO_TYPE_PIN PINx);
void GPIOB_ResetBit(GPIO_TYPE_PIN PINx);
void GPIOB_ToggleBit(GPIO_TYPE_PIN PINx);
void GPIOA_SetDirection(GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir_Type);
void GPIOB_SetDirection(GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir_Type);
void PINT_Config(PINT_TYPE PINTx, PINT_TYPE_SEL SELx, PINT_TYPE_TRIG TRIGx);
void GPIO_SetSingalTypeFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_Pin_Signal GPIO_Signal);
void GPIO_SetDirRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir);
void GPIO_SetODERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_ODE_Output ODE);
void GPIO_SetDSRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DS DS);
void GPIO_SetPUERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PUE_Input PUE);
void GPIO_SetPDERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PDE_Input PDE);
void GPIO_SetFuncxRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_FUNC Func);
FlagStatus PINT_GetIFStatus(PINT_TYPE_IT PINT_Flag);
FlagStatus PINT_GetITStatus(PINT_TYPE_IT PINT_Flag);
void PINT_ClearITPendingBit(PINT_TYPE_IT PINT_Flag);
#endif

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __ES8P508x_IAP_TABLE_H
#define __ES8P508x_IAP_TABLE_H
#include "ES8P508x.h"
#include "type.h"
#ifdef __cplusplus
extern "C" {
#endif
#define IAP_PageProgram_addr 0x10000008
#define IAP_PageErase_addr 0x10000000
#define IAP_WordProgram_addr 0x10000004
typedef ErrorStatus (*IAP_PE)(uint32_t address);
typedef ErrorStatus (*IAP_WP)(uint32_t address, uint32_t data);
typedef ErrorStatus (*IAP_PP)(uint32_t address, uint32_t data[], uint32_t length, uint32_t erase);
ErrorStatus IAP_PageErase(uint32_t address);
ErrorStatus IAP_WordProgram(uint32_t address, uint32_t data);
ErrorStatus IAP_PageProgram(uint32_t address, uint32_t data[], uint32_t length, uint32_t erase);
ErrorStatus IAPRead(uint32_t *Ram_Addr, uint32_t Flash_Addr, uint8_t Len);
#define PageEraseEnable 0x00000001
#define PageEraseDisable 0x00000000
#ifdef __cplusplus
}
#endif
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __LIBIIC_H__
#define __LIBIIC_H__
#include "ES8P508x.h"
#include "type.h"
#include "system_ES8P508x.h"
typedef enum
{
I2C_PinMode_PP = 0x0 ,
I2C_PinMode_OD = 0x1 ,
}I2C_TYPE_PINOD;
typedef enum
{
I2C_Mode_Master = 0x0 ,
I2C_Mode_Slave = 0x1 ,
}I2C_TYPE_MODE;
typedef enum
{
I2C_AckDelay_0P5 = 0x0 ,
I2C_AckDelay_1 = 0x1 ,
I2C_AckDelay_1P5 = 0x2 ,
I2C_AckDelay_2 = 0x3 ,
I2C_AckDelay_2P5 = 0x4 ,
I2C_AckDelay_3 = 0x5 ,
I2C_AckDelay_3P5 = 0x6 ,
I2C_AckDelay_4 = 0x7 ,
}I2C_TYPE_ADLY;
typedef enum
{
I2C_RecMode_0 = 0x0 ,
I2C_RecMode_1 = 0x1 ,
I2C_RecMode_2 = 0x2 ,
I2C_RecMode_3 = 0x3 ,
I2C_RecMode_4 = 0x4 ,
I2C_RecMode_5 = 0x5 ,
I2C_RecMode_6 = 0x6,
I2C_RecMode_7 = 0x7,
}I2C_TYPE_RECMODE;
typedef enum
{
I2C_TI_Disable = 0x0 ,
I2C_TI_1 = 0x1 ,
I2C_TI_2 = 0x2 ,
I2C_TI_3 = 0x3 ,
I2C_TI_4 = 0x4 ,
I2C_TI_5 = 0x5 ,
I2C_TI_6 = 0x6 ,
I2C_TI_7 = 0x7 ,
I2C_TI_8 = 0x8 ,
I2C_TI_9 = 0x9 ,
I2C_TI_10 = 0xA ,
I2C_TI_11 = 0xB ,
I2C_TI_12 = 0xC ,
I2C_TI_13 = 0xD ,
I2C_TI_14 = 0xE ,
I2C_TI_15 = 0xF ,
}I2C_TYPE_TIS;
typedef struct
{
I2C_TYPE_PINOD I2C_SclOd;
I2C_TYPE_PINOD I2C_SdaOd;
TYPE_FUNCEN I2C_16XSamp;
uint32_t I2C_Clk;
I2C_TYPE_MODE I2C_Mode;
TYPE_FUNCEN I2C_AutoStop;
TYPE_FUNCEN I2C_AutoCall;
}I2C_InitStruType;
typedef enum
{
I2C_TRBIM_Byte = 0x0 ,
I2C_TRBIM_HalfWord = 0x1 ,
I2C_TRBIM_Word = 0x2 ,
}I2C_TYPE_TRBIM;
typedef enum
{
I2C_Mode_Write = 0x0 ,
I2C_Mode_Read = 0x1 ,
}I2C_TYPE_RWMODE;
typedef enum
{
I2C_IT_SR = 0x0001 ,
I2C_IT_SP = 0x0002 ,
I2C_IT_TB = 0x0004 ,
I2C_IT_RB = 0x0008 ,
I2C_IT_TE = 0x0010 ,
I2C_IT_RO = 0x0020 ,
I2C_IT_NA = 0x0040 ,
I2C_IT_TBWE = 0x0080 ,
I2C_IT_TIDLE = 0x01000 ,
}I2C_TYPE_IT;
typedef enum
{
I2C_Flag_SR = 0x0001 ,
I2C_Flag_SP = 0x0002 ,
I2C_Flag_TB = 0x0004 ,
I2C_Flag_RB = 0x0008 ,
I2C_Flag_TE = 0x0010 ,
I2C_Flag_RO = 0x0020 ,
I2C_Flag_NA = 0x0040 ,
I2C_Flag_TBWE = 0x0080,
I2C_Flag_TIDLE= 0X1000,
}I2C_TYPE_FLAG;
typedef enum
{
I2C_Clr_SR = 0x0001 ,
I2C_Clr_SP = 0x0002 ,
I2C_Clr_TE = 0x0010 ,
I2C_Clr_RO = 0x0020 ,
I2C_Clr_NA = 0x0040 ,
I2C_Clr_TBWE = 0x0080 ,
I2C_Clr_TIDLE= 0X01000,
}I2C_CLR_IF;
#define I2C_Enable() (I2C0->CON.EN = 1)
#define I2C_Disable() (I2C0->CON.EN = 0)
#define I2C_Reset() (I2C0->CON.RST = 1)
#define I2C_TJEnable() (I2C0->CON.TJE = 1)
#define I2C_TJDisable() (I2C0->CON.TJE = 0)
#define I2C_Read() (I2C0->CON.RW = 1)
#define I2C_Write() (I2C0->CON.RW = 0)
#define I2C_CSEnable() (I2C0->MOD.CSE = 1)
#define I2C_CSDisable() (I2C0->MOD.CSE = 0)
#define I2C_ANAEnable() (I2C0->MOD.ANAE = 1)
#define I2C_ANADisable() (I2C0->MOD.ANAE = 0)
#define I2C_SRAEnable() (I2C0->MOD.SRAE = 1)
#define I2C_SRADisable() (I2C0->MOD.SRAE = 0)
#define I2C_SPAEnable() (I2C0->MOD.SPAE = 1)
#define I2C_SPADisable() (I2C0->MOD.SPAE = 0)
#define I2C_SRTrigger() (I2C0->MOD.SRT=1)
#define I2C_SPTrigger() (I2C0->MOD.SPT = 1)
#define I2C_RDTrigger() (I2C0->MOD.RDT = 1)
#define I2C_Release() (I2C0->MOD.BLD = 1)
#define I2C_TACK() (I2C0->MOD.TAS = 1)
#define I2C_TNACK() (I2C0->MOD.TAS = 0)
void I2C_Init(I2C_InitStruType* I2C_InitStruct);
void I2C_ITConfig(I2C_TYPE_IT I2C_IT,TYPE_FUNCEN NewState);
void I2C_SendAddress(uint8_t I2C_Address,I2C_TYPE_RWMODE Mode);
void I2C_SetAddress(uint8_t I2C_Address);
void I2C_RecModeConfig(I2C_TYPE_RECMODE RecType);
void I2C_TBIMConfig(I2C_TYPE_TRBIM Type);
void I2C_RBIMConfig(I2C_TYPE_TRBIM Type);
void I2C_AckDelay(I2C_TYPE_ADLY Type,TYPE_FUNCEN NewStatus);
void I2C_TISConfig(I2C_TYPE_TIS Time);
void I2C_SendByte(uint8_t Byte);
void I2C_SendHalfWord(uint16_t HalfWord);
void I2C_SendWord(uint32_t Word);
uint8_t I2C_RecByte(void);
uint16_t I2C_RecHalfWord(void);
uint32_t I2C_RecWord(void);
I2C_TYPE_RWMODE I2C_GetRWMode(void);
FlagStatus I2C_GetTBStatus(void);
FlagStatus I2C_GetFlagStatus(I2C_TYPE_FLAG I2C_Flag);
FlagStatus I2C_GetITStatus( I2C_TYPE_IT I2C_Flag);
void I2C_ClearITPendingBit(I2C_CLR_IF I2C_IT);
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __LIBPRINTF_H__
#define __LIBPRINTF_H__
#include "lib_uart.h"
#include <stdio.h>
#include "type.h"
int fputc(int ch, FILE *f);
static char *itoa(int value, char *string, int radix);
ErrorStatus UART_printf(UART_TypeDef* UARTx, uint8_t *Data,...);
#endif
/*************************END OF FILE**********************/

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/*********************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
**********************************************************/
#ifndef __LIBRTC_H__
#define __LIBRTC_H__
#include "ES8P508x.h"
#include "type.h"
typedef enum
{
RTC_LOSC = 0x0,
RTC_LRC = 0x1,
RTC_PLCK_256 = 0x2,
RTC_PLCK = 0x3,
}RTC_TYPE_CLKS;
typedef enum
{
RTC_HOUR12 = 0x0,
RTC_HOUR24 = 0x1,
}RTC_TYPE_TIME;
typedef enum
{
RTC_Interrupt_Source_Second = 0,
RTC_Interrupt_Source_Minute = 1,
RTC_Interrupt_Source_Hour = 2,
RTC_Interrupt_Source_Day = 3,
RTC_Interrupt_Source_Month = 4,
RTC_Interrupt_Source_DayALE = 5,
RTC_Interrupt_Source_WeekALE = 6,
} RTC_Interrupt_Source;
void RTC_Init(RTC_TYPE_CLKS CLKx,RTC_TYPE_TIME HOURx);
uint32_t RTC_ReadHourmode(void);
uint32_t RTC_ReadSecond(void);
uint32_t RTC_ReadMinute(void);
uint32_t RTC_ReadHour(uint32_t *meridiem);
uint32_t RTC_ReadDay(void);
uint32_t RTC_ReadMonth(void);
uint32_t RTC_ReadYear(void);
uint32_t RTC_ReadWeek(void);
ErrorStatus RTC_WriteSecond(uint32_t second);
ErrorStatus RTC_WriteMinute(uint32_t minute);
ErrorStatus RTC_WriteHour(uint32_t hour, uint32_t meridiem);
ErrorStatus RTC_WriteDay(uint32_t day);
ErrorStatus RTC_WriteMonth(uint32_t month);
ErrorStatus RTC_WriteYear(uint32_t year);
ErrorStatus RTC_WriteWeek(uint32_t week);
uint32_t RTC_ReadWeekAlarmMinute(void);
uint32_t RTC_ReadWeekAlarmHour(uint32_t *meridiem);
uint32_t RTC_ReadWeekAlarmWeek(void);
uint32_t RTC_ReadDayAlarmMinute(void);
uint32_t RTC_ReadDayAlarmHour(uint32_t *meridiem);
ErrorStatus RTC_WriteWeekAlarmMinute(uint32_t minute);
ErrorStatus RTC_WriteWeekAlarmHour(uint32_t hour, uint32_t meridiem);
ErrorStatus RTC_WriteWeekAlarmWeek(uint32_t week);
ErrorStatus RTC_WriteDayAlarmMinute(uint32_t minute);
ErrorStatus RTC_WriteDayAlarmHour(uint32_t hour, uint32_t meridiem);
void RTC_InterruptEnable(RTC_Interrupt_Source src);
void RTC_InterruptDisable(RTC_Interrupt_Source src);
ITStatus RTC_GetITStatus(RTC_Interrupt_Source src);
FlagStatus RTC_GetFlagStatus(RTC_Interrupt_Source src);
void RTC_ClearAllITFlag(void);
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __LIBNVIC_H__
#define __LIBNVIC_H__
#include "ES8P508x.h"
#include "type.h"
typedef enum
{
NVIC_PINT0_IRQn = 0,
NVIC_PINT1_IRQn = 1,
NVIC_PINT2_IRQn = 2,
NVIC_PINT3_IRQn = 3,
NVIC_PINT4_IRQn = 4,
NVIC_PINT5_IRQn = 5,
NVIC_PINT6_IRQn = 6,
NVIC_PINT7_IRQn = 7,
NVIC_T16N0_IRQn = 8,
NVIC_T16N1_IRQn = 9,
NVIC_T16N2_IRQn = 10,
NVIC_T16N3_IRQn = 11,
NVIC_T32N0_IRQn = 12,
NVIC_IWDT_IRQn = 14,
NVIC_WWDT_IRQn = 15,
NVIC_CCM_IRQn = 16,
NVIC_PLK_IRQn = 17,
NVIC_LVD_IRQn = 18,
NVIC_KINT_IRQn = 19,
NVIC_RTC_IRQn = 20,
NVIC_ADC_IRQn = 21,
NVIC_AES_IRQn = 23,
NVIC_UART0_IRQn = 24,
NVIC_UART1_IRQn = 25,
NVIC_UART2_IRQn = 26,
NVIC_UART3_IRQn = 27,
NVIC_UART4_IRQn = 28,
NVIC_UART5_IRQn = 29,
NVIC_SPI0_IRQn = 30,
NVIC_I2C0_IRQn = 31,
}NVIC_IRQChannel;
typedef enum
{
NVIC_Priority_0 = 0x0 ,
NVIC_Priority_1 = 0x1 ,
NVIC_Priority_2 = 0x2 ,
NVIC_Priority_3 = 0x3 ,
}NVIC_IRQPriority;
typedef enum
{
SCB_LP_SleepOnExit = 0x02 ,
SCB_LP_SleepDeep = 0x04 ,
SCB_LP_SEVOPend = 0x10 ,
}SCB_TYPE_SCR;
typedef enum
{
SysTick_ClkS_Base = 0x0 ,
SysTick_ClkS_Cpu = 0x1 ,
}SYST_TYPE_CLKS;
typedef struct
{
uint32_t SysTick_Value;
SYST_TYPE_CLKS SysTick_ClkSource;
TYPE_FUNCEN SysTick_ITEnable;
}SYSTICK_InitStruType;
#define SysTick_Enable() (SysTick->CTRL |= 0x00000001)
#define SysTick_Disable() (SysTick->CTRL &= 0xFFFFFFFE)
void NVIC_Init(NVIC_IRQChannel Channel,NVIC_IRQPriority Priority,TYPE_FUNCEN Cmd);
void SCB_SystemLPConfig(SCB_TYPE_SCR LowPowerMode, TYPE_FUNCEN NewState);
uint32_t SCB_GetCpuID(void);
void SysTick_Init(SYSTICK_InitStruType* SysT_InitStruct);
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __LIBSCU_H
#define __LIBSCU_H
#include "system_ES8P508x.h"
#include "ES8P508x.h"
#include "type.h"
typedef enum
{
SCU_PINT0_IRQn = 0,
SCU_PINT1_IRQn = 1,
SCU_PINT2_IRQn = 2,
SCU_PINT3_IRQn = 3,
SCU_PINT4_IRQn = 4,
SCU_PINT5_IRQn = 5,
SCU_PINT6_IRQn = 6,
SCU_PINT7_IRQn = 7,
SCU_T16N0_IRQn = 8,
SCU_T16N1_IRQn = 9,
SCU_T16N2_IRQn = 10,
SCU_T16N3_IRQn = 11,
SCU_T32N0_IRQn = 12,
SCU_IWDT_IRQn = 14,
SCU_WWDT_IRQn = 15,
SCU_CCM_IRQn = 16,
SCU_PLK_IRQn = 17,
SCU_LVD_IRQn = 18,
SCU_KINT_IRQn = 19,
SCU_RTC_IRQn = 20,
SCU_ADC_IRQn = 21,
SCU_AES_IRQn = 23,
SCU_UART0_IRQn = 24,
SCU_UART1_IRQn = 25,
SCU_UART2_IRQn = 26,
SCU_UART3_IRQn = 27,
SCU_UART4_IRQn = 28,
SCU_UART5_IRQn = 29,
SCU_SPI0_IRQn = 30,
SCU_I2C0_IRQn = 31,
}SCU_TYPE_NMICS;
typedef enum
{
SCU_PWRC_PORF= 0X00001,
SCU_PWRC_RRCF = 0X00002,
SCU_PWRC_PORRSTF = 0x00004,
SCU_PWRC_BORF = 0x00008,
SCU_PWRC_WWDTRSTF = 0x00010,
SCU_PWRC_IWDTRSTF = 0x00020,
SCU_PWRC_MRSTF = 0x00040,
SCU_PWRC_SOFTRSTF = 0x00080,
}SCU_TYPE_PWRC;
typedef enum
{
SCU_LVDFlag_IF = 0x0100,
SCU_LVDFlag_Out = 0x8000,
}SCU_TYPE_LVD0CON;
typedef enum
{
SCU_SysClk_HRC = 0x0 ,
SCU_SysClk_XTAL = 0x1 ,
SCU_SysClk_PLL = 0x2 ,
}SCU_TYPE_SYSCLK;
typedef enum
{
CLK_SEL_HRC = 0x0,
CLK_SEL_LRC = 0x1,
CLK_SEL_XTAL = 0x2,
}SCU_TYPE_CLK_SEL;
typedef enum
{
PLL_HRC = 0x0,
PLL_LRC = 0x1,
PLL_XTAL = 0x2,
}PLL_TYPE_CLK;
typedef enum
{
SCU_PLL_HRC = 0x0 ,
SCU_PLL_LRC = 0x2 ,
SCU_PLL_XTAL_32K = 0x3 ,
SCU_PLL_XTAL_4M = 0x4 ,
SCU_PLL_XTAL_8M = 0x5,
SCU_PLL_XTAL_16M = 0x6,
SCU_PLL_XTAL_20M = 0x7,
} SCU_PLL_Origin;
typedef enum
{
SCU_PLL_32M = 0x0 ,
SCU_PLL_48M = 0x1 ,
} SCU_PLL_Out;
#define SCU_RegUnLock() (SCU->PROT.Word = 0x55AA6996)
#define SCU_RegLock() (SCU->PROT.Word = 0x00000000)
#define SCU_NMI_Enable() (SCU->NMICON.NMIEN = 0x1)
#define SCU_NMI_Disable() (SCU->NMICON.NMIEN = 0x0)
#define SCU_LVD_Enable() (SCU->LVDCON.EN = 0x1)
#define SCU_LVD_Disable() (SCU->LVDCON.EN = 0x0)
#define SCU_LVDFLT_Enable() (SCU->LVDCON.FLTEN = 0x1)
#define SCU_LVDFLT_Disable() (SCU->LVDCON.FLTEN = 0x0)
#define SCU_LVDVS_2V0() (SCU->LVDCON.VS = 0x0)
#define SCU_LVDVS_2V1() (SCU->LVDCON.VS = 0x1)
#define SCU_LVDVS_2V2() (SCU->LVDCON.VS = 0x2)
#define SCU_LVDVS_2V4() (SCU->LVDCON.VS = 0x3)
#define SCU_LVDVS_2V6() (SCU->LVDCON.VS = 0x4)
#define SCU_LVDVS_2V8() (SCU->LVDCON.VS = 0x5)
#define SCU_LVDVS_3V0() (SCU->LVDCON.VS = 0x6)
#define SCU_LVDVS_3V6() (SCU->LVDCON.VS = 0x7)
#define SCU_LVDVS_4V() (SCU->LVDCON.VS = 0x8)
#define SCU_LVDVS_4V6() (SCU->LVDCON.VS = 0x9)
#define SCU_LVDVS_2V3() (SCU->LVDCON.VS = 0xA)
#define SCU_LVDVS_LVDIN() (SCU->LVDCON.VS = 0xE)
#define SCU_LVDIT_Enable() (SCU->LVDCON.IE = 0x1)
#define SCU_LVDIT_Disable() (SCU->LVDCON.IE = 0x0)
#define SCU_LVDClearIFBit() (SCU->LVDCON.LVDIF = 1)
#define SCU_LVDIFS_Rise() (SCU->LVDCON.IFS = 0x0)
#define SCU_LVDIFS_Fall() (SCU->LVDCON.IFS = 0x1)
#define SCU_LVDIFS_High() (SCU->LVDCON.IFS = 0x2)
#define SCU_LVDIFS_Low() (SCU->LVDCON.IFS = 0x3)
#define SCU_LVDIFS_Change() (SCU->LVDCON.IFS = 0x4)
#define SCU_FlashWait_1Tclk() (SCU->FLASHWAIT.ACCT = 0x0)
#define SCU_FlashWait_2Tclk() (SCU->FLASHWAIT.ACCT = 0x1)
#define SCU_FlashWait_3Tclk() (SCU->FLASHWAIT.ACCT = 0x2)
#define SCU_FlashWait_4Tclk() (SCU->FLASHWAIT.ACCT = 0x3)
#define SCU_FlashWait_5Tclk() (SCU->FLASHWAIT.ACCT = 0x4)
#define SCU_FlashWait_6Tclk() (SCU->FLASHWAIT.ACCT = 0x5)
#define SCU_FlashWait_7Tclk() (SCU->FLASHWAIT.ACCT = 0x6)
#define SCU_FlashWait_8Tclk() (SCU->FLASHWAIT.ACCT = 0x7)
#define SCU_FlashWait_9Tclk() (SCU->FLASHWAIT.ACCT = 0x8)
#define SCU_FlashWait_10Tclk() (SCU->FLASHWAIT.ACCT = 0x9)
#define SCU_FlashWait_11Tclk() (SCU->FLASHWAIT.ACCT = 0xA)
#define SCU_FlashWait_12Tclk() (SCU->FLASHWAIT.ACCT = 0xB)
#define SCU_FlashWait_13Tclk() (SCU->FLASHWAIT.ACCT = 0xC)
#define SCU_FlashWait_14Tclk() (SCU->FLASHWAIT.ACCT = 0xD)
#define SCU_FlashWait_15Tclk() (SCU->FLASHWAIT.ACCT = 0xE)
#define SCU_FlashWait_16Tclk() (SCU->FLASHWAIT.ACCT = 0xF)
#define SCU_SysClk_Div1() (SCU->SCLKEN0.SYSCLK_DIV = 0)
#define SCU_SysClk_Div2() (SCU->SCLKEN0.SYSCLK_DIV = 1)
#define SCU_SysClk_Div4() (SCU->SCLKEN0.SYSCLK_DIV = 2)
#define SCU_SysClk_Div8() (SCU->SCLKEN0.SYSCLK_DIV = 3)
#define SCU_SysClk_Div16() (SCU->SCLKEN0.SYSCLK_DIV = 4)
#define SCU_SysClk_Div32() (SCU->SCLKEN0.SYSCLK_DIV = 5)
#define SCU_SysClk_Div64() (SCU->SCLKEN0.SYSCLK_DIV = 6)
#define SCU_SysClk_Div128() (SCU->SCLKEN0.SYSCLK_DIV = 7)
#define SCU_HRC_Enable() (SCU->SCLKEN1.HRC_EN = 1)
#define SCU_HRC_Disable() (SCU->SCLKEN1.HRC_EN = 0)
#define SCU_XTAL_Enable() (SCU->SCLKEN1.XTAL_EN = 1)
#define SCU_XTAL_Disable() (SCU->SCLKEN1.XTAL_EN = 0)
#define SCU_PLL_Enable() (SCU->SCLKEN1.PLL_EN = 1)
#define SCU_PLL_Disable() (SCU->SCLKEN1.PLL_EN = 0)
#define SCU_SCUCLK_Enable() (SCU->PCLKEN0.SCU_EN = 1)
#define SCU_SCUCLK_Disable() (SCU->PCLKEN0.SCU_EN = 0)
#define SCU_GPIOCLK_Enable() (SCU->PCLKEN0.GPIO_EN = 1)
#define SCU_GPIOCLK_Disable() (SCU->PCLKEN0.GPIO_EN = 0)
#define SCU_IAPCLK_Enable() (SCU->PCLKEN0.IAP_EN = 1)
#define SCU_IAPCLK_Disable() (SCU->PCLKEN0.IAP_EN = 0)
#define SCU_CRCCLK_Enable() (SCU->PCLKEN0.CRC_EN = 1)
#define SCU_CRCCLK_Disable() (SCU->PCLKEN0.CRC_EN = 0)
#define SCU_ADCCLK_Enable() (SCU->PCLKEN0.ADC_EN = 1)
#define SCU_ADCCLK_Disable() (SCU->PCLKEN0.ADC_EN = 0)
#define SCU_RTCCLK_Enable() (SCU->PCLKEN0.RTC_EN = 1)
#define SCU_RTCCLK_Disable() (SCU->PCLKEN0.RTC_EN = 0)
#define SCU_IWDTCLK_Enable() (SCU->PCLKEN0.IWDT_EN = 1)
#define SCU_IWDTCLK_Disable() (SCU->PCLKEN0.IWDT_EN = 0)
#define SCU_WWDTCLK_Enable() (SCU->PCLKEN0.WWDT_EN = 1)
#define SCU_WWDTCLK_Disable() (SCU->PCLKEN0.WWDT_EN = 0)
#define SCU_AESCLK_Enable() (SCU->PCLKEN0.AES_EN = 1)
#define SCU_AESCLK_Disable() (SCU->PCLKEN0.AES_EN = 0)
#define SCU_T16N0CLK_Enable() (SCU->PCLKEN1.T16N0_EN = 1)
#define SCU_T16N0CLK_Disable() (SCU->PCLKEN1.T16N0_EN = 0)
#define SCU_T16N1CLK_Enable() (SCU->PCLKEN1.T16N1_EN = 1)
#define SCU_T16N1CLK_Disable() (SCU->PCLKEN1.T16N1_EN = 0)
#define SCU_T16N2CLK_Enable() (SCU->PCLKEN1.T16N2_EN = 1)
#define SCU_T16N2CLK_Disable() (SCU->PCLKEN1.T16N2_EN = 0)
#define SCU_T16N3CLK_Enable() (SCU->PCLKEN1.T16N3_EN = 1)
#define SCU_T16N3CLK_Disable() (SCU->PCLKEN1.T16N3_EN = 0)
#define SCU_T32N0CLK_Enable() (SCU->PCLKEN1.T32N0_EN = 1)
#define SCU_T32N0CLK_Disable() (SCU->PCLKEN1.T32N0_EN = 0)
#define SCU_UART0CLK_Enable() (SCU->PCLKEN1.UART0_EN = 1)
#define SCU_UART0CLK_Disable() (SCU->PCLKEN1.UART0_EN = 0)
#define SCU_UART1CLK_Enable() (SCU->PCLKEN1.UART1_EN = 1)
#define SCU_UART1CLK_Disable() (SCU->PCLKEN1.UART1_EN = 0)
#define SCU_UART2CLK_Enable() (SCU->PCLKEN1.UART2_EN = 1)
#define SCU_UART2CLK_Disable() (SCU->PCLKEN1.UART2_EN = 0)
#define SCU_UART3CLK_Enable() (SCU->PCLKEN1.UART3_EN = 1)
#define SCU_UART3CLK_Disable() (SCU->PCLKEN1.UART3_EN = 0)
#define SCU_UART4CLK_Enable() (SCU->PCLKEN1.UART4_EN = 1)
#define SCU_UART4CLK_Disable() (SCU->PCLKEN1.UART4_EN = 0)
#define SCU_UART5CLK_Enable() (SCU->PCLKEN1.UART5_EN = 1)
#define SCU_UART5CLK_Disable() (SCU->PCLKEN1.UART5_EN = 0)
#define SCU_SPI0CLK_Enable() (SCU->PCLKEN1.SPI0_EN = 1)
#define SCU_SPI0CLK_Disable() (SCU->PCLKEN1.SPI0_EN = 0)
#define SCU_IIC0CLK_Enable() (SCU->PCLKEN1.I2C0_EN = 1)
#define SCU_IIC0CLK_Disable() (SCU->PCLKEN1.I2C0_EN = 0)
#define SCU_TBLRemap_Enable() (SCU->TBLREMAPEN.EN= 1)
#define SCU_TBLRemap_Disable() (SCU->TBLREMAPEN.EN= 0)
#define SCU_TBL_Offset(x) (SCU->TBLOFF.TBLOFF = (uint32_t)x)
void SCU_NMISelect(SCU_TYPE_NMICS NMI_Type);
FlagStatus SCU_GetPWRCFlagStatus(SCU_TYPE_PWRC PWRC_Flag);
void SCU_ClearPWRCFlagBit(SCU_TYPE_PWRC PWRC_Flag);
FlagStatus SCU_GetLVDFlagStatus(SCU_TYPE_LVD0CON LVD_Flag);
void SCU_SysClkSelect(SCU_TYPE_SYSCLK Sysclk);
SCU_TYPE_SYSCLK SCU_GetSysClk(void);
FlagStatus SCU_HRCReadyFlag(void);
FlagStatus SCU_XTALReadyFlag(void);
FlagStatus SCU_PLLReadyFlag(void);
void SystemClockConfig(void);
void SystemClockConfig_1(void);
void DeviceClockAllEnable(void);
void DeviceClockAllDisable(void);
void SystemClockSelect(SCU_TYPE_SYSCLK SYSCLKx , SCU_TYPE_CLK_SEL CLK_SEL);
void SysclkPLL(PLL_TYPE_CLK CLKx);
void PLLClock_Config(TYPE_FUNCEN pll_en , SCU_PLL_Origin pll_origin ,SCU_PLL_Out pll_out,TYPE_FUNCEN sys_pll);
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __LIBSPI_H__
#define __LIBSPI_H__
#include "system_ES8P508x.h"
#include "ES8P508x.h"
#include "type.h"
typedef enum
{
SPI_RiseSendFallRec = 0x0 ,
SPI_FallSendRiseRec = 0x1 ,
SPI_RiseRecFallSend = 0x2 ,
SPI_FallRecRiseSend = 0x3 ,
}SPI_TYPE_DFS;
typedef enum
{
SPI_Mode_Master = 0x0 ,
SPI_Mode_Slave = 0x1 ,
}SPI_TYPE_MODE;
typedef struct
{
uint32_t SPI_Freq;
SPI_TYPE_DFS SPI_Df;
SPI_TYPE_MODE SPI_Mode;
uint8_t SPI_DW;
TYPE_FUNCEN SPI_DelayRec;
TYPE_FUNCEN SPI_DelaySend;
uint8_t SPI_SendDelayPeroid;
}SPI_InitStruType;
typedef enum
{
SPI_Flag_TB = 0x00000001,
SPI_Flag_RB = 0x00000002,
SPI_Flag_TE = 0x00000004,
SPI_Flag_RO = 0x00000008,
SPI_Flag_ID = 0x00000010,
SPI_Flag_NSSIF = 0x00000020,
SPI_Flag_TBWE = 0x00000040,
SPI_Flag_NSS = 0x00000080,
SPI_Flag_TBEF0 = 0x00000100,
SPI_Flag_TBEF1 = 0x00000200,
SPI_Flag_TBEF2 = 0x00000400,
SPI_Flag_TBEF3 = 0x00000800,
SPI_Flag_RBFF0 = 0x00001000,
SPI_Flag_RBFF1 = 0x00002000,
SPI_Flag_RBFF2 = 0x00004000,
SPI_Flag_RBFF3 = 0x00008000,
SPI_Flag_IDLE = 0x00010000,
SPI_Flag_TMS = 0x00020000,
}SPI_TYPE_FLAG;
typedef enum
{
SPI_IType_BYTE = 0x0 ,
SPI_IType_HALFWORD = 0x1 ,
SPI_IType_WORD = 0x2 ,
}SPI_TYPE_TRBIM;
typedef enum
{
SPI_IT_TB = 0x01 ,
SPI_IT_RB = 0x02 ,
SPI_IT_TE = 0x04 ,
SPI_IT_RO = 0x08 ,
SPI_IT_ID = 0x10 ,
SPI_IT_NSS = 0x20 ,
SPI_IT_TBWE = 0x40 ,
}SPI_TYPE_IT;
typedef enum
{
SPI_Clr_TE = 0x04 ,
SPI_Clr_RO = 0x08 ,
SPI_Clr_ID = 0x10 ,
SPI_Clr_NSS = 0x20 ,
SPI_Clr_TBWE = 0x40 ,
}SPI_CLR_IF;
#define SPI_Enable() (SPI0->CON.EN = 1)
#define SPI_Disable() (SPI0->CON.EN = 0)
#define SPI_RecEnable() (SPI0->CON.REN = 1)
#define SPI_RecDisable() (SPI0->CON.REN = 0)
#define SPI_Rst() (SPI0->CON.RST = 1)
#define SPI_RX_CLR() (SPI0->CON.RXCLR = 1)
#define SPI_TX_CLR() (SPI0->CON.TXCLR = 1)
void SPI_Init(SPI_InitStruType* SPI_InitStruct);
void SPI_ITConfig(SPI_TYPE_IT SPI_IE,TYPE_FUNCEN NewState);
void SPI_DataFormatConfig(SPI_TYPE_DFS Type);
void SPI_SendByte(uint8_t Temp);
void SPI_SendHalfWord(uint16_t Temp);
void SPI_SendWord(uint32_t Temp);
uint8_t SPI_RecByte(void);
uint16_t SPI_RecHalfWord(void);
uint32_t SPI_RecWord(void);
void SPI_TBIMConfig(SPI_TYPE_TRBIM Type);
void SPI_RBIMConfig(SPI_TYPE_TRBIM Type);
FlagStatus SPI_GetFlagStatus(SPI_TYPE_FLAG Flag);
ITStatus SPI_GetITStatus(SPI_TYPE_IT Flag);
void SPI_ClearITPendingBit(SPI_CLR_IF Flag);
#endif
/*************************END OF FILE**********************/

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/******************************************************************************************
* Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
*******************************************************************************************/
#ifndef __LIBTIMER_H__
#define __LIBTIMER_H__
#include "ES8P508x.h"
#include "type.h"
typedef enum
{
TIM_ClkS_PCLK = 0x0 ,
TIM_ClkS_CK0 = 0x1 ,
TIM_ClkS_CK1 = 0x2 ,
}TIM_TYPE_CLKS;
typedef enum
{
TIM_EDGE_Rise = 0x0 ,
TIM_EDGE_Fall = 0x1 ,
TIM_EDGE_All = 0x2 ,
}TIM_TYPE_EDGE;
typedef enum
{
TIM_Mode_TC0 = 0x0 ,
TIM_Mode_TC1 = 0x1 ,
TIM_Mode_CAP = 0x2 ,
TIM_Mode_PWM = 0x3 ,
}TIM_TYPE_MODE;
typedef struct
{
TIM_TYPE_CLKS TIM_ClkS;
TYPE_FUNCEN TIM_SYNC;
TIM_TYPE_EDGE TIM_EDGE;
TIM_TYPE_MODE TIM_Mode;
}TIM_BaseInitStruType;
typedef enum
{
TIM_Go_No = 0x0 ,
TIM_Hold_Int = 0x1 ,
TIM_Clr_Int = 0x2 ,
TIM_Go_Int = 0x3 ,
}TIM_TYPE_MATCON;
typedef enum
{
TIM_Out_Hold = 0x0 ,
TIM_Out_Low = 0x1 ,
TIM_Out_High = 0x2 ,
TIM_Out_Switch = 0x3 ,
}TIM_TYPE_MATOUT;
typedef enum
{
TIM_CapTime_1 = 0x0 ,
TIM_CapTime_2 = 0x1 ,
TIM_CapTime_3 = 0x2 ,
TIM_CapTime_4 = 0x3 ,
TIM_CapTime_5 = 0x4 ,
TIM_CapTime_6 = 0x5 ,
TIM_CapTime_7 = 0x6 ,
TIM_CapTime_8 = 0x7 ,
TIM_CapTime_9 = 0x8 ,
TIM_CapTime_10 = 0x9 ,
TIM_CapTime_11 = 0xA ,
TIM_CapTime_12 = 0xB ,
TIM_CapTime_13 = 0xC ,
TIM_CapTime_14 = 0xD ,
TIM_CapTime_15 = 0xE ,
TIM_CapTime_16 = 0xF ,
}TIM_TYPE_CAPT;
typedef enum
{
POSITIVE = 0X00,
NEGATIVE = 0X01,
}T16Nx_PWMOUT_POLAR_Type;
typedef struct
{
TYPE_FUNCEN T16Nx_MOE0;
TYPE_FUNCEN T16Nx_MOE1;
T16Nx_PWMOUT_POLAR_Type T16Nx_POL0;
T16Nx_PWMOUT_POLAR_Type T16Nx_POL1;
}T16Nx_PWMInitStruType;
typedef struct
{
TYPE_FUNCEN TIM_CapRise;
TYPE_FUNCEN TIM_CapFall;
TYPE_FUNCEN TIM_CapIS0;
TYPE_FUNCEN TIM_CapIS1;
TIM_TYPE_CAPT TIM_CapTime;
}TIM_CapInitStruType;
typedef enum
{
PWMBKOUT_Low = 0,
PWMBKOUT_High = 1,
}T16Nx_PWMBKOUT_LEVEl;
typedef enum
{
PWMBKP_High = 0,
PWMBKP_Low = 1,
}T16Nx_PWMBKP_LEVEl;
typedef enum
{
PWMBKPS_PINT0 = 0,
PWMBKPS_PINT1 = 1,
PWMBKPS_PINT2 = 2,
PWMBKPS_PINT3 = 3,
PWMBKPS_PINT4 = 4,
PWMBKPS_PINT5 = 5,
PWMBKPS_PINT6 = 6,
PWMBKPS_PINT7 = 7,
}T16Nx_PWMBKP_S;
typedef struct
{
T16Nx_PWMBKOUT_LEVEl T16Nx_PWMBKL0;
T16Nx_PWMBKOUT_LEVEl T16Nx_PWMBKL1;
T16Nx_PWMBKP_S T16Nx_PWMBKS;
T16Nx_PWMBKP_LEVEl T16Nx_PWMBKPS;
TYPE_FUNCEN T16Nx_PWMBKEN;
}T16Nx_PWMBK_Type;
typedef enum
{
TIM_IT_MAT0 = 0x01 ,
TIM_IT_MAT1 = 0x02 ,
TIM_IT_MAT2 = 0x04 ,
TIM_IT_MAT3 = 0x08 ,
TIM_IT_N = 0x10 ,
TIM_IT_CAP0 = 0x20 ,
TIM_IT_CAP1 = 0x40 ,
TIM_IT_PBK = 0x80 ,
}TIM_TYPE_IT;
typedef enum
{
TIM_IF_MAT0 = 0x01 ,
TIM_IF_MAT1 = 0x02 ,
TIM_IF_MAT2 = 0x04 ,
TIM_IF_MAT3 = 0x08 ,
TIM_IF_N = 0x10 ,
TIM_IF_CAP0 = 0x20 ,
TIM_IF_CAP1 = 0x40 ,
TIM_IF_PBK = 0x80 ,
}TIM_TYPE_IF;
typedef enum
{
TIM_MAT0 = 0x00 ,
TIM_MAT1 = 0x01 ,
TIM_MAT2 = 0x02 ,
TIM_MAT3 = 0x03 ,
}TIM_TYPE_MATX;
typedef enum
{
T16Nx_MAT0 = 0x02,
T16Nx_MAT1 = 0x04,
T16Nx_MAT2 = 0x20,
T16Nx_MAT3 = 0x40,
}T16Nx_PWMTRG_type;
#define T16N0_Enable() (T16N0->CON0.EN = 1)
#define T16N1_Enable() (T16N1->CON0.EN = 1)
#define T16N2_Enable() (T16N2->CON0.EN = 1)
#define T16N3_Enable() (T16N3->CON0.EN = 1)
#define T32N0_Enable() (T32N0->CON0.EN = 1)
#define T16N0_Disable() (T16N0->CON0.EN = 0)
#define T16N1_Disable() (T16N1->CON0.EN = 0)
#define T16N2_Disable() (T16N2->CON0.EN = 0)
#define T16N3_Disable() (T16N3->CON0.EN = 0)
#define T32N0_Disable() (T32N0->CON0.EN = 0)
#define T16N0_ASYNCWR_Enable() (T16N0->CON0.ASYWEN = 1)
#define T16N1_ASYNCWR_Enable() (T16N1->CON0.ASYWEN = 1)
#define T16N2_ASYNCWR_Enable() (T16N2->CON0.ASYWEN = 1)
#define T16N3_ASYNCWR_Enable() (T16N3->CON0.ASYWEN = 1)
#define T32N0_ASYNCWR_Enable() (T32N0->CON0.ASYNCWREN = 1)
#define T16N0_ASYNCWR_Disable() (T16N0->CON0.ASYWEN= 0)
#define T16N1_ASYNCWR_Disable() (T16N1->CON0.ASYWEN = 0)
#define T16N2_ASYNCWR_Disable() (T16N2->CON0.ASYWEN = 0)
#define T16N3_ASYNCWR_Disable() (T16N3->CON0.ASYWEN = 0)
#define T32N0_ASYNCWR_Disable() (T32N0->CON0.ASYNCWREN = 0)
#define T16N0_PwmOut0_Enable() (T16N0->CON2.MOE0 = 1)
#define T16N1_PwmOut0_Enable() (T16N1->CON2.MOE0 = 1)
#define T16N2_PwmOut0_Enable() (T16N2->CON2.MOE0 = 1)
#define T16N3_PwmOut0_Enable() (T16N3->CON2.MOE0 = 1)
#define T32N0_PwmOut0_Enable() (T32N0->CON2.MOE0 = 1)
#define T16N0_PwmOut1_Enable() (T16N0->CON2.MOE1 = 1)
#define T16N1_PwmOut1_Enable() (T16N1->CON2.MOE1 = 1)
#define T16N2_PwmOut1_Enable() (T16N2->CON2.MOE1 = 1)
#define T16N3_PwmOut1_Enable() (T16N3->CON2.MOE1 = 1)
#define T32N0_PwmOut1_Enable() (T32N0->CON2.MOE1 = 1)
#define T16N0_PwmOut0_Disable() (T16N0->CON2.MOE0 = 0)
#define T16N1_PwmOut0_Disable() (T16N1->CON2.MOE0 = 0)
#define T16N2_PwmOut0_Disable() (T16N2->CON2.MOE0 = 0)
#define T16N3_PwmOut0_Disable() (T16N3->CON2.MOE0 = 0)
#define T32N0_PwmOut0_Disable() (T32N0->CON2.MOE0 = 0)
#define T16N0_PwmOut1_Disable() (T16N0->CON2.MOE1 = 0)
#define T16N1_PwmOut1_Disable() (T16N1->CON2.MOE1 = 0)
#define T16N2_PwmOut1_Disable() (T16N2->CON2.MOE1 = 0)
#define T16N3_PwmOut1_Disable() (T16N3->CON2.MOE1 = 0)
#define T32N0_PwmOut1_Disable() (T32N0->CON2.MOE1 = 0)
void T16Nx_BaseInit(T16N_TypeDef* T16Nx,TIM_BaseInitStruType* TIM_BaseInitStruct);
void T16Nx_CapInit(T16N_TypeDef* T16Nx,TIM_CapInitStruType* TIM_CapInitStruct);
void T16Nx_MAT0ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type);
void T16Nx_MAT1ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type);
void T16Nx_MAT2ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type);
void T16Nx_MAT3ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type);
void T16Nx_MAT0Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type);
void T16Nx_MAT1Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type);
void T16Nx_MAT2Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type);
void T16Nx_MAT3Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type);
void T16Nx_ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState);
void T16Nx_PWMOutConfig(T16N_TypeDef* T16Nx,T16Nx_PWMInitStruType* T16Nx_PWMInitStruct);
void T16Nx_PWMBK_Config(T16N_TypeDef* T16Nx,T16Nx_PWMBK_Type* type);
void T16Nx_TRG_Config(T16N_TypeDef* T16Nx,T16Nx_PWMTRG_type Type,TYPE_FUNCEN NewState);
FlagStatus T16Nx_GetPWMBKF(T16N_TypeDef* T16Nx);
void T16Nx_ResetPWMBKF(T16N_TypeDef* T16Nx);
void T16Nx_SetCNT(T16N_TypeDef* T16Nx,uint16_t Value);
void T16Nx_SetPRECNT(T16N_TypeDef* T16Nx,uint8_t Value);
void T16Nx_SetPREMAT(T16N_TypeDef* T16Nx,uint8_t Value);
void T16Nx_SetMAT0(T16N_TypeDef* T16Nx,uint16_t Value);
void T16Nx_SetMAT1(T16N_TypeDef* T16Nx,uint16_t Value);
void T16Nx_SetMAT2(T16N_TypeDef* T16Nx,uint16_t Value);
void T16Nx_SetMAT3(T16N_TypeDef* T16Nx,uint16_t Value);
uint16_t T16Nx_GetMAT0(T16N_TypeDef* T16Nx);
uint16_t T16Nx_GetMAT1(T16N_TypeDef* T16Nx);
uint16_t T16Nx_GetMAT2(T16N_TypeDef* T16Nx);
uint16_t T16Nx_GetMAT3(T16N_TypeDef* T16Nx);
uint16_t T16Nx_GetCNT(T16N_TypeDef* T16Nx);
uint8_t T16Nx_GetPRECNT(T16N_TypeDef* T16Nx);
FlagStatus T16Nx_GetFlagStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag);
ITStatus T16Nx_GetITStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IT TIM_Flag);
void T16Nx_ClearIFPendingBit(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag);
void T32Nx_BaseInit(T32N_TypeDef* T32Nx,TIM_BaseInitStruType* TIM_BaseInitStruct);
void T32Nx_CapInit(T32N_TypeDef* T32Nx,TIM_CapInitStruType* TIM_CapInitStruct);
void T32Nx_MAT0ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type);
void T32Nx_MAT1ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type);
void T32Nx_MAT2ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type);
void T32Nx_MAT3ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type);
void T32Nx_MAT0Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type);
void T32Nx_MAT1Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type);
void T32Nx_MAT2Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type);
void T32Nx_MAT3Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type);
void T32Nx_ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState);
void T32Nx_SetCNT(T32N_TypeDef* T16Nx,uint32_t Value);
void T32Nx_SetPRECNT(T32N_TypeDef* T32Nx,uint8_t Value);
void T32Nx_SetPREMAT(T32N_TypeDef* T32Nx,uint8_t Value);
void T32Nx_SetMAT0(T32N_TypeDef* T32Nx,uint32_t Value);
void T32Nx_SetMAT1(T32N_TypeDef* T32Nx,uint32_t Value);
void T32Nx_SetMAT2(T32N_TypeDef* T32Nx,uint32_t Value);
void T32Nx_SetMAT3(T32N_TypeDef* T32Nx,uint32_t Value);
uint32_t T32Nx_GetMAT0(T32N_TypeDef* T32Nx);
uint32_t T32Nx_GetMAT1(T32N_TypeDef* T32Nx);
uint32_t T32Nx_GetMAT2(T32N_TypeDef* T32Nx);
uint32_t T32Nx_GetMAT3(T32N_TypeDef* T32Nx);
uint32_t T32Nx_GetCNT(T32N_TypeDef* T32Nx);
uint8_t T32Nx_GetPRECNT(T32N_TypeDef* T32Nx);
FlagStatus T32Nx_GetFlagStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag);
ITStatus T32Nx_GetITStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IT TIM_Flag);
void T32Nx_ClearIFPendingBit(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag);
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#ifndef __LIBUART_H__
#define __LIBUART_H__
#include "ES8P508x.h"
#include "type.h"
#include "system_ES8P508x.h"
typedef enum
{
UART_StopBits_1 = 0x0 ,
UART_StopBits_2 = 0x1 ,
}UART_TYPE_TXFS;
typedef enum
{
UART_DataMode_7 = 0x0 ,
UART_DataMode_8 = 0x1 ,
UART_DataMode_9 = 0x2 ,
UART_DataMode_7Odd = 0x4 ,
UART_DataMode_7Even = 0x5 ,
UART_DataMode_8Odd = 0x6 ,
UART_DataMode_8Even = 0x7 ,
}UART_TYPE_DATAMOD;
typedef enum
{
UART_Polar_Normal = 0x0 ,
UART_Polar_Opposite = 0x1 ,
}UART_TYPE_RTXP;
typedef enum
{
UART_Clock_1 = 0x1 ,
UART_Clock_2 = 0x2 ,
UART_Clock_4 = 0x3 ,
UART_Clock_8 = 0x4 ,
}UART_TYPE_BCS;
typedef struct
{
UART_TYPE_TXFS UART_StopBits;
UART_TYPE_DATAMOD UART_TxMode;
UART_TYPE_RTXP UART_TxPolar;
UART_TYPE_DATAMOD UART_RxMode;
UART_TYPE_RTXP UART_RxPolar;
uint32_t UART_BaudRate;
UART_TYPE_BCS UART_ClockSet;
}UART_InitStruType;
typedef enum
{
UART_IT_TB = 0x0001 ,
UART_IT_RB = 0x0002 ,
UART_IT_RO = 0x0004 ,
UART_IT_FE = 0x0008 ,
UART_IT_PE = 0x0010 ,
UART_IT_TBWE = 0x0020 ,
UART_IT_TXIDLE = 0x1000 ,
UART_IT_RXIDLE = 0x2000 ,
}UART_TYPE_IT;
typedef enum
{
UART_FLAG_TB = 0x0001 ,
UART_FLAG_RB = 0x0002 ,
UART_FLAG_RO = 0x0004 ,
UART_FLAG_FE = 0x0008 ,
UART_FLAG_PE = 0x0010 ,
UART_FLAG_TBWE = 0x0020 ,
UART_FLAG_TXIDLE = 0x1000 ,
UART_FLAG_RXIDLE = 0x2000 ,
}UART_TYPE_FLAG;
typedef enum
{
UART_Clr_RO = 0x0004 ,
UART_Clr_FE = 0x0008 ,
UART_Clr_PE = 0x0010 ,
UART_Clr_TBWE = 0x0020 ,
}UART_CLR_IF;
typedef enum
{
UART_TRBIM_Byte = 0x0 ,
UART_TRBIM_HalfWord = 0x1 ,
UART_TRBIM_Word = 0x2 ,
}UART_TYPE_TRBIM;
#define UART0_TxEnable() (UART0->CON.TXEN = 1)
#define UART1_TxEnable() (UART1->CON.TXEN = 1)
#define UART2_TxEnable() (UART2->CON.TXEN = 1)
#define UART3_TxEnable() (UART3->CON.TXEN = 1)
#define UART0_TxDisable() (UART0->CON.TXEN = 0)
#define UART1_TxDisable() (UART1->CON.TXEN = 0)
#define UART2_TxDisable() (UART2->CON.TXEN = 0)
#define UART3_TxDisable() (UART3->CON.TXEN = 0)
#define UART0_RxEnable() (UART0->CON.RXEN = 1)
#define UART1_RxEnable() (UART1->CON.RXEN = 1)
#define UART2_RxEnable() (UART2->CON.RXEN = 1)
#define UART3_RxEnable() (UART3->CON.RXEN = 1)
#define UART0_RxDisable() (UART0->CON.RXEN = 0)
#define UART1_RxDisable() (UART1->CON.RXEN = 0)
#define UART2_RxDisable() (UART2->CON.RXEN = 0)
#define UART3_RxDisable() (UART3->CON.RXEN = 0)
#define UART0_TxRst() (UART0->CON.TRST = 1)
#define UART1_TxRst() (UART1->CON.TRST = 1)
#define UART2_TxRst() (UART2->CON.TRST = 1)
#define UART3_TxRst() (UART3->CON.TRST = 1)
#define UART0_RxRst() (UART0->CON.RRST = 1)
#define UART1_RxRst() (UART1->CON.RRST = 1)
#define UART2_RxRst() (UART2->CON.RRST = 1)
#define UART3_RxRst() (UART3->CON.RRST = 1)
void UART_Init(UART_TypeDef* UARTx,UART_InitStruType* UART_InitStruct);
void UART_ITConfig(UART_TypeDef* UARTx,UART_TYPE_IT UART_IT,TYPE_FUNCEN NewState);
void UART_TBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type);
void UART_RBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type);
void UART_SendByte(UART_TypeDef* UARTx,uint8_t Temp08);
void UART_SendHalfWord(UART_TypeDef* UARTx,uint16_t Temp16);
void UART_SendWord(UART_TypeDef* UARTx,uint32_t Temp32);
uint8_t UART_RecByte(UART_TypeDef* UARTx);
uint16_t UART_RecHalfWord(UART_TypeDef* UARTx);
uint32_t UART_RecWord(UART_TypeDef* UARTx);
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx,UART_TYPE_FLAG UART_Flag);
ITStatus UART_GetITStatus(UART_TypeDef* UARTx,UART_TYPE_IT UART_Flag);
void UART_ClearITPendingBit(UART_TypeDef* UARTx,UART_CLR_IF UART_Flag);
#endif
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#ifndef __LIBWDT_H__
#define __LIBWDT_H__
#include "system_ES8P508x.h"
#include "ES8P508x.h"
#include "type.h"
typedef enum
{
WDT_CLOCK_PCLK = 0x0,
WDT_CLOCK_WDT = 0x1,
} WDT_TYPE_CLKS;
typedef struct
{
uint32_t WDT_Tms;
TYPE_FUNCEN WDT_IE;
TYPE_FUNCEN WDT_Rst;
WDT_TYPE_CLKS WDT_Clock;
} IWDT_InitStruType;
typedef enum
{
WDT_WIN_25 = 0x0,
WDT_WIN_50 = 0x1,
WDT_WIN_75 = 0x2,
WDT_WIN_100 = 0x3,
} WDT_TYPE_WIN;
typedef struct
{
uint32_t WDT_Tms;
TYPE_FUNCEN WDT_IE;
TYPE_FUNCEN WDT_Rst;
WDT_TYPE_CLKS WDT_Clock;
WDT_TYPE_WIN WDT_Win;
} WWDT_InitStruType;
#define IWDT_RegUnLock() (IWDT->LOCK.Word = 0x1ACCE551)
#define IWDT_RegLock() (IWDT->LOCK.Word = 0x0)
#define IWDT_Enable() {IWDT_RegUnLock();IWDT->CON.EN = 1;IWDT_RegLock();}
#define IWDT_Disable() {IWDT_RegUnLock();IWDT->CON.EN = 0;IWDT_RegLock();}
#define IWDT_Clear() {IWDT_RegUnLock();IWDT->INTCLR.INTCLR = 0;IWDT_RegLock();}
#define IWDT_ITEnable() {IWDT_RegUnLock();IWDT->CON.IE = 1;IWDT_RegLock();}
#define IWDT_ITDisable() {IWDT_RegUnLock();IWDT->CON.IE = 0;IWDT_RegLock();}
#define IWDT_RstEnable() {IWDT_RegUnLock();IWDT->CON.RSTEN = 1;IWDT_RegLock();}
#define IWDT_RstDisable() {IWDT_RegUnLock();IWDT->CON.RSTEN = 0;IWDT_RegLock();}
#define IWDT_CLOCK_PCLK() {IWDT_RegUnLock();IWDT->CON.CLKS = 0;IWDT_RegLock();}
#define IWDT_CLOCK_WDT() {IWDT_RegUnLock();IWDT->CON.CLKS = 1;IWDT_RegLock();}
#define WWDT_RegUnLock() (WWDT->LOCK.Word = 0x1ACCE551)
#define WWDT_RegLock() (WWDT->LOCK.Word = 0x0)
#define WWDT_Enable() {WWDT_RegUnLock();WWDT->CON.EN = 1;WWDT_RegLock();}
#define WWDT_Disable() {WWDT_RegUnLock();WWDT->CON.EN = 0;WWDT_RegLock();}
#define WWDT_Clear() {WWDT_RegUnLock();WWDT->INTCLR.INTCLR = 0;WWDT_RegLock();}
#define WWDT_ITEnable() {WWDT_RegUnLock();WWDT->CON.IE = 1;WWDT_RegLock();}
#define WWDT_ITDisable() {WWDT_RegUnLock();WWDT->CON.IE = 0;WWDT_RegLock();}
#define WWDT_RstEnable() {WWDT_RegUnLock();WWDT->CON.RSTEN = 1;WWDT_RegLock();}
#define WWDT_RstDisable() {WWDT_RegUnLock();WWDT->CON.RSTEN = 0;WWDT_RegLock();}
#define WWDT_CLOCK_PCLK() {WWDT_RegUnLock();WWDT->CON.CLKS = 0;WWDT_RegLock();}
#define WWDT_CLOCK_WDT() {WWDT_RegUnLock();WWDT->CON.CLKS = 1;WWDT_RegLock();}
void IWDT_Init(IWDT_InitStruType *IWDT_InitStruct);
void IWDT_SetReloadValue(uint32_t Value);
uint32_t IWDT_GetValue(void);
FlagStatus IWDT_GetFlagStatus(void);
FlagStatus IWDT_GetITStatus(void);
void WWDT_Init(WWDT_InitStruType *WDT_InitStruct);
void WWDT_SetReloadValue(uint32_t Value);
uint32_t WWDT_GetValue(void);
FlagStatus WWDT_GetFlagStatus(void);
FlagStatus WWDT_GetITStatus(void);
#endif
/*************************END OF FILE**********************/

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/*********************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
**********************************************************/
#ifndef __TYPE_H__
#define __TYPE_H__
typedef enum {DISABLE = 0, ENABLE = !DISABLE} TYPE_FUNCEN,FuncState,TYPE_PINTIE,TYPE_PINTMASK;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, PinStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
#endif

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#include "lib_adc.h"
void ADC_Init(ADC_InitStruType * ADC_InitStruct)
{
ADC->CON1.CLKS = ADC_InitStruct->ADC_ClkS;
ADC->CON1.CLKDIV = ADC_InitStruct->ADC_ClkDiv;
ADC->CON1.VREFP = ADC_InitStruct->ADC_VrefP;
ADC->CON1.SMPS = ADC_InitStruct->ADC_SampS;
ADC->CON1.ST = ADC_InitStruct->ADC_SampClk;
ADC->CON1.HSEN = ADC_InitStruct->ADC_ConvSpeed;
ADC->CHS.CHS = ADC_InitStruct->ADC_ChS;
ADC->VREFCON.IREF_EN = ADC_InitStruct->ADC_IREF_EN;
ADC->VREFCON.VREF_EN = ADC_InitStruct->ADC_VREF_EN;
ADC->CON1.VCMBUF_EN = ADC_InitStruct->ADC_VCMBUF_EN;
ADC->CON1.VREFN = ADC_InitStruct->ADC_VREFN;
ADC->CON1.VRBUF_EN = ADC_InitStruct->ADC_VRBUF_EN;
}
void ADC_Set_CH(ADC_TYPE_CHS AdcCH)
{
ADC->CHS.CHS = AdcCH;
}
uint16_t ADC_GetConvValue(void)
{
return ((uint16_t)ADC->DR.DR);
}
FlagStatus ADC_GetConvStatus(void)
{
FlagStatus bitstatus = RESET;
if ((ADC->CON0.TRIG != (uint32_t)RESET))
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
ErrorStatus ADC_ACPConfig(ADC_ACP_TypeDef *ADC_ACP_InitStruct)
{
if(ADC_ACP_InitStruct->ACPC_OVER_TIME > ADC_ACPC_OVFL_TIME_MAX
||ADC_ACP_InitStruct->ACPC_TIMES > ADC_ACPC_TIMES_MAX
||ADC_ACP_InitStruct->ACPC_MIN_TARGET > ADC_ACP_MIN_MAX
||ADC_ACP_InitStruct->ACPC_MAX_TARGET > ADC_ACP_MAX_MAX)
{
return ERROR;
}
if(ADC_ACP_InitStruct->ACP_EN == ENABLE)
{
if(ADC->CON1.CLKS == ADC_ClkS_PCLK)
{
ADC->ACPC.CLKS = ADC_ACPC_CLKS_PCLK;
}
else
{
ADC->ACPC.CLKS = ADC_ACPC_CLKS_LRC;
}
ADC->ACPC.OVFL_TIME = ADC_ACP_InitStruct ->ACPC_OVER_TIME;
ADC->ACPC.TIMES = ADC_ACP_InitStruct->ACPC_TIMES;
ADC->IE.ACPOVIE = ENABLE;
if(ADC_ACP_InitStruct ->ACPC_MAX_TARGET ==0x0)
{
ADC->IE.ACPMAXIE = DISABLE;
}
else
{
ADC->ACPCMP.CMP_MAX =ADC_ACP_InitStruct ->ACPC_MAX_TARGET;
ADC->IE.ACPMAXIE = ENABLE;
}
if(ADC_ACP_InitStruct ->ACPC_MIN_TARGET == 0xfff)
{
ADC->IE.ACPMINIE = DISABLE;
}
else
{
ADC->ACPCMP.CMP_MIN =ADC_ACP_InitStruct ->ACPC_MIN_TARGET;
ADC->IE.ACPMINIE = ENABLE;
}
ADC->CON0.ACP_EN = ENABLE;
}
else
{
ADC->CON0.ACP_EN = DISABLE;
}
return SUCCESS;
}
ErrorStatus ADC_SoftStart(void)
{
if(ADC->CON1.SMPS == ADC_SMPS_HARD)
return ERROR;
ADC ->CON1.SMPON = SET;
return SUCCESS;
}
ErrorStatus ADC_SoftStop(void)
{
if(ADC->CON1.SMPS == ADC_SMPS_HARD)
return ERROR;
ADC->CON1.SMPON = RESET;
return SUCCESS;
}
uint16_t ADC_GetACPMeanValue(void)
{
return ((uint16_t)ADC->ACPMEAN.MEAN_DATA);
}
uint16_t ADC_GetACPMinValue(void)
{
return ((uint16_t)ADC->ACPCMP.CMP_MIN);
}
uint16_t ADC_GetACPMaxValue(void)
{
return ((uint16_t)ADC->ACPCMP.CMP_MAX);
}
FlagStatus ADC_GetFlagStatus(ADC_TYPE_IF IFName)
{
FlagStatus bitstatus = RESET;
if (((ADC->IF.Word & IFName) != (uint32_t)RESET))
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
ITStatus ADC_GetITStatus(ADC_TYPE_IE IEName)
{
ITStatus bitstatus = RESET;
if (((ADC->IE.Word & IEName) != (uint32_t)RESET))
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
ErrorStatus ADC_ClearIFStatus(ADC_TYPE_IF IFName)
{
ADC->IF.Word = (uint32_t)IFName;
return SUCCESS;
}
void ADC_Reset(void)
{
ADC->CON0.Word = 0x00000030;
ADC->CON1.Word = 0x00041000;
ADC->CHS.Word = 0x00000100;
ADC->IE.Word = 0x00000000;
ADC->IF.Word = 0x00000000;
ADC->ACPC.Word = 0x00000000;
ADC->ACPCMP.Word = 0x0FFF0000;
ADC->VREFCON.Word = 0x00000000;
}
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#include "lib_aes.h"
void AES_Init(AES_InitStruType * AES_InitStruct)
{
AES_Reset();
AES->CON.ENCRYPT = AES_InitStruct->MODE;
return;
}
void AES_WriteKey(uint32_t *AES_KEY)
{
uint32_t *address = AES_KEY;
AES->KEY3.AES_KEY3 = *address;
address ++;
AES->KEY2.AES_KEY2 = *address;
address ++;
AES->KEY1.AES_KEY1 = *address;
address ++;
AES->KEY0.AES_KEY0 = *address;
}
void AES_ReadKey(uint32_t * AES_KEY)
{
uint32_t *address = AES_KEY;
*address = AES->KEY3.AES_KEY3;
address ++;
*address = AES->KEY2.AES_KEY2;
address ++;
*address = AES->KEY1.AES_KEY1;
address ++;
*address = AES->KEY0.AES_KEY0;
return;
}
void AES_WriteData(uint32_t *AES_DATA)
{
uint32_t *address = AES_DATA;
AES->DATA3.AES_DATA3 = *address;
address ++;
AES->DATA2.AES_DATA2 = *address;
address ++;
AES->DATA1.AES_DATA1 = *address;
address ++;
AES->DATA0.AES_DATA0 = *address;
}
void AES_ReadData(uint32_t * AES_DATA)
{
uint32_t *address = AES_DATA;
*address = AES->DATA3.AES_DATA3;
address ++;
*address = AES->DATA2.AES_DATA2;
address ++;
*address = AES->DATA1.AES_DATA1;
address ++;
*address = AES->DATA0.AES_DATA0;
return;
}
void AES_ITConfig(AES_TYPE_IT AES_IE, TYPE_FUNCEN NewState)
{
uint32_t Word = AES->CON.Word&0xffffff8e;
if(AES->CON.GO_DONE == 1)
{
return;
}
if (NewState == ENABLE)
Word |= (uint32_t)AES_IE;
else
Word &= ~(uint32_t)AES_IE;
AES->CON.Word = Word;
return;
}
FlagStatus AES_GetFlagStatus(AES_TYPE_IF IFName)
{
if(AES->CON.Word & IFName) {
return SET;
}
return RESET;
}
void AES_ClearITPendingBit(AES_TYPE_IF IFName)
{
if(AES->CON.GO_DONE == SET)
{
return;
}
AES->CON.IF = SET;
return;
}
AES_TYPE_DONE AES_GetDoneStatus(void)
{
if(AES->CON.GO_DONE == 1)
{
return AES_DONE_NO;
}
return AES_DONE_YES;
}
void AES_Reset(void)
{
AES->DATA0.Word = 0x00000000;
AES->DATA1.Word = 0x00000000;
AES->DATA2.Word = 0x00000000;
AES->DATA3.Word = 0x00000000;
AES->KEY0.Word = 0x00000000;
AES->KEY1.Word = 0x00000000;
AES->KEY2.Word = 0x00000000;
AES->KEY3.Word = 0x00000000;
AES->CON.Word = 0x00000000;
}

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#include "lib_crc.h"
uint32_t CRC_getTypeValue(CRC_CONValueStruType con_value)
{
uint32_t type =0;
type = (con_value.xorout | con_value.refout | con_value.refin |\
con_value.mode|con_value.hs_type|con_value.init_data_type);
return type;
}
uint32_t CRC_EmptayCheck(void* address, uint32_t data_len)
{
CRC_EM CRC_EmptayCheck = (CRC_EM)(*(uint32_t *)CRC_EmptayCheck_addr);
uint32_t result;
__ASM("CPSID i");
result = (*CRC_EmptayCheck)(address, data_len);
__ASM("CPSIE i");
return result;
}
uint32_t CRC_FlashVerify(void* address, uint32_t data_len, uint32_t type)
{
CRC_FL CRC_FlashVerify = (CRC_FL)(*(uint32_t *)CRC_FlashVerify_addr);
uint32_t result;
__ASM("CPSID i");
result = (*CRC_FlashVerify)(address, data_len, type);
__ASM("CPSIE i");
return result;
}
uint32_t CRC_UserCal(void* address, uint32_t data_len, uint32_t type)
{
CRC_US CRC_UserCal = (CRC_US)(*(uint32_t *)CRC_UserCal_addr);
uint32_t result;
__ASM("CPSID i");
result = (*CRC_UserCal)(address, data_len, type);
__ASM("CPSIE i");
return result;
}
uint32_t CRC_CheckReset(void)
{
CRC_CH CRC_CheckReset = (CRC_CH)(*(uint32_t *)CRC_CheckReset_addr);
uint32_t result;
__ASM("CPSID i");
result = (*CRC_CheckReset)();
__ASM("CPSIE i");
return result;
}
/************************END OF FILE**************************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#include "lib_flashiap.h"
ErrorStatus FlashIap_Close_WPROT(uint8_t Page)
{
if(Page > 64)
return ERROR;
if(Page == 64)
{
IAP->WPROT2.Word = 0x00000000;
return SUCCESS;
}
if(Page < 32)
{
IAP->WPROT0.Word &=~ ((uint32_t)0x1 << Page);
}
else
{
Page -= 32;
IAP->WPROT1.Word &=~ ((uint32_t)0x1 << Page);
}
return SUCCESS;
}
ErrorStatus FlashIap_Open_WPROT(uint8_t Page)
{
if(Page > 64)
return ERROR;
if(Page == 64)
{
IAP->WPROT2.Word = 0x00000001;
return SUCCESS;
}
if(Page < 32)
{
IAP->WPROT0.Word &=~ ((uint32_t)0x1 << Page);
IAP->WPROT0.Word |= ((uint32_t)0x1 << Page);
}
else
{
Page -= 32;
IAP->WPROT1.Word &=~ ((uint32_t)0x1 << Page);
IAP->WPROT1.Word |= ((uint32_t)0x1 << Page);
}
return SUCCESS;
}
ErrorStatus FlashIap_CloseAll_WPROT(void)
{
IAP->WPROT0.Word = 0x00000000;
IAP->WPROT1.Word = 0x00000000;
IAP->WPROT2.Word = 0x00000000;
return SUCCESS;
}
ErrorStatus FlashIap_OpenAll_WPROT(void)
{
IAP->WPROT0.Word = 0xFFFFFFFF;
IAP->WPROT1.Word = 0xFFFFFFFF;
IAP->WPROT2.Word = 0xFFFFFFFF;
return SUCCESS;
}
ErrorStatus FlashIap_Unlock(void)
{
uint16_t Temp16;
FlashIAP_RegUnLock();
FlashIAP_Enable();
FlashIAP_REQ();
for(Temp16 = 0; Temp16 < 0xFFFF; Temp16++)
{
if(IAP->CON.FLASH_ACK != 0)
break;
}
if(Temp16 == 0xFFFF)
return ERROR;
else
return SUCCESS;
}
ErrorStatus FlashIap_WriteEnd(void)
{
uint32_t Temp32;
FlashIAP_RegUnLock();
IAP->CON.Word &= 0xFFFFFFEE;
for(Temp32 = 0; Temp32 < 0xFFFF; Temp32++)
{
if(IAP->CON.FLASH_ACK == 0)
break;
}
if(Temp32 == 0xFFFF)
return ERROR;
else
return SUCCESS;
}
ErrorStatus FlashIap_ErasePage(uint8_t Page_Addr)
{
uint16_t Temp16;
uint32_t temp;
temp = __get_PRIMASK();
__disable_irq();
if(FlashIap_Unlock() == ERROR)
{
__set_PRIMASK(temp);
return ERROR;
}
if(FlashIap_CloseAll_WPROT() == ERROR)
{
__set_PRIMASK(temp);
return ERROR;
}
IAP->ADDR.IAPPA = Page_Addr;
IAP->TRIG.TRIG = 0x00005EA1;
for(Temp16 = 0; Temp16 < 0xFFFF; Temp16++)
{
if((IAP->STA.Word & (uint32_t)0x01) == (uint32_t)0x00)
break;
}
if(Temp16 == 0xFFFF)
{
__set_PRIMASK(temp);
return ERROR;
}
for(Temp16 = 0; Temp16 < 0xFFFF; Temp16++)
{
if((IAP->STA.Word & (uint32_t)0x02) == (uint32_t)0x02)
break;
}
if(Temp16 == 0xFFFF)
{
__set_PRIMASK(temp);
return ERROR;
}
if(FlashIap_WriteEnd() == ERROR)
{
__set_PRIMASK(temp);
return ERROR;
}
if(FlashIap_OpenAll_WPROT() == ERROR)
{
__set_PRIMASK(temp);
return ERROR;
}
__set_PRIMASK(temp);
return SUCCESS;
}
ErrorStatus FlashIap_WriteCont(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32)
{
uint16_t temp16;
IAP->ADDR.IAPPA = Page_addr;
IAP->ADDR.IAPCA = Unit_addr;
IAP->DATA.DATA = Data32;
IAP->TRIG.TRIG = 0x00005DA2;
for(temp16 = 0; temp16 < 0xFFFF; temp16++)
{
if((IAP->STA.Word & (uint32_t)0x01) == (uint32_t)0x00)
break;
}
if(temp16 == 0xFFFF)
return ERROR;
for(temp16 = 0; temp16 < 0xFFFF; temp16++)
{
if((IAP->STA.Word & 0x04)==0x04)
break;
}
if(temp16 == 0xFFFF)
return ERROR;
return SUCCESS;
}
ErrorStatus FlashIap_WriteWord(uint8_t Unit_addr, uint8_t Page_addr, uint32_t Data32)
{
uint32_t temp;
temp = __get_PRIMASK();
__disable_irq();
if(FlashIap_Unlock() == ERROR)
{
__set_PRIMASK(temp);
return ERROR;
}
if(FlashIap_CloseAll_WPROT() == ERROR)
{
__set_PRIMASK(temp);
return ERROR;
}
if(FlashIap_WriteCont(Unit_addr, Page_addr, Data32) == ERROR)
{
__set_PRIMASK(temp);
return ERROR;
}
if(FlashIap_WriteEnd() == ERROR)
{
__set_PRIMASK(temp);
return ERROR;
}
if(FlashIap_OpenAll_WPROT() == ERROR)
{
__set_PRIMASK(temp);
return ERROR;
}
__set_PRIMASK(temp);
return SUCCESS;
}
ErrorStatus Flash_Read(uint32_t * Ram_Addr, uint32_t Flash_Addr, uint8_t Len)
{
uint8_t i;
uint32_t *ram_addr32;
const uint32_t *flash_addr32;
ram_addr32 = (uint32_t *)Ram_Addr;
flash_addr32 = (const uint32_t *)Flash_Addr;
if((Len == 0) & (Len>(0x20000 - Flash_Addr) / 4))
{
return ERROR;
}
for(i=0; i<Len; i++)
{
*ram_addr32 = *flash_addr32;
ram_addr32++;
flash_addr32++;
}
return SUCCESS;
}
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#include "lib_gpio.h"
void GPIO_Init(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_InitStruType* GPIO_InitStruct)
{
if (GPIO_InitStruct->GPIO_Signal == GPIO_Pin_Signal_Analog) {
GPIO_SetSingalTypeFromPin(GPIOx, PINx, GPIO_Pin_Signal_Analog);
GPIO_SetDirRegFromPin(GPIOx, PINx, GPIO_Dir_In);
GPIO_SetFuncxRegFromPin(GPIOx, PINx, GPIO_Func_0);
}
else {
GPIO_SetSingalTypeFromPin(GPIOx, PINx, GPIO_Pin_Signal_Digital);
GPIO_SetDirRegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_Direction);
GPIO_SetFuncxRegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_Func);
if (GPIO_InitStruct->GPIO_Direction == GPIO_Dir_Out) {
GPIO_SetODERegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_OD);
GPIO_SetDSRegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_DS);
}
GPIO_SetPUERegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_PUEN);
GPIO_SetPDERegFromPin(GPIOx, PINx, GPIO_InitStruct->GPIO_PDEN);
}
}
void GPIO_SetFuncxRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_FUNC Func)
{
uint32_t value;
switch (Func) {
case GPIO_Func_0:
value = 0;
break;
case GPIO_Func_1:
value = 1;
break;
case GPIO_Func_2:
value = 2;
break;
case GPIO_Func_3:
value = 3;
break;
default:
value = 0;
break;
}
if(GPIOx == GPIOB){
switch (PINx) {
case GPIO_Pin_0:
GPIO->PBFUNC0.PB0 = value;
break;
case GPIO_Pin_1:
GPIO->PBFUNC0.PB1 = value;
break;
case GPIO_Pin_2:
GPIO->PBFUNC0.PB2 = value;
break;
case GPIO_Pin_3:
GPIO->PBFUNC0.PB3 = value;
break;
case GPIO_Pin_4:
GPIO->PBFUNC0.PB4 = value;
break;
case GPIO_Pin_5:
GPIO->PBFUNC0.PB5 = value;
break;
case GPIO_Pin_6:
GPIO->PBFUNC0.PB6 = value;
break;
case GPIO_Pin_7:
GPIO->PBFUNC0.PB7 = value;
break;
case GPIO_Pin_8:
GPIO->PBFUNC1.PB8 = value;
break;
case GPIO_Pin_9:
GPIO->PBFUNC1.PB9 = value;
break;
case GPIO_Pin_10:
GPIO->PBFUNC1.PB10 = value;
break;
case GPIO_Pin_11:
GPIO->PBFUNC1.PB11 = value;
break;
case GPIO_Pin_12:
GPIO->PBFUNC1.PB12 = value;
break;
case GPIO_Pin_13:
GPIO->PBFUNC1.PB13 = value;
break;
default:
break;
}
}
else{
switch (PINx) {
case GPIO_Pin_0:
GPIO->PAFUNC0.PA0 = value;
break;
case GPIO_Pin_1:
GPIO->PAFUNC0.PA1 = value;
break;
case GPIO_Pin_2:
GPIO->PAFUNC0.PA2 = value;
break;
case GPIO_Pin_3:
GPIO->PAFUNC0.PA3 = value;
break;
case GPIO_Pin_4:
GPIO->PAFUNC0.PA4 = value;
break;
case GPIO_Pin_5:
GPIO->PAFUNC0.PA5 = value;
break;
case GPIO_Pin_6:
GPIO->PAFUNC0.PA6 = value;
break;
case GPIO_Pin_7:
GPIO->PAFUNC0.PA7 = value;
break;
case GPIO_Pin_8:
GPIO->PAFUNC1.PA8 = value;
break;
case GPIO_Pin_9:
GPIO->PAFUNC1.PA9 = value;
break;
case GPIO_Pin_10:
GPIO->PAFUNC1.PA10 = value;
break;
case GPIO_Pin_11:
GPIO->PAFUNC1.PA11 = value;
break;
case GPIO_Pin_12:
GPIO->PAFUNC1.PA12 = value;
break;
case GPIO_Pin_13:
GPIO->PAFUNC1.PA13 = value;
break;
case GPIO_Pin_14:
GPIO->PAFUNC1.PA14 = value;
break;
case GPIO_Pin_15:
GPIO->PAFUNC1.PA15 = value;
break;
case GPIO_Pin_16:
GPIO->PAFUNC2.PA16 = value;
break;
case GPIO_Pin_17:
GPIO->PAFUNC2.PA17 = value;
break;
case GPIO_Pin_18:
GPIO->PAFUNC2.PA18 = value;
break;
case GPIO_Pin_19:
GPIO->PAFUNC2.PA19 = value;
break;
case GPIO_Pin_20:
GPIO->PAFUNC2.PA20 = value;
break;
case GPIO_Pin_21:
GPIO->PAFUNC2.PA21 = value;
break;
case GPIO_Pin_22:
GPIO->PAFUNC2.PA22 = value;
break;
case GPIO_Pin_23:
GPIO->PAFUNC2.PA23 = value;
break;
case GPIO_Pin_24:
GPIO->PAFUNC3.PA24 = value;
break;
case GPIO_Pin_25:
GPIO->PAFUNC3.PA25 = value;
break;
case GPIO_Pin_26:
GPIO->PAFUNC3.PA26 = value;
break;
case GPIO_Pin_27:
GPIO->PAFUNC3.PA27 = value;
break;
case GPIO_Pin_28:
GPIO->PAFUNC3.PA28 = value;
break;
case GPIO_Pin_29:
GPIO->PAFUNC3.PA29 = value;
break;
case GPIO_Pin_30:
GPIO->PAFUNC3.PA30 = value;
break;
case GPIO_Pin_31:
GPIO->PAFUNC3.PA31 = value;
break;
default:
break;
}
}
return;
}
void GPIO_SetSingalTypeFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_Pin_Signal GPIO_Signal)
{
if(GPIOx == GPIOB) {
if (GPIO_Signal == GPIO_Pin_Signal_Digital)
GPIO->PBINEB.Word &= (~(1 << PINx));
else
GPIO->PBINEB.Word |= (1 << PINx);
}
else{
if (GPIO_Signal == GPIO_Pin_Signal_Digital)
GPIO->PAINEB.Word &= (~(1 << PINx));
else
GPIO->PAINEB.Word |= (1 << PINx);
}
return;
}
void GPIO_SetDirRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir)
{
if (GPIOx == GPIOB) {
if (Dir == GPIO_Dir_In)
GPIO->PBDIRBSR.Word = (1 << PINx);
else
GPIO->PBDIRBCR.Word = (1 << PINx);
}
else {
if (Dir == GPIO_Dir_In)
GPIO->PADIRBSR.Word = (1 << PINx);
else
GPIO->PADIRBCR.Word = (1 << PINx);
}
return;
}
void GPIO_SetODERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_ODE_Output ODE)
{
if (GPIOx == GPIOB) {
if (ODE == GPIO_ODE_Output_Disable)
GPIO->PBODE.Word &= (~(1 << PINx));
else
GPIO->PBODE.Word |= (1 << PINx);
}
else {
if (ODE == GPIO_ODE_Output_Disable)
GPIO->PAODE.Word &= (~(1 << PINx));
else
GPIO->PAODE.Word |= (1 << PINx);
}
return;
}
void GPIO_SetDSRegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_TYPE_DS DS)
{
if (GPIOx == GPIOB) {
if (DS == GPIO_DS_Output_Normal)
GPIO->PBDS.Word &= (~(1 << PINx));
else
GPIO->PBDS.Word |= (1 << PINx);
}
else {
if (DS == GPIO_DS_Output_Normal)
GPIO->PADS.Word &= (~(1 << PINx));
else
GPIO->PADS.Word |= (1 << PINx);
}
return;
}
void GPIO_SetPUERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PUE_Input PUE)
{
if (GPIOx == GPIOB) {
if (PUE == GPIO_PUE_Input_Disable)
GPIO->PBPUE.Word &= (~(1 << PINx));
else
GPIO->PBPUE.Word |= (1 << PINx);
}
else {
if (PUE == GPIO_PUE_Input_Disable)
GPIO->PAPUE.Word &= (~(1 << PINx));
else
GPIO->PAPUE.Word |= (1 << PINx);
}
}
void GPIO_SetPDERegFromPin(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx, GPIO_PDE_Input PDE)
{
if (GPIOx == GPIOB) {
if (PDE == GPIO_PDE_Input_Disable)
GPIO->PBPDE.Word &= (~(1 << PINx));
else
GPIO->PBPDE.Word |= (1 << PINx);
}
else {
if (PDE == GPIO_PDE_Input_Disable)
GPIO->PAPDE.Word &= (~(1 << PINx));
else
GPIO->PAPDE.Word |= (1 << PINx);
}
return;
}
void GPIO_Write(GPIO_TYPE GPIOx, uint32_t Value)
{
if(GPIOx == GPIOA)
GPIO->PADATA.Word = Value;
else if(GPIOx == GPIOB)
GPIO->PBDATA.Word = Value;
}
uint32_t GPIO_Read(GPIO_TYPE GPIOx)
{
if(GPIOx == GPIOA)
return GPIO->PAPORT.Word;
else if(GPIOx == GPIOB)
return GPIO->PBPORT.Word;
return 0;
}
PinStatus GPIO_ReadBit(GPIO_TYPE GPIOx,GPIO_TYPE_PIN PINx)
{
PinStatus bitstatus = RESET;
if(GPIOx == GPIOA)
{
if((GPIO->PAPORT.Word&((uint32_t)0x1<<PINx)) != RESET)
bitstatus = SET;
else
bitstatus = RESET;
}
else if(GPIOx == GPIOB)
{
if((GPIO->PBPORT.Word&((uint32_t)0x1<<PINx)) != RESET)
bitstatus = SET;
else
bitstatus = RESET;
}
return bitstatus;
}
void GPIOA_SetBit(GPIO_TYPE_PIN PINx)
{
GPIO->PADATABSR.Word = (uint32_t)0x1<<PINx;
}
void GPIOA_ResetBit(GPIO_TYPE_PIN PINx)
{
GPIO->PADATABCR.Word = (uint32_t)0x1<<PINx;
}
void GPIOA_ToggleBit(GPIO_TYPE_PIN PINx)
{
GPIO->PADATABRR.Word = (uint32_t)0x1<<PINx;
}
void GPIOB_SetBit(GPIO_TYPE_PIN PINx)
{
GPIO->PBDATABSR.Word = (uint32_t)0x1<<PINx;
}
void GPIOB_ResetBit(GPIO_TYPE_PIN PINx)
{
GPIO->PBDATABCR.Word = (uint32_t)0x1<<PINx;
}
void GPIOB_ToggleBit(GPIO_TYPE_PIN PINx)
{
GPIO->PBDATABRR.Word = (uint32_t)0x1<<PINx;
}
void GPIOA_SetDirection(GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir_Type)
{
GPIO->PADIR.Word &=~((uint32_t)0x1 << PINx);
GPIO->PADIR.Word |= ((uint32_t)Dir_Type <<PINx);
}
void GPIOB_SetDirection(GPIO_TYPE_PIN PINx, GPIO_TYPE_DIR Dir_Type)
{
GPIO->PBDIR.Word &=~((uint32_t)0x1 << PINx);
GPIO->PBDIR.Word |= ((uint32_t)Dir_Type <<PINx);
}
void PINT_Config(PINT_TYPE PINTx, PINT_TYPE_SEL SELx, PINT_TYPE_TRIG TRIGx)
{
GPIO->PINTSEL.Word &= ~((uint32_t)0x07<<(PINTx*4));
GPIO->PINTSEL.Word |=((uint32_t)SELx << (PINTx*4));
GPIO->PINTCFG.Word &= ~((uint32_t)0x07<<(PINTx*4));
GPIO->PINTCFG.Word |=((uint32_t)TRIGx << (PINTx*4));
}
FlagStatus PINT_GetIFStatus(PINT_TYPE_IT PINT_Flag)
{
FlagStatus bitstatus = RESET;
if((GPIO->PINTIF.Word & (uint32_t)PINT_Flag) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
FlagStatus PINT_GetITStatus(PINT_TYPE_IT PINT_Flag)
{
FlagStatus bitstatus = RESET;
if((GPIO->PINTIF.Word & (uint32_t)PINT_Flag) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
void PINT_ClearITPendingBit(PINT_TYPE_IT PINT_Flag)
{
GPIO->PINTIF.Word = (uint32_t)PINT_Flag;
}
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd.
***************************************************************/
#include "lib_iap.h"
ErrorStatus IAP_PageErase(uint32_t address)
{
IAP_PE IAPPageErase = (IAP_PE)(*(uint32_t *)IAP_PageErase_addr);
ErrorStatus result;
__ASM("CPSID i");
result = (*IAPPageErase)(address);
__ASM("CPSIE i");
return result;
}
ErrorStatus IAP_WordProgram(uint32_t address, uint32_t data)
{
IAP_WP IAPWordProgram = (IAP_WP)(*(uint32_t *)IAP_WordProgram_addr);
ErrorStatus result;
__ASM("CPSID i");
result = (*IAPWordProgram)( address, data);
__ASM("CPSIE i");
return result;
}
ErrorStatus IAP_PageProgram(uint32_t address, uint32_t data[], uint32_t length, uint32_t erase) //@0x100001c5
{
IAP_PP IAPPageProgram = (IAP_PP)(*(uint32_t *)IAP_PageProgram_addr);
ErrorStatus result;
__ASM("CPSID i");
result = (*IAPPageProgram)(address,data,length,erase);
__ASM("CPSIE i");
return result;
}
ErrorStatus IAPRead(uint32_t *Ram_Addr, uint32_t Flash_Addr, uint8_t Len)
{
uint8_t i;
uint32_t *ram_addr;
const uint32_t *flash_addr;
ram_addr = Ram_Addr;
flash_addr = (const uint32_t *)Flash_Addr;
if (Len == 0)
return ERROR;
for (i = 0; i < Len; ++i)
{
*ram_addr = *flash_addr;
++ram_addr;
++flash_addr;
}
return SUCCESS;
}
/************************END OF FILE**************************/

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Living_SDK/platform/mcu/es8p508x/library/Source/lib_iic.c Normal file
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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#include "lib_iic.h"
void I2C_Init(I2C_InitStruType* I2C_InitStruct)
{
uint32_t temp;
if(I2C_InitStruct->I2C_Mode == I2C_Mode_Master)
{
if(I2C_InitStruct->I2C_16XSamp != DISABLE)
temp = SystemCoreClock/24/I2C_InitStruct->I2C_Clk - 1;
else
temp = SystemCoreClock/16/I2C_InitStruct->I2C_Clk - 1;
if(temp > 254)
temp = 255;
I2C0->CON.TJP = temp;
I2C0->CON.TJE = 0x1;
}
I2C0->CON.SDASE = I2C_InitStruct->I2C_16XSamp;
I2C0->CON.SCKSE = I2C_InitStruct->I2C_16XSamp;
I2C0->CON.SCKOD = I2C_InitStruct->I2C_SclOd;
I2C0->CON.SDAOD = I2C_InitStruct->I2C_SdaOd;
I2C0->MOD.MS = I2C_InitStruct->I2C_Mode;
I2C0->MOD.SPAE = I2C_InitStruct->I2C_AutoStop;
I2C0->MOD.SRAE = I2C_InitStruct->I2C_AutoCall;
}
void I2C_ITConfig(I2C_TYPE_IT I2C_IT,TYPE_FUNCEN NewState)
{
if (NewState != DISABLE)
I2C0->IE.Word |= (uint32_t)I2C_IT;
else
I2C0->IE.Word &= ~((uint32_t)I2C_IT);
}
void I2C_SendAddress(uint8_t I2C_Address,I2C_TYPE_RWMODE Mode)
{
I2C0->CON.SA = I2C_Address>>1;
I2C0->CON.RW = Mode;
}
void I2C_SetAddress(uint8_t I2C_Address)
{
I2C0->CON.SA = I2C_Address>>1;
}
void I2C_RecModeConfig(I2C_TYPE_RECMODE RecType)
{
I2C0->MOD.RDM = RecType;
}
void I2C_TBIMConfig(I2C_TYPE_TRBIM Type)
{
I2C0->IE.TBIM = Type;
}
void I2C_RBIMConfig(I2C_TYPE_TRBIM Type)
{
I2C0->IE.RBIM = Type;
}
void I2C_AckDelay(I2C_TYPE_ADLY Type,TYPE_FUNCEN NewStatus)
{
I2C0->MOD.ADLY = Type;
I2C0->MOD.ADE = NewStatus;
}
void I2C_TISConfig(I2C_TYPE_TIS Time)
{
I2C0->MOD.TIS = Time;
}
void I2C_SendByte(uint8_t Byte)
{
I2C0->TBW.Byte[0] = Byte;
}
void I2C_SendHalfWord(uint16_t HalfWord)
{
I2C0->TBW.HalfWord[0] = HalfWord;
}
void I2C_SendWord(uint32_t Word)
{
I2C0->TBW.Word = Word;
}
uint8_t I2C_RecByte(void)
{
return I2C0->RBR.Byte[0] ;
}
uint16_t I2C_RecHalfWord(void)
{
return I2C0->RBR.HalfWord[0];
}
uint32_t I2C_RecWord(void)
{
return I2C0->RBR.Word ;
}
I2C_TYPE_RWMODE I2C_GetRWMode(void)
{
I2C_TYPE_RWMODE Status = I2C_Mode_Write;
if(I2C0->CON.RW != 0)
Status = I2C_Mode_Read;
else
Status = I2C_Mode_Write;
return Status;
}
FlagStatus I2C_GetTBStatus(void)
{
FlagStatus bitstatus = RESET;
if((I2C0->STA.Word&(uint32_t)0x0f00) != (uint32_t)0x0f00)
bitstatus = RESET;
else
bitstatus = SET;
return bitstatus;
}
FlagStatus I2C_GetFlagStatus(I2C_TYPE_FLAG I2C_Flag)
{
FlagStatus bitstatus = RESET;
if ((I2C0->IF.Word & (uint32_t)I2C_Flag) != RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
FlagStatus I2C_GetITStatus( I2C_TYPE_IT I2C_Flag)
{
FlagStatus status = RESET;
if ((I2C0->IE.Word & (uint32_t)I2C_Flag) == RESET)
return status;
if ((I2C0->IF.Word & (uint32_t)I2C_Flag) != RESET)
status = SET;
return status;
}
void I2C_ClearITPendingBit(I2C_CLR_IF I2C_IT)
{
I2C0->IF.Word = (uint32_t)I2C_IT;
}
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#include "lib_printf.h"
#include <stdarg.h>
int fputc(int ch, FILE *f)
{
FlagStatus Status = RESET;
uint32_t Count=0;
#if defined __PRINTF_USE_UART3__
UART_SendByte(UART3, (unsigned char) ch);
do
{
Status = UART_GetFlagStatus(UART3,UART_FLAG_TXIDLE);
Count++;
}while((Status == RESET)&&(Count != 0x1CE2));
if(Count == 0x1CE2)
return (EOF);
#elif defined __PRINTF_USE_UART2__
UART_SendByte(UART2, (unsigned char) ch);
do
{
Status = UART_GetFlagStatus(UART2,UART_FLAG_TXIDLE);
Count++;
}while((Status == RESET)&&(Count != 0x1CE2));
if(Count == 0x1CE2)
return (EOF);
#elif defined __PRINTF_USE_UART1__
UART_SendByte(UART1, (unsigned char) ch);
do
{
Status = UART_GetFlagStatus(UART1,UART_FLAG_TXIDLE);
Count++;
}while((Status == RESET)&&(Count != 0x1CE2));
if(Count == 0x1CE2)
return (EOF);
#else
UART_SendByte(UART0, (unsigned char) ch);
do
{
Status = UART_GetFlagStatus(UART0,UART_FLAG_TXIDLE);
Count++;
}while((Status == RESET)&&(Count != 0x1CE2));
if(Count == 0x1CE2)
return (EOF);
#endif
return (ch);
}
static char *itoa(int value, char *string, int radix)
{
int i, d;
int flag = 0;
char *ptr = string;
/* This implementation only works for decimal numbers. */
if (radix != 10)
{
*ptr = 0;
return string;
}
if (!value)
{
*ptr++ = 0x30;
*ptr = 0;
return string;
}
/* if this is a negative value insert the minus sign. */
if (value < 0)
{
*ptr++ = '-';
/* Make the value positive. */
value *= -1;
}
for (i = 10000; i > 0; i /= 10)
{
d = value / i;
if (d || flag)
{
*ptr++ = (char)(d + 0x30);
value -= (d * i);
flag = 1;
}
}
/* Null terminate the string. */
*ptr = 0;
return string;
}
ErrorStatus UART_printf(UART_TypeDef* UARTx, uint8_t *Data,...)
{
const char *s;
int d;
char buf[16];
ErrorStatus RET = SUCCESS;
FlagStatus Status = RESET;
uint32_t Count=0;
va_list ap;
va_start(ap, Data);
while ( *Data != 0)
{
if ( *Data == 0x5c )
{
switch ( *++Data )
{
case 'r':
Count=0;
UART_SendByte(UARTx, 0x0d);
do
{
Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE);
Count++;
}while((Status == RESET)&&(Count != 0x1CE2));
if(Count == 0x1CE2)
RET = ERROR;
Data ++;
break;
case 'n':
Count=0;
UART_SendByte(UARTx, 0x0a);
do
{
Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE);
Count++;
}while((Status == RESET)&&(Count != 0x1CE2));
if(Count == 0x1CE2)
RET = ERROR;
Data ++;
break;
default:
Data ++;
break;
}
}
else if ( *Data == '%')
{
switch ( *++Data )
{
case 's':
s = va_arg(ap, const char *);
for ( ; *s; s++)
{
Count=0;
UART_SendByte(UARTx,*s);
do
{
Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE);
Count++;
}while((Status == RESET)&&(Count != 0x1CE2));
if(Count == 0x1CE2)
RET = ERROR;
}
Data++;
break;
case 'd':
d = va_arg(ap, int);
itoa(d, buf, 10);
for (s = buf; *s; s++)
{
Count=0;
UART_SendByte(UARTx,*s);
do
{
Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE);
Count++;
}while((Status == RESET)&&(Count != 0x1CE2));
if(Count == 0x1CE2)
RET = ERROR;
}
Data++;
break;
default:
Data++;
break;
}
} /* end of else if */
else
{
Count=0;
UART_SendByte(UARTx, *Data++);
do
{
Status = UART_GetFlagStatus(UARTx,UART_FLAG_TXIDLE);
Count++;
}while((Status == RESET)&&(Count != 0x1CE2));
if(Count == 0x1CE2)
RET = ERROR;
}
}
return RET;
}
/*************************END OF FILE**********************/

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Living_SDK/platform/mcu/es8p508x/library/Source/lib_rtc.c Normal file
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62
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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#include "lib_scs.h"
void NVIC_Init(NVIC_IRQChannel Channel,NVIC_IRQPriority Priority,TYPE_FUNCEN Cmd)
{
uint32_t tmppriority = 0x00;
if (Cmd != DISABLE)
{
/* Compute the Corresponding IRQ Priority */
tmppriority = NVIC->IP[Channel >> 0x02];
tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((Channel & 0x03) * 8)));
tmppriority |= (uint32_t)((((uint32_t)Priority << 6) & 0xFF) << ((Channel & 0x03) * 8));
NVIC->IP[Channel >> 0x02] = tmppriority;
/* Enable the Selected IRQ Channels */
NVIC->ISER[0] = (uint32_t)0x01 << (Channel & (uint8_t)0x1F);
}
else
{
/* Disable the Selected IRQ Channels */
NVIC->ICER[0] = (uint32_t)0x01 << (Channel & (uint8_t)0x1F);
}
}
void SCB_SystemLPConfig(SCB_TYPE_SCR LowPowerMode, TYPE_FUNCEN NewState)
{
if (NewState != DISABLE)
SCB->SCR |= LowPowerMode;
else
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
}
uint32_t SCB_GetCpuID(void)
{
return (SCB->CPUID);
}
void SysTick_Init(SYSTICK_InitStruType* SysT_InitStruct)
{
uint32_t temp32 = 0;
SysTick->LOAD = SysT_InitStruct->SysTick_Value;
SysTick->VAL = (uint32_t)0;
if(SysT_InitStruct->SysTick_ClkSource != SysTick_ClkS_Base)
temp32 |= 0x00000004;
else
temp32 &= 0xFFFFFFFB;
if(SysT_InitStruct->SysTick_ITEnable != DISABLE)
temp32 |= 0x00000002;
else
temp32 &= 0xFFFFFFFD;
SysTick->CTRL = temp32;
}
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#include "lib_scu.h"
void SCU_NMISelect(SCU_TYPE_NMICS NMI_Type)
{
SCU->NMICON.NMICS = NMI_Type;
}
FlagStatus SCU_GetPWRCFlagStatus(SCU_TYPE_PWRC PWRC_Flag)
{
FlagStatus bitstatus = RESET;
if((SCU->PWRC.Word & (uint32_t)PWRC_Flag) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
void SCU_ClearPWRCFlagBit(SCU_TYPE_PWRC PWRC_Flag)
{
SCU->PWRC.Word &= ~((uint32_t)PWRC_Flag);
}
FlagStatus SCU_GetLVDFlagStatus(SCU_TYPE_LVD0CON LVD_Flag)
{
FlagStatus bitstatus = RESET;
if((SCU->LVDCON.Word & (uint32_t)LVD_Flag) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
void SCU_SysClkSelect(SCU_TYPE_SYSCLK Sysclk)
{
SCU->SCLKEN0.CLK_SEL = Sysclk;
}
SCU_TYPE_SYSCLK SCU_GetSysClk(void)
{
return (SCU_TYPE_SYSCLK)(SCU->SCLKEN0.CLK_SEL);
}
FlagStatus SCU_HRCReadyFlag(void)
{
FlagStatus bitstatus = RESET;
if((SCU->SCLKEN1.HRC_RDY) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
FlagStatus SCU_XTALReadyFlag(void)
{
FlagStatus bitstatus = RESET;
if((SCU->SCLKEN1.XTAL_RDY) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
FlagStatus SCU_PLLReadyFlag(void)
{
FlagStatus bitstatus = RESET;
if((SCU->SCLKEN1.PLL_RDY) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
void SystemClockConfig(void)
{
uint32_t Prot_Temp;
Prot_Temp = SCU->PROT.PROT;
if(Prot_Temp != 0)
SCU_RegUnLock();
SCU_HRC_Enable();
while(SCU_HRCReadyFlag() != SET);
SCU_SysClkSelect(SCU_SysClk_HRC);
SCU_SysClk_Div1();
SystemCoreClock = 20000000;
if(Prot_Temp != 0)
SCU_RegLock();
}
void DeviceClockAllEnable(void)
{
uint32_t Prot_Temp;
Prot_Temp = SCU->PROT.PROT;
if(Prot_Temp != 0)
SCU_RegUnLock();
SCU->PCLKEN0.Word = 0xFFFFFFFF;
SCU->PCLKEN1.Word = 0xFFFFFFFF;
if(Prot_Temp != 0)
SCU_RegLock();
}
void DeviceClockAllDisable(void)
{
uint32_t Prot_Temp;
Prot_Temp = SCU->PROT.PROT;
if(Prot_Temp != 0)
SCU_RegUnLock();
SCU->PCLKEN0.Word = 0x00000000;
SCU->PCLKEN1.Word = 0x00000000;
if(Prot_Temp != 0)
SCU_RegLock();
}
void SystemClockSelect(SCU_TYPE_SYSCLK SYSCLKx , SCU_TYPE_CLK_SEL CLK_SEL)
{
SCU_RegUnLock();
switch(SYSCLKx)
{
case 0:
SCU_HRC_Enable();
while(SCU_HRCReadyFlag() != SET);
break;
case 1:
SCU_XTAL_Enable();
while(SCU_XTALReadyFlag() != SET);
break;
case 2:
SCU_PLL_Enable();
while(SCU_PLLReadyFlag() != SET);
break;
default:break;
}
SCU->SCLKEN0.SYSCLK_DIV = 0;
SCU->SCLKEN0.CLK_SEL = 2;
SCU_RegLock();
}
void SysclkPLL(PLL_TYPE_CLK CLKx)
{
SCU_RegUnLock();
SCU->SCLKEN0.CLK_SEL = CLKx;
SCU_PLL_Enable();
while(SCU_PLLReadyFlag() != SET);
SCU_SysClkSelect(SCU_SysClk_PLL);
SCU_RegLock();
}
void PLLClock_Config(TYPE_FUNCEN pll_en , SCU_PLL_Origin pll_origin ,SCU_PLL_Out pll_out,TYPE_FUNCEN sys_pll)
{
SCU_RegUnLock();
if(pll_en == DISABLE)
{
SCU->SCLKEN1.PLL_EN = 0;
return;
}
if((pll_origin == SCU_PLL_HRC))
{
if(SCU->SCLKEN1.HRC_RDY == 0)
{
SCU->SCLKEN1.HRC_EN = 1;
while(SCU->SCLKEN1.HRC_RDY == 0);
}
}
if((pll_origin == SCU_PLL_XTAL_32K)
|| (pll_origin == SCU_PLL_XTAL_4M)
||(pll_origin == SCU_PLL_XTAL_8M)
|| (pll_origin == SCU_PLL_XTAL_16M)
|| (pll_origin == SCU_PLL_XTAL_20M))
{
if(SCU->SCLKEN1.XTAL_RDY == 0)
{
SCU->SCLKEN1.XTAL_EN = 1;
SCU->SCLKEN0.XTAL_LP = 0;
while(SCU->SCLKEN1.XTAL_RDY == 0);
}
}
switch(pll_origin)
{
case SCU_PLL_HRC:
SCU->SCLKEN1.PLL_REF_SEL = 0x00;
break;
case SCU_PLL_LRC:
SCU->SCLKEN1.PLL_REF_SEL = 0x02;
break;
case SCU_PLL_XTAL_32K:
SCU->SCLKEN1.PLL_REF_SEL = 0x03;
break;
case SCU_PLL_XTAL_4M:
SCU->SCLKEN1.PLL_REF_SEL = 0x04;
break;
case SCU_PLL_XTAL_8M:
SCU->SCLKEN1.PLL_REF_SEL = 0x05;
break;
case SCU_PLL_XTAL_16M:
SCU->SCLKEN1.PLL_REF_SEL = 0x06;
break;
case SCU_PLL_XTAL_20M:
SCU->SCLKEN1.PLL_REF_SEL = 0x07;
break;
default:
break;
}
SCU->SCLKEN1.PLL_48M_SEL = pll_out;
SCU->SCLKEN1.PLL_EN = 1;
while(SCU->SCLKEN1.PLL_RDY == 0);
if(sys_pll == ENABLE){
SCU->SCLKEN0.PLL_MUX = 1;
SCU->SCLKEN1.PLL_BYLOCK = 1;
SCU->SCLKEN0.CLKFLT_BY = 0x55;
}
else{
SCU->SCLKEN0.PLL_MUX = 0;
SCU->SCLKEN1.PLL_BYLOCK = 0;
SCU->SCLKEN0.CLKFLT_BY = 0x00;
}
SCU_RegLock();
}
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#include "lib_spi.h"
void SPI_Init(SPI_InitStruType* SPI_InitStruct)
{
uint32_t Temp = 0;
Temp = SystemCoreClock / (SPI_InitStruct->SPI_Freq * 2);
if(Temp > 254)
Temp = 255;
SPI0->CKS.CKS = Temp;
SPI0->CON.DFS = SPI_InitStruct->SPI_Df;
SPI0->CON.MS = SPI_InitStruct->SPI_Mode;
SPI0->CON.DW = SPI_InitStruct->SPI_DW;
SPI0->CON.DRE = SPI_InitStruct->SPI_DelayRec;
SPI0->CON.TME = SPI_InitStruct->SPI_DelaySend;
Temp = (uint32_t)SPI_InitStruct->SPI_SendDelayPeroid - 1;
if(Temp > 62)
Temp = 63;
SPI0->CON.TMP = Temp;
}
void SPI_ITConfig(SPI_TYPE_IT SPI_IE,TYPE_FUNCEN NewState)
{
if(NewState != DISABLE)
SPI0->IE.Word |= (uint32_t)SPI_IE;
else
SPI0->IE.Word &= ~((uint32_t)SPI_IE);
}
void SPI_DataFormatConfig(SPI_TYPE_DFS Type)
{
SPI0->CON.DFS = Type;
}
void SPI_SendByte(uint8_t Temp)
{
SPI0->TBW.Byte[0] = Temp;
}
void SPI_SendHalfWord(uint16_t Temp)
{
SPI0->TBW.HalfWord[0] = Temp;
}
void SPI_SendWord(uint32_t Temp)
{
SPI0->TBW.Word = Temp;
}
uint8_t SPI_RecByte(void)
{
return SPI0->RBR.Byte[0];
}
uint16_t SPI_RecHalfWord(void)
{
return SPI0->RBR.HalfWord[0];
}
uint32_t SPI_RecWord(void)
{
return SPI0->RBR.Word;
}
void SPI_TBIMConfig(SPI_TYPE_TRBIM Type)
{
SPI0->IE.TBIM = Type;
}
void SPI_RBIMConfig(SPI_TYPE_TRBIM Type)
{
SPI0->IE.RBIM = Type;
}
FlagStatus SPI_GetFlagStatus(SPI_TYPE_FLAG Flag)
{
FlagStatus bitstatus = RESET;
if((uint32_t)Flag <= 0x00000040)
{
if ((SPI0->IF.Word & Flag) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
}
else
{
if ((SPI0->STA.Word & Flag) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
}
return bitstatus;
}
ITStatus SPI_GetITStatus(SPI_TYPE_IT Flag)
{
FlagStatus bitstatus = RESET;
uint32_t itstatus = 0x0, itenable = 0x0;
itstatus = SPI0->IF.Word & (uint32_t)Flag;
itenable = SPI0->IE.Word & (uint32_t)Flag;
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
void SPI_ClearITPendingBit(SPI_CLR_IF Flag)
{
SPI0->IF.Word = (uint32_t)Flag;
}
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#include "lib_timer.h"
void T16Nx_BaseInit(T16N_TypeDef* T16Nx,TIM_BaseInitStruType* TIM_BaseInitStruct)
{
T16Nx->CON0.CS = TIM_BaseInitStruct->TIM_ClkS;
T16Nx->CON0.SYNC = TIM_BaseInitStruct->TIM_SYNC;
T16Nx->CON0.EDGE = TIM_BaseInitStruct->TIM_EDGE;
T16Nx->CON0.MOD = TIM_BaseInitStruct->TIM_Mode;
}
void T32Nx_BaseInit(T32N_TypeDef* T32Nx,TIM_BaseInitStruType* TIM_BaseInitStruct)
{
T32Nx->CON0.CS = TIM_BaseInitStruct->TIM_ClkS;
T32Nx->CON0.SYNC = TIM_BaseInitStruct->TIM_SYNC;
T32Nx->CON0.EDGE = TIM_BaseInitStruct->TIM_EDGE;
T32Nx->CON0.MOD = TIM_BaseInitStruct->TIM_Mode;
}
void T16Nx_CapInit(T16N_TypeDef* T16Nx,TIM_CapInitStruType* TIM_CapInitStruct)
{
T16Nx->CON1.CAPPE = TIM_CapInitStruct->TIM_CapRise;
T16Nx->CON1.CAPNE = TIM_CapInitStruct->TIM_CapFall;
T16Nx->CON1.CAPIS0 = TIM_CapInitStruct->TIM_CapIS0;
T16Nx->CON1.CAPIS1 = TIM_CapInitStruct->TIM_CapIS1;
T16Nx->CON1.CAPT = TIM_CapInitStruct->TIM_CapTime;
}
void T32Nx_CapInit(T32N_TypeDef* T32Nx,TIM_CapInitStruType* TIM_CapInitStruct)
{
T32Nx->CON1.CAPPE = TIM_CapInitStruct->TIM_CapRise;
T32Nx->CON1.CAPNE = TIM_CapInitStruct->TIM_CapFall;
T32Nx->CON1.CAPIS0 = TIM_CapInitStruct->TIM_CapIS0;
T32Nx->CON1.CAPIS1 = TIM_CapInitStruct->TIM_CapIS1;
T32Nx->CON1.CAPT = TIM_CapInitStruct->TIM_CapTime;
}
void T16Nx_MAT0ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type)
{
T16Nx->CON0.MAT0S = Type;
}
void T16Nx_MAT1ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type)
{
T16Nx->CON0.MAT1S = Type;
}
void T16Nx_MAT2ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type)
{
T16Nx->CON0.MAT2S = Type;
}
void T16Nx_MAT3ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_MATCON Type)
{
T16Nx->CON0.MAT3S = Type;
}
void T32Nx_MAT0ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type)
{
T32Nx->CON0.MAT0S = Type;
}
void T32Nx_MAT1ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type)
{
T32Nx->CON0.MAT1S = Type;
}
void T32Nx_MAT2ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type)
{
T32Nx->CON0.MAT2S = Type;
}
void T32Nx_MAT3ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_MATCON Type)
{
T32Nx->CON0.MAT3S = Type;
}
void T16Nx_MAT0Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type)
{
T16Nx->CON2.MOM0 = Type;
}
void T16Nx_MAT1Out0Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type)
{
T16Nx->CON2.MOM1 = Type;
}
void T16Nx_MAT2Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type)
{
T16Nx->CON2.MOM2 = Type;
}
void T16Nx_MAT3Out1Config(T16N_TypeDef* T16Nx,TIM_TYPE_MATOUT Type)
{
T16Nx->CON2.MOM3 = Type;
}
void T32Nx_MAT0Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type)
{
T32Nx->CON2.MOM0 = Type;
}
void T32Nx_MAT1Out0Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type)
{
T32Nx->CON2.MOM1 = Type;
}
void T32Nx_MAT2Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type)
{
T32Nx->CON2.MOM2 = Type;
}
void T32Nx_MAT3Out1Config(T32N_TypeDef* T32Nx,TIM_TYPE_MATOUT Type)
{
T32Nx->CON2.MOM3 = Type;
}
void T16Nx_ITConfig(T16N_TypeDef* T16Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState)
{
if (NewState != DISABLE)
T16Nx->IE.Word |= (uint32_t)Type;
else
T16Nx->IE.Word &= (~(uint32_t)Type);
}
void T32Nx_ITConfig(T32N_TypeDef* T32Nx,TIM_TYPE_IT Type,TYPE_FUNCEN NewState)
{
if (NewState != DISABLE)
T32Nx->IE.Word|= (uint32_t)Type;
else
T32Nx->IE.Word &= (~(uint32_t)Type);
}
void T16Nx_PWMOutConfig(T16N_TypeDef* T16Nx,T16Nx_PWMInitStruType* T16Nx_PWMInitStruct)
{
T16Nx->CON2.MOE0 = T16Nx_PWMInitStruct->T16Nx_MOE0;
T16Nx->CON2.MOE1 = T16Nx_PWMInitStruct->T16Nx_MOE1;
T16Nx->CON2.POL0 = T16Nx_PWMInitStruct->T16Nx_POL0;
T16Nx->CON2.POL1 = T16Nx_PWMInitStruct->T16Nx_POL1;
}
void T16Nx_PWMBK_Config(T16N_TypeDef* T16Nx,T16Nx_PWMBK_Type* type)
{
T16Nx->CON2.PBKL0 = type->T16Nx_PWMBKL0;
T16Nx->CON2.PBKL1 = type->T16Nx_PWMBKL1;
T16Nx->CON2.PBKS = type->T16Nx_PWMBKS;
T16Nx->CON2.PBKPS = type->T16Nx_PWMBKPS;
T16Nx->CON2.PBKEN = type->T16Nx_PWMBKEN;
}
void T16Nx_TRG_Config(T16N_TypeDef* T16Nx,T16Nx_PWMTRG_type Type,TYPE_FUNCEN NewState)
{
if(Type == T16Nx_MAT0)
T16Nx->TRG.MAT0TAR = 1;
else if(Type == T16Nx_MAT1)
T16Nx->TRG.MAT1TAR = 1;
else if(Type == T16Nx_MAT2)
T16Nx->TRG.MAT2TAR = 1;
else if(Type == T16Nx_MAT3)
T16Nx->TRG.MAT3TAR = 1;
T16Nx->TRG.OVTAR = NewState;
}
FlagStatus T16Nx_GetPWMBKF(T16N_TypeDef* T16Nx)
{
if(T16Nx->CON2.PBKF == 1)
return SET;
else
return RESET;
}
void T16Nx_ResetPWMBKF(T16N_TypeDef* T16Nx)
{
T16Nx->CON2.PBKF = 1;
}
void T16Nx_SetCNT(T16N_TypeDef* T16Nx,uint16_t Value)
{
T16Nx->CNT.CNT = Value;
}
void T32Nx_SetCNT(T32N_TypeDef* T32Nx,uint32_t Value)
{
T32Nx->CNT.CNT = Value;
}
void T16Nx_SetPRECNT(T16N_TypeDef* T16Nx,uint8_t Value)
{
T16Nx->PRECNT.PRECNT = Value;
}
void T32Nx_SetPRECNT(T32N_TypeDef* T32Nx,uint8_t Value)
{
T32Nx->PRECNT.PRECNT = Value;
}
void T16Nx_SetPREMAT(T16N_TypeDef* T16Nx,uint8_t Value)
{
T16Nx->PREMAT.PREMAT = Value;
}
void T32Nx_SetPREMAT(T32N_TypeDef* T32Nx,uint8_t Value)
{
T32Nx->PREMAT.PREMAT = Value;
}
void T16Nx_SetMAT0(T16N_TypeDef* T16Nx,uint16_t Value)
{
T16Nx->MAT0.MAT0 = Value;
}
void T16Nx_SetMAT1(T16N_TypeDef* T16Nx,uint16_t Value)
{
T16Nx->MAT1.MAT1 = Value;
}
void T16Nx_SetMAT2(T16N_TypeDef* T16Nx,uint16_t Value)
{
T16Nx->MAT2.MAT2 = Value;
}
void T16Nx_SetMAT3(T16N_TypeDef* T16Nx,uint16_t Value)
{
T16Nx->MAT3.MAT3 = Value;
}
void T32Nx_SetMAT0(T32N_TypeDef* T32Nx,uint32_t Value)
{
T32Nx->MAT0.MAT0 = Value;
}
void T32Nx_SetMAT1(T32N_TypeDef* T32Nx,uint32_t Value)
{
T32Nx->MAT1.MAT1 = Value;
}
void T32Nx_SetMAT2(T32N_TypeDef* T32Nx,uint32_t Value)
{
T32Nx->MAT2.MAT2 = Value;
}
void T32Nx_SetMAT3(T32N_TypeDef* T32Nx,uint32_t Value)
{
T32Nx->MAT3.MAT3 = Value;
}
uint16_t T16Nx_GetMAT0(T16N_TypeDef* T16Nx)
{
return (T16Nx->MAT0.MAT0);
}
uint16_t T16Nx_GetMAT1(T16N_TypeDef* T16Nx)
{
return (T16Nx->MAT1.MAT1);
}
uint16_t T16Nx_GetMAT2(T16N_TypeDef* T16Nx)
{
return (T16Nx->MAT2.MAT2);
}
uint16_t T16Nx_GetMAT3(T16N_TypeDef* T16Nx)
{
return (T16Nx->MAT3.MAT3);
}
uint32_t T32Nx_GetMAT0(T32N_TypeDef* T32Nx)
{
return (T32Nx->MAT0.MAT0);
}
uint32_t T32Nx_GetMAT1(T32N_TypeDef* T32Nx)
{
return (T32Nx->MAT1.MAT1);
}
uint32_t T32Nx_GetMAT2(T32N_TypeDef* T32Nx)
{
return (T32Nx->MAT2.MAT2);
}
uint32_t T32Nx_GetMAT3(T32N_TypeDef* T32Nx)
{
return (T32Nx->MAT3.MAT3);
}
uint16_t T16Nx_GetCNT(T16N_TypeDef* T16Nx)
{
return (T16Nx->CNT.CNT);
}
uint32_t T32Nx_GetCNT(T32N_TypeDef* T32Nx)
{
return (T32Nx->CNT.CNT);
}
uint8_t T16Nx_GetPRECNT(T16N_TypeDef* T16Nx)
{
return (uint8_t)(T16Nx->PRECNT.PRECNT);
}
uint8_t T32Nx_GetPRECNT(T32N_TypeDef* T32Nx)
{
return (uint8_t)(T32Nx->PRECNT.PRECNT);
}
FlagStatus T16Nx_GetFlagStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag)
{
FlagStatus bitstatus = RESET;
if((T16Nx->IF.Word & (uint32_t)TIM_Flag) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
FlagStatus T32Nx_GetFlagStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag)
{
FlagStatus bitstatus = RESET;
if((T32Nx->IF.Word & (uint32_t)TIM_Flag) != (uint32_t)RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
ITStatus T16Nx_GetITStatus(T16N_TypeDef* T16Nx,TIM_TYPE_IT TIM_Flag)
{
ITStatus bitstatus = RESET;
uint32_t itstatus = 0x0, itenable = 0x0;
itstatus = T16Nx->IF.Word & (uint32_t)TIM_Flag;
itenable = T16Nx->IE.Word & (uint32_t)TIM_Flag;
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
ITStatus T32Nx_GetITStatus(T32N_TypeDef* T32Nx,TIM_TYPE_IT TIM_Flag)
{
ITStatus bitstatus = RESET;
uint32_t itstatus = 0x0, itenable = 0x0;
itstatus = T32Nx->IF.Word & (uint32_t)TIM_Flag;
itenable = T32Nx->IE.Word & (uint32_t)TIM_Flag;
if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
void T16Nx_ClearIFPendingBit(T16N_TypeDef* T16Nx,TIM_TYPE_IF TIM_Flag)
{
T16Nx->IF.Word = (uint32_t)TIM_Flag;
}
void T32Nx_ClearIFPendingBit(T32N_TypeDef* T32Nx,TIM_TYPE_IF TIM_Flag)
{
T32Nx->IF.Word = (uint32_t)TIM_Flag;
}
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#include "lib_uart.h"
void UART_Init(UART_TypeDef* UARTx,UART_InitStruType* UART_InitStruct)
{
uint32_t BaudClockTemp = 0, BaudTemp = 0;
if(UART_InitStruct->UART_ClockSet == UART_Clock_1)
{
BaudClockTemp = (SystemCoreClock/16)%UART_InitStruct->UART_BaudRate;
if(UART_InitStruct->UART_BaudRate >= (2*BaudClockTemp))
{
BaudTemp = (SystemCoreClock/16/UART_InitStruct->UART_BaudRate)-1;
}
else
{
BaudTemp = SystemCoreClock/16/UART_InitStruct->UART_BaudRate;
}
}
else if(UART_InitStruct->UART_ClockSet == UART_Clock_2)
{
BaudClockTemp = (SystemCoreClock/32)%UART_InitStruct->UART_BaudRate;
if(UART_InitStruct->UART_BaudRate >= (2*BaudClockTemp))
{
BaudTemp = (SystemCoreClock/32/UART_InitStruct->UART_BaudRate)-1;
}
else
{
BaudTemp = SystemCoreClock/32/UART_InitStruct->UART_BaudRate;
}
}
else if(UART_InitStruct->UART_ClockSet == UART_Clock_4)
{
BaudClockTemp = (SystemCoreClock/64)%UART_InitStruct->UART_BaudRate;
if(UART_InitStruct->UART_BaudRate >= (2*BaudClockTemp))
{
BaudTemp = (SystemCoreClock/64/UART_InitStruct->UART_BaudRate)-1;
}
else
{
BaudTemp = SystemCoreClock/64/UART_InitStruct->UART_BaudRate;
}
}
if(BaudTemp > 2046)
{
BaudTemp = 2047;
}
UARTx->CON.BCS = UART_InitStruct->UART_ClockSet;
UARTx->BRR.BRR = BaudTemp ;
UARTx->CON.TXFS = UART_InitStruct->UART_StopBits;
UARTx->CON.TXMOD = UART_InitStruct->UART_TxMode;
UARTx->CON.TXP = UART_InitStruct->UART_TxPolar;
UARTx->CON.RXMOD = UART_InitStruct->UART_RxMode;
UARTx->CON.RXP = UART_InitStruct->UART_RxPolar;
}
void UART_ITConfig(UART_TypeDef* UARTx,UART_TYPE_IT UART_IT,TYPE_FUNCEN NewState)
{
if (NewState != DISABLE)
UARTx->IE.Word = (UARTx->IE.Word & (uint32_t)0x0000FFFF) | (uint32_t) UART_IT;
else
UARTx->IE.Word = (UARTx->IE.Word & (uint32_t)0x0000FFFF) & (~((uint32_t) UART_IT));
}
void UART_TBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type)
{
UARTx->IE.TBIM = Type;
}
void UART_RBIMConfig(UART_TypeDef* UARTx,UART_TYPE_TRBIM Type)
{
UARTx->IE.RBIM = Type;
}
void UART_SendByte(UART_TypeDef* UARTx,uint8_t Temp08)
{
UARTx->TBW.Byte[0] = Temp08;
}
void UART_SendHalfWord(UART_TypeDef* UARTx,uint16_t Temp16)
{
UARTx->TBW.HalfWord[0] = Temp16;
}
void UART_SendWord(UART_TypeDef* UARTx,uint32_t Temp32)
{
UARTx->TBW.Word = Temp32;
}
uint8_t UART_RecByte(UART_TypeDef* UARTx)
{
return UARTx->RBR.Byte[0];
}
uint16_t UART_RecHalfWord(UART_TypeDef* UARTx)
{
return UARTx->RBR.HalfWord[0];
}
uint32_t UART_RecWord(UART_TypeDef* UARTx)
{
return UARTx->RBR.Word;
}
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx,UART_TYPE_FLAG UART_Flag)
{
FlagStatus bitstatus = RESET;
if ((UARTx->IF.Word & ((uint32_t)UART_Flag)) != RESET)
bitstatus = SET;
else
bitstatus = RESET;
return bitstatus;
}
ITStatus UART_GetITStatus(UART_TypeDef* UARTx,UART_TYPE_IT UART_IT)
{
FlagStatus bitstatus = RESET;
if((UARTx->IE.Word & ((uint32_t)UART_IT)) == 0)
bitstatus = RESET;
else
bitstatus = SET;
return bitstatus;
}
void UART_ClearIFPendingBit(UART_TypeDef* UARTx,UART_CLR_IF UART_Flag)
{
UARTx->IF.Word = (uint32_t)UART_Flag;
}
/*************************END OF FILE**********************/

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/***************************************************************
*Copyright (C), 2017, Shanghai Eastsoft Microelectronics Co., Ltd
***************************************************************/
#include "lib_wdt.h"
void IWDT_Init(IWDT_InitStruType *WDT_InitStruct)
{
uint32_t tmp;
if (WDT_InitStruct->WDT_Clock != WDT_CLOCK_PCLK)
tmp = (uint32_t)(32 * WDT_InitStruct->WDT_Tms);
else
tmp = SystemCoreClock / 1000 * WDT_InitStruct->WDT_Tms;
IWDT->LOAD.LOAD = tmp;
IWDT->CON.CLKS = WDT_InitStruct->WDT_Clock;
IWDT->CON.IE = WDT_InitStruct->WDT_IE;
IWDT->CON.RSTEN = WDT_InitStruct->WDT_Rst;
return;
}
void IWDT_SetReloadValue(uint32_t Value)
{
IWDT->LOAD.LOAD = Value;
return;
}
uint32_t IWDT_GetValue(void)
{
return (uint32_t)IWDT->VALUE.VALUE;
}
FlagStatus IWDT_GetFlagStatus(void)
{
FlagStatus bitstatus = RESET;
if (IWDT->RIS.WDTIF != RESET)
bitstatus = SET;
return bitstatus;
}
FlagStatus IWDT_GetITStatus(void)
{
FlagStatus bitstatus = RESET;
if (IWDT->CON.IE != RESET)
bitstatus = SET;
return bitstatus;
}
void WWDT_Init(WWDT_InitStruType *WDT_InitStruct)
{
uint32_t tmp;
if (WDT_InitStruct->WDT_Clock != WDT_CLOCK_PCLK)
tmp = (uint32_t)(32 * WDT_InitStruct->WDT_Tms);
else
tmp = SystemCoreClock / 1000 * WDT_InitStruct->WDT_Tms;
WWDT->LOAD.LOAD = tmp;
WWDT->CON.CLKS = WDT_InitStruct->WDT_Clock;
WWDT->CON.IE = WDT_InitStruct->WDT_IE;
WWDT->CON.RSTEN = WDT_InitStruct->WDT_Rst;
WWDT->CON.WWDTWIN = WDT_InitStruct->WDT_Win;
return;
}
void WWDT_SetReloadValue(uint32_t Value)
{
WWDT->LOAD.LOAD = Value;
return;
}
uint32_t WWDT_GetValue(void)
{
return (uint32_t)WWDT->VALUE.VALUE;
}
FlagStatus WWDT_GetFlagStatus(void)
{
FlagStatus bitstatus = RESET;
if (WWDT->RIS.WWDTIF != RESET)
bitstatus = SET;
return bitstatus;
}
FlagStatus WWDT_GetITStatus(void)
{
FlagStatus bitstatus = RESET;
if (WWDT->CON.IE != RESET)
bitstatus = SET;
return bitstatus;
}
/*************************END OF FILE**********************/