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rel_1.6.0 init

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guocheng.kgc 2020-06-18 20:06:52 +08:00 • committed by shengdong.dsd
commit 27b3e2883d
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62
Living_SDK/kernel/pwrmgmt/include/cpu_pwr_hal_lib.h Executable file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
#ifndef CPU_PWR_HAL_H
#define CPU_PWR_HAL_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <k_err.h>
#include "pwrmgmt_state.h"
#define CPU_PWR_NODE_NAME_LEN 64
#define CPU_STATE_BIT(n) (1 << (n))
#define CPU_FREQ_UNKNOW (-1)
#define CPU_VOLT_UNKNOW (-1)
#define CPU_LATENCY_UNKNOW (-1)
typedef struct {
uint32_t state;
uint32_t value;
} state_val_pair_t;
struct cpu_pwr;
typedef pwr_status_t (*cpu_pstate_set_t)(struct cpu_pwr *p_cpu_node, uint32_t cpu_state);
typedef pwr_status_t (*cpu_cstate_set_t)(uint32_t cpu_state, int master);
typedef pwr_status_t (*cpu_cstate_get_t)(struct cpu_pwr *p_cpu_node, uint32_t *pCpuState);
typedef struct cpu_pwr {
uint32_t support_bitset_c;
int cstate_nums;
state_val_pair_t *p_pair_latency;
unsigned int cstate_updating;
cpu_cstate_t current_c_state;
cpu_cstate_t desire_c_state;
cpu_cstate_set_t cpu_cstate_set_func;
char * name;
uint32_t unit;
} cpu_pwr_t;
extern void cpu_pwr_hal_lib_init(void);
extern pwr_status_t cpu_pwr_node_init_static(char *, uint32_t, cpu_pwr_t *);
extern pwr_status_t cpu_pwr_node_init_dyn(char *, uint32_t, cpu_pwr_t **);
extern cpu_pwr_t * cpu_pwr_node_find_by_name(char *pName, uint32_t index);
extern pwr_status_t cpu_pwr_node_record(cpu_pwr_t *p_cpu_node, uint32_t cpuIndex);
extern pwr_status_t cpu_pwr_c_state_capability_set(uint32_t cpuIndex, uint32_t supportBitsetC);
extern pwr_status_t cpu_pwr_c_state_latency_save(uint32_t cpuIndex, cpu_cstate_t cpu_state,
uint32_t latency);
extern uint32_t cpu_pwr_c_state_latency_get(uint32_t cpuIndex, cpu_cstate_t CState);
extern pwr_status_t cpu_pwr_c_method_set(uint32_t cpu_idx, cpu_cstate_set_t cpu_cstate_set_func);
#ifdef __cplusplus
}
#endif
#endif /* CPU_PWR_HAL_H */

33
Living_SDK/kernel/pwrmgmt/include/cpu_pwr_lib.h Executable file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
#ifndef CPU_PWR_LIB_H
#define CPU_PWR_LIB_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <k_api.h>
#include "pwrmgmt_state.h"
#ifndef container_of
#define container_of(ptr, type, member) \
((type *)((char *)(ptr) - offsetof(type, member)))
#endif /* container_of */
int cpu_pwrmgmt_init(void);
void cpu_pwr_down(void);
void cpu_pwr_up(void);
extern void (*_func_cpu_tickless_up)(void);
extern void (*_func_cpu_tickless_down)(void);
#ifdef __cplusplus
}
#endif
#endif /* CPU_PWR_LIB_H */

37
Living_SDK/kernel/pwrmgmt/include/cpu_tickless.h Executable file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
#ifndef CPU_TICKLSEE_H
#define CPU_TICKLSEE_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <k_api.h>
#include "pwrmgmt_state.h"
typedef pwr_status_t (*one_shot_init_t)(void);
typedef uint32_t (*one_shot_seconds_max_t)(void);
typedef pwr_status_t (*one_shot_start_t)(uint64_t planUse);
typedef pwr_status_t (*one_shot_stop_t)(uint64_t *pPassedUs);
typedef struct {
one_shot_init_t one_shot_init;
one_shot_seconds_max_t one_shot_seconds_max;
one_shot_start_t one_shot_start;
one_shot_stop_t one_shot_stop;
} one_shot_timer_t;
extern pwr_status_t tickless_init(void);
extern void tickless_c_states_add(uint32_t c_state_set);
extern void tickless_one_shot_timer_save(cpu_cstate_t c_state, one_shot_timer_t *p_timer);
#ifdef __cplusplus
}
#endif
#endif /* CPU_TICKLSEE_H */

68
Living_SDK/kernel/pwrmgmt/include/pwrmgmt_api.h Executable file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
DESCRIPTION
This file provides APIs for management CPU power.
*/
#ifndef PWRMGMT_API_H
#define PWRMGMT_API_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <k_api.h>
#include "pwrmgmt_default_config.h"
#include "cpu_pwr_lib.h"
#include "cpu_pwr_hal_lib.h"
#include "pwrmgmt_state.h"
/*
* CPU power management operates in one of three possible modes:
*
* CPU_IDLE_MODE_RUN:
* In this CPU mode of operation, idle CPU power management is disabled.
*
* CPU_IDLE_MODE_SLEEP:
* the CPUs sleep when idle, but system clock interupts wakes up the CPU
* at every tick.
*
* CPU_IDLE_MODE_TICKLESS: CPUs sleep when idle, potentially for multiple
* ticks once enter idle mode.
*/
typedef enum cpu_idle_mode {
CPU_IDLE_MODE_RUN = 0,
CPU_IDLE_MODE_SLEEP = 1,
CPU_IDLE_MODE_TICKLESS = 2
} CPU_IDLE_MODE;
extern pwr_status_t cpu_pwr_c_state_set(cpu_cstate_t target_c_state);
extern pwr_status_t cpu_pwr_c_state_get(uint32_t cpu_idx, cpu_cstate_t *p_cstate);
extern pwr_status_t cpu_pwr_c_state_capability_get(uint32_t cpu_idx, uint32_t *p_support_bitset_c);
extern pwr_status_t cpu_pwr_idle_mode_set(CPU_IDLE_MODE mode);
extern CPU_IDLE_MODE cpu_pwr_idle_mode_get(void);
int pwrmgmt_suspend_lowpower();
int pwrmgmt_resume_lowpower();
#if (PWRMGMT_CONFIG_SHOW > 0)
extern void cpu_pwr_state_show(void);
extern void cpu_pwr_info_show(void);
#endif /* PWRMGMT_CONFIG_SHOW */
#if (WIFI_CONFIG_SUPPORT_LOWPOWER > 0)
extern int wifi_enter_powersave();
extern int wifi_exit_powersave();
#endif
#ifdef __cplusplus
}
#endif
#endif /* PWRMGMT_API_H */

42
Living_SDK/kernel/pwrmgmt/include/pwrmgmt_debug.h Executable file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
#ifndef PWRMGMT_DEBUG_H
#define PWRMGMT_DEBUG_H
#ifdef __cplusplus
extern "C"
{
#endif
#include <stdio.h>
#include <stdarg.h>
#include "pwrmgmt_default_config.h"
/*
* when use debug, do not close uart when turn into pwr down state
*/
#define PWR_DEBUG_LEVEL DBG_INFO
typedef enum {
DBG_OFF = 0x00000000,
DBG_INFO = 0x00000001,
DBG_WARN = 0x00000002,
DBG_ERR = 0x00000003,
} pwr_debug_level_t;
void pwr_debug(pwr_debug_level_t debug_level, const char *fmt_str, ...);
#if (PWRMGMT_CONFIG_DEBUG > 0)
#define PWR_DBG pwr_debug
#else
#define PWR_DBG(lvl, ...)
#endif /* PWRMGMT_CONFIG_DEBUG > DBG_OFF */
#ifdef __cplusplus
}
#endif
#endif /* PWRMGMT_DEBUG_H */

31
Living_SDK/kernel/pwrmgmt/include/pwrmgmt_default_config.h Executable file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
#ifndef PWRMGMT_DEFAULT_CONFIG_H
#define PWRMGMT_DEFAULT_CONFIG_H
#ifdef __cplusplus
extern "C"
{
#endif
#include "pwrmgmt_api.h"
#ifndef PWRMGMT_CONFIG_SHOW
#define PWRMGMT_CONFIG_SHOW 0
#endif
#ifndef PWRMGMT_CONFIG_DEBUG
#define PWRMGMT_CONFIG_DEBUG 0
#endif
#ifndef PWRMGMT_CONFIG_LOG_ENTERSLEEP
#define PWRMGMT_CONFIG_LOG_ENTERSLEEP 0
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* PWRMGMT_DEFAULT_CONFIG_H */

111
Living_SDK/kernel/pwrmgmt/include/pwrmgmt_state.h Executable file
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/*
* Copyright (C) 2018 Alibaba Group Holding Limited
*/
/*
DESCRIPTION
This file provides base type define power state.
*/
#ifndef PWRMGMT_STATE_H
#define PWRMGMT_STATE_H
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
typedef enum {
PWR_ERR = (-1),
PWR_OK = (0)
} pwr_status_t;
/* CPU states */
typedef enum {
CPU_CSTATE_C0 = 0, /* Operating */
CPU_CSTATE_C1 = 1, /* Halt -- not executing put powered on */
CPU_CSTATE_C2 = 2, /* not execuing with lower power than C1 */
CPU_CSTATE_C3 = 3, /* not execuing with lower power than C2 */
CPU_CSTATE_C4 = 4, /* not execuing with lower power than C3 */
CPU_CSTATE_C5 = 5,
CPU_CSTATE_C6 = 6,
CPU_CSTATE_C7 = 7,
CPU_CSTATE_C8 = 8,
CPU_CSTATE_C9 = 9,
CPU_CSTATE_C10 = 10,
CPU_CSTATE_C11 = 11,
CPU_CSTATE_C12 = 12,
CPU_CSTATE_C13 = 13,
CPU_CSTATE_C14 = 14,
CPU_CSTATE_C15 = 15,
CPU_CSTATE_C16 = 16,
CPU_CSTATE_C17 = 17,
CPU_CSTATE_C18 = 18,
CPU_CSTATE_C19 = 19,
CPU_CSTATE_C20 = 20,
CPU_CSTATE_C21 = 21,
CPU_CSTATE_C22 = 22,
CPU_CSTATE_C23 = 23,
CPU_CSTATE_C24 = 24,
CPU_CSTATE_C25 = 25,
CPU_CSTATE_C26 = 26,
CPU_CSTATE_C27 = 27,
CPU_CSTATE_C28 = 28,
CPU_CSTATE_C29 = 29,
CPU_CSTATE_C30 = 30,
CPU_CSTATE_C31 = 31,
CPU_CSTATE_MAX = 31,
CPU_CSTATE_NONE = 0xFF
} cpu_cstate_t;
/* Performance states */
typedef enum {
CPU_PSTATE_P0 = 0, /* Max power and clock */
CPU_PSTATE_P1 = 1,
CPU_PSTATE_P2 = 2,
CPU_PSTATE_P3 = 3,
CPU_PSTATE_P4 = 4,
CPU_PSTATE_P5 = 5,
CPU_PSTATE_P6 = 6,
CPU_PSTATE_P7 = 7,
CPU_PSTATE_P8 = 8,
CPU_PSTATE_P9 = 9,
CPU_PSTATE_P10 = 10,
CPU_PSTATE_P11 = 11,
CPU_PSTATE_P12 = 12,
CPU_PSTATE_P13 = 13,
CPU_PSTATE_P14 = 14,
CPU_PSTATE_P15 = 15,
CPU_PSTATE_P16 = 16,
CPU_PSTATE_P17 = 17,
CPU_PSTATE_P18 = 18,
CPU_PSTATE_P19 = 19,
CPU_PSTATE_P20 = 20,
CPU_PSTATE_P21 = 21,
CPU_PSTATE_P22 = 22,
CPU_PSTATE_P23 = 23,
CPU_PSTATE_P24 = 24,
CPU_PSTATE_P25 = 25,
CPU_PSTATE_P26 = 26,
CPU_PSTATE_P27 = 27,
CPU_PSTATE_P28 = 28,
CPU_PSTATE_P29 = 29,
CPU_PSTATE_P30 = 30,
CPU_PSTATE_P31 = 31,
CPU_PSTATE_MAX = 32,
CPU_PSTATE_NONE = 0xFF
} cpu_pstate_t;
#ifdef __cplusplus
}
#endif
#endif /* PWRMGMT_STATE_H */